title: Abraham in Islam

text: All these events and more have been discussed with more details in Muslim tradition, and especially in the "Stories of the Prophets" and works of universal Islamic theology. Certain episodes from the life of Abraham have been more heavily detailed in Islamic text, such as the arguments between Abraham and the evil king, Nimrod, the near-sacrifice of his son, and the story of Hagar and Ishmael, which Muslims commemorate when performing pilgrimage in Mecca. An important Islamic religious holiday, Eid al-Adha, commemorates Abraham's willingness to sacrifice his son Ishmael as an act of obedience to God, before God intervened to provide him with a sheep to sacrifice instead. In some cases, some believe these legends in Islamic text may have influenced later Jewish tradition.


title: Isaiah

text: Isaiah ( or ; , "Yəšaʿyāhū", "God is Salvation") was the 8th-century BC Israelite prophet after whom the Book of Isaiah is named.


title: Isaiah

text: Within the text of the Book of Isaiah, Isaiah himself is referred to as "the prophet", but the exact relationship between the Book of Isaiah and the actual prophet Isaiah is complicated. The traditional view is that all 66 chapters of the book of Isaiah were written by one man, Isaiah, possibly in two periods between 740 BC and c. 686 BC, separated by approximately 15 years, and that the book includes dramatic prophetic declarations of Cyrus the Great in the Bible, acting to restore the nation of Israel from Babylonian captivity. Another widely held view is that parts of the first half of the book (chapters 1–39) originated with the historical prophet, interspersed with prose commentaries written in the time of King Josiah a hundred years later, and that the remainder of the book dates from immediately before and immediately after the end of the exile in Babylon, almost two centuries after the time of the historical prophet, and perhaps these later chapters represent the work of an ongoing school of prophets who prophesied in accordance with his prophecies.


title: Isaiah

text: The first verse of the Book of Isaiah states that Isaiah prophesied during the reigns of Uzziah (or Azariah), Jotham, Ahaz, and Hezekiah, the kings of Judah. Uzziah's reign was 52 years in the middle of the 8th century BC, and Isaiah must have begun his ministry a few years before Uzziah's death, probably in the 740s BC. He may have been contemporary for some years with Manasseh. Thus, Isaiah may have prophesied for as long as 64 years.


title: Isaiah

text: According to some modern interpretations, Isaiah's wife was called "the prophetess", either because she was endowed with the prophetic gift, like Deborah and Huldah, or simply because she was the "wife of the prophet". They had two sons, naming the elder Shear-jashub, meaning "A remnant shall return", and the younger Maher-Shalal-Hash-Baz, meaning, "Quickly to spoils, plunder speedily."


title: Isaiah

text: Soon after this, Shalmaneser V determined to subdue the kingdom of Israel, taking over and destroying Samaria (722 BC). So long as Ahaz reigned, the kingdom of Judah was untouched by the Assyrian power. But when Hezekiah gained the throne, he was encouraged to rebel "against the king of Assyria", and entered into an alliance with the king of Egypt. The king of Assyria threatened the king of Judah, and at length invaded the land. Sennacherib (701 BC) led a powerful army into Judah. Hezekiah was reduced to despair, and submitted to the Assyrians. But after a brief interval, war broke out again. Again Sennacherib led an army into Judah, one detachment of which threatened Jerusalem Isaiah on that occasion encouraged Hezekiah to resist the Assyrians, whereupon Sennacherib sent a threatening letter to Hezekiah, which he "spread before the LORD".


title: Isaiah

text: According to the account in 2 Kings 19 (and its derivative account in 2 Chronicles 32) an angel of God fell on the Assyrian army and 185,000 of its men were killed in one night. "Like Xerxes in Greece, Sennacherib never recovered from the shock of the disaster in Judah. He made no more expeditions against either Southern Palestine or Egypt."


title: Isaiah

text: The remaining years of Hezekiah's reign were peaceful. Isaiah probably lived to its close, and possibly into the reign of Manasseh. The time and manner of his death are not specified in either the Bible or other primary sources. Later Jewish tradition says that he suffered martyrdom by being sawn in two under the orders of Manasseh.


title: Isaiah

text: The book of Isaiah, along with the book of Jeremiah, is distinctive in the Hebrew bible for its direct portrayal of the "wrath of the Lord" as presented, for example, in Isaiah 9:19 stating, "Through the wrath of the Lord of hosts is the land darkened, and the people shall be as the fuel of the fire."


title: Isaiah

text: The Ascension of Isaiah, a pseudepigraphical Christian text dated to sometime between the end of the 1st century and the beginning of the 3rd, gives a detailed story of Isaiah confronting an evil false prophet and ending with Isaiah being martyred – none of which is attested in the original Biblical account.


title: Isaiah

text: Gregory of Nyssa (c. 335–395) believed that the Prophet Isaiah "knew more perfectly than all others the mystery of the religion of the Gospel". Jerome (c. 342–420) also lauds the Prophet Isaiah, saying, "He was more of an Evangelist than a Prophet, because he described all of the Mysteries of the Church of Christ so vividly that you would assume he was not prophesying about the future, but rather was composing a history of past events." Of specific note are the songs of the Suffering Servant, which Christians say are a direct prophetic revelation of the nature, purpose, and detail of the death of Jesus Christ.


title: Isaiah

text: The Book of Isaiah is quoted many times by New Testament writers. Ten of those references are about the Suffering Servant, how he will suffer and die to save many from their sins, be buried in a rich man's tomb, and be a light to the Gentiles. The Gospel of John says that Isaiah "saw Jesus' glory and spoke about him."


title: Isaiah

text: The Eastern Orthodox Church celebrates Saint Isaiah the Prophet with Saint Christopher on May 9. Isaiah is also listed on the page of saints for May 9 in the Roman martyrology of the Roman Catholic Church.


title: Isaiah

text: The Book of Mormon quotes Jesus Christ as stating that "great are the words of Isaiah", and that all things prophesied by Isaiah have been and will be fulfilled. The Book of Mormon and Doctrine and Covenants also quote Isaiah more than any other prophet from the Old Testament. Additionally, members of the Church of Jesus Christ of Latter-day Saints consider the founding of the church by Joseph Smith in the 19th century to be a fulfillment of Isaiah 11, the translation of the Book of Mormon to be a fulfillment of Isaiah 29, and the building of Latter-day Saint temples as a fulfillment of Isaiah 2:2.


title: Isaiah

text: Isaiah () is not mentioned by name in the Quran or the Hadith, but appears frequently as a prophet in Islamic sources, such as Qisas Al-Anbiya and Tafsir. Tabari (310/923) provides the typical accounts for Islamic traditions regarding Isaiah. He is further mentioned and accepted as a prophet by other Islamic scholars such as Ibn Kathir, Al-Tha`labi and Kisa'i and also modern scholars such as Muhammad Asad and Abdullah Yusuf Ali. According to Muslim scholars, Isaiah prophesied the coming of Jesus and Muhammad, although the reference to Muhammad is disputed by other religious scholars. Isaiah's narrative in Islamic literature can be divided into three sections. The first establishes Isaiah as a prophet of Israel during the reign of Hezekiah; the second relates Isaiah's actions during the siege of Jerusalem by Sennacherib; and the third warns the nation of coming doom.


title: Isaiah

text: Paralleling the Hebrew Bible, Islamic tradition states that Hezekiah was king in Jerusalem during Isaiah's time. Hezekiah heard and obeyed Isaiah's advice, but could not quell the turbulence in Israel. This tradition maintains that Hezekiah was a righteous man and that the turbulence worsened after him. After the death of the king, Isaiah told the people not to forsake God, and warned Israel to cease from its persistent sin and disobedience. Muslim tradition maintains that the unrighteous of Israel in their anger sought to kill Isaiah. In a death that resembles that attributed to Isaiah in "Lives of the Prophets", Muslim exegesis recounts that Isaiah was martyred by Israelites by being sawn in two.


title: Isaiah

text: In the courts of Al-Ma'mun, the seventh Abbasid caliph, Ali al-Ridha, the great-grandson of Muhammad and prominent scholar (Imam) of his era, was questioned by the High Jewish Rabbi to prove through the Torah that both Jesus and Muhammad were prophets. Among his several proofs, the Imam references the Book of Isaiah, stating "Sha‘ya (Isaiah), the Prophet, said in the Torah concerning what you and your companions say: ‘I have seen two riders to whom (He) illuminated earth. One of them was on a donkey and the other was on a camel. Who is the rider of the donkey, and who is the rider of the camel?'" The Rabbi was unable to answer with certainty. Al-Ridha goes on to state that "As for the rider of the donkey, he is ‘Isa (Jesus); and as for the rider of the camel, he is Muhammad, may Allah bless him and his family. Do you deny that this (statement) is in the Torah?" The Rabbi responds "No, I do not deny it."


title: Isaiah

text: Allusions in Jewish rabbinic literature to Isaiah contain various expansions, elaborations and inferences that go beyond what is presented in the text of the Bible itself.


title: Isaiah

text: According to the ancient rabbis, Isaiah was a descendant of Judah and Tamar, and his father Amoz was the brother of King Amaziah.


title: Isaiah

text: While Isaiah, says the Midrash, was walking up and down in his study he heard God saying, "Whom shall I send?" Then Isaiah said, "Here am I; send me!" Thereupon God said to him," My children are troublesome and sensitive; if you are ready to be insulted and even beaten by them, you may accept My message; if not, you would better renounce it". Isaiah accepted the mission, and was the most forbearing, as well as the most patriotic, among the prophets, always defending Israel and imploring forgiveness for its sins. When Isaiah said, "I dwell in the midst of a people of unclean lips", he was rebuked by God for speaking in such terms of His people.


title: Isaiah

text: It is related in the Talmud that Rabbi Simeon ben Azzai found in Jerusalem an account wherein it was written that King Manasseh killed Isaiah. King Manasseh said to Isaiah, "Moses, your master, said, 'No man may see God and live'; but you have said, 'I saw the Lord seated upon his throne'"; and went on to point out other contradictions—as between Deuteronomy and Isaiah 40; between Exodus 33 and 2 Kings Isaiah thought: "I know that he will not accept my explanations; why should I increase his guilt?" He then uttered the tetragrammaton, a cedar-tree opened, and Isaiah disappeared within it. King Manasseh ordered the cedar to be sawn asunder, and when the saw reached his mouth Isaiah died; thus was he punished for having said, "I dwell in the midst of a people of unclean lips".


title: Isaiah

text: A somewhat different version of this legend is given in the Jerusalem Talmud. According to that version Isaiah, fearing King Manasseh, hid himself in a cedar-tree, but his presence was betrayed by the fringes of his garment, and King Manasseh caused the tree to be sawn in half. A passage of the Targum to Isaiah quoted by Jolowicz states that when Isaiah fled from his pursuers and took refuge in the tree, and the tree was sawn in half, the prophet's blood spurted forth. The legend of Isaiah's martyrdom spread to the Arabs and to the Christians as, for example, Athanasius the bishop of Alexandria ( 318) wrote, "Isaiah was sawn asunder".


title: Isaiah

text: In February 2018, archaeologist Eilat Mazar announced that she and her team had discovered a small seal impression which reads "[belonging] to Isaiah nvy" (could be reconstructed and read as "[belonging] to Isaiah the prophet") during the Ophel excavations, just south of the Temple Mount in Jerusalem. The tiny bulla was found "only 10 feet away" from where an intact bulla bearing the inscription "[belonging] to King Hezekiah of Judah" was discovered in 2015 by the same team. Although the name "Isaiah" in the Paleo-Hebrew alphabet is unmistakable, the damage on the bottom left part of the seal causes difficulties in confirming the word "prophet" or a name "Navi", casting some doubts whether this seal really belongs to the prophet Isaiah.


title: Harry's House

text: Harry's House is the third studio album by English singer and songwriter Harry Styles, released on 20 May 2022 by Columbia Records and Erskine. The album was largely written and recorded during 2020 and 2021 and has been noted as Styles' most introspective work. Musically, it is inspired by city pop and features pop-funk, pop rock, synth-pop and R&B styles.


title: Harry's House

text: Despite reportedly being leaked a month before its release, "Harry's House" debuted with the best first-week sales in Styles' career. It debuted at number one on the UK Albums Chart with 113,000 album-equivalent units, becoming the fastest-selling album of 2022 in the country. It also debuted at number one on the US "Billboard" 200 with 521,500 album-equivalent units, including 330,000 album sales, making it the largest opening week of 2022 in the United States. It debuted at number one in various other countries, including Australia, Belgium, Canada, France, Germany, Ireland, Italy, the Netherlands, New Zealand, Spain, Sweden and Switzerland.


title: Harry's House

text: "Harrys House" was met with critical acclaim. It was supported by the singles "As It Was", "Late Night Talking", and "Music for a Sushi Restaurant"; the first of which debuted atop the UK and US charts, becoming Styles' second solo number-one song in both countries. Besides the chart-topper "As It Was", three other songs were concurrently in the top 10 of the US "Billboard" Hot 100: "Late Night Talking", "Music for a Sushi Restaurant" and "Matilda", making Styles the first British solo artist to achieve this feat. The album was nominated for the 2022 Mercury Music Prize.


title: Harry's House

text: In an interview with Apple Music, Styles explained how he came up with the album title: "The album is named after Haruomi Hosono, he had an album in the '70s called , and I spent that chunk in Japan; I heard that record and I was like 'I love that.[...] It'd be really fun to make a record called "Harry's House"'." The initial idea behind the album came when Styles wanted to take the title in a literal way so he could make an acoustic extended play recorded at his own house. The album is considered Styles's most introspective of his career thus fair; according to Styles the central concept of 'house' is a metaphor for the inside of his mind rather than a "geographical location". Speaking on the album's concept, Styles said "It was much more of an internal thing… [and] it felt like it took on this whole new meaning and it was about, like: imagine, it’s a day in my house, what do I go through? A day in my mind, what do I go through? In my house I’m playing fun music, sad music, I’m playing this, I’m playing that. It’s a day in the life."


title: Harry's House

text: The album was largely written and recorded during 2020 and 2021. "Boyfriends", however, was initially written during the final week of "Fine Line" (2019) recording. The first song to be written for the album was "Late Night Talking", which was written the day Styles, the band and the producers arrived at Shangri-La studios in Malibu. "Matilda" is titled after the lead character from a book of the same name, written by Roald Dahl. The song was inspired by a relationship Styles had with someone who was going through difficulty. In an interview with Zane Lowe, Style's stated he wrote the song to show he was listening: "Sometimes it's just about listening. I hope that's what I did here. If nothing else, it just says, 'I was listening to you'". The album features John Mayer on lead guitar on "Cinema" and "Daydreaming".


title: Harry's House

text: "Boyfriends" lyrically discusses the experience of romantic relationships in which "people don't treat each other very nicely sometimes" that Styles observed in his sister and friends when dating other people as well as his own experiences with dating. "Cinema" was Styles's "fun" track which he started writing while being on the treadmill and continued writing piecewise. "Love of My Life" is Styles's way of showing his love and appreciation to England and home.


title: Harry's House

text: Musically, "Harrys House" takes influence from Japan's city pop genre and also features pop-funk, pop rock, synth-pop and R&B. Jon Dolan of "Rolling Stone" described the album's musical sound as "bright", especially the productions use of synths and horns over synth-pop and R&B songs.


title: Harry's House

text: Styles announced the title of his upcoming third studio album as "Harry's House" on 23 March 2022, unveiling its artwork, a 40-second trailer and the album's release date of 20 May 2022. In the trailer, Styles steps on the podium of a theatre and grins while a "house façade" rises near him and reversed synthesisers play in the background; the audio would later be revealed to be a backwards version of the album's closing track, "Love of My Life". Joni Mitchell, whose 1975 album "The Hissing of Summer Lawns" featured a track called "Harry's House / Centerpiece", tweeted that she "love[d] the title". Upon announcing the album, Styles set up an interactive website and a new Twitter account. The messages published included "you are home" and "in this world, it's just us, you know it's not the same as it was". The album was released on 20 May 2022 through Erskine and Columbia.


title: Harry's House

text: On 15 April 2022, during his Coachella headlining performance, Styles performed "As It Was" live for the first time, in addition to two then-unreleased songs from the album, "Boyfriends" and "Late Night Talking".


title: Harry's House

text: One month before the album's release, "Harry's House" was reportedly leaked on Twitter in its entirety. Sony, owner of Columbia Records, publicly condemned the leak in a tweet.


title: Harry's House

text: On 26 May 2022, in a segment on "The Late Late Show with James Corden", Styles and James Corden filmed a music video for the song "Daylight" directed by the latter, in which they visit an apartment belonging to some fans. Both the music video and segment were released on the show's YouTube channel on 28 May 2022.


title: Harry's House

text: "As It Was" was released as the lead single of "Harry's House" on 1 April 2022, having been previously announced on 28 March 2022. "As It Was" debuted atop the UK and US charts, becoming his second solo number one single in both countries, and reached the top of Australian and Canadian charts.


title: Harry's House

text: "Late Night Talking" was released to US pop radio on 21 June 2022, as the album's second single. It reached the top five on American, Australian, British, and Canadian charts.


title: Harry's House

text: "Music for a Sushi Restaurant" was released to adult contemporary radio on 3 October 2022, as the album's third single. It peaked in the top ten on American, Australian, British, and Canadian charts prior to its release as a single.


title: Harry's House

text: "Harry's House" was met with critical acclaim. At Metacritic, which assigns a normalised rating out of 100 to reviews from professional publications, the album received an average score of 83 based on 26 reviews, indicating "universal acclaim"—Styles' highest rated album.


title: Harry's House

text: Alexis Petridis of "The Guardian" wrote that the album "ticks a lot of the right boxes and has abundant charm, which makes it a perfect reflection of the pop star who made it". Reviewing the album for "DIY", Emma Swann felt that while Styles alternately spends time "exploring vivid lyrical micro-vignettes" and then "obfuscating" the narrative on the album, he is "also not scared of being secondary to the song; a lesson it's taken many others far longer to learn". Neil Z. Yeung from AllMusic stated that ""Harry's House" is what happens when Styles steps out of the spotlight to live his life. And despite the fact that there's nothing as immortal as 'Watermelon Sugar' to be found, this album, as a whole, has solid bones and is sturdy enough to last."


title: Harry's House

text: Two hours after the album was released on Apple Music, "Harry's House" earned the most first-day streams for a pop album released in 2022. In the United Kingdom, the album debuted at number one on the UK Albums chart with 113,000 album-equivalent units, becoming Styles' second number-one album and the fastest-selling album of 2022 so far.


title: Harry's House

text: In the United States, "Harry's House" debuted at number one on the "Billboard" 200 chart with 521,500 units, consisting of 330,000 pure sales and 189,000 streaming units (from the 246.96 million on-demand streams of the album's tracks). It became Styles' third US number-one album, his biggest debut in the country, and the second-largest opening week for an album in 2022, behind Taylor Swift's "Midnights". Additionally, it set a modern-era record for single-week vinyl album sales in the US, selling 182,000 copies, and marked the second-largest week for an album on vinyl since Luminate began tracking music sales in 1991. "Harry's House" notched a second consecutive week at number one, with 160,500 units sold, becoming his second album to spend multiple weeks atop the charts after 2019's "Fine Line" and the first album to spend its first two weeks at number one since Adele's "30" spent its first six weeks at number one from late 2021 through early 2022. With the entire tracklist charting within the top 15 of the ARIA Charts, the album set a new record in Australia.


title: Harry's House

text: Besides the chart-topper "As It Was", three other songs reached the top 10 of the US "Billboard" Hot 100: "Late Night Talking" (at number four), "Music for a Sushi Restaurant" (at number eight) and "Matilda" (at number nine). With four concurrent top-ten hits on the chart, this made Styles the first British solo artist to achieve this, and among all British acts he joins the Beatles, who achieved the feat in 1964.


title: Tsundere

text: The word is derived from the terms ('to turn away in disgust or anger') and ('to become affectionate'). Originally found in Japanese bishōjo games, the word is now part of the otaku moe phenomenon, reaching into other media. The term was made popular in the visual novel "Kimi ga Nozomu Eien".


title: Tsundere

text: Manga author Ken Akamatsu lists "tsundere" as one of the special cases in his definition of "moe": "The person feeling it must be stronger: The object of 'moe' is weak and dependent (like a child) on the person, or is in a situation where she cannot oppose (like a maid)... (*Tsundere only: There will be times where the stronger and weaker role is reversed)." The concept has received increasing attention in Japan, with a maid cafe named Nagomi in Akihabara started having "tsundere" events in 2006 and "tsundere"-themed products released (like Tomy Co.'s portable television set), and the concept increasingly reflected in recent anime, from an extended discussion of the meaning of the concept and its origin on the Internet in "Lucky Star" Lucky Channel segment classifying the characters according to "tsundere"-ness. Another accepted definition of "tsundere" is someone who has a combative attitude towards others but is also kind on the inside. They usually play out as having an attitude toward the main character, either a male or a female, and often criticizing them in one way or another, until they eventually warm up to them or fall in love with them as the series progresses, though they usually find it very hard to admit it or outright deny it in some cases.


title: Tsundere

text: Comiket organizer Koichi Ichikawa has described Lum from "Urusei Yatsura" as being both the source of "moe" and the first "tsundere"; figurine sculptor Bome has also cited Lum as an inspiration for his designs. Manga critic Jason Thompson named Madoka Ayukawa of the 1980s series "Kimagure Orange Road" as the root of the tsundere archetype. Other anime and manga featuring "tsundere" include "Love Hina", "Neon Genesis Evangelion", and "Bakemonogatari", among many others. Some voice actors have garnered a reputation for voicing "tsundere" characters such as Rie Kugimiya who voices Louise in "The Familiar of Zero" and Nagi in "Hayate the Combat Butler". In "Excel Saga" volume 15, author Rikdo Koshi defines "tsundere" as "hard on the outside, soft on the inside" and associates it with character Misaki Matsuya.


title: Tsundere

text: "Tsundere" as a concept is not strictly limited to women, and is not strictly limited to manga or anime. The character from the series "" is portrayed as being "tsundere", and is paired with a "lovable loser", . "Tsundere" role-play has become a common theme in maid cafés.


title: X86

text: x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the Intel 8086 microprocessor and its 8088 variant. The 8086 was introduced in 1978 as a fully 16-bit extension of Intel's 8-bit 8080 microprocessor, with memory segmentation as a solution for addressing more memory than can be covered by a plain 16-bit address. The term "x86" came into being because the names of several successors to Intel's 8086 processor end in "86", including the 80186, 80286, 80386 and 80486 processors.


title: X86

text: The term is not synonymous with IBM PC compatibility, as this implies a multitude of other computer hardware. Embedded systems and general-purpose computers used x86 chips before the PC-compatible market started, some of them before the IBM PC (1981) debut.


title: X86

text: , most desktop and laptop computers sold are based on the x86 architecture family, while mobile categories such as smartphones or tablets are dominated by ARM. At the high end, x86 continues to dominate computation-intensive workstation and cloud computing segments. The fastest supercomputer in the TOP500 list for June 2022 was the first exascale system, Frontier, built using AMD Epyc CPUs based on the x86 ISA; it broke the 1 exaFLOPS barrier in May 2022.


title: X86

text: In the 1980s and early 1990s, when the 8088 and 80286 were still in common use, the term x86 usually represented any 8086-compatible CPU. Today, however, x86 usually implies a binary compatibility also with the 32-bit instruction set of the 80386. This is due to the fact that this instruction set has become something of a lowest common denominator for many modern operating systems and probably also because the term became common "after" the introduction of the 80386 in 1985.


title: X86

text: A few years after the introduction of the 8086 and 8088, Intel added some complexity to its naming scheme and terminology as the "iAPX" of the ambitious but ill-fated Intel iAPX 432 processor was tried on the more successful 8086 family of chips, applied as a kind of system-level prefix. An 8086 "system", including coprocessors such as 8087 and 8089, and simpler Intel-specific system chips, was thereby described as an iAPX 86 "system". There were also terms "iRMX" (for operating systems), "iSBC" (for single-board computers), and "iSBX" (for multimodule boards based on the 8086-architecture), all together under the heading "Microsystem 80". However, this naming scheme was quite temporary, lasting for a few years during the early 1980s.


title: X86

text: Although the 8086 was primarily developed for embedded systems and small multi-user or single-user computers, largely as a response to the successful 8080-compatible Zilog Z80, the x86 line soon grew in features and processing power. Today, x86 is ubiquitous in both stationary and portable personal computers, and is also used in midrange computers, workstations, servers, and most new supercomputer clusters of the TOP500 list. A large amount of software, including a large list of are using x86-based hardware.


title: X86

text: Modern x86 is relatively uncommon in embedded systems, however, and small low power applications (using tiny batteries), and low-cost microprocessor markets, such as home appliances and toys, lack significant x86 presence. Simple 8- and 16-bit based architectures are common here, as well as simpler RISC architectures like RISC-V, although the x86-compatible VIA C7, VIA Nano, AMD's Geode, Athlon Neo and Intel Atom are examples of 32- and 64-bit designs used in some "relatively" low-power and low-cost segments.


title: X86

text: There have been several attempts, including by Intel, to end the market dominance of the "inelegant" x86 architecture designed directly from the first simple 8-bit microprocessors. Examples of this are the iAPX 432 (a project originally named the "Intel 8800"), the Intel 960, Intel 860 and the Intel/Hewlett-Packard Itanium architecture. However, the continuous refinement of x86 microarchitectures, circuitry and semiconductor manufacturing would make it hard to replace x86 in many segments. AMD's 64-bit extension of x86 (which Intel eventually responded to with a compatible design) and the scalability of x86 chips in the form of modern multi-core CPUs, is underlining x86 as an example of how continuous refinement of established industry standards can resist the competition from completely new architectures.


title: X86

text: The table below lists processor models and model series implementing various architectures in the x86 family, in chronological order. Each line item is characterized by significantly improved or commercially successful processor microarchitecture designs.


title: X86

text: At various times, companies such as IBM, VIA, NEC, AMD, TI, STM, Fujitsu, OKI, Siemens, Cyrix, Intersil, C&T, NexGen, UMC, and DM&P started to design or manufacture x86 processors (CPUs) intended for personal computers and embedded systems. Other companies that designed or manufactured x86 or x87 processors include ITT Corporation, National Semiconductor, ULSI System Technology, and Weitek.


title: X86

text: Such x86 implementations were seldom simple copies but often employed different internal microarchitectures and different solutions at the electronic and physical levels. Quite naturally, early compatible microprocessors were 16-bit, while 32-bit designs were developed much later. For the personal computer market, real quantities started to appear around 1990 with i386 and i486 compatible processors, often named similarly to Intel's original chips.


title: X86

text: After the fully pipelined i486, in 1993 Intel introduced the Pentium brand name (which, unlike numbers, could be trademarked) for their new set of superscalar x86 designs. With the x86 naming scheme now legally cleared, other x86 vendors had to choose different names for their x86-compatible products, and initially some chose to continue with variations of the numbering scheme: IBM partnered with Cyrix to produce the 5x86 and then the very efficient 6x86 (M1) and 6x86MX (MII) lines of Cyrix designs, which were the first x86 microprocessors implementing register renaming to enable speculative execution.


title: X86

text: AMD meanwhile designed and manufactured the advanced but delayed 5k86 (K5), which, "internally", was closely based on AMD's earlier 29K RISC design; similar to NexGen's Nx586, it used a strategy such that dedicated pipeline stages decode x86 instructions into uniform and easily handled micro-operations, a method that has remained the basis for most x86 designs to this day.


title: X86

text: Some early versions of these microprocessors had heat dissipation problems. The 6x86 was also affected by a few minor compatibility problems, the Nx586 lacked a floating-point unit (FPU) and (the then crucial) pin-compatibility, while the K5 had somewhat disappointing performance when it was (eventually) introduced.


title: X86

text: Customer ignorance of alternatives to the Pentium series further contributed to these designs being comparatively unsuccessful, despite the fact that the K5 had very good Pentium compatibility and the 6x86 was significantly faster than the Pentium on integer code. AMD later managed to grow into a serious contender with the K6 set of processors, which gave way to the very successful Athlon and Opteron.


title: X86

text: There were also other contenders, such as Centaur Technology (formerly IDT), Rise Technology, and Transmeta. VIA Technologies' energy efficient C3 and C7 processors, which were designed by the Centaur company, were sold for many years following their release in 2005. Centaur's 2008 design, the VIA Nano, was their first processor with superscalar and speculative execution. It was introduced at about the same time (in 2008) as Intel introduced the Intel Atom, its first "in-order" processor after the P5 Pentium.


title: X86

text: Many additions and extensions have been added to the original x86 instruction set over the years, almost consistently with full backward compatibility. The architecture family has been implemented in processors from Intel, Cyrix, AMD, VIA Technologies and many other companies; there are also open implementations, such as the Zet SoC platform (currently inactive). Nevertheless, of those, only Intel, AMD, VIA Technologies, and DM&P Electronics hold x86 architectural licenses, and from these, only the first two actively produce modern 64-bit designs, leading to what has been called a "duopoly" of Intel and AMD in x86 processors.


title: X86

text: However, in 2014 the Shanghai-based Chinese company Zhaoxin, a joint venture between a Chinese company and VIA Technologies, began designing VIA based x86 processors for desktops and laptops. The release of its newest "7" family of x86 processors (e.g. KX-7000), which are not quite as fast as AMD or Intel chips but are still state of the art, had been planned for 2021; as of March 2022 the release had not taken place, however.


title: X86

text: The instruction set architecture has twice been extended to a larger word size. In 1985, Intel released the 32-bit 80386 (later known as i386) which gradually replaced the earlier 16-bit chips in computers (although typically not in embedded systems) during the following years; this extended programming model was originally referred to as "the i386 architecture" (like its first implementation) but Intel later dubbed it IA-32 when introducing its (unrelated) IA-64 architecture.


title: X86

text: In 1999–2003, AMD extended this 32-bit architecture to 64 bits and referred to it as x86-64 in early documents and later as AMD64. Intel soon adopted AMD's architectural extensions under the name IA-32e, later using the name EM64T and finally using Intel 64. Microsoft and Sun Microsystems/Oracle also use term "x64", while many Linux distributions, and the BSDs also use the "amd64" term. Microsoft Windows, for example, designates its 32-bit versions as "x86" and 64-bit versions as "x64", while installation files of 64-bit Windows versions are required to be placed into a directory called "AMD64".


title: X86

text: The x86 architecture is a variable instruction length, primarily "CISC" design with emphasis on backward compatibility. The instruction set is not typical CISC, however, but basically an extended version of the simple eight-bit 8008 and 8080 architectures. Byte-addressing is enabled and words are stored in memory with little-endian byte order. Memory access to unaligned addresses is allowed for almost all instructions. The largest native size for integer "arithmetic" and memory addresses (or offsets) is 16, 32 or 64 bits depending on architecture generation (newer processors include direct support for smaller integers as well). Multiple scalar values can be handled simultaneously via the SIMD unit present in later generations, as described below. Immediate addressing offsets and immediate data may be expressed as 8-bit quantities for the frequently occurring cases or contexts where a -128..127 range is enough. Typical instructions are therefore 2 or 3 bytes in length (although some are much longer, and some are single-byte).


title: X86

text: To further conserve encoding space, most registers are expressed in opcodes using three or four bits, the latter via an opcode prefix in 64-bit mode, while at most one operand to an instruction can be a memory location. However, this memory operand may also be the "destination" (or a combined source "and" destination), while the other operand, the "source", can be either "register" or "immediate". Among other factors, this contributes to a code size that rivals eight-bit machines and enables efficient use of instruction cache memory. The relatively small number of general registers (also inherited from its 8-bit ancestors) has made register-relative addressing (using small immediate offsets) an important method of accessing operands, especially on the stack. Much work has therefore been invested in making such accesses as fast as register accesses—i.e., a one cycle instruction throughput, in most circumstances where the accessed data is available in the top-level cache.


title: X86

text: A dedicated floating-point processor with 80-bit internal registers, the 8087, was developed for the original 8086. This microprocessor subsequently developed into the extended 80387, and later processors incorporated a backward compatible version of this functionality on the same microprocessor as the main processor. In addition to this, modern x86 designs also contain a SIMD-unit (see SSE below) where instructions can work in parallel on (one or two) 128-bit words, each containing two or four floating-point numbers (each 64 or 32 bits wide respectively), or alternatively, 2, 4, 8 or 16 integers (each 64, 32, 16 or 8 bits wide respectively).


title: X86

text: The presence of wide SIMD registers means that existing x86 processors can load or store up to 128 bits of memory data in a single instruction and also perform bitwise operations (although not integer arithmetic) on full 128-bits quantities in parallel. Intel's Sandy Bridge processors added the Advanced Vector Extensions (AVX) instructions, widening the SIMD registers to 256 bits. The Intel Initial Many Core Instructions implemented by the Knights Corner Xeon Phi processors, and the AVX-512 instructions implemented by the Knights Landing Xeon Phi processors and by Skylake-X processors, use 512-bit wide SIMD registers.


title: X86

text: During execution, current x86 processors employ a few extra decoding steps to split most instructions into smaller pieces called micro-operations. These are then handed to a control unit that buffers and schedules them in compliance with x86-semantics so that they can be executed, partly in parallel, by one of several (more or less specialized) execution units. These modern x86 designs are thus pipelined, superscalar, and also capable of out of order and speculative execution (via branch prediction, register renaming, and memory dependence prediction), which means they may execute multiple (partial or complete) x86 instructions simultaneously, and not necessarily in the same order as given in the instruction stream.


title: X86

text: Some Intel CPUs (Xeon Foster MP, some Pentium 4, and some Nehalem and later Intel Core processors) and AMD CPUs (starting from Zen) are also capable of simultaneous multithreading with two threads per core (Xeon Phi has four threads per core). Some Intel CPUs support transactional memory (TSX).


title: X86

text: When introduced, in the mid-1990s, this method was sometimes referred to as a "RISC core" or as "RISC translation", partly for marketing reasons, but also because these micro-operations share some properties with certain types of RISC instructions. However, "traditional" microcode (used since the 1950s) also inherently shares many of the same properties; the new method differs mainly in that the translation to micro-operations now occurs asynchronously. Not having to synchronize the execution units with the decode steps opens up possibilities for more analysis of the (buffered) code stream, and therefore permits detection of operations that can be performed in parallel, simultaneously feeding more than one execution unit.


title: X86

text: The latest processors also do the opposite when appropriate; they combine certain x86 sequences (such as a compare followed by a conditional jump) into a more complex micro-op which fits the execution model better and thus can be executed faster or with fewer machine resources involved.


title: X86

text: Another way to try to improve performance is to cache the decoded micro-operations, so the processor can directly access the decoded micro-operations from a special cache, instead of decoding them again. Intel followed this approach with the Execution Trace Cache feature in their NetBurst microarchitecture (for Pentium 4 processors) and later in the Decoded Stream Buffer (for Core-branded processors since Sandy Bridge).


title: X86

text: Transmeta used a completely different method in their Crusoe x86 compatible CPUs. They used just-in-time translation to convert x86 instructions to the CPU's native VLIW instruction set. Transmeta argued that their approach allows for more power efficient designs since the CPU can forgo the complicated decode step of more traditional x86 implementations.


title: X86

text: Instruction relative addressing in 64-bit code (RIP + displacement, where RIP is the instruction pointer register) simplifies the implementation of position-independent code (as used in shared libraries in some operating systems).


title: X86

text: The 8086 had of eight-bit (or alternatively ) I/O space, and a (one segment) stack in memory supported by computer hardware. Only words (two bytes) can be pushed to the stack. The stack grows toward numerically lower addresses, with pointing to the most recently pushed item. There are 256 interrupts, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the return address.


title: X86

text: The original Intel 8086 and 8088 have fourteen 16-bit registers. Four of them (AX, BX, CX, DX) are general-purpose registers (GPRs), although each may have an additional purpose; for example, only CX can be used as a counter with the "loop" instruction. Each can be accessed as two separate bytes (thus BX's high byte can be accessed as BH and low byte as BL). Two pointer registers have special roles: SP (stack pointer) points to the "top" of the stack, and BP (base pointer) is often used to point at some other place in the stack, typically above the local variables (see frame pointer). The registers SI, DI, BX and BP are address registers, and may also be used for array indexing.


title: X86

text: Four segment registers (CS, DS, SS and ES) are used to form a memory address. The FLAGS register contains flags such as carry flag, overflow flag and zero flag. Finally, the instruction pointer (IP) points to the next instruction that will be fetched from memory and then executed; this register cannot be directly accessed (read or written) by a program.


title: X86

text: The Intel 80186 and 80188 are essentially an upgraded 8086 or 8088 CPU, respectively, with on-chip peripherals added, and they have the same CPU registers as the 8086 and 8088 (in addition to interface registers for the peripherals).


title: X86

text: The 8086, 8088, 80186, and 80188 can use an optional floating-point coprocessor, the 8087. The 8087 appears to the programmer as part of the CPU and adds eight 80-bit wide registers, st(0) to st(7), each of which can hold numeric data in one of seven formats: 32-, 64-, or 80-bit floating point, 16-, 32-, or 64-bit (binary) integer, and 80-bit packed decimal integer. It also has its own 16-bit status register accessible through the instruction, and it is common to simply use some of its bits for branching by copying it "into" the normal FLAGS.


title: X86

text: In the Intel 80286, to support protected mode, three special registers hold descriptor table addresses (GDTR, LDTR, IDTR), and a fourth task register (TR) is used for task switching. The 80287 is the floating-point coprocessor for the 80286 and has the same registers as the 8087 with the same data formats.


title: X86

text: With the advent of the 32-bit 80386 processor, the 16-bit general-purpose registers, base registers, index registers, instruction pointer, and FLAGS register, but not the segment registers, were expanded to 32 bits. The nomenclature represented this by prefixing an "E" (for "extended") to the register names in x86 assembly language. Thus, the AX register corresponds to the lower 16 bits of the new 32-bit EAX register, SI corresponds to the lower 16 bits of ESI, and so on. The general-purpose registers, base registers, and index registers can all be used as the base in addressing modes, and all of those registers except for the stack pointer can be used as the index in addressing modes.


title: X86

text: Two new segment registers (FS and GS) were added. With a greater number of registers, instructions and operands, the machine code format was expanded. To provide backward compatibility, segments with executable code can be marked as containing either 16-bit or 32-bit instructions. Special prefixes allow inclusion of 32-bit instructions in a 16-bit segment or "vice versa".


title: X86

text: The 80386 had an optional floating-point coprocessor, the 80387; it had eight 80-bit wide registers: st(0) to st(7), like the 8087 and 80287. The 80386 could also use an 80287 coprocessor. With the 80486 and all subsequent x86 models, the floating-point processing unit (FPU) is integrated on-chip.


title: X86

text: The Pentium MMX added eight 64-bit MMX integer vector registers (MM0 to MM7, which share lower bits with the 80-bit-wide FPU stack). With the Pentium III, Intel added a 32-bit Streaming SIMD Extensions (SSE) control/status register (MXCSR) and eight 128-bit SSE floating-point registers (XMM0 to XMM7).


title: X86

text: Starting with the AMD Opteron processor, the x86 architecture extended the 32-bit registers into 64-bit registers in a way similar to how the 16 to 32-bit extension took place. An R-prefix (for "register") identifies the 64-bit registers (RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, RFLAGS, RIP), and eight additional 64-bit general registers (R8–R15) were also introduced in the creation of x86-64. Also, eight more SSE vector registers (XMM8–XMM15) were added. However, these extensions are only usable in 64-bit mode, which is one of the two modes only available in long mode. The addressing modes were not dramatically changed from 32-bit mode, except that addressing was extended to 64 bits, virtual addresses are now sign extended to 64 bits (in order to disallow mode bits in virtual addresses), and other selector details were dramatically reduced. In addition, an addressing mode was added to allow memory references relative to RIP (the instruction pointer), to ease the implementation of position-independent code, used in shared libraries in some operating systems.


title: X86

text: SIMD registers YMM0–YMM15 (YMM0–YMM31 when AVX-512 is supported). Lower half of each of the YMM registers maps onto the corresponding XMM register.


title: X86

text: SIMD registers ZMM0–ZMM31. Lower half of each of the ZMM registers maps onto the corresponding YMM register.


title: X86

text: x86 processors that have a protected mode, i.e. the 80286 and later processors, also have three descriptor registers (GDTR, LDTR, IDTR) and a task register (TR).


title: X86

text: 32-bit x86 processors (starting with the 80386) also include various special/miscellaneous registers such as control registers (CR0 through 4, CR8 for 64-bit only), debug registers (DR0 through 3, plus 6 and 7), test registers (TR3 through 7; 80486 only), and model-specific registers (MSRs, appearing with the Pentium).


title: X86

text: AVX-512 has eight extra 64-bit mask registers K0–K7 for selecting elements in a vector register. Depending on the vector register and element widths, only a subset of bits of the mask register may be used by a given instruction.


title: X86

text: Although the main registers (with the exception of the instruction pointer) are "general-purpose" in the 32-bit and 64-bit versions of the instruction set and can be used for anything, it was originally envisioned that they be used for the following purposes:


title: X86

text: Some instructions compile and execute more efficiently when using these registers for their designed purpose. For example, using AL as an accumulator and adding an immediate byte value to it produces the efficient "add to AL" opcode of 04h, whilst using the BL register produces the generic and longer "add to register" opcode of 80C3h. Another example is double precision division and multiplication that works specifically with the AX and DX registers.


title: X86

text: Modern compilers benefited from the introduction of the "sib" byte ("scale-index-base byte") that allows registers to be treated uniformly (minicomputer-like). However, using the sib byte universally is non-optimal, as it produces longer encodings than only using it selectively when necessary. (The main benefit of the sib byte is the orthogonality and more powerful addressing modes it provides, which make it possible to save instructions and the use of registers for address calculations such as scaling an index.) Some special instructions lost priority in the hardware design and became slower than equivalent small code sequences. A notable example is the LODSW instruction.


title: X86

text: Real Address mode, commonly called Real mode, is an operating mode of 8086 and later x86-compatible CPUs. Real mode is characterized by a 20-bit segmented memory address space (meaning that only slightly more than 1 MiB of memory can be addressed), direct software access to peripheral hardware, and no concept of memory protection or multitasking at the hardware level. All x86 CPUs in the 80286 series and later start up in real mode at power-on; 80186 CPUs and earlier had only one operational mode, which is equivalent to real mode in later chips. (On the IBM PC platform, direct software access to the IBM BIOS routines is available only in real mode, since BIOS is written for real mode. However, this is not a property of the x86 CPU but of the IBM BIOS design.)


title: X86

text: In order to use more than 64 KB of memory, the segment registers must be used. This created great complications for compiler implementors who introduced odd pointer modes such as "near", "far" and "huge" to leverage the implicit nature of segmented architecture to different degrees, with some pointers containing 16-bit offsets within implied segments and other pointers containing segment addresses and offsets within segments. It is technically possible to use up to 256 KB of memory for code and data, with up to 64 KB for code, by setting all four segment registers once and then only using 16-bit offsets (optionally with default-segment override prefixes) to address memory, but this puts substantial restrictions on the way data can be addressed and memory operands can be combined, and it violates the architectural intent of the Intel designers, which is for separate data items (e.g. arrays, structures, code units) to be contained in separate segments and addressed by their own segment addresses, in new programs that are not ported from earlier 8-bit processors with 16-bit address spaces.


title: X86

text: The System Management Mode (SMM) is only used by the system firmware (BIOS/UEFI), not by operating systems and applications software. The SMM code is running in SMRAM.


title: X86

text: In addition to real mode, the Intel 80286 supports protected mode, expanding addressable physical memory to 16 MB and addressable virtual memory to 1 GB, and providing protected memory, which prevents programs from corrupting one another. This is done by using the segment registers only for storing an index into a descriptor table that is stored in memory. There are two such tables, the Global Descriptor Table (GDT) and the Local Descriptor Table (LDT), each holding up to 8192 segment descriptors, each segment giving access to 64 KB of memory. In the 80286, a segment descriptor provides a 24-bit base address, and this base address is added to a 16-bit offset to create an absolute address. The base address from the table fulfills the same role that the literal value of the segment register fulfills in real mode; the segment registers have been converted from direct registers to indirect registers. Each segment can be assigned one of four ring levels used for hardware-based computer security. Each segment descriptor also contains a segment limit field which specifies the maximum offset that may be used with the segment. Because offsets are 16 bits, segments are still limited to 64 KB each in 80286 protected mode.


title: X86

text: Each time a segment register is loaded in protected mode, the 80286 must read a 6-byte segment descriptor from memory into a set of hidden internal registers. Thus, loading segment registers is much slower in protected mode than in real mode, and changing segments very frequently is to be avoided. Actual memory operations using protected mode segments are not slowed much because the 80286 and later have hardware to check the offset against the segment limit in parallel with instruction execution.


title: X86

text: The Intel 80386 extended offsets and also the segment limit field in each segment descriptor to 32 bits, enabling a segment to span the entire memory space. It also introduced support in protected mode for paging, a mechanism making it possible to use paged virtual memory (with 4 KB page size). Paging allows the CPU to map any page of the virtual memory space to any page of the physical memory space. To do this, it uses additional mapping tables in memory called page tables. Protected mode on the 80386 can operate with paging either enabled or disabled; the segmentation mechanism is always active and generates virtual addresses that are then mapped by the paging mechanism if it is enabled. The segmentation mechanism can also be effectively disabled by setting all segments to have a base address of 0 and size limit equal to the whole address space; this also requires a minimally-sized segment descriptor table of only four descriptors (since the FS and GS segments need not be used).


title: X86

text: Paging is used extensively by modern multitasking operating systems. Linux, 386BSD and Windows NT were developed for the 386 because it was the first Intel architecture CPU to support paging and 32-bit segment offsets. The 386 architecture became the basis of all further development in the x86 series.


title: X86

text: x86 processors that support protected mode boot into real mode for backward compatibility with the older 8086 class of processors. Upon power-on (a.k.a. booting), the processor initializes in real mode, and then begins executing instructions. Operating system boot code, which might be stored in read-only memory, may place the processor into the protected mode to enable paging and other features). do not apply in protected mode. Conversely, segment arithmetic, a common practice in real mode code, is not allowed in protected mode.


title: X86

text: There is also a sub-mode of operation in 32-bit protected mode (a.k.a. 80386 protected mode) called "virtual 8086 mode", also known as "V86 mode". This is basically a special hybrid operating mode that allows real mode programs and operating systems to run while under the control of a protected mode supervisor operating system. This allows for a great deal of flexibility in running both protected mode programs and real mode programs simultaneously. This mode is exclusively available for the 32-bit version of protected mode; it does not exist in the 16-bit version of protected mode, or in long mode.


title: X86

text: In the mid 1990s, it was obvious that the 32-bit address space of the x86 architecture was limiting its performance in applications requiring large data sets. A 32-bit address space would allow the processor to directly address only 4 GB of data, a size surpassed by applications such as video processing and database engines. Using 64-bit addresses, it is possible to directly address 16 EiB of data, although most 64-bit architectures do not support access to the full 64-bit address space; for example, AMD64 supports only 48 bits from a 64-bit address, split into four paging levels.


title: X86

text: In 1999, AMD published a (nearly) complete specification for a 64-bit extension of the x86 architecture which they called "x86-64" with claimed intentions to produce. That design is currently used in almost all x86 processors, with some exceptions intended for embedded systems.


title: X86

text: Mass-produced "x86-64" chips for the general market were available four years later, in 2003, after the time was spent for working prototypes to be tested and refined; about the same time, the initial name "x86-64" was changed to "AMD64". The success of the AMD64 line of processors coupled with lukewarm reception of the IA-64 architecture forced Intel to release its own implementation of the AMD64 instruction set. Intel had previously implemented support for AMD64 but opted not to enable it in hopes that AMD would not bring AMD64 to market before Itanium's new IA-64 instruction set was widely adopted. It branded its implementation of AMD64 as "EM64T", and later rebranded it "Intel 64".


title: X86

text: In its literature and product version names, Microsoft and Sun refer to AMD64/Intel 64 collectively as "x64" in the Windows and Solaris operating systems. Linux distributions refer to it either as "x86-64", its variant "x86_64", or "amd64". BSD systems use "amd64" while macOS uses "x86_64".


title: X86

text: Long mode is mostly an extension of the 32-bit instruction set, but unlike the 16–to–32-bit transition, many instructions were dropped in the 64-bit mode. This does not affect actual binary backward compatibility (which would execute legacy code in other modes that retain support for those instructions), but it changes the way assembler and compilers for new code have to work.


title: X86

text: This was the first time that a "major" extension of the x86 architecture was initiated and originated by a manufacturer other than Intel. It was also the first time that Intel accepted technology of this nature from an outside source.


title: X86

text: Early x86 processors could be extended with floating-point hardware in the form of a series of floating-point numerical co-processors with names like 8087, 80287 and 80387, abbreviated x87. This was also known as the NPX ("Numeric Processor eXtension"), an apt name since the coprocessors, while used mainly for floating-point calculations, also performed integer operations on both binary and decimal formats. With very few exceptions, the 80486 and subsequent x86 processors then integrated this x87 functionality on chip which made the x87 instructions a de facto integral part of the x86 instruction set.


title: X86

text: Each x87 register, known as ST(0) through ST(7), is 80 bits wide and stores numbers in the IEEE floating-point standard double extended precision format. These registers are organized as a stack with ST(0) as the top. This was done in order to conserve opcode space, and the registers are therefore randomly accessible only for either operand in a register-to-register instruction; ST0 must always be one of the two operands, either the source or the destination, regardless of whether the other operand is ST(x) or a memory operand. However, random access to the stack registers can be obtained through an instruction which exchanges any specified ST(x) with ST(0).


title: X86

text: The operations include arithmetic and transcendental functions, including trigonometric and exponential functions, and instructions that load common constants (such as 0; 1; e, the base of the natural logarithm; log2(10); and log10(2)) into one of the stack registers. While the integer ability is often overlooked, the x87 can operate on larger integers with a single instruction than the 8086, 80286, 80386, or any x86 CPU without to 64-bit extensions can, and repeated integer calculations even on small values (e.g., 16-bit) can be accelerated by executing integer instructions on the x86 CPU and the x87 in parallel. (The x86 CPU keeps running while the x87 coprocessor calculates, and the x87 sets a signal to the x86 when it is finished or interrupts the x86 if it needs attention because of an error.)


title: X86

text: MMX is a SIMD instruction set designed by Intel and introduced in 1997 for the Pentium MMX microprocessor. The MMX instruction set was developed from a similar concept first used on the Intel i860. It is supported on most subsequent IA-32 processors by Intel and other vendors. MMX is typically used for video processing (in multimedia applications, for instance).


title: X86

text: MMX added 8 new "registers" to the architecture, known as MM0 through MM7 (henceforth referred to as "MMn"). In reality, these new "registers" were just aliases for the existing x87 FPU stack registers. Hence, anything that was done to the floating-point stack would also affect the MMX registers. Unlike the FP stack, these MMn registers were fixed, not relative, and therefore they were randomly accessible. The instruction set did not adopt the stack-like semantics so that existing operating systems could still correctly save and restore the register state when multitasking without modifications.


title: X86

text: Each of the MMn registers are 64-bit integers. However, one of the main concepts of the MMX instruction set is the concept of "packed data types", which means instead of using the whole register for a single 64-bit integer (quadword), one may use it to contain two 32-bit integers (doubleword), four 16-bit integers (word) or eight 8-bit integers (byte). Given that the MMX's 64-bit MMn registers are aliased to the FPU stack and each of the floating-point registers are 80 bits wide, the upper 16 bits of the floating-point registers are unused in MMX. These bits are set to all ones by any MMX instruction, which correspond to the floating-point representation of NaNs or infinities.


title: X86

text: In 1997, AMD introduced 3DNow!. The introduction of this technology coincided with the rise of 3D entertainment applications and was designed to improve the CPU's vector processing performance of graphic-intensive applications. 3D video game developers and 3D graphics hardware vendors use 3DNow! to enhance their performance on AMD's K6 and Athlon series of processors.


title: X86

text: 3DNow! was designed to be the natural evolution of MMX from integers to floating point. As such, it uses exactly the same register naming convention as MMX, that is MM0 through MM7. The only difference is that instead of packing integers into these registers, two single-precision floating-point numbers are packed into each register. The advantage of aliasing the FPU registers is that the same instruction and data structures used to save the state of the FPU registers can also be used to save 3DNow! register states. Thus no special modifications are required to be made to operating systems which would otherwise not know about them.


title: X86

text: In 1999, Intel introduced the Streaming SIMD Extensions (SSE) instruction set, following in 2000 with SSE2. The first addition allowed offloading of basic floating-point operations from the x87 stack and the second made MMX almost obsolete and allowed the instructions to be realistically targeted by conventional compilers. Introduced in 2004 along with the "Prescott" revision of the Pentium 4 processor, SSE3 added specific memory and thread-handling instructions to boost the performance of Intel's HyperThreading technology. AMD licensed the SSE3 instruction set and implemented most of the SSE3 instructions for its revision E and later Athlon 64 processors. The Athlon 64 does not support HyperThreading and lacks those SSE3 instructions used only for HyperThreading.


title: X86

text: SSE discarded all legacy connections to the FPU stack. This also meant that this instruction set discarded all legacy connections to previous generations of SIMD instruction sets like MMX. But it freed the designers up, allowing them to use larger registers, not limited by the size of the FPU registers. The designers created eight 128-bit registers, named XMM0 through XMM7. ("Note": in AMD64, the number of SSE XMM registers has been increased from 8 to 16.) However, the downside was that operating systems had to have an awareness of this new set of instructions in order to be able to save their register states. So Intel created a slightly modified version of Protected mode, called Enhanced mode which enables the usage of SSE instructions, whereas they stay disabled in regular Protected mode. An OS that is aware of SSE will activate Enhanced mode, whereas an unaware OS will only enter into traditional Protected mode.


title: X86

text: SSE is a SIMD instruction set that works only on floating-point values, like 3DNow!. However, unlike 3DNow! it severs all legacy connection to the FPU stack. Because it has larger registers than 3DNow!, SSE can pack twice the number of single precision floats into its registers. The original SSE was limited to only single-precision numbers, like 3DNow!. The SSE2 introduced the capability to pack double precision numbers too, which 3DNow! had no possibility of doing since a double precision number is 64-bit in size which would be the full size of a single 3DNow! MMn register. At 128 bits, the SSE XMMn registers could pack two double precision floats into one register. Thus SSE2 is much more suitable for scientific calculations than either SSE1 or 3DNow!, which were limited to only single precision. SSE3 does not introduce any additional registers.


title: X86

text: The Advanced Vector Extensions (AVX) doubled the size of SSE registers to 256-bit YMM registers. It also introduced the VEX coding scheme to accommodate the larger registers, plus a few instructions to permute elements. AVX2 did not introduce extra registers, but was notable for the addition for masking, gather, and shuffle instructions.


title: X86

text: AVX-512 features yet another expansion to 32 512-bit ZMM registers and a new EVEX scheme. Unlike its predecessors featuring a monolithic extension, it is divided into many subsets that specific models of CPUs can choose to implement.


title: X86

text: Physical Address Extension or PAE was first added in the Intel Pentium Pro, and later by AMD in the Athlon processors, to allow up to 64 GB of RAM to be addressed. Without PAE, physical RAM in 32-bit protected mode is usually limited to 4 GB. PAE defines a different page table structure with wider page table entries and a third level of page table, allowing additional bits of physical address. Although the initial implementations on 32-bit processors theoretically supported up to 64 GB of RAM, chipset and other platform limitations often restricted what could actually be used. x86-64 processors define page table structures that theoretically allow up to 52 bits of physical address, although again, chipset and other platform concerns (like the number of DIMM slots available, and the maximum RAM possible per DIMM) prevent such a large physical address space to be realized. On x86-64 processors PAE mode must be active before the switch to long mode, and must remain active while long mode is active, so while in long mode there is no "non-PAE" mode. PAE mode does not affect the width of linear or virtual addresses.


title: X86

text: By the 2000s, 32-bit x86 processors' limits in memory addressing were an obstacle to their use in high-performance computing clusters and powerful desktop workstations. The aged 32-bit x86 was competing with much more advanced 64-bit RISC architectures which could address much more memory. Intel and the whole x86 ecosystem needed 64-bit memory addressing if x86 was to survive the 64-bit computing era, as workstation and desktop software applications were soon to start hitting the limits of 32-bit memory addressing. However, Intel felt that it was the right time to make a bold step and use the transition to 64-bit desktop computers for a transition away from the x86 architecture in general, an experiment which ultimately failed.


title: X86

text: In 2001, Intel attempted to introduce a non-x86 64-bit architecture named IA-64 in its Itanium processor, initially aiming for the high-performance computing market, hoping that it would eventually replace the 32-bit x86. While IA-64 was incompatible with x86, the Itanium processor did provide emulation abilities for translating x86 instructions into IA-64, but this affected the performance of x86 programs so badly that it was rarely, if ever, actually useful to the users: programmers should rewrite x86 programs for the IA-64 architecture or their performance on Itanium would be orders of magnitude worse than on a true x86 processor. The market rejected the Itanium processor since it broke backward compatibility and preferred to continue using x86 chips, and very few programs were rewritten for IA-64.


title: X86

text: AMD decided to take another path toward 64-bit memory addressing, making sure backward compatibility would not suffer. In April 2003, AMD released the first x86 processor with 64-bit general-purpose registers, the Opteron, capable of addressing much more than 4 GB of virtual memory using the new x86-64 extension (also known as AMD64 or x64). The 64-bit extensions to the x86 architecture were enabled only in the newly introduced long mode, therefore 32-bit and 16-bit applications and operating systems could simply continue using an AMD64 processor in protected or other modes, without even the slightest sacrifice of performance and with full compatibility back to the original instructions of the 16-bit Intel 8086. The market responded positively, adopting the 64-bit AMD processors for both high-performance applications and business or home computers.


title: X86

text: Seeing the market rejecting the incompatible Itanium processor and Microsoft supporting AMD64, Intel had to respond and introduced its own x86-64 processor, the "Prescott" Pentium 4, in July 2004. As a result, the Itanium processor with its IA-64 instruction set is rarely used and x86, through its x86-64 incarnation, is still the dominant CPU architecture in non-embedded computers.


title: X86

text: x86-64 also introduced the NX bit, which offers some protection against security bugs caused by buffer overruns.


title: X86

text: As a result of AMD's 64-bit contribution to the x86 lineage and its subsequent acceptance by Intel, the 64-bit RISC architectures ceased to be a threat to the x86 ecosystem and almost disappeared from the workstation market. x86-64 began to be utilized in powerful supercomputers (in its AMD Opteron and Intel Xeon incarnations), a market which was previously the natural habitat for 64-bit RISC designs (such as the IBM Power microprocessors or SPARC processors). The great leap toward 64-bit computing and the maintenance of backward compatibility with 32-bit and 16-bit software enabled the x86 architecture to become an extremely flexible platform today, with x86 chips being utilized from small low-power systems (for example, Intel Quark and Intel Atom) to fast gaming desktop computers (for example, Intel Core i7 and AMD FX/Ryzen), and even dominate large supercomputing clusters, effectively leaving only the ARM 32-bit and 64-bit RISC architecture as a competitor in the smartphone and tablet market.


title: X86

text: Prior to 2005, x86 architecture processors were unable to meet the Popek and Goldberg requirements - a specification for virtualization created in 1974 by Gerald J. Popek and Robert P. Goldberg. However, both proprietary and open-source x86 virtualization hypervisor products were developed using software-based virtualization. Proprietary systems include Hyper-V, Parallels Workstation, VMware ESX, VMware Workstation, VMware Workstation Player and Windows Virtual PC, while free and open-source systems include QEMU, Kernel-based Virtual Machine, VirtualBox, and Xen.


title: X86

text: The introduction of the AMD-V and Intel VT-x instruction sets in 2005 allowed x86 processors to meet the Popek and Goldberg virtualization requirements.


title: Joey Badass

text: Jo-Vaughn Virginie Scott (born January 20, 1995), known professionally as Joey Badass (stylized as Joey Bada$$), is an American rapper, singer, and actor. A native of Brooklyn, New York City, he is a founding member of the hip-hop collective Pro Era, with whom he has released three mixtape as well as his numerous solo projects.


title: Joey Badass

text: Joey Badass released his debut mixtape, "1999", in June 2012 to critical acclaim and recognition, followed by "Rejex" in September, and "Summer Knights" in July 2013. His debut studio album, "B4.Da.$$", was released in January 2015. In 2016, he made his television debut on the USA Network series "Mr. Robot". His second and third studio album, "All-Amerikkkan Badass and" "2000", were released in April 2017 and July 22, 2022, respectively.


title: Joey Badass

text: Jo-Vaughn Virginie Scott was born on January 20, 1995, and was the first of his immediate Caribbean family to be born in the United States. His


title: Joey Badass

text: maternal family originated from the Caribbean island of St. Lucia, while his paternal family originates from the island of Jamaica. He was born in the East Flatbush section of Brooklyn, New York City. He was raised in Bed-Stuy and attended the Edward R. Murrow High School. He originally enrolled at Edward R. Murrow to study acting, but transitioned towards music around the time of 9th grade, with a focus on rapping.


title: Joey Badass

text: He started rapping under the name "JayOhVee", but eventually changed it to Joey Badass. He says that the name change is due to the media's focus on rappers with more cynical names, saying it was "what sounded cool at the time, what fit [his] mood". He began writing poetry and songs at the age of 11. Along with CJ Fly, he is a founding member of the collective known as Progressive Era, or Pro Era for short, which was formed by his high school friends Capital Steez and Powers Pleasant.


title: Joey Badass

text: In October 2010, Joey Badass uploaded a video of himself freestyling to YouTube. The video was re-posted on to American hip hop site World Star Hip Hop and caught the attention of Jonny Shipes, the president of Cinematic Music Group, who soon after became his manager.


title: Joey Badass

text: In early 2012, Joey Badass and Capital Steez released a video for "Survival Tactics" via their YouTube channel "PROfckingERA", which samples the 2000 Fold song of the same name by Styles of Beyond. In February 2012, Pro Era released their debut mixtape entitled "The Secc$ Tap.e". On March 21, 2012, MTV News featured Joey Badass' verse from the video during a RapFix Live segment and subsequently appeared as a featured guest on "Sucker Free" the following month. The song was succeeded with the video premiere of "Hardknock" featuring CJ Fly on MTV2.


title: Joey Badass

text: On June 12, 2012, Joey Badass released his debut solo mixtape "1999". This album was only released to music streaming platforms such as Spotify and Apple Music in 2018. A video for the song "Waves" was released in June 2012. The mixtape immediately increased his popularity in the underground scene. The mixtape was named the 38th best album of 2012 by "Complex" magazine and the best mixtape of 2012 by HipHopDX. On September 6 of the same year, he released another mixtape titled "Rejex", which featured all the tracks that did not make it on the 1999 mixtape.


title: Joey Badass

text: Subsequently, American rapper Mac Miller reached out to Joey Badass through Twitter to collaborate. He appeared on the song "America" from the mixtape "Macadelic" and opened for Miller at the Roseland Ballroom in April 2012. Along with headliner Juicy J, Joey Badass and Pro Era performed on The Smoker's Club's One Hazy Summer Tour, presented by Eckō Unltd. and livemixtapes.com. The 30-date tour began in July 2012. He was featured on the posse cut track "1 Train" off ASAP Rocky's album "Long.Live.ASAP" (2013) which also features Action Bronson, Kendrick Lamar, Yelawolf, Big K.R.I.T., and Danny Brown.


title: Joey Badass

text: In December 2012 it was rumored that Joey Badass would be signing to Jay Z's Roc Nation record label, but in January 2013, he dispelled the rumors saying he would rather stay independent than sign to a major label for the time being. On December 21, 2012, Pro Era released the "" mixtape.


title: Joey Badass

text: On November 9, 2012, Joey Badass released a track with Ab-Soul produced by Lee Bannon called "Enter the Void" along with "Waves". These songs were his first official releases to retail. On January 14, 2013, he released the first single off his second mixtape "Summer Knights", "Unorthodox", which was produced by DJ Premier. On February 8, he released a music video featuring Big K.R.I.T. and Smoke DZA titled "Underground Airplay". The song was featured on the Eckō Unltd. mixtape. On March 5, 2013, he released the music video for "Unorthodox". On March 21, 2013, he began the Beast Coast concert tour with Pro Era, The Underachievers and Flatbush Zombies. On March 26, 2013, it was announced that Joey Badass would be a part of "XXL Magazine's" 2013 Freshman Class.


title: Joey Badass

text: On October 29, 2013, "Summer Knights EP" was released. It featured four songs from the mixtape of the same name, and three new songs including a remix. Upon release, the EP debuted at number 48 on the US "Billboard" Top R&B/Hip-Hop Albums chart.


title: Joey Badass

text: In August 2014, Joey Badass appeared in a quasi-autobiographical short film entitled "No Regrets", directed by Rik Cordero, in which he portrays himself. In an interview on Shade 45 Radio in March 2016, he explained that "it's been my dream to act since I was in like eighth grade. I always wanted to be an actor. And I feel like the music just made it a little bit easier for me to chase that dream."


title: Joey Badass

text: On August 4, 2014, he released the first single from his upcoming debut studio album titled "Big Dusty" with the music video coming out 8 days later. On September 30, he premiered the second single from the album titled "Christ Conscious" on MTV Jams. The third single from the album entitled "No. 99" was released on December 9. On December 23, the fourth single, "Curry Chicken" was released. On January 13 appearing on "The Tonight Show Starring Jimmy Fallon", he performed the song "Like Me" live with BJ the Chicago Kid, The Roots and Statik Selektah. On January 20, 2015, his 20th birthday, the album entitled "B4.DA.$$" was released to critical acclaim.


title: Joey Badass

text: On September 3, 2015, Joey Badass released a collaborative single with Korean hip-hop group Epik High's Tablo and producer Code Kunst called "Hood". On October 6, 2015, he collaborated with British indie rock band Glass Animals, releasing a single titled "Lose Control".


title: Joey Badass

text: On March 4, 2016, Joey Badass made his television debut in the second season of the hit TV series "Mr. Robot", where he was cast in the recurring role of Leon, who is an associate of Elliot (played by Rami Malek). On May 26, 2016, he released another single called "Devastated". The song peaked at number 25 on the Bubbling Under Hot 100 Singles chart, which became Joey's highest charting single to date (as a solo artist). The single was certified gold by the RIAA on January 6, 2017. On January 20, 2017, Joey Badass released "Land of the Free". On March 2, 2017, Joey Bada$$ revealed the title of his second studio album tilted "All-Amerikkkan Bada$$". On April 7, 2017, Joey Badass released the album. On May 12, 2017, it was announced that Joey Badass will go on Logic's Everybody's Tour with Big Lenbo, in support of Logic's third studio album "Everybody".


title: Joey Badass

text: On December 28, 2017, Joey Badass announced via Twitter that he was originally featured on Post Malone's track "Rockstar" along with T-Pain. Badass also admitted to ghostwriting the track. Florida rapper XXXTentacion announced on Instagram that he had a collaboration project with Joey Badass, Badass later confirmed this on January 20, 2018. The two dropped a remix of the song "King's Dead" on SoundCloud on March 9, 2018. The two later on dropped a song titled "Infinity (888)" on XXXTentacion's second studio album "?" one week later on March 16. With the killing of XXXTentacion, though, their collaborative project is all but confirmed to be not happening. On June 12, 2018, Joey re-issued "1999" on all streaming services and vinyl for its 6th anniversary, and in a following interview with Peter Rosenberg, revealed his fatherhood, making public his first child, then 2-month-old Indigo Rain. In December 2019, he was also featured in XXXTentacion's second posthumous and last album, "Bad Vibes Forever".


title: Joey Badass

text: In July 2020, Joey Badass released a 3-track EP entitled "The Light Pack". In November, he featured on Phony Ppl's "On My Shit".


title: Joey Badass

text: On May 11, 2022, he announced his upcoming third studio album, titled "2000" The album was to be released on June 17, 2022, however due to sample clearance issues, he announced on Twitter that he would have to delay the project. The album was released on July 22, 2022, with guest appearances from Diddy, Westside Gunn, Larry June, Chris Brown, Capella Grey, and JID. He also went on a 20-date summer concert tour called the "1999-2000 Tour" in support, which began July 1, 2022 in Boston and concluded July 28, 2022 in Los Angeles.


title: Joey Badass

text: In an interview with XXL, Joey Badass stated that he was influenced by Nas, 2Pac, Black Thought, MF DOOM, J Dilla, Andre 3000, Jay-Z, and The Notorious B.I.G. He has been compared to rapper Big L and Nas during his "Illmatic" era.


title: Joey Badass

text: In January 2015, Joey Badass was arrested and charged with assault for allegedly breaking a security guard's nose before performing at the Falls Festival in Byron Bay, New South Wales, Australia.


title: Joey Badass

text: In June 2015, tensions between Joey Badass and fellow Brooklyn native Troy Ave began brewing after the former declared himself the "#1 independent hip hop artist/brand in the world" in a series of tweets. Troy Ave responded in another tweet by pointing out that Joey Badass is signed to Cinematic Music Group, whose music is distributed by RED Distribution, a subsidiary of Sony Music Entertainment, but Joey Badass later denied reports of a feud between the two of them.


title: Joey Badass

text: On July 7, 2015, in an interview with Ebro Darden on Hot 97, Joey Badass had words of praise for Troy Ave, stating: "At some point you gotta have some level of respect for Troy because, at the end of the day, we're both independent artists who are standing on major platforms next to a whole bunch of major artists and they know who we are." However, in February 2016, he reignited the feud in a single entitled "Ready", where he rapped: "60k, first week for the badass / 200k to this day, I know you niggas mad / With that 80-20 split, my nigga do the math / my nigga Kirk just outsold Troy Ave" (in reference to Kirk Knight's debut studio album "Late Knight Special" and Troy Ave's second studio album "Major Without a Deal").


title: Joey Badass

text: In response to "Ready", Troy Ave released a diss track entitled "Badass" the following week, in which he not only insulted Joey Badass, but also targeted Capital Steez and his suicide. Following the song's release, Troy Ave defended his actions on Shade 45's "Sway in the Morning", stating: "He didn't pass away; he killed himself. There's a difference. He took his own life. God gave you life, it ain't your right to take that. That's a fact. I got niggas in jail who got life sentences, they might as well be dead. They could've traded their life for his." He then received heavy criticism from both fans and fellow artists, including A$AP Ant, A$AP Twelvyy and Styles P who wrote, amongst a series of other tweets: "If you never experienced a family [member] committing suicide you have no fukn [sic] idea about that pain. NONE." Troy Ave then replied to Styles P's comments and apologized to his fans on Twitter. In an interview on VladTV, another Brooklyn rapper, Maino, stated that mentioning Capital Steez's suicide in the song was "a bit much".


title: Joey Badass

text: In a freestyle on "Sway in the Morning" on March 29, 2016, Joey Badass responded to "Badass" in a series of lines aimed at Troy Ave, though never referring to him directly. Among other lines, he rapped: "I destroy average rappers, it's just practice […] Men lie, women lie, numbers sure don't / Got the whole Beast Coast coming for your skull / The karma gon' catch up, your album sales won't". In an interview with "HipHopDX" the following day, Fat Joe stated that he personally reached out to both Joey Badass and Troy Ave to try and squash the feud, but failed.


title: Joey Badass

text: In May 2020, Joey Badass donated $25,000 to support homeless students in New York City during the COVID-19 crisis.


title: Asheville, North Carolina

text: Asheville ( ) is a city in, and the county seat of, Buncombe County, North Carolina. Located at the confluence of the French Broad and Swannanoa rivers, it is the largest city in Western North Carolina, and the state's 11th-most populous city. According to the 2020 census, the city's population was 94,589, up from 83,393 in the 2010 census. It is the principal city in the four-county Asheville metropolitan area, which had a population of 424,858 in 2010, and of 469,015 in 2020.


title: Asheville, North Carolina

text: Before the arrival of the Europeans, the land where Asheville now exists lay within the boundaries of the Cherokee Nation, which had homelands in modern western North and South Carolina, southeastern Tennessee, and northeastern Georgia. A town at the site of the river confluence was recorded as "Guaxule" by Spanish explorer Hernando de Soto during his 1540 expedition through this area. His expedition comprised the first European visitors, who carried endemic Eurasian infectious diseases that killed many in the native population.


title: Asheville, North Carolina

text: The Cherokee had traditionally used the area by the confluence for open hunting and meeting grounds. They called it "Untokiasdiyi" (in Cherokee), meaning "Where they race", until the middle of the 19th century.


title: Asheville, North Carolina

text: European Americans began to settle in the area of Asheville in 1784, after the United States gained independence in the American Revolutionary War. In that year, Colonel Samuel Davidson and his family settled in the Swannanoa Valley, redeeming a soldier's land grant from the state of North Carolina made in lieu of pay. Soon after building a log cabin at the bank of Christian Creek, Davidson was lured into the woods and killed by a band of Cherokee hunters resisting white encroachment. Davidson's wife, child, and female slave fled on foot overnight to Davidson's Fort (named after Davidson's father General John Davidson) 16 miles away.


title: Asheville, North Carolina

text: In response to the killing, Davidson's twin brother Major William Davidson and brother-in-law Colonel Daniel Smith formed an expedition to retrieve Samuel Davidson's body and avenge his murder. Months after the expedition, Major Davidson and other members of his extended family returned to the area and settled at the mouth of Bee Tree Creek.


title: Asheville, North Carolina

text: The U.S. Census of 1790 counted 1,000 residents of the area, excluding the Cherokee Native Americans as a separate nation. Buncombe County was officially formed in 1792. In the 1800 US Census, some 107 settlers in the county were slaveholders, owning a total of 300 enslaved African Americans. Total county population was 5,812.


title: Asheville, North Carolina

text: The county seat, named "Morristown" in 1793, was established on a plateau where two old Indian trails crossed. In 1797, Morristown was incorporated and renamed "Asheville" after North Carolina Governor Samuel Ashe.


title: Asheville, North Carolina

text: In the 1800s, James McDowell established land for burial of slaves belonging to his and the Smith families in Asheville. His son William Wallace McDowell continued this practice, setting aside about two acres of land for this purpose.


title: Asheville, North Carolina

text: On the eve of the Civil War, James W. Patton, son of an Irish immigrant, was the largest slaveholder in the county, and had built a luxurious mansion, known as The Henrietta, in Asheville. Buncombe County had the largest number of prominent slaveholders in Western North Carolina, many in the professional class based in Asheville, numbering a total of 293 countywide in 1863.


title: Asheville, North Carolina

text: Asheville, with a population of about 2,500 by 1861, remained relatively untouched by battles of the Civil War. The city contributed a number of companies to the Confederate States Army, as well as a number for the Union Army. For a time, an Enfield rifle manufacturing facility was located in the town.


title: Asheville, North Carolina

text: The war did not reach Asheville until early April 1865, when the "Battle of Asheville" was fought at the present-day site of the University of North Carolina at Asheville. Union forces withdrew to Tennessee, which they had occupied since 1862. They had encountered resistance in Asheville from a small group of Confederate senior and junior reserves, and recuperating Confederate soldiers in prepared trench lines across the Buncombe Turnpike. The Union force had been ordered to take Asheville only if they could accomplish it without significant losses.


title: Asheville, North Carolina

text: An engagement was fought later that month at Swannanoa Gap, as part of the larger Stoneman's Raid throughout western North Carolina, Virginia and Tennessee. Union forces retreated in the face of resistance from Brig. Gen. Martin, commander of Confederate troops in western North Carolina. Later, Union forces returned to the area via Howard's Gap and Henderson County. In late April 1865, North Carolina Union troops from the 3rd North Carolina Mounted Infantry, under the overall command of Union Gen. George Stoneman, captured Asheville. After a negotiated departure, the 2,700 troops left town, accompanied by "hundreds of freed slaves."


title: Asheville, North Carolina

text: The slave George Avery was among 40 slaves known to have traveled with the troops to Tennessee. There he enlisted in the US Colored Troops. He returned to Asheville after being formally discharged in 1866. After the war, he was hired by his former master William W. McDowell to manage the South Asheville Cemetery, a public place for black burials. This is the oldest and largest black public cemetery in the state. By 1943, when the last burial was conducted, it held remains of an estimated 2,000 people.


title: Asheville, North Carolina

text: Later, the federal troops returned and plundered Asheville, burning a number of Confederate supporters' homes in Asheville.


title: Asheville, North Carolina

text: On October 2, 1880, the Western North Carolina Railroad completed its line from Salisbury to Asheville, the first rail line to reach the city. Almost immediately it was sold and resold to the Richmond and Danville Railroad Company, becoming part of the Southern Railway in 1894. With the completion of the first railway, Asheville developed with steady growth as industrial plants increased in number and size, and new residents built homes. Textile mills were built to process cotton from the region, and other plants were set up to manufacture wood and mica products, foodstuffs, and other commodities.


title: Asheville, North Carolina

text: The distance between Hendersonville and Asheville of the former Asheville and Spartanburg Railroad was completed in 1886. By that point, the line was operated as part of the Richmond and Danville Railroad until 1894 and controlled by the Southern Railway afterward. Following major changes in the industry because of the competition from automobiles, railroad restructuring resulted in Asheville's final passenger train, a coach-only remnant of the Southern Railway's "Carolina Special", making its last run on December 5, 1968.


title: Asheville, North Carolina

text: Asheville had the first electric street railway lines in the state of North Carolina, the first of which opened in 1889. These were replaced by buses in 1934.


title: Asheville, North Carolina

text: In 1900, Asheville was the third-largest city in the state, behind Wilmington and Charlotte. Asheville prospered in the decades of the 1910s and 1920s. During these years, Rutherford P. Hayes, son of President Rutherford B. Hayes, bought land, and worked with the prominent African-American businessman Edward W. Pearson, Sr. to develop his land for residential housing known as the African-American Burton Street Community. Hayes also worked to establish a sanitary district in West Asheville, which became an incorporated town in 1913, and merged with Asheville in 1917.


title: Asheville, North Carolina

text: The Asheville Masonic Temple was constructed in 1913, under the direction of famed architect Richard Sharp Smith, a Freemason. It was the meeting place for local Masons through much of the 20th century.


title: Asheville, North Carolina

text: On July 15–16, 1916, the Asheville area was subject to severe flooding from the remnants of a tropical storm which caused more than $3 million in damage. Areas flooded included part of the Biltmore Estate, and the company that ran it sold some of the property to lower their maintenance costs. This area was later developed as an independent jurisdiction known as Biltmore Forest, which is now one of the wealthiest in the country.


title: Asheville, North Carolina

text: The Great Depression hit Asheville quite hard. On November 20, 1930, eight local banks failed. Only Wachovia remained open with infusions of cash from Winston-Salem. Because of the explosive growth of the previous decades, the per capita debt owed by the city (through municipal bonds) was the highest in the nation. By 1929, both the city and Buncombe County had incurred over $56 million in bonded debt to pay for a wide range of municipal and infrastructure improvements, including City Hall, the water system, Beaucatcher Tunnel, and Asheville High School. Rather than default, the city paid those debts over a period of fifty years.


title: Asheville, North Carolina

text: From the start of the depression through the 1980s, economic growth in Asheville was slow. During this time of financial stagnation, most of the buildings in the downtown district remained unaltered. As a result, Asheville has one of the most impressive, comprehensive collections of Art Deco architecture in the United States.


title: Asheville, North Carolina

text: In 1959, the city council would purchase property partially located in neighboring Henderson County for the development of Asheville Regional Airport. The North Carolina General Assembly would pass a bill that would to redesign the boundaries of Buncombe and Henderson to include the proposed airport property entirely in Buncombe, allowing Asheville to annex the complete site.


title: Asheville, North Carolina

text: From the 1950s to the 1970s, urban renewal displaced much of Asheville's African-American population. Asheville's neighborhoods of Montford and Kenilworth, now mostly white, used to have a majority of black home owners. Since the late 20th century, there has been an effort to maintain and preserve the South Asheville Cemetery, in the Kenilworth neighborhood. It is the largest public black cemetery in the state, holding about 2000 burials, dating from the early 1800s and slavery years, to 1943. Fewer than 100 of the graves are marked by tombstones.


title: Asheville, North Carolina

text: In 2003, Centennial Olympic Park bomber Eric Robert Rudolph was transported to Asheville from Murphy, North Carolina, for arraignment in federal court.


title: Asheville, North Carolina

text: In September 2004, remnants of Hurricanes Frances and Ivan caused major flooding in Asheville, particularly at Biltmore Village. In 2006, the Asheville Zombie Walk was organized for the first time, starting a tradition that lasted until 2016.


title: Asheville, North Carolina

text: In July 2020, the Asheville City Council voted to provide reparations to Black residents for the city's "historic role in slavery, discrimination and denial of basic liberties". The resolution was unanimously passed, and Asheville committed to "make investments in areas where Black residents face disparities". Also in 2020, efforts were made to remove or change several monuments in the city that celebrated the Confederate States of America or slave owners. Attorney Sean Devereux proposed renaming Asheville in honor of Arthur Ashe, whose ancestors were owned by Samuel Ashe, for whom the city was named. In June 2021, Asheville Mayor Esther Manheimer was one of 11 U.S. mayors to form Mayors Organized for Reparations and Equity (MORE), a coalition of municipal leaders dedicated to starting pilot reparations programs in their cities.


title: Asheville, North Carolina

text: Asheville is located in the Blue Ridge Mountains at the confluence of the Swannanoa River and the French Broad River. According to the United States Census Bureau, the city has a total area of , of which is land and , or 0.66%, is water.


title: Asheville, North Carolina

text: Asheville is 68.44 miles west of Hickory, North Carolina, 99.51 northwest of Charlotte, and 133.84 miles southwest of Winston-Salem.