title: Northwest Passage

text: The first explorer to conquer the Northwest Passage solely by ship was the Norwegian explorer Roald Amundsen. In a three-year journey between 1903 and 1906, Amundsen explored the passage with a crew of six. Amundsen, who had sailed to escape creditors seeking to stop the expedition, completed the voyage in the converted 45 net register tonnage () herring boat "Gjøa". "Gjøa" was much smaller than vessels used by other Arctic expeditions and had a shallow draft. Amundsen intended to hug the shore, live off the limited resources of the land and sea through which he was to travel, and had determined that he needed to have a tiny crew to make this work. (Trying to support much larger crews had contributed to the catastrophic failure of John Franklin's expedition fifty years previously). The ship's shallow draft was intended to help her traverse the shoals of the Arctic straits.


title: Northwest Passage

text: Amundsen set out from Kristiania (Oslo) in June 1903 and was west of the Boothia Peninsula by late September. "Gjøa" was put into a natural harbour on the south shore of King William Island; by October 3 she was iced in. There the expedition remained for nearly two years, with the expedition members learning from the local Inuit and undertaking measurements to determine the location of the North Magnetic Pole. The harbour, now known as Gjoa Haven, later developed as the only permanent settlement on the island.


title: Northwest Passage

text: After completing the Northwest Passage portion of this trip and having anchored near Herschel Island, Amundsen skied to the city of Eagle, Alaska. He sent a telegram announcing his success and skied the return to rejoin his companions. Although his chosen east–west route, via the Rae Strait, contained young ice and thus was navigable, some of the waterways were extremely shallow ( deep), making the route commercially impractical.


title: Northwest Passage

text: The first traversal of the Northwest Passage via dog sled was accomplished by Greenlander Knud Rasmussen while on the Fifth Thule Expedition (1921–1924). Rasmussen and two Greenland Inuit travelled from the Atlantic to the Pacific over the course of 16 months via dog sled.


title: Northwest Passage

text: Canadian Royal Canadian Mounted Police officer Henry Larsen was the second to sail the passage, crossing west to east, leaving Vancouver on June 23, 1940, and arriving at Halifax on October 11, 1942. More than once on this trip, he was uncertain whether , a Royal Canadian Mounted Police "ice-fortified" schooner, would survive the pressures of the sea ice. At one point, Larsen wondered "if we had come this far only to be crushed like a nut on a shoal and then buried by the ice." The ship and all but one of her crew survived the winter on Boothia Peninsula. Each of the men on the trip was awarded a medal by Canada's sovereign, King George VI, in recognition of this feat of Arctic navigation.


title: Northwest Passage

text: Later in 1944, Larsen's return trip was far more swift than his first. He made the trip in 86 days to sail back from Halifax, Nova Scotia, to Vancouver, British Columbia. He set a record for traversing the route in a single season. The ship, after extensive upgrades, followed a more northerly, partially uncharted route.


title: Northwest Passage

text: In 1954, completed the east-to-west transit, under the command of Captain O.C.S. Robertson, conducting hydrographic soundings along the route. She was the first warship (and the first deep draft ship) to transit the Northwest Passage and the first warship to circumnavigate North America. In 1956, HMCS "Labrador" again completed the east-to-west transit, this time under the command of Captain T.C. Pullen.


title: Northwest Passage

text: On July 1, 1957, the United States Coast Guard Cutter departed in company with and to search for a deep-draft channel through the Arctic Ocean and to collect hydrographic information. The US Coast Guard Squadron was escorted through Bellot Strait and the Eastern Arctic by HMCS "Labrador". Upon her return to Greenland waters, "Storis" became the first U.S.-registered vessel to circumnavigate North America. Shortly after her return in late 1957, she was reassigned to her new home port of Kodiak, Alaska.


title: Northwest Passage

text: In 1969, SS "Manhattan" made the passage, accompanied by the Canadian icebreakers and . The U.S. Coast Guard icebreakers and also sailed in support of the expedition.


title: Northwest Passage

text: "Manhattan" was a specially reinforced supertanker sent to test the viability of the passage for the transport of oil. While "Manhattan" succeeded, the route was deemed not to be cost-effective. The United States built the Alaska Pipeline instead.


title: Northwest Passage

text: In June 1977, sailor Willy de Roos left Belgium to attempt the Northwest Passage in his steel yacht "Williwaw". He reached the Bering Strait in September and after a stopover in Victoria, British Columbia, went on to round Cape Horn and sail back to Belgium, thus being the first sailor to circumnavigate the Americas entirely by ship.


title: Northwest Passage

text: In 1981 as part of the Transglobe Expedition, Ranulph Fiennes and Charles R. Burton completed the Northwest Passage. They left Tuktoyaktuk on July 26, 1981, in the open Boston Whaler and reached Tanquary Fiord on August 31, 1981. Their journey was the first open-boat transit from west to east and covered around , taking a route through Dolphin and Union Strait following the south coast of Victoria and King William islands, north to Resolute Bay via Franklin Strait and Peel Sound, around the south and east coasts of Devon Island, through Hell Gate and across Norwegian Bay to Eureka, Greely Bay and the head of Tanquary Fiord. Once they reached Tanquary Fiord, they had to trek via Lake Hazen to Alert before setting up their winter base camp.


title: Northwest Passage

text: In 1984, the commercial passenger vessel (which sank in the Antarctic Ocean in 2007) became the first cruise ship to navigate the Northwest Passage.


title: Northwest Passage

text: In July 1986, Jeff MacInnis and Mike Beedell set out on an catamaran called "Perception" on a 100-day sail, west to east, through the Northwest Passage. This pair was the first to sail the passage, although they had the benefit of doing so over a couple of summers.


title: Northwest Passage

text: In July 1986, David Scott Cowper set out from England in a lifeboat named "Mabel El Holland", and survived three Arctic winters in the Northwest Passage before reaching the Bering Strait in August 1989. He continued around the world via the Cape of Good Hope to return to England on September 24, 1990. His was the first vessel to circumnavigate the world via the Northwest Passage.


title: Northwest Passage

text: On July 1, 2000, the Royal Canadian Mounted Police patrol vessel , having assumed the name "St Roch II", departed Vancouver on a "Voyage of Rediscovery." "Nadon"s mission was to circumnavigate North America via the Northwest Passage and the Panama Canal, recreating the epic voyage of her predecessor, "St. Roch." The Voyage of Rediscovery was intended to raise awareness concerning "St. Roch" and kick off the fund-raising efforts necessary to ensure the continued preservation of "St. Roch". The voyage was organized by the Vancouver Maritime Museum and supported by a variety of corporate sponsors and agencies of the Canadian government.


title: Northwest Passage

text: "Nadon" is an aluminum, catamaran-hulled, high-speed patrol vessel. To make the voyage possible, she was escorted and supported by the Canadian Coast Guard icebreaker . The Coast Guard vessel was chartered by the Voyage of Rediscovery and crewed by volunteers. Throughout the voyage, she provided a variety of necessary services, including provisions and spares, fuel and water, helicopter facilities, and ice escort; she also conducted oceanographic research during the voyage. The Voyage of Rediscovery was completed in five and a half months, with "Nadon" reaching Vancouver on December 16, 2000.


title: Northwest Passage

text: On September 1, 2001, "Northabout", an aluminium sailboat with diesel engine, built and captained by Jarlath Cunnane, completed the Northwest Passage east-to-west from Ireland to the Bering Strait. The voyage from the Atlantic to the Pacific was completed in 24 days. Cunnane cruised in "Northabout" in Canada for two years before returning to Ireland in 2005 via the Northeast Passage; he completed the first east-to-west circumnavigation of the pole by a single sailboat. The Northeast Passage return along the coast of Russia was slower, starting in 2004, requiring an ice stop and winter over in Khatanga, Siberia. He returned to Ireland via the Norwegian coast in October 2005. On January 18, 2006, the Cruising Club of America awarded Jarlath Cunnane their Blue Water Medal, an award for "meritorious seamanship and adventure upon the sea displayed by amateur sailors of all nationalities."


title: Northwest Passage

text: On July 18, 2003, a father-and-son team, Richard and Andrew Wood, with Zoe Birchenough, sailed the yacht "Norwegian Blue" into the Bering Strait. Two months later she sailed into the Davis Strait to become the first British yacht to transit the Northwest Passage from west to east. She also became the only British vessel to complete the Northwest Passage in one season, as well as the only British sailing yacht to return from there to British waters.


title: Northwest Passage

text: In 2006, a scheduled cruise liner () successfully ran the Northwest Passage, helped by satellite images telling the location of sea ice.


title: Northwest Passage

text: On May 19, 2007, a French sailor, Sébastien Roubinet, and one other crew member left Anchorage, Alaska, in "Babouche", a ice catamaran designed to sail on water and slide over ice. The goal was to navigate west to east through the Northwest Passage by sail only. Following a journey of more than , Roubinet reached Greenland on September 9, 2007, thereby completing the first Northwest Passage voyage made in one season without engine.


title: Northwest Passage

text: In April 2009, planetary scientist Pascal Lee and a team of four on the Northwest Passage Drive Expedition drove the HMP "Okarian" Humvee rover a record-setting on sea-ice from Kugluktuk to Cambridge Bay, Nunavut, the longest distance driven on sea-ice in a road vehicle. The HMP "Okarian" was being ferried from the North American mainland to the Haughton–Mars Project (HMP) Research Station on Devon Island, where it would be used as a simulator of future pressurized rovers for astronauts on the Moon and Mars. The HMP "Okarian" was eventually flown from Cambridge Bay to Resolute Bay in May 2009, and then driven again on sea-ice by Lee and a team of five from Resolute to the West coast of Devon Island in May 2010. The HMP "Okarian" reached the HMP Research Station in July 2011. The Northwest Passage Drive Expedition is captured in the motion picture documentary film "Passage To Mars" (2016).


title: Northwest Passage

text: In 2009, sea ice conditions were such that at least nine small vessels and two cruise ships completed the transit of the Northwest Passage. These trips included one by Eric Forsyth on board the Westsail sailboat "Fiona", a boat he built in the 1980s. Self-financed, Forsyth, a retired engineer from the Brookhaven National Laboratory, and winner of the Cruising Club of America's Blue Water Medal, sailed the Canadian Archipelago with sailor Joey Waits, airline captain Russ Roberts and carpenter David Wilson. After successfully sailing the Passage, the 77-year-old Forsyth completed the circumnavigation of North America, returning to his home port on Long Island, New York.


title: Northwest Passage

text: Cameron Dueck and his crew aboard the sailing yacht "Silent Sound" also transited in the summer of 2009. Their voyage began in Victoria, BC, on June 6, and they arrived in Halifax on October 10. Dueck wrote a book about the voyage called "The New Northwest Passage".


title: Northwest Passage

text: In August–September 2010, Graeme Kendall (New Zealand) sailed the "Astral Express" through the Northwest Passage. He was the first person to sail solo non-stop through the passage. He began in Lancaster Sound on August 27 and ended 12 days later at Point Barrow, Alaska, on September 9. The trip covered . It was part of a circumnavigation that started and ended in New Zealand.


title: Northwest Passage

text: On September 9, 2010, Bear Grylls and a team of five completed a point-to-point navigation between Pond Inlet and Tuktoyaktuk in the Northwest Territories on a rigid inflatable boat (RIB). The expedition drew attention to how the effects of global warming made this journey possible and raised funds for the Global Angels charity.


title: Northwest Passage

text: On August 30, 2012 Sailing yacht , , an English SY, successfully completed the Northwest Passage in Nome, Alaska, while sailing a northern route never sailed by a sailing pleasure vessel before. After six cruising seasons in the Arctic (Greenland, Baffin Bay, Devon Island, Kane Basin, Lancaster Sound, Peel Sound, Regent Sound) and four seasons in the South (Antarctic Peninsula, Patagonia, Falkland Islands, South Georgia), SY "Billy Budd", owned by and under the command of an Italian sporting enthusiast, Mariacristina Rapisardi. Crewed by Marco Bonzanigo, five Italian friends, one Australian, one Dutch, one South African, and one New Zealander, it sailed through the Northwest Passage. The northernmost route was chosen. "Billy Budd" sailed through the Parry Channel, Viscount Melville Sound and Prince of Wales Strait, a channel long and wide which flows south into the Amundsen Gulf. During the passage "Billy Budd" – likely a first for a pleasure vessel – anchored in Winter Harbour in Melville Island, the very same site where almost 200 years ago Sir William Parry was blocked by ice and forced to winter.


title: Northwest Passage

text: On August 29, 2012, the Swedish yacht "Belzebub II," a fibreglass cutter captained by Canadian Nicolas Peissel, Swede Edvin Buregren and Morgan Peissel, became the first sailboat in history to sail through McClure Strait, part of a journey of achieving the most northerly Northwest Passage. "Belzebub II" departed Newfoundland following the coast of Greenland to Qaanaaq before tracking the sea ice to Grise Fiord, Canada's most northern community. From there the team continued through Parry Channel into McClure Strait and the Beaufort Sea, tracking the highest latitudes of 2012's record sea ice depletion before completing their Northwest Passage September 14, 2012. The expedition received extensive media coverage, including recognition by former U.S. Vice President Al Gore. The accomplishment is recorded in the Polar Scott Institute's record of Northwest Passage Transits and recognized by the Explorers Club and the Royal Canadian Geographic Society.


title: Northwest Passage

text: At 18:45 GMT on September 18, 2012, "Best Explorer", a steel cutter , skipper Nanni Acquarone, passing between the two Diomedes, was the first Italian sailboat to complete the Northwest Passage along the classical Amundsen route. Twenty-two Italian amateur sailors took part of the trip, in eight legs from Tromsø, Norway, to King Cove, Alaska, totalling . Later in 2019 "Best Explorer" skippered again by Nanni Acquarone became the first Italian sailboat to circumnavigate the Arctic sailing north of Siberia from Petropavlovsk-Kamchatsky to Tromsø and the second ever to do it clockwise.


title: Northwest Passage

text: Setting sail from Nome, Alaska, on August 18, 2012, and reaching Nuuk, Greenland, on September 12, 2012, became the largest passenger vessel to transit the Northwest Passage. The ship, carrying 481 passengers, for 26 days and at sea, followed in the path of Captain Roald Amundsen. "The World" transit of the Northwest Passage was documented by "National Geographic" photographer Raul Touzon.


title: Northwest Passage

text: In September 2013, became the first commercial bulk carrier to transit the Northwest Passage. She was carrying a cargo of of coking coal from Port Metro Vancouver, Canada, to the Finnish Port of Pori, more than would have been possible via the traditional Panama Canal route. The Northwest Passage shortened the distance by compared to traditional route via the Panama Canal.


title: Northwest Passage

text: In August and September 2016 a cruise ship was sailed through the Northwest Passage. The ship "Crystal Serenity", (with 1,000 passengers, and 600 crew) left Seward, Alaska, used Amundsen's route and reached New York on September 17. Tickets for the 32-day trip started at $22,000 and were quickly sold out. The trip was repeated in 2017. In 2017 33 vessels made a complete transit, breaking the prior record of 20 in 2012.


title: Northwest Passage

text: In September 2018, sailing yacht "Infinity" (a 36·6 m ketch) and her 22-person crew successfully sailed through the Northwest Passage. This was part of their mission to plant the flag of Earth on the remaining Arctic ice. Supported by the EarthToday initiative, this voyage was a symbol for future global collaboration against climate change. The flag of Planet Earth was planted on September 21, 2018, the International Day of Peace.


title: Northwest Passage

text: The Canadian government classifies the waters of the Northwest Passage in the Canadian Arctic Archipelago, as internal waters of Canada as per the United Nations Convention on the Law of the Sea and by the precedent in the drawing of baselines for other archipelagos, giving Canada the right to bar transit through these waters. Some maritime nations, notably the United States, claim these waters to be an international strait, where foreign vessels have the right of "transit passage." In such a regime, Canada would have the right to enact fishing and environmental regulation, and fiscal and smuggling laws, as well as laws intended for the safety of shipping, but not the right to close the passage. While Canada is a party to the 1982 convention, the United States has not ratified it.


title: Northwest Passage

text: The dispute between Canada and the United States arose in 1969 with the trip of the U.S. oil tanker through the Arctic Archipelago. The prospect of more American traffic headed to the Prudhoe Bay Oil Field made the Canadian government realize that political action was required. If the passage's deep waters become completely ice-free in summer months, they will be particularly enticing for supertankers that are too big to pass through the Panama Canal and must otherwise navigate around the tip of South America.


title: Northwest Passage

text: In 1985, the U.S. Coast Guard icebreaker passed through from Greenland to Alaska; the ship submitted to inspection by the Canadian Coast Guard before passing through, but the event infuriated the Canadian public and resulted in a diplomatic incident. The United States government, when asked by a Canadian reporter, indicated that they did not ask for permission as they insist that the waters were an international strait. The Canadian government issued a declaration in 1986 reaffirming Canadian rights to the waters. The United States refused to recognize the Canadian claim. In 1988 the governments of Canada and the United States signed an agreement, "Arctic Cooperation," that resolved the practical issue without solving the sovereignty questions. Under the law of the sea, ships engaged in transit passage are not permitted to engage in research. The agreement states that all U.S. Coast Guard and Navy vessels are engaged in research, and so would require permission from the Government of Canada to pass through.


title: Northwest Passage

text: However, in late 2005, it was reported that U.S. nuclear submarines had travelled unannounced through Canadian Arctic waters, breaking the "Arctic Cooperation" agreement and sparking outrage in Canada. In his first news conference after the 2006 federal election, Prime Minister-designate Stephen Harper contested an earlier statement made by the U.S. ambassador that Arctic waters were international, stating the Canadian government's intention to enforce its sovereignty there. The allegations arose after the U.S. Navy released photographs of surfaced at the North Pole.


title: Northwest Passage

text: On April 9, 2006, Canada's Joint Task Force (North) declared that the Canadian Forces will no longer refer to the region as the Northwest Passage, but as the Canadian Internal Waters. The declaration came after the successful completion of Operation Nunalivut (Inuktitut for "the land is ours"), which was an expedition into the region by five military patrols.


title: Northwest Passage

text: In 2006 a report prepared by the staff of the Parliamentary Information and Research Service of Canada suggested that because of the September 11 attacks, the United States might be less interested in pursuing the international waterways claim in the interests of having a more secure North American perimeter. This report was based on an earlier paper, "The Northwest Passage Shipping Channel: Is Canada's Sovereignty Really Floating Away?" by Andrea Charron, given to the 2004 Canadian Defence and Foreign Affairs Institute Symposium. Later in 2006 former United States Ambassador to Canada, Paul Cellucci agreed with this position; however, the succeeding ambassador, David Wilkins, stated that the Northwest Passage was in international waters.


title: Northwest Passage

text: On July 9, 2007, Prime Minister Harper announced the establishment of a deep-water port in the far North. In the press release Harper said, "Canada has a choice when it comes to defending our sovereignty over the Arctic. We either use it or lose it. And make no mistake, this Government intends to use it. Because Canada's Arctic is central to our national identity as a northern nation. It is part of our history. And it represents the tremendous potential of our future."


title: Northwest Passage

text: On July 10, 2007, Rear Admiral Timothy McGee of the U.S. Navy and Rear Admiral Brian Salerno of the U.S. Coast Guard announced that the United States would be increasing its ability to patrol the Arctic.


title: Northwest Passage

text: In June 2019, the U.S. State Department spokesperson Morgan Ortagus said, “We view Canada’s claim that the waters of the Northwest Passage are internal waters of Canada as inconsistent with international law,” despite historical precedent regarding archipelago baselines.


title: Northwest Passage

text: In summer 2000, two Canadian ships took advantage of thinning summer ice cover on the Arctic Ocean to make the crossing. It is thought that climate change is likely to open the passage for increasing periods, making it potentially attractive as a major shipping route. However, the passage through the Arctic Ocean would require significant investment in escort vessels and staging ports, and it would remain seasonal. Therefore, the Canadian commercial marine transport industry does not anticipate the route as a viable alternative to the Panama Canal within the next 10 to 20 years (as of 2004).


title: Northwest Passage

text: On September 14, 2007, the European Space Agency (ESA) stated that ice loss that year had opened up the historically impassable passage, setting a new low of ice cover as seen in satellite measurements which went back to 1978. According to the Arctic Climate Impact Assessment, the latter part of the 20th century and the start of the 21st had seen marked shrinkage of ice cover. The extreme loss in 2007 rendered the passage "fully navigable." However, the ESA study was based only on analysis of satellite images and could in practice not confirm anything about the actual navigation of the waters of the passage. ESA suggested the passage would be navigable "during reduced ice cover by multi-year ice pack" (namely sea ice surviving one or more summers) where previously any traverse of the route had to be undertaken during favourable seasonable climatic conditions or by specialist vessels or expeditions. The agency's report speculated that the conditions prevalent in 2007 had shown the passage may "open" sooner than expected. An expedition in May 2008 reported that the passage was not yet continuously navigable even by an icebreaker and not yet ice-free.


title: Northwest Passage

text: Scientists at a meeting of the American Geophysical Union on December 13, 2007, revealed that NASA satellites observing the western Arctic showed a 16% decrease in cloud coverage during the summer of 2007 compared to 2006. This would have the effect of allowing more sunlight to penetrate Earth's atmosphere and warm the Arctic Ocean waters, thus melting sea ice and contributing to opening the Northwest Passage.


title: Northwest Passage

text: In 2006 the cruise liner successfully ran the Northwest Passage, helped by satellite images telling where sea ice was.


title: Northwest Passage

text: On November 28, 2008, the Canadian Coast Guard confirmed the first commercial ship sailed through the Northwest Passage. In September 2008, , owned by Desgagnés Transarctik Inc. and, along with the Arctic Cooperative, part of Nunavut Sealift and Supply Incorporated (NSSI), transported cargo from Montreal to the hamlets of Cambridge Bay, Kugluktuk, Gjoa Haven, and Taloyoak. A member of the crew is reported to have claimed that "there was no ice whatsoever." Shipping from the east was to resume in the fall of 2009. Although sealift is an annual feature of the Canadian Arctic this was the first time that the western communities had been serviced from the east. The western portion of the Canadian Arctic is normally supplied by Northern Transportation Company Limited (NTCL) from Hay River, and the eastern portion by NNSI and NTCL from Churchill and Montreal.


title: Northwest Passage

text: In January 2010, the ongoing reduction in the Arctic sea ice led telecoms cable specialist Kodiak-Kenai Cable to propose the laying of a fibre-optic cable connecting London and Tokyo by way of the Northwest Passage, saying the proposed system would nearly cut in half the time it takes to send messages from the United Kingdom to Japan.


title: Northwest Passage

text: In 2016 a new record was set when the cruise ship "Crystal Serenity" transited with 1,700 passengers and crew. "Crystal Serenity" is the largest cruise ship to navigate the Northwest Passage. Starting on August 10, 2016, the ship sailed from Vancouver to New York City, taking 28 days for the journey.


title: Northwest Passage

text: Plans to lay a fibre-optic cable through the passage were revived in 2021, the project is known as Far North Fiber.


title: Northwest Passage

text: Scientists believe that reduced sea ice in the Northwest Passage has permitted some new species to migrate across the Arctic Ocean. The gray whale "Eschrichtius robustus" has not been seen in the Atlantic since it was hunted to extinction there in the 18th century, but in May 2010, one such whale turned up in the Mediterranean. Scientists speculated the whale had followed its food sources through the Northwest Passage and simply kept on going.


title: Northwest Passage

text: The plankton species "Neodenticula seminae" had not been recorded in the Atlantic for 800,000 years. However, it has become increasingly prevalent there. Again, scientists believe that it got there through the reopened Northwest Passage.


title: Northwest Passage

text: In August 2010, two bowhead whales from West Greenland and Alaska respectively, entered the Northwest Passage from opposite directions and spent approximately 10 days in the same area.


title: Are You Being Served?

text: Are You Being Served? is a British sitcom created and written by executive producer David Croft (Croft also directed some episodes) and Jeremy Lloyd, with contributions from Michael Knowles and John Chapman, for the BBC. Set in London, the show follows the misadventures and mishaps of the staff of the retail ladies' and gentlemen's clothing departments in the flagship department store of a fictional chain called Grace Brothers.


title: Are You Being Served?

text: The series was broadcast on the BBC for ten series, totalling 69 episodes between 8 September 1972 and 1 April 1985 – and included five Christmas specials. There was also a 1977 film, a spin-off series "Grace & Favour" with the same main cast in 1991–1992, and a one-off episode with a new cast in 2016. Since its original release, all 69 episodes, the pilot, the Christmas specials, the sequel and the film have been released on DVD.


title: Are You Being Served?

text: "Are You Being Served?" was a success in the UK audience ratings. The series was screened in Canada, New Zealand, Australia and the Republic of Ireland, and was aired in the Netherlands and Belgium with Dutch subtitles. The show was also broadcast in Israel and in the United States, where it gained a loyal following when PBS television stations began airing reruns of it in the mid-1980s, along with other British sitcoms. In 2004, it was ranked 20th in a television countdown of "Britain's Best Sitcom". It is regularly rebroadcast in the English-speaking world.


title: Are You Being Served?

text: The idea for the show came from Lloyd's brief period in the early 1950s working at Simpsons of Piccadilly, a clothing store which traded for over 60 years until its closing in 1999. The inspiration for the store has also been credited to the former Clements of Watford where the concept of the floor walker character Captain Peacock was devised.


title: Are You Being Served?

text: The pilot episode was created as part of the "Comedy Playhouse" series, although the BBC had originally chosen not to broadcast the programme. The pilot was used as a filler during the 1972 Summer Olympics when the coverage of the games was interrupted by the Munich massacre on 8 September 1972, leading to a full series being produced. The pilot episode was repeated before the first series began, on 14 March 1973. Although the first series was aired in the same timeslot as "Coronation Street" on ITV, consequently receiving relatively little attention, the repeats shown later in the year were much more successful.


title: Are You Being Served?

text: The show became a ratings hit and, after a successful 13-year run, "Are You Being Served?" came to an end on 1 April 1985.


title: Are You Being Served?

text: Of the original cast, only Frank Thornton, Mollie Sugden, John Inman, Wendy Richard and Nicholas Smith appeared in all 69 episodes. The same five later featured in the sequel sitcom, "Grace & Favour" (also known as "Are You Being Served? Again!"). The cast performed in character for a stage sketch on the BBC1 programme "Variety" on 19 June 1976.


title: Are You Being Served?

text: Although the pilot was produced in colour, the videotape was wiped in the 1970s, leaving only a 16mm black-and-white film telerecording, which was made for international syndication to countries where colour television broadcasts had not been adopted. In 2009, the pilot episode was restored to colour using the colour recovery technique previously used for the "Dad's Army" episode "Room at the Bottom". The restored colour version was first shown on BBC2 on 1 January 2010 as part of a special "Are You Being Served?" night. As of 2022, the colour version has yet to be released on DVD or Blu Ray.


title: Are You Being Served?

text: The theme song, written by the show's co-writer David Croft and composer Ronnie Hazlehurst, consists of an imaginary lift girl, voiced by Stephanie Gathercole, also Mr Rumbold's first secretary, (r.n. Reeve), (1944-2011), announcing each floor over the "musique concrète" sounds of a cash register (which effectively serves as the only percussion instrument) and a simple musical accompaniment.


title: Are You Being Served?

text: The 1977 "Are You Being Served?" film has a different version of the theme song which is longer, in a different key and without the floor announcements. A remix of the theme was released in 1996 by a dance act calling itself "Grace Brothers", and featured vocal samples of John Inman and Frank Thornton.


title: Are You Being Served?

text: There is a homage to the theme song in the Ladytron song "Paco!" from the album "604", and New Zealand band Minuit's "I hate guns". A lugubrious version of the theme song is featured on the album "The Ape of Naples" by the experimental music group Coil. The theme song has also been covered by Australian band Regurgitator on their 1999 album "...art". Pop singer Jamelia's song "Window Shopping" (from her 2006 album "Walk with Me") begins with a sample of the familiar cash register sound effect as well as Mrs Slocombe's voice inquiring, "Good morning, Mr Grainger; are you free?"


title: Are You Being Served?

text: The series was shown in the United States on PBS stations and on BBC America, as well as in many Commonwealth nations around the world. PBS first began airing it (on 24 stations) in 1987, and viewership steadily climbed as more stations carried it. By the early 1990s, it had gained such a loyal following that American viewers of the show formed fan clubs and were in large attendance wherever cast members made guest appearances.


title: Are You Being Served?

text: "Are You Being Served?" aired in Canada in prime time on Global Television Network in the mid 1980s and late night on YTV. The show aired on Saturday evening prime time from the mid 1980s to late 1990s. It was also available to Canadian viewers from most border PBS stations in the United States.


title: Are You Being Served?

text: The series was successfully screened in Australia. It began on ABC Television in 1974 and was repeated by ABC in Australia several times. By 1978, the rights to early episodes had been acquired by the commercial Seven Network who gained a larger audience than it had received on the ABC. "Are You Being Served?" was ranked as the top-rated show on Australian television for 1978, being watched by 2,255,000 people in five cities. New episodes were aired on ABC until 1984. After that, the last series was broadcast on the Seven Network.


title: Are You Being Served?

text: "Are You Being Served?" featured humour based on sexual innuendo, misunderstanding, mistaken identity, farce, and occasional slapstick. In addition, there were sight gags generated by outrageous costumes which the characters were sometimes required to wear for store promotions, and gaudy store displays sometimes featuring malfunctioning robotic mannequins. The show is remembered for its prolific use of double entendres.


title: Are You Being Served?

text: A key humorous base of the series was a parody of the British class system. This permeated a range of relationships and interactions, such as conversations between the maintenance men and sales personnel, or between sales staff and management. The episodes rarely featured locations outside the store. Characters rarely addressed each other by their first names, even after work, instead using their titles (commonly Mr, Mrs, Miss, or Captain).


title: Are You Being Served?

text: "Are You Being Served?" was initially broadcast from 1973 to 1985. Each series had between five and nine episodes. Counting the pilot episode, all episodes and specials from the series, and the film, the show ran for sixty-nine episodes and ten series. Each episode was self-contained, with no continuing story or theme throughout the series.


title: Are You Being Served?

text: In 1977, as for many other British sitcoms of the time, a feature film was released. The film version of "Are You Being Served?" followed the staff of Grace Brothers taking a package holiday together while the store is closed for redecoration, a loose adaptation of the play version from the year before. Set in the fictional resort of Costa Plonka, in Spain, the entire cast of the television series reprised their roles in the film. Reviews of the film were generally negative, with the "Monthly Film Bulletin" reviewer John Pym declaring, "The humour consists mainly of withering selection of patent British puns; an inflatable brassiere, some let's-insult-the-Germans jokes and a rickey thunder-box which bolts from the outside are thrown in for good measure."


title: Are You Being Served?

text: Buoyed by the huge success of the series in the United States, BBC America commissioned a special straight-to-VHS compilation in 1992. Running at 78 minutes, "The Best of Are You Being Served" featured newly-shot scenes of Mr Humphries reminiscing with his elderly mother, Annie, about his time working at Grace Brothers. Both roles were played by John Inman. The additional sequences were filmed in America, and directed by Don Hopfer.


title: Are You Being Served?

text: In 2016, a one-off revival episode was announced and filmed at dock10 studios. It was broadcast as part of BBC's Landmark Sitcom Season, a celebration of 60 years of television sitcoms. It was set in 1988 with the original characters, played by a new cast.


title: Are You Being Served?

text: Former "Only Fools and Horses" actor John Challis portrayed Captain Peacock; former "Coronation Street" actors Sherrie Hewson and Roy Barraclough were cast as Mrs Slocombe and Mr Grainger respectively, and comedian Arthur Smith as Mr Harman. Mr Humphries was portrayed by Jason Watkins, Miss Brahms by Niky Wardley, and Mr Rumbold by Justin Edwards. New characters introduced in the show included Young Mr Grace's grandson, also called Young Mr Grace, played by Mathew Horne; Miss Croft, named as a tribute to series co-creator David Croft, played by Jorgie Porter; and newcomer Mr Conway, played by Kayode Ewumi. The episode was written by Derren Litten. The BBC issued a press release saying: "It's 1988 and Young Mr Grace is determined to drag Grace Brothers into, well 1988, but he has a problem on his hands. Mr Humphries, Captain Peacock, Mr Rumbold and Mrs Slocombe all seem to be stuck in another era. A new member of staff, Mr Conway, joins the team but will he help shake things up or will he just put a pussy amongst the pigeons?"


title: Are You Being Served?

text: The episode was aired in August 2016 to universally poor reviews for both the writing and the acting. No further episodes were commissioned.


title: Are You Being Served?

text: Almost immediately after the cancellation of "Are You Being Served?" in 1985, the cast began suggesting a spin-off to Jeremy Lloyd and David Croft. Though all felt the department store format was exhausted, it was suggested the characters could be moved to a new location. In 1992, most of the original cast reunited for "Grace & Favour" (known as "Are You Being Served Again!" in the United States and Canada). The new series followed the characters after Young Mr Grace's death, when they are forced to run a hotel in a dilapidated manor house that was purchased using their pension fund. "Grace & Favour" ran for two series.


title: Are You Being Served?

text: In the summer of 1976, a stage adaptation of "Are You Being Served?" ran at the Winter Gardens in Blackpool. Directed by Robert Redfarn, John Inman, Mollie Sugden, Frank Thornton, Wendy Richard, and Nicholas Smith reprised their characters from the television show while the characters of Mr Lucas, Mr Grainger, and Mr Mash were recast. The play had basically the same plot as the film version which would debut the next year, though Young Mr Grace's role was omitted entirely and Mr Mash had less to do than Mr Harman in the film. Reviews for the play were mixed; a writer for the Blackpool "Diarist of the Stage" declared it the funniest show he had seen in thirty years, while Michael Leapman from "The Times" declared the play to be worthless except for the final line, though he admitted he had never seen the television show. The play has occasionally been run at other theatres since.


title: Are You Being Served?

text: In 1979, Garry Marshall, in the midst of success producing and directing "Happy Days" and its spin-offs, produced a pilot for an American version of "Are You Being Served?", "Beane's of Boston", remaking the episode, "German Week" for the television pilot.


title: Are You Being Served?

text: At the time, Americanised versions of British series, including "Three's Company", "All in the Family", and "Sanford and Son" were doing well in the ratings, and Marshall hoped to capitalise on this with his script for the production.


title: Are You Being Served?

text: Most of the characters were substantially similar to those of the UK version, with slight name changes in some instances. The one significant difference was that the Rumbold character was replaced by “Franklin Beane” (George O’Hanlan, Jr.), the young nephew of the proprietor who has recently been put in charge of the department.


title: Are You Being Served?

text: Jeremy Lloyd's "Laugh-In" partner, Alan Sues, was cast as Mr Humphries, a decision Lloyd regretted, saying Sues had been miscast.


title: Are You Being Served?

text: Other cast included future "Magnum PI" star John Hillerman as Mr Peacock, Charlotte Rae as Mrs Slocombe, Lorna Patterson as Miss Brahms, Tom Poston as Mr. Beane (the Mr. Grace equivalent), Larry Bishop as Mr. Lucas, Morgan Farley as Mr. Granger, and Don Bexley as Mr. Johnson (the Mash/Harman role).


title: Are You Being Served?

text: An Australian adaptation, also called "Are You Being Served?", ran for two series and sixteen episodes from 1980 to 1981 on Network Ten. It starred John Inman as Mr Humphries, who travels to Australia on loan from Grace Brothers to work for the Grace brothers' cousin, Mr Bone at his department store, Bone Brothers. Renamed versions of characters from the original series rounded out the cast including June Bronhill as Mrs Crawford, a copy of Mrs Slocombe, and Reg Gillam as Captain Wagstaff, a copy of Captain Peacock. Jeremy Lloyd adapted episodes for the show from his own scripts from the British "Are You Being Served", drawing from the then-new episodes of the seventh series for series one of the Australian version, and a selection of older episodes for series two. Lloyd would later say he hated the process of adapting the episodes, which were mostly left intact with the exception of some topical jokes, which were changed or deleted.


title: Are You Being Served?

text: The TROS, the Dutch broadcaster that showed "AYBS?" in the Netherlands, invited over the key faces of the original cast twice to reprise their characters on Dutch television (albeit not for a full, half-hour episode). First in 1976, Dutch comedian André van Duin entered a shop and ran into Mr Humphries, Miss Brahms and Mrs Slocombe. A different special was made 1994, on the occasion of the 30 years jubilee of the TROS. This time, the search was for a replacement for Mrs Slocombe, with Mollie Sugden, John Inman, Frank Thornton, Wendy Richard, and Trevor Bannister all reprising their roles. In 1985 John Inman also assisted in character as co-presenter for a quiz.


title: Are You Being Served?

text: The series gained much of its popularity with TV viewers by "pushing the envelope" through its deliberate-yet-subtle use of risqué visual gags, innuendo-infused dialogue and cleverly-disguised sophomoric humour. These comical devices also attracted some mild criticism, in part for relying on sexual stereotypes and double entendres – e.g., Mrs Slocombe discussing her cat: "Animals are very psychic; the least sign of danger and my pussy's hair stands on end".


title: Are You Being Served?

text: John Inman's portrayal of Humphries' over-the-top antics and sharp-tongued, witty responses, along with his trademark catch-phrase "I'm free!", were enthusiastically embraced by many audience members, and the character evolved into a gay icon in popular culture. Despite this, Inman pointed out that Mr Humphries' true sexual orientation was never explicitly stated in the series, and David Croft said in an interview that the character was not homosexual, but "just a mother's boy". In an episode of the spin-off "Grace & Favour", the character is further described as neither a "woman's man" nor a "man's man" and as being "in limbo".


title: Are You Being Served?

text: Seven early episodes were novelised for a book, written by Jeremy Lloyd, called "Are You Being Served? – Camping in and other Fiascos". This was written in 1976, and republished in 1997 by "KQED Books". The seven episodes featured are "Camping In", "Up Captain Peacock", "Wedding Bells", "His and Hers", "Coffee Morning", "The Hand of Fate" and "The Clock".


title: Are You Being Served?

text: In 1995, KQED Books published "Are You Being Served – The Inside Story" by Adrian Rigelsford, Anthony Brown, and Geoff Tibbals, with a foreword by Jeremy Lloyd, and sub-titled: "The Inside Story of Britain's Funniest – and Public Television's Favorite – Comedy Series". In 212 pages, the book's six chapters cover: The Cast of Characters, Behind the Scenes, The Episodes, The Spin-offs, Trivia Quiz, and Glossary. .


title: Are You Being Served?

text: In 1999, "I'm Free! The Complete Are You Being Served?", a guide to the series, was published by Orion Books. It was written by Richard Webber, with contributions from David Croft and Jeremy Lloyd.


title: Are You Being Served?

text: A board game was also produced in the 1970s. Players moved round a board resembling the shop floor to purchase one item from each of the four counters and leave the store, before their opponents and without going over budget.


title: Are You Being Served?

text: All episodes exist in the BBC Archives. All ten series, including a black and white version of the pilot episode, and all five Christmas specials from those years, as well as both series of "Grace & Favour" are now available on DVD in the UK (Region 2). The "Are You Being Served?" film was released in 2002. A colour-restored version of the original pilot episode has yet to be released commercially.


title: Are You Being Served?

text: All ten series, as well as both series of "Grace & Favour" (in packaging titled "Are You Being Served? Again!") and the film are available on DVD in Region 1 (North America).


title: Are You Being Served?

text: All ten series, as well as both series of "Grace & Favour" and the film have been released in Australia (Region 4).


title: Are You Being Served?

text: A DVD titled "Are You Being Served? – Best of The Early Years" and "Are You Being Served? Christmas Specials" have also been released.


title: Jordan Masterson

text: Jordan Masterson (born April 9, 1986) is an American actor. He played Zeb, a five-year-old boy, in Danielle Steel's 1993 TV adaptation "Star". He is perhaps best known for his role as Mark in the 2005 film "The 40-Year-Old Virgin" and his recurring role as Dumptruck in ABC Family comedy-drama series "Greek". He co-starred as Ryan Vogelson in "Last Man Standing" on ABC (2012-2017) and FOX (2018-2021).


title: Jordan Masterson

text: He also guest starred in the television series "Grounded for Life", "George Lopez", "Las Vegas", "7th Heaven", "", "Without a Trace" and "How I Met Your Mother".


title: Jordan Masterson

text: Masterson is the brother of actress Alanna Masterson and the maternal half-brother of actors Danny Masterson and Christopher Masterson. His cousin is Angus T. Jones.


title: Jordan Masterson

text: Masterson was born on April 9, 1986 in Dunedin, Florida. His mother, Carol Masterson, is also his manager, and his father, Joe Reaiche, who is of Lebanese descent, is a former National Rugby League NRL Professional player.


title: Jordan Masterson

text: He is the younger half-brother of actors Danny Masterson and Christopher Masterson. (He guest starred on both of his half-brothers' respective series, "That '70s Show" and "Malcolm in the Middle".) He is the older brother of actress Alanna Masterson.


title: Jordan Masterson

text: Along with his mother, sister, and half-brothers, Masterson is a member of the Church of Scientology.


title: 1992 United Kingdom general election

text: The 1992 United Kingdom general election was held on Thursday 9 April 1992, to elect 651 members to the House of Commons. The election resulted in the fourth consecutive victory for the Conservative Party since 1979 and would be the last time that the Conservatives would win an overall majority at a general election until 2015. It was also the last general election to be held on a day which did not coincide with any local elections until 2017. This election result took many by surprise, as opinion polling leading up to the election day had shown the Labour Party, under leader Neil Kinnock, consistently, if narrowly, ahead.


title: 1992 United Kingdom general election

text: John Major had won the Conservative Party leadership election in November 1990 following the resignation of Margaret Thatcher. During his first term leading up to the 1992 election he oversaw the British involvement in the Gulf War, introduced legislation to replace the unpopular Community Charge with Council Tax, and signed the Maastricht Treaty. Britain was sliding into its second recession in a decade at the time of Major's appointment.


title: 1992 United Kingdom general election

text: Opinion polls in the run-up to the election had suggested that it would end in a hung parliament or a narrow Labour majority. The fact that it produced a Conservative majority meant that it was one of the most dramatic and memorable elections in the UK since the end of the Second World War.


title: 1992 United Kingdom general election

text: The Conservative Party received what remains the largest number of votes at a United Kingdom general election in British history, breaking the previous record set by the Labour Party in 1951. Former Conservative Leader and Prime Minister Margaret Thatcher, Former Labour Party leader Michael Foot, former SDP leader David Owen, three former Chancellors of the Exchequer, Denis Healey, Geoffrey Howe and Nigel Lawson, former Home Secretary Merlyn Rees, Francis Maude, Norman Tebbit, Rosie Barnes, Sinn Féin leader Gerry Adams and Speaker of the House of Commons Bernard Weatherill left the House of Commons after this election, though Maude and Adams returned at the next election. Future Conservative Leader Iain Duncan Smith was elected to parliament in this election.


title: 1992 United Kingdom general election

text: The Conservatives had been re-elected in a landslide at the 1987 general election under the leadership of Margaret Thatcher, who had led the party back into power in 1979 and won a landslide majority in 1983, but her popularity and that of her government sharply declined due to internal divisions in the party and the unpopular Community Charge (also known as the 'poll tax'), as well as the fact that Britain was sliding into recession in the run-up to her resignation in November 1990.


title: 1992 United Kingdom general election

text: Labour began to lead the Conservatives in the opinion polls by as much as 20 percentage points. Thatcher resigned following the party leadership ballot in November 1990, initiated by Michael Heseltine, and was replaced by her Chancellor of the Exchequer John Major. This was well received by the public; Labour lost some momentum as it reduced the impact of their calls for "Time for a Change".


title: 1992 United Kingdom general election

text: On 16 January 1991, Operation Desert Storm began the Gulf War, the Major ministry's first foreign affairs crisis. The quick and successful outcome on the conflict led to a boost in opinion polls for Major, in spite of the deepening recession and rising unemployment. Another boost in the polls for Major was his announcement that the unpopular community charge (poll tax) would be replaced with the Council Tax. The Labour opposition made repeated calls for a general election to be held during 1991, but Major resisted these calls.


title: 1992 United Kingdom general election

text: As 1992 dawned, the recession had still not ended, unemployment now topped 2.5 million and the election loomed, with most opinion polls suggested that the election would produce a hung parliament or a narrow Labour majority, although the lead in the polls had shifted between Tory and Labour on several occasions since November 1990.


title: 1992 United Kingdom general election

text: Parliament was due to expire no later than 16 June 1992. Major called the election on 11 March, as was widely expected, the day after Chancellor of the Exchequer Norman Lamont had delivered the Budget. The Conservatives maintained strong support in many newspapers, especially "The Sun", which ran a series of anti-Labour articles that culminated on election day with a front-page headline which urged "the last person to leave Britain" to "turn out the lights" if Labour won the election.


title: 1992 United Kingdom general election

text: The 50th Parliament of the United Kingdom sat for the last time on Monday 16 March, being dissolved on the same day.


title: 1992 United Kingdom general election

text: Under the leadership of Neil Kinnock, the Labour Party had undergone further developments and alterations since its 1987 general election defeat. Labour entered the campaign confident, with most opinion polls showing a slight Labour lead that if maintained suggested a hung parliament, with no single party having an overall majority.


title: 1992 United Kingdom general election

text: The parties campaigned on the familiar grounds of taxation and health care. Major became known for delivering his speeches while standing on an upturned soapbox during public meetings. Immigration was also an issue, with Home Secretary Kenneth Baker making a controversial speech stating that, under Labour, the floodgates would be opened for immigrants from developing countries. Some speculated that this was a bid by the Conservatives to shore up its support amongst its white working-class supporters. The Conservatives also pounded the Labour Party over the issue of taxation, producing a memorable poster entitled "Labour's Double-Whammy", showing a boxer wearing gloves marked "tax rises" and "inflation".


title: 1992 United Kingdom general election

text: An early setback for Labour came in the form of the "War of Jennifer's Ear" controversy, which questioned the truthfulness of a Labour party election broadcast concerning National Health Service (NHS) waiting lists.


title: 1992 United Kingdom general election

text: Labour seemingly recovered from the NHS controversy, and opinion polls on 1 April (dubbed "Red Wednesday") showed a clear Labour lead. But the lead fell considerably in the following day's polls. Observers blamed the decline on the Labour Party's triumphalist "Sheffield Rally", an enthusiastic American-style political convention at the Sheffield Arena, where Neil Kinnock famously cried out "We're all right!" three times. However, some analysts and participants in the campaign believed it actually had little effect, with the event only receiving widespread attention after the election.


title: 1992 United Kingdom general election

text: This was the first general election for the newly formed Liberal Democrats, a party formed by the formal merger of the SDP-Liberal Alliance following the 1987 general election. Its formation had not been without its problems, but under the strong leadership of Paddy Ashdown, who proved to be a likeable and candid figure, the party went into the election ready to win votes and seats. They focused on education throughout the campaign, as well as a promise on reforming the voting system.


title: 1992 United Kingdom general election

text: The weather was largely dull for most of the campaign, but sunny conditions on 9 April may have been a factor in the high turnout.


title: 1992 United Kingdom general election

text: In Scotland, the Scottish National Party (SNP) hoped for a major electoral breakthrough in 1992 and had run a hard independence campaign with "Free by '93" as their slogan, urging voters to back a party which would deliver Scottish independence from the United Kingdom. Although the party increased its total vote by 50% compared to 1987, they only held onto the three seats they had won at the previous election. They lost Glasgow Govan, which their deputy leader Jim Sillars had taken from Labour in a by-election in 1988. Sillars quit active politics after the general election with a parting shot at the Scottish electorate as being "ninety-minute patriots", referring to their supporting the Scotland national football team only during match time.


title: 1992 United Kingdom general election

text: The election also saw a small change in Northern Ireland: the Conservatives organised and stood candidates in the constituent country for the first time since the Ulster Unionist Party had broken with them in 1972 over the Sunningdale Agreement. Although they won no seats, their best result was Laurence Kennedy achieving over 14,000 votes to run second to James Kilfedder in North Down.


title: 1992 United Kingdom general election

text: Former prime minister Margaret Thatcher stepped down at the general election, as did former cabinet minister Norman Tebbit, Labour veteran Denis Healey, former Conservative chancellor Nigel Lawson, Geoffrey Howe, former Labour leader Michael Foot, former SDP leader David Owen, Merlyn Rees, then-Speaker Bernard Weatherill, former Conservative Party chairman Cecil Parkinson, John Wakeham, Nicholas Ridley and Peter Morrison. Alan Clark also retired from Parliament, though he returned in 1997 as MP for Kensington and Chelsea, only to die two years later.


title: 1992 United Kingdom general election

text: In a move later described in "The Observer" as appalling to its City readership, the "Financial Times" endorsed the Labour Party in this general election.


title: 1992 United Kingdom general election

text: Almost every poll leading up to polling day predicted either a hung parliament with Labour the largest party, or a small Labour majority of around 19 to 23. Polls on the last few days before the country voted predicted a very slim Labour majority. Of the 50 opinion polls published during the election campaign period, 38 suggested Labour had a narrow but clear lead. After the polls closed, the BBC and ITV exit polls still predicted that there would be a hung parliament and "that the Conservatives would only just get more seats than Labour".


title: 1992 United Kingdom general election

text: With opinion polls at the end of the campaign showing Labour and the Conservatives neck and neck, the actual election result was a surprise to many in the media and in polling organisations. The apparent failure of the opinion polls to come close to predicting the actual result led to an inquiry by the "Market Research Society", and would eventually result in the creation of the British Polling Council a decade later. Following the election, most opinion polling companies changed their methodology in the belief that a 'Shy Tory factor' affected the polling.


title: 1992 United Kingdom general election

text: The election turnout of 77.67% was the highest in 18 years. There was an overall Labour swing of 2.2%, which widened the gap between Labour and the Liberal Democrats. Although the percentage of Conservative votes was only 0.3% down on 1987, the Conservative overall majority in the House of Commons was reduced from 102 to 21. This number was reduced progressively during the course of Major's term in office due to defections of MPs to other parties, by-election defeats, and for a time in 1994–95 the suspension of the Conservative whip for some MPs who voted against the government on its European policyby 1996, the Conservative majority had been reduced to just 1 seat, and they were in a minority going into 1997 until the 1997 general election. The Conservatives in 1992 received 14,093,007 votes, the highest total of votes for any political party in any UK general election, beating the previous largest total vote of 13.98 million achieved by Labour in 1951 (although this was from a smaller electorate and represented a higher vote share). Nine government ministers lost their seats in 1992, including party chairman Chris Patten.


title: 1992 United Kingdom general election

text: "The Sun"s analysis of the election results was headlined "It's The Sun Wot Won It", though in his testimony to the April 2012 Leveson Inquiry, Rupert Murdoch claimed that the "infamous" headline was "both tasteless and wrong".


title: 1992 United Kingdom general election

text: Tony Blair also accepted this theory of Labour's defeat and put considerable effort into securing "The Sun"s support for New Labour, both as Leader of the Opposition before the 1997 general election and as Prime Minister afterwards.


title: 1992 United Kingdom general election

text: Steve Richards notes that one theory for Labour's defeat relates to Kinnock seeming triumphalist, "overconfident and cocky" at a major Labour Party election rally in Sheffield. At the time of the event polls suggested Labour was well ahead of the Conservatives. Richards argues the rally "acquired a mythological status as fatal event" after Labour's defeat, but considers this theory to be "a red herring". He notes that prior to the result of the election becoming known, "there was no suggestion that Kinnock had made a terrible blunder" at the event. Indeed, Richards notes that the BBC's political editor John Cole had indicated he had been impressed in his live reporting of the rally which Cole compared with similar events held by President Kennedy . Richards concluded that the party would have lost the election even if there had been no Sheffield Rally.


title: 1992 United Kingdom general election

text: This election continued the Conservatives' decline in Northern England, with Labour regaining many seats they had not held since 1979. The Conservatives also began to lose support in the Midlands, but achieved a slight increase in their vote in Scotland, where they had a net gain of one seat. Labour and Plaid Cymru strengthened in Wales, with Conservative support declining. However, in the South East, South West, London and Eastern England the Conservative vote held up, leading to few losses there: many considered Basildon to be indicative of a nouveau riche working-class element, referred to as Essex man, voting strongly Conservative. This election is the most recent in which the Conservatives won more seats than Labour in Greater London, at 48 to 35; in the 1997 election, the Conservatives would win only 11.


title: 1992 United Kingdom general election

text: For the Liberal Democrats their first election campaign was a reasonable success; the party had worked itself up from a "low base" during its troubled creation and come out relatively unscathed.


title: 1992 United Kingdom general election

text: It was Labour's second general election defeat under leader Neil Kinnock and deputy leader Roy Hattersley. Both resigned soon after the election, and were succeeded by John Smith and Margaret Beckett respectively.


title: 1992 United Kingdom general election

text: Sitting MPs Dave Nellist, Terry Fields, Ron Brown, John Hughes and Syd Bidwell, who had been expelled or deselected by the Labour Party and stood as independents, were all defeated, although in Nellist's case only very narrowly. Tommy Sheridan, fighting the election from prison, polled 19%.


title: 1992 United Kingdom general election

text: "All parties with more than 500 votes shown. Plaid Cymru result includes votes for Green/Plaid Cymru Alliance."


title: 1992 United Kingdom general election

text: Coverage was, according to the "Radio Times", supposed to end at 04:00 on Friday morning, but was extended.


title: 1992 United Kingdom general election

text: The BBC began construction of the Election 92 studio in October 1990, completing it in February 1991, due to speculation that an early election may be called in 1991. Rehearsals were held in the event of a Conservative and Labour victory.


title: 1992 United Kingdom general election

text: Although the election was not part of the storyline, there was much background chanting and campaigning in the BBC television soap opera "EastEnders".


title: 1992 United Kingdom general election

text: On ITV, ITN produced their election night coverage from their studios in London, with Jon Snow anchoring the coverage from 22:00 until 06:00. They continued their daytime coverage on Friday 10 April from 09:25 until 15:25. Breakfast coverage of the election results were provided by TV-am, the ITV breakfast franchise, from 06:00 until 09:25, who were producing their third and final general election special.


title: CPU cache

text: A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, which stores copies of the data from frequently used main memory locations. Most CPUs have a hierarchy of multiple cache levels (L1, L2, often L3, and rarely even L4), with different instruction-specific and data-specific caches at level 1. The cache memory is typically implemented with static random-access memory (SRAM), in modern CPUs by far the largest part of them by chip area, but SRAM is not always used for all levels (of I- or D-cache), or even any level, sometimes some latter or all levels are implemented with eDRAM.


title: CPU cache

text: Other types of caches exist (that are not counted towards the "cache size" of the most important caches mentioned above), such as the translation lookaside buffer (TLB) which is part of the memory management unit (MMU) which most CPUs have.


title: CPU cache

text: When trying to read from or write to a location in the main memory, the processor checks whether the data from that location is already in the cache. If so, the processor will read from or write to the cache instead of the much slower main memory.


title: CPU cache

text: Early examples of CPU caches include the Atlas 2 and the IBM System/360 Model 85 in the 1960s. The first CPUs that used a cache had only one level of cache; unlike later level 1 cache, it was not split into L1d (for data) and L1i (for instructions). Split L1 cache started in 1976 with the IBM 801 CPU, became mainstream in the late 1980s, and in 1997 entered the embedded CPU market with the ARMv5TE. In 2015, even sub-dollar SoC split the L1 cache. They also have L2 caches and, for larger processors, L3 caches as well. The L2 cache is usually not split and acts as a common repository for the already split L1 cache. Every core of a multi-core processor has a dedicated L1 cache and is usually not shared between the cores. The L2 cache, and higher-level caches, may be shared between the cores. L4 cache is currently uncommon, and is generally on (a form of) dynamic random-access memory (DRAM), rather than on static random-access memory (SRAM), on a separate die or chip (exceptionally, the form, eDRAM is used for all levels of cache, down to L1). That was also the case historically with L1, while bigger chips have allowed integration of it and generally all cache levels, with the possible exception of the last level. Each extra level of cache tends to be bigger and optimized differently.


title: CPU cache

text: Caches (like for RAM historically) have generally been sized in powers of: 2, 4, 8, 16 etc. KiB; when up to MiB sizes (i.e. for larger non-L1), very early on the pattern broke down, to allow for larger caches without being forced into the doubling-in-size paradigm, with e.g. Intel Core 2 Duo with 3 MiB L2 cache in April 2008. Much later however for L1 sizes, that still only count in small number of KiB, however IBM zEC12 from 2012 is an exception, to gain unusually large 96 KiB L1 data cache for its time, and e.g. the IBM z13 having a 96 KiB L1 instruction cache (and 128 KiB L1 data cache), and Intel Ice Lake-based processors from 2018, having 48 KiB L1 data cache and 48 KiB L1 instruction cache. In 2020, some Intel Atom CPUs (with up to 24 cores) have (multiple of) 4.5 MiB and 15 MiB cache sizes.


title: CPU cache

text: Data is transferred between memory and cache in blocks of fixed size, called "cache lines" or "cache blocks". When a cache line is copied from memory into the cache, a cache entry is created. The cache entry will include the copied data as well as the requested memory location (called a tag).


title: CPU cache

text: When the processor needs to read or write a location in memory, it first checks for a corresponding entry in the cache. The cache checks for the contents of the requested memory location in any cache lines that might contain that address. If the processor finds that the memory location is in the cache, a cache hit has occurred. However, if the processor does not find the memory location in the cache, a cache miss has occurred. In the case of a cache hit, the processor immediately reads or writes the data in the cache line. For a cache miss, the cache allocates a new entry and copies data from main memory, then the request is fulfilled from the contents of the cache.


title: CPU cache

text: To make room for the new entry on a cache miss, the cache may have to evict one of the existing entries. The heuristic it uses to choose the entry to evict is called the replacement policy. The fundamental problem with any replacement policy is that it must predict which existing cache entry is least likely to be used in the future. Predicting the future is difficult, so there is no perfect method to choose among the variety of replacement policies available. One popular replacement policy, least-recently used (LRU), replaces the least recently accessed entry.


title: CPU cache

text: Marking some memory ranges as non-cacheable can improve performance, by avoiding caching of memory regions that are rarely re-accessed. This avoids the overhead of loading something into the cache without having any reuse. Cache entries may also be disabled or locked depending on the context.


title: CPU cache

text: If data is written to the cache, at some point it must also be written to main memory; the timing of this write is known as the write policy. In a write-through cache, every write to the cache causes a write to main memory. Alternatively, in a write-back or copy-back cache, writes are not immediately mirrored to the main memory, and the cache instead tracks which locations have been written over, marking them as dirty. The data in these locations is written back to the main memory only when that data is evicted from the cache. For this reason, a read miss in a write-back cache may sometimes require two memory accesses to service: one to first write the dirty location to main memory, and then another to read the new location from memory. Also, a write to a main memory location that is not yet mapped in a write-back cache may evict an already dirty location, thereby freeing that cache space for the new memory location.


title: CPU cache

text: There are intermediate policies as well. The cache may be write-through, but the writes may be held in a store data queue temporarily, usually so multiple stores can be processed together (which can reduce bus turnarounds and improve bus utilization).


title: CPU cache

text: Cached data from the main memory may be changed by other entities (e.g., peripherals using direct memory access (DMA) or another core in a multi-core processor), in which case the copy in the cache may become out-of-date or stale. Alternatively, when a CPU in a multiprocessor system updates data in the cache, copies of data in caches associated with other CPUs become stale. Communication protocols between the cache managers that keep the data consistent are known as cache coherence protocols.


title: CPU cache

text: Cache performance measurement has become important in recent times where the speed gap between the memory performance and the processor performance is increasing exponentially. The cache was introduced to reduce this speed gap. Thus knowing how well the cache is able to bridge the gap in the speed of processor and memory becomes important, especially in high-performance systems. The cache hit rate and the cache miss rate play an important role in determining this performance. To improve the cache performance, reducing the miss rate becomes one of the necessary steps among other steps. Decreasing the access time to the cache also gives a boost to its performance.


title: CPU cache

text: The time taken to fetch one cache line from memory (read latency due to a cache miss) matters because the CPU will run out of things to do while waiting for the cache line. When a CPU reaches this state, it is called a stall. As CPUs become faster compared to main memory, stalls due to cache misses displace more potential computation; modern CPUs can execute hundreds of instructions in the time taken to fetch a single cache line from main memory.


title: CPU cache

text: Various techniques have been employed to keep the CPU busy during this time, including out-of-order execution in which the CPU attempts to execute independent instructions after the instruction that is waiting for the cache miss data. Another technology, used by many processors, is simultaneous multithreading (SMT), which allows an alternate thread to use the CPU core while the first thread waits for required CPU resources to become available.


title: CPU cache

text: The placement policy decides where in the cache a copy of a particular entry of main memory will go. If the placement policy is free to choose any entry in the cache to hold the copy, the cache is called "fully associative". At the other extreme, if each entry in the main memory can go in just one place in the cache, the cache is "direct-mapped". Many caches implement a compromise in which each entry in the main memory can go to any one of N places in the cache, and are described as N-way set associative. For example, the level-1 data cache in an AMD Athlon is two-way set associative, which means that any particular location in main memory can be cached in either of two locations in the level-1 data cache.


title: CPU cache

text: Choosing the right value of associativity involves a trade-off. If there are ten places to which the placement policy could have mapped a memory location, then to check if that location is in the cache, ten cache entries must be searched. Checking more places takes more power and chip area, and potentially more time. On the other hand, caches with more associativity suffer fewer misses (see conflict misses), so that the CPU wastes less time reading from the slow main memory. The general guideline is that doubling the associativity, from direct mapped to two-way, or from two-way to four-way, has about the same effect on raising the hit rate as doubling the cache size. However, increasing associativity more than four does not improve hit rate as much, and are generally done for other reasons (see virtual aliasing). Some CPUs can dynamically reduce the associativity of their caches in low-power states, which acts as a power-saving measure.


title: CPU cache

text: In this cache organization, each location in the main memory can go in only one entry in the cache. Therefore, a direct-mapped cache can also be called a "one-way set associative" cache. It does not have a placement policy as such, since there is no choice of which cache entry's contents to evict. This means that if two locations map to the same entry, they may continually knock each other out. Although simpler, a direct-mapped cache needs to be much larger than an associative one to give comparable performance, and it is more unpredictable. Let be block number in cache, be block number of memory, and be number of blocks in cache, then mapping is done with the help of the equation .


title: CPU cache

text: If each location in the main memory can be cached in either of two locations in the cache, one logical question is: "which one of the two?" The simplest and most commonly used scheme, shown in the right-hand diagram above, is to use the least significant bits of the memory location's index as the index for the cache memory, and to have two entries for each index. One benefit of this scheme is that the tags stored in the cache do not have to include that part of the main memory address which is implied by the cache memory's index. Since the cache tags have fewer bits, they require fewer transistors, take less space on the processor circuit board or on the microprocessor chip, and can be read and compared faster. Also LRU is especially simple since only one bit needs to be stored for each pair.


title: CPU cache

text: One of the advantages of a direct-mapped cache is that it allows simple and fast speculation. Once the address has been computed, the one cache index which might have a copy of that location in memory is known. That cache entry can be read, and the processor can continue to work with that data before it finishes checking that the tag actually matches the requested address.


title: CPU cache

text: The idea of having the processor use the cached data before the tag match completes can be applied to associative caches as well. A subset of the tag, called a "hint", can be used to pick just one of the possible cache entries mapping to the requested address. The entry selected by the hint can then be used in parallel with checking the full tag. The hint technique works best when used in the context of address translation, as explained below.


title: CPU cache

text: Other schemes have been suggested, such as the "skewed cache", where the index for way 0 is direct, as above, but the index for way 1 is formed with a hash function. A good hash function has the property that addresses which conflict with the direct mapping tend not to conflict when mapped with the hash function, and so it is less likely that a program will suffer from an unexpectedly large number of conflict misses due to a pathological access pattern. The downside is extra latency from computing the hash function. Additionally, when it comes time to load a new line and evict an old line, it may be difficult to determine which existing line was least recently used, because the new line conflicts with data at different indexes in each way; LRU tracking for non-skewed caches is usually done on a per-set basis. Nevertheless, skewed-associative caches have major advantages over conventional set-associative ones.


title: CPU cache

text: A true set-associative cache tests all the possible ways simultaneously, using something like a content-addressable memory. A pseudo-associative cache tests each possible way one at a time. A hash-rehash cache and a column-associative cache are examples of a pseudo-associative cache.


title: CPU cache

text: In the common case of finding a hit in the first way tested, a pseudo-associative cache is as fast as a direct-mapped cache, but it has a much lower conflict miss rate than a direct-mapped cache, closer to the miss rate of a fully associative cache.


title: CPU cache

text: Comparing with a direct-mapped cache, a set associative cache has a reduced number of bits for its cache set index that maps to a cache set, where multiple ways or blocks stays, such as 2 blocks for a 2-way set associative cache and 4 blocks for a 4-way set associative cache. Comparing with a direct mapped cache, the unused cache index bits become a part of the tag bits. For example, a 2-way set associative cache contributes 1 bit to the tag and a 4-way set associative cache contributes 2 bits to the tag. The basic idea of the multicolumn cache is to use the set index to map to a cache set as a conventional set associative cache does, and to use the added tag bits to index a way in the set. For example, in a 4-way set associative cache, the two bits are used to index way 00, way 01, way 10, and way 11, respectively. This double cache indexing is called a “major location mapping”, and its latency is equivalent to a direct-mapped access. Extensive experiments in multicolumn cache design shows that the hit ratio to major locations is as high as 90%. If cache mapping conflicts with a cache block in the major location, the existing cache block will be moved to another cache way in the same set, which is called “selected location”. Because the newly indexed cache block is a most recently used (MRU) block, it is placed in the major location in multicolumn cache with a consideration of temporal locality. Since multicolumn cache is designed for a cache with a high associativity, the number of ways in each set is high; thus, it is easy find a selected location in the set. A selected location index by an additional hardware is maintained for the major location in a cache block.


title: CPU cache

text: Multicolumn cache remains a high hit ratio due to its high associativity, and has a comparable low latency to a direct-mapped cache due to its high percentage of hits in major locations. The concepts of major locations and selected locations in multicolumn cache have been used in several cache designs in ARM Cortex R chip, Intel’s way-predicting cache memory, IBM’s reconfigurable multi-way associative cache memory, and Oracle’s dynamic cache replacement way selection based on address tab bits.


title: CPU cache

text: The "data block" (cache line) contains the actual data fetched from the main memory. The "tag" contains (part of) the address of the actual data fetched from the main memory. The flag bits are discussed below.


title: CPU cache

text: The "size" of the cache is the amount of main memory data it can hold. This size can be calculated as the number of bytes stored in each data block times the number of blocks stored in the cache. (The tag, flag and error correction code bits are not included in the size, although they do affect the physical area of a cache.)


title: CPU cache

text: An effective memory address which goes along with the cache line (memory block) is split (MSB to LSB) into the tag, the index and the block offset.


title: CPU cache

text: The index describes which cache set that the data has been put in. The index length is formula_1 bits for cache sets.


title: CPU cache

text: The block offset specifies the desired data within the stored data block within the cache row. Typically the effective address is in bytes, so the block offset length is formula_2 bits, where is the number of bytes per data block.


title: CPU cache

text: The tag contains the most significant bits of the address, which are checked against all rows in the current set (the set has been retrieved by index) to see if this set contains the requested address. If it does, a cache hit occurs. The tag length in bits is as follows:


title: CPU cache

text: The original Pentium 4 processor had a four-way set associative L1 data cache of 8 KiB in size, with 64-byte cache blocks. Hence, there are 8 KiB / 64 = 128 cache blocks. The number of sets is equal to the number of cache blocks divided by the number of ways of associativity, what leads to 128 / 4 = 32 sets, and hence 2 = 32 different indices. There are 2 = 64 possible offsets. Since the CPU address is 32 bits wide, this implies 32 - 5 - 6 = 21 bits for the tag field.


title: CPU cache

text: The original Pentium 4 processor also had an eight-way set associative L2 integrated cache 256 KiB in size, with 128-byte cache blocks. This implies 32 - 8 - 7 = 17 bits for the tag field.


title: CPU cache

text: An instruction cache requires only one flag bit per cache row entry: a valid bit. The valid bit indicates whether or not a cache block has been loaded with valid data.


title: CPU cache

text: On power-up, the hardware sets all the valid bits in all the caches to "invalid". Some systems also set a valid bit to "invalid" at other times, such as when multi-master bus snooping hardware in the cache of one processor hears an address broadcast from some other processor, and realizes that certain data blocks in the local cache are now stale and should be marked invalid.


title: CPU cache

text: A data cache typically requires two flag bits per cache line a valid bit and a dirty bit. Having a dirty bit set indicates that the associated cache line has been changed since it was read from main memory ("dirty"), meaning that the processor has written data to that line and the new value has not propagated all the way to main memory.


title: CPU cache

text: A cache miss is a failed attempt to read or write a piece of data in the cache, which results in a main memory access with much longer latency. There are three kinds of cache misses: instruction read miss, data read miss, and data write miss.


title: CPU cache

text: "Cache read misses" from an "instruction" cache generally cause the largest delay, because the processor, or at least the thread of execution, has to wait (stall) until the instruction is fetched from main memory. "Cache read misses" from a "data" cache usually cause a smaller delay, because instructions not dependent on the cache read can be issued and continue execution until the data is returned from main memory, and the dependent instructions can resume execution. "Cache write misses" to a "data" cache generally cause the shortest delay, because the write can be queued and there are few limitations on the execution of subsequent instructions; the processor can continue until the queue is full. For a detailed introduction to the types of misses, see cache performance measurement and metric.


title: CPU cache

text: Most general purpose CPUs implement some form of virtual memory. To summarize, either each program running on the machine sees its own simplified address space, which contains code and data for that program only, or all programs run in a common virtual address space. A program executes by calculating, comparing, reading and writing to addresses of its virtual address space, rather than addresses of physical address space, making programs simpler and thus easier to write.


title: CPU cache

text: Virtual memory requires the processor to translate virtual addresses generated by the program into physical addresses in main memory. The portion of the processor that does this translation is known as the memory management unit (MMU). The fast path through the MMU can perform those translations stored in the translation lookaside buffer (TLB), which is a cache of mappings from the operating system's page table, segment table, or both.


title: CPU cache

text: For the purposes of the present discussion, there are three important features of address translation:


title: CPU cache

text: Some early virtual memory systems were very slow because they required an access to the page table (held in main memory) before every programmed access to main memory. With no caches, this effectively cut the speed of memory access in half. The first hardware cache used in a computer system was not actually a data or instruction cache, but rather a TLB.


title: CPU cache

text: Caches can be divided into four types, based on whether the index or tag correspond to physical or virtual addresses:


title: CPU cache

text: The speed of this recurrence (the "load latency") is crucial to CPU performance, and so most modern level-1 caches are virtually indexed, which at least allows the MMU's TLB lookup to proceed in parallel with fetching the data from the cache RAM.


title: CPU cache

text: But virtual indexing is not the best choice for all cache levels. The cost of dealing with virtual aliases grows with cache size, and as a result most level-2 and larger caches are physically indexed.


title: CPU cache

text: Caches have historically used both virtual and physical addresses for the cache tags, although virtual tagging is now uncommon. If the TLB lookup can finish before the cache RAM lookup, then the physical address is available in time for tag compare, and there is no need for virtual tagging. Large caches, then, tend to be physically tagged, and only small, very low latency caches are virtually tagged. In recent general-purpose CPUs, virtual tagging has been superseded by vhints, as described below.


title: CPU cache

text: A cache that relies on virtual indexing and tagging becomes inconsistent after the same virtual address is mapped into different physical addresses (homonym), which can be solved by using physical address for tagging, or by storing the address space identifier in the cache line. However, the latter approach does not help against the synonym problem, in which several cache lines end up storing data for the same physical address. Writing to such locations may update only one location in the cache, leaving the others with inconsistent data. This issue may be solved by using non-overlapping memory layouts for different address spaces, or otherwise the cache (or a part of it) must be flushed when the mapping changes.


title: CPU cache

text: The great advantage of virtual tags is that, for associative caches, they allow the tag match to proceed before the virtual to physical translation is done. However, coherence probes and evictions present a physical address for action. The hardware must have some means of converting the physical addresses into a cache index, generally by storing physical tags as well as virtual tags. For comparison, a physically tagged cache does not need to keep virtual tags, which is simpler. When a virtual to physical mapping is deleted from the TLB, cache entries with those virtual addresses will have to be flushed somehow. Alternatively, if cache entries are allowed on pages not mapped by the TLB, then those entries will have to be flushed when the access rights on those pages are changed in the page table.


title: CPU cache

text: It is also possible for the operating system to ensure that no virtual aliases are simultaneously resident in the cache. The operating system makes this guarantee by enforcing page coloring, which is described below. Some early RISC processors (SPARC, RS/6000) took this approach. It has not been used recently, as the hardware cost of detecting and evicting virtual aliases has fallen and the software complexity and performance penalty of perfect page coloring has risen.


title: CPU cache

text: It can be useful to distinguish the two functions of tags in an associative cache: they are used to determine which way of the entry set to select, and they are used to determine if the cache hit or missed. The second function must always be correct, but it is permissible for the first function to guess, and get the wrong answer occasionally.


title: CPU cache

text: Some processors (e.g. early SPARCs) have caches with both virtual and physical tags. The virtual tags are used for way selection, and the physical tags are used for determining hit or miss. This kind of cache enjoys the latency advantage of a virtually tagged cache, and the simple software interface of a physically tagged cache. It bears the added cost of duplicated tags, however. Also, during miss processing, the alternate ways of the cache line indexed have to be probed for virtual aliases and any matches evicted.


title: CPU cache

text: The extra area (and some latency) can be mitigated by keeping "virtual hints" with each cache entry instead of virtual tags. These hints are a subset or hash of the virtual tag, and are used for selecting the way of the cache from which to get data and a physical tag. Like a virtually tagged cache, there may be a virtual hint match but physical tag mismatch, in which case the cache entry with the matching hint must be evicted so that cache accesses after the cache fill at this address will have just one hint match. Since virtual hints have fewer bits than virtual tags distinguishing them from one another, a virtually hinted cache suffers more conflict misses than a virtually tagged cache.


title: CPU cache

text: Perhaps the ultimate reduction of virtual hints can be found in the Pentium 4 (Willamette and Northwood cores). In these processors the virtual hint is effectively two bits, and the cache is four-way set associative. Effectively, the hardware maintains a simple permutation from virtual address to cache index, so that no content-addressable memory (CAM) is necessary to select the right one of the four ways fetched.


title: CPU cache

text: Large physically indexed caches (usually secondary caches) run into a problem: the operating system rather than the application controls which pages collide with one another in the cache. Differences in page allocation from one program run to the next lead to differences in the cache collision patterns, which can lead to very large differences in program performance. These differences can make it very difficult to get a consistent and repeatable timing for a benchmark run.


title: CPU cache

text: To understand the problem, consider a CPU with a 1 MiB physically indexed direct-mapped level-2 cache and 4 KiB virtual memory pages. Sequential physical pages map to sequential locations in the cache until after 256 pages the pattern wraps around. We can label each physical page with a color of 0–255 to denote where in the cache it can go. Locations within physical pages with different colors cannot conflict in the cache.


title: CPU cache

text: Programmers attempting to make maximum use of the cache may arrange their programs' access patterns so that only 1 MiB of data need be cached at any given time, thus avoiding capacity misses. But they should also ensure that the access patterns do not have conflict misses. One way to think about this problem is to divide up the virtual pages the program uses and assign them virtual colors in the same way as physical colors were assigned to physical pages before. Programmers can then arrange the access patterns of their code so that no two pages with the same virtual color are in use at the same time. There is a wide literature on such optimizations (e.g. loop nest optimization), largely coming from the High Performance Computing (HPC) community.


title: CPU cache

text: The snag is that while all the pages in use at any given moment may have different virtual colors, some may have the same physical colors. In fact, if the operating system assigns physical pages to virtual pages randomly and uniformly, it is extremely likely that some pages will have the same physical color, and then locations from those pages will collide in the cache (this is the birthday paradox).


title: CPU cache

text: The solution is to have the operating system attempt to assign different physical color pages to different virtual colors, a technique called "page coloring". Although the actual mapping from virtual to physical color is irrelevant to system performance, odd mappings are difficult to keep track of and have little benefit, so most approaches to page coloring simply try to keep physical and virtual page colors the same.


title: CPU cache

text: If the operating system can guarantee that each physical page maps to only one virtual color, then there are no virtual aliases, and the processor can use virtually indexed caches with no need for extra virtual alias probes during miss handling. Alternatively, the OS can flush a page from the cache whenever it changes from one virtual color to another. As mentioned above, this approach was used for some early SPARC and RS/6000 designs.


title: CPU cache

text: The software page coloring technique has been used to effectively partition the shared Last level Cache (LLC) in multicore processors. This operating system-based LLC management in multicore processors has been adopted by Intel.


title: CPU cache

text: Modern processors have multiple interacting on-chip caches. The operation of a particular cache can be completely specified by the cache size, the cache block size, the number of blocks in a set, the cache set replacement policy, and the cache write policy (write-through or write-back).


title: CPU cache

text: While all of the cache blocks in a particular cache are the same size and have the same associativity, typically the "lower-level" caches (called Level 1 cache) have a smaller number of blocks, smaller block size, and fewer blocks in a set, but have very short access times. "Higher-level" caches (i.e. Level 2 and above) have progressively larger numbers of blocks, larger block size, more blocks in a set, and relatively longer access times, but are still much faster than main memory.


title: CPU cache

text: Cache entry replacement policy is determined by a cache algorithm selected to be implemented by the processor designers. In some cases, multiple algorithms are provided for different kinds of work loads.


title: CPU cache

text: Pipelined CPUs access memory from multiple points in the pipeline: instruction fetch, virtual-to-physical address translation, and data fetch (see classic RISC pipeline). The natural design is to use different physical caches for each of these points, so that no one physical resource has to be scheduled to service two points in the pipeline. Thus the pipeline naturally ends up with at least three separate caches (instruction, TLB, and data), each specialized to its particular role.


title: CPU cache

text: A victim cache is a cache used to hold blocks evicted from a CPU cache upon replacement. The victim cache lies between the main cache and its refill path, and holds only those blocks of data that were evicted from the main cache. The victim cache is usually fully associative, and is intended to reduce the number of conflict misses. Many commonly used programs do not require an associative mapping for all the accesses. In fact, only a small fraction of the memory accesses of the program require high associativity. The victim cache exploits this property by providing high associativity to only these accesses. It was introduced by Norman Jouppi from DEC in 1990.


title: CPU cache

text: Intel's "Crystalwell" variant of its Haswell processors introduced an on-package 128 MiB eDRAM Level 4 cache which serves as a victim cache to the processors' Level 3 cache. In the Skylake microarchitecture the Level 4 cache no longer works as a victim cache.


title: CPU cache

text: One of the more extreme examples of cache specialization is the trace cache (also known as "execution trace cache") found in the Intel Pentium 4 microprocessors. A trace cache is a mechanism for increasing the instruction fetch bandwidth and decreasing power consumption (in the case of the Pentium 4) by storing traces of instructions that have already been fetched and decoded.


title: CPU cache

text: A trace cache stores instructions either after they have been decoded, or as they are retired. Generally, instructions are added to trace caches in groups representing either individual basic blocks or dynamic instruction traces. The Pentium 4's trace cache stores micro-operations resulting from decoding x86 instructions, providing also the functionality of a micro-operation cache. Having this, the next time an instruction is needed, it does not have to be decoded into micro-ops again.