Compile times are getting insane with 16GB RAM. Split out several shared libs of either modules, or object families (as Teigha does). With modules encode/decode split compile-time will still require >10min, only with the dwg.spec splitup it will become managable. so split out dynblocks and maybe acsh solids, surfaces

or maybe just upgrade to 32GB RAM (160EUR)
Shorter compile times
This is a GitHub Issue
repo:libredwg
owner:LibreDWG
Title : Shorter compile times
Issue date:

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Compile times are getting insane with 16GB RAM. Split out several shared libs of either modules, or object families (as Teigha does). With modules encode/decode split compile-time will still require >10min, only with the dwg.spec splitup it will become managable. so split out dynblocks and maybe acsh solids, surfaces

or maybe just upgrade to 32GB RAM (160EUR)
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