components/esp_hw_support/port/esp32s3/spiram_psram.c
esp_err_t psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode)   //psram init
{
    assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now.");

    psram_gpio_config();
    psram_set_cs_timing();

    //enter MSPI slow mode to init PSRAM device registers
    spi_timing_enter_mspi_low_speed_mode(true);

    //We use SPI1 to init PSRAM
    psram_disable_qio_mode(SPI1_NUM);
    psram_read_id(SPI1_NUM, &s_psram_id);
    if (!PSRAM_IS_VALID(s_psram_id)) {
        /* 16Mbit psram ID read error workaround:
         * treat the first read id as a dummy one as the pre-condition,
         * Send Read ID command again
         */
        psram_read_id(SPI1_NUM, &s_psram_id);
        if (!PSRAM_IS_VALID(s_psram_id)) {
            ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", s_psram_id);
            return ESP_FAIL;
        }
    }

    //SPI1: send psram reset command
    psram_reset_mode(SPI1_NUM);
    //SPI1: send QPI enable command
    psram_enable_qio_mode(SPI1_NUM);

    //Do PSRAM timing tuning, we use SPI1 to do the tuning, and set the SPI0 PSRAM timing related registers accordingly
    spi_timing_psram_tuning();

    //Configure SPI0 PSRAM related SPI Phases
    config_psram_spi_phases();
    //Back to the high speed mode. Flash/PSRAM clocks are set to the clock that user selected. SPI0/1 registers are all set correctly
    spi_timing_enter_mspi_high_speed_mode(true);

    return ESP_OK;
}
/*
 * Psram mode init will overwrite original flash speed mode, so that it is possible to change psram and flash speed after OTA.
 * Flash read mode(QIO/QOUT/DIO/DOUT) will not be changed in app bin. It is decided by bootloader, OTA can not change this mode.
 */
Psram mode init will overwrite original flash speed mode, so that it is possible to change psram and flash speed after OTA.
Flash read mode(QIO/QOUT/DIO/DOUT) will not be changed in app bin. It is decided by bootloader, OTA can not change this mode.
Psram mode init will overwrite original flash speed mode so that it is possible to change psram and flash speed after OTA . Flash read mode ( QIO / QOUT / DIO / DOUT ) will not be changed in app bin . It is decided by bootloader OTA can not change this mode .
esp_err_t psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode)   
{
    assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now.");
    psram_gpio_config();
    psram_set_cs_timing();
    spi_timing_enter_mspi_low_speed_mode(true);
    psram_disable_qio_mode(SPI1_NUM);
    psram_read_id(SPI1_NUM, &s_psram_id);
    if (!PSRAM_IS_VALID(s_psram_id)) {
        psram_read_id(SPI1_NUM, &s_psram_id);
        if (!PSRAM_IS_VALID(s_psram_id)) {
            ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", s_psram_id);
            return ESP_FAIL;
        }
    }
    psram_reset_mode(SPI1_NUM);
    psram_enable_qio_mode(SPI1_NUM);
    spi_timing_psram_tuning();
    config_psram_spi_phases();
    spi_timing_enter_mspi_high_speed_mode(true);
    return ESP_OK;
}
esp_err_t psram_enable ( psram_cache_mode_t mode , psram_vaddr_mode_t vaddrmode ) { assert ( mode < PSRAM_CACHE_MAX && " " ) ; psram_gpio_config ( ) ; psram_set_cs_timing ( ) ; spi_timing_enter_mspi_low_speed_mode ( true ) ; psram_disable_qio_mode ( SPI1_NUM ) ; psram_read_id ( SPI1_NUM , & s_psram_id ) ; if ( ! PSRAM_IS_VALID ( s_psram_id ) ) { psram_read_id ( SPI1_NUM , & s_psram_id ) ; if ( ! PSRAM_IS_VALID ( s_psram_id ) ) { ESP_EARLY_LOGE ( TAG , " " , s_psram_id ) ; return ESP_FAIL ; } } psram_reset_mode ( SPI1_NUM ) ; psram_enable_qio_mode ( SPI1_NUM ) ; spi_timing_psram_tuning ( ) ; config_psram_spi_phases ( ) ; spi_timing_enter_mspi_high_speed_mode ( true ) ; return ESP_OK ; }
Psram mode init will overwrite original flash speed mode, so that it is possible to change psram and flash speed after OTA.
Psram mode init will overwrite original flash speed mode so that it is possible to change psram and flash speed after OTA .
//psram init //enter MSPI slow mode to init PSRAM device registers //We use SPI1 to init PSRAM /* 16Mbit psram ID read error workaround:
         * treat the first read id as a dummy one as the pre-condition,
         * Send Read ID command again
         */ //SPI1: send psram reset command //SPI1: send QPI enable command //Do PSRAM timing tuning, we use SPI1 to do the tuning, and set the SPI0 PSRAM timing related registers accordingly //Configure SPI0 PSRAM related SPI Phases //Back to the high speed mode. Flash/PSRAM clocks are set to the clock that user selected. SPI0/1 registers are all set correctly