The MPEG4 Encoder/Decoder has an interface for 1) ZBT SRAM and has an interface 2) that is standalone to hook up to another memory controller.
The standalone edif netlist has been used in the decoder case by Don Hodapp but I do not recall if this was MPMC2 or Ultra Memory Controller.
The standalone edif netlist has also been used by Mark Paluszkiewicz in research demonstrations with DDR memory.
Yes, this standalone edif netlist interface can be used to connect to the MPMC with some interfacing HDL (NPI port or VFBC PIM).
How to calculate the frame buffer size for the MPEG Cores.
Frame size K = ([Pixel Width x Pixel Height x Bit Depth] / 8) / 1024
Frame size K = ([640 x 480 x 24] / 8) / 1024 = 900K
Frame size K = ([720 x 576 x 24] / 8) / 1024 = 1215K
Memory Bandwidth Calculations:
This is the theorectical max, and rarely ever be reached after the first frame, but you need that much bandwidth, just in case you have a complete transition from one frame to then next.
The amount of memory bandwidth would then be (Frame Size * Frame Rate * bytes) * 2. Where bytes =bitwidth / 4, and we multiply by 2 because we do 1 frame read and 1 frame write.
e.g. (640x480 * 30fps * 4 bytes (32bit bus)) * 2 = (36.864 MB/s) * 2 = 73.728 MB/s
The customer would need to modify these calculations are for SRAM. The customer would need to modify these approriatly for other types of memory, such as DRAM, where systems efficiency also plays a role. Thus if we are only 25% efficient due to precharge or RAS/CAS scenarios then add a 2x into the calculations.