Can you summarize the following document?
        
  記憶體地址"a"被稱為"n位元組對齊",當"a"是"n"的倍數("n"應是2的冪)。  一次記憶體訪問被稱為對齊的,當被訪問的資料長度為"n" 位元組且該資料地址為"n"位元組對齊。如果記憶體未對齊,稱作"misaligned"。顯然,位元組訪問總是對齊的。  記憶體指標是對齊的,如果它所指的資料是對齊的。指向聚合資料(aggregate data,如struct或陣列)是對齊的,當且僅當它的每個組成資料是對齊的。

  

  Most RISC processors will generate an alignment fault when a load or store instruction accesses a misaligned address. This allows the operating system to emulate the misaligned access using other instructions. For example, the alignment fault handler might use byte loads or stores (which are always aligned) to emulate a larger load or store instruction.  Some architectures like MIPS have special unaligned load and store instructions. One unaligned load instruction gets the bytes from the memory word with the lowest byte address and another gets the bytes from the memory word with the highest byte address. Similarly, store-high and store-low instructions store the appropriate bytes in the higher and lower memory words respectively.  The Alpha architecture has a two-step approach to unaligned loads and stores. The first step is to load the upper and lower memory words into separate registers. The second step is to extract or modify the memory words using special low/high instructions similar to the MIPS instructions. An unaligned store is completed by storing the modified memory words back to memory. The reason for this complexity is that the original Alpha architecture could only read or write 32-bit or 64-bit values. This proved to be a severe limitation that often led to code bloat and poor performance. To address this limitation, an extension called the "Byte Word Extensions" (BWX) was added to the original architecture. It consisted of instructions for byte and word loads and stores.  Because these instructions are larger and slower than the normal memory load and store instructions, they should only be used when necessary. Some C and C++ compilers have an “unaligned” attribute that can be applied to pointers that need the unaligned instructions.

  x86體系架構最初是不要求記憶體對齊。一些SSE2指令要求資料是128位元(16位元組)對齊。有些CPU指令用於未對齊訪問如MOVDQU。讀寫記憶體操作僅在對齊時才是原子的。

  C語言資料結構內的成員先後順序不能改變。  常見的C語言編譯器在32位元x86上,double是8位元組對齊,但Linux上是4位元組對齊(編譯選項"-malign-double"實現8位元組對齊)。 一些編譯器(Microsoft, Borland, GNU,等等)使用 directive指定對齊的包入(packing)。例如:  這個結構在32位系統的大小為6位元組。

  Microsoft編譯器的專案預設packing(編譯選項/Zp)與指令。指令僅能減少packing尺寸。
資料結構對齊是程式碼編譯後在記憶體的佈局與使用方式。包括三方面內容:資料對齊、資料結構填充(padding)與包入(packing)。