Nightly testing for make-dist on sst-elements provides a false pass if distribution files are missing some ref files
Issue #1683 indicated that the simple carwash test was failing due to a missing test ref file.   This should have been caught by our nightly testing of the distribution.  

Analysis of the nightly build/test system for make-dist discovered that the frameworks build/test script (copied from the old bamboo script) copied the reference files from the devel branch to the extracted distribution files that were being tested.  This allowed some tests that are missing reference files from the distribution to **falsely** pass.  

Upon testing of a corrected build/test script, it was discovered that the following elements will fail testing:  
  * **simpleSimulation**  
  * **prospero**
  * **zodiac**

NOTE: This affects the SST 11.0 release.  

A new PR will soon be generated to correct the Makefile.am for the appropriate elements, and an updated frameworks build/test system will be merged.
diff --git a/src/sst/elements/CramSim/tests/ariel_cramsim.py b/src/sst/elements/CramSim/tests/ariel_cramsim.py
index ac83897f4..cb46f653f 100644
--- a/src/sst/elements/CramSim/tests/ariel_cramsim.py
+++ b/src/sst/elements/CramSim/tests/ariel_cramsim.py
@@ -5,30 +5,30 @@ import os
 
 #######################################################################################################
 def read_arguments():
-	config_file = list()
-        override_list = list()
-        boolDefaultConfig = True;
+    config_file = list()
+    override_list = list()
+    boolDefaultConfig = True;
 
-	for arg in sys.argv:
-            if arg.find("--configfile=") != -1:
-		substrIndex = arg.find("=")+1
-		config_file = arg[substrIndex:]
-		print("Config file:", config_file)
-		boolDefaultConfig = False;
+    for arg in sys.argv:
+        if arg.find("--configfile=") != -1:
+            substrIndex = arg.find("=")+1
+            config_file = arg[substrIndex:]
+            print("Config file:", config_file)
+            boolDefaultConfig = False;
 
-  	    elif arg != sys.argv[0]:
-                if arg.find("=") == -1:
-                    print("Malformed config override found!: ", arg)
-                    exit(-1)
-                override_list.append(arg)
-                print("Override: ", override_list[-1])
+        elif arg != sys.argv[0]:
+            if arg.find("=") == -1:
+                print("Malformed config override found!: ", arg)
+                exit(-1)
+            override_list.append(arg)
+            print("Override: ", override_list[-1])
 
-	
-	if boolDefaultConfig == True:
-		config_file = "../ddr4_verimem.cfg"
-		print("config file is not specified.. using ddr4_verimem.cfg")
+    
+    if boolDefaultConfig == True:
+        config_file = "../ddr4_verimem.cfg"
+        print("config file is not specified.. using ddr4_verimem.cfg")
 
-	return [config_file, override_list]
+    return [config_file, override_list]
 
 
 
@@ -122,131 +122,131 @@ ariel.addParams({
 
 def genMemHierarchy(cores):
    
-   membus = sst.Component("membus", "memHierarchy.Bus")
-   membus.addParams({
-       "bus_frequency" : cacheFrequency,
-   })
+    membus = sst.Component("membus", "memHierarchy.Bus")
+    membus.addParams({
+        "bus_frequency" : cacheFrequency,
+    })
   
 
-   memory = sst.Component("memory", "memHierarchy.MemController")
-   memory.addParams({
-       "debug"                 : memDebug,
-       "clock"                 : "1Ghz",
-       "request_width"         : cacheLineSize
-   })
-   backend = memory.setSubComponent("backend", "memHierarchy.cramsim")
-   backend.addParams({
-      "access_time" : "2 ns",   # Phy latency
-      "mem_size" : "512MiB",
-      "max_outstanding_requests" : 256,
-      "verbose" : 1,
-   })
+    memory = sst.Component("memory", "memHierarchy.MemController")
+    memory.addParams({
+        "debug"                 : memDebug,
+        "clock"                 : "1Ghz",
+        "request_width"         : cacheLineSize
+    })
+    backend = memory.setSubComponent("backend", "memHierarchy.cramsim")
+    backend.addParams({
+        "access_time" : "2 ns",   # Phy latency
+        "mem_size" : "512MiB",
+        "max_outstanding_requests" : 256,
+        "verbose" : 1,
+    })
    
-   for core in range (cores):
-       l1 = sst.Component("l1cache_%d"%core, "memHierarchy.Cache")
-       l1.addParams({
-           "cache_frequency"       : cacheFrequency,
-           "cache_size"            : "32KB",
-           "cache_line_size"       : cacheLineSize,
-           "associativity"         : "8",
-           "access_latency_cycles" : "4",
-           "coherence_protocol"    : coherenceProtocol,
-           "replacement_policy"    : rplPolicy,
-           "L1"                    : "1",
-           "debug"                 : memDebug,  
-           "debug_level"           : memDebugLevel, 
-       })
-
-       l2 = sst.Component("l2cache_%d"%core, "memHierarchy.Cache")
-       l2.addParams({
-           "cache_frequency"       : cacheFrequency,
-           "cache_size"            : "256 KB",
-           "cache_line_size"       : cacheLineSize,
-           "associativity"         : "8",
-           "access_latency_cycles" : "10",
-           "coherence_protocol"    : coherenceProtocol,
-           "replacement_policy"    : rplPolicy,
-           "L1"                    : "0",
-           "debug"                 : memDebug,  
-           "debug_level"           : memDebugLevel, 
-           "mshr_num_entries"      : "16",
-       })
+    for core in range (cores):
+        l1 = sst.Component("l1cache_%d"%core, "memHierarchy.Cache")
+        l1.addParams({
+            "cache_frequency"       : cacheFrequency,
+            "cache_size"            : "32KB",
+            "cache_line_size"       : cacheLineSize,
+            "associativity"         : "8",
+            "access_latency_cycles" : "4",
+            "coherence_protocol"    : coherenceProtocol,
+            "replacement_policy"    : rplPolicy,
+            "L1"                    : "1",
+            "debug"                 : memDebug,  
+            "debug_level"           : memDebugLevel, 
+        })
+
+        l2 = sst.Component("l2cache_%d"%core, "memHierarchy.Cache")
+        l2.addParams({
+            "cache_frequency"       : cacheFrequency,
+            "cache_size"            : "256 KB",
+            "cache_line_size"       : cacheLineSize,
+            "associativity"         : "8",
+            "access_latency_cycles" : "10",
+            "coherence_protocol"    : coherenceProtocol,
+            "replacement_policy"    : rplPolicy,
+            "L1"                    : "0",
+            "debug"                 : memDebug,  
+            "debug_level"           : memDebugLevel, 
+            "mshr_num_entries"      : "16",
+        })
        
-       ## SST Links
-       # Ariel -> L1(PRIVATE) -> L2(PRIVATE)  -> L3 (SHARED) -> DRAM 
-       ArielL1Link = sst.Link("cpu_cache_%d"%core)
-       ArielL1Link.connect((ariel, "cache_link_%d"%core, busLat), (l1, "high_network_0", busLat))
-       L1L2Link = sst.Link("l1_l2_%d"%core)
-       L1L2Link.connect((l1, "low_network_0", busLat), (l2, "high_network_0", busLat))
-       L2MembusLink = sst.Link("l2_membus_%d"%core)
-       L2MembusLink.connect((l2, "low_network_0", busLat), (membus, "high_network_%d"%core, busLat))
+        ## SST Links
+        # Ariel -> L1(PRIVATE) -> L2(PRIVATE)  -> L3 (SHARED) -> DRAM 
+        ArielL1Link = sst.Link("cpu_cache_%d"%core)
+        ArielL1Link.connect((ariel, "cache_link_%d"%core, busLat), (l1, "high_network_0", busLat))
+        L1L2Link = sst.Link("l1_l2_%d"%core)
+        L1L2Link.connect((l1, "low_network_0", busLat), (l2, "high_network_0", busLat))
+        L2MembusLink = sst.Link("l2_membus_%d"%core)
+        L2MembusLink.connect((l2, "low_network_0", busLat), (membus, "high_network_%d"%core, busLat))
    
 
-   l3 = sst.Component("L3cache", "memHierarchy.Cache")
-   l3.addParams({
-       "cache_frequency"       : cacheFrequency,
-       "cache_size"            : "8 MB",
-       "cache_line_size"       : cacheLineSize,
-       "associativity"         : "8",
-       "access_latency_cycles" : "20",
-       "coherence_protocol"    : coherenceProtocol,
-       "replacement_policy"    : rplPolicy,
-       "L1"                    : "0",
-       "debug"                 : memDebug,  
-       "debug_level"           : memDebugLevel, 
-       "mshr_num_entries"      : "16",
-   })
+    l3 = sst.Component("L3cache", "memHierarchy.Cache")
+    l3.addParams({
+        "cache_frequency"       : cacheFrequency,
+        "cache_size"            : "8 MB",
+        "cache_line_size"       : cacheLineSize,
+        "associativity"         : "8",
+        "access_latency_cycles" : "20",
+        "coherence_protocol"    : coherenceProtocol,
+        "replacement_policy"    : rplPolicy,
+        "L1"                    : "0",
+        "debug"                 : memDebug,  
+        "debug_level"           : memDebugLevel, 
+        "mshr_num_entries"      : "16",
+    })
   
-   # Bus to L3 and L3 <-> MM
-   BusL3Link = sst.Link("bus_L3")
-   BusL3Link.connect((membus, "low_network_0", busLat), (l3, "high_network_0", busLat))
-   L3MemCtrlLink = sst.Link("L3MemCtrl")
-   L3MemCtrlLink.connect((l3, "low_network_0", busLat), (memory, "direct_link", busLat))
+    # Bus to L3 and L3 <-> MM
+    BusL3Link = sst.Link("bus_L3")
+    BusL3Link.connect((membus, "low_network_0", busLat), (l3, "high_network_0", busLat))
+    L3MemCtrlLink = sst.Link("L3MemCtrl")
+    L3MemCtrlLink.connect((l3, "low_network_0", busLat), (memory, "direct_link", busLat))
 
     # txn gen --> memHierarchy Bridge
-   comp_memhBridge = sst.Component("memh_bridge", "CramSim.c_MemhBridge")
-   comp_memhBridge.addParams(g_params);
-   comp_memhBridge.addParams({
+    comp_memhBridge = sst.Component("memh_bridge", "CramSim.c_MemhBridge")
+    comp_memhBridge.addParams(g_params);
+    comp_memhBridge.addParams({
                         "verbose" : "0",
                         "numTxnPerCycle" : g_params["numChannels"],
                         "strTxnTraceFile" : "arielTrace",
                         "boolPrintTxnTrace" : "1"
                         })
-   # controller
-   comp_controller0 = sst.Component("MemController0", "CramSim.c_Controller")
-   comp_controller0.addParams(g_params)
-   comp_controller0.addParams({
+    # controller
+    comp_controller0 = sst.Component("MemController0", "CramSim.c_Controller")
+    comp_controller0.addParams(g_params)
+    comp_controller0.addParams({
                         "verbose" : "0",
-			})
-   c0 = comp_controller0.setSubComponent("TxnConverter","CramSim.c_TxnConverter")
-   c1 = comp_controller0.setSubComponent("AddrMapper", "CramSim.c_AddressHasher")
-   c2 = comp_controller0.setSubComponent("CmdScheduler", "CramSim.c_CmdScheduler")
-   c3 = comp_controller0.setSubComponent("DeviceController", "CramSim.c_DeviceController")
-   c0.addParams(g_params)
-   c1.addParams(g_params)
-   c2.addParams(g_params)
-   c3.addParams(g_params)
+                        })
+    c0 = comp_controller0.setSubComponent("TxnConverter","CramSim.c_TxnConverter")
+    c1 = comp_controller0.setSubComponent("AddrMapper", "CramSim.c_AddressHasher")
+    c2 = comp_controller0.setSubComponent("CmdScheduler", "CramSim.c_CmdScheduler")
+    c3 = comp_controller0.setSubComponent("DeviceController", "CramSim.c_DeviceController")
+    c0.addParams(g_params)
+    c1.addParams(g_params)
+    c2.addParams(g_params)
+    c3.addParams(g_params)
 
-		# bank receiver
-   comp_dimm0 = sst.Component("Dimm0", "CramSim.c_Dimm")
-   comp_dimm0.addParams(g_params)
+    # bank receiver
+    comp_dimm0 = sst.Component("Dimm0", "CramSim.c_Dimm")
+    comp_dimm0.addParams(g_params)
 
 
-   link_dir_cramsim_link = sst.Link("link_dir_cramsim_link")
-   link_dir_cramsim_link.connect( (backend, "cramsim_link", "2ns"), (comp_memhBridge, "cpuLink", "2ns") )
+    link_dir_cramsim_link = sst.Link("link_dir_cramsim_link")
+    link_dir_cramsim_link.connect( (backend, "cramsim_link", "2ns"), (comp_memhBridge, "cpuLink", "2ns") )
 
-   # memhBridge(=TxnGen) <-> Memory Controller 
-   memHLink = sst.Link("memHLink_1")
-   memHLink.connect( (comp_memhBridge, "memLink", g_params["clockCycle"]), (comp_controller0, "txngenLink", g_params["clockCycle"]) )
+    # memhBridge(=TxnGen) <-> Memory Controller 
+    memHLink = sst.Link("memHLink_1")
+    memHLink.connect( (comp_memhBridge, "memLink", g_params["clockCycle"]), (comp_controller0, "txngenLink", g_params["clockCycle"]) )
 
-   # Controller <-> Dimm
-   cmdLink = sst.Link("cmdLink_1")
-   cmdLink.connect( (comp_controller0, "memLink", g_params["clockCycle"]), (comp_dimm0, "ctrlLink", g_params["clockCycle"]) )
+    # Controller <-> Dimm
+    cmdLink = sst.Link("cmdLink_1")
+    cmdLink.connect( (comp_controller0, "memLink", g_params["clockCycle"]), (comp_dimm0, "ctrlLink", g_params["clockCycle"]) )
 
 
-   comp_controller0.enableAllStatistics()
-   comp_memhBridge.enableAllStatistics()
-   comp_dimm0.enableAllStatistics()
+    comp_controller0.enableAllStatistics()
+    comp_memhBridge.enableAllStatistics()
+    comp_dimm0.enableAllStatistics()
 
 
 sst.setStatisticLoadLevel(7)
diff --git a/src/sst/elements/CramSim/tests/macsim_cramsim.py b/src/sst/elements/CramSim/tests/macsim_cramsim.py
index 4be485cd2..90f3d5585 100644
--- a/src/sst/elements/CramSim/tests/macsim_cramsim.py
+++ b/src/sst/elements/CramSim/tests/macsim_cramsim.py
@@ -6,30 +6,30 @@ import time
 
 #######################################################################################################
 def read_arguments():
-	config_file = list()
-        override_list = list()
-        boolDefaultConfig = True;
+    config_file = list()
+    override_list = list()
+    boolDefaultConfig = True;
 
-	for arg in sys.argv:
-            if arg.find("--configfile=") != -1:
-		substrIndex = arg.find("=")+1
-		config_file = arg[substrIndex:]
-		print("Config file:", config_file)
-		boolDefaultConfig = False;
+    for arg in sys.argv:
+        if arg.find("--configfile=") != -1:
+            substrIndex = arg.find("=")+1
+            config_file = arg[substrIndex:]
+            print("Config file:", config_file)
+            boolDefaultConfig = False;
 
-  	    elif arg != sys.argv[0]:
-                if arg.find("=") == -1:
-                    print("Malformed config override found!: ", arg)
-                    exit(-1)
-                override_list.append(arg)
-                print("Override: ", override_list[-1])
+        elif arg != sys.argv[0]:
+            if arg.find("=") == -1:
+                print("Malformed config override found!: ", arg)
+                exit(-1)
+            override_list.append(arg)
+            print("Override: ", override_list[-1])
 
-	
-	if boolDefaultConfig == True:
-		config_file = "../ddr4_verimem.cfg"
-		print("config file is not specified.. using ddr4_verimem.cfg")
 
-	return [config_file, override_list]
+    if boolDefaultConfig == True:
+        config_file = "../ddr4_verimem.cfg"
+        print("config file is not specified.. using ddr4_verimem.cfg")
+
+    return [config_file, override_list]
 
 
 
@@ -577,14 +577,14 @@ comp_gpu0l2cache.addParams({
 })
 comp_memory0 = sst.Component("memory0", "memHierarchy.MemController")
 comp_memory0.addParams({
-     "debug" : "0",
-     "coherence_protocol" : "MESI",
-	 "backend" : "memHierarchy.cramsim",
-	 "backend.access_time" : "100 ns",
-     "backend.mem_size" : "4096MiB",
-     "clock" : "1GHz",
-     "rangeStart" : "0",
-	 "request_width"	: "128"
+    "debug" : "0",
+    "coherence_protocol" : "MESI",
+    "backend" : "memHierarchy.cramsim",
+    "backend.access_time" : "100 ns",
+    "backend.mem_size" : "4096MiB",
+    "clock" : "1GHz",
+    "rangeStart" : "0",
+    "request_width" : "128"
 })
 
 
@@ -754,12 +754,12 @@ comp_memhBridge.addParams({
 comp_controller0 = sst.Component("MemController0", "CramSim.c_Controller")
 comp_controller0.addParams(g_params)
 comp_controller0.addParams({
-                     "verbose" : "0",
-     		"TxnConverter" : "CramSim.c_TxnConverter",
-     		"AddrHasher" : "CramSim.c_AddressHasher",
-     		"CmdScheduler" : "CramSim.c_CmdScheduler" ,
-     		"DeviceController" : "CramSim.c_DeviceController"
-     		})
+                "verbose" : "0",
+                "TxnConverter" : "CramSim.c_TxnConverter",
+                "AddrHasher" : "CramSim.c_AddressHasher",
+                "CmdScheduler" : "CramSim.c_CmdScheduler" ,
+                "DeviceController" : "CramSim.c_DeviceController"
+                })
 
 
 # bank receiver
diff --git a/src/sst/elements/CramSim/tests/run.py b/src/sst/elements/CramSim/tests/run.py
index ffbf78270..e8bb6db78 100755
--- a/src/sst/elements/CramSim/tests/run.py
+++ b/src/sst/elements/CramSim/tests/run.py
@@ -6,14 +6,14 @@ import sys
 
 def run(osCmd):
 
-	print(osCmd)
+    print(osCmd)
 
-	start=time.time()
-	os.system(osCmd)
-	end=time.time()
-	sim_elapsed_time=end-start
-	print("sim_elapsed_time(sec): ", sim_elapsed_time)
-	print("\n\n")
+    start=time.time()
+    os.system(osCmd)
+    end=time.time()
+    sim_elapsed_time=end-start
+    print("sim_elapsed_time(sec): ", sim_elapsed_time)
+    print("\n\n")
 
 
 stopAtCycle = "100us"
@@ -26,34 +26,34 @@ if len(sys.argv) > 1:
    sel = sys.argv[1]
 
 sstCmds = {
-	1:"sst --lib-path=../.libs ./test_txngen.py --model-options=\"--configfile=%s mode=rand stopAtCycle=%s\"" % (sysconfig,stopAtCycle), 							# test with random trace
-	2:"sst --lib-path=../.libs ./test_txngen.py --model-options=\"--configfile=%s mode=seq stopAtCycle=%s\"" % (sysconfig,stopAtCycle),							# test with seq trace
-	3:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_1_R.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle),	# test with verimem_1_R trace
-	4:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_2_R.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle),	# test with verimem_2_R trace
-	5:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_4_R.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle),	# test with verimem_4_R trace
-	6:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_5_R.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle),	# test with verimem_5_R trace
-	7:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_6_R.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle),	# test with verimem_6_R trace
-	8:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_1_W.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle),	# test with verimem_1_W trace
-	9:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_2_W.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle),	# test with verimem_2_W trace
-	10:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_4_W.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle),	# test with verimem_4_W trace
-	11:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_5_W.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle),	# test with verimem_5_W trace
-	12:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_6_W.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle),	# test with verimem_6_W trace
-	13:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_1_RW.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle),	# test with verimem_1_RW trace
-	14:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/usimm.trc stopAtCycle=%s traceFileType=USIMM\"" % (sysconfig,stopAtCycle),		# test with usimm trace
-	15:"sst --lib-path=../.libs ./test_multilanes_4lane.py --model-options=\"--configfile=../ddr4_2400.cfg stopAtCycle=%s\"" % (stopAtCycle),						# test for txn dispatcher with 4lane
-	16:"mpirun -np 5 sst --lib-path=../.libs ./test_multilanes_4lane.py --model-options=\"--configfile=../ddr4_2400.cfg stopAtCycle=%s\"" % (stopAtCycle),			            	# test for txn dispatcher with 4lane(mpi)
-	17:"sst --lib-path=../.libs ./test_txngen.py --model-options=\"--configfile=%s mode=seq stopAtCycle=%s\"" % ("../hbm_legacy_4h.cfg",stopAtCycle), 					# test for hbm
-	18:"sst --lib-path=../.libs ./test_txngen.py --model-options=\"--configfile=%s mode=rand stopAtCycle=%s\"" % ("../ddr3_power.cfg",stopAtCycle), 							# test for ddr3 with power model
-	}                                                                                                                                                                                       
-
-	
+    1:"sst --lib-path=../.libs ./test_txngen.py --model-options=\"--configfile=%s mode=rand stopAtCycle=%s\"" % (sysconfig,stopAtCycle),                                                # test with random trace
+    2:"sst --lib-path=../.libs ./test_txngen.py --model-options=\"--configfile=%s mode=seq stopAtCycle=%s\"" % (sysconfig,stopAtCycle),                                                 # test with seq trace
+    3:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_1_R.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle),  # test with verimem_1_R trace
+    4:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_2_R.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle),  # test with verimem_2_R trace
+    5:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_4_R.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle),  # test with verimem_4_R trace
+    6:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_5_R.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle),  # test with verimem_5_R trace
+    7:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_6_R.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle),  # test with verimem_6_R trace
+    8:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_1_W.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle),  # test with verimem_1_W trace
+    9:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_2_W.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle),  # test with verimem_2_W trace
+    10:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_4_W.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle), # test with verimem_4_W trace
+    11:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_5_W.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle), # test with verimem_5_W trace
+    12:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_6_W.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle), # test with verimem_6_W trace
+    13:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/sst-CramSim-trace_verimem_1_RW.trc stopAtCycle=%s\"" % (sysconfig,stopAtCycle),# test with verimem_1_RW trace
+    14:"sst --lib-path=../.libs ./test_txntrace.py --model-options=\"--configfile=%s traceFile=../traces/usimm.trc stopAtCycle=%s traceFileType=USIMM\"" % (sysconfig,stopAtCycle),     # test with usimm trace
+    15:"sst --lib-path=../.libs ./test_multilanes_4lane.py --model-options=\"--configfile=../ddr4_2400.cfg stopAtCycle=%s\"" % (stopAtCycle),                                           # test for txn dispatcher with 4lane
+    16:"mpirun -np 5 sst --lib-path=../.libs ./test_multilanes_4lane.py --model-options=\"--configfile=../ddr4_2400.cfg stopAtCycle=%s\"" % (stopAtCycle),                              # test for txn dispatcher with 4lane(mpi)
+    17:"sst --lib-path=../.libs ./test_txngen.py --model-options=\"--configfile=%s mode=seq stopAtCycle=%s\"" % ("../hbm_legacy_4h.cfg",stopAtCycle),                                   # test for hbm
+    18:"sst --lib-path=../.libs ./test_txngen.py --model-options=\"--configfile=%s mode=rand stopAtCycle=%s\"" % ("../ddr3_power.cfg",stopAtCycle),                                     # test for ddr3 with power model
+    }                                                                                                                                                                                       
+
+    
 
 if(sel == "batch"):
-	for sel in sstCmds:
-		run(sstCmds[sel])
-		time.sleep(1)
+    for sel in sstCmds:
+        run(sstCmds[sel])
+        time.sleep(1)
 elif(sel.isdigit()):
-	params=sstCmds[int(sel)]
-	run(params)
+    params=sstCmds[int(sel)]
+    run(params)
 else:
-	print("Param#1 should be \"batch\" or [0-%d]" % (len(sstCmds)-1))
+    print("Param#1 should be \"batch\" or [0-%d]" % (len(sstCmds)-1))
diff --git a/src/sst/elements/CramSim/tests/test_multilanes_4lane.py b/src/sst/elements/CramSim/tests/test_multilanes_4lane.py
index d25589cfc..5e8d92120 100644
--- a/src/sst/elements/CramSim/tests/test_multilanes_4lane.py
+++ b/src/sst/elements/CramSim/tests/test_multilanes_4lane.py
@@ -38,21 +38,21 @@ sst.setStatisticOutput("sst.statOutputConsole")
 comp_txnGen = sst.Component("TxnGen", "CramSim.c_TxnGen")
 comp_txnGen.addParams(g_params)
 comp_txnGen.addParams({
-	"mode" : "rand",
-	"maxTxns" : maxTxns,
-	"numTxnPerCycle" : totalChannel,
-	"maxOutstandingReqs" : maxOutstandingReqs,
-	"readWriteRatio" : readWriteRatio
-	})
+        "mode" : "rand",
+        "maxTxns" : maxTxns,
+        "numTxnPerCycle" : totalChannel,
+        "maxOutstandingReqs" : maxOutstandingReqs,
+        "readWriteRatio" : readWriteRatio
+        })
 comp_txnGen.enableAllStatistics()
 
 comp_txnDispatcher = sst.Component("txnDispatcher", "CramSim.c_TxnDispatcher");
 comp_txnDispatcher.addParams({
-	"numLanes" : numLanes,
-	"laneIdxPos" : laneIdxPos,
-	"debug" : 0,
-	"debug_level" : 0
-	})
+        "numLanes" : numLanes,
+        "laneIdxPos" : laneIdxPos,
+        "debug" : 0,
+        "debug_level" : 0
+        })
 
 txnGenLink = sst.Link("txnGenLink")
 txnGenLink.connect((comp_txnGen, "memLink", g_params["clockCycle"]),(comp_txnDispatcher,"txnGen",g_params["clockCycle"]))
@@ -61,38 +61,36 @@ txnGenLink.connect((comp_txnGen, "memLink", g_params["clockCycle"]),(comp_txnDis
 # Configure controller and device
 for chid in range(numLanes):
 
-	# controller
-	comp_controller = sst.Component("MemController"+str(chid), "CramSim.c_Controller")
-	comp_controller.addParams(g_params)
-	c0 = comp_controller.setSubComponent("TxnScheduler", "CramSim.c_TxnScheduler")
-	c1 = comp_controller.setSubComponent("TxnConverter", "CramSim.c_TxnConverter")
-	c2 = comp_controller.setSubComponent("AddrMapper", "CramSim.c_AddressHasher")
-	c3 = comp_controller.setSubComponent("CmdScheduler", "CramSim.c_CmdScheduler")
-	c4 = comp_controller.setSubComponent("DeviceDriver", "CramSim.c_DeviceDriver")
-        c0.addParams(g_params)
-        c1.addParams(g_params)
-        c2.addParams(g_params)
-        c3.addParams(g_params)
-        c4.addParams(g_params)
-	
-        # device
-	comp_dimm = sst.Component("Dimm"+str(chid), "CramSim.c_Dimm")
-	comp_dimm.addParams(g_params)
-
-	# TXNGEN / Controller LINKS
-	# TxnGen -> Controller (Req)(Txn)
-	txnReqLink_0 = sst.Link("txnReqLink_0_"+(str(chid)))
-	txnReqLink_0.connect((comp_txnDispatcher, "lane_"+(str(chid)), g_params["clockCycle"]), (comp_controller, "txngenLink", g_params["clockCycle"]) )
-
-
-	# Controller -> Dimm (Req)
-	cmdReqLink_1 = sst.Link("cmdReqLink_1_"+(str(chid)))
-	cmdReqLink_1.connect( (comp_controller, "memLink", g_params["clockCycle"]), (comp_dimm, "ctrlLink", g_params["clockCycle"]) )
-
-	
-
-	# enable all statistics
-	comp_controller.enableAllStatistics()
-	#comp_txnUnit0.enableAllStatistics({ "type":"sst.AccumulatorStatistic",
-	#                                    "rate":"1 us"})
-	#comp_dimm.enableAllStatistics()
+    # controller
+    comp_controller = sst.Component("MemController"+str(chid), "CramSim.c_Controller")
+    comp_controller.addParams(g_params)
+    c0 = comp_controller.setSubComponent("TxnScheduler", "CramSim.c_TxnScheduler")
+    c1 = comp_controller.setSubComponent("TxnConverter", "CramSim.c_TxnConverter")
+    c2 = comp_controller.setSubComponent("AddrMapper", "CramSim.c_AddressHasher")
+    c3 = comp_controller.setSubComponent("CmdScheduler", "CramSim.c_CmdScheduler")
+    c4 = comp_controller.setSubComponent("DeviceDriver", "CramSim.c_DeviceDriver")
+    c0.addParams(g_params)
+    c1.addParams(g_params)
+    c2.addParams(g_params)
+    c3.addParams(g_params)
+    c4.addParams(g_params)
+    
+    # device
+    comp_dimm = sst.Component("Dimm"+str(chid), "CramSim.c_Dimm")
+    comp_dimm.addParams(g_params)
+
+    # TXNGEN / Controller LINKS
+    # TxnGen -> Controller (Req)(Txn)
+    txnReqLink_0 = sst.Link("txnReqLink_0_"+(str(chid)))
+    txnReqLink_0.connect((comp_txnDispatcher, "lane_"+(str(chid)), g_params["clockCycle"]), (comp_controller, "txngenLink", g_params["clockCycle"]) )
+
+
+    # Controller -> Dimm (Req)
+    cmdReqLink_1 = sst.Link("cmdReqLink_1_"+(str(chid)))
+    cmdReqLink_1.connect( (comp_controller, "memLink", g_params["clockCycle"]), (comp_dimm, "ctrlLink", g_params["clockCycle"]) )
+
+    # enable all statistics
+    comp_controller.enableAllStatistics()
+    #comp_txnUnit0.enableAllStatistics({ "type":"sst.AccumulatorStatistic",
+    #                                    "rate":"1 us"})
+    #comp_dimm.enableAllStatistics()
diff --git a/src/sst/elements/CramSim/tests/test_statTest1.py b/src/sst/elements/CramSim/tests/test_statTest1.py
index af8846994..ec6e08d6f 100644
--- a/src/sst/elements/CramSim/tests/test_statTest1.py
+++ b/src/sst/elements/CramSim/tests/test_statTest1.py
@@ -7,30 +7,30 @@ import time
 
 #######################################################################################################
 def read_arguments():
-	config_file = list()
-        override_list = list()
-        boolDefaultConfig = True;
+    config_file = list()
+    override_list = list()
+    boolDefaultConfig = True;
 
-	for arg in sys.argv:
-            if arg.find("--configfile=") != -1:
-		substrIndex = arg.find("=")+1
-		config_file = arg[substrIndex:]
-		print("Config file:", config_file)
-		boolDefaultConfig = False;
+    for arg in sys.argv:
+        if arg.find("--configfile=") != -1:
+            substrIndex = arg.find("=")+1
+            config_file = arg[substrIndex:]
+            print("Config file:", config_file)
+            boolDefaultConfig = False;
 
-  	    elif arg != sys.argv[0]:
-                if arg.find("=") == -1:
-                    print("Malformed config override found!: ", arg)
-                    exit(-1)
-                override_list.append(arg)
-                print("Override: ", override_list[-1])
+        elif arg != sys.argv[0]:
+            if arg.find("=") == -1:
+                print("Malformed config override found!: ", arg)
+                exit(-1)
+            override_list.append(arg)
+            print("Override: ", override_list[-1])
 
-	
-	if boolDefaultConfig == True:
-		config_file = "../ddr4_verimem.cfg"
-		print("config file is not specified.. using ddr4_verimem.cfg")
 
-	return [config_file, override_list]
+    if boolDefaultConfig == True:
+        config_file = "../ddr4_verimem.cfg"
+        print("config file is not specified.. using ddr4_verimem.cfg")
+
+    return [config_file, override_list]
 
 
 
@@ -74,9 +74,9 @@ comp_txnGen0 = sst.Component("TxnGen", "CramSim.c_TxnGen")
 comp_txnGen0.addParams(g_params)
 comp_txnGen0.addParams({
         "mode" : "rand",
-	"numTxnPerCycle" : 1,
-	"readWriteRatio" : 0.5
-	})
+        "numTxnPerCycle" : 1,
+        "readWriteRatio" : 0.5
+    })
 comp_txnGen0.enableAllStatistics()
 
 
diff --git a/src/sst/elements/CramSim/tests/util.py b/src/sst/elements/CramSim/tests/util.py
index 4a598cffe..5214e99cf 100644
--- a/src/sst/elements/CramSim/tests/util.py
+++ b/src/sst/elements/CramSim/tests/util.py
@@ -1,30 +1,30 @@
 import sys
 
 def read_arguments():
-	config_file = list()
-        override_list = list()
-        boolDefaultConfig = True;
-
-	for arg in sys.argv:
-            if arg.find("--configfile=") != -1:
-		substrIndex = arg.find("=")+1
-		config_file = arg[substrIndex:]
-		print("Config file:", config_file)
-		boolDefaultConfig = False;
-
-  	    elif arg != sys.argv[0]:
-                if arg.find("=") == -1:
-                    print("Malformed config override found!: ", arg)
-                    exit(-1)
-                override_list.append(arg)
-                print("Override: ", override_list[-1])
-
-	
-	if boolDefaultConfig == True:
-		config_file = "../ddr4_verimem.cfg"
-		print("config file is not specified.. using ddr4_verimem.cfg")
-
-	return [config_file, override_list]
+    config_file = list()
+    override_list = list()
+    boolDefaultConfig = True;
+
+    for arg in sys.argv:
+        if arg.find("--configfile=") != -1:
+            substrIndex = arg.find("=")+1
+            config_file = arg[substrIndex:]
+            print("Config file:", config_file)
+            boolDefaultConfig = False;
+
+        elif arg != sys.argv[0]:
+            if arg.find("=") == -1:
+                print("Malformed config override found!: ", arg)
+                exit(-1)
+            override_list.append(arg)
+            print("Override: ", override_list[-1])
+
+
+    if boolDefaultConfig == True:
+        config_file = "../ddr4_verimem.cfg"
+        print("config file is not specified.. using ddr4_verimem.cfg")
+
+    return [config_file, override_list]
 
 
 
diff --git a/src/sst/elements/GNA/tests/test.ref.out b/src/sst/elements/GNA/tests/test.ref.out
index 2177521f9..4fbc347b8 100644
--- a/src/sst/elements/GNA/tests/test.ref.out
+++ b/src/sst/elements/GNA/tests/test.ref.out
@@ -147,14 +147,14 @@ Completed 245698 spike deliveries
  l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 672305; SumSQ.u64 = 672305; Count.u64 = 672305; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 245696; SumSQ.u64 = 245696; Count.u64 = 245696; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetXResp_recv : Accumulator : Sum.u64 = 34623; SumSQ.u64 = 34623; Count.u64 = 34623; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetXResp_recv : Accumulator : Sum.u64 = 29143; SumSQ.u64 = 29143; Count.u64 = 29143; Min.u64 = 1; Max.u64 = 1; 
  l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/Messier/tests/refFiles/test_Messier_gupsgen.out b/src/sst/elements/Messier/tests/refFiles/test_Messier_gupsgen.out
index befb02528..91d4bfa54 100644
--- a/src/sst/elements/Messier/tests/refFiles/test_Messier_gupsgen.out
+++ b/src/sst/elements/Messier/tests/refFiles/test_Messier_gupsgen.out
@@ -159,9 +159,9 @@ After initialization
  l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 565; SumSQ.u64 = 565; Count.u64 = 565; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 15271; SumSQ.u64 = 15271; Count.u64 = 15271; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 10208; SumSQ.u64 = 10208; Count.u64 = 10208; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 14911; SumSQ.u64 = 14911; Count.u64 = 14911; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/Messier/tests/refFiles/test_Messier_gupsgen_2RANKS.out b/src/sst/elements/Messier/tests/refFiles/test_Messier_gupsgen_2RANKS.out
index 1ee99dc4d..cf71a6789 100644
--- a/src/sst/elements/Messier/tests/refFiles/test_Messier_gupsgen_2RANKS.out
+++ b/src/sst/elements/Messier/tests/refFiles/test_Messier_gupsgen_2RANKS.out
@@ -159,9 +159,9 @@ After initialization
  l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 596; SumSQ.u64 = 596; Count.u64 = 596; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 15306; SumSQ.u64 = 15306; Count.u64 = 15306; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 10217; SumSQ.u64 = 10217; Count.u64 = 10217; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 14923; SumSQ.u64 = 14923; Count.u64 = 14923; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/Messier/tests/refFiles/test_Messier_gupsgen_fastNVM.out b/src/sst/elements/Messier/tests/refFiles/test_Messier_gupsgen_fastNVM.out
index f37bf8fa3..9dd9cecf9 100644
--- a/src/sst/elements/Messier/tests/refFiles/test_Messier_gupsgen_fastNVM.out
+++ b/src/sst/elements/Messier/tests/refFiles/test_Messier_gupsgen_fastNVM.out
@@ -159,9 +159,9 @@ After initialization
  l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 583; SumSQ.u64 = 583; Count.u64 = 583; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 15279; SumSQ.u64 = 15279; Count.u64 = 15279; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 10216; SumSQ.u64 = 10216; Count.u64 = 10216; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 14908; SumSQ.u64 = 14908; Count.u64 = 14908; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/Messier/tests/refFiles/test_Messier_stencil3dbench_messier.out b/src/sst/elements/Messier/tests/refFiles/test_Messier_stencil3dbench_messier.out
index b31ee368f..84ad95fee 100644
--- a/src/sst/elements/Messier/tests/refFiles/test_Messier_stencil3dbench_messier.out
+++ b/src/sst/elements/Messier/tests/refFiles/test_Messier_stencil3dbench_messier.out
@@ -1,19 +1,19 @@
-0:cpu:RequestGenCPU[RequestGenCPU:42]: Configured CPU to allow 16 maximum Load requests to be memory to be outstanding.
-0:cpu:RequestGenCPU[RequestGenCPU:44]: Configured CPU to allow 16 maximum Store requests to be memory to be outstanding.
-0:cpu:RequestGenCPU[RequestGenCPU:46]: Configured CPU to allow 16 maximum Custom requests to be memory to be outstanding.
-0:cpu:RequestGenCPU[RequestGenCPU:53]: CPU clock configured for 2GHz
-0:cpu:RequestGenCPU[RequestGenCPU:58]: Memory interface to be loaded is: memHierarchy.memInterface
-0:cpu:RequestGenCPU[RequestGenCPU:71]: Loaded memory interface successfully.
-0:cpu:RequestGenCPU[RequestGenCPU:105]: Generator loaded successfully.
-0:cpu:RequestGenCPU[RequestGenCPU:161]: Miranda CPU Configuration:
-0:cpu:RequestGenCPU[RequestGenCPU:162]: - Max requests per cycle:         2
-0:cpu:RequestGenCPU[RequestGenCPU:163]: - Max reorder lookups             16
-0:cpu:RequestGenCPU[RequestGenCPU:164]: - Clock:                          2GHz
-0:cpu:RequestGenCPU[RequestGenCPU:165]: - Cache line size:                64 bytes
-0:cpu:RequestGenCPU[RequestGenCPU:166]: - Max Load requests pending:      16
-0:cpu:RequestGenCPU[RequestGenCPU:167]: - Max Store requests pending:     16
-0:cpu:RequestGenCPU[RequestGenCPU:168]: - Max Custom requests pending:     16
-0:cpu:RequestGenCPU[RequestGenCPU:169]: Configuration completed.
+0:cpu:RequestGenCPU[RequestGenCPU:44]: Configured CPU to allow 16 maximum Load requests to be memory to be outstanding.
+0:cpu:RequestGenCPU[RequestGenCPU:46]: Configured CPU to allow 16 maximum Store requests to be memory to be outstanding.
+0:cpu:RequestGenCPU[RequestGenCPU:48]: Configured CPU to allow 16 maximum Custom requests to be memory to be outstanding.
+0:cpu:RequestGenCPU[RequestGenCPU:55]: CPU clock configured for 2GHz
+0:cpu:RequestGenCPU[RequestGenCPU:60]: Memory interface to be loaded is: memHierarchy.memInterface
+0:cpu:RequestGenCPU[RequestGenCPU:73]: Loaded memory interface successfully.
+0:cpu:RequestGenCPU[RequestGenCPU:107]: Generator loaded successfully.
+0:cpu:RequestGenCPU[RequestGenCPU:163]: Miranda CPU Configuration:
+0:cpu:RequestGenCPU[RequestGenCPU:164]: - Max requests per cycle:         2
+0:cpu:RequestGenCPU[RequestGenCPU:165]: - Max reorder lookups             16
+0:cpu:RequestGenCPU[RequestGenCPU:166]: - Clock:                          2GHz
+0:cpu:RequestGenCPU[RequestGenCPU:167]: - Cache line size:                64 bytes
+0:cpu:RequestGenCPU[RequestGenCPU:168]: - Max Load requests pending:      16
+0:cpu:RequestGenCPU[RequestGenCPU:169]: - Max Store requests pending:     16
+0:cpu:RequestGenCPU[RequestGenCPU:170]: - Max Custom requests pending:     16
+0:cpu:RequestGenCPU[RequestGenCPU:171]: Configuration completed.
 The value of tRCD is 300
 After initialization 
  cpu.read_reqs : Accumulator : Sum.u64 = 108864; SumSQ.u64 = 108864; Count.u64 = 108864; Min.u64 = 1; Max.u64 = 1; 
@@ -176,13 +176,13 @@ After initialization
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 155514; SumSQ.u64 = 155514; Count.u64 = 155514; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 6240; SumSQ.u64 = 6240; Count.u64 = 6240; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 114208; SumSQ.u64 = 114208; Count.u64 = 114208; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 4032; SumSQ.u64 = 4032; Count.u64 = 4032; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetXResp_recv : Accumulator : Sum.u64 = 1353; SumSQ.u64 = 1353; Count.u64 = 1353; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetXResp_recv : Accumulator : Sum.u64 = 1303; SumSQ.u64 = 1303; Count.u64 = 1303; Min.u64 = 1; Max.u64 = 1; 
  l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/Messier/tests/refFiles/test_Messier_streambench_messier.out b/src/sst/elements/Messier/tests/refFiles/test_Messier_streambench_messier.out
index 873934efc..f6d6ca795 100644
--- a/src/sst/elements/Messier/tests/refFiles/test_Messier_streambench_messier.out
+++ b/src/sst/elements/Messier/tests/refFiles/test_Messier_streambench_messier.out
@@ -160,8 +160,8 @@ After initialization
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 44204; SumSQ.u64 = 44204; Count.u64 = 44204; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 14921; SumSQ.u64 = 14921; Count.u64 = 14921; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 25810; SumSQ.u64 = 25810; Count.u64 = 25810; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_nbp.out b/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_nbp.out
index 104454aee..2dfe16c69 100644
--- a/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_nbp.out
+++ b/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_nbp.out
@@ -142,13 +142,13 @@ Completed @ 11134750 ns
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 142237; SumSQ.u64 = 142237; Count.u64 = 142237; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 15471; SumSQ.u64 = 15471; Count.u64 = 15471; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 96081; SumSQ.u64 = 96081; Count.u64 = 96081; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 10169; SumSQ.u64 = 10169; Count.u64 = 10169; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetXResp_recv : Accumulator : Sum.u64 = 12522; SumSQ.u64 = 12522; Count.u64 = 12522; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetXResp_recv : Accumulator : Sum.u64 = 12500; SumSQ.u64 = 12500; Count.u64 = 12500; Min.u64 = 1; Max.u64 = 1; 
  l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_nopf.out b/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_nopf.out
index 2b11a1118..65ecae26f 100644
--- a/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_nopf.out
+++ b/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_nopf.out
@@ -132,13 +132,13 @@ Completed @ 11524920 ns
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 162504; SumSQ.u64 = 162504; Count.u64 = 162504; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 18347; SumSQ.u64 = 18347; Count.u64 = 18347; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 89828; SumSQ.u64 = 89828; Count.u64 = 89828; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 10172; SumSQ.u64 = 10172; Count.u64 = 10172; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetXResp_recv : Accumulator : Sum.u64 = 12527; SumSQ.u64 = 12527; Count.u64 = 12527; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetXResp_recv : Accumulator : Sum.u64 = 12500; SumSQ.u64 = 12500; Count.u64 = 12500; Min.u64 = 1; Max.u64 = 1; 
  l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_pp.out b/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_pp.out
index e84fc9220..9084a7514 100644
--- a/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_pp.out
+++ b/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_pp.out
@@ -143,13 +143,13 @@ Completed @ 11197483 ns
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 164965; SumSQ.u64 = 164965; Count.u64 = 164965; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 17190; SumSQ.u64 = 17190; Count.u64 = 17190; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 102379; SumSQ.u64 = 102379; Count.u64 = 102379; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 10121; SumSQ.u64 = 10121; Count.u64 = 10121; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetXResp_recv : Accumulator : Sum.u64 = 12553; SumSQ.u64 = 12553; Count.u64 = 12553; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetXResp_recv : Accumulator : Sum.u64 = 12500; SumSQ.u64 = 12500; Count.u64 = 12500; Min.u64 = 1; Max.u64 = 1; 
  l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_sp.out b/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_sp.out
index 1c586337a..d84597eb6 100644
--- a/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_sp.out
+++ b/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_sp.out
@@ -143,13 +143,13 @@ Completed @ 11074943 ns
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 182611; SumSQ.u64 = 182611; Count.u64 = 182611; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 18496; SumSQ.u64 = 18496; Count.u64 = 18496; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 102152; SumSQ.u64 = 102152; Count.u64 = 102152; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 10153; SumSQ.u64 = 10153; Count.u64 = 10153; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetXResp_recv : Accumulator : Sum.u64 = 12542; SumSQ.u64 = 12542; Count.u64 = 12542; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetXResp_recv : Accumulator : Sum.u64 = 12500; SumSQ.u64 = 12500; Count.u64 = 12500; Min.u64 = 1; Max.u64 = 1; 
  l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/cacheController.cc b/src/sst/elements/memHierarchy/cacheController.cc
index 9d1302e93..498392f42 100644
--- a/src/sst/elements/memHierarchy/cacheController.cc
+++ b/src/sst/elements/memHierarchy/cacheController.cc
@@ -45,10 +45,22 @@ void Cache::handleEvent(SST::Event * ev) {
     if (CommandClassArr[(int)event->getCmd()] == CommandClass::Request && !CommandWriteback[(int)event->getCmd()])
         coherenceMgr_->recordIncomingRequest(event);
 
+    // Record that an event was received
+    if (MemEventTypeArr[(int)event->getCmd()] != MemEventType::Cache || event->queryFlag(MemEventBase::F_NONCACHEABLE)) {
+        statUncacheRecv[(int)event->getCmd()]->addData(1);
+    } else {
+        statCacheRecv[(int)event->getCmd()]->addData(1);
+    }
+
     eventBuffer_.push_back(event);
 }
 
-/* Handle event from cache listener (prefetcher) */
+/* 
+ * Handle event from cache listener (prefetcher) 
+ * -> Delay prefetch using a self link since prefetcher can 
+ *  return a prefetch request in the same cycle it identifies
+ *  a prefetch target
+ */
 void Cache::handlePrefetchEvent(SST::Event * ev) {
     prefetchSelfLink_->send(prefetchDelay_, ev);
 }
@@ -66,6 +78,7 @@ void Cache::processPrefetchEvent(SST::Event * ev) {
 
     // Record received prefetch
     statPrefetchRequest->addData(1);
+    statCacheRecv[(int)event->getCmd()]->addData(1);
     prefetchBuffer_.push(event);
 }
 
@@ -213,13 +226,10 @@ bool Cache::processEvent(MemEventBase* ev, bool inMSHR) {
     }
 
     if (MemEventTypeArr[(int)ev->getCmd()] != MemEventType::Cache || ev->queryFlag(MemEventBase::F_NONCACHEABLE)) {
-        statUncacheRecv[(int)ev->getCmd()]->addData(1);
         processNoncacheable(ev);
         return true;
     }
 
-    statCacheRecv[(int)ev->getCmd()]->addData(1);
-
     /* Handle cache events */
     MemEvent * event = static_cast<MemEvent*>(ev);
 
diff --git a/src/sst/elements/memHierarchy/memoryController.cc b/src/sst/elements/memHierarchy/memoryController.cc
index fa2193cdd..3ee6601c4 100644
--- a/src/sst/elements/memHierarchy/memoryController.cc
+++ b/src/sst/elements/memHierarchy/memoryController.cc
@@ -109,7 +109,14 @@ MemController::MemController(ComponentId_t id, Params &params) : Component(id),
 
     MemBackend * memory = loadUserSubComponent<MemBackend>("backend");
     if (!memory) {  /* Try to load from our parameters (legacy mode 1) */
-        out.output("%s, WARNING: loading backend in legacy mode (from parameter set). Instead, load backend into this controller's 'backend' slot via ctrl.setSubComponent() in configuration.\n", getName().c_str());
+        /* Check if there's an error with the subcomponent the user specified */
+        SubComponentSlotInfo * info = getSubComponentSlotInfo("backend");
+        if (info && info->isPopulated(0)) {
+            out.fatal(CALL_INFO, -1, "%s, ERROR: Unable to load the subcomponent in the 'backend' slot. Check that the requested subcomponent is registered with the SST core.\n", 
+                    getName().c_str());
+        } else {
+            out.output("%s, WARNING: loading backend in legacy mode (from parameter set). Instead, load backend into this controller's 'backend' slot via ctrl.setSubComponent() in configuration.\n", getName().c_str());
+        }
         Params tmpParams = params.find_prefix_params("backendConvertor.backend.");
         std::string name = params.find<std::string>("backendConvertor.backend", "memHierarchy.simpleMem");
         memory = loadAnonymousSubComponent<MemBackend>(name, "backend", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, tmpParams);
@@ -331,6 +338,38 @@ void MemController::handleEvent(SST::Event* event) {
 
     MemEvent * ev = static_cast<MemEvent*>(meb);
 
+#ifdef __SST_DEBUG_OUTPUT__
+    // Check that the request address(es) belong to this memory
+    // Disabled except in debug mode
+    if (!region_.contains(ev->getBaseAddr())) {
+        out.fatal(CALL_INFO, -1, "%s, Error: Received an event with a base address that does not map to this controller. Event: %s\n", getName().c_str(), ev->getVerboseString().c_str());
+    }
+    if (!region_.contains(ev->getAddr())) {
+        out.fatal(CALL_INFO, -1, "%s, Error: Received an event with an address that does not map to this controller. Event: %s\n", getName().c_str(), ev->getVerboseString().c_str());
+    }
+    
+    bool noncacheable = ev->queryFlag(MemEvent::F_NONCACHEABLE);
+    Addr chkAddr = noncacheable ? ev->getAddr() : ev->getBaseAddr();
+
+    if (region_.interleaveStep != 0 && ev->getSize() > 0) {  // Non-contiguous address region so make sure this request doesn't fall outside the region
+        Addr a0 = (chkAddr - region_.start) / region_.interleaveStep; 
+        a0 = a0 * region_.interleaveStep + region_.start; // Address of the interleave chunk that contains the target address
+        Addr b0 = a0 + region_.interleaveSize - 1; // Last address in the interleave chunk that contains the target starting address
+        Addr a1 = a0 + region_.interleaveStep; // Address of the next interleave chunk
+
+        // If the request size is larger than one of our interleaved chunks
+        // then the only way for it to completely fall in our region is if our interleaving is contiguous (e.g., not reall interleaving)
+        if (b0 < (chkAddr + ev->getSize() - 1)) {
+            if ((b0 + 1) != a1) {
+                out.fatal(CALL_INFO, -1, "%s: Error: Received an event for an address range that does not map to this controller. Event: %s\n", getName().c_str(), ev->getVerboseString().c_str());
+            }
+        }
+    } else if (ev->getSize() > 0) { // Contiguous address region, make sure last address of request falls in region
+        if (!region_.contains(chkAddr + ev->getSize() - 1))
+        out.fatal(CALL_INFO, -1, "%s, Error: Received an event for an address range that does not map to this controller. Event: %s\n", getName().c_str(), ev->getVerboseString().c_str());
+    }
+#endif
+
     if (ev->isAddrGlobal()) {
         ev->setBaseAddr(translateToLocal(ev->getBaseAddr()));
         ev->setAddr(translateToLocal(ev->getAddr()));
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendChaining.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendChaining.out
index 134803edc..d97390366 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendChaining.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendChaining.out
@@ -145,9 +145,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (63340 clocks)
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 475; SumSQ.u64 = 475; Count.u64 = 475; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 1331; SumSQ.u64 = 1331; Count.u64 = 1331; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 898; SumSQ.u64 = 898; Count.u64 = 898; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -299,9 +299,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (63340 clocks)
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 515; SumSQ.u64 = 515; Count.u64 = 515; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1345; SumSQ.u64 = 1345; Count.u64 = 1345; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 887; SumSQ.u64 = 887; Count.u64 = 887; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -520,7 +520,7 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (63340 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1789; SumSQ.u64 = 1789; Count.u64 = 1789; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1780; SumSQ.u64 = 1780; Count.u64 = 1780; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -532,11 +532,11 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (63340 clocks)
  n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 1385; SumSQ.u64 = 1385; Count.u64 = 1385; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1345; SumSQ.u64 = 1345; Count.u64 = 1345; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1083; SumSQ.u64 = 1083; Count.u64 = 1083; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -680,9 +680,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (63340 clocks)
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 507; SumSQ.u64 = 507; Count.u64 = 507; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 1359; SumSQ.u64 = 1359; Count.u64 = 1359; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 896; SumSQ.u64 = 896; Count.u64 = 896; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -834,9 +834,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (63340 clocks)
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 499; SumSQ.u64 = 499; Count.u64 = 499; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 1352; SumSQ.u64 = 1352; Count.u64 = 1352; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 897; SumSQ.u64 = 897; Count.u64 = 897; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1055,8 +1055,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (63340 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1796; SumSQ.u64 = 1796; Count.u64 = 1796; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 209; SumSQ.u64 = 209; Count.u64 = 209; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1789; SumSQ.u64 = 1789; Count.u64 = 1789; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1067,11 +1067,11 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (63340 clocks)
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 1388; SumSQ.u64 = 1388; Count.u64 = 1388; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1298; SumSQ.u64 = 1298; Count.u64 = 1298; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1026; SumSQ.u64 = 1026; Count.u64 = 1026; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 271; SumSQ.u64 = 271; Count.u64 = 271; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1285,9 +1285,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (63340 clocks)
  l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 2167; SumSQ.u64 = 2167; Count.u64 = 2167; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 5506; SumSQ.u64 = 5506; Count.u64 = 5506; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 638; SumSQ.u64 = 638; Count.u64 = 638; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 3496; SumSQ.u64 = 3496; Count.u64 = 3496; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 408; SumSQ.u64 = 408; Count.u64 = 408; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendChaining_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendChaining_MC.out
index 1df9f7ed8..961db33e9 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendChaining_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendChaining_MC.out
@@ -145,9 +145,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (61099 clocks)
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 475; SumSQ.u64 = 475; Count.u64 = 475; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 1331; SumSQ.u64 = 1331; Count.u64 = 1331; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 898; SumSQ.u64 = 898; Count.u64 = 898; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -299,9 +299,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (61099 clocks)
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 515; SumSQ.u64 = 515; Count.u64 = 515; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1345; SumSQ.u64 = 1345; Count.u64 = 1345; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 887; SumSQ.u64 = 887; Count.u64 = 887; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -520,7 +520,7 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (61099 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1789; SumSQ.u64 = 1789; Count.u64 = 1789; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1780; SumSQ.u64 = 1780; Count.u64 = 1780; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -532,11 +532,11 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (61099 clocks)
  n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 1385; SumSQ.u64 = 1385; Count.u64 = 1385; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1345; SumSQ.u64 = 1345; Count.u64 = 1345; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1083; SumSQ.u64 = 1083; Count.u64 = 1083; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -680,9 +680,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (61099 clocks)
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 507; SumSQ.u64 = 507; Count.u64 = 507; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 1359; SumSQ.u64 = 1359; Count.u64 = 1359; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 896; SumSQ.u64 = 896; Count.u64 = 896; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -834,9 +834,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (61099 clocks)
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 499; SumSQ.u64 = 499; Count.u64 = 499; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 1352; SumSQ.u64 = 1352; Count.u64 = 1352; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 897; SumSQ.u64 = 897; Count.u64 = 897; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1055,8 +1055,8 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (61099 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1796; SumSQ.u64 = 1796; Count.u64 = 1796; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 209; SumSQ.u64 = 209; Count.u64 = 209; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1789; SumSQ.u64 = 1789; Count.u64 = 1789; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1067,11 +1067,11 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (61099 clocks)
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 1388; SumSQ.u64 = 1388; Count.u64 = 1388; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1298; SumSQ.u64 = 1298; Count.u64 = 1298; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1026; SumSQ.u64 = 1026; Count.u64 = 1026; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 271; SumSQ.u64 = 271; Count.u64 = 271; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1285,9 +1285,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (61099 clocks)
  l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 2167; SumSQ.u64 = 2167; Count.u64 = 2167; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 5506; SumSQ.u64 = 5506; Count.u64 = 5506; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 638; SumSQ.u64 = 638; Count.u64 = 638; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 3496; SumSQ.u64 = 3496; Count.u64 = 3496; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 408; SumSQ.u64 = 408; Count.u64 = 408; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendDelayBuffer.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendDelayBuffer.out
index 6b6bc8cc3..b7948de8a 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendDelayBuffer.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendDelayBuffer.out
@@ -145,9 +145,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (457009 clocks)
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 496; SumSQ.u64 = 496; Count.u64 = 496; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 1355; SumSQ.u64 = 1355; Count.u64 = 1355; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 901; SumSQ.u64 = 901; Count.u64 = 901; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -299,9 +299,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (457009 clocks)
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 482; SumSQ.u64 = 482; Count.u64 = 482; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1336; SumSQ.u64 = 1336; Count.u64 = 1336; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 901; SumSQ.u64 = 901; Count.u64 = 901; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -520,8 +520,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (457009 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1804; SumSQ.u64 = 1804; Count.u64 = 1804; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1796; SumSQ.u64 = 1796; Count.u64 = 1796; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -532,11 +532,11 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (457009 clocks)
  n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 1381; SumSQ.u64 = 1381; Count.u64 = 1381; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1335; SumSQ.u64 = 1335; Count.u64 = 1335; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1058; SumSQ.u64 = 1058; Count.u64 = 1058; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 275; SumSQ.u64 = 275; Count.u64 = 275; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -680,9 +680,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (457009 clocks)
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 455; SumSQ.u64 = 455; Count.u64 = 455; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 1331; SumSQ.u64 = 1331; Count.u64 = 1331; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -834,9 +834,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (457009 clocks)
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 414; SumSQ.u64 = 414; Count.u64 = 414; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 1299; SumSQ.u64 = 1299; Count.u64 = 1299; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 916; SumSQ.u64 = 916; Count.u64 = 916; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1055,7 +1055,7 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (457009 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1827; SumSQ.u64 = 1827; Count.u64 = 1827; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1820; SumSQ.u64 = 1820; Count.u64 = 1820; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1067,11 +1067,11 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (457009 clocks)
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 1413; SumSQ.u64 = 1413; Count.u64 = 1413; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1307; SumSQ.u64 = 1307; Count.u64 = 1307; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1055; SumSQ.u64 = 1055; Count.u64 = 1055; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 248; SumSQ.u64 = 248; Count.u64 = 248; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1285,9 +1285,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (457009 clocks)
  l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 2176; SumSQ.u64 = 2176; Count.u64 = 2176; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 5615; SumSQ.u64 = 5615; Count.u64 = 5615; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 576; SumSQ.u64 = 576; Count.u64 = 576; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 3556; SumSQ.u64 = 3556; Count.u64 = 3556; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendDelayBuffer_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendDelayBuffer_MC.out
index f3dd4173e..c0d121165 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendDelayBuffer_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendDelayBuffer_MC.out
@@ -145,9 +145,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (472129 clocks)
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 496; SumSQ.u64 = 496; Count.u64 = 496; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 1355; SumSQ.u64 = 1355; Count.u64 = 1355; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 901; SumSQ.u64 = 901; Count.u64 = 901; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -299,9 +299,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (472129 clocks)
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 482; SumSQ.u64 = 482; Count.u64 = 482; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1336; SumSQ.u64 = 1336; Count.u64 = 1336; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 901; SumSQ.u64 = 901; Count.u64 = 901; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -520,8 +520,8 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (472129 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1804; SumSQ.u64 = 1804; Count.u64 = 1804; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1796; SumSQ.u64 = 1796; Count.u64 = 1796; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -532,11 +532,11 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (472129 clocks)
  n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 1381; SumSQ.u64 = 1381; Count.u64 = 1381; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1335; SumSQ.u64 = 1335; Count.u64 = 1335; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1058; SumSQ.u64 = 1058; Count.u64 = 1058; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 275; SumSQ.u64 = 275; Count.u64 = 275; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -680,9 +680,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (472129 clocks)
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 455; SumSQ.u64 = 455; Count.u64 = 455; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 1331; SumSQ.u64 = 1331; Count.u64 = 1331; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -834,9 +834,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (472129 clocks)
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 414; SumSQ.u64 = 414; Count.u64 = 414; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 1299; SumSQ.u64 = 1299; Count.u64 = 1299; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 916; SumSQ.u64 = 916; Count.u64 = 916; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1055,7 +1055,7 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (472129 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1827; SumSQ.u64 = 1827; Count.u64 = 1827; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1820; SumSQ.u64 = 1820; Count.u64 = 1820; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1067,11 +1067,11 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (472129 clocks)
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 1413; SumSQ.u64 = 1413; Count.u64 = 1413; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1307; SumSQ.u64 = 1307; Count.u64 = 1307; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1055; SumSQ.u64 = 1055; Count.u64 = 1055; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 248; SumSQ.u64 = 248; Count.u64 = 248; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1285,9 +1285,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (472129 clocks)
  l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 2176; SumSQ.u64 = 2176; Count.u64 = 2176; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 5615; SumSQ.u64 = 5615; Count.u64 = 5615; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 576; SumSQ.u64 = 576; Count.u64 = 576; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 3556; SumSQ.u64 = 3556; Count.u64 = 3556; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendGoblinHMC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendGoblinHMC.out
index 21c3d0fd1..71c0ede71 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendGoblinHMC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendGoblinHMC.out
@@ -278,9 +278,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (471149 clocks)
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 896; SumSQ.u64 = 896; Count.u64 = 896; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 890; SumSQ.u64 = 890; Count.u64 = 890; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -464,7 +464,7 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (471149 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1778; SumSQ.u64 = 1778; Count.u64 = 1778; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1777; SumSQ.u64 = 1777; Count.u64 = 1777; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 213; SumSQ.u64 = 213; Count.u64 = 213; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -476,11 +476,11 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (471149 clocks)
  n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -616,7 +616,7 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (471149 clocks)
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 900; SumSQ.u64 = 900; Count.u64 = 900; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 899; SumSQ.u64 = 899; Count.u64 = 899; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -760,8 +760,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (471149 clocks)
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 911; SumSQ.u64 = 911; Count.u64 = 911; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -946,7 +946,7 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (471149 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1802; SumSQ.u64 = 1802; Count.u64 = 1802; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1797; SumSQ.u64 = 1797; Count.u64 = 1797; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -962,7 +962,7 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (471149 clocks)
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1142,8 +1142,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (471149 clocks)
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 3511; SumSQ.u64 = 3511; Count.u64 = 3511; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 405; SumSQ.u64 = 405; Count.u64 = 405; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 3489; SumSQ.u64 = 3489; Count.u64 = 3489; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 403; SumSQ.u64 = 403; Count.u64 = 403; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendGoblinHMC_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendGoblinHMC_MC.out
index 36408c6d1..a2bc352cb 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendGoblinHMC_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendGoblinHMC_MC.out
@@ -2,10 +2,10 @@ TrivialCPU: Test Completed Successfuly
 TrivialCPU: Test Completed Successfuly
 TrivialCPU: Test Completed Successfuly
 TrivialCPU: Test Completed Successfuly
-TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (471149 clocks)
-TrivialCPU cpu2 Finished after 1000 issued reads, 1000 returned (466757 clocks)
-TrivialCPU cpu1 Finished after 1000 issued reads, 1000 returned (465461 clocks)
 TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (470717 clocks)
+TrivialCPU cpu1 Finished after 1000 issued reads, 1000 returned (465461 clocks)
+TrivialCPU cpu2 Finished after 1000 issued reads, 1000 returned (466757 clocks)
+TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (471149 clocks)
  cpu0.pendCycle : Accumulator : Sum.u64 = 4581674; SumSQ.u64 = 44798204; Count.u64 = 470717; Min.u64 = 0; Max.u64 = 10; 
  c0.l1cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 891; SumSQ.u64 = 891; Count.u64 = 891; Min.u64 = 1; Max.u64 = 1; 
@@ -278,9 +278,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (470717 clocks)
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 896; SumSQ.u64 = 896; Count.u64 = 896; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 890; SumSQ.u64 = 890; Count.u64 = 890; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -476,11 +476,11 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (470717 clocks)
  n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -616,7 +616,7 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (470717 clocks)
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 900; SumSQ.u64 = 900; Count.u64 = 900; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 899; SumSQ.u64 = 899; Count.u64 = 899; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -760,8 +760,8 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (470717 clocks)
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 911; SumSQ.u64 = 911; Count.u64 = 911; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -946,7 +946,7 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (470717 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1802; SumSQ.u64 = 1802; Count.u64 = 1802; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1797; SumSQ.u64 = 1797; Count.u64 = 1797; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -962,7 +962,7 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (470717 clocks)
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1142,8 +1142,8 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (470717 clocks)
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 3511; SumSQ.u64 = 3511; Count.u64 = 3511; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 405; SumSQ.u64 = 405; Count.u64 = 405; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 3489; SumSQ.u64 = 3489; Count.u64 = 3489; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 403; SumSQ.u64 = 403; Count.u64 = 403; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMDramsim.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMDramsim.out
index b06c79fcb..7056b7fb8 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMDramsim.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMDramsim.out
@@ -149,9 +149,9 @@ Channel 7 statistics
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 937; SumSQ.u64 = 937; Count.u64 = 937; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 897; SumSQ.u64 = 897; Count.u64 = 897; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -294,9 +294,9 @@ Channel 7 statistics
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 916; SumSQ.u64 = 916; Count.u64 = 916; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 881; SumSQ.u64 = 881; Count.u64 = 881; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -480,8 +480,8 @@ Channel 7 statistics
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1746; SumSQ.u64 = 1746; Count.u64 = 1746; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 221; SumSQ.u64 = 221; Count.u64 = 221; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1733; SumSQ.u64 = 1733; Count.u64 = 1733; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 220; SumSQ.u64 = 220; Count.u64 = 220; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -492,11 +492,11 @@ Channel 7 statistics
  n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -631,9 +631,9 @@ Channel 7 statistics
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 943; SumSQ.u64 = 943; Count.u64 = 943; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 899; SumSQ.u64 = 899; Count.u64 = 899; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -776,9 +776,9 @@ Channel 7 statistics
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 918; SumSQ.u64 = 918; Count.u64 = 918; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 885; SumSQ.u64 = 885; Count.u64 = 885; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -962,8 +962,8 @@ Channel 7 statistics
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1738; SumSQ.u64 = 1738; Count.u64 = 1738; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 216; SumSQ.u64 = 216; Count.u64 = 216; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1728; SumSQ.u64 = 1728; Count.u64 = 1728; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -974,11 +974,11 @@ Channel 7 statistics
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1158,12 +1158,12 @@ Channel 7 statistics
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 3189; SumSQ.u64 = 3189; Count.u64 = 3189; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 480; SumSQ.u64 = 480; Count.u64 = 480; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 3139; SumSQ.u64 = 3139; Count.u64 = 3139; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 429; SumSQ.u64 = 429; Count.u64 = 429; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetSResp_recv : Accumulator : Sum.u64 = 449; SumSQ.u64 = 449; Count.u64 = 449; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetSResp_recv : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetXResp_recv : Accumulator : Sum.u64 = 298; SumSQ.u64 = 298; Count.u64 = 298; Min.u64 = 1; Max.u64 = 1; 
  l3cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.PutS_recv : Accumulator : Sum.u64 = 2972; SumSQ.u64 = 2972; Count.u64 = 2972; Min.u64 = 1; Max.u64 = 1; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMDramsim_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMDramsim_MC.out
index 2e63bf38b..7056b7fb8 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMDramsim_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMDramsim_MC.out
@@ -22,8 +22,6 @@ Channel 6 statistics
 Channel 7 statistics
  Total Return Transactions: 32 (1024 bytes) aggregate average bandwidth 0.046GB/s
  Rank 0 -  Reads: 32 (1024 bytes) Writes: 0 (0 bytes)
-== Loading device model file 'ddr_device.ini' ==
-== Loading system model file 'ddr_system.ini' ==
  cpu0.pendCycle : Accumulator : Sum.u64 = 47113; SumSQ.u64 = 185567; Count.u64 = 19687; Min.u64 = 0; Max.u64 = 10; 
  c0.l1cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 870; SumSQ.u64 = 870; Count.u64 = 870; Min.u64 = 1; Max.u64 = 1; 
@@ -151,9 +149,9 @@ Channel 7 statistics
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 937; SumSQ.u64 = 937; Count.u64 = 937; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 897; SumSQ.u64 = 897; Count.u64 = 897; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -296,9 +294,9 @@ Channel 7 statistics
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 916; SumSQ.u64 = 916; Count.u64 = 916; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 881; SumSQ.u64 = 881; Count.u64 = 881; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -482,8 +480,8 @@ Channel 7 statistics
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1746; SumSQ.u64 = 1746; Count.u64 = 1746; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 221; SumSQ.u64 = 221; Count.u64 = 221; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1733; SumSQ.u64 = 1733; Count.u64 = 1733; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 220; SumSQ.u64 = 220; Count.u64 = 220; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -494,11 +492,11 @@ Channel 7 statistics
  n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -633,9 +631,9 @@ Channel 7 statistics
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 943; SumSQ.u64 = 943; Count.u64 = 943; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 899; SumSQ.u64 = 899; Count.u64 = 899; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -778,9 +776,9 @@ Channel 7 statistics
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 918; SumSQ.u64 = 918; Count.u64 = 918; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 885; SumSQ.u64 = 885; Count.u64 = 885; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -964,8 +962,8 @@ Channel 7 statistics
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1738; SumSQ.u64 = 1738; Count.u64 = 1738; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 216; SumSQ.u64 = 216; Count.u64 = 216; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1728; SumSQ.u64 = 1728; Count.u64 = 1728; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -976,11 +974,11 @@ Channel 7 statistics
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1160,12 +1158,12 @@ Channel 7 statistics
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 3189; SumSQ.u64 = 3189; Count.u64 = 3189; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 480; SumSQ.u64 = 480; Count.u64 = 480; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 3139; SumSQ.u64 = 3139; Count.u64 = 3139; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 429; SumSQ.u64 = 429; Count.u64 = 429; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetSResp_recv : Accumulator : Sum.u64 = 449; SumSQ.u64 = 449; Count.u64 = 449; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetSResp_recv : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetXResp_recv : Accumulator : Sum.u64 = 298; SumSQ.u64 = 298; Count.u64 = 298; Min.u64 = 1; Max.u64 = 1; 
  l3cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.PutS_recv : Accumulator : Sum.u64 = 2972; SumSQ.u64 = 2972; Count.u64 = 2972; Min.u64 = 1; Max.u64 = 1; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMDramsim_MR.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMDramsim_MR.out
index 2e63bf38b..7056b7fb8 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMDramsim_MR.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMDramsim_MR.out
@@ -22,8 +22,6 @@ Channel 6 statistics
 Channel 7 statistics
  Total Return Transactions: 32 (1024 bytes) aggregate average bandwidth 0.046GB/s
  Rank 0 -  Reads: 32 (1024 bytes) Writes: 0 (0 bytes)
-== Loading device model file 'ddr_device.ini' ==
-== Loading system model file 'ddr_system.ini' ==
  cpu0.pendCycle : Accumulator : Sum.u64 = 47113; SumSQ.u64 = 185567; Count.u64 = 19687; Min.u64 = 0; Max.u64 = 10; 
  c0.l1cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 870; SumSQ.u64 = 870; Count.u64 = 870; Min.u64 = 1; Max.u64 = 1; 
@@ -151,9 +149,9 @@ Channel 7 statistics
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 937; SumSQ.u64 = 937; Count.u64 = 937; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 897; SumSQ.u64 = 897; Count.u64 = 897; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -296,9 +294,9 @@ Channel 7 statistics
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 916; SumSQ.u64 = 916; Count.u64 = 916; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 881; SumSQ.u64 = 881; Count.u64 = 881; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -482,8 +480,8 @@ Channel 7 statistics
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1746; SumSQ.u64 = 1746; Count.u64 = 1746; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 221; SumSQ.u64 = 221; Count.u64 = 221; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1733; SumSQ.u64 = 1733; Count.u64 = 1733; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 220; SumSQ.u64 = 220; Count.u64 = 220; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -494,11 +492,11 @@ Channel 7 statistics
  n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -633,9 +631,9 @@ Channel 7 statistics
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 943; SumSQ.u64 = 943; Count.u64 = 943; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 899; SumSQ.u64 = 899; Count.u64 = 899; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -778,9 +776,9 @@ Channel 7 statistics
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 918; SumSQ.u64 = 918; Count.u64 = 918; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 885; SumSQ.u64 = 885; Count.u64 = 885; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -964,8 +962,8 @@ Channel 7 statistics
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1738; SumSQ.u64 = 1738; Count.u64 = 1738; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 216; SumSQ.u64 = 216; Count.u64 = 216; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1728; SumSQ.u64 = 1728; Count.u64 = 1728; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -976,11 +974,11 @@ Channel 7 statistics
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1160,12 +1158,12 @@ Channel 7 statistics
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 3189; SumSQ.u64 = 3189; Count.u64 = 3189; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 480; SumSQ.u64 = 480; Count.u64 = 480; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 3139; SumSQ.u64 = 3139; Count.u64 = 3139; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 429; SumSQ.u64 = 429; Count.u64 = 429; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetSResp_recv : Accumulator : Sum.u64 = 449; SumSQ.u64 = 449; Count.u64 = 449; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetSResp_recv : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetXResp_recv : Accumulator : Sum.u64 = 298; SumSQ.u64 = 298; Count.u64 = 298; Min.u64 = 1; Max.u64 = 1; 
  l3cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.PutS_recv : Accumulator : Sum.u64 = 2972; SumSQ.u64 = 2972; Count.u64 = 2972; Min.u64 = 1; Max.u64 = 1; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMPagedMulti.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMPagedMulti.out
index a136d73ec..2885d3092 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMPagedMulti.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMPagedMulti.out
@@ -162,9 +162,9 @@ Channel 7 statistics
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 4697; SumSQ.u64 = 4697; Count.u64 = 4697; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 13212; SumSQ.u64 = 13212; Count.u64 = 13212; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 1492; SumSQ.u64 = 1492; Count.u64 = 1492; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 8999; SumSQ.u64 = 8999; Count.u64 = 8999; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 1001; SumSQ.u64 = 1001; Count.u64 = 1001; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -316,9 +316,9 @@ Channel 7 statistics
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 457; SumSQ.u64 = 457; Count.u64 = 457; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1316; SumSQ.u64 = 1316; Count.u64 = 1316; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 907; SumSQ.u64 = 907; Count.u64 = 907; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -537,8 +537,8 @@ Channel 7 statistics
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 9876; SumSQ.u64 = 9876; Count.u64 = 9876; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 1090; SumSQ.u64 = 1090; Count.u64 = 1090; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 9858; SumSQ.u64 = 9858; Count.u64 = 9858; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 1089; SumSQ.u64 = 1089; Count.u64 = 1089; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -549,11 +549,11 @@ Channel 7 statistics
  n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 1027; SumSQ.u64 = 1027; Count.u64 = 1027; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 9057; SumSQ.u64 = 9057; Count.u64 = 9057; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 5135; SumSQ.u64 = 5135; Count.u64 = 5135; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 4446; SumSQ.u64 = 4446; Count.u64 = 4446; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 676; SumSQ.u64 = 676; Count.u64 = 676; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -697,9 +697,9 @@ Channel 7 statistics
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 480; SumSQ.u64 = 480; Count.u64 = 480; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 1324; SumSQ.u64 = 1324; Count.u64 = 1324; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 899; SumSQ.u64 = 899; Count.u64 = 899; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -851,9 +851,9 @@ Channel 7 statistics
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 496; SumSQ.u64 = 496; Count.u64 = 496; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 1339; SumSQ.u64 = 1339; Count.u64 = 1339; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 902; SumSQ.u64 = 902; Count.u64 = 902; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1072,8 +1072,8 @@ Channel 7 statistics
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1802; SumSQ.u64 = 1802; Count.u64 = 1802; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 200; SumSQ.u64 = 200; Count.u64 = 200; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1794; SumSQ.u64 = 1794; Count.u64 = 1794; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1084,11 +1084,11 @@ Channel 7 statistics
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 1378; SumSQ.u64 = 1378; Count.u64 = 1378; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1835; SumSQ.u64 = 1835; Count.u64 = 1835; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1459; SumSQ.u64 = 1459; Count.u64 = 1459; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1302,9 +1302,9 @@ Channel 7 statistics
  l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 6009; SumSQ.u64 = 6009; Count.u64 = 6009; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 16861; SumSQ.u64 = 16861; Count.u64 = 16861; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 1872; SumSQ.u64 = 1872; Count.u64 = 1872; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 11354; SumSQ.u64 = 11354; Count.u64 = 11354; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 1260; SumSQ.u64 = 1260; Count.u64 = 1260; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendPagedMulti.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendPagedMulti.out
index 88bbda4a9..fbac807f9 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendPagedMulti.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendPagedMulti.out
@@ -146,9 +146,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (472116 clocks)
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 4840; SumSQ.u64 = 4840; Count.u64 = 4840; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 13358; SumSQ.u64 = 13358; Count.u64 = 13358; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 1489; SumSQ.u64 = 1489; Count.u64 = 1489; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 9000; SumSQ.u64 = 9000; Count.u64 = 9000; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -300,9 +300,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (472116 clocks)
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 451; SumSQ.u64 = 451; Count.u64 = 451; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1312; SumSQ.u64 = 1312; Count.u64 = 1312; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 904; SumSQ.u64 = 904; Count.u64 = 904; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -521,8 +521,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (472116 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 9885; SumSQ.u64 = 9885; Count.u64 = 9885; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 1088; SumSQ.u64 = 1088; Count.u64 = 1088; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 9875; SumSQ.u64 = 9875; Count.u64 = 9875; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 1087; SumSQ.u64 = 1087; Count.u64 = 1087; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -533,11 +533,11 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (472116 clocks)
  n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 1020; SumSQ.u64 = 1020; Count.u64 = 1020; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 9076; SumSQ.u64 = 9076; Count.u64 = 9076; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 5137; SumSQ.u64 = 5137; Count.u64 = 5137; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 4430; SumSQ.u64 = 4430; Count.u64 = 4430; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 702; SumSQ.u64 = 702; Count.u64 = 702; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -681,9 +681,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (472116 clocks)
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 455; SumSQ.u64 = 455; Count.u64 = 455; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 1301; SumSQ.u64 = 1301; Count.u64 = 1301; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 898; SumSQ.u64 = 898; Count.u64 = 898; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -835,9 +835,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (472116 clocks)
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 460; SumSQ.u64 = 460; Count.u64 = 460; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 1345; SumSQ.u64 = 1345; Count.u64 = 1345; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 917; SumSQ.u64 = 917; Count.u64 = 917; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1056,8 +1056,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (472116 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1817; SumSQ.u64 = 1817; Count.u64 = 1817; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1812; SumSQ.u64 = 1812; Count.u64 = 1812; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1068,11 +1068,11 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (472116 clocks)
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 1397; SumSQ.u64 = 1397; Count.u64 = 1397; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1829; SumSQ.u64 = 1829; Count.u64 = 1829; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1464; SumSQ.u64 = 1464; Count.u64 = 1464; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 361; SumSQ.u64 = 361; Count.u64 = 361; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1286,9 +1286,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (472116 clocks)
  l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 5999; SumSQ.u64 = 5999; Count.u64 = 5999; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 16900; SumSQ.u64 = 16900; Count.u64 = 16900; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 1833; SumSQ.u64 = 1833; Count.u64 = 1833; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 11388; SumSQ.u64 = 11388; Count.u64 = 11388; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 1238; SumSQ.u64 = 1238; Count.u64 = 1238; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendPagedMulti_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendPagedMulti_MC.out
index bb6e37aaf..fbac807f9 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendPagedMulti_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendPagedMulti_MC.out
@@ -5,11 +5,11 @@ TrivialCPU: Test Completed Successfuly
 TrivialCPU: Test Completed Successfuly
 TrivialCPU: Test Completed Successfuly
 TrivialCPU: Test Completed Successfuly
-TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (472116 clocks)
 fast_t_pages: 1024
-TrivialCPU cpu2 Finished after 1000 issued reads, 1000 returned (472548 clocks)
-TrivialCPU cpu1 Finished after 1000 issued reads, 1000 returned (467220 clocks)
 TrivialCPU cpu0 Finished after 10000 issued reads, 10000 returned (1699068 clocks)
+TrivialCPU cpu1 Finished after 1000 issued reads, 1000 returned (467220 clocks)
+TrivialCPU cpu2 Finished after 1000 issued reads, 1000 returned (472548 clocks)
+TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (472116 clocks)
  cpu0.pendCycle : Accumulator : Sum.u64 = 15045016; SumSQ.u64 = 136505564; Count.u64 = 1699068; Min.u64 = 0; Max.u64 = 10; 
  c0.l1cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 8971; SumSQ.u64 = 8971; Count.u64 = 8971; Min.u64 = 1; Max.u64 = 1; 
@@ -146,9 +146,9 @@ TrivialCPU cpu0 Finished after 10000 issued reads, 10000 returned (1699068 clock
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 4840; SumSQ.u64 = 4840; Count.u64 = 4840; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 13358; SumSQ.u64 = 13358; Count.u64 = 13358; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 1489; SumSQ.u64 = 1489; Count.u64 = 1489; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 9000; SumSQ.u64 = 9000; Count.u64 = 9000; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -300,9 +300,9 @@ TrivialCPU cpu0 Finished after 10000 issued reads, 10000 returned (1699068 clock
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 451; SumSQ.u64 = 451; Count.u64 = 451; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1312; SumSQ.u64 = 1312; Count.u64 = 1312; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 904; SumSQ.u64 = 904; Count.u64 = 904; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -521,8 +521,8 @@ TrivialCPU cpu0 Finished after 10000 issued reads, 10000 returned (1699068 clock
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 9885; SumSQ.u64 = 9885; Count.u64 = 9885; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 1088; SumSQ.u64 = 1088; Count.u64 = 1088; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 9875; SumSQ.u64 = 9875; Count.u64 = 9875; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 1087; SumSQ.u64 = 1087; Count.u64 = 1087; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -533,11 +533,11 @@ TrivialCPU cpu0 Finished after 10000 issued reads, 10000 returned (1699068 clock
  n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 1020; SumSQ.u64 = 1020; Count.u64 = 1020; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 9076; SumSQ.u64 = 9076; Count.u64 = 9076; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 5137; SumSQ.u64 = 5137; Count.u64 = 5137; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 4430; SumSQ.u64 = 4430; Count.u64 = 4430; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 702; SumSQ.u64 = 702; Count.u64 = 702; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -681,9 +681,9 @@ TrivialCPU cpu0 Finished after 10000 issued reads, 10000 returned (1699068 clock
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 455; SumSQ.u64 = 455; Count.u64 = 455; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 1301; SumSQ.u64 = 1301; Count.u64 = 1301; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 898; SumSQ.u64 = 898; Count.u64 = 898; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -835,9 +835,9 @@ TrivialCPU cpu0 Finished after 10000 issued reads, 10000 returned (1699068 clock
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 460; SumSQ.u64 = 460; Count.u64 = 460; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 1345; SumSQ.u64 = 1345; Count.u64 = 1345; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 917; SumSQ.u64 = 917; Count.u64 = 917; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1056,8 +1056,8 @@ TrivialCPU cpu0 Finished after 10000 issued reads, 10000 returned (1699068 clock
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1817; SumSQ.u64 = 1817; Count.u64 = 1817; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1812; SumSQ.u64 = 1812; Count.u64 = 1812; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1068,11 +1068,11 @@ TrivialCPU cpu0 Finished after 10000 issued reads, 10000 returned (1699068 clock
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 1397; SumSQ.u64 = 1397; Count.u64 = 1397; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1829; SumSQ.u64 = 1829; Count.u64 = 1829; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1464; SumSQ.u64 = 1464; Count.u64 = 1464; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 361; SumSQ.u64 = 361; Count.u64 = 361; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1286,9 +1286,9 @@ TrivialCPU cpu0 Finished after 10000 issued reads, 10000 returned (1699068 clock
  l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 5999; SumSQ.u64 = 5999; Count.u64 = 5999; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 16900; SumSQ.u64 = 16900; Count.u64 = 16900; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 1833; SumSQ.u64 = 1833; Count.u64 = 1833; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 11388; SumSQ.u64 = 11388; Count.u64 = 11388; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 1238; SumSQ.u64 = 1238; Count.u64 = 1238; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderRow.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderRow.out
index 80197986a..15c9fae89 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderRow.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderRow.out
@@ -145,9 +145,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (57359 clocks)
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 477; SumSQ.u64 = 477; Count.u64 = 477; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 1341; SumSQ.u64 = 1341; Count.u64 = 1341; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 907; SumSQ.u64 = 907; Count.u64 = 907; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -299,9 +299,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (57359 clocks)
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 507; SumSQ.u64 = 507; Count.u64 = 507; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1351; SumSQ.u64 = 1351; Count.u64 = 1351; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 895; SumSQ.u64 = 895; Count.u64 = 895; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -520,7 +520,7 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (57359 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1805; SumSQ.u64 = 1805; Count.u64 = 1805; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1797; SumSQ.u64 = 1797; Count.u64 = 1797; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -532,11 +532,11 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (57359 clocks)
  n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 1420; SumSQ.u64 = 1420; Count.u64 = 1420; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1274; SumSQ.u64 = 1274; Count.u64 = 1274; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1027; SumSQ.u64 = 1027; Count.u64 = 1027; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -680,9 +680,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (57359 clocks)
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 498; SumSQ.u64 = 498; Count.u64 = 498; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 1361; SumSQ.u64 = 1361; Count.u64 = 1361; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -834,9 +834,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (57359 clocks)
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 481; SumSQ.u64 = 481; Count.u64 = 481; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 1331; SumSQ.u64 = 1331; Count.u64 = 1331; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1055,8 +1055,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (57359 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1809; SumSQ.u64 = 1809; Count.u64 = 1809; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 190; SumSQ.u64 = 190; Count.u64 = 190; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1805; SumSQ.u64 = 1805; Count.u64 = 1805; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1067,11 +1067,11 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (57359 clocks)
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 1398; SumSQ.u64 = 1398; Count.u64 = 1398; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1340; SumSQ.u64 = 1340; Count.u64 = 1340; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1074; SumSQ.u64 = 1074; Count.u64 = 1074; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 266; SumSQ.u64 = 266; Count.u64 = 266; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1285,9 +1285,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (57359 clocks)
  l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 2151; SumSQ.u64 = 2151; Count.u64 = 2151; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 5550; SumSQ.u64 = 5550; Count.u64 = 5550; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 593; SumSQ.u64 = 593; Count.u64 = 593; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 3533; SumSQ.u64 = 3533; Count.u64 = 3533; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 378; SumSQ.u64 = 378; Count.u64 = 378; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1306,7 +1306,7 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (57359 clocks)
  l3cache.FetchResp_recv : Accumulator : Sum.u64 = 2100; SumSQ.u64 = 2100; Count.u64 = 2100; Min.u64 = 1; Max.u64 = 1; 
  l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; 
  l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.AckInv_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.AckInv_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; 
  l3cache.AckPut_recv : Accumulator : Sum.u64 = 2764; SumSQ.u64 = 2764; Count.u64 = 2764; Min.u64 = 1; Max.u64 = 1; 
  l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 1358730; SumSQ.u64 = 36036188; Count.u64 = 52393; Min.u64 = 0; Max.u64 = 40; 
  l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderRow_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderRow_MC.out
index a96b471f1..d4fa27f65 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderRow_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderRow_MC.out
@@ -145,9 +145,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (57575 clocks)
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 477; SumSQ.u64 = 477; Count.u64 = 477; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 1341; SumSQ.u64 = 1341; Count.u64 = 1341; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 907; SumSQ.u64 = 907; Count.u64 = 907; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -299,9 +299,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (57575 clocks)
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 507; SumSQ.u64 = 507; Count.u64 = 507; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1351; SumSQ.u64 = 1351; Count.u64 = 1351; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 895; SumSQ.u64 = 895; Count.u64 = 895; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -520,7 +520,7 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (57575 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1805; SumSQ.u64 = 1805; Count.u64 = 1805; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1797; SumSQ.u64 = 1797; Count.u64 = 1797; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -532,11 +532,11 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (57575 clocks)
  n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 1420; SumSQ.u64 = 1420; Count.u64 = 1420; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1274; SumSQ.u64 = 1274; Count.u64 = 1274; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1027; SumSQ.u64 = 1027; Count.u64 = 1027; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -680,9 +680,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (57575 clocks)
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 498; SumSQ.u64 = 498; Count.u64 = 498; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 1361; SumSQ.u64 = 1361; Count.u64 = 1361; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -834,9 +834,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (57575 clocks)
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 481; SumSQ.u64 = 481; Count.u64 = 481; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 1331; SumSQ.u64 = 1331; Count.u64 = 1331; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1055,8 +1055,8 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (57575 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1809; SumSQ.u64 = 1809; Count.u64 = 1809; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 190; SumSQ.u64 = 190; Count.u64 = 190; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1805; SumSQ.u64 = 1805; Count.u64 = 1805; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1067,11 +1067,11 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (57575 clocks)
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 1398; SumSQ.u64 = 1398; Count.u64 = 1398; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1340; SumSQ.u64 = 1340; Count.u64 = 1340; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1074; SumSQ.u64 = 1074; Count.u64 = 1074; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 266; SumSQ.u64 = 266; Count.u64 = 266; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1285,9 +1285,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (57575 clocks)
  l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 2151; SumSQ.u64 = 2151; Count.u64 = 2151; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 5550; SumSQ.u64 = 5550; Count.u64 = 5550; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 593; SumSQ.u64 = 593; Count.u64 = 593; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 3533; SumSQ.u64 = 3533; Count.u64 = 3533; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 378; SumSQ.u64 = 378; Count.u64 = 378; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1306,7 +1306,7 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (57575 clocks)
  l3cache.FetchResp_recv : Accumulator : Sum.u64 = 2100; SumSQ.u64 = 2100; Count.u64 = 2100; Min.u64 = 1; Max.u64 = 1; 
  l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; 
  l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.AckInv_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.AckInv_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; 
  l3cache.AckPut_recv : Accumulator : Sum.u64 = 2764; SumSQ.u64 = 2764; Count.u64 = 2764; Min.u64 = 1; Max.u64 = 1; 
  l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 1358730; SumSQ.u64 = 36036188; Count.u64 = 52393; Min.u64 = 0; Max.u64 = 40; 
  l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderSimple.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderSimple.out
index 88fbd80f4..b04d53ef4 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderSimple.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderSimple.out
@@ -145,9 +145,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (460520 clocks)
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 1970; SumSQ.u64 = 1970; Count.u64 = 1970; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 5388; SumSQ.u64 = 5388; Count.u64 = 5388; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 583; SumSQ.u64 = 583; Count.u64 = 583; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 3610; SumSQ.u64 = 3610; Count.u64 = 3610; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 390; SumSQ.u64 = 390; Count.u64 = 390; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -299,9 +299,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (460520 clocks)
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 463; SumSQ.u64 = 463; Count.u64 = 463; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1350; SumSQ.u64 = 1350; Count.u64 = 1350; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 919; SumSQ.u64 = 919; Count.u64 = 919; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -520,8 +520,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (460520 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 4526; SumSQ.u64 = 4526; Count.u64 = 4526; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 472; SumSQ.u64 = 472; Count.u64 = 472; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 4513; SumSQ.u64 = 4513; Count.u64 = 4513; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 468; SumSQ.u64 = 468; Count.u64 = 468; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -532,11 +532,11 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (460520 clocks)
  n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 419; SumSQ.u64 = 419; Count.u64 = 419; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 3948; SumSQ.u64 = 3948; Count.u64 = 3948; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2561; SumSQ.u64 = 2561; Count.u64 = 2561; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2120; SumSQ.u64 = 2120; Count.u64 = 2120; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 434; SumSQ.u64 = 434; Count.u64 = 434; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -680,9 +680,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (460520 clocks)
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 478; SumSQ.u64 = 478; Count.u64 = 478; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 1334; SumSQ.u64 = 1334; Count.u64 = 1334; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 910; SumSQ.u64 = 910; Count.u64 = 910; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -834,9 +834,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (460520 clocks)
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 402; SumSQ.u64 = 402; Count.u64 = 402; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 1289; SumSQ.u64 = 1289; Count.u64 = 1289; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 923; SumSQ.u64 = 923; Count.u64 = 923; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1055,8 +1055,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (460520 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1835; SumSQ.u64 = 1835; Count.u64 = 1835; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1830; SumSQ.u64 = 1830; Count.u64 = 1830; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1067,11 +1067,11 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (460520 clocks)
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 133; SumSQ.u64 = 133; Count.u64 = 133; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 1398; SumSQ.u64 = 1398; Count.u64 = 1398; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1836; SumSQ.u64 = 1836; Count.u64 = 1836; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1447; SumSQ.u64 = 1447; Count.u64 = 1447; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1285,9 +1285,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (460520 clocks)
  l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 3666; SumSQ.u64 = 3666; Count.u64 = 3666; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 9638; SumSQ.u64 = 9638; Count.u64 = 9638; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 947; SumSQ.u64 = 947; Count.u64 = 947; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 6201; SumSQ.u64 = 6201; Count.u64 = 6201; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 607; SumSQ.u64 = 607; Count.u64 = 607; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderSimple_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderSimple_MC.out
index c34c7b0b6..75f482870 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderSimple_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderSimple_MC.out
@@ -145,9 +145,9 @@ TrivialCPU cpu0 Finished after 4000 issued reads, 4000 returned (875744 clocks)
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 1970; SumSQ.u64 = 1970; Count.u64 = 1970; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 5388; SumSQ.u64 = 5388; Count.u64 = 5388; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 583; SumSQ.u64 = 583; Count.u64 = 583; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 3610; SumSQ.u64 = 3610; Count.u64 = 3610; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 390; SumSQ.u64 = 390; Count.u64 = 390; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -299,9 +299,9 @@ TrivialCPU cpu0 Finished after 4000 issued reads, 4000 returned (875744 clocks)
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 463; SumSQ.u64 = 463; Count.u64 = 463; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1350; SumSQ.u64 = 1350; Count.u64 = 1350; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 919; SumSQ.u64 = 919; Count.u64 = 919; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -520,8 +520,8 @@ TrivialCPU cpu0 Finished after 4000 issued reads, 4000 returned (875744 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 4526; SumSQ.u64 = 4526; Count.u64 = 4526; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 472; SumSQ.u64 = 472; Count.u64 = 472; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 4513; SumSQ.u64 = 4513; Count.u64 = 4513; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 468; SumSQ.u64 = 468; Count.u64 = 468; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -532,11 +532,11 @@ TrivialCPU cpu0 Finished after 4000 issued reads, 4000 returned (875744 clocks)
  n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 419; SumSQ.u64 = 419; Count.u64 = 419; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 3948; SumSQ.u64 = 3948; Count.u64 = 3948; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2561; SumSQ.u64 = 2561; Count.u64 = 2561; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2120; SumSQ.u64 = 2120; Count.u64 = 2120; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 434; SumSQ.u64 = 434; Count.u64 = 434; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -680,9 +680,9 @@ TrivialCPU cpu0 Finished after 4000 issued reads, 4000 returned (875744 clocks)
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 478; SumSQ.u64 = 478; Count.u64 = 478; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 1334; SumSQ.u64 = 1334; Count.u64 = 1334; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 910; SumSQ.u64 = 910; Count.u64 = 910; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -834,9 +834,9 @@ TrivialCPU cpu0 Finished after 4000 issued reads, 4000 returned (875744 clocks)
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 402; SumSQ.u64 = 402; Count.u64 = 402; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 1289; SumSQ.u64 = 1289; Count.u64 = 1289; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 923; SumSQ.u64 = 923; Count.u64 = 923; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1055,8 +1055,8 @@ TrivialCPU cpu0 Finished after 4000 issued reads, 4000 returned (875744 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1835; SumSQ.u64 = 1835; Count.u64 = 1835; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1830; SumSQ.u64 = 1830; Count.u64 = 1830; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1067,11 +1067,11 @@ TrivialCPU cpu0 Finished after 4000 issued reads, 4000 returned (875744 clocks)
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 133; SumSQ.u64 = 133; Count.u64 = 133; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 1398; SumSQ.u64 = 1398; Count.u64 = 1398; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1836; SumSQ.u64 = 1836; Count.u64 = 1836; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1447; SumSQ.u64 = 1447; Count.u64 = 1447; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1285,9 +1285,9 @@ TrivialCPU cpu0 Finished after 4000 issued reads, 4000 returned (875744 clocks)
  l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 3666; SumSQ.u64 = 3666; Count.u64 = 3666; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 9638; SumSQ.u64 = 9638; Count.u64 = 9638; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 947; SumSQ.u64 = 947; Count.u64 = 947; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 6201; SumSQ.u64 = 6201; Count.u64 = 6201; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 607; SumSQ.u64 = 607; Count.u64 = 607; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_1.out
index 5c522771c..0f108ff48 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_1.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_1.out
@@ -145,9 +145,9 @@ TrivialCPU cpu3 Finished after 2000 issued reads, 2000 returned (1708753 clocks)
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 1820; SumSQ.u64 = 1820; Count.u64 = 1820; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 183; SumSQ.u64 = 183; Count.u64 = 183; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 1818; SumSQ.u64 = 1818; Count.u64 = 1818; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 182; SumSQ.u64 = 182; Count.u64 = 182; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -299,9 +299,9 @@ TrivialCPU cpu3 Finished after 2000 issued reads, 2000 returned (1708753 clocks)
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1812; SumSQ.u64 = 1812; Count.u64 = 1812; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1804; SumSQ.u64 = 1804; Count.u64 = 1804; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -520,8 +520,8 @@ TrivialCPU cpu3 Finished after 2000 issued reads, 2000 returned (1708753 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 3612; SumSQ.u64 = 3612; Count.u64 = 3612; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 374; SumSQ.u64 = 374; Count.u64 = 374; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 3603; SumSQ.u64 = 3603; Count.u64 = 3603; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -535,8 +535,8 @@ TrivialCPU cpu3 Finished after 2000 issued reads, 2000 returned (1708753 clocks)
  n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -680,9 +680,9 @@ TrivialCPU cpu3 Finished after 2000 issued reads, 2000 returned (1708753 clocks)
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 1794; SumSQ.u64 = 1794; Count.u64 = 1794; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 211; SumSQ.u64 = 211; Count.u64 = 211; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 1790; SumSQ.u64 = 1790; Count.u64 = 1790; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -835,7 +835,7 @@ TrivialCPU cpu3 Finished after 2000 issued reads, 2000 returned (1708753 clocks)
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 1828; SumSQ.u64 = 1828; Count.u64 = 1828; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 1827; SumSQ.u64 = 1827; Count.u64 = 1827; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1055,7 +1055,7 @@ TrivialCPU cpu3 Finished after 2000 issued reads, 2000 returned (1708753 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 3618; SumSQ.u64 = 3618; Count.u64 = 3618; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 3599; SumSQ.u64 = 3599; Count.u64 = 3599; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 381; SumSQ.u64 = 381; Count.u64 = 381; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1070,8 +1070,8 @@ TrivialCPU cpu3 Finished after 2000 issued reads, 2000 returned (1708753 clocks)
  n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1286,8 +1286,8 @@ TrivialCPU cpu3 Finished after 2000 issued reads, 2000 returned (1708753 clocks)
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 7236; SumSQ.u64 = 7236; Count.u64 = 7236; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 769; SumSQ.u64 = 769; Count.u64 = 769; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 7014; SumSQ.u64 = 7014; Count.u64 = 7014; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 741; SumSQ.u64 = 741; Count.u64 = 741; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_1_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_1_MC.out
index a87cb9582..3b51c4263 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_1_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_1_MC.out
@@ -145,9 +145,9 @@ TrivialCPU cpu0 Finished after 2000 issued reads, 2000 returned (2014099 clocks)
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 1820; SumSQ.u64 = 1820; Count.u64 = 1820; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 183; SumSQ.u64 = 183; Count.u64 = 183; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 1818; SumSQ.u64 = 1818; Count.u64 = 1818; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 182; SumSQ.u64 = 182; Count.u64 = 182; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -299,9 +299,9 @@ TrivialCPU cpu0 Finished after 2000 issued reads, 2000 returned (2014099 clocks)
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1812; SumSQ.u64 = 1812; Count.u64 = 1812; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1804; SumSQ.u64 = 1804; Count.u64 = 1804; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -520,8 +520,8 @@ TrivialCPU cpu0 Finished after 2000 issued reads, 2000 returned (2014099 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 3612; SumSQ.u64 = 3612; Count.u64 = 3612; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 374; SumSQ.u64 = 374; Count.u64 = 374; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 3603; SumSQ.u64 = 3603; Count.u64 = 3603; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -535,8 +535,8 @@ TrivialCPU cpu0 Finished after 2000 issued reads, 2000 returned (2014099 clocks)
  n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -680,9 +680,9 @@ TrivialCPU cpu0 Finished after 2000 issued reads, 2000 returned (2014099 clocks)
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 1794; SumSQ.u64 = 1794; Count.u64 = 1794; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 211; SumSQ.u64 = 211; Count.u64 = 211; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 1790; SumSQ.u64 = 1790; Count.u64 = 1790; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -835,7 +835,7 @@ TrivialCPU cpu0 Finished after 2000 issued reads, 2000 returned (2014099 clocks)
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 1828; SumSQ.u64 = 1828; Count.u64 = 1828; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 1827; SumSQ.u64 = 1827; Count.u64 = 1827; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1055,7 +1055,7 @@ TrivialCPU cpu0 Finished after 2000 issued reads, 2000 returned (2014099 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 3618; SumSQ.u64 = 3618; Count.u64 = 3618; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 3599; SumSQ.u64 = 3599; Count.u64 = 3599; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 381; SumSQ.u64 = 381; Count.u64 = 381; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1070,8 +1070,8 @@ TrivialCPU cpu0 Finished after 2000 issued reads, 2000 returned (2014099 clocks)
  n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1286,8 +1286,8 @@ TrivialCPU cpu0 Finished after 2000 issued reads, 2000 returned (2014099 clocks)
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 7236; SumSQ.u64 = 7236; Count.u64 = 7236; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 769; SumSQ.u64 = 769; Count.u64 = 769; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 7014; SumSQ.u64 = 7014; Count.u64 = 7014; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 741; SumSQ.u64 = 741; Count.u64 = 741; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_2.out
index 1ff0e8dab..617dc41b3 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_2.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_2.out
@@ -145,9 +145,9 @@ TrivialCPU cpu3 Finished after 2000 issued reads, 2000 returned (1605954 clocks)
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 1793; SumSQ.u64 = 1793; Count.u64 = 1793; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 216; SumSQ.u64 = 216; Count.u64 = 216; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 1786; SumSQ.u64 = 1786; Count.u64 = 1786; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 214; SumSQ.u64 = 214; Count.u64 = 214; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -299,8 +299,8 @@ TrivialCPU cpu3 Finished after 2000 issued reads, 2000 returned (1605954 clocks)
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1812; SumSQ.u64 = 1812; Count.u64 = 1812; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1807; SumSQ.u64 = 1807; Count.u64 = 1807; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -520,8 +520,8 @@ TrivialCPU cpu3 Finished after 2000 issued reads, 2000 returned (1605954 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 3591; SumSQ.u64 = 3591; Count.u64 = 3591; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 410; SumSQ.u64 = 410; Count.u64 = 410; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 3575; SumSQ.u64 = 3575; Count.u64 = 3575; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 406; SumSQ.u64 = 406; Count.u64 = 406; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -535,8 +535,8 @@ TrivialCPU cpu3 Finished after 2000 issued reads, 2000 returned (1605954 clocks)
  n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -680,9 +680,9 @@ TrivialCPU cpu3 Finished after 2000 issued reads, 2000 returned (1605954 clocks)
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 1800; SumSQ.u64 = 1800; Count.u64 = 1800; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 1794; SumSQ.u64 = 1794; Count.u64 = 1794; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 206; SumSQ.u64 = 206; Count.u64 = 206; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -834,8 +834,8 @@ TrivialCPU cpu3 Finished after 2000 issued reads, 2000 returned (1605954 clocks)
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 1769; SumSQ.u64 = 1769; Count.u64 = 1769; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 1766; SumSQ.u64 = 1766; Count.u64 = 1766; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1055,8 +1055,8 @@ TrivialCPU cpu3 Finished after 2000 issued reads, 2000 returned (1605954 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 3570; SumSQ.u64 = 3570; Count.u64 = 3570; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 441; SumSQ.u64 = 441; Count.u64 = 441; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 3551; SumSQ.u64 = 3551; Count.u64 = 3551; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 437; SumSQ.u64 = 437; Count.u64 = 437; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1070,8 +1070,8 @@ TrivialCPU cpu3 Finished after 2000 issued reads, 2000 returned (1605954 clocks)
  n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1286,8 +1286,8 @@ TrivialCPU cpu3 Finished after 2000 issued reads, 2000 returned (1605954 clocks)
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 7154; SumSQ.u64 = 7154; Count.u64 = 7154; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 838; SumSQ.u64 = 838; Count.u64 = 838; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 6961; SumSQ.u64 = 6961; Count.u64 = 6961; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 819; SumSQ.u64 = 819; Count.u64 = 819; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_2_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_2_MC.out
index 36e06cc2a..b000171ce 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_2_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_2_MC.out
@@ -145,9 +145,9 @@ TrivialCPU cpu0 Finished after 2000 issued reads, 2000 returned (1614522 clocks)
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 1793; SumSQ.u64 = 1793; Count.u64 = 1793; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 216; SumSQ.u64 = 216; Count.u64 = 216; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 1786; SumSQ.u64 = 1786; Count.u64 = 1786; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 214; SumSQ.u64 = 214; Count.u64 = 214; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -299,8 +299,8 @@ TrivialCPU cpu0 Finished after 2000 issued reads, 2000 returned (1614522 clocks)
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1812; SumSQ.u64 = 1812; Count.u64 = 1812; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1807; SumSQ.u64 = 1807; Count.u64 = 1807; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -520,8 +520,8 @@ TrivialCPU cpu0 Finished after 2000 issued reads, 2000 returned (1614522 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 3591; SumSQ.u64 = 3591; Count.u64 = 3591; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 410; SumSQ.u64 = 410; Count.u64 = 410; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 3575; SumSQ.u64 = 3575; Count.u64 = 3575; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 406; SumSQ.u64 = 406; Count.u64 = 406; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -535,8 +535,8 @@ TrivialCPU cpu0 Finished after 2000 issued reads, 2000 returned (1614522 clocks)
  n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -680,9 +680,9 @@ TrivialCPU cpu0 Finished after 2000 issued reads, 2000 returned (1614522 clocks)
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 1800; SumSQ.u64 = 1800; Count.u64 = 1800; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 1794; SumSQ.u64 = 1794; Count.u64 = 1794; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 206; SumSQ.u64 = 206; Count.u64 = 206; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -834,8 +834,8 @@ TrivialCPU cpu0 Finished after 2000 issued reads, 2000 returned (1614522 clocks)
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 1769; SumSQ.u64 = 1769; Count.u64 = 1769; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 1766; SumSQ.u64 = 1766; Count.u64 = 1766; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1055,8 +1055,8 @@ TrivialCPU cpu0 Finished after 2000 issued reads, 2000 returned (1614522 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 3570; SumSQ.u64 = 3570; Count.u64 = 3570; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 441; SumSQ.u64 = 441; Count.u64 = 441; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 3551; SumSQ.u64 = 3551; Count.u64 = 3551; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 437; SumSQ.u64 = 437; Count.u64 = 437; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1070,8 +1070,8 @@ TrivialCPU cpu0 Finished after 2000 issued reads, 2000 returned (1614522 clocks)
  n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1286,8 +1286,8 @@ TrivialCPU cpu0 Finished after 2000 issued reads, 2000 returned (1614522 clocks)
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 7154; SumSQ.u64 = 7154; Count.u64 = 7154; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 838; SumSQ.u64 = 838; Count.u64 = 838; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 6961; SumSQ.u64 = 6961; Count.u64 = 6961; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 819; SumSQ.u64 = 819; Count.u64 = 819; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_1.out
index 661014af8..9572d0dba 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_1.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_1.out
@@ -220,9 +220,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 99468; SumSQ.u64 = 99468; Count.u64 = 99468; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 87446; SumSQ.u64 = 87446; Count.u64 = 87446; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 9720; SumSQ.u64 = 9720; Count.u64 = 9720; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 35632; SumSQ.u64 = 35632; Count.u64 = 35632; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 3929; SumSQ.u64 = 3929; Count.u64 = 3929; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -241,7 +241,7 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  l3cache.FetchResp_recv : Accumulator : Sum.u64 = 15366; SumSQ.u64 = 15366; Count.u64 = 15366; Min.u64 = 1; Max.u64 = 1; 
  l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 895; SumSQ.u64 = 895; Count.u64 = 895; Min.u64 = 1; Max.u64 = 1; 
  l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.AckInv_recv : Accumulator : Sum.u64 = 21603; SumSQ.u64 = 21603; Count.u64 = 21603; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.AckInv_recv : Accumulator : Sum.u64 = 21592; SumSQ.u64 = 21592; Count.u64 = 21592; Min.u64 = 1; Max.u64 = 1; 
  l3cache.AckPut_recv : Accumulator : Sum.u64 = 36500; SumSQ.u64 = 36500; Count.u64 = 36500; Min.u64 = 1; Max.u64 = 1; 
  l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 842688270; SumSQ.u64 = 66870425350; Count.u64 = 10660197; Min.u64 = 0; Max.u64 = 80; 
  l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -381,9 +381,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 4549; SumSQ.u64 = 4549; Count.u64 = 4549; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 4503; SumSQ.u64 = 4503; Count.u64 = 4503; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 497; SumSQ.u64 = 497; Count.u64 = 497; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -614,11 +614,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c0.l2cache.PutM_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.PutE_recv : Accumulator : Sum.u64 = 1025; SumSQ.u64 = 1025; Count.u64 = 1025; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l2cache.Inv_recv : Accumulator : Sum.u64 = 5336; SumSQ.u64 = 5336; Count.u64 = 5336; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.Inv_recv : Accumulator : Sum.u64 = 2700; SumSQ.u64 = 2700; Count.u64 = 2700; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2682; SumSQ.u64 = 2682; Count.u64 = 2682; Min.u64 = 1; Max.u64 = 1; 
- c0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1874; SumSQ.u64 = 1874; Count.u64 = 1874; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 808; SumSQ.u64 = 808; Count.u64 = 808; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -762,9 +762,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 4499; SumSQ.u64 = 4499; Count.u64 = 4499; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 527; SumSQ.u64 = 527; Count.u64 = 527; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 4476; SumSQ.u64 = 4476; Count.u64 = 4476; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 524; SumSQ.u64 = 524; Count.u64 = 524; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -995,11 +995,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c1.l2cache.PutM_recv : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.PutE_recv : Accumulator : Sum.u64 = 1029; SumSQ.u64 = 1029; Count.u64 = 1029; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l2cache.Inv_recv : Accumulator : Sum.u64 = 5302; SumSQ.u64 = 5302; Count.u64 = 5302; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.Inv_recv : Accumulator : Sum.u64 = 2681; SumSQ.u64 = 2681; Count.u64 = 2681; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2833; SumSQ.u64 = 2833; Count.u64 = 2833; Min.u64 = 1; Max.u64 = 1; 
- c1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1971; SumSQ.u64 = 1971; Count.u64 = 1971; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 862; SumSQ.u64 = 862; Count.u64 = 862; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1143,9 +1143,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 4532; SumSQ.u64 = 4532; Count.u64 = 4532; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 491; SumSQ.u64 = 491; Count.u64 = 491; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 4510; SumSQ.u64 = 4510; Count.u64 = 4510; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 490; SumSQ.u64 = 490; Count.u64 = 490; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1376,11 +1376,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c2.l2cache.PutM_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.PutE_recv : Accumulator : Sum.u64 = 1065; SumSQ.u64 = 1065; Count.u64 = 1065; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l2cache.Inv_recv : Accumulator : Sum.u64 = 5285; SumSQ.u64 = 5285; Count.u64 = 5285; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.Inv_recv : Accumulator : Sum.u64 = 2669; SumSQ.u64 = 2669; Count.u64 = 2669; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2768; SumSQ.u64 = 2768; Count.u64 = 2768; Min.u64 = 1; Max.u64 = 1; 
- c2.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1947; SumSQ.u64 = 1947; Count.u64 = 1947; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 821; SumSQ.u64 = 821; Count.u64 = 821; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1524,9 +1524,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 4541; SumSQ.u64 = 4541; Count.u64 = 4541; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 487; SumSQ.u64 = 487; Count.u64 = 487; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 4515; SumSQ.u64 = 4515; Count.u64 = 4515; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1757,11 +1757,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c3.l2cache.PutM_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.PutE_recv : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l2cache.Inv_recv : Accumulator : Sum.u64 = 5329; SumSQ.u64 = 5329; Count.u64 = 5329; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.Inv_recv : Accumulator : Sum.u64 = 2693; SumSQ.u64 = 2693; Count.u64 = 2693; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2759; SumSQ.u64 = 2759; Count.u64 = 2759; Min.u64 = 1; Max.u64 = 1; 
- c3.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1950; SumSQ.u64 = 1950; Count.u64 = 1950; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 809; SumSQ.u64 = 809; Count.u64 = 809; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1905,9 +1905,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c4.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; 
- c4.l1cache.GetS_recv : Accumulator : Sum.u64 = 4533; SumSQ.u64 = 4533; Count.u64 = 4533; Min.u64 = 1; Max.u64 = 1; 
- c4.l1cache.GetX_recv : Accumulator : Sum.u64 = 498; SumSQ.u64 = 498; Count.u64 = 498; Min.u64 = 1; Max.u64 = 1; 
+ c4.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c4.l1cache.GetS_recv : Accumulator : Sum.u64 = 4506; SumSQ.u64 = 4506; Count.u64 = 4506; Min.u64 = 1; Max.u64 = 1; 
+ c4.l1cache.GetX_recv : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 494; Min.u64 = 1; Max.u64 = 1; 
  c4.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2138,11 +2138,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c4.l2cache.PutM_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.PutE_recv : Accumulator : Sum.u64 = 1060; SumSQ.u64 = 1060; Count.u64 = 1060; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l2cache.Inv_recv : Accumulator : Sum.u64 = 5383; SumSQ.u64 = 5383; Count.u64 = 5383; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.Inv_recv : Accumulator : Sum.u64 = 2722; SumSQ.u64 = 2722; Count.u64 = 2722; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2676; SumSQ.u64 = 2676; Count.u64 = 2676; Min.u64 = 1; Max.u64 = 1; 
- c4.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1911; SumSQ.u64 = 1911; Count.u64 = 1911; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 765; SumSQ.u64 = 765; Count.u64 = 765; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2286,9 +2286,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c5.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- c5.l1cache.GetS_recv : Accumulator : Sum.u64 = 4567; SumSQ.u64 = 4567; Count.u64 = 4567; Min.u64 = 1; Max.u64 = 1; 
- c5.l1cache.GetX_recv : Accumulator : Sum.u64 = 462; SumSQ.u64 = 462; Count.u64 = 462; Min.u64 = 1; Max.u64 = 1; 
+ c5.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c5.l1cache.GetS_recv : Accumulator : Sum.u64 = 4542; SumSQ.u64 = 4542; Count.u64 = 4542; Min.u64 = 1; Max.u64 = 1; 
+ c5.l1cache.GetX_recv : Accumulator : Sum.u64 = 458; SumSQ.u64 = 458; Count.u64 = 458; Min.u64 = 1; Max.u64 = 1; 
  c5.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2519,11 +2519,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c5.l2cache.PutM_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.PutE_recv : Accumulator : Sum.u64 = 1046; SumSQ.u64 = 1046; Count.u64 = 1046; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l2cache.Inv_recv : Accumulator : Sum.u64 = 5455; SumSQ.u64 = 5455; Count.u64 = 5455; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.Inv_recv : Accumulator : Sum.u64 = 2753; SumSQ.u64 = 2753; Count.u64 = 2753; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2642; SumSQ.u64 = 2642; Count.u64 = 2642; Min.u64 = 1; Max.u64 = 1; 
- c5.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1859; SumSQ.u64 = 1859; Count.u64 = 1859; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 783; SumSQ.u64 = 783; Count.u64 = 783; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2667,9 +2667,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c6.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
- c6.l1cache.GetS_recv : Accumulator : Sum.u64 = 4514; SumSQ.u64 = 4514; Count.u64 = 4514; Min.u64 = 1; Max.u64 = 1; 
- c6.l1cache.GetX_recv : Accumulator : Sum.u64 = 513; SumSQ.u64 = 513; Count.u64 = 513; Min.u64 = 1; Max.u64 = 1; 
+ c6.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c6.l1cache.GetS_recv : Accumulator : Sum.u64 = 4490; SumSQ.u64 = 4490; Count.u64 = 4490; Min.u64 = 1; Max.u64 = 1; 
+ c6.l1cache.GetX_recv : Accumulator : Sum.u64 = 510; SumSQ.u64 = 510; Count.u64 = 510; Min.u64 = 1; Max.u64 = 1; 
  c6.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2900,11 +2900,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c6.l2cache.PutM_recv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.PutE_recv : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l2cache.Inv_recv : Accumulator : Sum.u64 = 5317; SumSQ.u64 = 5317; Count.u64 = 5317; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.Inv_recv : Accumulator : Sum.u64 = 2688; SumSQ.u64 = 2688; Count.u64 = 2688; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2725; SumSQ.u64 = 2725; Count.u64 = 2725; Min.u64 = 1; Max.u64 = 1; 
- c6.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 176; SumSQ.u64 = 176; Count.u64 = 176; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1934; SumSQ.u64 = 1934; Count.u64 = 1934; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 791; SumSQ.u64 = 791; Count.u64 = 791; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3048,9 +3048,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c7.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
- c7.l1cache.GetS_recv : Accumulator : Sum.u64 = 4534; SumSQ.u64 = 4534; Count.u64 = 4534; Min.u64 = 1; Max.u64 = 1; 
- c7.l1cache.GetX_recv : Accumulator : Sum.u64 = 486; SumSQ.u64 = 486; Count.u64 = 486; Min.u64 = 1; Max.u64 = 1; 
+ c7.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c7.l1cache.GetS_recv : Accumulator : Sum.u64 = 4517; SumSQ.u64 = 4517; Count.u64 = 4517; Min.u64 = 1; Max.u64 = 1; 
+ c7.l1cache.GetX_recv : Accumulator : Sum.u64 = 483; SumSQ.u64 = 483; Count.u64 = 483; Min.u64 = 1; Max.u64 = 1; 
  c7.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3281,11 +3281,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c7.l2cache.PutM_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.PutE_recv : Accumulator : Sum.u64 = 1078; SumSQ.u64 = 1078; Count.u64 = 1078; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l2cache.Inv_recv : Accumulator : Sum.u64 = 5329; SumSQ.u64 = 5329; Count.u64 = 5329; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.Inv_recv : Accumulator : Sum.u64 = 2686; SumSQ.u64 = 2686; Count.u64 = 2686; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2719; SumSQ.u64 = 2719; Count.u64 = 2719; Min.u64 = 1; Max.u64 = 1; 
- c7.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1920; SumSQ.u64 = 1920; Count.u64 = 1920; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 799; SumSQ.u64 = 799; Count.u64 = 799; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_1_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_1_MC.out
index 2549465a2..001246332 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_1_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_1_MC.out
@@ -8,12 +8,12 @@ TrivialCPU: Test Completed Successfuly
 TrivialCPU: Test Completed Successfuly
 TrivialCPU cpu4 Finished after 5000 issued reads, 5000 returned (15857113 clocks)
 TrivialCPU cpu3 Finished after 5000 issued reads, 5000 returned (15904248 clocks)
-TrivialCPU cpu7 Finished after 5000 issued reads, 5000 returned (15989437 clocks)
-TrivialCPU cpu1 Finished after 5000 issued reads, 5000 returned (15858410 clocks)
 TrivialCPU cpu0 Finished after 5000 issued reads, 5000 returned (16006302 clocks)
-TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks)
+TrivialCPU cpu1 Finished after 5000 issued reads, 5000 returned (15858410 clocks)
 TrivialCPU cpu2 Finished after 5000 issued reads, 5000 returned (15969113 clocks)
 TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks)
+TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks)
+TrivialCPU cpu7 Finished after 5000 issued reads, 5000 returned (15989437 clocks)
  l3cache:memlink.packet_latency : Accumulator : Sum.u64 = 7032280; SumSQ.u64 = 668066600; Count.u64 = 74024; Min.u64 = 95; Max.u64 = 95; 
  l3cache:memlink.send_bit_count : Accumulator : Sum.u64 = 6681088; SumSQ.u64 = 1547075584; Count.u64 = 74024; Min.u64 = 64; Max.u64 = 576; 
  l3cache:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -220,9 +220,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 99468; SumSQ.u64 = 99468; Count.u64 = 99468; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 87446; SumSQ.u64 = 87446; Count.u64 = 87446; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 9720; SumSQ.u64 = 9720; Count.u64 = 9720; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 35632; SumSQ.u64 = 35632; Count.u64 = 35632; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 3929; SumSQ.u64 = 3929; Count.u64 = 3929; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -241,7 +241,7 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  l3cache.FetchResp_recv : Accumulator : Sum.u64 = 15366; SumSQ.u64 = 15366; Count.u64 = 15366; Min.u64 = 1; Max.u64 = 1; 
  l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 895; SumSQ.u64 = 895; Count.u64 = 895; Min.u64 = 1; Max.u64 = 1; 
  l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.AckInv_recv : Accumulator : Sum.u64 = 21603; SumSQ.u64 = 21603; Count.u64 = 21603; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.AckInv_recv : Accumulator : Sum.u64 = 21592; SumSQ.u64 = 21592; Count.u64 = 21592; Min.u64 = 1; Max.u64 = 1; 
  l3cache.AckPut_recv : Accumulator : Sum.u64 = 36500; SumSQ.u64 = 36500; Count.u64 = 36500; Min.u64 = 1; Max.u64 = 1; 
  l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 842688270; SumSQ.u64 = 66870425350; Count.u64 = 10660197; Min.u64 = 0; Max.u64 = 80; 
  l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -381,9 +381,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 4549; SumSQ.u64 = 4549; Count.u64 = 4549; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 4503; SumSQ.u64 = 4503; Count.u64 = 4503; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 497; SumSQ.u64 = 497; Count.u64 = 497; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -614,11 +614,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c0.l2cache.PutM_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.PutE_recv : Accumulator : Sum.u64 = 1025; SumSQ.u64 = 1025; Count.u64 = 1025; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l2cache.Inv_recv : Accumulator : Sum.u64 = 5336; SumSQ.u64 = 5336; Count.u64 = 5336; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.Inv_recv : Accumulator : Sum.u64 = 2700; SumSQ.u64 = 2700; Count.u64 = 2700; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2682; SumSQ.u64 = 2682; Count.u64 = 2682; Min.u64 = 1; Max.u64 = 1; 
- c0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1874; SumSQ.u64 = 1874; Count.u64 = 1874; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 808; SumSQ.u64 = 808; Count.u64 = 808; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -762,9 +762,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 4499; SumSQ.u64 = 4499; Count.u64 = 4499; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 527; SumSQ.u64 = 527; Count.u64 = 527; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 4476; SumSQ.u64 = 4476; Count.u64 = 4476; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 524; SumSQ.u64 = 524; Count.u64 = 524; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -995,11 +995,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c1.l2cache.PutM_recv : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.PutE_recv : Accumulator : Sum.u64 = 1029; SumSQ.u64 = 1029; Count.u64 = 1029; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l2cache.Inv_recv : Accumulator : Sum.u64 = 5302; SumSQ.u64 = 5302; Count.u64 = 5302; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.Inv_recv : Accumulator : Sum.u64 = 2681; SumSQ.u64 = 2681; Count.u64 = 2681; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2833; SumSQ.u64 = 2833; Count.u64 = 2833; Min.u64 = 1; Max.u64 = 1; 
- c1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1971; SumSQ.u64 = 1971; Count.u64 = 1971; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 862; SumSQ.u64 = 862; Count.u64 = 862; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1143,9 +1143,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 4532; SumSQ.u64 = 4532; Count.u64 = 4532; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 491; SumSQ.u64 = 491; Count.u64 = 491; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 4510; SumSQ.u64 = 4510; Count.u64 = 4510; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 490; SumSQ.u64 = 490; Count.u64 = 490; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1376,11 +1376,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c2.l2cache.PutM_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.PutE_recv : Accumulator : Sum.u64 = 1065; SumSQ.u64 = 1065; Count.u64 = 1065; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l2cache.Inv_recv : Accumulator : Sum.u64 = 5285; SumSQ.u64 = 5285; Count.u64 = 5285; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.Inv_recv : Accumulator : Sum.u64 = 2669; SumSQ.u64 = 2669; Count.u64 = 2669; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2768; SumSQ.u64 = 2768; Count.u64 = 2768; Min.u64 = 1; Max.u64 = 1; 
- c2.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1947; SumSQ.u64 = 1947; Count.u64 = 1947; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 821; SumSQ.u64 = 821; Count.u64 = 821; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1524,9 +1524,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 4541; SumSQ.u64 = 4541; Count.u64 = 4541; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 487; SumSQ.u64 = 487; Count.u64 = 487; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 4515; SumSQ.u64 = 4515; Count.u64 = 4515; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1757,11 +1757,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c3.l2cache.PutM_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.PutE_recv : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l2cache.Inv_recv : Accumulator : Sum.u64 = 5329; SumSQ.u64 = 5329; Count.u64 = 5329; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.Inv_recv : Accumulator : Sum.u64 = 2693; SumSQ.u64 = 2693; Count.u64 = 2693; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2759; SumSQ.u64 = 2759; Count.u64 = 2759; Min.u64 = 1; Max.u64 = 1; 
- c3.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1950; SumSQ.u64 = 1950; Count.u64 = 1950; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 809; SumSQ.u64 = 809; Count.u64 = 809; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1905,9 +1905,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c4.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; 
- c4.l1cache.GetS_recv : Accumulator : Sum.u64 = 4533; SumSQ.u64 = 4533; Count.u64 = 4533; Min.u64 = 1; Max.u64 = 1; 
- c4.l1cache.GetX_recv : Accumulator : Sum.u64 = 498; SumSQ.u64 = 498; Count.u64 = 498; Min.u64 = 1; Max.u64 = 1; 
+ c4.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c4.l1cache.GetS_recv : Accumulator : Sum.u64 = 4506; SumSQ.u64 = 4506; Count.u64 = 4506; Min.u64 = 1; Max.u64 = 1; 
+ c4.l1cache.GetX_recv : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 494; Min.u64 = 1; Max.u64 = 1; 
  c4.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2138,11 +2138,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c4.l2cache.PutM_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.PutE_recv : Accumulator : Sum.u64 = 1060; SumSQ.u64 = 1060; Count.u64 = 1060; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l2cache.Inv_recv : Accumulator : Sum.u64 = 5383; SumSQ.u64 = 5383; Count.u64 = 5383; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.Inv_recv : Accumulator : Sum.u64 = 2722; SumSQ.u64 = 2722; Count.u64 = 2722; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2676; SumSQ.u64 = 2676; Count.u64 = 2676; Min.u64 = 1; Max.u64 = 1; 
- c4.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1911; SumSQ.u64 = 1911; Count.u64 = 1911; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 765; SumSQ.u64 = 765; Count.u64 = 765; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2286,9 +2286,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c5.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- c5.l1cache.GetS_recv : Accumulator : Sum.u64 = 4567; SumSQ.u64 = 4567; Count.u64 = 4567; Min.u64 = 1; Max.u64 = 1; 
- c5.l1cache.GetX_recv : Accumulator : Sum.u64 = 462; SumSQ.u64 = 462; Count.u64 = 462; Min.u64 = 1; Max.u64 = 1; 
+ c5.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c5.l1cache.GetS_recv : Accumulator : Sum.u64 = 4542; SumSQ.u64 = 4542; Count.u64 = 4542; Min.u64 = 1; Max.u64 = 1; 
+ c5.l1cache.GetX_recv : Accumulator : Sum.u64 = 458; SumSQ.u64 = 458; Count.u64 = 458; Min.u64 = 1; Max.u64 = 1; 
  c5.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2519,11 +2519,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c5.l2cache.PutM_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.PutE_recv : Accumulator : Sum.u64 = 1046; SumSQ.u64 = 1046; Count.u64 = 1046; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l2cache.Inv_recv : Accumulator : Sum.u64 = 5455; SumSQ.u64 = 5455; Count.u64 = 5455; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.Inv_recv : Accumulator : Sum.u64 = 2753; SumSQ.u64 = 2753; Count.u64 = 2753; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2642; SumSQ.u64 = 2642; Count.u64 = 2642; Min.u64 = 1; Max.u64 = 1; 
- c5.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1859; SumSQ.u64 = 1859; Count.u64 = 1859; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 783; SumSQ.u64 = 783; Count.u64 = 783; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2667,9 +2667,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c6.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
- c6.l1cache.GetS_recv : Accumulator : Sum.u64 = 4514; SumSQ.u64 = 4514; Count.u64 = 4514; Min.u64 = 1; Max.u64 = 1; 
- c6.l1cache.GetX_recv : Accumulator : Sum.u64 = 513; SumSQ.u64 = 513; Count.u64 = 513; Min.u64 = 1; Max.u64 = 1; 
+ c6.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c6.l1cache.GetS_recv : Accumulator : Sum.u64 = 4490; SumSQ.u64 = 4490; Count.u64 = 4490; Min.u64 = 1; Max.u64 = 1; 
+ c6.l1cache.GetX_recv : Accumulator : Sum.u64 = 510; SumSQ.u64 = 510; Count.u64 = 510; Min.u64 = 1; Max.u64 = 1; 
  c6.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2900,11 +2900,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c6.l2cache.PutM_recv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.PutE_recv : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l2cache.Inv_recv : Accumulator : Sum.u64 = 5317; SumSQ.u64 = 5317; Count.u64 = 5317; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.Inv_recv : Accumulator : Sum.u64 = 2688; SumSQ.u64 = 2688; Count.u64 = 2688; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2725; SumSQ.u64 = 2725; Count.u64 = 2725; Min.u64 = 1; Max.u64 = 1; 
- c6.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 176; SumSQ.u64 = 176; Count.u64 = 176; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1934; SumSQ.u64 = 1934; Count.u64 = 1934; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 791; SumSQ.u64 = 791; Count.u64 = 791; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3048,9 +3048,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c7.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
- c7.l1cache.GetS_recv : Accumulator : Sum.u64 = 4534; SumSQ.u64 = 4534; Count.u64 = 4534; Min.u64 = 1; Max.u64 = 1; 
- c7.l1cache.GetX_recv : Accumulator : Sum.u64 = 486; SumSQ.u64 = 486; Count.u64 = 486; Min.u64 = 1; Max.u64 = 1; 
+ c7.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c7.l1cache.GetS_recv : Accumulator : Sum.u64 = 4517; SumSQ.u64 = 4517; Count.u64 = 4517; Min.u64 = 1; Max.u64 = 1; 
+ c7.l1cache.GetX_recv : Accumulator : Sum.u64 = 483; SumSQ.u64 = 483; Count.u64 = 483; Min.u64 = 1; Max.u64 = 1; 
  c7.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3281,11 +3281,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c7.l2cache.PutM_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.PutE_recv : Accumulator : Sum.u64 = 1078; SumSQ.u64 = 1078; Count.u64 = 1078; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l2cache.Inv_recv : Accumulator : Sum.u64 = 5329; SumSQ.u64 = 5329; Count.u64 = 5329; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.Inv_recv : Accumulator : Sum.u64 = 2686; SumSQ.u64 = 2686; Count.u64 = 2686; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2719; SumSQ.u64 = 2719; Count.u64 = 2719; Min.u64 = 1; Max.u64 = 1; 
- c7.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1920; SumSQ.u64 = 1920; Count.u64 = 1920; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 799; SumSQ.u64 = 799; Count.u64 = 799; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_2.out
index 5a5e0ef6b..482dd814a 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_2.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_2.out
@@ -220,9 +220,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 99468; SumSQ.u64 = 99468; Count.u64 = 99468; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 87446; SumSQ.u64 = 87446; Count.u64 = 87446; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 9720; SumSQ.u64 = 9720; Count.u64 = 9720; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 35632; SumSQ.u64 = 35632; Count.u64 = 35632; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 3929; SumSQ.u64 = 3929; Count.u64 = 3929; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -241,7 +241,7 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  l3cache.FetchResp_recv : Accumulator : Sum.u64 = 15366; SumSQ.u64 = 15366; Count.u64 = 15366; Min.u64 = 1; Max.u64 = 1; 
  l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 895; SumSQ.u64 = 895; Count.u64 = 895; Min.u64 = 1; Max.u64 = 1; 
  l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.AckInv_recv : Accumulator : Sum.u64 = 21603; SumSQ.u64 = 21603; Count.u64 = 21603; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.AckInv_recv : Accumulator : Sum.u64 = 21592; SumSQ.u64 = 21592; Count.u64 = 21592; Min.u64 = 1; Max.u64 = 1; 
  l3cache.AckPut_recv : Accumulator : Sum.u64 = 36500; SumSQ.u64 = 36500; Count.u64 = 36500; Min.u64 = 1; Max.u64 = 1; 
  l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 842688270; SumSQ.u64 = 66870425350; Count.u64 = 10660197; Min.u64 = 0; Max.u64 = 80; 
  l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -381,9 +381,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 4549; SumSQ.u64 = 4549; Count.u64 = 4549; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 4503; SumSQ.u64 = 4503; Count.u64 = 4503; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 497; SumSQ.u64 = 497; Count.u64 = 497; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -614,11 +614,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c0.l2cache.PutM_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.PutE_recv : Accumulator : Sum.u64 = 1025; SumSQ.u64 = 1025; Count.u64 = 1025; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l2cache.Inv_recv : Accumulator : Sum.u64 = 5336; SumSQ.u64 = 5336; Count.u64 = 5336; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.Inv_recv : Accumulator : Sum.u64 = 2700; SumSQ.u64 = 2700; Count.u64 = 2700; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2682; SumSQ.u64 = 2682; Count.u64 = 2682; Min.u64 = 1; Max.u64 = 1; 
- c0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1874; SumSQ.u64 = 1874; Count.u64 = 1874; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 808; SumSQ.u64 = 808; Count.u64 = 808; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -762,9 +762,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 4499; SumSQ.u64 = 4499; Count.u64 = 4499; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 527; SumSQ.u64 = 527; Count.u64 = 527; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 4476; SumSQ.u64 = 4476; Count.u64 = 4476; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 524; SumSQ.u64 = 524; Count.u64 = 524; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -995,11 +995,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c1.l2cache.PutM_recv : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.PutE_recv : Accumulator : Sum.u64 = 1029; SumSQ.u64 = 1029; Count.u64 = 1029; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l2cache.Inv_recv : Accumulator : Sum.u64 = 5302; SumSQ.u64 = 5302; Count.u64 = 5302; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.Inv_recv : Accumulator : Sum.u64 = 2681; SumSQ.u64 = 2681; Count.u64 = 2681; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2833; SumSQ.u64 = 2833; Count.u64 = 2833; Min.u64 = 1; Max.u64 = 1; 
- c1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1971; SumSQ.u64 = 1971; Count.u64 = 1971; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 862; SumSQ.u64 = 862; Count.u64 = 862; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1143,9 +1143,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 4532; SumSQ.u64 = 4532; Count.u64 = 4532; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 491; SumSQ.u64 = 491; Count.u64 = 491; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 4510; SumSQ.u64 = 4510; Count.u64 = 4510; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 490; SumSQ.u64 = 490; Count.u64 = 490; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1376,11 +1376,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c2.l2cache.PutM_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.PutE_recv : Accumulator : Sum.u64 = 1065; SumSQ.u64 = 1065; Count.u64 = 1065; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l2cache.Inv_recv : Accumulator : Sum.u64 = 5285; SumSQ.u64 = 5285; Count.u64 = 5285; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.Inv_recv : Accumulator : Sum.u64 = 2669; SumSQ.u64 = 2669; Count.u64 = 2669; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2768; SumSQ.u64 = 2768; Count.u64 = 2768; Min.u64 = 1; Max.u64 = 1; 
- c2.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1947; SumSQ.u64 = 1947; Count.u64 = 1947; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 821; SumSQ.u64 = 821; Count.u64 = 821; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1524,9 +1524,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 4541; SumSQ.u64 = 4541; Count.u64 = 4541; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 487; SumSQ.u64 = 487; Count.u64 = 487; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 4515; SumSQ.u64 = 4515; Count.u64 = 4515; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1757,11 +1757,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c3.l2cache.PutM_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.PutE_recv : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l2cache.Inv_recv : Accumulator : Sum.u64 = 5329; SumSQ.u64 = 5329; Count.u64 = 5329; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.Inv_recv : Accumulator : Sum.u64 = 2693; SumSQ.u64 = 2693; Count.u64 = 2693; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2759; SumSQ.u64 = 2759; Count.u64 = 2759; Min.u64 = 1; Max.u64 = 1; 
- c3.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1950; SumSQ.u64 = 1950; Count.u64 = 1950; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 809; SumSQ.u64 = 809; Count.u64 = 809; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1905,9 +1905,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c4.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; 
- c4.l1cache.GetS_recv : Accumulator : Sum.u64 = 4533; SumSQ.u64 = 4533; Count.u64 = 4533; Min.u64 = 1; Max.u64 = 1; 
- c4.l1cache.GetX_recv : Accumulator : Sum.u64 = 498; SumSQ.u64 = 498; Count.u64 = 498; Min.u64 = 1; Max.u64 = 1; 
+ c4.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c4.l1cache.GetS_recv : Accumulator : Sum.u64 = 4506; SumSQ.u64 = 4506; Count.u64 = 4506; Min.u64 = 1; Max.u64 = 1; 
+ c4.l1cache.GetX_recv : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 494; Min.u64 = 1; Max.u64 = 1; 
  c4.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2138,11 +2138,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c4.l2cache.PutM_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.PutE_recv : Accumulator : Sum.u64 = 1060; SumSQ.u64 = 1060; Count.u64 = 1060; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l2cache.Inv_recv : Accumulator : Sum.u64 = 5383; SumSQ.u64 = 5383; Count.u64 = 5383; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.Inv_recv : Accumulator : Sum.u64 = 2722; SumSQ.u64 = 2722; Count.u64 = 2722; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2676; SumSQ.u64 = 2676; Count.u64 = 2676; Min.u64 = 1; Max.u64 = 1; 
- c4.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1911; SumSQ.u64 = 1911; Count.u64 = 1911; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 765; SumSQ.u64 = 765; Count.u64 = 765; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2286,9 +2286,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c5.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- c5.l1cache.GetS_recv : Accumulator : Sum.u64 = 4567; SumSQ.u64 = 4567; Count.u64 = 4567; Min.u64 = 1; Max.u64 = 1; 
- c5.l1cache.GetX_recv : Accumulator : Sum.u64 = 462; SumSQ.u64 = 462; Count.u64 = 462; Min.u64 = 1; Max.u64 = 1; 
+ c5.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c5.l1cache.GetS_recv : Accumulator : Sum.u64 = 4542; SumSQ.u64 = 4542; Count.u64 = 4542; Min.u64 = 1; Max.u64 = 1; 
+ c5.l1cache.GetX_recv : Accumulator : Sum.u64 = 458; SumSQ.u64 = 458; Count.u64 = 458; Min.u64 = 1; Max.u64 = 1; 
  c5.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2519,11 +2519,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c5.l2cache.PutM_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.PutE_recv : Accumulator : Sum.u64 = 1046; SumSQ.u64 = 1046; Count.u64 = 1046; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l2cache.Inv_recv : Accumulator : Sum.u64 = 5455; SumSQ.u64 = 5455; Count.u64 = 5455; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.Inv_recv : Accumulator : Sum.u64 = 2753; SumSQ.u64 = 2753; Count.u64 = 2753; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2642; SumSQ.u64 = 2642; Count.u64 = 2642; Min.u64 = 1; Max.u64 = 1; 
- c5.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1859; SumSQ.u64 = 1859; Count.u64 = 1859; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 783; SumSQ.u64 = 783; Count.u64 = 783; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2667,9 +2667,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c6.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
- c6.l1cache.GetS_recv : Accumulator : Sum.u64 = 4514; SumSQ.u64 = 4514; Count.u64 = 4514; Min.u64 = 1; Max.u64 = 1; 
- c6.l1cache.GetX_recv : Accumulator : Sum.u64 = 513; SumSQ.u64 = 513; Count.u64 = 513; Min.u64 = 1; Max.u64 = 1; 
+ c6.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c6.l1cache.GetS_recv : Accumulator : Sum.u64 = 4490; SumSQ.u64 = 4490; Count.u64 = 4490; Min.u64 = 1; Max.u64 = 1; 
+ c6.l1cache.GetX_recv : Accumulator : Sum.u64 = 510; SumSQ.u64 = 510; Count.u64 = 510; Min.u64 = 1; Max.u64 = 1; 
  c6.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2900,11 +2900,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c6.l2cache.PutM_recv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.PutE_recv : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l2cache.Inv_recv : Accumulator : Sum.u64 = 5317; SumSQ.u64 = 5317; Count.u64 = 5317; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.Inv_recv : Accumulator : Sum.u64 = 2688; SumSQ.u64 = 2688; Count.u64 = 2688; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2725; SumSQ.u64 = 2725; Count.u64 = 2725; Min.u64 = 1; Max.u64 = 1; 
- c6.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 176; SumSQ.u64 = 176; Count.u64 = 176; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1934; SumSQ.u64 = 1934; Count.u64 = 1934; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 791; SumSQ.u64 = 791; Count.u64 = 791; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3048,9 +3048,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c7.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
- c7.l1cache.GetS_recv : Accumulator : Sum.u64 = 4534; SumSQ.u64 = 4534; Count.u64 = 4534; Min.u64 = 1; Max.u64 = 1; 
- c7.l1cache.GetX_recv : Accumulator : Sum.u64 = 486; SumSQ.u64 = 486; Count.u64 = 486; Min.u64 = 1; Max.u64 = 1; 
+ c7.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c7.l1cache.GetS_recv : Accumulator : Sum.u64 = 4517; SumSQ.u64 = 4517; Count.u64 = 4517; Min.u64 = 1; Max.u64 = 1; 
+ c7.l1cache.GetX_recv : Accumulator : Sum.u64 = 483; SumSQ.u64 = 483; Count.u64 = 483; Min.u64 = 1; Max.u64 = 1; 
  c7.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3281,11 +3281,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c7.l2cache.PutM_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.PutE_recv : Accumulator : Sum.u64 = 1078; SumSQ.u64 = 1078; Count.u64 = 1078; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l2cache.Inv_recv : Accumulator : Sum.u64 = 5329; SumSQ.u64 = 5329; Count.u64 = 5329; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.Inv_recv : Accumulator : Sum.u64 = 2686; SumSQ.u64 = 2686; Count.u64 = 2686; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2719; SumSQ.u64 = 2719; Count.u64 = 2719; Min.u64 = 1; Max.u64 = 1; 
- c7.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1920; SumSQ.u64 = 1920; Count.u64 = 1920; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 799; SumSQ.u64 = 799; Count.u64 = 799; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_2_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_2_MC.out
index 3878f6a70..add0546a0 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_2_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_2_MC.out
@@ -6,14 +6,14 @@ TrivialCPU: Test Completed Successfuly
 TrivialCPU: Test Completed Successfuly
 TrivialCPU: Test Completed Successfuly
 TrivialCPU: Test Completed Successfuly
-TrivialCPU cpu7 Finished after 5000 issued reads, 5000 returned (15989437 clocks)
-TrivialCPU cpu2 Finished after 5000 issued reads, 5000 returned (15969113 clocks)
-TrivialCPU cpu1 Finished after 5000 issued reads, 5000 returned (15858410 clocks)
-TrivialCPU cpu0 Finished after 5000 issued reads, 5000 returned (16006302 clocks)
-TrivialCPU cpu3 Finished after 5000 issued reads, 5000 returned (15904248 clocks)
 TrivialCPU cpu4 Finished after 5000 issued reads, 5000 returned (15857113 clocks)
+TrivialCPU cpu3 Finished after 5000 issued reads, 5000 returned (15904248 clocks)
+TrivialCPU cpu0 Finished after 5000 issued reads, 5000 returned (16006302 clocks)
+TrivialCPU cpu1 Finished after 5000 issued reads, 5000 returned (15858410 clocks)
+TrivialCPU cpu2 Finished after 5000 issued reads, 5000 returned (15969113 clocks)
 TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks)
 TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks)
+TrivialCPU cpu7 Finished after 5000 issued reads, 5000 returned (15989437 clocks)
  l3cache:memlink.packet_latency : Accumulator : Sum.u64 = 7476424; SumSQ.u64 = 755118824; Count.u64 = 74024; Min.u64 = 101; Max.u64 = 101; 
  l3cache:memlink.send_bit_count : Accumulator : Sum.u64 = 6681088; SumSQ.u64 = 1547075584; Count.u64 = 74024; Min.u64 = 64; Max.u64 = 576; 
  l3cache:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -220,9 +220,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 99468; SumSQ.u64 = 99468; Count.u64 = 99468; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 87446; SumSQ.u64 = 87446; Count.u64 = 87446; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 9720; SumSQ.u64 = 9720; Count.u64 = 9720; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 35632; SumSQ.u64 = 35632; Count.u64 = 35632; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 3929; SumSQ.u64 = 3929; Count.u64 = 3929; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -241,7 +241,7 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  l3cache.FetchResp_recv : Accumulator : Sum.u64 = 15366; SumSQ.u64 = 15366; Count.u64 = 15366; Min.u64 = 1; Max.u64 = 1; 
  l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 895; SumSQ.u64 = 895; Count.u64 = 895; Min.u64 = 1; Max.u64 = 1; 
  l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.AckInv_recv : Accumulator : Sum.u64 = 21603; SumSQ.u64 = 21603; Count.u64 = 21603; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.AckInv_recv : Accumulator : Sum.u64 = 21592; SumSQ.u64 = 21592; Count.u64 = 21592; Min.u64 = 1; Max.u64 = 1; 
  l3cache.AckPut_recv : Accumulator : Sum.u64 = 36500; SumSQ.u64 = 36500; Count.u64 = 36500; Min.u64 = 1; Max.u64 = 1; 
  l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 842688270; SumSQ.u64 = 66870425350; Count.u64 = 10660197; Min.u64 = 0; Max.u64 = 80; 
  l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -381,9 +381,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 4549; SumSQ.u64 = 4549; Count.u64 = 4549; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 4503; SumSQ.u64 = 4503; Count.u64 = 4503; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 497; SumSQ.u64 = 497; Count.u64 = 497; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -614,11 +614,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c0.l2cache.PutM_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.PutE_recv : Accumulator : Sum.u64 = 1025; SumSQ.u64 = 1025; Count.u64 = 1025; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l2cache.Inv_recv : Accumulator : Sum.u64 = 5336; SumSQ.u64 = 5336; Count.u64 = 5336; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.Inv_recv : Accumulator : Sum.u64 = 2700; SumSQ.u64 = 2700; Count.u64 = 2700; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2682; SumSQ.u64 = 2682; Count.u64 = 2682; Min.u64 = 1; Max.u64 = 1; 
- c0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1874; SumSQ.u64 = 1874; Count.u64 = 1874; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 808; SumSQ.u64 = 808; Count.u64 = 808; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -762,9 +762,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 4499; SumSQ.u64 = 4499; Count.u64 = 4499; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 527; SumSQ.u64 = 527; Count.u64 = 527; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 4476; SumSQ.u64 = 4476; Count.u64 = 4476; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 524; SumSQ.u64 = 524; Count.u64 = 524; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -995,11 +995,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c1.l2cache.PutM_recv : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.PutE_recv : Accumulator : Sum.u64 = 1029; SumSQ.u64 = 1029; Count.u64 = 1029; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l2cache.Inv_recv : Accumulator : Sum.u64 = 5302; SumSQ.u64 = 5302; Count.u64 = 5302; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.Inv_recv : Accumulator : Sum.u64 = 2681; SumSQ.u64 = 2681; Count.u64 = 2681; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2833; SumSQ.u64 = 2833; Count.u64 = 2833; Min.u64 = 1; Max.u64 = 1; 
- c1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1971; SumSQ.u64 = 1971; Count.u64 = 1971; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 862; SumSQ.u64 = 862; Count.u64 = 862; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1143,9 +1143,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 4532; SumSQ.u64 = 4532; Count.u64 = 4532; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 491; SumSQ.u64 = 491; Count.u64 = 491; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 4510; SumSQ.u64 = 4510; Count.u64 = 4510; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 490; SumSQ.u64 = 490; Count.u64 = 490; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1376,11 +1376,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c2.l2cache.PutM_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.PutE_recv : Accumulator : Sum.u64 = 1065; SumSQ.u64 = 1065; Count.u64 = 1065; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l2cache.Inv_recv : Accumulator : Sum.u64 = 5285; SumSQ.u64 = 5285; Count.u64 = 5285; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.Inv_recv : Accumulator : Sum.u64 = 2669; SumSQ.u64 = 2669; Count.u64 = 2669; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2768; SumSQ.u64 = 2768; Count.u64 = 2768; Min.u64 = 1; Max.u64 = 1; 
- c2.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1947; SumSQ.u64 = 1947; Count.u64 = 1947; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 821; SumSQ.u64 = 821; Count.u64 = 821; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1524,9 +1524,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 4541; SumSQ.u64 = 4541; Count.u64 = 4541; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 487; SumSQ.u64 = 487; Count.u64 = 487; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 4515; SumSQ.u64 = 4515; Count.u64 = 4515; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1757,11 +1757,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c3.l2cache.PutM_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.PutE_recv : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l2cache.Inv_recv : Accumulator : Sum.u64 = 5329; SumSQ.u64 = 5329; Count.u64 = 5329; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.Inv_recv : Accumulator : Sum.u64 = 2693; SumSQ.u64 = 2693; Count.u64 = 2693; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2759; SumSQ.u64 = 2759; Count.u64 = 2759; Min.u64 = 1; Max.u64 = 1; 
- c3.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1950; SumSQ.u64 = 1950; Count.u64 = 1950; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 809; SumSQ.u64 = 809; Count.u64 = 809; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1905,9 +1905,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c4.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; 
- c4.l1cache.GetS_recv : Accumulator : Sum.u64 = 4533; SumSQ.u64 = 4533; Count.u64 = 4533; Min.u64 = 1; Max.u64 = 1; 
- c4.l1cache.GetX_recv : Accumulator : Sum.u64 = 498; SumSQ.u64 = 498; Count.u64 = 498; Min.u64 = 1; Max.u64 = 1; 
+ c4.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c4.l1cache.GetS_recv : Accumulator : Sum.u64 = 4506; SumSQ.u64 = 4506; Count.u64 = 4506; Min.u64 = 1; Max.u64 = 1; 
+ c4.l1cache.GetX_recv : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 494; Min.u64 = 1; Max.u64 = 1; 
  c4.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2138,11 +2138,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c4.l2cache.PutM_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.PutE_recv : Accumulator : Sum.u64 = 1060; SumSQ.u64 = 1060; Count.u64 = 1060; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l2cache.Inv_recv : Accumulator : Sum.u64 = 5383; SumSQ.u64 = 5383; Count.u64 = 5383; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.Inv_recv : Accumulator : Sum.u64 = 2722; SumSQ.u64 = 2722; Count.u64 = 2722; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2676; SumSQ.u64 = 2676; Count.u64 = 2676; Min.u64 = 1; Max.u64 = 1; 
- c4.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1911; SumSQ.u64 = 1911; Count.u64 = 1911; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 765; SumSQ.u64 = 765; Count.u64 = 765; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2286,9 +2286,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c5.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- c5.l1cache.GetS_recv : Accumulator : Sum.u64 = 4567; SumSQ.u64 = 4567; Count.u64 = 4567; Min.u64 = 1; Max.u64 = 1; 
- c5.l1cache.GetX_recv : Accumulator : Sum.u64 = 462; SumSQ.u64 = 462; Count.u64 = 462; Min.u64 = 1; Max.u64 = 1; 
+ c5.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c5.l1cache.GetS_recv : Accumulator : Sum.u64 = 4542; SumSQ.u64 = 4542; Count.u64 = 4542; Min.u64 = 1; Max.u64 = 1; 
+ c5.l1cache.GetX_recv : Accumulator : Sum.u64 = 458; SumSQ.u64 = 458; Count.u64 = 458; Min.u64 = 1; Max.u64 = 1; 
  c5.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2519,11 +2519,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c5.l2cache.PutM_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.PutE_recv : Accumulator : Sum.u64 = 1046; SumSQ.u64 = 1046; Count.u64 = 1046; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l2cache.Inv_recv : Accumulator : Sum.u64 = 5455; SumSQ.u64 = 5455; Count.u64 = 5455; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.Inv_recv : Accumulator : Sum.u64 = 2753; SumSQ.u64 = 2753; Count.u64 = 2753; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2642; SumSQ.u64 = 2642; Count.u64 = 2642; Min.u64 = 1; Max.u64 = 1; 
- c5.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1859; SumSQ.u64 = 1859; Count.u64 = 1859; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 783; SumSQ.u64 = 783; Count.u64 = 783; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2667,9 +2667,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c6.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
- c6.l1cache.GetS_recv : Accumulator : Sum.u64 = 4514; SumSQ.u64 = 4514; Count.u64 = 4514; Min.u64 = 1; Max.u64 = 1; 
- c6.l1cache.GetX_recv : Accumulator : Sum.u64 = 513; SumSQ.u64 = 513; Count.u64 = 513; Min.u64 = 1; Max.u64 = 1; 
+ c6.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c6.l1cache.GetS_recv : Accumulator : Sum.u64 = 4490; SumSQ.u64 = 4490; Count.u64 = 4490; Min.u64 = 1; Max.u64 = 1; 
+ c6.l1cache.GetX_recv : Accumulator : Sum.u64 = 510; SumSQ.u64 = 510; Count.u64 = 510; Min.u64 = 1; Max.u64 = 1; 
  c6.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2900,11 +2900,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c6.l2cache.PutM_recv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.PutE_recv : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l2cache.Inv_recv : Accumulator : Sum.u64 = 5317; SumSQ.u64 = 5317; Count.u64 = 5317; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.Inv_recv : Accumulator : Sum.u64 = 2688; SumSQ.u64 = 2688; Count.u64 = 2688; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2725; SumSQ.u64 = 2725; Count.u64 = 2725; Min.u64 = 1; Max.u64 = 1; 
- c6.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 176; SumSQ.u64 = 176; Count.u64 = 176; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1934; SumSQ.u64 = 1934; Count.u64 = 1934; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 791; SumSQ.u64 = 791; Count.u64 = 791; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3048,9 +3048,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c7.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
- c7.l1cache.GetS_recv : Accumulator : Sum.u64 = 4534; SumSQ.u64 = 4534; Count.u64 = 4534; Min.u64 = 1; Max.u64 = 1; 
- c7.l1cache.GetX_recv : Accumulator : Sum.u64 = 486; SumSQ.u64 = 486; Count.u64 = 486; Min.u64 = 1; Max.u64 = 1; 
+ c7.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c7.l1cache.GetS_recv : Accumulator : Sum.u64 = 4517; SumSQ.u64 = 4517; Count.u64 = 4517; Min.u64 = 1; Max.u64 = 1; 
+ c7.l1cache.GetX_recv : Accumulator : Sum.u64 = 483; SumSQ.u64 = 483; Count.u64 = 483; Min.u64 = 1; Max.u64 = 1; 
  c7.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3281,11 +3281,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c7.l2cache.PutM_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.PutE_recv : Accumulator : Sum.u64 = 1078; SumSQ.u64 = 1078; Count.u64 = 1078; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l2cache.Inv_recv : Accumulator : Sum.u64 = 5329; SumSQ.u64 = 5329; Count.u64 = 5329; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.Inv_recv : Accumulator : Sum.u64 = 2686; SumSQ.u64 = 2686; Count.u64 = 2686; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2719; SumSQ.u64 = 2719; Count.u64 = 2719; Min.u64 = 1; Max.u64 = 1; 
- c7.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1920; SumSQ.u64 = 1920; Count.u64 = 1920; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 799; SumSQ.u64 = 799; Count.u64 = 799; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_3.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_3.out
index 7dbff05db..e44acb927 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_3.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_3.out
@@ -220,9 +220,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 99468; SumSQ.u64 = 99468; Count.u64 = 99468; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 87446; SumSQ.u64 = 87446; Count.u64 = 87446; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 9720; SumSQ.u64 = 9720; Count.u64 = 9720; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 35632; SumSQ.u64 = 35632; Count.u64 = 35632; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 3929; SumSQ.u64 = 3929; Count.u64 = 3929; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -241,7 +241,7 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  l3cache.FetchResp_recv : Accumulator : Sum.u64 = 15366; SumSQ.u64 = 15366; Count.u64 = 15366; Min.u64 = 1; Max.u64 = 1; 
  l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 895; SumSQ.u64 = 895; Count.u64 = 895; Min.u64 = 1; Max.u64 = 1; 
  l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.AckInv_recv : Accumulator : Sum.u64 = 21603; SumSQ.u64 = 21603; Count.u64 = 21603; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.AckInv_recv : Accumulator : Sum.u64 = 21592; SumSQ.u64 = 21592; Count.u64 = 21592; Min.u64 = 1; Max.u64 = 1; 
  l3cache.AckPut_recv : Accumulator : Sum.u64 = 36500; SumSQ.u64 = 36500; Count.u64 = 36500; Min.u64 = 1; Max.u64 = 1; 
  l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 842688270; SumSQ.u64 = 66870425350; Count.u64 = 10660197; Min.u64 = 0; Max.u64 = 80; 
  l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -381,9 +381,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 4549; SumSQ.u64 = 4549; Count.u64 = 4549; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 4503; SumSQ.u64 = 4503; Count.u64 = 4503; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 497; SumSQ.u64 = 497; Count.u64 = 497; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -614,11 +614,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c0.l2cache.PutM_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.PutE_recv : Accumulator : Sum.u64 = 1025; SumSQ.u64 = 1025; Count.u64 = 1025; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l2cache.Inv_recv : Accumulator : Sum.u64 = 5336; SumSQ.u64 = 5336; Count.u64 = 5336; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.Inv_recv : Accumulator : Sum.u64 = 2700; SumSQ.u64 = 2700; Count.u64 = 2700; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2682; SumSQ.u64 = 2682; Count.u64 = 2682; Min.u64 = 1; Max.u64 = 1; 
- c0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1874; SumSQ.u64 = 1874; Count.u64 = 1874; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 808; SumSQ.u64 = 808; Count.u64 = 808; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -762,9 +762,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 4499; SumSQ.u64 = 4499; Count.u64 = 4499; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 527; SumSQ.u64 = 527; Count.u64 = 527; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 4476; SumSQ.u64 = 4476; Count.u64 = 4476; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 524; SumSQ.u64 = 524; Count.u64 = 524; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -995,11 +995,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c1.l2cache.PutM_recv : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.PutE_recv : Accumulator : Sum.u64 = 1029; SumSQ.u64 = 1029; Count.u64 = 1029; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l2cache.Inv_recv : Accumulator : Sum.u64 = 5302; SumSQ.u64 = 5302; Count.u64 = 5302; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.Inv_recv : Accumulator : Sum.u64 = 2681; SumSQ.u64 = 2681; Count.u64 = 2681; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2833; SumSQ.u64 = 2833; Count.u64 = 2833; Min.u64 = 1; Max.u64 = 1; 
- c1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1971; SumSQ.u64 = 1971; Count.u64 = 1971; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 862; SumSQ.u64 = 862; Count.u64 = 862; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1143,9 +1143,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 4532; SumSQ.u64 = 4532; Count.u64 = 4532; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 491; SumSQ.u64 = 491; Count.u64 = 491; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 4510; SumSQ.u64 = 4510; Count.u64 = 4510; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 490; SumSQ.u64 = 490; Count.u64 = 490; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1376,11 +1376,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c2.l2cache.PutM_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.PutE_recv : Accumulator : Sum.u64 = 1065; SumSQ.u64 = 1065; Count.u64 = 1065; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l2cache.Inv_recv : Accumulator : Sum.u64 = 5285; SumSQ.u64 = 5285; Count.u64 = 5285; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.Inv_recv : Accumulator : Sum.u64 = 2669; SumSQ.u64 = 2669; Count.u64 = 2669; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2768; SumSQ.u64 = 2768; Count.u64 = 2768; Min.u64 = 1; Max.u64 = 1; 
- c2.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1947; SumSQ.u64 = 1947; Count.u64 = 1947; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 821; SumSQ.u64 = 821; Count.u64 = 821; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1524,9 +1524,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 4541; SumSQ.u64 = 4541; Count.u64 = 4541; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 487; SumSQ.u64 = 487; Count.u64 = 487; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 4515; SumSQ.u64 = 4515; Count.u64 = 4515; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1757,11 +1757,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c3.l2cache.PutM_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.PutE_recv : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l2cache.Inv_recv : Accumulator : Sum.u64 = 5329; SumSQ.u64 = 5329; Count.u64 = 5329; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.Inv_recv : Accumulator : Sum.u64 = 2693; SumSQ.u64 = 2693; Count.u64 = 2693; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2759; SumSQ.u64 = 2759; Count.u64 = 2759; Min.u64 = 1; Max.u64 = 1; 
- c3.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1950; SumSQ.u64 = 1950; Count.u64 = 1950; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 809; SumSQ.u64 = 809; Count.u64 = 809; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1905,9 +1905,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c4.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; 
- c4.l1cache.GetS_recv : Accumulator : Sum.u64 = 4533; SumSQ.u64 = 4533; Count.u64 = 4533; Min.u64 = 1; Max.u64 = 1; 
- c4.l1cache.GetX_recv : Accumulator : Sum.u64 = 498; SumSQ.u64 = 498; Count.u64 = 498; Min.u64 = 1; Max.u64 = 1; 
+ c4.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c4.l1cache.GetS_recv : Accumulator : Sum.u64 = 4506; SumSQ.u64 = 4506; Count.u64 = 4506; Min.u64 = 1; Max.u64 = 1; 
+ c4.l1cache.GetX_recv : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 494; Min.u64 = 1; Max.u64 = 1; 
  c4.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2138,11 +2138,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c4.l2cache.PutM_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.PutE_recv : Accumulator : Sum.u64 = 1060; SumSQ.u64 = 1060; Count.u64 = 1060; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l2cache.Inv_recv : Accumulator : Sum.u64 = 5383; SumSQ.u64 = 5383; Count.u64 = 5383; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.Inv_recv : Accumulator : Sum.u64 = 2722; SumSQ.u64 = 2722; Count.u64 = 2722; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2676; SumSQ.u64 = 2676; Count.u64 = 2676; Min.u64 = 1; Max.u64 = 1; 
- c4.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1911; SumSQ.u64 = 1911; Count.u64 = 1911; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 765; SumSQ.u64 = 765; Count.u64 = 765; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2286,9 +2286,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c5.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- c5.l1cache.GetS_recv : Accumulator : Sum.u64 = 4567; SumSQ.u64 = 4567; Count.u64 = 4567; Min.u64 = 1; Max.u64 = 1; 
- c5.l1cache.GetX_recv : Accumulator : Sum.u64 = 462; SumSQ.u64 = 462; Count.u64 = 462; Min.u64 = 1; Max.u64 = 1; 
+ c5.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c5.l1cache.GetS_recv : Accumulator : Sum.u64 = 4542; SumSQ.u64 = 4542; Count.u64 = 4542; Min.u64 = 1; Max.u64 = 1; 
+ c5.l1cache.GetX_recv : Accumulator : Sum.u64 = 458; SumSQ.u64 = 458; Count.u64 = 458; Min.u64 = 1; Max.u64 = 1; 
  c5.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2519,11 +2519,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c5.l2cache.PutM_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.PutE_recv : Accumulator : Sum.u64 = 1046; SumSQ.u64 = 1046; Count.u64 = 1046; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l2cache.Inv_recv : Accumulator : Sum.u64 = 5455; SumSQ.u64 = 5455; Count.u64 = 5455; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.Inv_recv : Accumulator : Sum.u64 = 2753; SumSQ.u64 = 2753; Count.u64 = 2753; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2642; SumSQ.u64 = 2642; Count.u64 = 2642; Min.u64 = 1; Max.u64 = 1; 
- c5.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1859; SumSQ.u64 = 1859; Count.u64 = 1859; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 783; SumSQ.u64 = 783; Count.u64 = 783; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2667,9 +2667,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c6.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
- c6.l1cache.GetS_recv : Accumulator : Sum.u64 = 4514; SumSQ.u64 = 4514; Count.u64 = 4514; Min.u64 = 1; Max.u64 = 1; 
- c6.l1cache.GetX_recv : Accumulator : Sum.u64 = 513; SumSQ.u64 = 513; Count.u64 = 513; Min.u64 = 1; Max.u64 = 1; 
+ c6.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c6.l1cache.GetS_recv : Accumulator : Sum.u64 = 4490; SumSQ.u64 = 4490; Count.u64 = 4490; Min.u64 = 1; Max.u64 = 1; 
+ c6.l1cache.GetX_recv : Accumulator : Sum.u64 = 510; SumSQ.u64 = 510; Count.u64 = 510; Min.u64 = 1; Max.u64 = 1; 
  c6.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2900,11 +2900,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c6.l2cache.PutM_recv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.PutE_recv : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l2cache.Inv_recv : Accumulator : Sum.u64 = 5317; SumSQ.u64 = 5317; Count.u64 = 5317; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.Inv_recv : Accumulator : Sum.u64 = 2688; SumSQ.u64 = 2688; Count.u64 = 2688; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2725; SumSQ.u64 = 2725; Count.u64 = 2725; Min.u64 = 1; Max.u64 = 1; 
- c6.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 176; SumSQ.u64 = 176; Count.u64 = 176; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1934; SumSQ.u64 = 1934; Count.u64 = 1934; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 791; SumSQ.u64 = 791; Count.u64 = 791; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3048,9 +3048,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c7.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
- c7.l1cache.GetS_recv : Accumulator : Sum.u64 = 4534; SumSQ.u64 = 4534; Count.u64 = 4534; Min.u64 = 1; Max.u64 = 1; 
- c7.l1cache.GetX_recv : Accumulator : Sum.u64 = 486; SumSQ.u64 = 486; Count.u64 = 486; Min.u64 = 1; Max.u64 = 1; 
+ c7.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c7.l1cache.GetS_recv : Accumulator : Sum.u64 = 4517; SumSQ.u64 = 4517; Count.u64 = 4517; Min.u64 = 1; Max.u64 = 1; 
+ c7.l1cache.GetX_recv : Accumulator : Sum.u64 = 483; SumSQ.u64 = 483; Count.u64 = 483; Min.u64 = 1; Max.u64 = 1; 
  c7.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3281,11 +3281,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c7.l2cache.PutM_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.PutE_recv : Accumulator : Sum.u64 = 1078; SumSQ.u64 = 1078; Count.u64 = 1078; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l2cache.Inv_recv : Accumulator : Sum.u64 = 5329; SumSQ.u64 = 5329; Count.u64 = 5329; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.Inv_recv : Accumulator : Sum.u64 = 2686; SumSQ.u64 = 2686; Count.u64 = 2686; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2719; SumSQ.u64 = 2719; Count.u64 = 2719; Min.u64 = 1; Max.u64 = 1; 
- c7.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1920; SumSQ.u64 = 1920; Count.u64 = 1920; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 799; SumSQ.u64 = 799; Count.u64 = 799; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_3_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_3_MC.out
index ff6709a1c..0c67e640b 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_3_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_3_MC.out
@@ -8,12 +8,12 @@ TrivialCPU: Test Completed Successfuly
 TrivialCPU: Test Completed Successfuly
 TrivialCPU cpu4 Finished after 5000 issued reads, 5000 returned (15857113 clocks)
 TrivialCPU cpu3 Finished after 5000 issued reads, 5000 returned (15904248 clocks)
-TrivialCPU cpu7 Finished after 5000 issued reads, 5000 returned (15989437 clocks)
+TrivialCPU cpu0 Finished after 5000 issued reads, 5000 returned (16006302 clocks)
 TrivialCPU cpu1 Finished after 5000 issued reads, 5000 returned (15858410 clocks)
 TrivialCPU cpu2 Finished after 5000 issued reads, 5000 returned (15969113 clocks)
-TrivialCPU cpu0 Finished after 5000 issued reads, 5000 returned (16006302 clocks)
-TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks)
 TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks)
+TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks)
+TrivialCPU cpu7 Finished after 5000 issued reads, 5000 returned (15989437 clocks)
  l3cache:memlink.packet_latency : Accumulator : Sum.u64 = 7032280; SumSQ.u64 = 668066600; Count.u64 = 74024; Min.u64 = 95; Max.u64 = 95; 
  l3cache:memlink.send_bit_count : Accumulator : Sum.u64 = 6681088; SumSQ.u64 = 1547075584; Count.u64 = 74024; Min.u64 = 64; Max.u64 = 576; 
  l3cache:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -220,9 +220,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 99468; SumSQ.u64 = 99468; Count.u64 = 99468; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 87446; SumSQ.u64 = 87446; Count.u64 = 87446; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 9720; SumSQ.u64 = 9720; Count.u64 = 9720; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 35632; SumSQ.u64 = 35632; Count.u64 = 35632; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 3929; SumSQ.u64 = 3929; Count.u64 = 3929; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -241,7 +241,7 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  l3cache.FetchResp_recv : Accumulator : Sum.u64 = 15366; SumSQ.u64 = 15366; Count.u64 = 15366; Min.u64 = 1; Max.u64 = 1; 
  l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 895; SumSQ.u64 = 895; Count.u64 = 895; Min.u64 = 1; Max.u64 = 1; 
  l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.AckInv_recv : Accumulator : Sum.u64 = 21603; SumSQ.u64 = 21603; Count.u64 = 21603; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.AckInv_recv : Accumulator : Sum.u64 = 21592; SumSQ.u64 = 21592; Count.u64 = 21592; Min.u64 = 1; Max.u64 = 1; 
  l3cache.AckPut_recv : Accumulator : Sum.u64 = 36500; SumSQ.u64 = 36500; Count.u64 = 36500; Min.u64 = 1; Max.u64 = 1; 
  l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 842688270; SumSQ.u64 = 66870425350; Count.u64 = 10660197; Min.u64 = 0; Max.u64 = 80; 
  l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -381,9 +381,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 4549; SumSQ.u64 = 4549; Count.u64 = 4549; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 4503; SumSQ.u64 = 4503; Count.u64 = 4503; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 497; SumSQ.u64 = 497; Count.u64 = 497; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -614,11 +614,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c0.l2cache.PutM_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.PutE_recv : Accumulator : Sum.u64 = 1025; SumSQ.u64 = 1025; Count.u64 = 1025; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l2cache.Inv_recv : Accumulator : Sum.u64 = 5336; SumSQ.u64 = 5336; Count.u64 = 5336; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.Inv_recv : Accumulator : Sum.u64 = 2700; SumSQ.u64 = 2700; Count.u64 = 2700; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2682; SumSQ.u64 = 2682; Count.u64 = 2682; Min.u64 = 1; Max.u64 = 1; 
- c0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1874; SumSQ.u64 = 1874; Count.u64 = 1874; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 808; SumSQ.u64 = 808; Count.u64 = 808; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -762,9 +762,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 4499; SumSQ.u64 = 4499; Count.u64 = 4499; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 527; SumSQ.u64 = 527; Count.u64 = 527; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 4476; SumSQ.u64 = 4476; Count.u64 = 4476; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 524; SumSQ.u64 = 524; Count.u64 = 524; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -995,11 +995,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c1.l2cache.PutM_recv : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.PutE_recv : Accumulator : Sum.u64 = 1029; SumSQ.u64 = 1029; Count.u64 = 1029; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l2cache.Inv_recv : Accumulator : Sum.u64 = 5302; SumSQ.u64 = 5302; Count.u64 = 5302; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.Inv_recv : Accumulator : Sum.u64 = 2681; SumSQ.u64 = 2681; Count.u64 = 2681; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2833; SumSQ.u64 = 2833; Count.u64 = 2833; Min.u64 = 1; Max.u64 = 1; 
- c1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1971; SumSQ.u64 = 1971; Count.u64 = 1971; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 862; SumSQ.u64 = 862; Count.u64 = 862; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1143,9 +1143,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 4532; SumSQ.u64 = 4532; Count.u64 = 4532; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 491; SumSQ.u64 = 491; Count.u64 = 491; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 4510; SumSQ.u64 = 4510; Count.u64 = 4510; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 490; SumSQ.u64 = 490; Count.u64 = 490; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1376,11 +1376,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c2.l2cache.PutM_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.PutE_recv : Accumulator : Sum.u64 = 1065; SumSQ.u64 = 1065; Count.u64 = 1065; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l2cache.Inv_recv : Accumulator : Sum.u64 = 5285; SumSQ.u64 = 5285; Count.u64 = 5285; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.Inv_recv : Accumulator : Sum.u64 = 2669; SumSQ.u64 = 2669; Count.u64 = 2669; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2768; SumSQ.u64 = 2768; Count.u64 = 2768; Min.u64 = 1; Max.u64 = 1; 
- c2.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1947; SumSQ.u64 = 1947; Count.u64 = 1947; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 821; SumSQ.u64 = 821; Count.u64 = 821; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1524,9 +1524,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 4541; SumSQ.u64 = 4541; Count.u64 = 4541; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 487; SumSQ.u64 = 487; Count.u64 = 487; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 4515; SumSQ.u64 = 4515; Count.u64 = 4515; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1757,11 +1757,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c3.l2cache.PutM_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.PutE_recv : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l2cache.Inv_recv : Accumulator : Sum.u64 = 5329; SumSQ.u64 = 5329; Count.u64 = 5329; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.Inv_recv : Accumulator : Sum.u64 = 2693; SumSQ.u64 = 2693; Count.u64 = 2693; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2759; SumSQ.u64 = 2759; Count.u64 = 2759; Min.u64 = 1; Max.u64 = 1; 
- c3.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1950; SumSQ.u64 = 1950; Count.u64 = 1950; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 809; SumSQ.u64 = 809; Count.u64 = 809; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1905,9 +1905,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c4.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; 
- c4.l1cache.GetS_recv : Accumulator : Sum.u64 = 4533; SumSQ.u64 = 4533; Count.u64 = 4533; Min.u64 = 1; Max.u64 = 1; 
- c4.l1cache.GetX_recv : Accumulator : Sum.u64 = 498; SumSQ.u64 = 498; Count.u64 = 498; Min.u64 = 1; Max.u64 = 1; 
+ c4.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c4.l1cache.GetS_recv : Accumulator : Sum.u64 = 4506; SumSQ.u64 = 4506; Count.u64 = 4506; Min.u64 = 1; Max.u64 = 1; 
+ c4.l1cache.GetX_recv : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 494; Min.u64 = 1; Max.u64 = 1; 
  c4.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2138,11 +2138,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c4.l2cache.PutM_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.PutE_recv : Accumulator : Sum.u64 = 1060; SumSQ.u64 = 1060; Count.u64 = 1060; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l2cache.Inv_recv : Accumulator : Sum.u64 = 5383; SumSQ.u64 = 5383; Count.u64 = 5383; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.Inv_recv : Accumulator : Sum.u64 = 2722; SumSQ.u64 = 2722; Count.u64 = 2722; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2676; SumSQ.u64 = 2676; Count.u64 = 2676; Min.u64 = 1; Max.u64 = 1; 
- c4.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1911; SumSQ.u64 = 1911; Count.u64 = 1911; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 765; SumSQ.u64 = 765; Count.u64 = 765; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2286,9 +2286,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c5.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- c5.l1cache.GetS_recv : Accumulator : Sum.u64 = 4567; SumSQ.u64 = 4567; Count.u64 = 4567; Min.u64 = 1; Max.u64 = 1; 
- c5.l1cache.GetX_recv : Accumulator : Sum.u64 = 462; SumSQ.u64 = 462; Count.u64 = 462; Min.u64 = 1; Max.u64 = 1; 
+ c5.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c5.l1cache.GetS_recv : Accumulator : Sum.u64 = 4542; SumSQ.u64 = 4542; Count.u64 = 4542; Min.u64 = 1; Max.u64 = 1; 
+ c5.l1cache.GetX_recv : Accumulator : Sum.u64 = 458; SumSQ.u64 = 458; Count.u64 = 458; Min.u64 = 1; Max.u64 = 1; 
  c5.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2519,11 +2519,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c5.l2cache.PutM_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.PutE_recv : Accumulator : Sum.u64 = 1046; SumSQ.u64 = 1046; Count.u64 = 1046; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l2cache.Inv_recv : Accumulator : Sum.u64 = 5455; SumSQ.u64 = 5455; Count.u64 = 5455; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.Inv_recv : Accumulator : Sum.u64 = 2753; SumSQ.u64 = 2753; Count.u64 = 2753; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2642; SumSQ.u64 = 2642; Count.u64 = 2642; Min.u64 = 1; Max.u64 = 1; 
- c5.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1859; SumSQ.u64 = 1859; Count.u64 = 1859; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 783; SumSQ.u64 = 783; Count.u64 = 783; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2667,9 +2667,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c6.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
- c6.l1cache.GetS_recv : Accumulator : Sum.u64 = 4514; SumSQ.u64 = 4514; Count.u64 = 4514; Min.u64 = 1; Max.u64 = 1; 
- c6.l1cache.GetX_recv : Accumulator : Sum.u64 = 513; SumSQ.u64 = 513; Count.u64 = 513; Min.u64 = 1; Max.u64 = 1; 
+ c6.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c6.l1cache.GetS_recv : Accumulator : Sum.u64 = 4490; SumSQ.u64 = 4490; Count.u64 = 4490; Min.u64 = 1; Max.u64 = 1; 
+ c6.l1cache.GetX_recv : Accumulator : Sum.u64 = 510; SumSQ.u64 = 510; Count.u64 = 510; Min.u64 = 1; Max.u64 = 1; 
  c6.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2900,11 +2900,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c6.l2cache.PutM_recv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.PutE_recv : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l2cache.Inv_recv : Accumulator : Sum.u64 = 5317; SumSQ.u64 = 5317; Count.u64 = 5317; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.Inv_recv : Accumulator : Sum.u64 = 2688; SumSQ.u64 = 2688; Count.u64 = 2688; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2725; SumSQ.u64 = 2725; Count.u64 = 2725; Min.u64 = 1; Max.u64 = 1; 
- c6.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 176; SumSQ.u64 = 176; Count.u64 = 176; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1934; SumSQ.u64 = 1934; Count.u64 = 1934; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 791; SumSQ.u64 = 791; Count.u64 = 791; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3048,9 +3048,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c7.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
- c7.l1cache.GetS_recv : Accumulator : Sum.u64 = 4534; SumSQ.u64 = 4534; Count.u64 = 4534; Min.u64 = 1; Max.u64 = 1; 
- c7.l1cache.GetX_recv : Accumulator : Sum.u64 = 486; SumSQ.u64 = 486; Count.u64 = 486; Min.u64 = 1; Max.u64 = 1; 
+ c7.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c7.l1cache.GetS_recv : Accumulator : Sum.u64 = 4517; SumSQ.u64 = 4517; Count.u64 = 4517; Min.u64 = 1; Max.u64 = 1; 
+ c7.l1cache.GetX_recv : Accumulator : Sum.u64 = 483; SumSQ.u64 = 483; Count.u64 = 483; Min.u64 = 1; Max.u64 = 1; 
  c7.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3281,11 +3281,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c7.l2cache.PutM_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.PutE_recv : Accumulator : Sum.u64 = 1078; SumSQ.u64 = 1078; Count.u64 = 1078; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l2cache.Inv_recv : Accumulator : Sum.u64 = 5329; SumSQ.u64 = 5329; Count.u64 = 5329; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.Inv_recv : Accumulator : Sum.u64 = 2686; SumSQ.u64 = 2686; Count.u64 = 2686; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2719; SumSQ.u64 = 2719; Count.u64 = 2719; Min.u64 = 1; Max.u64 = 1; 
- c7.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1920; SumSQ.u64 = 1920; Count.u64 = 1920; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 799; SumSQ.u64 = 799; Count.u64 = 799; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_4.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_4.out
index 160fe307c..b0c45b2bf 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_4.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_4.out
@@ -220,9 +220,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 99468; SumSQ.u64 = 99468; Count.u64 = 99468; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 87446; SumSQ.u64 = 87446; Count.u64 = 87446; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 9720; SumSQ.u64 = 9720; Count.u64 = 9720; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 35632; SumSQ.u64 = 35632; Count.u64 = 35632; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 3929; SumSQ.u64 = 3929; Count.u64 = 3929; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -241,7 +241,7 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  l3cache.FetchResp_recv : Accumulator : Sum.u64 = 15366; SumSQ.u64 = 15366; Count.u64 = 15366; Min.u64 = 1; Max.u64 = 1; 
  l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 895; SumSQ.u64 = 895; Count.u64 = 895; Min.u64 = 1; Max.u64 = 1; 
  l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.AckInv_recv : Accumulator : Sum.u64 = 21603; SumSQ.u64 = 21603; Count.u64 = 21603; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.AckInv_recv : Accumulator : Sum.u64 = 21592; SumSQ.u64 = 21592; Count.u64 = 21592; Min.u64 = 1; Max.u64 = 1; 
  l3cache.AckPut_recv : Accumulator : Sum.u64 = 36500; SumSQ.u64 = 36500; Count.u64 = 36500; Min.u64 = 1; Max.u64 = 1; 
  l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 842688270; SumSQ.u64 = 66870425350; Count.u64 = 10660197; Min.u64 = 0; Max.u64 = 80; 
  l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -381,9 +381,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 4549; SumSQ.u64 = 4549; Count.u64 = 4549; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 4503; SumSQ.u64 = 4503; Count.u64 = 4503; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 497; SumSQ.u64 = 497; Count.u64 = 497; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -614,11 +614,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c0.l2cache.PutM_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.PutE_recv : Accumulator : Sum.u64 = 1025; SumSQ.u64 = 1025; Count.u64 = 1025; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l2cache.Inv_recv : Accumulator : Sum.u64 = 5336; SumSQ.u64 = 5336; Count.u64 = 5336; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.Inv_recv : Accumulator : Sum.u64 = 2700; SumSQ.u64 = 2700; Count.u64 = 2700; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2682; SumSQ.u64 = 2682; Count.u64 = 2682; Min.u64 = 1; Max.u64 = 1; 
- c0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1874; SumSQ.u64 = 1874; Count.u64 = 1874; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 808; SumSQ.u64 = 808; Count.u64 = 808; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -762,9 +762,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 4499; SumSQ.u64 = 4499; Count.u64 = 4499; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 527; SumSQ.u64 = 527; Count.u64 = 527; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 4476; SumSQ.u64 = 4476; Count.u64 = 4476; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 524; SumSQ.u64 = 524; Count.u64 = 524; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -995,11 +995,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c1.l2cache.PutM_recv : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.PutE_recv : Accumulator : Sum.u64 = 1029; SumSQ.u64 = 1029; Count.u64 = 1029; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l2cache.Inv_recv : Accumulator : Sum.u64 = 5302; SumSQ.u64 = 5302; Count.u64 = 5302; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.Inv_recv : Accumulator : Sum.u64 = 2681; SumSQ.u64 = 2681; Count.u64 = 2681; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2833; SumSQ.u64 = 2833; Count.u64 = 2833; Min.u64 = 1; Max.u64 = 1; 
- c1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1971; SumSQ.u64 = 1971; Count.u64 = 1971; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 862; SumSQ.u64 = 862; Count.u64 = 862; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1143,9 +1143,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 4532; SumSQ.u64 = 4532; Count.u64 = 4532; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 491; SumSQ.u64 = 491; Count.u64 = 491; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 4510; SumSQ.u64 = 4510; Count.u64 = 4510; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 490; SumSQ.u64 = 490; Count.u64 = 490; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1376,11 +1376,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c2.l2cache.PutM_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.PutE_recv : Accumulator : Sum.u64 = 1065; SumSQ.u64 = 1065; Count.u64 = 1065; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l2cache.Inv_recv : Accumulator : Sum.u64 = 5285; SumSQ.u64 = 5285; Count.u64 = 5285; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.Inv_recv : Accumulator : Sum.u64 = 2669; SumSQ.u64 = 2669; Count.u64 = 2669; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2768; SumSQ.u64 = 2768; Count.u64 = 2768; Min.u64 = 1; Max.u64 = 1; 
- c2.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1947; SumSQ.u64 = 1947; Count.u64 = 1947; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 821; SumSQ.u64 = 821; Count.u64 = 821; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1524,9 +1524,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 4541; SumSQ.u64 = 4541; Count.u64 = 4541; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 487; SumSQ.u64 = 487; Count.u64 = 487; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 4515; SumSQ.u64 = 4515; Count.u64 = 4515; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1757,11 +1757,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c3.l2cache.PutM_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.PutE_recv : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l2cache.Inv_recv : Accumulator : Sum.u64 = 5329; SumSQ.u64 = 5329; Count.u64 = 5329; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.Inv_recv : Accumulator : Sum.u64 = 2693; SumSQ.u64 = 2693; Count.u64 = 2693; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2759; SumSQ.u64 = 2759; Count.u64 = 2759; Min.u64 = 1; Max.u64 = 1; 
- c3.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1950; SumSQ.u64 = 1950; Count.u64 = 1950; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 809; SumSQ.u64 = 809; Count.u64 = 809; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1905,9 +1905,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c4.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; 
- c4.l1cache.GetS_recv : Accumulator : Sum.u64 = 4533; SumSQ.u64 = 4533; Count.u64 = 4533; Min.u64 = 1; Max.u64 = 1; 
- c4.l1cache.GetX_recv : Accumulator : Sum.u64 = 498; SumSQ.u64 = 498; Count.u64 = 498; Min.u64 = 1; Max.u64 = 1; 
+ c4.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c4.l1cache.GetS_recv : Accumulator : Sum.u64 = 4506; SumSQ.u64 = 4506; Count.u64 = 4506; Min.u64 = 1; Max.u64 = 1; 
+ c4.l1cache.GetX_recv : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 494; Min.u64 = 1; Max.u64 = 1; 
  c4.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2138,11 +2138,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c4.l2cache.PutM_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.PutE_recv : Accumulator : Sum.u64 = 1060; SumSQ.u64 = 1060; Count.u64 = 1060; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l2cache.Inv_recv : Accumulator : Sum.u64 = 5383; SumSQ.u64 = 5383; Count.u64 = 5383; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.Inv_recv : Accumulator : Sum.u64 = 2722; SumSQ.u64 = 2722; Count.u64 = 2722; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2676; SumSQ.u64 = 2676; Count.u64 = 2676; Min.u64 = 1; Max.u64 = 1; 
- c4.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1911; SumSQ.u64 = 1911; Count.u64 = 1911; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 765; SumSQ.u64 = 765; Count.u64 = 765; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2286,9 +2286,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c5.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- c5.l1cache.GetS_recv : Accumulator : Sum.u64 = 4567; SumSQ.u64 = 4567; Count.u64 = 4567; Min.u64 = 1; Max.u64 = 1; 
- c5.l1cache.GetX_recv : Accumulator : Sum.u64 = 462; SumSQ.u64 = 462; Count.u64 = 462; Min.u64 = 1; Max.u64 = 1; 
+ c5.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c5.l1cache.GetS_recv : Accumulator : Sum.u64 = 4542; SumSQ.u64 = 4542; Count.u64 = 4542; Min.u64 = 1; Max.u64 = 1; 
+ c5.l1cache.GetX_recv : Accumulator : Sum.u64 = 458; SumSQ.u64 = 458; Count.u64 = 458; Min.u64 = 1; Max.u64 = 1; 
  c5.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2519,11 +2519,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c5.l2cache.PutM_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.PutE_recv : Accumulator : Sum.u64 = 1046; SumSQ.u64 = 1046; Count.u64 = 1046; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l2cache.Inv_recv : Accumulator : Sum.u64 = 5455; SumSQ.u64 = 5455; Count.u64 = 5455; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.Inv_recv : Accumulator : Sum.u64 = 2753; SumSQ.u64 = 2753; Count.u64 = 2753; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2642; SumSQ.u64 = 2642; Count.u64 = 2642; Min.u64 = 1; Max.u64 = 1; 
- c5.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1859; SumSQ.u64 = 1859; Count.u64 = 1859; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 783; SumSQ.u64 = 783; Count.u64 = 783; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2667,9 +2667,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c6.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
- c6.l1cache.GetS_recv : Accumulator : Sum.u64 = 4514; SumSQ.u64 = 4514; Count.u64 = 4514; Min.u64 = 1; Max.u64 = 1; 
- c6.l1cache.GetX_recv : Accumulator : Sum.u64 = 513; SumSQ.u64 = 513; Count.u64 = 513; Min.u64 = 1; Max.u64 = 1; 
+ c6.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c6.l1cache.GetS_recv : Accumulator : Sum.u64 = 4490; SumSQ.u64 = 4490; Count.u64 = 4490; Min.u64 = 1; Max.u64 = 1; 
+ c6.l1cache.GetX_recv : Accumulator : Sum.u64 = 510; SumSQ.u64 = 510; Count.u64 = 510; Min.u64 = 1; Max.u64 = 1; 
  c6.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2900,11 +2900,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c6.l2cache.PutM_recv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.PutE_recv : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l2cache.Inv_recv : Accumulator : Sum.u64 = 5317; SumSQ.u64 = 5317; Count.u64 = 5317; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.Inv_recv : Accumulator : Sum.u64 = 2688; SumSQ.u64 = 2688; Count.u64 = 2688; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2725; SumSQ.u64 = 2725; Count.u64 = 2725; Min.u64 = 1; Max.u64 = 1; 
- c6.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 176; SumSQ.u64 = 176; Count.u64 = 176; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1934; SumSQ.u64 = 1934; Count.u64 = 1934; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 791; SumSQ.u64 = 791; Count.u64 = 791; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3048,9 +3048,9 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c7.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
- c7.l1cache.GetS_recv : Accumulator : Sum.u64 = 4534; SumSQ.u64 = 4534; Count.u64 = 4534; Min.u64 = 1; Max.u64 = 1; 
- c7.l1cache.GetX_recv : Accumulator : Sum.u64 = 486; SumSQ.u64 = 486; Count.u64 = 486; Min.u64 = 1; Max.u64 = 1; 
+ c7.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c7.l1cache.GetS_recv : Accumulator : Sum.u64 = 4517; SumSQ.u64 = 4517; Count.u64 = 4517; Min.u64 = 1; Max.u64 = 1; 
+ c7.l1cache.GetX_recv : Accumulator : Sum.u64 = 483; SumSQ.u64 = 483; Count.u64 = 483; Min.u64 = 1; Max.u64 = 1; 
  c7.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3281,11 +3281,11 @@ TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks
  c7.l2cache.PutM_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.PutE_recv : Accumulator : Sum.u64 = 1078; SumSQ.u64 = 1078; Count.u64 = 1078; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l2cache.Inv_recv : Accumulator : Sum.u64 = 5329; SumSQ.u64 = 5329; Count.u64 = 5329; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.Inv_recv : Accumulator : Sum.u64 = 2686; SumSQ.u64 = 2686; Count.u64 = 2686; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2719; SumSQ.u64 = 2719; Count.u64 = 2719; Min.u64 = 1; Max.u64 = 1; 
- c7.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1920; SumSQ.u64 = 1920; Count.u64 = 1920; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 799; SumSQ.u64 = 799; Count.u64 = 799; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_4_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_4_MC.out
index 39753a566..96b3ac0c0 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_4_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_4_MC.out
@@ -8,12 +8,12 @@ TrivialCPU: Test Completed Successfuly
 TrivialCPU: Test Completed Successfuly
 TrivialCPU cpu4 Finished after 5000 issued reads, 5000 returned (15857113 clocks)
 TrivialCPU cpu3 Finished after 5000 issued reads, 5000 returned (15904248 clocks)
-TrivialCPU cpu1 Finished after 5000 issued reads, 5000 returned (15858410 clocks)
 TrivialCPU cpu0 Finished after 5000 issued reads, 5000 returned (16006302 clocks)
-TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks)
+TrivialCPU cpu1 Finished after 5000 issued reads, 5000 returned (15858410 clocks)
 TrivialCPU cpu2 Finished after 5000 issued reads, 5000 returned (15969113 clocks)
-TrivialCPU cpu7 Finished after 5000 issued reads, 5000 returned (15989437 clocks)
 TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks)
+TrivialCPU cpu6 Finished after 5000 issued reads, 5000 returned (15837221 clocks)
+TrivialCPU cpu7 Finished after 5000 issued reads, 5000 returned (15989437 clocks)
  l3cache:memlink.packet_latency : Accumulator : Sum.u64 = 7032280; SumSQ.u64 = 668066600; Count.u64 = 74024; Min.u64 = 95; Max.u64 = 95; 
  l3cache:memlink.send_bit_count : Accumulator : Sum.u64 = 6681088; SumSQ.u64 = 1547075584; Count.u64 = 74024; Min.u64 = 64; Max.u64 = 576; 
  l3cache:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -220,9 +220,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 99468; SumSQ.u64 = 99468; Count.u64 = 99468; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 87446; SumSQ.u64 = 87446; Count.u64 = 87446; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 9720; SumSQ.u64 = 9720; Count.u64 = 9720; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 35632; SumSQ.u64 = 35632; Count.u64 = 35632; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 3929; SumSQ.u64 = 3929; Count.u64 = 3929; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -241,7 +241,7 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  l3cache.FetchResp_recv : Accumulator : Sum.u64 = 15366; SumSQ.u64 = 15366; Count.u64 = 15366; Min.u64 = 1; Max.u64 = 1; 
  l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 895; SumSQ.u64 = 895; Count.u64 = 895; Min.u64 = 1; Max.u64 = 1; 
  l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.AckInv_recv : Accumulator : Sum.u64 = 21603; SumSQ.u64 = 21603; Count.u64 = 21603; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.AckInv_recv : Accumulator : Sum.u64 = 21592; SumSQ.u64 = 21592; Count.u64 = 21592; Min.u64 = 1; Max.u64 = 1; 
  l3cache.AckPut_recv : Accumulator : Sum.u64 = 36500; SumSQ.u64 = 36500; Count.u64 = 36500; Min.u64 = 1; Max.u64 = 1; 
  l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 842688270; SumSQ.u64 = 66870425350; Count.u64 = 10660197; Min.u64 = 0; Max.u64 = 80; 
  l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -381,9 +381,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 4549; SumSQ.u64 = 4549; Count.u64 = 4549; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 4503; SumSQ.u64 = 4503; Count.u64 = 4503; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 497; SumSQ.u64 = 497; Count.u64 = 497; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -614,11 +614,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c0.l2cache.PutM_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.PutE_recv : Accumulator : Sum.u64 = 1025; SumSQ.u64 = 1025; Count.u64 = 1025; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l2cache.Inv_recv : Accumulator : Sum.u64 = 5336; SumSQ.u64 = 5336; Count.u64 = 5336; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.Inv_recv : Accumulator : Sum.u64 = 2700; SumSQ.u64 = 2700; Count.u64 = 2700; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2682; SumSQ.u64 = 2682; Count.u64 = 2682; Min.u64 = 1; Max.u64 = 1; 
- c0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1874; SumSQ.u64 = 1874; Count.u64 = 1874; Min.u64 = 1; Max.u64 = 1; 
+ c0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 808; SumSQ.u64 = 808; Count.u64 = 808; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
  c0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -762,9 +762,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 4499; SumSQ.u64 = 4499; Count.u64 = 4499; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 527; SumSQ.u64 = 527; Count.u64 = 527; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 4476; SumSQ.u64 = 4476; Count.u64 = 4476; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 524; SumSQ.u64 = 524; Count.u64 = 524; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -995,11 +995,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c1.l2cache.PutM_recv : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.PutE_recv : Accumulator : Sum.u64 = 1029; SumSQ.u64 = 1029; Count.u64 = 1029; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l2cache.Inv_recv : Accumulator : Sum.u64 = 5302; SumSQ.u64 = 5302; Count.u64 = 5302; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.Inv_recv : Accumulator : Sum.u64 = 2681; SumSQ.u64 = 2681; Count.u64 = 2681; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2833; SumSQ.u64 = 2833; Count.u64 = 2833; Min.u64 = 1; Max.u64 = 1; 
- c1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1971; SumSQ.u64 = 1971; Count.u64 = 1971; Min.u64 = 1; Max.u64 = 1; 
+ c1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 862; SumSQ.u64 = 862; Count.u64 = 862; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; 
  c1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1143,9 +1143,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 4532; SumSQ.u64 = 4532; Count.u64 = 4532; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 491; SumSQ.u64 = 491; Count.u64 = 491; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 4510; SumSQ.u64 = 4510; Count.u64 = 4510; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 490; SumSQ.u64 = 490; Count.u64 = 490; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1376,11 +1376,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c2.l2cache.PutM_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.PutE_recv : Accumulator : Sum.u64 = 1065; SumSQ.u64 = 1065; Count.u64 = 1065; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l2cache.Inv_recv : Accumulator : Sum.u64 = 5285; SumSQ.u64 = 5285; Count.u64 = 5285; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.Inv_recv : Accumulator : Sum.u64 = 2669; SumSQ.u64 = 2669; Count.u64 = 2669; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2768; SumSQ.u64 = 2768; Count.u64 = 2768; Min.u64 = 1; Max.u64 = 1; 
- c2.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1947; SumSQ.u64 = 1947; Count.u64 = 1947; Min.u64 = 1; Max.u64 = 1; 
+ c2.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 821; SumSQ.u64 = 821; Count.u64 = 821; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
  c2.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1524,9 +1524,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 4541; SumSQ.u64 = 4541; Count.u64 = 4541; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 487; SumSQ.u64 = 487; Count.u64 = 487; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 4515; SumSQ.u64 = 4515; Count.u64 = 4515; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1757,11 +1757,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c3.l2cache.PutM_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.PutE_recv : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l2cache.Inv_recv : Accumulator : Sum.u64 = 5329; SumSQ.u64 = 5329; Count.u64 = 5329; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.Inv_recv : Accumulator : Sum.u64 = 2693; SumSQ.u64 = 2693; Count.u64 = 2693; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2759; SumSQ.u64 = 2759; Count.u64 = 2759; Min.u64 = 1; Max.u64 = 1; 
- c3.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1950; SumSQ.u64 = 1950; Count.u64 = 1950; Min.u64 = 1; Max.u64 = 1; 
+ c3.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 809; SumSQ.u64 = 809; Count.u64 = 809; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
  c3.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1905,9 +1905,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c4.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; 
- c4.l1cache.GetS_recv : Accumulator : Sum.u64 = 4533; SumSQ.u64 = 4533; Count.u64 = 4533; Min.u64 = 1; Max.u64 = 1; 
- c4.l1cache.GetX_recv : Accumulator : Sum.u64 = 498; SumSQ.u64 = 498; Count.u64 = 498; Min.u64 = 1; Max.u64 = 1; 
+ c4.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c4.l1cache.GetS_recv : Accumulator : Sum.u64 = 4506; SumSQ.u64 = 4506; Count.u64 = 4506; Min.u64 = 1; Max.u64 = 1; 
+ c4.l1cache.GetX_recv : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 494; Min.u64 = 1; Max.u64 = 1; 
  c4.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2138,11 +2138,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c4.l2cache.PutM_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.PutE_recv : Accumulator : Sum.u64 = 1060; SumSQ.u64 = 1060; Count.u64 = 1060; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l2cache.Inv_recv : Accumulator : Sum.u64 = 5383; SumSQ.u64 = 5383; Count.u64 = 5383; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.Inv_recv : Accumulator : Sum.u64 = 2722; SumSQ.u64 = 2722; Count.u64 = 2722; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2676; SumSQ.u64 = 2676; Count.u64 = 2676; Min.u64 = 1; Max.u64 = 1; 
- c4.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1911; SumSQ.u64 = 1911; Count.u64 = 1911; Min.u64 = 1; Max.u64 = 1; 
+ c4.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 765; SumSQ.u64 = 765; Count.u64 = 765; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; 
  c4.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2286,9 +2286,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c5.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- c5.l1cache.GetS_recv : Accumulator : Sum.u64 = 4567; SumSQ.u64 = 4567; Count.u64 = 4567; Min.u64 = 1; Max.u64 = 1; 
- c5.l1cache.GetX_recv : Accumulator : Sum.u64 = 462; SumSQ.u64 = 462; Count.u64 = 462; Min.u64 = 1; Max.u64 = 1; 
+ c5.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c5.l1cache.GetS_recv : Accumulator : Sum.u64 = 4542; SumSQ.u64 = 4542; Count.u64 = 4542; Min.u64 = 1; Max.u64 = 1; 
+ c5.l1cache.GetX_recv : Accumulator : Sum.u64 = 458; SumSQ.u64 = 458; Count.u64 = 458; Min.u64 = 1; Max.u64 = 1; 
  c5.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2519,11 +2519,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c5.l2cache.PutM_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.PutE_recv : Accumulator : Sum.u64 = 1046; SumSQ.u64 = 1046; Count.u64 = 1046; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l2cache.Inv_recv : Accumulator : Sum.u64 = 5455; SumSQ.u64 = 5455; Count.u64 = 5455; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.Inv_recv : Accumulator : Sum.u64 = 2753; SumSQ.u64 = 2753; Count.u64 = 2753; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2642; SumSQ.u64 = 2642; Count.u64 = 2642; Min.u64 = 1; Max.u64 = 1; 
- c5.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1859; SumSQ.u64 = 1859; Count.u64 = 1859; Min.u64 = 1; Max.u64 = 1; 
+ c5.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 783; SumSQ.u64 = 783; Count.u64 = 783; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; 
  c5.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2667,9 +2667,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c6.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
- c6.l1cache.GetS_recv : Accumulator : Sum.u64 = 4514; SumSQ.u64 = 4514; Count.u64 = 4514; Min.u64 = 1; Max.u64 = 1; 
- c6.l1cache.GetX_recv : Accumulator : Sum.u64 = 513; SumSQ.u64 = 513; Count.u64 = 513; Min.u64 = 1; Max.u64 = 1; 
+ c6.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c6.l1cache.GetS_recv : Accumulator : Sum.u64 = 4490; SumSQ.u64 = 4490; Count.u64 = 4490; Min.u64 = 1; Max.u64 = 1; 
+ c6.l1cache.GetX_recv : Accumulator : Sum.u64 = 510; SumSQ.u64 = 510; Count.u64 = 510; Min.u64 = 1; Max.u64 = 1; 
  c6.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2900,11 +2900,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c6.l2cache.PutM_recv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.PutE_recv : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l2cache.Inv_recv : Accumulator : Sum.u64 = 5317; SumSQ.u64 = 5317; Count.u64 = 5317; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.Inv_recv : Accumulator : Sum.u64 = 2688; SumSQ.u64 = 2688; Count.u64 = 2688; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2725; SumSQ.u64 = 2725; Count.u64 = 2725; Min.u64 = 1; Max.u64 = 1; 
- c6.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 176; SumSQ.u64 = 176; Count.u64 = 176; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1934; SumSQ.u64 = 1934; Count.u64 = 1934; Min.u64 = 1; Max.u64 = 1; 
+ c6.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 791; SumSQ.u64 = 791; Count.u64 = 791; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; 
  c6.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3048,9 +3048,9 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c7.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
- c7.l1cache.GetS_recv : Accumulator : Sum.u64 = 4534; SumSQ.u64 = 4534; Count.u64 = 4534; Min.u64 = 1; Max.u64 = 1; 
- c7.l1cache.GetX_recv : Accumulator : Sum.u64 = 486; SumSQ.u64 = 486; Count.u64 = 486; Min.u64 = 1; Max.u64 = 1; 
+ c7.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c7.l1cache.GetS_recv : Accumulator : Sum.u64 = 4517; SumSQ.u64 = 4517; Count.u64 = 4517; Min.u64 = 1; Max.u64 = 1; 
+ c7.l1cache.GetX_recv : Accumulator : Sum.u64 = 483; SumSQ.u64 = 483; Count.u64 = 483; Min.u64 = 1; Max.u64 = 1; 
  c7.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3281,11 +3281,11 @@ TrivialCPU cpu5 Finished after 5000 issued reads, 5000 returned (15968248 clocks
  c7.l2cache.PutM_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.PutE_recv : Accumulator : Sum.u64 = 1078; SumSQ.u64 = 1078; Count.u64 = 1078; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l2cache.Inv_recv : Accumulator : Sum.u64 = 5329; SumSQ.u64 = 5329; Count.u64 = 5329; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.Inv_recv : Accumulator : Sum.u64 = 2686; SumSQ.u64 = 2686; Count.u64 = 2686; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2719; SumSQ.u64 = 2719; Count.u64 = 2719; Min.u64 = 1; Max.u64 = 1; 
- c7.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1920; SumSQ.u64 = 1920; Count.u64 = 1920; Min.u64 = 1; Max.u64 = 1; 
+ c7.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 799; SumSQ.u64 = 799; Count.u64 = 799; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; 
  c7.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendVaultSim.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendVaultSim.out
index a813a5f4a..131f808d4 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendVaultSim.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendVaultSim.out
@@ -468,7 +468,7 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (471522 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1784; SumSQ.u64 = 1784; Count.u64 = 1784; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1783; SumSQ.u64 = 1783; Count.u64 = 1783; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 211; SumSQ.u64 = 211; Count.u64 = 211; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -480,11 +480,11 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (471522 clocks)
  n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -619,8 +619,8 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (471522 clocks)
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 905; SumSQ.u64 = 905; Count.u64 = 905; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 904; SumSQ.u64 = 904; Count.u64 = 904; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -962,11 +962,11 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (471522 clocks)
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1146,8 +1146,8 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (471522 clocks)
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 3539; SumSQ.u64 = 3539; Count.u64 = 3539; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 403; SumSQ.u64 = 403; Count.u64 = 403; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 3514; SumSQ.u64 = 3514; Count.u64 = 3514; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 400; SumSQ.u64 = 400; Count.u64 = 400; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendVaultSim_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendVaultSim_MC.out
index 0f22b2559..abb54d4f7 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendVaultSim_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendVaultSim_MC.out
@@ -468,7 +468,7 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (471954 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1784; SumSQ.u64 = 1784; Count.u64 = 1784; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1783; SumSQ.u64 = 1783; Count.u64 = 1783; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 211; SumSQ.u64 = 211; Count.u64 = 211; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -480,11 +480,11 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (471954 clocks)
  n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -619,8 +619,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (471954 clocks)
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 905; SumSQ.u64 = 905; Count.u64 = 905; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 904; SumSQ.u64 = 904; Count.u64 = 904; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -962,11 +962,11 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (471954 clocks)
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1146,8 +1146,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (471954 clocks)
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 3539; SumSQ.u64 = 3539; Count.u64 = 3539; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 403; SumSQ.u64 = 403; Count.u64 = 403; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 3514; SumSQ.u64 = 3514; Count.u64 = 3514; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 400; SumSQ.u64 = 400; Count.u64 = 400; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_1.out
index 7df8e37a6..59c8fcef3 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_1.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_1.out
@@ -158,13 +158,13 @@
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 32511; SumSQ.u64 = 32511; Count.u64 = 32511; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 21977; SumSQ.u64 = 21977; Count.u64 = 21977; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetXResp_recv : Accumulator : Sum.u64 = 3001; SumSQ.u64 = 3001; Count.u64 = 3001; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetXResp_recv : Accumulator : Sum.u64 = 2502; SumSQ.u64 = 2502; Count.u64 = 2502; Min.u64 = 1; Max.u64 = 1; 
  l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_3.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_3.out
index 43dfc84f1..23e5cf01b 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_3.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_3.out
@@ -298,13 +298,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l1cache_0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l1cache_0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_0.GetS_recv : Accumulator : Sum.u64 = 1211; SumSQ.u64 = 1211; Count.u64 = 1211; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_0.GetS_recv : Accumulator : Sum.u64 = 768; SumSQ.u64 = 768; Count.u64 = 768; Min.u64 = 1; Max.u64 = 1; 
  l1cache_0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
- l1cache_0.GetXResp_recv : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_0.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l1cache_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -721,13 +721,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l1cache_1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 468; SumSQ.u64 = 468; Count.u64 = 468; Min.u64 = 1; Max.u64 = 1; 
  l1cache_1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_1.GetS_recv : Accumulator : Sum.u64 = 1922; SumSQ.u64 = 1922; Count.u64 = 1922; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_1.GetS_recv : Accumulator : Sum.u64 = 1137; SumSQ.u64 = 1137; Count.u64 = 1137; Min.u64 = 1; Max.u64 = 1; 
  l1cache_1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
- l1cache_1.GetXResp_recv : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_1.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l1cache_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -972,7 +972,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l2cache_1.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_1.FetchXResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l2cache_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1144,7 +1144,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l1cache_2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l1cache_2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_2.GetS_recv : Accumulator : Sum.u64 = 1190; SumSQ.u64 = 1190; Count.u64 = 1190; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_2.GetS_recv : Accumulator : Sum.u64 = 761; SumSQ.u64 = 761; Count.u64 = 761; Min.u64 = 1; Max.u64 = 1; 
  l1cache_2.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1379,7 +1379,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l2cache_2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_2.GetS_recv : Accumulator : Sum.u64 = 560; SumSQ.u64 = 560; Count.u64 = 560; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_2.GetS_recv : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; 
  l2cache_2.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1395,7 +1395,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_2.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l2cache_2.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_2.FetchXResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l2cache_2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1567,13 +1567,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l1cache_3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 468; SumSQ.u64 = 468; Count.u64 = 468; Min.u64 = 1; Max.u64 = 1; 
  l1cache_3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_3.GetS_recv : Accumulator : Sum.u64 = 1933; SumSQ.u64 = 1933; Count.u64 = 1933; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_3.GetS_recv : Accumulator : Sum.u64 = 1141; SumSQ.u64 = 1141; Count.u64 = 1141; Min.u64 = 1; Max.u64 = 1; 
  l1cache_3.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
- l1cache_3.GetXResp_recv : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_3.GetXResp_recv : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; 
  l1cache_3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1818,7 +1818,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_3.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_3.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_3.FetchInvX_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l2cache_3.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_3.FetchXResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l2cache_3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1990,7 +1990,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l1cache_4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l1cache_4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_4.GetS_recv : Accumulator : Sum.u64 = 1196; SumSQ.u64 = 1196; Count.u64 = 1196; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_4.GetS_recv : Accumulator : Sum.u64 = 758; SumSQ.u64 = 758; Count.u64 = 758; Min.u64 = 1; Max.u64 = 1; 
  l1cache_4.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2241,7 +2241,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_4.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_4.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_4.FetchInvX_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l2cache_4.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_4.FetchXResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l2cache_4.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2413,13 +2413,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l1cache_5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 468; SumSQ.u64 = 468; Count.u64 = 468; Min.u64 = 1; Max.u64 = 1; 
  l1cache_5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_5.GetS_recv : Accumulator : Sum.u64 = 1909; SumSQ.u64 = 1909; Count.u64 = 1909; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_5.GetS_recv : Accumulator : Sum.u64 = 1128; SumSQ.u64 = 1128; Count.u64 = 1128; Min.u64 = 1; Max.u64 = 1; 
  l1cache_5.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.GetSResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
- l1cache_5.GetXResp_recv : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_5.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l1cache_5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2664,7 +2664,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_5.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_5.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_5.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l2cache_5.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_5.FetchXResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l2cache_5.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2836,7 +2836,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l1cache_6.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l1cache_6.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_6.GetS_recv : Accumulator : Sum.u64 = 1196; SumSQ.u64 = 1196; Count.u64 = 1196; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_6.GetS_recv : Accumulator : Sum.u64 = 762; SumSQ.u64 = 762; Count.u64 = 762; Min.u64 = 1; Max.u64 = 1; 
  l1cache_6.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3071,7 +3071,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_6.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l2cache_6.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_6.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_6.GetS_recv : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_6.GetS_recv : Accumulator : Sum.u64 = 555; SumSQ.u64 = 555; Count.u64 = 555; Min.u64 = 1; Max.u64 = 1; 
  l2cache_6.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_6.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3087,7 +3087,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_6.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_6.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_6.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_6.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_6.FetchInvX_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l2cache_6.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_6.FetchXResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l2cache_6.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3259,13 +3259,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l1cache_7.CustomResp_uncache_recv : Accumulator : Sum.u64 = 468; SumSQ.u64 = 468; Count.u64 = 468; Min.u64 = 1; Max.u64 = 1; 
  l1cache_7.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_7.GetS_recv : Accumulator : Sum.u64 = 1934; SumSQ.u64 = 1934; Count.u64 = 1934; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_7.GetS_recv : Accumulator : Sum.u64 = 1140; SumSQ.u64 = 1140; Count.u64 = 1140; Min.u64 = 1; Max.u64 = 1; 
  l1cache_7.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
- l1cache_7.GetXResp_recv : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_7.GetXResp_recv : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; 
  l1cache_7.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3510,7 +3510,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_7.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_7.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_7.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_7.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_7.FetchInvX_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l2cache_7.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_7.FetchXResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l2cache_7.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3682,7 +3682,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l1cache_8.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l1cache_8.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_8.GetS_recv : Accumulator : Sum.u64 = 1204; SumSQ.u64 = 1204; Count.u64 = 1204; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_8.GetS_recv : Accumulator : Sum.u64 = 764; SumSQ.u64 = 764; Count.u64 = 764; Min.u64 = 1; Max.u64 = 1; 
  l1cache_8.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3917,7 +3917,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_8.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l2cache_8.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_8.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_8.GetS_recv : Accumulator : Sum.u64 = 560; SumSQ.u64 = 560; Count.u64 = 560; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_8.GetS_recv : Accumulator : Sum.u64 = 559; SumSQ.u64 = 559; Count.u64 = 559; Min.u64 = 1; Max.u64 = 1; 
  l2cache_8.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_8.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_8.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3933,7 +3933,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_8.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_8.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_8.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_8.FetchInvX_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_8.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l2cache_8.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_8.FetchXResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l2cache_8.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -4105,13 +4105,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l1cache_9.CustomResp_uncache_recv : Accumulator : Sum.u64 = 468; SumSQ.u64 = 468; Count.u64 = 468; Min.u64 = 1; Max.u64 = 1; 
  l1cache_9.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_9.GetS_recv : Accumulator : Sum.u64 = 1927; SumSQ.u64 = 1927; Count.u64 = 1927; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_9.GetS_recv : Accumulator : Sum.u64 = 1139; SumSQ.u64 = 1139; Count.u64 = 1139; Min.u64 = 1; Max.u64 = 1; 
  l1cache_9.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.GetSResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
- l1cache_9.GetXResp_recv : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_9.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l1cache_9.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -4356,7 +4356,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_9.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_9.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_9.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_9.FetchInvX_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_9.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l2cache_9.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_9.FetchXResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l2cache_9.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -4528,7 +4528,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l1cache_10.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l1cache_10.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_10.GetS_recv : Accumulator : Sum.u64 = 1211; SumSQ.u64 = 1211; Count.u64 = 1211; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_10.GetS_recv : Accumulator : Sum.u64 = 767; SumSQ.u64 = 767; Count.u64 = 767; Min.u64 = 1; Max.u64 = 1; 
  l1cache_10.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -4763,7 +4763,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_10.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l2cache_10.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_10.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_10.GetS_recv : Accumulator : Sum.u64 = 552; SumSQ.u64 = 552; Count.u64 = 552; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_10.GetS_recv : Accumulator : Sum.u64 = 550; SumSQ.u64 = 550; Count.u64 = 550; Min.u64 = 1; Max.u64 = 1; 
  l2cache_10.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_10.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_10.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -4779,7 +4779,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_10.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_10.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_10.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_10.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_10.FetchInvX_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l2cache_10.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_10.FetchXResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l2cache_10.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -4951,13 +4951,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l1cache_11.CustomResp_uncache_recv : Accumulator : Sum.u64 = 468; SumSQ.u64 = 468; Count.u64 = 468; Min.u64 = 1; Max.u64 = 1; 
  l1cache_11.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_11.GetS_recv : Accumulator : Sum.u64 = 1918; SumSQ.u64 = 1918; Count.u64 = 1918; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_11.GetS_recv : Accumulator : Sum.u64 = 1139; SumSQ.u64 = 1139; Count.u64 = 1139; Min.u64 = 1; Max.u64 = 1; 
  l1cache_11.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.GetSResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
- l1cache_11.GetXResp_recv : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_11.GetXResp_recv : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; 
  l1cache_11.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -5201,8 +5201,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_11.Inv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l2cache_11.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_11.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_11.FetchInv_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
- l2cache_11.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_11.FetchInv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_11.FetchInvX_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l2cache_11.FetchResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l2cache_11.FetchXResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l2cache_11.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -5374,13 +5374,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l1cache_12.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l1cache_12.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_12.GetS_recv : Accumulator : Sum.u64 = 1202; SumSQ.u64 = 1202; Count.u64 = 1202; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_12.GetS_recv : Accumulator : Sum.u64 = 761; SumSQ.u64 = 761; Count.u64 = 761; Min.u64 = 1; Max.u64 = 1; 
  l1cache_12.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.GetSResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
- l1cache_12.GetXResp_recv : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_12.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l1cache_12.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -5609,7 +5609,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_12.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l2cache_12.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_12.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_12.GetS_recv : Accumulator : Sum.u64 = 562; SumSQ.u64 = 562; Count.u64 = 562; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_12.GetS_recv : Accumulator : Sum.u64 = 561; SumSQ.u64 = 561; Count.u64 = 561; Min.u64 = 1; Max.u64 = 1; 
  l2cache_12.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_12.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_12.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -5625,7 +5625,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_12.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_12.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_12.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_12.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_12.FetchInvX_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l2cache_12.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_12.FetchXResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l2cache_12.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -5797,13 +5797,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l1cache_13.CustomResp_uncache_recv : Accumulator : Sum.u64 = 468; SumSQ.u64 = 468; Count.u64 = 468; Min.u64 = 1; Max.u64 = 1; 
  l1cache_13.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_13.GetS_recv : Accumulator : Sum.u64 = 1905; SumSQ.u64 = 1905; Count.u64 = 1905; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_13.GetS_recv : Accumulator : Sum.u64 = 1135; SumSQ.u64 = 1135; Count.u64 = 1135; Min.u64 = 1; Max.u64 = 1; 
  l1cache_13.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
- l1cache_13.GetXResp_recv : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_13.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l1cache_13.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -6048,7 +6048,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_13.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_13.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_13.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_13.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_13.FetchInvX_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l2cache_13.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_13.FetchXResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l2cache_13.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -6220,7 +6220,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l1cache_14.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l1cache_14.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_14.GetS_recv : Accumulator : Sum.u64 = 1196; SumSQ.u64 = 1196; Count.u64 = 1196; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_14.GetS_recv : Accumulator : Sum.u64 = 761; SumSQ.u64 = 761; Count.u64 = 761; Min.u64 = 1; Max.u64 = 1; 
  l1cache_14.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -6455,7 +6455,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_14.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
  l2cache_14.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_14.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_14.GetS_recv : Accumulator : Sum.u64 = 567; SumSQ.u64 = 567; Count.u64 = 567; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_14.GetS_recv : Accumulator : Sum.u64 = 565; SumSQ.u64 = 565; Count.u64 = 565; Min.u64 = 1; Max.u64 = 1; 
  l2cache_14.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_14.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_14.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -6471,7 +6471,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_14.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_14.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_14.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_14.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_14.FetchInvX_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l2cache_14.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_14.FetchXResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l2cache_14.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -6643,13 +6643,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l1cache_15.CustomResp_uncache_recv : Accumulator : Sum.u64 = 468; SumSQ.u64 = 468; Count.u64 = 468; Min.u64 = 1; Max.u64 = 1; 
  l1cache_15.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_15.GetS_recv : Accumulator : Sum.u64 = 1900; SumSQ.u64 = 1900; Count.u64 = 1900; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_15.GetS_recv : Accumulator : Sum.u64 = 1124; SumSQ.u64 = 1124; Count.u64 = 1124; Min.u64 = 1; Max.u64 = 1; 
  l1cache_15.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_15.GetXResp_recv : Accumulator : Sum.u64 = 327; SumSQ.u64 = 327; Count.u64 = 327; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_15.GetXResp_recv : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; 
  l1cache_15.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -6894,7 +6894,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l2cache_15.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_15.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_15.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_15.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_15.FetchInvX_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l2cache_15.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_15.FetchXResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l2cache_15.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_DistributedCaches.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_DistributedCaches.out
index d6470796c..31c771a23 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_DistributedCaches.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_DistributedCaches.out
@@ -254,9 +254,9 @@ TrivialCPU cpu7 Finished after 1200 issued reads, 1200 returned (92033 clocks)
  l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetS_recv : Accumulator : Sum.u64 = 1237; SumSQ.u64 = 1237; Count.u64 = 1237; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetX_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache0.GetS_recv : Accumulator : Sum.u64 = 1077; SumSQ.u64 = 1077; Count.u64 = 1077; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetX_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -412,9 +412,9 @@ TrivialCPU cpu7 Finished after 1200 issued reads, 1200 returned (92033 clocks)
  l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetS_recv : Accumulator : Sum.u64 = 1264; SumSQ.u64 = 1264; Count.u64 = 1264; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetX_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache1.GetS_recv : Accumulator : Sum.u64 = 1085; SumSQ.u64 = 1085; Count.u64 = 1085; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetX_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -570,9 +570,9 @@ TrivialCPU cpu7 Finished after 1200 issued reads, 1200 returned (92033 clocks)
  l1cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetS_recv : Accumulator : Sum.u64 = 1212; SumSQ.u64 = 1212; Count.u64 = 1212; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetX_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache2.GetS_recv : Accumulator : Sum.u64 = 1081; SumSQ.u64 = 1081; Count.u64 = 1081; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetX_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -728,9 +728,9 @@ TrivialCPU cpu7 Finished after 1200 issued reads, 1200 returned (92033 clocks)
  l1cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetS_recv : Accumulator : Sum.u64 = 1249; SumSQ.u64 = 1249; Count.u64 = 1249; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetX_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache3.GetS_recv : Accumulator : Sum.u64 = 1088; SumSQ.u64 = 1088; Count.u64 = 1088; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetX_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -886,9 +886,9 @@ TrivialCPU cpu7 Finished after 1200 issued reads, 1200 returned (92033 clocks)
  l1cache4.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetS_recv : Accumulator : Sum.u64 = 1216; SumSQ.u64 = 1216; Count.u64 = 1216; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetX_recv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache4.GetS_recv : Accumulator : Sum.u64 = 1079; SumSQ.u64 = 1079; Count.u64 = 1079; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetX_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1044,9 +1044,9 @@ TrivialCPU cpu7 Finished after 1200 issued reads, 1200 returned (92033 clocks)
  l1cache5.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetS_recv : Accumulator : Sum.u64 = 1204; SumSQ.u64 = 1204; Count.u64 = 1204; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetX_recv : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache5.GetS_recv : Accumulator : Sum.u64 = 1050; SumSQ.u64 = 1050; Count.u64 = 1050; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetX_recv : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1202,9 +1202,9 @@ TrivialCPU cpu7 Finished after 1200 issued reads, 1200 returned (92033 clocks)
  l1cache6.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache6.NULLCMD_recv : Accumulator : Sum.u64 = 181; SumSQ.u64 = 181; Count.u64 = 181; Min.u64 = 1; Max.u64 = 1; 
- l1cache6.GetS_recv : Accumulator : Sum.u64 = 1246; SumSQ.u64 = 1246; Count.u64 = 1246; Min.u64 = 1; Max.u64 = 1; 
- l1cache6.GetX_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; 
+ l1cache6.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache6.GetS_recv : Accumulator : Sum.u64 = 1077; SumSQ.u64 = 1077; Count.u64 = 1077; Min.u64 = 1; Max.u64 = 1; 
+ l1cache6.GetX_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
  l1cache6.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1360,9 +1360,9 @@ TrivialCPU cpu7 Finished after 1200 issued reads, 1200 returned (92033 clocks)
  l1cache7.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache7.NULLCMD_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; 
- l1cache7.GetS_recv : Accumulator : Sum.u64 = 1199; SumSQ.u64 = 1199; Count.u64 = 1199; Min.u64 = 1; Max.u64 = 1; 
- l1cache7.GetX_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; 
+ l1cache7.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache7.GetS_recv : Accumulator : Sum.u64 = 1075; SumSQ.u64 = 1075; Count.u64 = 1075; Min.u64 = 1; Max.u64 = 1; 
+ l1cache7.GetX_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l1cache7.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1585,7 +1585,7 @@ TrivialCPU cpu7 Finished after 1200 issued reads, 1200 returned (92033 clocks)
  l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.GetS_recv : Accumulator : Sum.u64 = 2075; SumSQ.u64 = 2075; Count.u64 = 2075; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.GetS_recv : Accumulator : Sum.u64 = 2074; SumSQ.u64 = 2074; Count.u64 = 2074; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.GetX_recv : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_DistributedCaches_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_DistributedCaches_MC.out
index d85dae0ef..3068c5815 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_DistributedCaches_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_DistributedCaches_MC.out
@@ -11,8 +11,8 @@ TrivialCPU: Test Completed Successfuly
 TrivialCPU: Test Completed Successfuly
 TrivialCPU: Test Completed Successfuly
 TrivialCPU cpu6 Finished after 1200 issued reads, 1200 returned (91576 clocks)
-TrivialCPU cpu7 Finished after 1200 issued reads, 1200 returned (92033 clocks)
 TrivialCPU cpu5 Finished after 1200 issued reads, 1200 returned (90963 clocks)
+TrivialCPU cpu7 Finished after 1200 issued reads, 1200 returned (92033 clocks)
 TrivialCPU cpu0 Finished after 1200 issued reads, 1200 returned (90955 clocks)
 TrivialCPU cpu1 Finished after 1200 issued reads, 1200 returned (92334 clocks)
 TrivialCPU cpu2 Finished after 1200 issued reads, 1200 returned (91728 clocks)
@@ -254,9 +254,9 @@ TrivialCPU cpu4 Finished after 1200 issued reads, 1200 returned (90086 clocks)
  l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetS_recv : Accumulator : Sum.u64 = 1237; SumSQ.u64 = 1237; Count.u64 = 1237; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetX_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache0.GetS_recv : Accumulator : Sum.u64 = 1077; SumSQ.u64 = 1077; Count.u64 = 1077; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetX_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -412,9 +412,9 @@ TrivialCPU cpu4 Finished after 1200 issued reads, 1200 returned (90086 clocks)
  l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetS_recv : Accumulator : Sum.u64 = 1264; SumSQ.u64 = 1264; Count.u64 = 1264; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetX_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache1.GetS_recv : Accumulator : Sum.u64 = 1085; SumSQ.u64 = 1085; Count.u64 = 1085; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetX_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -570,9 +570,9 @@ TrivialCPU cpu4 Finished after 1200 issued reads, 1200 returned (90086 clocks)
  l1cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetS_recv : Accumulator : Sum.u64 = 1212; SumSQ.u64 = 1212; Count.u64 = 1212; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetX_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache2.GetS_recv : Accumulator : Sum.u64 = 1081; SumSQ.u64 = 1081; Count.u64 = 1081; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetX_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -728,9 +728,9 @@ TrivialCPU cpu4 Finished after 1200 issued reads, 1200 returned (90086 clocks)
  l1cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetS_recv : Accumulator : Sum.u64 = 1249; SumSQ.u64 = 1249; Count.u64 = 1249; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetX_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache3.GetS_recv : Accumulator : Sum.u64 = 1088; SumSQ.u64 = 1088; Count.u64 = 1088; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetX_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -886,9 +886,9 @@ TrivialCPU cpu4 Finished after 1200 issued reads, 1200 returned (90086 clocks)
  l1cache4.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetS_recv : Accumulator : Sum.u64 = 1216; SumSQ.u64 = 1216; Count.u64 = 1216; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetX_recv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache4.GetS_recv : Accumulator : Sum.u64 = 1079; SumSQ.u64 = 1079; Count.u64 = 1079; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetX_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1044,9 +1044,9 @@ TrivialCPU cpu4 Finished after 1200 issued reads, 1200 returned (90086 clocks)
  l1cache5.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetS_recv : Accumulator : Sum.u64 = 1204; SumSQ.u64 = 1204; Count.u64 = 1204; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetX_recv : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache5.GetS_recv : Accumulator : Sum.u64 = 1050; SumSQ.u64 = 1050; Count.u64 = 1050; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetX_recv : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1202,9 +1202,9 @@ TrivialCPU cpu4 Finished after 1200 issued reads, 1200 returned (90086 clocks)
  l1cache6.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache6.NULLCMD_recv : Accumulator : Sum.u64 = 181; SumSQ.u64 = 181; Count.u64 = 181; Min.u64 = 1; Max.u64 = 1; 
- l1cache6.GetS_recv : Accumulator : Sum.u64 = 1246; SumSQ.u64 = 1246; Count.u64 = 1246; Min.u64 = 1; Max.u64 = 1; 
- l1cache6.GetX_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; 
+ l1cache6.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache6.GetS_recv : Accumulator : Sum.u64 = 1077; SumSQ.u64 = 1077; Count.u64 = 1077; Min.u64 = 1; Max.u64 = 1; 
+ l1cache6.GetX_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
  l1cache6.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1360,9 +1360,9 @@ TrivialCPU cpu4 Finished after 1200 issued reads, 1200 returned (90086 clocks)
  l1cache7.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache7.NULLCMD_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; 
- l1cache7.GetS_recv : Accumulator : Sum.u64 = 1199; SumSQ.u64 = 1199; Count.u64 = 1199; Min.u64 = 1; Max.u64 = 1; 
- l1cache7.GetX_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; 
+ l1cache7.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache7.GetS_recv : Accumulator : Sum.u64 = 1075; SumSQ.u64 = 1075; Count.u64 = 1075; Min.u64 = 1; Max.u64 = 1; 
+ l1cache7.GetX_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l1cache7.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1585,7 +1585,7 @@ TrivialCPU cpu4 Finished after 1200 issued reads, 1200 returned (90086 clocks)
  l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.GetS_recv : Accumulator : Sum.u64 = 2075; SumSQ.u64 = 2075; Count.u64 = 2075; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.GetS_recv : Accumulator : Sum.u64 = 2074; SumSQ.u64 = 2074; Count.u64 = 2074; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.GetX_recv : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes.out
index 09da63959..c16e42749 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes.out
@@ -212,21 +212,21 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
  l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetS_recv : Accumulator : Sum.u64 = 1474; SumSQ.u64 = 1474; Count.u64 = 1474; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetX_recv : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache0.GetS_recv : Accumulator : Sum.u64 = 1197; SumSQ.u64 = 1197; Count.u64 = 1197; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetX_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 673; SumSQ.u64 = 673; Count.u64 = 673; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 672; SumSQ.u64 = 672; Count.u64 = 672; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 200; SumSQ.u64 = 200; Count.u64 = 200; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.Inv_recv : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.Inv_recv : Accumulator : Sum.u64 = 309; SumSQ.u64 = 309; Count.u64 = 309; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.NACK_recv : Accumulator : Sum.u64 = 1310; SumSQ.u64 = 1310; Count.u64 = 1310; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.NACK_recv : Accumulator : Sum.u64 = 1309; SumSQ.u64 = 1309; Count.u64 = 1309; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 202610; SumSQ.u64 = 2996758; Count.u64 = 15616; Min.u64 = 0; Max.u64 = 16; 
  l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -449,11 +449,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
  l2cache0.PutM_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.PutE_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.Inv_recv : Accumulator : Sum.u64 = 826; SumSQ.u64 = 826; Count.u64 = 826; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.Inv_recv : Accumulator : Sum.u64 = 517; SumSQ.u64 = 517; Count.u64 = 517; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
- l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 283; SumSQ.u64 = 283; Count.u64 = 283; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.NACK_recv : Accumulator : Sum.u64 = 310; SumSQ.u64 = 310; Count.u64 = 310; Min.u64 = 1; Max.u64 = 1; 
@@ -597,21 +597,21 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
  l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetS_recv : Accumulator : Sum.u64 = 1487; SumSQ.u64 = 1487; Count.u64 = 1487; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetX_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache1.GetS_recv : Accumulator : Sum.u64 = 1219; SumSQ.u64 = 1219; Count.u64 = 1219; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetX_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 673; SumSQ.u64 = 673; Count.u64 = 673; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 670; SumSQ.u64 = 670; Count.u64 = 670; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.Inv_recv : Accumulator : Sum.u64 = 329; SumSQ.u64 = 329; Count.u64 = 329; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.NACK_recv : Accumulator : Sum.u64 = 1276; SumSQ.u64 = 1276; Count.u64 = 1276; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.NACK_recv : Accumulator : Sum.u64 = 1274; SumSQ.u64 = 1274; Count.u64 = 1274; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 208046; SumSQ.u64 = 3089574; Count.u64 = 15616; Min.u64 = 0; Max.u64 = 16; 
  l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -834,11 +834,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
  l2cache1.PutM_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.PutE_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.Inv_recv : Accumulator : Sum.u64 = 853; SumSQ.u64 = 853; Count.u64 = 853; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.Inv_recv : Accumulator : Sum.u64 = 524; SumSQ.u64 = 524; Count.u64 = 524; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
- l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 269; SumSQ.u64 = 269; Count.u64 = 269; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.NACK_recv : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; 
@@ -982,21 +982,21 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
  l1cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetS_recv : Accumulator : Sum.u64 = 1507; SumSQ.u64 = 1507; Count.u64 = 1507; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetX_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache2.GetS_recv : Accumulator : Sum.u64 = 1215; SumSQ.u64 = 1215; Count.u64 = 1215; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetX_recv : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 644; SumSQ.u64 = 644; Count.u64 = 644; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 642; SumSQ.u64 = 642; Count.u64 = 642; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.Inv_recv : Accumulator : Sum.u64 = 329; SumSQ.u64 = 329; Count.u64 = 329; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.Inv_recv : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.NACK_recv : Accumulator : Sum.u64 = 1177; SumSQ.u64 = 1177; Count.u64 = 1177; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.NACK_recv : Accumulator : Sum.u64 = 1175; SumSQ.u64 = 1175; Count.u64 = 1175; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.MSHR_occupancy : Accumulator : Sum.u64 = 197449; SumSQ.u64 = 2920681; Count.u64 = 15616; Min.u64 = 0; Max.u64 = 16; 
  l1cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1208,9 +1208,9 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
  l2cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.GetS_recv : Accumulator : Sum.u64 = 1411; SumSQ.u64 = 1411; Count.u64 = 1411; Min.u64 = 1; Max.u64 = 1; 
- l2cache2.GetX_recv : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.GetX_recv : Accumulator : Sum.u64 = 333; SumSQ.u64 = 333; Count.u64 = 333; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 209; SumSQ.u64 = 209; Count.u64 = 209; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 208; SumSQ.u64 = 208; Count.u64 = 208; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetSResp_recv : Accumulator : Sum.u64 = 458; SumSQ.u64 = 458; Count.u64 = 458; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetXResp_recv : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; 
@@ -1219,11 +1219,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
  l2cache2.PutM_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.PutE_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.Inv_recv : Accumulator : Sum.u64 = 856; SumSQ.u64 = 856; Count.u64 = 856; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.Inv_recv : Accumulator : Sum.u64 = 533; SumSQ.u64 = 533; Count.u64 = 533; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; 
- l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 268; SumSQ.u64 = 268; Count.u64 = 268; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.NACK_recv : Accumulator : Sum.u64 = 270; SumSQ.u64 = 270; Count.u64 = 270; Min.u64 = 1; Max.u64 = 1; 
@@ -1367,21 +1367,21 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
  l1cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetS_recv : Accumulator : Sum.u64 = 1463; SumSQ.u64 = 1463; Count.u64 = 1463; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetX_recv : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache3.GetS_recv : Accumulator : Sum.u64 = 1192; SumSQ.u64 = 1192; Count.u64 = 1192; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetX_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 638; SumSQ.u64 = 638; Count.u64 = 638; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 637; SumSQ.u64 = 637; Count.u64 = 637; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 181; SumSQ.u64 = 181; Count.u64 = 181; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.Inv_recv : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.Inv_recv : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.NACK_recv : Accumulator : Sum.u64 = 1410; SumSQ.u64 = 1410; Count.u64 = 1410; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.NACK_recv : Accumulator : Sum.u64 = 1407; SumSQ.u64 = 1407; Count.u64 = 1407; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 207769; SumSQ.u64 = 3085825; Count.u64 = 15616; Min.u64 = 0; Max.u64 = 16; 
  l1cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1604,11 +1604,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
  l2cache3.PutM_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.PutE_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.Inv_recv : Accumulator : Sum.u64 = 831; SumSQ.u64 = 831; Count.u64 = 831; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.Inv_recv : Accumulator : Sum.u64 = 512; SumSQ.u64 = 512; Count.u64 = 512; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; 
- l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 265; SumSQ.u64 = 265; Count.u64 = 265; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.NACK_recv : Accumulator : Sum.u64 = 273; SumSQ.u64 = 273; Count.u64 = 273; Min.u64 = 1; Max.u64 = 1; 
@@ -1752,21 +1752,21 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
  l1cache4.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetS_recv : Accumulator : Sum.u64 = 1456; SumSQ.u64 = 1456; Count.u64 = 1456; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetX_recv : Accumulator : Sum.u64 = 177; SumSQ.u64 = 177; Count.u64 = 177; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache4.GetS_recv : Accumulator : Sum.u64 = 1211; SumSQ.u64 = 1211; Count.u64 = 1211; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetX_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 641; SumSQ.u64 = 641; Count.u64 = 641; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 218; SumSQ.u64 = 218; Count.u64 = 218; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.Inv_recv : Accumulator : Sum.u64 = 294; SumSQ.u64 = 294; Count.u64 = 294; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.Inv_recv : Accumulator : Sum.u64 = 292; SumSQ.u64 = 292; Count.u64 = 292; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FetchInv_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.FetchInvX_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.NACK_recv : Accumulator : Sum.u64 = 1047; SumSQ.u64 = 1047; Count.u64 = 1047; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.NACK_recv : Accumulator : Sum.u64 = 1046; SumSQ.u64 = 1046; Count.u64 = 1046; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.MSHR_occupancy : Accumulator : Sum.u64 = 230547; SumSQ.u64 = 3450777; Count.u64 = 15616; Min.u64 = 0; Max.u64 = 16; 
  l1cache4.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1989,11 +1989,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
  l2cache4.PutM_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.PutE_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.Inv_recv : Accumulator : Sum.u64 = 746; SumSQ.u64 = 746; Count.u64 = 746; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.Inv_recv : Accumulator : Sum.u64 = 454; SumSQ.u64 = 454; Count.u64 = 454; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; 
- l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 206; SumSQ.u64 = 206; Count.u64 = 206; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FetchResp_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FetchXResp_recv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.NACK_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
@@ -2137,21 +2137,21 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
  l1cache5.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetS_recv : Accumulator : Sum.u64 = 1439; SumSQ.u64 = 1439; Count.u64 = 1439; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetX_recv : Accumulator : Sum.u64 = 189; SumSQ.u64 = 189; Count.u64 = 189; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache5.GetS_recv : Accumulator : Sum.u64 = 1193; SumSQ.u64 = 1193; Count.u64 = 1193; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetX_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 645; SumSQ.u64 = 645; Count.u64 = 645; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 642; SumSQ.u64 = 642; Count.u64 = 642; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.Inv_recv : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.FetchInv_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.FetchInv_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.FetchInvX_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.NACK_recv : Accumulator : Sum.u64 = 1150; SumSQ.u64 = 1150; Count.u64 = 1150; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.NACK_recv : Accumulator : Sum.u64 = 1149; SumSQ.u64 = 1149; Count.u64 = 1149; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.MSHR_occupancy : Accumulator : Sum.u64 = 218174; SumSQ.u64 = 3245130; Count.u64 = 15616; Min.u64 = 0; Max.u64 = 16; 
  l1cache5.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2374,11 +2374,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
  l2cache5.PutM_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.PutE_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.Inv_recv : Accumulator : Sum.u64 = 796; SumSQ.u64 = 796; Count.u64 = 796; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.Inv_recv : Accumulator : Sum.u64 = 490; SumSQ.u64 = 490; Count.u64 = 490; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; 
- l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 285; SumSQ.u64 = 285; Count.u64 = 285; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.FetchResp_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.FetchXResp_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.NACK_recv : Accumulator : Sum.u64 = 260; SumSQ.u64 = 260; Count.u64 = 260; Min.u64 = 1; Max.u64 = 1; 
@@ -2593,14 +2593,14 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
  l3cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.GetS_recv : Accumulator : Sum.u64 = 1743; SumSQ.u64 = 1743; Count.u64 = 1743; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.GetX_recv : Accumulator : Sum.u64 = 702; SumSQ.u64 = 702; Count.u64 = 702; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetS_recv : Accumulator : Sum.u64 = 1261; SumSQ.u64 = 1261; Count.u64 = 1261; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetX_recv : Accumulator : Sum.u64 = 425; SumSQ.u64 = 425; Count.u64 = 425; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 394; SumSQ.u64 = 394; Count.u64 = 394; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 237; SumSQ.u64 = 237; Count.u64 = 237; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.GetXResp_recv : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 304; SumSQ.u64 = 304; Count.u64 = 304; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetXResp_recv : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 303; SumSQ.u64 = 303; Count.u64 = 303; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2611,9 +2611,9 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
  l3cache0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 281; SumSQ.u64 = 281; Count.u64 = 281; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.NACK_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.AckInv_recv : Accumulator : Sum.u64 = 1007; SumSQ.u64 = 1007; Count.u64 = 1007; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 280; SumSQ.u64 = 280; Count.u64 = 280; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.NACK_recv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.AckInv_recv : Accumulator : Sum.u64 = 945; SumSQ.u64 = 945; Count.u64 = 945; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 43750; SumSQ.u64 = 246784; Count.u64 = 9120; Min.u64 = 0; Max.u64 = 7; 
  l3cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2824,13 +2824,13 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
  l3cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.GetS_recv : Accumulator : Sum.u64 = 1767; SumSQ.u64 = 1767; Count.u64 = 1767; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.GetX_recv : Accumulator : Sum.u64 = 714; SumSQ.u64 = 714; Count.u64 = 714; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetS_recv : Accumulator : Sum.u64 = 1292; SumSQ.u64 = 1292; Count.u64 = 1292; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetX_recv : Accumulator : Sum.u64 = 408; SumSQ.u64 = 408; Count.u64 = 408; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 281; SumSQ.u64 = 281; Count.u64 = 281; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 344; SumSQ.u64 = 344; Count.u64 = 344; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 203; SumSQ.u64 = 203; Count.u64 = 203; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 220; SumSQ.u64 = 220; Count.u64 = 220; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 297; SumSQ.u64 = 297; Count.u64 = 297; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2842,9 +2842,9 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
  l3cache1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.NACK_recv : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.AckInv_recv : Accumulator : Sum.u64 = 1046; SumSQ.u64 = 1046; Count.u64 = 1046; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 279; SumSQ.u64 = 279; Count.u64 = 279; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.NACK_recv : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.AckInv_recv : Accumulator : Sum.u64 = 983; SumSQ.u64 = 983; Count.u64 = 983; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 42670; SumSQ.u64 = 238562; Count.u64 = 9120; Min.u64 = 0; Max.u64 = 7; 
  l3cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3055,14 +3055,14 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
  l3cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache2.GetS_recv : Accumulator : Sum.u64 = 1771; SumSQ.u64 = 1771; Count.u64 = 1771; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.GetX_recv : Accumulator : Sum.u64 = 686; SumSQ.u64 = 686; Count.u64 = 686; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetS_recv : Accumulator : Sum.u64 = 1302; SumSQ.u64 = 1302; Count.u64 = 1302; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetX_recv : Accumulator : Sum.u64 = 398; SumSQ.u64 = 398; Count.u64 = 398; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 403; SumSQ.u64 = 403; Count.u64 = 403; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 231; SumSQ.u64 = 231; Count.u64 = 231; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.GetXResp_recv : Accumulator : Sum.u64 = 237; SumSQ.u64 = 237; Count.u64 = 237; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 301; SumSQ.u64 = 301; Count.u64 = 301; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 300; SumSQ.u64 = 300; Count.u64 = 300; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3073,9 +3073,9 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
  l3cache2.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FetchResp_recv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 271; SumSQ.u64 = 271; Count.u64 = 271; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.NACK_recv : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.AckInv_recv : Accumulator : Sum.u64 = 1043; SumSQ.u64 = 1043; Count.u64 = 1043; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 270; SumSQ.u64 = 270; Count.u64 = 270; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.NACK_recv : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.AckInv_recv : Accumulator : Sum.u64 = 973; SumSQ.u64 = 973; Count.u64 = 973; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.MSHR_occupancy : Accumulator : Sum.u64 = 44130; SumSQ.u64 = 247506; Count.u64 = 9120; Min.u64 = 0; Max.u64 = 7; 
  l3cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes_2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes_2.out
index fcf77d91c..57e547a0d 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes_2.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes_2.out
@@ -224,21 +224,21 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetS_recv : Accumulator : Sum.u64 = 1393; SumSQ.u64 = 1393; Count.u64 = 1393; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetX_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache0.GetS_recv : Accumulator : Sum.u64 = 1136; SumSQ.u64 = 1136; Count.u64 = 1136; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetX_recv : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 604; SumSQ.u64 = 604; Count.u64 = 604; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 603; SumSQ.u64 = 603; Count.u64 = 603; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.Inv_recv : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.Inv_recv : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.NACK_recv : Accumulator : Sum.u64 = 1170; SumSQ.u64 = 1170; Count.u64 = 1170; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.NACK_recv : Accumulator : Sum.u64 = 1169; SumSQ.u64 = 1169; Count.u64 = 1169; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 270982; SumSQ.u64 = 3961956; Count.u64 = 20115; Min.u64 = 0; Max.u64 = 16; 
  l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -461,11 +461,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l2cache0.PutM_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.PutE_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.Inv_recv : Accumulator : Sum.u64 = 804; SumSQ.u64 = 804; Count.u64 = 804; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.Inv_recv : Accumulator : Sum.u64 = 484; SumSQ.u64 = 484; Count.u64 = 484; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; 
- l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.NACK_recv : Accumulator : Sum.u64 = 401; SumSQ.u64 = 401; Count.u64 = 401; Min.u64 = 1; Max.u64 = 1; 
@@ -609,21 +609,21 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetS_recv : Accumulator : Sum.u64 = 1355; SumSQ.u64 = 1355; Count.u64 = 1355; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetX_recv : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache1.GetS_recv : Accumulator : Sum.u64 = 1129; SumSQ.u64 = 1129; Count.u64 = 1129; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetX_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 617; SumSQ.u64 = 617; Count.u64 = 617; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.Inv_recv : Accumulator : Sum.u64 = 303; SumSQ.u64 = 303; Count.u64 = 303; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.Inv_recv : Accumulator : Sum.u64 = 300; SumSQ.u64 = 300; Count.u64 = 300; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.NACK_recv : Accumulator : Sum.u64 = 1225; SumSQ.u64 = 1225; Count.u64 = 1225; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.NACK_recv : Accumulator : Sum.u64 = 1224; SumSQ.u64 = 1224; Count.u64 = 1224; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 276704; SumSQ.u64 = 4021574; Count.u64 = 20115; Min.u64 = 0; Max.u64 = 16; 
  l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -835,7 +835,7 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.GetS_recv : Accumulator : Sum.u64 = 1421; SumSQ.u64 = 1421; Count.u64 = 1421; Min.u64 = 1; Max.u64 = 1; 
- l2cache1.GetX_recv : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.GetX_recv : Accumulator : Sum.u64 = 305; SumSQ.u64 = 305; Count.u64 = 305; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 212; SumSQ.u64 = 212; Count.u64 = 212; Min.u64 = 1; Max.u64 = 1; 
@@ -846,11 +846,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l2cache1.PutM_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.PutE_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.Inv_recv : Accumulator : Sum.u64 = 774; SumSQ.u64 = 774; Count.u64 = 774; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.Inv_recv : Accumulator : Sum.u64 = 474; SumSQ.u64 = 474; Count.u64 = 474; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; 
- l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.NACK_recv : Accumulator : Sum.u64 = 421; SumSQ.u64 = 421; Count.u64 = 421; Min.u64 = 1; Max.u64 = 1; 
@@ -994,21 +994,21 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l1cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetS_recv : Accumulator : Sum.u64 = 1381; SumSQ.u64 = 1381; Count.u64 = 1381; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetX_recv : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache2.GetS_recv : Accumulator : Sum.u64 = 1130; SumSQ.u64 = 1130; Count.u64 = 1130; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetX_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 608; SumSQ.u64 = 608; Count.u64 = 608; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.Inv_recv : Accumulator : Sum.u64 = 292; SumSQ.u64 = 292; Count.u64 = 292; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.Inv_recv : Accumulator : Sum.u64 = 290; SumSQ.u64 = 290; Count.u64 = 290; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.NACK_recv : Accumulator : Sum.u64 = 1004; SumSQ.u64 = 1004; Count.u64 = 1004; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.NACK_recv : Accumulator : Sum.u64 = 1003; SumSQ.u64 = 1003; Count.u64 = 1003; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.MSHR_occupancy : Accumulator : Sum.u64 = 268114; SumSQ.u64 = 3841900; Count.u64 = 20115; Min.u64 = 0; Max.u64 = 16; 
  l1cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1222,7 +1222,7 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l2cache2.GetS_recv : Accumulator : Sum.u64 = 1289; SumSQ.u64 = 1289; Count.u64 = 1289; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetX_recv : Accumulator : Sum.u64 = 267; SumSQ.u64 = 267; Count.u64 = 267; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetSResp_recv : Accumulator : Sum.u64 = 437; SumSQ.u64 = 437; Count.u64 = 437; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetXResp_recv : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; 
@@ -1231,11 +1231,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l2cache2.PutM_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.PutE_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.Inv_recv : Accumulator : Sum.u64 = 758; SumSQ.u64 = 758; Count.u64 = 758; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.Inv_recv : Accumulator : Sum.u64 = 468; SumSQ.u64 = 468; Count.u64 = 468; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; 
- l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 133; SumSQ.u64 = 133; Count.u64 = 133; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.NACK_recv : Accumulator : Sum.u64 = 404; SumSQ.u64 = 404; Count.u64 = 404; Min.u64 = 1; Max.u64 = 1; 
@@ -1379,21 +1379,21 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l1cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetS_recv : Accumulator : Sum.u64 = 1330; SumSQ.u64 = 1330; Count.u64 = 1330; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetX_recv : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache3.GetS_recv : Accumulator : Sum.u64 = 1114; SumSQ.u64 = 1114; Count.u64 = 1114; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetX_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 603; SumSQ.u64 = 603; Count.u64 = 603; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 183; SumSQ.u64 = 183; Count.u64 = 183; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 182; SumSQ.u64 = 182; Count.u64 = 182; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.Inv_recv : Accumulator : Sum.u64 = 307; SumSQ.u64 = 307; Count.u64 = 307; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.Inv_recv : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.NACK_recv : Accumulator : Sum.u64 = 1237; SumSQ.u64 = 1237; Count.u64 = 1237; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.NACK_recv : Accumulator : Sum.u64 = 1236; SumSQ.u64 = 1236; Count.u64 = 1236; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 292714; SumSQ.u64 = 4304740; Count.u64 = 20115; Min.u64 = 0; Max.u64 = 16; 
  l1cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1616,11 +1616,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l2cache3.PutM_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.PutE_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.Inv_recv : Accumulator : Sum.u64 = 745; SumSQ.u64 = 745; Count.u64 = 745; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.Inv_recv : Accumulator : Sum.u64 = 439; SumSQ.u64 = 439; Count.u64 = 439; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
- l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.NACK_recv : Accumulator : Sum.u64 = 388; SumSQ.u64 = 388; Count.u64 = 388; Min.u64 = 1; Max.u64 = 1; 
@@ -1764,16 +1764,16 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l1cache4.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetS_recv : Accumulator : Sum.u64 = 1377; SumSQ.u64 = 1377; Count.u64 = 1377; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetX_recv : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache4.GetS_recv : Accumulator : Sum.u64 = 1130; SumSQ.u64 = 1130; Count.u64 = 1130; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetX_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 573; SumSQ.u64 = 573; Count.u64 = 573; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 572; SumSQ.u64 = 572; Count.u64 = 572; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 180; SumSQ.u64 = 180; Count.u64 = 180; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.Inv_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.Inv_recv : Accumulator : Sum.u64 = 310; SumSQ.u64 = 310; Count.u64 = 310; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FetchInv_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; 
@@ -1990,10 +1990,10 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l2cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.GetS_recv : Accumulator : Sum.u64 = 1411; SumSQ.u64 = 1411; Count.u64 = 1411; Min.u64 = 1; Max.u64 = 1; 
- l2cache4.GetX_recv : Accumulator : Sum.u64 = 266; SumSQ.u64 = 266; Count.u64 = 266; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.GetX_recv : Accumulator : Sum.u64 = 265; SumSQ.u64 = 265; Count.u64 = 265; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.FlushLine_recv : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; 
- l2cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 228; SumSQ.u64 = 228; Count.u64 = 228; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 227; SumSQ.u64 = 227; Count.u64 = 227; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.GetSResp_recv : Accumulator : Sum.u64 = 435; SumSQ.u64 = 435; Count.u64 = 435; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.GetXResp_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; 
@@ -2001,11 +2001,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l2cache4.PutM_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.PutE_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.Inv_recv : Accumulator : Sum.u64 = 770; SumSQ.u64 = 770; Count.u64 = 770; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.Inv_recv : Accumulator : Sum.u64 = 461; SumSQ.u64 = 461; Count.u64 = 461; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; 
- l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FetchResp_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FetchXResp_recv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.NACK_recv : Accumulator : Sum.u64 = 393; SumSQ.u64 = 393; Count.u64 = 393; Min.u64 = 1; Max.u64 = 1; 
@@ -2149,13 +2149,13 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l1cache5.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetS_recv : Accumulator : Sum.u64 = 1378; SumSQ.u64 = 1378; Count.u64 = 1378; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetX_recv : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache5.GetS_recv : Accumulator : Sum.u64 = 1149; SumSQ.u64 = 1149; Count.u64 = 1149; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetX_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 613; SumSQ.u64 = 613; Count.u64 = 613; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 612; SumSQ.u64 = 612; Count.u64 = 612; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.Inv_recv : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; 
@@ -2163,7 +2163,7 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l1cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FetchInv_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.FetchInvX_recv : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.NACK_recv : Accumulator : Sum.u64 = 1533; SumSQ.u64 = 1533; Count.u64 = 1533; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.NACK_recv : Accumulator : Sum.u64 = 1532; SumSQ.u64 = 1532; Count.u64 = 1532; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.MSHR_occupancy : Accumulator : Sum.u64 = 265126; SumSQ.u64 = 3865796; Count.u64 = 20115; Min.u64 = 0; Max.u64 = 16; 
  l1cache5.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2377,7 +2377,7 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l2cache5.GetS_recv : Accumulator : Sum.u64 = 1587; SumSQ.u64 = 1587; Count.u64 = 1587; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.GetX_recv : Accumulator : Sum.u64 = 386; SumSQ.u64 = 386; Count.u64 = 386; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.FlushLine_recv : Accumulator : Sum.u64 = 235; SumSQ.u64 = 235; Count.u64 = 235; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.FlushLine_recv : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 233; SumSQ.u64 = 233; Count.u64 = 233; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.GetSResp_recv : Accumulator : Sum.u64 = 445; SumSQ.u64 = 445; Count.u64 = 445; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.GetXResp_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; 
@@ -2386,11 +2386,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l2cache5.PutM_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.PutE_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.Inv_recv : Accumulator : Sum.u64 = 802; SumSQ.u64 = 802; Count.u64 = 802; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.Inv_recv : Accumulator : Sum.u64 = 481; SumSQ.u64 = 481; Count.u64 = 481; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; 
- l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 230; SumSQ.u64 = 230; Count.u64 = 230; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.FetchResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.FetchXResp_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.NACK_recv : Accumulator : Sum.u64 = 396; SumSQ.u64 = 396; Count.u64 = 396; Min.u64 = 1; Max.u64 = 1; 
@@ -2605,11 +2605,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l3cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.GetS_recv : Accumulator : Sum.u64 = 1662; SumSQ.u64 = 1662; Count.u64 = 1662; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.GetX_recv : Accumulator : Sum.u64 = 620; SumSQ.u64 = 620; Count.u64 = 620; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetS_recv : Accumulator : Sum.u64 = 1233; SumSQ.u64 = 1233; Count.u64 = 1233; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetX_recv : Accumulator : Sum.u64 = 367; SumSQ.u64 = 367; Count.u64 = 367; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 392; SumSQ.u64 = 392; Count.u64 = 392; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 208; SumSQ.u64 = 208; Count.u64 = 208; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.GetXResp_recv : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 278; SumSQ.u64 = 278; Count.u64 = 278; Min.u64 = 1; Max.u64 = 1; 
@@ -2622,10 +2622,10 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l3cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.NACK_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.AckInv_recv : Accumulator : Sum.u64 = 954; SumSQ.u64 = 954; Count.u64 = 954; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 236; SumSQ.u64 = 236; Count.u64 = 236; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.NACK_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.AckInv_recv : Accumulator : Sum.u64 = 890; SumSQ.u64 = 890; Count.u64 = 890; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 54567; SumSQ.u64 = 303933; Count.u64 = 11747; Min.u64 = 0; Max.u64 = 7; 
  l3cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2836,13 +2836,13 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l3cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.GetS_recv : Accumulator : Sum.u64 = 2071; SumSQ.u64 = 2071; Count.u64 = 2071; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.GetX_recv : Accumulator : Sum.u64 = 829; SumSQ.u64 = 829; Count.u64 = 829; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetS_recv : Accumulator : Sum.u64 = 1594; SumSQ.u64 = 1594; Count.u64 = 1594; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetX_recv : Accumulator : Sum.u64 = 539; SumSQ.u64 = 539; Count.u64 = 539; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 360; SumSQ.u64 = 360; Count.u64 = 360; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 488; SumSQ.u64 = 488; Count.u64 = 488; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 309; SumSQ.u64 = 309; Count.u64 = 309; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 225; SumSQ.u64 = 225; Count.u64 = 225; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2856,7 +2856,7 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 75; SumSQ.u64 = 75; Count.u64 = 75; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.NACK_recv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.AckInv_recv : Accumulator : Sum.u64 = 965; SumSQ.u64 = 965; Count.u64 = 965; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.AckInv_recv : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 65374; SumSQ.u64 = 399656; Count.u64 = 11747; Min.u64 = 0; Max.u64 = 7; 
  l3cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3067,14 +3067,14 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l3cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache2.GetS_recv : Accumulator : Sum.u64 = 1721; SumSQ.u64 = 1721; Count.u64 = 1721; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.GetX_recv : Accumulator : Sum.u64 = 627; SumSQ.u64 = 627; Count.u64 = 627; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetS_recv : Accumulator : Sum.u64 = 1273; SumSQ.u64 = 1273; Count.u64 = 1273; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetX_recv : Accumulator : Sum.u64 = 377; SumSQ.u64 = 377; Count.u64 = 377; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 274; SumSQ.u64 = 274; Count.u64 = 274; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 231; SumSQ.u64 = 231; Count.u64 = 231; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache2.GetXResp_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 300; SumSQ.u64 = 300; Count.u64 = 300; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetXResp_recv : Accumulator : Sum.u64 = 204; SumSQ.u64 = 204; Count.u64 = 204; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 297; SumSQ.u64 = 297; Count.u64 = 297; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3085,9 +3085,9 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
  l3cache2.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FetchResp_recv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.NACK_recv : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.AckInv_recv : Accumulator : Sum.u64 = 969; SumSQ.u64 = 969; Count.u64 = 969; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.NACK_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.AckInv_recv : Accumulator : Sum.u64 = 900; SumSQ.u64 = 900; Count.u64 = 900; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.MSHR_occupancy : Accumulator : Sum.u64 = 59324; SumSQ.u64 = 343442; Count.u64 = 11747; Min.u64 = 0; Max.u64 = 7; 
  l3cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes_2_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes_2_MC.out
index 754bf373a..92e59a385 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes_2_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes_2_MC.out
@@ -5,17 +5,17 @@ TrivialCPU: Test Completed Successfuly
 TrivialCPU: Test Completed Successfuly
 TrivialCPU: Test Completed Successfuly
 TrivialCPU cpu3 Finished after 1500 issued reads, 1500 returned (20115 clocks)
-	74 Noncacheable Reads
-	9 Noncacheable Writes
 TrivialCPU cpu4 Finished after 1500 issued reads, 1500 returned (19639 clocks)
-TrivialCPU cpu0 Finished after 1500 issued reads, 1500 returned (18854 clocks)
 	84 Noncacheable Reads
 	6 Noncacheable Writes
-	75 Noncacheable Reads
-	10 Noncacheable Writes
+	74 Noncacheable Reads
+	9 Noncacheable Writes
 TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (18440 clocks)
 	72 Noncacheable Reads
 	13 Noncacheable Writes
+TrivialCPU cpu0 Finished after 1500 issued reads, 1500 returned (18854 clocks)
+	75 Noncacheable Reads
+	10 Noncacheable Writes
 TrivialCPU cpu1 Finished after 1500 issued reads, 1500 returned (19317 clocks)
 	82 Noncacheable Reads
 	8 Noncacheable Writes
@@ -224,21 +224,21 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetS_recv : Accumulator : Sum.u64 = 1393; SumSQ.u64 = 1393; Count.u64 = 1393; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetX_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache0.GetS_recv : Accumulator : Sum.u64 = 1136; SumSQ.u64 = 1136; Count.u64 = 1136; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetX_recv : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 604; SumSQ.u64 = 604; Count.u64 = 604; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 603; SumSQ.u64 = 603; Count.u64 = 603; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.Inv_recv : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.Inv_recv : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.NACK_recv : Accumulator : Sum.u64 = 1170; SumSQ.u64 = 1170; Count.u64 = 1170; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.NACK_recv : Accumulator : Sum.u64 = 1169; SumSQ.u64 = 1169; Count.u64 = 1169; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 270982; SumSQ.u64 = 3961956; Count.u64 = 20115; Min.u64 = 0; Max.u64 = 16; 
  l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -461,11 +461,11 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l2cache0.PutM_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.PutE_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.Inv_recv : Accumulator : Sum.u64 = 804; SumSQ.u64 = 804; Count.u64 = 804; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.Inv_recv : Accumulator : Sum.u64 = 484; SumSQ.u64 = 484; Count.u64 = 484; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; 
- l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.NACK_recv : Accumulator : Sum.u64 = 401; SumSQ.u64 = 401; Count.u64 = 401; Min.u64 = 1; Max.u64 = 1; 
@@ -609,21 +609,21 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetS_recv : Accumulator : Sum.u64 = 1355; SumSQ.u64 = 1355; Count.u64 = 1355; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetX_recv : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache1.GetS_recv : Accumulator : Sum.u64 = 1129; SumSQ.u64 = 1129; Count.u64 = 1129; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetX_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 617; SumSQ.u64 = 617; Count.u64 = 617; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.Inv_recv : Accumulator : Sum.u64 = 303; SumSQ.u64 = 303; Count.u64 = 303; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.Inv_recv : Accumulator : Sum.u64 = 300; SumSQ.u64 = 300; Count.u64 = 300; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.NACK_recv : Accumulator : Sum.u64 = 1225; SumSQ.u64 = 1225; Count.u64 = 1225; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.NACK_recv : Accumulator : Sum.u64 = 1224; SumSQ.u64 = 1224; Count.u64 = 1224; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 276704; SumSQ.u64 = 4021574; Count.u64 = 20115; Min.u64 = 0; Max.u64 = 16; 
  l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -835,7 +835,7 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.GetS_recv : Accumulator : Sum.u64 = 1421; SumSQ.u64 = 1421; Count.u64 = 1421; Min.u64 = 1; Max.u64 = 1; 
- l2cache1.GetX_recv : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.GetX_recv : Accumulator : Sum.u64 = 305; SumSQ.u64 = 305; Count.u64 = 305; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 212; SumSQ.u64 = 212; Count.u64 = 212; Min.u64 = 1; Max.u64 = 1; 
@@ -846,11 +846,11 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l2cache1.PutM_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.PutE_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.Inv_recv : Accumulator : Sum.u64 = 774; SumSQ.u64 = 774; Count.u64 = 774; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.Inv_recv : Accumulator : Sum.u64 = 474; SumSQ.u64 = 474; Count.u64 = 474; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; 
- l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.NACK_recv : Accumulator : Sum.u64 = 421; SumSQ.u64 = 421; Count.u64 = 421; Min.u64 = 1; Max.u64 = 1; 
@@ -994,21 +994,21 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l1cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetS_recv : Accumulator : Sum.u64 = 1381; SumSQ.u64 = 1381; Count.u64 = 1381; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetX_recv : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache2.GetS_recv : Accumulator : Sum.u64 = 1130; SumSQ.u64 = 1130; Count.u64 = 1130; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetX_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 608; SumSQ.u64 = 608; Count.u64 = 608; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.Inv_recv : Accumulator : Sum.u64 = 292; SumSQ.u64 = 292; Count.u64 = 292; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.Inv_recv : Accumulator : Sum.u64 = 290; SumSQ.u64 = 290; Count.u64 = 290; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.NACK_recv : Accumulator : Sum.u64 = 1004; SumSQ.u64 = 1004; Count.u64 = 1004; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.NACK_recv : Accumulator : Sum.u64 = 1003; SumSQ.u64 = 1003; Count.u64 = 1003; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.MSHR_occupancy : Accumulator : Sum.u64 = 268114; SumSQ.u64 = 3841900; Count.u64 = 20115; Min.u64 = 0; Max.u64 = 16; 
  l1cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1222,7 +1222,7 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l2cache2.GetS_recv : Accumulator : Sum.u64 = 1289; SumSQ.u64 = 1289; Count.u64 = 1289; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetX_recv : Accumulator : Sum.u64 = 267; SumSQ.u64 = 267; Count.u64 = 267; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetSResp_recv : Accumulator : Sum.u64 = 437; SumSQ.u64 = 437; Count.u64 = 437; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetXResp_recv : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; 
@@ -1231,11 +1231,11 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l2cache2.PutM_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.PutE_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.Inv_recv : Accumulator : Sum.u64 = 758; SumSQ.u64 = 758; Count.u64 = 758; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.Inv_recv : Accumulator : Sum.u64 = 468; SumSQ.u64 = 468; Count.u64 = 468; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; 
- l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 133; SumSQ.u64 = 133; Count.u64 = 133; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.NACK_recv : Accumulator : Sum.u64 = 404; SumSQ.u64 = 404; Count.u64 = 404; Min.u64 = 1; Max.u64 = 1; 
@@ -1379,21 +1379,21 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l1cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetS_recv : Accumulator : Sum.u64 = 1330; SumSQ.u64 = 1330; Count.u64 = 1330; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetX_recv : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache3.GetS_recv : Accumulator : Sum.u64 = 1114; SumSQ.u64 = 1114; Count.u64 = 1114; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetX_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 603; SumSQ.u64 = 603; Count.u64 = 603; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 183; SumSQ.u64 = 183; Count.u64 = 183; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 182; SumSQ.u64 = 182; Count.u64 = 182; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.Inv_recv : Accumulator : Sum.u64 = 307; SumSQ.u64 = 307; Count.u64 = 307; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.Inv_recv : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.NACK_recv : Accumulator : Sum.u64 = 1237; SumSQ.u64 = 1237; Count.u64 = 1237; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.NACK_recv : Accumulator : Sum.u64 = 1236; SumSQ.u64 = 1236; Count.u64 = 1236; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 292714; SumSQ.u64 = 4304740; Count.u64 = 20115; Min.u64 = 0; Max.u64 = 16; 
  l1cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1616,11 +1616,11 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l2cache3.PutM_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.PutE_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.Inv_recv : Accumulator : Sum.u64 = 745; SumSQ.u64 = 745; Count.u64 = 745; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.Inv_recv : Accumulator : Sum.u64 = 439; SumSQ.u64 = 439; Count.u64 = 439; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
- l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.NACK_recv : Accumulator : Sum.u64 = 388; SumSQ.u64 = 388; Count.u64 = 388; Min.u64 = 1; Max.u64 = 1; 
@@ -1764,16 +1764,16 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l1cache4.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetS_recv : Accumulator : Sum.u64 = 1377; SumSQ.u64 = 1377; Count.u64 = 1377; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetX_recv : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache4.GetS_recv : Accumulator : Sum.u64 = 1130; SumSQ.u64 = 1130; Count.u64 = 1130; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetX_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 573; SumSQ.u64 = 573; Count.u64 = 573; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 572; SumSQ.u64 = 572; Count.u64 = 572; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 180; SumSQ.u64 = 180; Count.u64 = 180; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.Inv_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.Inv_recv : Accumulator : Sum.u64 = 310; SumSQ.u64 = 310; Count.u64 = 310; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FetchInv_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; 
@@ -1990,10 +1990,10 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l2cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.GetS_recv : Accumulator : Sum.u64 = 1411; SumSQ.u64 = 1411; Count.u64 = 1411; Min.u64 = 1; Max.u64 = 1; 
- l2cache4.GetX_recv : Accumulator : Sum.u64 = 266; SumSQ.u64 = 266; Count.u64 = 266; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.GetX_recv : Accumulator : Sum.u64 = 265; SumSQ.u64 = 265; Count.u64 = 265; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.FlushLine_recv : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; 
- l2cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 228; SumSQ.u64 = 228; Count.u64 = 228; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 227; SumSQ.u64 = 227; Count.u64 = 227; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.GetSResp_recv : Accumulator : Sum.u64 = 435; SumSQ.u64 = 435; Count.u64 = 435; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.GetXResp_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; 
@@ -2001,11 +2001,11 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l2cache4.PutM_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.PutE_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.Inv_recv : Accumulator : Sum.u64 = 770; SumSQ.u64 = 770; Count.u64 = 770; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.Inv_recv : Accumulator : Sum.u64 = 461; SumSQ.u64 = 461; Count.u64 = 461; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; 
- l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FetchResp_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FetchXResp_recv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.NACK_recv : Accumulator : Sum.u64 = 393; SumSQ.u64 = 393; Count.u64 = 393; Min.u64 = 1; Max.u64 = 1; 
@@ -2149,13 +2149,13 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l1cache5.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetS_recv : Accumulator : Sum.u64 = 1378; SumSQ.u64 = 1378; Count.u64 = 1378; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetX_recv : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache5.GetS_recv : Accumulator : Sum.u64 = 1149; SumSQ.u64 = 1149; Count.u64 = 1149; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetX_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 613; SumSQ.u64 = 613; Count.u64 = 613; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 612; SumSQ.u64 = 612; Count.u64 = 612; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.Inv_recv : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; 
@@ -2163,7 +2163,7 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l1cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FetchInv_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.FetchInvX_recv : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.NACK_recv : Accumulator : Sum.u64 = 1533; SumSQ.u64 = 1533; Count.u64 = 1533; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.NACK_recv : Accumulator : Sum.u64 = 1532; SumSQ.u64 = 1532; Count.u64 = 1532; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.MSHR_occupancy : Accumulator : Sum.u64 = 265126; SumSQ.u64 = 3865796; Count.u64 = 20115; Min.u64 = 0; Max.u64 = 16; 
  l1cache5.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2377,7 +2377,7 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l2cache5.GetS_recv : Accumulator : Sum.u64 = 1587; SumSQ.u64 = 1587; Count.u64 = 1587; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.GetX_recv : Accumulator : Sum.u64 = 386; SumSQ.u64 = 386; Count.u64 = 386; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.FlushLine_recv : Accumulator : Sum.u64 = 235; SumSQ.u64 = 235; Count.u64 = 235; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.FlushLine_recv : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 233; SumSQ.u64 = 233; Count.u64 = 233; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.GetSResp_recv : Accumulator : Sum.u64 = 445; SumSQ.u64 = 445; Count.u64 = 445; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.GetXResp_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; 
@@ -2386,11 +2386,11 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l2cache5.PutM_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.PutE_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.Inv_recv : Accumulator : Sum.u64 = 802; SumSQ.u64 = 802; Count.u64 = 802; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.Inv_recv : Accumulator : Sum.u64 = 481; SumSQ.u64 = 481; Count.u64 = 481; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; 
- l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 230; SumSQ.u64 = 230; Count.u64 = 230; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.FetchResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.FetchXResp_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.NACK_recv : Accumulator : Sum.u64 = 396; SumSQ.u64 = 396; Count.u64 = 396; Min.u64 = 1; Max.u64 = 1; 
@@ -2605,11 +2605,11 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l3cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.GetS_recv : Accumulator : Sum.u64 = 1662; SumSQ.u64 = 1662; Count.u64 = 1662; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.GetX_recv : Accumulator : Sum.u64 = 620; SumSQ.u64 = 620; Count.u64 = 620; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetS_recv : Accumulator : Sum.u64 = 1233; SumSQ.u64 = 1233; Count.u64 = 1233; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetX_recv : Accumulator : Sum.u64 = 367; SumSQ.u64 = 367; Count.u64 = 367; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 392; SumSQ.u64 = 392; Count.u64 = 392; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 208; SumSQ.u64 = 208; Count.u64 = 208; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.GetXResp_recv : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 278; SumSQ.u64 = 278; Count.u64 = 278; Min.u64 = 1; Max.u64 = 1; 
@@ -2622,10 +2622,10 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l3cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.NACK_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.AckInv_recv : Accumulator : Sum.u64 = 954; SumSQ.u64 = 954; Count.u64 = 954; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 236; SumSQ.u64 = 236; Count.u64 = 236; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.NACK_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.AckInv_recv : Accumulator : Sum.u64 = 890; SumSQ.u64 = 890; Count.u64 = 890; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 54567; SumSQ.u64 = 303933; Count.u64 = 11747; Min.u64 = 0; Max.u64 = 7; 
  l3cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2836,13 +2836,13 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l3cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.GetS_recv : Accumulator : Sum.u64 = 2071; SumSQ.u64 = 2071; Count.u64 = 2071; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.GetX_recv : Accumulator : Sum.u64 = 829; SumSQ.u64 = 829; Count.u64 = 829; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetS_recv : Accumulator : Sum.u64 = 1594; SumSQ.u64 = 1594; Count.u64 = 1594; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetX_recv : Accumulator : Sum.u64 = 539; SumSQ.u64 = 539; Count.u64 = 539; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 360; SumSQ.u64 = 360; Count.u64 = 360; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 488; SumSQ.u64 = 488; Count.u64 = 488; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 309; SumSQ.u64 = 309; Count.u64 = 309; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 225; SumSQ.u64 = 225; Count.u64 = 225; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2856,7 +2856,7 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 75; SumSQ.u64 = 75; Count.u64 = 75; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.NACK_recv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.AckInv_recv : Accumulator : Sum.u64 = 965; SumSQ.u64 = 965; Count.u64 = 965; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.AckInv_recv : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 65374; SumSQ.u64 = 399656; Count.u64 = 11747; Min.u64 = 0; Max.u64 = 7; 
  l3cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3067,14 +3067,14 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l3cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache2.GetS_recv : Accumulator : Sum.u64 = 1721; SumSQ.u64 = 1721; Count.u64 = 1721; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.GetX_recv : Accumulator : Sum.u64 = 627; SumSQ.u64 = 627; Count.u64 = 627; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetS_recv : Accumulator : Sum.u64 = 1273; SumSQ.u64 = 1273; Count.u64 = 1273; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetX_recv : Accumulator : Sum.u64 = 377; SumSQ.u64 = 377; Count.u64 = 377; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 274; SumSQ.u64 = 274; Count.u64 = 274; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 231; SumSQ.u64 = 231; Count.u64 = 231; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache2.GetXResp_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 300; SumSQ.u64 = 300; Count.u64 = 300; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetXResp_recv : Accumulator : Sum.u64 = 204; SumSQ.u64 = 204; Count.u64 = 204; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 297; SumSQ.u64 = 297; Count.u64 = 297; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3085,9 +3085,9 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (19648 clocks)
  l3cache2.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FetchResp_recv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.NACK_recv : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.AckInv_recv : Accumulator : Sum.u64 = 969; SumSQ.u64 = 969; Count.u64 = 969; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.NACK_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.AckInv_recv : Accumulator : Sum.u64 = 900; SumSQ.u64 = 900; Count.u64 = 900; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.MSHR_occupancy : Accumulator : Sum.u64 = 59324; SumSQ.u64 = 343442; Count.u64 = 11747; Min.u64 = 0; Max.u64 = 7; 
  l3cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes_MC.out
index 3926745c3..fb4ee21f8 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes_MC.out
@@ -5,8 +5,8 @@ TrivialCPU: Test Completed Successfuly
 TrivialCPU: Test Completed Successfuly
 TrivialCPU: Test Completed Successfuly
 TrivialCPU cpu4 Finished after 1500 issued reads, 1500 returned (15616 clocks)
-TrivialCPU cpu3 Finished after 1500 issued reads, 1500 returned (14210 clocks)
 TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (14908 clocks)
+TrivialCPU cpu3 Finished after 1500 issued reads, 1500 returned (14210 clocks)
 TrivialCPU cpu0 Finished after 1500 issued reads, 1500 returned (14023 clocks)
 TrivialCPU cpu1 Finished after 1500 issued reads, 1500 returned (14319 clocks)
 TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
@@ -212,21 +212,21 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
  l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetS_recv : Accumulator : Sum.u64 = 1474; SumSQ.u64 = 1474; Count.u64 = 1474; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetX_recv : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache0.GetS_recv : Accumulator : Sum.u64 = 1197; SumSQ.u64 = 1197; Count.u64 = 1197; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetX_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 673; SumSQ.u64 = 673; Count.u64 = 673; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 672; SumSQ.u64 = 672; Count.u64 = 672; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 200; SumSQ.u64 = 200; Count.u64 = 200; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.Inv_recv : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.Inv_recv : Accumulator : Sum.u64 = 309; SumSQ.u64 = 309; Count.u64 = 309; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.NACK_recv : Accumulator : Sum.u64 = 1310; SumSQ.u64 = 1310; Count.u64 = 1310; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.NACK_recv : Accumulator : Sum.u64 = 1309; SumSQ.u64 = 1309; Count.u64 = 1309; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 202610; SumSQ.u64 = 2996758; Count.u64 = 15616; Min.u64 = 0; Max.u64 = 16; 
  l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -449,11 +449,11 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
  l2cache0.PutM_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.PutE_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.Inv_recv : Accumulator : Sum.u64 = 826; SumSQ.u64 = 826; Count.u64 = 826; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.Inv_recv : Accumulator : Sum.u64 = 517; SumSQ.u64 = 517; Count.u64 = 517; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
- l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 283; SumSQ.u64 = 283; Count.u64 = 283; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.NACK_recv : Accumulator : Sum.u64 = 310; SumSQ.u64 = 310; Count.u64 = 310; Min.u64 = 1; Max.u64 = 1; 
@@ -597,21 +597,21 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
  l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetS_recv : Accumulator : Sum.u64 = 1487; SumSQ.u64 = 1487; Count.u64 = 1487; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetX_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache1.GetS_recv : Accumulator : Sum.u64 = 1219; SumSQ.u64 = 1219; Count.u64 = 1219; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetX_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 673; SumSQ.u64 = 673; Count.u64 = 673; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 670; SumSQ.u64 = 670; Count.u64 = 670; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.Inv_recv : Accumulator : Sum.u64 = 329; SumSQ.u64 = 329; Count.u64 = 329; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.NACK_recv : Accumulator : Sum.u64 = 1276; SumSQ.u64 = 1276; Count.u64 = 1276; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.NACK_recv : Accumulator : Sum.u64 = 1274; SumSQ.u64 = 1274; Count.u64 = 1274; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 208046; SumSQ.u64 = 3089574; Count.u64 = 15616; Min.u64 = 0; Max.u64 = 16; 
  l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -834,11 +834,11 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
  l2cache1.PutM_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.PutE_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.Inv_recv : Accumulator : Sum.u64 = 853; SumSQ.u64 = 853; Count.u64 = 853; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.Inv_recv : Accumulator : Sum.u64 = 524; SumSQ.u64 = 524; Count.u64 = 524; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
- l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 269; SumSQ.u64 = 269; Count.u64 = 269; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.NACK_recv : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; 
@@ -982,21 +982,21 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
  l1cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetS_recv : Accumulator : Sum.u64 = 1507; SumSQ.u64 = 1507; Count.u64 = 1507; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetX_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache2.GetS_recv : Accumulator : Sum.u64 = 1215; SumSQ.u64 = 1215; Count.u64 = 1215; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetX_recv : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 644; SumSQ.u64 = 644; Count.u64 = 644; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 642; SumSQ.u64 = 642; Count.u64 = 642; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.Inv_recv : Accumulator : Sum.u64 = 329; SumSQ.u64 = 329; Count.u64 = 329; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.Inv_recv : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.NACK_recv : Accumulator : Sum.u64 = 1177; SumSQ.u64 = 1177; Count.u64 = 1177; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.NACK_recv : Accumulator : Sum.u64 = 1175; SumSQ.u64 = 1175; Count.u64 = 1175; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.MSHR_occupancy : Accumulator : Sum.u64 = 197449; SumSQ.u64 = 2920681; Count.u64 = 15616; Min.u64 = 0; Max.u64 = 16; 
  l1cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1208,9 +1208,9 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
  l2cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.GetS_recv : Accumulator : Sum.u64 = 1411; SumSQ.u64 = 1411; Count.u64 = 1411; Min.u64 = 1; Max.u64 = 1; 
- l2cache2.GetX_recv : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.GetX_recv : Accumulator : Sum.u64 = 333; SumSQ.u64 = 333; Count.u64 = 333; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 209; SumSQ.u64 = 209; Count.u64 = 209; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 208; SumSQ.u64 = 208; Count.u64 = 208; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetSResp_recv : Accumulator : Sum.u64 = 458; SumSQ.u64 = 458; Count.u64 = 458; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetXResp_recv : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; 
@@ -1219,11 +1219,11 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
  l2cache2.PutM_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.PutE_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.Inv_recv : Accumulator : Sum.u64 = 856; SumSQ.u64 = 856; Count.u64 = 856; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.Inv_recv : Accumulator : Sum.u64 = 533; SumSQ.u64 = 533; Count.u64 = 533; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; 
- l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 268; SumSQ.u64 = 268; Count.u64 = 268; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.NACK_recv : Accumulator : Sum.u64 = 270; SumSQ.u64 = 270; Count.u64 = 270; Min.u64 = 1; Max.u64 = 1; 
@@ -1367,21 +1367,21 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
  l1cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetS_recv : Accumulator : Sum.u64 = 1463; SumSQ.u64 = 1463; Count.u64 = 1463; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetX_recv : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache3.GetS_recv : Accumulator : Sum.u64 = 1192; SumSQ.u64 = 1192; Count.u64 = 1192; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetX_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 638; SumSQ.u64 = 638; Count.u64 = 638; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 637; SumSQ.u64 = 637; Count.u64 = 637; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 181; SumSQ.u64 = 181; Count.u64 = 181; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.Inv_recv : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.Inv_recv : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.NACK_recv : Accumulator : Sum.u64 = 1410; SumSQ.u64 = 1410; Count.u64 = 1410; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.NACK_recv : Accumulator : Sum.u64 = 1407; SumSQ.u64 = 1407; Count.u64 = 1407; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 207769; SumSQ.u64 = 3085825; Count.u64 = 15616; Min.u64 = 0; Max.u64 = 16; 
  l1cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1604,11 +1604,11 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
  l2cache3.PutM_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.PutE_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.Inv_recv : Accumulator : Sum.u64 = 831; SumSQ.u64 = 831; Count.u64 = 831; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.Inv_recv : Accumulator : Sum.u64 = 512; SumSQ.u64 = 512; Count.u64 = 512; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; 
- l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 265; SumSQ.u64 = 265; Count.u64 = 265; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.NACK_recv : Accumulator : Sum.u64 = 273; SumSQ.u64 = 273; Count.u64 = 273; Min.u64 = 1; Max.u64 = 1; 
@@ -1752,21 +1752,21 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
  l1cache4.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetS_recv : Accumulator : Sum.u64 = 1456; SumSQ.u64 = 1456; Count.u64 = 1456; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetX_recv : Accumulator : Sum.u64 = 177; SumSQ.u64 = 177; Count.u64 = 177; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache4.GetS_recv : Accumulator : Sum.u64 = 1211; SumSQ.u64 = 1211; Count.u64 = 1211; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetX_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 641; SumSQ.u64 = 641; Count.u64 = 641; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 218; SumSQ.u64 = 218; Count.u64 = 218; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.Inv_recv : Accumulator : Sum.u64 = 294; SumSQ.u64 = 294; Count.u64 = 294; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.Inv_recv : Accumulator : Sum.u64 = 292; SumSQ.u64 = 292; Count.u64 = 292; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FetchInv_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.FetchInvX_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.NACK_recv : Accumulator : Sum.u64 = 1047; SumSQ.u64 = 1047; Count.u64 = 1047; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.NACK_recv : Accumulator : Sum.u64 = 1046; SumSQ.u64 = 1046; Count.u64 = 1046; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.MSHR_occupancy : Accumulator : Sum.u64 = 230547; SumSQ.u64 = 3450777; Count.u64 = 15616; Min.u64 = 0; Max.u64 = 16; 
  l1cache4.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1989,11 +1989,11 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
  l2cache4.PutM_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.PutE_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.Inv_recv : Accumulator : Sum.u64 = 746; SumSQ.u64 = 746; Count.u64 = 746; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.Inv_recv : Accumulator : Sum.u64 = 454; SumSQ.u64 = 454; Count.u64 = 454; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; 
- l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 206; SumSQ.u64 = 206; Count.u64 = 206; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FetchResp_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FetchXResp_recv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.NACK_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
@@ -2137,21 +2137,21 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
  l1cache5.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetS_recv : Accumulator : Sum.u64 = 1439; SumSQ.u64 = 1439; Count.u64 = 1439; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetX_recv : Accumulator : Sum.u64 = 189; SumSQ.u64 = 189; Count.u64 = 189; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache5.GetS_recv : Accumulator : Sum.u64 = 1193; SumSQ.u64 = 1193; Count.u64 = 1193; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetX_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 645; SumSQ.u64 = 645; Count.u64 = 645; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 642; SumSQ.u64 = 642; Count.u64 = 642; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.Inv_recv : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.FetchInv_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.FetchInv_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.FetchInvX_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.NACK_recv : Accumulator : Sum.u64 = 1150; SumSQ.u64 = 1150; Count.u64 = 1150; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.NACK_recv : Accumulator : Sum.u64 = 1149; SumSQ.u64 = 1149; Count.u64 = 1149; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.MSHR_occupancy : Accumulator : Sum.u64 = 218174; SumSQ.u64 = 3245130; Count.u64 = 15616; Min.u64 = 0; Max.u64 = 16; 
  l1cache5.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2374,11 +2374,11 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
  l2cache5.PutM_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.PutE_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.Inv_recv : Accumulator : Sum.u64 = 796; SumSQ.u64 = 796; Count.u64 = 796; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.Inv_recv : Accumulator : Sum.u64 = 490; SumSQ.u64 = 490; Count.u64 = 490; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; 
- l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 285; SumSQ.u64 = 285; Count.u64 = 285; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.FetchResp_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.FetchXResp_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.NACK_recv : Accumulator : Sum.u64 = 260; SumSQ.u64 = 260; Count.u64 = 260; Min.u64 = 1; Max.u64 = 1; 
@@ -2593,14 +2593,14 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
  l3cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.GetS_recv : Accumulator : Sum.u64 = 1743; SumSQ.u64 = 1743; Count.u64 = 1743; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.GetX_recv : Accumulator : Sum.u64 = 702; SumSQ.u64 = 702; Count.u64 = 702; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetS_recv : Accumulator : Sum.u64 = 1261; SumSQ.u64 = 1261; Count.u64 = 1261; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetX_recv : Accumulator : Sum.u64 = 425; SumSQ.u64 = 425; Count.u64 = 425; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 394; SumSQ.u64 = 394; Count.u64 = 394; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 237; SumSQ.u64 = 237; Count.u64 = 237; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.GetXResp_recv : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 304; SumSQ.u64 = 304; Count.u64 = 304; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetXResp_recv : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 303; SumSQ.u64 = 303; Count.u64 = 303; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2611,9 +2611,9 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
  l3cache0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 281; SumSQ.u64 = 281; Count.u64 = 281; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.NACK_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.AckInv_recv : Accumulator : Sum.u64 = 1007; SumSQ.u64 = 1007; Count.u64 = 1007; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 280; SumSQ.u64 = 280; Count.u64 = 280; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.NACK_recv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.AckInv_recv : Accumulator : Sum.u64 = 945; SumSQ.u64 = 945; Count.u64 = 945; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 43750; SumSQ.u64 = 246784; Count.u64 = 9120; Min.u64 = 0; Max.u64 = 7; 
  l3cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2824,13 +2824,13 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
  l3cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.GetS_recv : Accumulator : Sum.u64 = 1767; SumSQ.u64 = 1767; Count.u64 = 1767; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.GetX_recv : Accumulator : Sum.u64 = 714; SumSQ.u64 = 714; Count.u64 = 714; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetS_recv : Accumulator : Sum.u64 = 1292; SumSQ.u64 = 1292; Count.u64 = 1292; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetX_recv : Accumulator : Sum.u64 = 408; SumSQ.u64 = 408; Count.u64 = 408; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 281; SumSQ.u64 = 281; Count.u64 = 281; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 344; SumSQ.u64 = 344; Count.u64 = 344; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 203; SumSQ.u64 = 203; Count.u64 = 203; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 220; SumSQ.u64 = 220; Count.u64 = 220; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 297; SumSQ.u64 = 297; Count.u64 = 297; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2842,9 +2842,9 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
  l3cache1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.NACK_recv : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.AckInv_recv : Accumulator : Sum.u64 = 1046; SumSQ.u64 = 1046; Count.u64 = 1046; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 279; SumSQ.u64 = 279; Count.u64 = 279; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.NACK_recv : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.AckInv_recv : Accumulator : Sum.u64 = 983; SumSQ.u64 = 983; Count.u64 = 983; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 42670; SumSQ.u64 = 238562; Count.u64 = 9120; Min.u64 = 0; Max.u64 = 7; 
  l3cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3055,14 +3055,14 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
  l3cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache2.GetS_recv : Accumulator : Sum.u64 = 1771; SumSQ.u64 = 1771; Count.u64 = 1771; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.GetX_recv : Accumulator : Sum.u64 = 686; SumSQ.u64 = 686; Count.u64 = 686; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetS_recv : Accumulator : Sum.u64 = 1302; SumSQ.u64 = 1302; Count.u64 = 1302; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetX_recv : Accumulator : Sum.u64 = 398; SumSQ.u64 = 398; Count.u64 = 398; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 403; SumSQ.u64 = 403; Count.u64 = 403; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 231; SumSQ.u64 = 231; Count.u64 = 231; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.GetXResp_recv : Accumulator : Sum.u64 = 237; SumSQ.u64 = 237; Count.u64 = 237; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 301; SumSQ.u64 = 301; Count.u64 = 301; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 300; SumSQ.u64 = 300; Count.u64 = 300; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3073,9 +3073,9 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (13706 clocks)
  l3cache2.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FetchResp_recv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 271; SumSQ.u64 = 271; Count.u64 = 271; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.NACK_recv : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.AckInv_recv : Accumulator : Sum.u64 = 1043; SumSQ.u64 = 1043; Count.u64 = 1043; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 270; SumSQ.u64 = 270; Count.u64 = 270; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.NACK_recv : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.AckInv_recv : Accumulator : Sum.u64 = 973; SumSQ.u64 = 973; Count.u64 = 973; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.MSHR_occupancy : Accumulator : Sum.u64 = 44130; SumSQ.u64 = 247506; Count.u64 = 9120; Min.u64 = 0; Max.u64 = 7; 
  l3cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_HashXor.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_HashXor.out
index c9a1a5c5d..5741c6a93 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_HashXor.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_HashXor.out
@@ -145,9 +145,9 @@ TrivialCPU cpu3 Finished after 10000 issued reads, 10000 returned (5684338 clock
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 9036; SumSQ.u64 = 9036; Count.u64 = 9036; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 989; SumSQ.u64 = 989; Count.u64 = 989; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 9016; SumSQ.u64 = 9016; Count.u64 = 9016; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 984; SumSQ.u64 = 984; Count.u64 = 984; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -299,8 +299,8 @@ TrivialCPU cpu3 Finished after 10000 issued reads, 10000 returned (5684338 clock
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 9017; SumSQ.u64 = 9017; Count.u64 = 9017; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 9007; SumSQ.u64 = 9007; Count.u64 = 9007; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 993; SumSQ.u64 = 993; Count.u64 = 993; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -680,8 +680,8 @@ TrivialCPU cpu3 Finished after 10000 issued reads, 10000 returned (5684338 clock
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 9009; SumSQ.u64 = 9009; Count.u64 = 9009; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 8996; SumSQ.u64 = 8996; Count.u64 = 8996; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 1004; SumSQ.u64 = 1004; Count.u64 = 1004; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -834,8 +834,8 @@ TrivialCPU cpu3 Finished after 10000 issued reads, 10000 returned (5684338 clock
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 9006; SumSQ.u64 = 9006; Count.u64 = 9006; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 8990; SumSQ.u64 = 8990; Count.u64 = 8990; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 1010; SumSQ.u64 = 1010; Count.u64 = 1010; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1071,7 +1071,7 @@ TrivialCPU cpu3 Finished after 10000 issued reads, 10000 returned (5684338 clock
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1286,7 +1286,7 @@ TrivialCPU cpu3 Finished after 10000 issued reads, 10000 returned (5684338 clock
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 36012; SumSQ.u64 = 36012; Count.u64 = 36012; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 36009; SumSQ.u64 = 36009; Count.u64 = 36009; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetX_recv : Accumulator : Sum.u64 = 3991; SumSQ.u64 = 3991; Count.u64 = 3991; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_HashXor_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_HashXor_MC.out
index 637d95aaa..96a10fd3e 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_HashXor_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_HashXor_MC.out
@@ -145,9 +145,9 @@ TrivialCPU cpu0 Finished after 10000 issued reads, 10000 returned (5685346 clock
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 9036; SumSQ.u64 = 9036; Count.u64 = 9036; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 989; SumSQ.u64 = 989; Count.u64 = 989; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 9016; SumSQ.u64 = 9016; Count.u64 = 9016; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 984; SumSQ.u64 = 984; Count.u64 = 984; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -299,8 +299,8 @@ TrivialCPU cpu0 Finished after 10000 issued reads, 10000 returned (5685346 clock
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 9017; SumSQ.u64 = 9017; Count.u64 = 9017; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 9007; SumSQ.u64 = 9007; Count.u64 = 9007; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 993; SumSQ.u64 = 993; Count.u64 = 993; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -680,8 +680,8 @@ TrivialCPU cpu0 Finished after 10000 issued reads, 10000 returned (5685346 clock
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 9009; SumSQ.u64 = 9009; Count.u64 = 9009; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 8996; SumSQ.u64 = 8996; Count.u64 = 8996; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 1004; SumSQ.u64 = 1004; Count.u64 = 1004; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -834,8 +834,8 @@ TrivialCPU cpu0 Finished after 10000 issued reads, 10000 returned (5685346 clock
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 9006; SumSQ.u64 = 9006; Count.u64 = 9006; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 8990; SumSQ.u64 = 8990; Count.u64 = 8990; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 1010; SumSQ.u64 = 1010; Count.u64 = 1010; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1071,7 +1071,7 @@ TrivialCPU cpu0 Finished after 10000 issued reads, 10000 returned (5685346 clock
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1286,7 +1286,7 @@ TrivialCPU cpu0 Finished after 10000 issued reads, 10000 returned (5685346 clock
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 36012; SumSQ.u64 = 36012; Count.u64 = 36012; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 36009; SumSQ.u64 = 36009; Count.u64 = 36009; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetX_recv : Accumulator : Sum.u64 = 3991; SumSQ.u64 = 3991; Count.u64 = 3991; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Incoherent.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Incoherent.out
index ab6c4f54d..dd13554b6 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Incoherent.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Incoherent.out
@@ -83,8 +83,8 @@ TrivialCPU cpu Finished after 1000 issued reads, 1000 returned (104054 clocks)
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 912; SumSQ.u64 = 912; Count.u64 = 912; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Incoherent_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Incoherent_MC.out
index ab6c4f54d..dd13554b6 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Incoherent_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Incoherent_MC.out
@@ -83,8 +83,8 @@ TrivialCPU cpu Finished after 1000 issued reads, 1000 returned (104054 clocks)
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 912; SumSQ.u64 = 912; Count.u64 = 912; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Kingsley.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Kingsley.out
index e0bfa1185..fee9eae43 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Kingsley.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Kingsley.out
@@ -1031,8 +1031,8 @@
  l1cache_0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_0.GetS_recv : Accumulator : Sum.u64 = 280482; SumSQ.u64 = 280482; Count.u64 = 280482; Min.u64 = 1; Max.u64 = 1; 
- l1cache_0.GetX_recv : Accumulator : Sum.u64 = 161595; SumSQ.u64 = 161595; Count.u64 = 161595; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_0.GetS_recv : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_0.GetX_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1218,8 +1218,8 @@
  l1cache_1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_1.GetS_recv : Accumulator : Sum.u64 = 278933; SumSQ.u64 = 278933; Count.u64 = 278933; Min.u64 = 1; Max.u64 = 1; 
- l1cache_1.GetX_recv : Accumulator : Sum.u64 = 160175; SumSQ.u64 = 160175; Count.u64 = 160175; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_1.GetS_recv : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_1.GetX_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1677,8 +1677,8 @@
  l1cache_2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_2.GetS_recv : Accumulator : Sum.u64 = 280306; SumSQ.u64 = 280306; Count.u64 = 280306; Min.u64 = 1; Max.u64 = 1; 
- l1cache_2.GetX_recv : Accumulator : Sum.u64 = 158413; SumSQ.u64 = 158413; Count.u64 = 158413; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_2.GetS_recv : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_2.GetX_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1864,8 +1864,8 @@
  l1cache_3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_3.GetS_recv : Accumulator : Sum.u64 = 285720; SumSQ.u64 = 285720; Count.u64 = 285720; Min.u64 = 1; Max.u64 = 1; 
- l1cache_3.GetX_recv : Accumulator : Sum.u64 = 164543; SumSQ.u64 = 164543; Count.u64 = 164543; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_3.GetS_recv : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_3.GetX_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2362,8 +2362,8 @@
  l1cache_4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_4.GetS_recv : Accumulator : Sum.u64 = 288642; SumSQ.u64 = 288642; Count.u64 = 288642; Min.u64 = 1; Max.u64 = 1; 
- l1cache_4.GetX_recv : Accumulator : Sum.u64 = 164772; SumSQ.u64 = 164772; Count.u64 = 164772; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_4.GetS_recv : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_4.GetX_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2549,8 +2549,8 @@
  l1cache_5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_5.GetS_recv : Accumulator : Sum.u64 = 278815; SumSQ.u64 = 278815; Count.u64 = 278815; Min.u64 = 1; Max.u64 = 1; 
- l1cache_5.GetX_recv : Accumulator : Sum.u64 = 162195; SumSQ.u64 = 162195; Count.u64 = 162195; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_5.GetS_recv : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_5.GetX_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2910,7 +2910,7 @@
  l2cache_3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_3.GetS_recv : Accumulator : Sum.u64 = 2479; SumSQ.u64 = 2479; Count.u64 = 2479; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_3.GetS_recv : Accumulator : Sum.u64 = 2478; SumSQ.u64 = 2478; Count.u64 = 2478; Min.u64 = 1; Max.u64 = 1; 
  l2cache_3.GetX_recv : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; 
  l2cache_3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3070,8 +3070,8 @@
  l1cache_6.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_6.GetS_recv : Accumulator : Sum.u64 = 280270; SumSQ.u64 = 280270; Count.u64 = 280270; Min.u64 = 1; Max.u64 = 1; 
- l1cache_6.GetX_recv : Accumulator : Sum.u64 = 162767; SumSQ.u64 = 162767; Count.u64 = 162767; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_6.GetS_recv : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_6.GetX_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_6.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3257,8 +3257,8 @@
  l1cache_7.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_7.GetS_recv : Accumulator : Sum.u64 = 277606; SumSQ.u64 = 277606; Count.u64 = 277606; Min.u64 = 1; Max.u64 = 1; 
- l1cache_7.GetX_recv : Accumulator : Sum.u64 = 161534; SumSQ.u64 = 161534; Count.u64 = 161534; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_7.GetS_recv : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_7.GetX_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_7.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3755,8 +3755,8 @@
  l1cache_8.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_8.GetS_recv : Accumulator : Sum.u64 = 283618; SumSQ.u64 = 283618; Count.u64 = 283618; Min.u64 = 1; Max.u64 = 1; 
- l1cache_8.GetX_recv : Accumulator : Sum.u64 = 157859; SumSQ.u64 = 157859; Count.u64 = 157859; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_8.GetS_recv : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_8.GetX_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_8.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3942,8 +3942,8 @@
  l1cache_9.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_9.GetS_recv : Accumulator : Sum.u64 = 288932; SumSQ.u64 = 288932; Count.u64 = 288932; Min.u64 = 1; Max.u64 = 1; 
- l1cache_9.GetX_recv : Accumulator : Sum.u64 = 164007; SumSQ.u64 = 164007; Count.u64 = 164007; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_9.GetS_recv : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_9.GetX_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_9.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -4463,8 +4463,8 @@
  l1cache_10.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_10.GetS_recv : Accumulator : Sum.u64 = 283894; SumSQ.u64 = 283894; Count.u64 = 283894; Min.u64 = 1; Max.u64 = 1; 
- l1cache_10.GetX_recv : Accumulator : Sum.u64 = 160177; SumSQ.u64 = 160177; Count.u64 = 160177; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_10.GetS_recv : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_10.GetX_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_10.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -4650,8 +4650,8 @@
  l1cache_11.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_11.GetS_recv : Accumulator : Sum.u64 = 291759; SumSQ.u64 = 291759; Count.u64 = 291759; Min.u64 = 1; Max.u64 = 1; 
- l1cache_11.GetX_recv : Accumulator : Sum.u64 = 164575; SumSQ.u64 = 164575; Count.u64 = 164575; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_11.GetS_recv : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_11.GetX_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_11.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -5148,8 +5148,8 @@
  l1cache_12.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_12.GetS_recv : Accumulator : Sum.u64 = 291143; SumSQ.u64 = 291143; Count.u64 = 291143; Min.u64 = 1; Max.u64 = 1; 
- l1cache_12.GetX_recv : Accumulator : Sum.u64 = 165649; SumSQ.u64 = 165649; Count.u64 = 165649; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_12.GetS_recv : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_12.GetX_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_12.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -5335,8 +5335,8 @@
  l1cache_13.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_13.GetS_recv : Accumulator : Sum.u64 = 286376; SumSQ.u64 = 286376; Count.u64 = 286376; Min.u64 = 1; Max.u64 = 1; 
- l1cache_13.GetX_recv : Accumulator : Sum.u64 = 163674; SumSQ.u64 = 163674; Count.u64 = 163674; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_13.GetS_recv : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_13.GetX_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_13.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -5856,8 +5856,8 @@
  l1cache_14.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_14.GetS_recv : Accumulator : Sum.u64 = 291163; SumSQ.u64 = 291163; Count.u64 = 291163; Min.u64 = 1; Max.u64 = 1; 
- l1cache_14.GetX_recv : Accumulator : Sum.u64 = 164170; SumSQ.u64 = 164170; Count.u64 = 164170; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_14.GetS_recv : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_14.GetX_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_14.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -6043,8 +6043,8 @@
  l1cache_15.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_15.GetS_recv : Accumulator : Sum.u64 = 291499; SumSQ.u64 = 291499; Count.u64 = 291499; Min.u64 = 1; Max.u64 = 1; 
- l1cache_15.GetX_recv : Accumulator : Sum.u64 = 164711; SumSQ.u64 = 164711; Count.u64 = 164711; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_15.GetS_recv : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_15.GetX_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_15.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -6541,8 +6541,8 @@
  l1cache_16.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_16.GetS_recv : Accumulator : Sum.u64 = 288407; SumSQ.u64 = 288407; Count.u64 = 288407; Min.u64 = 1; Max.u64 = 1; 
- l1cache_16.GetX_recv : Accumulator : Sum.u64 = 161734; SumSQ.u64 = 161734; Count.u64 = 161734; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_16.GetS_recv : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_16.GetX_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_16.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -6728,8 +6728,8 @@
  l1cache_17.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_17.GetS_recv : Accumulator : Sum.u64 = 300297; SumSQ.u64 = 300297; Count.u64 = 300297; Min.u64 = 1; Max.u64 = 1; 
- l1cache_17.GetX_recv : Accumulator : Sum.u64 = 173967; SumSQ.u64 = 173967; Count.u64 = 173967; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_17.GetS_recv : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_17.GetX_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_17.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_MemoryCache.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_MemoryCache.out
index dca0e597f..569584e3a 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_MemoryCache.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_MemoryCache.out
@@ -2856,11 +2856,11 @@ Model complete
  l2cache_0.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_0.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_0.Inv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_0.Inv_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
  l2cache_0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_0.FetchInv_recv : Accumulator : Sum.u64 = 478; SumSQ.u64 = 478; Count.u64 = 478; Min.u64 = 1; Max.u64 = 1; 
- l2cache_0.FetchInvX_recv : Accumulator : Sum.u64 = 455; SumSQ.u64 = 455; Count.u64 = 455; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_0.FetchInv_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_0.FetchInvX_recv : Accumulator : Sum.u64 = 213; SumSQ.u64 = 213; Count.u64 = 213; Min.u64 = 1; Max.u64 = 1; 
  l2cache_0.FetchResp_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; 
  l2cache_0.FetchXResp_recv : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; 
  l2cache_0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3004,19 +3004,19 @@ Model complete
  l1cache_0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_0.GetS_recv : Accumulator : Sum.u64 = 21079; SumSQ.u64 = 21079; Count.u64 = 21079; Min.u64 = 1; Max.u64 = 1; 
- l1cache_0.GetX_recv : Accumulator : Sum.u64 = 4691; SumSQ.u64 = 4691; Count.u64 = 4691; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_0.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_0.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_0.GetSResp_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; 
- l1cache_0.GetXResp_recv : Accumulator : Sum.u64 = 369; SumSQ.u64 = 369; Count.u64 = 369; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_0.GetSResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_0.GetXResp_recv : Accumulator : Sum.u64 = 365; SumSQ.u64 = 365; Count.u64 = 365; Min.u64 = 1; Max.u64 = 1; 
  l1cache_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l1cache_0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.FetchInv_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
- l1cache_0.FetchInvX_recv : Accumulator : Sum.u64 = 767; SumSQ.u64 = 767; Count.u64 = 767; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_0.FetchInvX_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; 
  l1cache_0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.MSHR_occupancy : Accumulator : Sum.u64 = 420962; SumSQ.u64 = 9258030; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -3174,19 +3174,19 @@ Model complete
  l1cache_1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_1.GetS_recv : Accumulator : Sum.u64 = 21326; SumSQ.u64 = 21326; Count.u64 = 21326; Min.u64 = 1; Max.u64 = 1; 
- l1cache_1.GetX_recv : Accumulator : Sum.u64 = 5477; SumSQ.u64 = 5477; Count.u64 = 5477; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_1.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_1.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_1.GetSResp_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_1.GetSResp_recv : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; 
  l1cache_1.GetXResp_recv : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; 
  l1cache_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l1cache_1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_1.FetchInv_recv : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; 
- l1cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 443; SumSQ.u64 = 443; Count.u64 = 443; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_1.FetchInv_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; 
  l1cache_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.MSHR_occupancy : Accumulator : Sum.u64 = 432583; SumSQ.u64 = 9459335; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -3534,11 +3534,11 @@ Model complete
  l2cache_1.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_1.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_1.Inv_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_1.Inv_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
  l2cache_1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_1.FetchInv_recv : Accumulator : Sum.u64 = 480; SumSQ.u64 = 480; Count.u64 = 480; Min.u64 = 1; Max.u64 = 1; 
- l2cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 540; SumSQ.u64 = 540; Count.u64 = 540; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_1.FetchInv_recv : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 254; SumSQ.u64 = 254; Count.u64 = 254; Min.u64 = 1; Max.u64 = 1; 
  l2cache_1.FetchResp_recv : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; 
  l2cache_1.FetchXResp_recv : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; 
  l2cache_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3682,19 +3682,19 @@ Model complete
  l1cache_2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_2.GetS_recv : Accumulator : Sum.u64 = 21222; SumSQ.u64 = 21222; Count.u64 = 21222; Min.u64 = 1; Max.u64 = 1; 
- l1cache_2.GetX_recv : Accumulator : Sum.u64 = 5656; SumSQ.u64 = 5656; Count.u64 = 5656; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_2.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_2.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_2.GetSResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_2.GetSResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
  l1cache_2.GetXResp_recv : Accumulator : Sum.u64 = 362; SumSQ.u64 = 362; Count.u64 = 362; Min.u64 = 1; Max.u64 = 1; 
  l1cache_2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.Inv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l1cache_2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.FetchInv_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
- l1cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 877; SumSQ.u64 = 877; Count.u64 = 877; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; 
  l1cache_2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.MSHR_occupancy : Accumulator : Sum.u64 = 421448; SumSQ.u64 = 9191218; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -3852,19 +3852,19 @@ Model complete
  l1cache_3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_3.GetS_recv : Accumulator : Sum.u64 = 22456; SumSQ.u64 = 22456; Count.u64 = 22456; Min.u64 = 1; Max.u64 = 1; 
- l1cache_3.GetX_recv : Accumulator : Sum.u64 = 7198; SumSQ.u64 = 7198; Count.u64 = 7198; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_3.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_3.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_3.GetSResp_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
- l1cache_3.GetXResp_recv : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_3.GetSResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_3.GetXResp_recv : Accumulator : Sum.u64 = 362; SumSQ.u64 = 362; Count.u64 = 362; Min.u64 = 1; Max.u64 = 1; 
  l1cache_3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.Inv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l1cache_3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.FetchInv_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
- l1cache_3.FetchInvX_recv : Accumulator : Sum.u64 = 788; SumSQ.u64 = 788; Count.u64 = 788; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_3.FetchInvX_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; 
  l1cache_3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.MSHR_occupancy : Accumulator : Sum.u64 = 415145; SumSQ.u64 = 9024217; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -4185,11 +4185,11 @@ Model complete
  l2cache_2.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_2.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_2.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_2.Inv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_2.Inv_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
  l2cache_2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_2.FetchInv_recv : Accumulator : Sum.u64 = 484; SumSQ.u64 = 484; Count.u64 = 484; Min.u64 = 1; Max.u64 = 1; 
- l2cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 554; SumSQ.u64 = 554; Count.u64 = 554; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_2.FetchInv_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l2cache_2.FetchResp_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
  l2cache_2.FetchXResp_recv : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; 
  l2cache_2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -4333,19 +4333,19 @@ Model complete
  l1cache_4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_4.GetS_recv : Accumulator : Sum.u64 = 21224; SumSQ.u64 = 21224; Count.u64 = 21224; Min.u64 = 1; Max.u64 = 1; 
- l1cache_4.GetX_recv : Accumulator : Sum.u64 = 5580; SumSQ.u64 = 5580; Count.u64 = 5580; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_4.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_4.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_4.GetSResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
- l1cache_4.GetXResp_recv : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_4.GetSResp_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_4.GetXResp_recv : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; 
  l1cache_4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_4.FetchInvX_recv : Accumulator : Sum.u64 = 865; SumSQ.u64 = 865; Count.u64 = 865; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_4.FetchInvX_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; 
  l1cache_4.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.MSHR_occupancy : Accumulator : Sum.u64 = 418352; SumSQ.u64 = 9151918; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -4503,19 +4503,19 @@ Model complete
  l1cache_5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_5.GetS_recv : Accumulator : Sum.u64 = 21539; SumSQ.u64 = 21539; Count.u64 = 21539; Min.u64 = 1; Max.u64 = 1; 
- l1cache_5.GetX_recv : Accumulator : Sum.u64 = 5364; SumSQ.u64 = 5364; Count.u64 = 5364; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_5.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_5.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_5.GetSResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
- l1cache_5.GetXResp_recv : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_5.GetSResp_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_5.GetXResp_recv : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; 
  l1cache_5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_5.FetchInvX_recv : Accumulator : Sum.u64 = 868; SumSQ.u64 = 868; Count.u64 = 868; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_5.FetchInvX_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; 
  l1cache_5.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.MSHR_occupancy : Accumulator : Sum.u64 = 420979; SumSQ.u64 = 9255399; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -4836,11 +4836,11 @@ Model complete
  l2cache_3.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_3.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_3.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_3.Inv_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_3.Inv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l2cache_3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_3.FetchInv_recv : Accumulator : Sum.u64 = 486; SumSQ.u64 = 486; Count.u64 = 486; Min.u64 = 1; Max.u64 = 1; 
- l2cache_3.FetchInvX_recv : Accumulator : Sum.u64 = 541; SumSQ.u64 = 541; Count.u64 = 541; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_3.FetchInv_recv : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_3.FetchInvX_recv : Accumulator : Sum.u64 = 248; SumSQ.u64 = 248; Count.u64 = 248; Min.u64 = 1; Max.u64 = 1; 
  l2cache_3.FetchResp_recv : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; 
  l2cache_3.FetchXResp_recv : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; 
  l2cache_3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -4984,19 +4984,19 @@ Model complete
  l1cache_6.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_6.GetS_recv : Accumulator : Sum.u64 = 21467; SumSQ.u64 = 21467; Count.u64 = 21467; Min.u64 = 1; Max.u64 = 1; 
- l1cache_6.GetX_recv : Accumulator : Sum.u64 = 5807; SumSQ.u64 = 5807; Count.u64 = 5807; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_6.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_6.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_6.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_6.GetSResp_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; 
- l1cache_6.GetXResp_recv : Accumulator : Sum.u64 = 367; SumSQ.u64 = 367; Count.u64 = 367; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_6.GetSResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_6.GetXResp_recv : Accumulator : Sum.u64 = 365; SumSQ.u64 = 365; Count.u64 = 365; Min.u64 = 1; Max.u64 = 1; 
  l1cache_6.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_6.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_6.FetchInvX_recv : Accumulator : Sum.u64 = 786; SumSQ.u64 = 786; Count.u64 = 786; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_6.FetchInvX_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
  l1cache_6.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.MSHR_occupancy : Accumulator : Sum.u64 = 422135; SumSQ.u64 = 9248329; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -5154,19 +5154,19 @@ Model complete
  l1cache_7.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_7.GetS_recv : Accumulator : Sum.u64 = 21764; SumSQ.u64 = 21764; Count.u64 = 21764; Min.u64 = 1; Max.u64 = 1; 
- l1cache_7.GetX_recv : Accumulator : Sum.u64 = 5546; SumSQ.u64 = 5546; Count.u64 = 5546; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_7.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_7.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_7.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_7.GetSResp_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
- l1cache_7.GetXResp_recv : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_7.GetSResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_7.GetXResp_recv : Accumulator : Sum.u64 = 362; SumSQ.u64 = 362; Count.u64 = 362; Min.u64 = 1; Max.u64 = 1; 
  l1cache_7.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.Inv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l1cache_7.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.FetchInv_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; 
- l1cache_7.FetchInvX_recv : Accumulator : Sum.u64 = 844; SumSQ.u64 = 844; Count.u64 = 844; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_7.FetchInvX_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; 
  l1cache_7.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.MSHR_occupancy : Accumulator : Sum.u64 = 420619; SumSQ.u64 = 9226305; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -5514,11 +5514,11 @@ Model complete
  l2cache_4.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_4.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_4.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_4.Inv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_4.Inv_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l2cache_4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_4.FetchInv_recv : Accumulator : Sum.u64 = 499; SumSQ.u64 = 499; Count.u64 = 499; Min.u64 = 1; Max.u64 = 1; 
- l2cache_4.FetchInvX_recv : Accumulator : Sum.u64 = 515; SumSQ.u64 = 515; Count.u64 = 515; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_4.FetchInv_recv : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_4.FetchInvX_recv : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; 
  l2cache_4.FetchResp_recv : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; 
  l2cache_4.FetchXResp_recv : Accumulator : Sum.u64 = 227; SumSQ.u64 = 227; Count.u64 = 227; Min.u64 = 1; Max.u64 = 1; 
  l2cache_4.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -5662,19 +5662,19 @@ Model complete
  l1cache_8.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_8.GetS_recv : Accumulator : Sum.u64 = 21100; SumSQ.u64 = 21100; Count.u64 = 21100; Min.u64 = 1; Max.u64 = 1; 
- l1cache_8.GetX_recv : Accumulator : Sum.u64 = 4987; SumSQ.u64 = 4987; Count.u64 = 4987; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_8.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_8.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_8.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.GetSResp_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
- l1cache_8.GetXResp_recv : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_8.GetXResp_recv : Accumulator : Sum.u64 = 360; SumSQ.u64 = 360; Count.u64 = 360; Min.u64 = 1; Max.u64 = 1; 
  l1cache_8.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.Inv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_8.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.FetchInv_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
- l1cache_8.FetchInvX_recv : Accumulator : Sum.u64 = 822; SumSQ.u64 = 822; Count.u64 = 822; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_8.FetchInvX_recv : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; 
  l1cache_8.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.MSHR_occupancy : Accumulator : Sum.u64 = 425811; SumSQ.u64 = 9322747; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -5832,8 +5832,8 @@ Model complete
  l1cache_9.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_9.GetS_recv : Accumulator : Sum.u64 = 21423; SumSQ.u64 = 21423; Count.u64 = 21423; Min.u64 = 1; Max.u64 = 1; 
- l1cache_9.GetX_recv : Accumulator : Sum.u64 = 6851; SumSQ.u64 = 6851; Count.u64 = 6851; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_9.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_9.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_9.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -5843,8 +5843,8 @@ Model complete
  l1cache_9.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_9.FetchInv_recv : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; 
- l1cache_9.FetchInvX_recv : Accumulator : Sum.u64 = 887; SumSQ.u64 = 887; Count.u64 = 887; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_9.FetchInv_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_9.FetchInvX_recv : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; 
  l1cache_9.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.MSHR_occupancy : Accumulator : Sum.u64 = 417187; SumSQ.u64 = 9066599; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -6192,11 +6192,11 @@ Model complete
  l2cache_5.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_5.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_5.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_5.Inv_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_5.Inv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l2cache_5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_5.FetchInv_recv : Accumulator : Sum.u64 = 486; SumSQ.u64 = 486; Count.u64 = 486; Min.u64 = 1; Max.u64 = 1; 
- l2cache_5.FetchInvX_recv : Accumulator : Sum.u64 = 550; SumSQ.u64 = 550; Count.u64 = 550; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_5.FetchInv_recv : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_5.FetchInvX_recv : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; 
  l2cache_5.FetchResp_recv : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; 
  l2cache_5.FetchXResp_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; 
  l2cache_5.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -6340,19 +6340,19 @@ Model complete
  l1cache_10.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_10.GetS_recv : Accumulator : Sum.u64 = 21826; SumSQ.u64 = 21826; Count.u64 = 21826; Min.u64 = 1; Max.u64 = 1; 
- l1cache_10.GetX_recv : Accumulator : Sum.u64 = 5469; SumSQ.u64 = 5469; Count.u64 = 5469; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_10.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_10.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_10.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_10.GetSResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
- l1cache_10.GetXResp_recv : Accumulator : Sum.u64 = 368; SumSQ.u64 = 368; Count.u64 = 368; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_10.GetSResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_10.GetXResp_recv : Accumulator : Sum.u64 = 366; SumSQ.u64 = 366; Count.u64 = 366; Min.u64 = 1; Max.u64 = 1; 
  l1cache_10.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.Inv_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l1cache_10.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.FetchInv_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
- l1cache_10.FetchInvX_recv : Accumulator : Sum.u64 = 878; SumSQ.u64 = 878; Count.u64 = 878; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_10.FetchInvX_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
  l1cache_10.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.MSHR_occupancy : Accumulator : Sum.u64 = 430279; SumSQ.u64 = 9451261; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -6510,19 +6510,19 @@ Model complete
  l1cache_11.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_11.GetS_recv : Accumulator : Sum.u64 = 22328; SumSQ.u64 = 22328; Count.u64 = 22328; Min.u64 = 1; Max.u64 = 1; 
- l1cache_11.GetX_recv : Accumulator : Sum.u64 = 6515; SumSQ.u64 = 6515; Count.u64 = 6515; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_11.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_11.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_11.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_11.GetSResp_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
- l1cache_11.GetXResp_recv : Accumulator : Sum.u64 = 368; SumSQ.u64 = 368; Count.u64 = 368; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_11.GetSResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_11.GetXResp_recv : Accumulator : Sum.u64 = 365; SumSQ.u64 = 365; Count.u64 = 365; Min.u64 = 1; Max.u64 = 1; 
  l1cache_11.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.Inv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l1cache_11.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.FetchInv_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
- l1cache_11.FetchInvX_recv : Accumulator : Sum.u64 = 825; SumSQ.u64 = 825; Count.u64 = 825; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_11.FetchInvX_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
  l1cache_11.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.MSHR_occupancy : Accumulator : Sum.u64 = 424342; SumSQ.u64 = 9296262; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -6866,11 +6866,11 @@ Model complete
  l2cache_6.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_6.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_6.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_6.Inv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_6.Inv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l2cache_6.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_6.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_6.FetchInv_recv : Accumulator : Sum.u64 = 489; SumSQ.u64 = 489; Count.u64 = 489; Min.u64 = 1; Max.u64 = 1; 
- l2cache_6.FetchInvX_recv : Accumulator : Sum.u64 = 433; SumSQ.u64 = 433; Count.u64 = 433; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_6.FetchInv_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_6.FetchInvX_recv : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; 
  l2cache_6.FetchResp_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
  l2cache_6.FetchXResp_recv : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; 
  l2cache_6.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -7014,19 +7014,19 @@ Model complete
  l1cache_12.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_12.GetS_recv : Accumulator : Sum.u64 = 21705; SumSQ.u64 = 21705; Count.u64 = 21705; Min.u64 = 1; Max.u64 = 1; 
- l1cache_12.GetX_recv : Accumulator : Sum.u64 = 5577; SumSQ.u64 = 5577; Count.u64 = 5577; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_12.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_12.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_12.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_12.GetSResp_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; 
- l1cache_12.GetXResp_recv : Accumulator : Sum.u64 = 368; SumSQ.u64 = 368; Count.u64 = 368; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_12.GetSResp_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_12.GetXResp_recv : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; 
  l1cache_12.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_12.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_12.FetchInvX_recv : Accumulator : Sum.u64 = 752; SumSQ.u64 = 752; Count.u64 = 752; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_12.FetchInvX_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
  l1cache_12.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.MSHR_occupancy : Accumulator : Sum.u64 = 420026; SumSQ.u64 = 9211310; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -7184,19 +7184,19 @@ Model complete
  l1cache_13.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_13.GetS_recv : Accumulator : Sum.u64 = 20396; SumSQ.u64 = 20396; Count.u64 = 20396; Min.u64 = 1; Max.u64 = 1; 
- l1cache_13.GetX_recv : Accumulator : Sum.u64 = 4616; SumSQ.u64 = 4616; Count.u64 = 4616; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_13.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_13.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_13.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_13.GetSResp_recv : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; 
- l1cache_13.GetXResp_recv : Accumulator : Sum.u64 = 327; SumSQ.u64 = 327; Count.u64 = 327; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_13.GetSResp_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_13.GetXResp_recv : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; 
  l1cache_13.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_13.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_13.FetchInv_recv : Accumulator : Sum.u64 = 213; SumSQ.u64 = 213; Count.u64 = 213; Min.u64 = 1; Max.u64 = 1; 
- l1cache_13.FetchInvX_recv : Accumulator : Sum.u64 = 539; SumSQ.u64 = 539; Count.u64 = 539; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_13.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_13.FetchInvX_recv : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; 
  l1cache_13.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.MSHR_occupancy : Accumulator : Sum.u64 = 429963; SumSQ.u64 = 9403687; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -7517,11 +7517,11 @@ Model complete
  l2cache_7.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_7.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_7.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_7.Inv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_7.Inv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
  l2cache_7.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_7.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_7.FetchInv_recv : Accumulator : Sum.u64 = 482; SumSQ.u64 = 482; Count.u64 = 482; Min.u64 = 1; Max.u64 = 1; 
- l2cache_7.FetchInvX_recv : Accumulator : Sum.u64 = 517; SumSQ.u64 = 517; Count.u64 = 517; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_7.FetchInv_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_7.FetchInvX_recv : Accumulator : Sum.u64 = 255; SumSQ.u64 = 255; Count.u64 = 255; Min.u64 = 1; Max.u64 = 1; 
  l2cache_7.FetchResp_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
  l2cache_7.FetchXResp_recv : Accumulator : Sum.u64 = 246; SumSQ.u64 = 246; Count.u64 = 246; Min.u64 = 1; Max.u64 = 1; 
  l2cache_7.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -7665,19 +7665,19 @@ Model complete
  l1cache_14.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_14.GetS_recv : Accumulator : Sum.u64 = 21844; SumSQ.u64 = 21844; Count.u64 = 21844; Min.u64 = 1; Max.u64 = 1; 
- l1cache_14.GetX_recv : Accumulator : Sum.u64 = 6187; SumSQ.u64 = 6187; Count.u64 = 6187; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_14.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_14.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_14.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_14.GetSResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
- l1cache_14.GetXResp_recv : Accumulator : Sum.u64 = 365; SumSQ.u64 = 365; Count.u64 = 365; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_14.GetSResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_14.GetXResp_recv : Accumulator : Sum.u64 = 362; SumSQ.u64 = 362; Count.u64 = 362; Min.u64 = 1; Max.u64 = 1; 
  l1cache_14.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.Inv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l1cache_14.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.FetchInv_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; 
- l1cache_14.FetchInvX_recv : Accumulator : Sum.u64 = 787; SumSQ.u64 = 787; Count.u64 = 787; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_14.FetchInvX_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
  l1cache_14.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.MSHR_occupancy : Accumulator : Sum.u64 = 414035; SumSQ.u64 = 9069337; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -7835,19 +7835,19 @@ Model complete
  l1cache_15.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_15.GetS_recv : Accumulator : Sum.u64 = 20937; SumSQ.u64 = 20937; Count.u64 = 20937; Min.u64 = 1; Max.u64 = 1; 
- l1cache_15.GetX_recv : Accumulator : Sum.u64 = 4987; SumSQ.u64 = 4987; Count.u64 = 4987; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_15.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_15.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_15.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_15.GetXResp_recv : Accumulator : Sum.u64 = 378; SumSQ.u64 = 378; Count.u64 = 378; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_15.GetXResp_recv : Accumulator : Sum.u64 = 375; SumSQ.u64 = 375; Count.u64 = 375; Min.u64 = 1; Max.u64 = 1; 
  l1cache_15.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.Inv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_15.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.FetchInv_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
- l1cache_15.FetchInvX_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_15.FetchInvX_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  l1cache_15.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.MSHR_occupancy : Accumulator : Sum.u64 = 426012; SumSQ.u64 = 9315566; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -8168,11 +8168,11 @@ Model complete
  l2cache_8.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_8.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_8.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_8.Inv_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_8.Inv_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
  l2cache_8.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_8.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_8.FetchInv_recv : Accumulator : Sum.u64 = 476; SumSQ.u64 = 476; Count.u64 = 476; Min.u64 = 1; Max.u64 = 1; 
- l2cache_8.FetchInvX_recv : Accumulator : Sum.u64 = 519; SumSQ.u64 = 519; Count.u64 = 519; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_8.FetchInv_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_8.FetchInvX_recv : Accumulator : Sum.u64 = 262; SumSQ.u64 = 262; Count.u64 = 262; Min.u64 = 1; Max.u64 = 1; 
  l2cache_8.FetchResp_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; 
  l2cache_8.FetchXResp_recv : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; 
  l2cache_8.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -8316,19 +8316,19 @@ Model complete
  l1cache_16.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_16.GetS_recv : Accumulator : Sum.u64 = 21627; SumSQ.u64 = 21627; Count.u64 = 21627; Min.u64 = 1; Max.u64 = 1; 
- l1cache_16.GetX_recv : Accumulator : Sum.u64 = 6444; SumSQ.u64 = 6444; Count.u64 = 6444; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_16.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_16.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_16.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_16.GetSResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
- l1cache_16.GetXResp_recv : Accumulator : Sum.u64 = 376; SumSQ.u64 = 376; Count.u64 = 376; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_16.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_16.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; 
  l1cache_16.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l1cache_16.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.FetchInv_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
- l1cache_16.FetchInvX_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_16.FetchInvX_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
  l1cache_16.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.MSHR_occupancy : Accumulator : Sum.u64 = 416365; SumSQ.u64 = 9068239; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -8486,19 +8486,19 @@ Model complete
  l1cache_17.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_17.GetS_recv : Accumulator : Sum.u64 = 20794; SumSQ.u64 = 20794; Count.u64 = 20794; Min.u64 = 1; Max.u64 = 1; 
- l1cache_17.GetX_recv : Accumulator : Sum.u64 = 5090; SumSQ.u64 = 5090; Count.u64 = 5090; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_17.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_17.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_17.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_17.GetSResp_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
- l1cache_17.GetXResp_recv : Accumulator : Sum.u64 = 376; SumSQ.u64 = 376; Count.u64 = 376; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_17.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_17.GetXResp_recv : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; 
  l1cache_17.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l1cache_17.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.FetchInv_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
- l1cache_17.FetchInvX_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_17.FetchInvX_recv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; 
  l1cache_17.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.MSHR_occupancy : Accumulator : Sum.u64 = 418846; SumSQ.u64 = 9144288; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -8819,11 +8819,11 @@ Model complete
  l2cache_9.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_9.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_9.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_9.Inv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_9.Inv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l2cache_9.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_9.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_9.FetchInv_recv : Accumulator : Sum.u64 = 484; SumSQ.u64 = 484; Count.u64 = 484; Min.u64 = 1; Max.u64 = 1; 
- l2cache_9.FetchInvX_recv : Accumulator : Sum.u64 = 502; SumSQ.u64 = 502; Count.u64 = 502; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_9.FetchInv_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_9.FetchInvX_recv : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; 
  l2cache_9.FetchResp_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
  l2cache_9.FetchXResp_recv : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; 
  l2cache_9.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -8967,19 +8967,19 @@ Model complete
  l1cache_18.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_18.GetS_recv : Accumulator : Sum.u64 = 21190; SumSQ.u64 = 21190; Count.u64 = 21190; Min.u64 = 1; Max.u64 = 1; 
- l1cache_18.GetX_recv : Accumulator : Sum.u64 = 6226; SumSQ.u64 = 6226; Count.u64 = 6226; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_18.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_18.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_18.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.GetSResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
- l1cache_18.GetXResp_recv : Accumulator : Sum.u64 = 380; SumSQ.u64 = 380; Count.u64 = 380; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_18.GetXResp_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; 
  l1cache_18.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.Inv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l1cache_18.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.FetchInv_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
- l1cache_18.FetchInvX_recv : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_18.FetchInvX_recv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; 
  l1cache_18.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.MSHR_occupancy : Accumulator : Sum.u64 = 412775; SumSQ.u64 = 8974385; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -9137,19 +9137,19 @@ Model complete
  l1cache_19.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_19.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_19.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_19.GetS_recv : Accumulator : Sum.u64 = 20865; SumSQ.u64 = 20865; Count.u64 = 20865; Min.u64 = 1; Max.u64 = 1; 
- l1cache_19.GetX_recv : Accumulator : Sum.u64 = 4570; SumSQ.u64 = 4570; Count.u64 = 4570; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_19.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_19.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_19.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_19.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_19.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_19.GetSResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
- l1cache_19.GetXResp_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_19.GetSResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_19.GetXResp_recv : Accumulator : Sum.u64 = 369; SumSQ.u64 = 369; Count.u64 = 369; Min.u64 = 1; Max.u64 = 1; 
  l1cache_19.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_19.Inv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l1cache_19.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_19.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_19.FetchInv_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; 
- l1cache_19.FetchInvX_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_19.FetchInvX_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; 
  l1cache_19.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_19.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_19.MSHR_occupancy : Accumulator : Sum.u64 = 422845; SumSQ.u64 = 9231557; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -9470,11 +9470,11 @@ Model complete
  l2cache_10.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_10.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_10.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_10.Inv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_10.Inv_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
  l2cache_10.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_10.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_10.FetchInv_recv : Accumulator : Sum.u64 = 482; SumSQ.u64 = 482; Count.u64 = 482; Min.u64 = 1; Max.u64 = 1; 
- l2cache_10.FetchInvX_recv : Accumulator : Sum.u64 = 509; SumSQ.u64 = 509; Count.u64 = 509; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_10.FetchInv_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_10.FetchInvX_recv : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; 
  l2cache_10.FetchResp_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
  l2cache_10.FetchXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l2cache_10.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -9618,19 +9618,19 @@ Model complete
  l1cache_20.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_20.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_20.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_20.GetS_recv : Accumulator : Sum.u64 = 21907; SumSQ.u64 = 21907; Count.u64 = 21907; Min.u64 = 1; Max.u64 = 1; 
- l1cache_20.GetX_recv : Accumulator : Sum.u64 = 5267; SumSQ.u64 = 5267; Count.u64 = 5267; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_20.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_20.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_20.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_20.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_20.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_20.GetSResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
- l1cache_20.GetXResp_recv : Accumulator : Sum.u64 = 380; SumSQ.u64 = 380; Count.u64 = 380; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_20.GetSResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_20.GetXResp_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; 
  l1cache_20.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_20.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_20.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_20.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_20.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_20.FetchInvX_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_20.FetchInvX_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  l1cache_20.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_20.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_20.MSHR_occupancy : Accumulator : Sum.u64 = 419331; SumSQ.u64 = 9177161; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -9788,19 +9788,19 @@ Model complete
  l1cache_21.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_21.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_21.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_21.GetS_recv : Accumulator : Sum.u64 = 22026; SumSQ.u64 = 22026; Count.u64 = 22026; Min.u64 = 1; Max.u64 = 1; 
- l1cache_21.GetX_recv : Accumulator : Sum.u64 = 6979; SumSQ.u64 = 6979; Count.u64 = 6979; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_21.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_21.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_21.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_21.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_21.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_21.GetSResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
- l1cache_21.GetXResp_recv : Accumulator : Sum.u64 = 375; SumSQ.u64 = 375; Count.u64 = 375; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_21.GetSResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_21.GetXResp_recv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; 
  l1cache_21.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_21.Inv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l1cache_21.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_21.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_21.FetchInv_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
- l1cache_21.FetchInvX_recv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_21.FetchInvX_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l1cache_21.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_21.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_21.MSHR_occupancy : Accumulator : Sum.u64 = 416441; SumSQ.u64 = 9085153; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -10144,11 +10144,11 @@ Model complete
  l2cache_11.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_11.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_11.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_11.Inv_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_11.Inv_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
  l2cache_11.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_11.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_11.FetchInv_recv : Accumulator : Sum.u64 = 476; SumSQ.u64 = 476; Count.u64 = 476; Min.u64 = 1; Max.u64 = 1; 
- l2cache_11.FetchInvX_recv : Accumulator : Sum.u64 = 509; SumSQ.u64 = 509; Count.u64 = 509; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_11.FetchInv_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_11.FetchInvX_recv : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; 
  l2cache_11.FetchResp_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; 
  l2cache_11.FetchXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
  l2cache_11.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -10292,13 +10292,13 @@ Model complete
  l1cache_22.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_22.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_22.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_22.GetS_recv : Accumulator : Sum.u64 = 21956; SumSQ.u64 = 21956; Count.u64 = 21956; Min.u64 = 1; Max.u64 = 1; 
- l1cache_22.GetX_recv : Accumulator : Sum.u64 = 6255; SumSQ.u64 = 6255; Count.u64 = 6255; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_22.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_22.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_22.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_22.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_22.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_22.GetSResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
- l1cache_22.GetXResp_recv : Accumulator : Sum.u64 = 375; SumSQ.u64 = 375; Count.u64 = 375; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_22.GetXResp_recv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; 
  l1cache_22.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_22.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l1cache_22.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -10462,19 +10462,19 @@ Model complete
  l1cache_23.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_23.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_23.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_23.GetS_recv : Accumulator : Sum.u64 = 20879; SumSQ.u64 = 20879; Count.u64 = 20879; Min.u64 = 1; Max.u64 = 1; 
- l1cache_23.GetX_recv : Accumulator : Sum.u64 = 5073; SumSQ.u64 = 5073; Count.u64 = 5073; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_23.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_23.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_23.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_23.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_23.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_23.GetSResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
- l1cache_23.GetXResp_recv : Accumulator : Sum.u64 = 374; SumSQ.u64 = 374; Count.u64 = 374; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_23.GetSResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_23.GetXResp_recv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; 
  l1cache_23.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_23.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l1cache_23.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_23.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_23.FetchInv_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
- l1cache_23.FetchInvX_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_23.FetchInvX_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  l1cache_23.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_23.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_23.MSHR_occupancy : Accumulator : Sum.u64 = 421039; SumSQ.u64 = 9205715; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -10818,11 +10818,11 @@ Model complete
  l2cache_12.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_12.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_12.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_12.Inv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_12.Inv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
  l2cache_12.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_12.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_12.FetchInv_recv : Accumulator : Sum.u64 = 482; SumSQ.u64 = 482; Count.u64 = 482; Min.u64 = 1; Max.u64 = 1; 
- l2cache_12.FetchInvX_recv : Accumulator : Sum.u64 = 515; SumSQ.u64 = 515; Count.u64 = 515; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_12.FetchInv_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_12.FetchInvX_recv : Accumulator : Sum.u64 = 259; SumSQ.u64 = 259; Count.u64 = 259; Min.u64 = 1; Max.u64 = 1; 
  l2cache_12.FetchResp_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
  l2cache_12.FetchXResp_recv : Accumulator : Sum.u64 = 255; SumSQ.u64 = 255; Count.u64 = 255; Min.u64 = 1; Max.u64 = 1; 
  l2cache_12.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -10966,19 +10966,19 @@ Model complete
  l1cache_24.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_24.GetS_recv : Accumulator : Sum.u64 = 20616; SumSQ.u64 = 20616; Count.u64 = 20616; Min.u64 = 1; Max.u64 = 1; 
- l1cache_24.GetX_recv : Accumulator : Sum.u64 = 4575; SumSQ.u64 = 4575; Count.u64 = 4575; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_24.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_24.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_24.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
- l1cache_24.GetXResp_recv : Accumulator : Sum.u64 = 376; SumSQ.u64 = 376; Count.u64 = 376; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_24.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; 
  l1cache_24.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l1cache_24.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.FetchInv_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
- l1cache_24.FetchInvX_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_24.FetchInvX_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
  l1cache_24.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.MSHR_occupancy : Accumulator : Sum.u64 = 426467; SumSQ.u64 = 9303395; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -11136,19 +11136,19 @@ Model complete
  l1cache_25.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_25.GetS_recv : Accumulator : Sum.u64 = 20226; SumSQ.u64 = 20226; Count.u64 = 20226; Min.u64 = 1; Max.u64 = 1; 
- l1cache_25.GetX_recv : Accumulator : Sum.u64 = 4428; SumSQ.u64 = 4428; Count.u64 = 4428; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_25.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_25.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_25.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
- l1cache_25.GetXResp_recv : Accumulator : Sum.u64 = 379; SumSQ.u64 = 379; Count.u64 = 379; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_25.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; 
  l1cache_25.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.Inv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l1cache_25.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.FetchInv_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; 
- l1cache_25.FetchInvX_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_25.FetchInvX_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  l1cache_25.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.MSHR_occupancy : Accumulator : Sum.u64 = 421428; SumSQ.u64 = 9205362; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -11469,11 +11469,11 @@ Model complete
  l2cache_13.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_13.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_13.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_13.Inv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_13.Inv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l2cache_13.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_13.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_13.FetchInv_recv : Accumulator : Sum.u64 = 484; SumSQ.u64 = 484; Count.u64 = 484; Min.u64 = 1; Max.u64 = 1; 
- l2cache_13.FetchInvX_recv : Accumulator : Sum.u64 = 510; SumSQ.u64 = 510; Count.u64 = 510; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_13.FetchInv_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_13.FetchInvX_recv : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; 
  l2cache_13.FetchResp_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
  l2cache_13.FetchXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
  l2cache_13.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -11617,19 +11617,19 @@ Model complete
  l1cache_26.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_26.GetS_recv : Accumulator : Sum.u64 = 21909; SumSQ.u64 = 21909; Count.u64 = 21909; Min.u64 = 1; Max.u64 = 1; 
- l1cache_26.GetX_recv : Accumulator : Sum.u64 = 7083; SumSQ.u64 = 7083; Count.u64 = 7083; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_26.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_26.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_26.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
- l1cache_26.GetXResp_recv : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_26.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; 
  l1cache_26.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_26.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_26.FetchInvX_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_26.FetchInvX_recv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; 
  l1cache_26.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.MSHR_occupancy : Accumulator : Sum.u64 = 413386; SumSQ.u64 = 8971880; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -11787,19 +11787,19 @@ Model complete
  l1cache_27.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_27.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_27.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_27.GetS_recv : Accumulator : Sum.u64 = 20962; SumSQ.u64 = 20962; Count.u64 = 20962; Min.u64 = 1; Max.u64 = 1; 
- l1cache_27.GetX_recv : Accumulator : Sum.u64 = 5401; SumSQ.u64 = 5401; Count.u64 = 5401; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_27.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_27.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_27.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_27.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_27.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_27.GetSResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
- l1cache_27.GetXResp_recv : Accumulator : Sum.u64 = 375; SumSQ.u64 = 375; Count.u64 = 375; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_27.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_27.GetXResp_recv : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; 
  l1cache_27.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_27.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_27.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_27.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_27.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_27.FetchInvX_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_27.FetchInvX_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l1cache_27.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_27.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_27.MSHR_occupancy : Accumulator : Sum.u64 = 430828; SumSQ.u64 = 9367262; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -12120,11 +12120,11 @@ Model complete
  l2cache_14.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_14.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_14.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_14.Inv_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_14.Inv_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
  l2cache_14.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_14.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_14.FetchInv_recv : Accumulator : Sum.u64 = 488; SumSQ.u64 = 488; Count.u64 = 488; Min.u64 = 1; Max.u64 = 1; 
- l2cache_14.FetchInvX_recv : Accumulator : Sum.u64 = 499; SumSQ.u64 = 499; Count.u64 = 499; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_14.FetchInv_recv : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_14.FetchInvX_recv : Accumulator : Sum.u64 = 255; SumSQ.u64 = 255; Count.u64 = 255; Min.u64 = 1; Max.u64 = 1; 
  l2cache_14.FetchResp_recv : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; 
  l2cache_14.FetchXResp_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
  l2cache_14.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -12268,19 +12268,19 @@ Model complete
  l1cache_28.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_28.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_28.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_28.GetS_recv : Accumulator : Sum.u64 = 21558; SumSQ.u64 = 21558; Count.u64 = 21558; Min.u64 = 1; Max.u64 = 1; 
- l1cache_28.GetX_recv : Accumulator : Sum.u64 = 6333; SumSQ.u64 = 6333; Count.u64 = 6333; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_28.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_28.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_28.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_28.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_28.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_28.GetSResp_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
- l1cache_28.GetXResp_recv : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_28.GetSResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_28.GetXResp_recv : Accumulator : Sum.u64 = 367; SumSQ.u64 = 367; Count.u64 = 367; Min.u64 = 1; Max.u64 = 1; 
  l1cache_28.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_28.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_28.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_28.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_28.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_28.FetchInvX_recv : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_28.FetchInvX_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
  l1cache_28.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_28.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_28.MSHR_occupancy : Accumulator : Sum.u64 = 424538; SumSQ.u64 = 9197892; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -12438,19 +12438,19 @@ Model complete
  l1cache_29.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_29.GetS_recv : Accumulator : Sum.u64 = 22209; SumSQ.u64 = 22209; Count.u64 = 22209; Min.u64 = 1; Max.u64 = 1; 
- l1cache_29.GetX_recv : Accumulator : Sum.u64 = 7872; SumSQ.u64 = 7872; Count.u64 = 7872; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_29.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_29.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_29.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.GetSResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
- l1cache_29.GetXResp_recv : Accumulator : Sum.u64 = 374; SumSQ.u64 = 374; Count.u64 = 374; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_29.GetXResp_recv : Accumulator : Sum.u64 = 369; SumSQ.u64 = 369; Count.u64 = 369; Min.u64 = 1; Max.u64 = 1; 
  l1cache_29.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.Inv_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l1cache_29.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.FetchInv_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
- l1cache_29.FetchInvX_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_29.FetchInvX_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
  l1cache_29.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.MSHR_occupancy : Accumulator : Sum.u64 = 425669; SumSQ.u64 = 9202783; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -12771,11 +12771,11 @@ Model complete
  l2cache_15.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_15.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_15.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_15.Inv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_15.Inv_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l2cache_15.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_15.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_15.FetchInv_recv : Accumulator : Sum.u64 = 498; SumSQ.u64 = 498; Count.u64 = 498; Min.u64 = 1; Max.u64 = 1; 
- l2cache_15.FetchInvX_recv : Accumulator : Sum.u64 = 495; SumSQ.u64 = 495; Count.u64 = 495; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_15.FetchInv_recv : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_15.FetchInvX_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l2cache_15.FetchResp_recv : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; 
  l2cache_15.FetchXResp_recv : Accumulator : Sum.u64 = 245; SumSQ.u64 = 245; Count.u64 = 245; Min.u64 = 1; Max.u64 = 1; 
  l2cache_15.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -12919,19 +12919,19 @@ Model complete
  l1cache_30.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_30.GetS_recv : Accumulator : Sum.u64 = 21032; SumSQ.u64 = 21032; Count.u64 = 21032; Min.u64 = 1; Max.u64 = 1; 
- l1cache_30.GetX_recv : Accumulator : Sum.u64 = 6024; SumSQ.u64 = 6024; Count.u64 = 6024; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_30.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_30.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_30.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
- l1cache_30.GetXResp_recv : Accumulator : Sum.u64 = 374; SumSQ.u64 = 374; Count.u64 = 374; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_30.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; 
  l1cache_30.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.FetchInv_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
- l1cache_30.FetchInvX_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_30.FetchInvX_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
  l1cache_30.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.MSHR_occupancy : Accumulator : Sum.u64 = 426427; SumSQ.u64 = 9234481; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -13089,19 +13089,19 @@ Model complete
  l1cache_31.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_31.GetS_recv : Accumulator : Sum.u64 = 20785; SumSQ.u64 = 20785; Count.u64 = 20785; Min.u64 = 1; Max.u64 = 1; 
- l1cache_31.GetX_recv : Accumulator : Sum.u64 = 5897; SumSQ.u64 = 5897; Count.u64 = 5897; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_31.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_31.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_31.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
- l1cache_31.GetXResp_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_31.GetXResp_recv : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; 
  l1cache_31.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.Inv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_31.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.FetchInv_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
- l1cache_31.FetchInvX_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_31.FetchInvX_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; 
  l1cache_31.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.MSHR_occupancy : Accumulator : Sum.u64 = 428343; SumSQ.u64 = 9261987; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -13422,11 +13422,11 @@ Model complete
  l2cache_16.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_16.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_16.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_16.Inv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_16.Inv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
  l2cache_16.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_16.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_16.FetchInv_recv : Accumulator : Sum.u64 = 482; SumSQ.u64 = 482; Count.u64 = 482; Min.u64 = 1; Max.u64 = 1; 
- l2cache_16.FetchInvX_recv : Accumulator : Sum.u64 = 511; SumSQ.u64 = 511; Count.u64 = 511; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_16.FetchInv_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_16.FetchInvX_recv : Accumulator : Sum.u64 = 259; SumSQ.u64 = 259; Count.u64 = 259; Min.u64 = 1; Max.u64 = 1; 
  l2cache_16.FetchResp_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
  l2cache_16.FetchXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l2cache_16.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -13570,19 +13570,19 @@ Model complete
  l1cache_32.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_32.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_32.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_32.GetS_recv : Accumulator : Sum.u64 = 21012; SumSQ.u64 = 21012; Count.u64 = 21012; Min.u64 = 1; Max.u64 = 1; 
- l1cache_32.GetX_recv : Accumulator : Sum.u64 = 5317; SumSQ.u64 = 5317; Count.u64 = 5317; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_32.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_32.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_32.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_32.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_32.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_32.GetSResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
- l1cache_32.GetXResp_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_32.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_32.GetXResp_recv : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; 
  l1cache_32.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_32.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_32.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_32.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_32.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_32.FetchInvX_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_32.FetchInvX_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l1cache_32.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_32.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_32.MSHR_occupancy : Accumulator : Sum.u64 = 432702; SumSQ.u64 = 9407254; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -13740,19 +13740,19 @@ Model complete
  l1cache_33.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_33.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_33.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_33.GetS_recv : Accumulator : Sum.u64 = 21067; SumSQ.u64 = 21067; Count.u64 = 21067; Min.u64 = 1; Max.u64 = 1; 
- l1cache_33.GetX_recv : Accumulator : Sum.u64 = 5675; SumSQ.u64 = 5675; Count.u64 = 5675; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_33.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_33.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_33.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_33.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_33.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_33.GetSResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
- l1cache_33.GetXResp_recv : Accumulator : Sum.u64 = 376; SumSQ.u64 = 376; Count.u64 = 376; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_33.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_33.GetXResp_recv : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; 
  l1cache_33.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_33.Inv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l1cache_33.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_33.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_33.FetchInv_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
- l1cache_33.FetchInvX_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_33.FetchInvX_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  l1cache_33.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_33.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_33.MSHR_occupancy : Accumulator : Sum.u64 = 431139; SumSQ.u64 = 9384415; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -14096,11 +14096,11 @@ Model complete
  l2cache_17.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_17.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_17.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_17.Inv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_17.Inv_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
  l2cache_17.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_17.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_17.FetchInv_recv : Accumulator : Sum.u64 = 484; SumSQ.u64 = 484; Count.u64 = 484; Min.u64 = 1; Max.u64 = 1; 
- l2cache_17.FetchInvX_recv : Accumulator : Sum.u64 = 503; SumSQ.u64 = 503; Count.u64 = 503; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_17.FetchInv_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_17.FetchInvX_recv : Accumulator : Sum.u64 = 258; SumSQ.u64 = 258; Count.u64 = 258; Min.u64 = 1; Max.u64 = 1; 
  l2cache_17.FetchResp_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
  l2cache_17.FetchXResp_recv : Accumulator : Sum.u64 = 245; SumSQ.u64 = 245; Count.u64 = 245; Min.u64 = 1; Max.u64 = 1; 
  l2cache_17.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -14244,19 +14244,19 @@ Model complete
  l1cache_34.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_34.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_34.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_34.GetS_recv : Accumulator : Sum.u64 = 21726; SumSQ.u64 = 21726; Count.u64 = 21726; Min.u64 = 1; Max.u64 = 1; 
- l1cache_34.GetX_recv : Accumulator : Sum.u64 = 6314; SumSQ.u64 = 6314; Count.u64 = 6314; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_34.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_34.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_34.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_34.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_34.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_34.GetSResp_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
- l1cache_34.GetXResp_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_34.GetSResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_34.GetXResp_recv : Accumulator : Sum.u64 = 367; SumSQ.u64 = 367; Count.u64 = 367; Min.u64 = 1; Max.u64 = 1; 
  l1cache_34.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_34.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_34.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_34.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_34.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_34.FetchInvX_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_34.FetchInvX_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
  l1cache_34.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_34.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_34.MSHR_occupancy : Accumulator : Sum.u64 = 434702; SumSQ.u64 = 9407154; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -14414,19 +14414,19 @@ Model complete
  l1cache_35.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_35.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_35.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_35.GetS_recv : Accumulator : Sum.u64 = 21832; SumSQ.u64 = 21832; Count.u64 = 21832; Min.u64 = 1; Max.u64 = 1; 
- l1cache_35.GetX_recv : Accumulator : Sum.u64 = 7296; SumSQ.u64 = 7296; Count.u64 = 7296; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_35.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_35.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_35.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_35.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_35.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_35.GetSResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
- l1cache_35.GetXResp_recv : Accumulator : Sum.u64 = 374; SumSQ.u64 = 374; Count.u64 = 374; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_35.GetSResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_35.GetXResp_recv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; 
  l1cache_35.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_35.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_35.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_35.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_35.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_35.FetchInvX_recv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_35.FetchInvX_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
  l1cache_35.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_35.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_35.MSHR_occupancy : Accumulator : Sum.u64 = 433197; SumSQ.u64 = 9315731; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -14774,7 +14774,7 @@ Model complete
  l2cache_18.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_18.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_18.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_18.FetchInvX_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_18.FetchInvX_recv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; 
  l2cache_18.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_18.FetchXResp_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; 
  l2cache_18.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -14918,13 +14918,13 @@ Model complete
  l1cache_36.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_36.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_36.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_36.GetS_recv : Accumulator : Sum.u64 = 10526; SumSQ.u64 = 10526; Count.u64 = 10526; Min.u64 = 1; Max.u64 = 1; 
- l1cache_36.GetX_recv : Accumulator : Sum.u64 = 3206; SumSQ.u64 = 3206; Count.u64 = 3206; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_36.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_36.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_36.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_36.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_36.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_36.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
- l1cache_36.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_36.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_36.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_36.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_36.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_36.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -15088,19 +15088,19 @@ Model complete
  l1cache_37.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_37.GetS_recv : Accumulator : Sum.u64 = 10928; SumSQ.u64 = 10928; Count.u64 = 10928; Min.u64 = 1; Max.u64 = 1; 
- l1cache_37.GetX_recv : Accumulator : Sum.u64 = 2506; SumSQ.u64 = 2506; Count.u64 = 2506; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_37.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_37.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_37.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_37.GetSResp_recv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_37.GetSResp_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; 
  l1cache_37.GetXResp_recv : Accumulator : Sum.u64 = 293; SumSQ.u64 = 293; Count.u64 = 293; Min.u64 = 1; Max.u64 = 1; 
  l1cache_37.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_37.FetchInvX_recv : Accumulator : Sum.u64 = 337; SumSQ.u64 = 337; Count.u64 = 337; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_37.FetchInvX_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; 
  l1cache_37.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.MSHR_occupancy : Accumulator : Sum.u64 = 366760; SumSQ.u64 = 6978750; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -15425,7 +15425,7 @@ Model complete
  l2cache_19.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_19.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_19.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_19.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_19.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l2cache_19.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_19.FetchXResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l2cache_19.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -15569,19 +15569,19 @@ Model complete
  l1cache_38.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_38.GetS_recv : Accumulator : Sum.u64 = 9796; SumSQ.u64 = 9796; Count.u64 = 9796; Min.u64 = 1; Max.u64 = 1; 
- l1cache_38.GetX_recv : Accumulator : Sum.u64 = 2379; SumSQ.u64 = 2379; Count.u64 = 2379; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_38.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_38.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_38.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_38.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_38.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
  l1cache_38.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_38.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_38.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_38.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_38.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.MSHR_occupancy : Accumulator : Sum.u64 = 351766; SumSQ.u64 = 6574908; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -15739,19 +15739,19 @@ Model complete
  l1cache_39.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_39.GetS_recv : Accumulator : Sum.u64 = 9941; SumSQ.u64 = 9941; Count.u64 = 9941; Min.u64 = 1; Max.u64 = 1; 
- l1cache_39.GetX_recv : Accumulator : Sum.u64 = 2955; SumSQ.u64 = 2955; Count.u64 = 2955; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_39.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_39.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_39.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_39.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
- l1cache_39.GetXResp_recv : Accumulator : Sum.u64 = 254; SumSQ.u64 = 254; Count.u64 = 254; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_39.GetSResp_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_39.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
  l1cache_39.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_39.FetchInvX_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_39.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l1cache_39.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.MSHR_occupancy : Accumulator : Sum.u64 = 346282; SumSQ.u64 = 6441290; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -16076,7 +16076,7 @@ Model complete
  l2cache_20.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_20.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_20.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_20.FetchInvX_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_20.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l2cache_20.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_20.FetchXResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l2cache_20.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -16220,19 +16220,19 @@ Model complete
  l1cache_40.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_40.GetS_recv : Accumulator : Sum.u64 = 9474; SumSQ.u64 = 9474; Count.u64 = 9474; Min.u64 = 1; Max.u64 = 1; 
- l1cache_40.GetX_recv : Accumulator : Sum.u64 = 2465; SumSQ.u64 = 2465; Count.u64 = 2465; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_40.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_40.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_40.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_40.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
- l1cache_40.GetXResp_recv : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_40.GetSResp_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_40.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
  l1cache_40.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_40.FetchInvX_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_40.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l1cache_40.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.MSHR_occupancy : Accumulator : Sum.u64 = 347589; SumSQ.u64 = 6445089; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -16390,19 +16390,19 @@ Model complete
  l1cache_41.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_41.GetS_recv : Accumulator : Sum.u64 = 9618; SumSQ.u64 = 9618; Count.u64 = 9618; Min.u64 = 1; Max.u64 = 1; 
- l1cache_41.GetX_recv : Accumulator : Sum.u64 = 2683; SumSQ.u64 = 2683; Count.u64 = 2683; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_41.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_41.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_41.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_41.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
- l1cache_41.GetXResp_recv : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_41.GetSResp_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_41.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
  l1cache_41.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_41.FetchInvX_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_41.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l1cache_41.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.MSHR_occupancy : Accumulator : Sum.u64 = 344920; SumSQ.u64 = 6376180; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -16727,7 +16727,7 @@ Model complete
  l2cache_21.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_21.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_21.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_21.FetchInvX_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_21.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
  l2cache_21.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_21.FetchXResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l2cache_21.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -16871,19 +16871,19 @@ Model complete
  l1cache_42.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_42.GetS_recv : Accumulator : Sum.u64 = 9479; SumSQ.u64 = 9479; Count.u64 = 9479; Min.u64 = 1; Max.u64 = 1; 
- l1cache_42.GetX_recv : Accumulator : Sum.u64 = 2760; SumSQ.u64 = 2760; Count.u64 = 2760; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_42.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_42.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_42.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_42.GetSResp_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
- l1cache_42.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_42.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_42.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_42.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_42.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_42.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_42.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.MSHR_occupancy : Accumulator : Sum.u64 = 348158; SumSQ.u64 = 6440322; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -17041,19 +17041,19 @@ Model complete
  l1cache_43.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_43.GetS_recv : Accumulator : Sum.u64 = 9494; SumSQ.u64 = 9494; Count.u64 = 9494; Min.u64 = 1; Max.u64 = 1; 
- l1cache_43.GetX_recv : Accumulator : Sum.u64 = 2342; SumSQ.u64 = 2342; Count.u64 = 2342; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_43.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_43.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_43.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_43.GetSResp_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
- l1cache_43.GetXResp_recv : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_43.GetSResp_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_43.GetXResp_recv : Accumulator : Sum.u64 = 254; SumSQ.u64 = 254; Count.u64 = 254; Min.u64 = 1; Max.u64 = 1; 
  l1cache_43.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_43.FetchInvX_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_43.FetchInvX_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_43.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.MSHR_occupancy : Accumulator : Sum.u64 = 348062; SumSQ.u64 = 6459326; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -17378,7 +17378,7 @@ Model complete
  l2cache_22.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_22.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_22.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_22.FetchInvX_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_22.FetchInvX_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
  l2cache_22.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_22.FetchXResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l2cache_22.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -17522,19 +17522,19 @@ Model complete
  l1cache_44.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_44.GetS_recv : Accumulator : Sum.u64 = 9496; SumSQ.u64 = 9496; Count.u64 = 9496; Min.u64 = 1; Max.u64 = 1; 
- l1cache_44.GetX_recv : Accumulator : Sum.u64 = 2382; SumSQ.u64 = 2382; Count.u64 = 2382; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_44.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_44.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_44.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_44.GetSResp_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
- l1cache_44.GetXResp_recv : Accumulator : Sum.u64 = 262; SumSQ.u64 = 262; Count.u64 = 262; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_44.GetSResp_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_44.GetXResp_recv : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; 
  l1cache_44.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_44.FetchInvX_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_44.FetchInvX_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
  l1cache_44.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.MSHR_occupancy : Accumulator : Sum.u64 = 353838; SumSQ.u64 = 6580546; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -17692,19 +17692,19 @@ Model complete
  l1cache_45.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_45.GetS_recv : Accumulator : Sum.u64 = 9991; SumSQ.u64 = 9991; Count.u64 = 9991; Min.u64 = 1; Max.u64 = 1; 
- l1cache_45.GetX_recv : Accumulator : Sum.u64 = 2523; SumSQ.u64 = 2523; Count.u64 = 2523; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_45.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_45.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_45.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_45.GetSResp_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
- l1cache_45.GetXResp_recv : Accumulator : Sum.u64 = 254; SumSQ.u64 = 254; Count.u64 = 254; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_45.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_45.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_45.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_45.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_45.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_45.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.MSHR_occupancy : Accumulator : Sum.u64 = 350270; SumSQ.u64 = 6526862; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -18052,7 +18052,7 @@ Model complete
  l2cache_23.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_23.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_23.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_23.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_23.FetchInvX_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l2cache_23.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_23.FetchXResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l2cache_23.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -18196,19 +18196,19 @@ Model complete
  l1cache_46.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_46.GetS_recv : Accumulator : Sum.u64 = 10681; SumSQ.u64 = 10681; Count.u64 = 10681; Min.u64 = 1; Max.u64 = 1; 
- l1cache_46.GetX_recv : Accumulator : Sum.u64 = 2803; SumSQ.u64 = 2803; Count.u64 = 2803; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_46.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_46.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_46.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_46.GetSResp_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
- l1cache_46.GetXResp_recv : Accumulator : Sum.u64 = 254; SumSQ.u64 = 254; Count.u64 = 254; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_46.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_46.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_46.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_46.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_46.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_46.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.MSHR_occupancy : Accumulator : Sum.u64 = 361214; SumSQ.u64 = 6831296; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -18366,19 +18366,19 @@ Model complete
  l1cache_47.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_47.GetS_recv : Accumulator : Sum.u64 = 10216; SumSQ.u64 = 10216; Count.u64 = 10216; Min.u64 = 1; Max.u64 = 1; 
- l1cache_47.GetX_recv : Accumulator : Sum.u64 = 2305; SumSQ.u64 = 2305; Count.u64 = 2305; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_47.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_47.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_47.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_47.GetSResp_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
- l1cache_47.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_47.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_47.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_47.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_47.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_47.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_47.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.MSHR_occupancy : Accumulator : Sum.u64 = 356390; SumSQ.u64 = 6733782; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -18703,7 +18703,7 @@ Model complete
  l2cache_24.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_24.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_24.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_24.FetchInvX_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_24.FetchInvX_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; 
  l2cache_24.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_24.FetchXResp_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; 
  l2cache_24.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -18847,19 +18847,19 @@ Model complete
  l1cache_48.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_48.GetS_recv : Accumulator : Sum.u64 = 10736; SumSQ.u64 = 10736; Count.u64 = 10736; Min.u64 = 1; Max.u64 = 1; 
- l1cache_48.GetX_recv : Accumulator : Sum.u64 = 3435; SumSQ.u64 = 3435; Count.u64 = 3435; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_48.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_48.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_48.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_48.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
- l1cache_48.GetXResp_recv : Accumulator : Sum.u64 = 258; SumSQ.u64 = 258; Count.u64 = 258; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_48.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_48.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_48.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_48.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_48.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_48.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.MSHR_occupancy : Accumulator : Sum.u64 = 351786; SumSQ.u64 = 6597708; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -19017,19 +19017,19 @@ Model complete
  l1cache_49.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_49.GetS_recv : Accumulator : Sum.u64 = 10678; SumSQ.u64 = 10678; Count.u64 = 10678; Min.u64 = 1; Max.u64 = 1; 
- l1cache_49.GetX_recv : Accumulator : Sum.u64 = 2158; SumSQ.u64 = 2158; Count.u64 = 2158; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_49.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_49.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_49.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_49.GetSResp_recv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; 
- l1cache_49.GetXResp_recv : Accumulator : Sum.u64 = 292; SumSQ.u64 = 292; Count.u64 = 292; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_49.GetSResp_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_49.GetXResp_recv : Accumulator : Sum.u64 = 291; SumSQ.u64 = 291; Count.u64 = 291; Min.u64 = 1; Max.u64 = 1; 
  l1cache_49.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_49.FetchInvX_recv : Accumulator : Sum.u64 = 326; SumSQ.u64 = 326; Count.u64 = 326; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_49.FetchInvX_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; 
  l1cache_49.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.MSHR_occupancy : Accumulator : Sum.u64 = 363966; SumSQ.u64 = 6917936; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -19338,7 +19338,7 @@ Model complete
  l2cache_25.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_25.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_25.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_25.GetS_recv : Accumulator : Sum.u64 = 1244; SumSQ.u64 = 1244; Count.u64 = 1244; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_25.GetS_recv : Accumulator : Sum.u64 = 1243; SumSQ.u64 = 1243; Count.u64 = 1243; Min.u64 = 1; Max.u64 = 1; 
  l2cache_25.GetX_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l2cache_25.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_25.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -19354,7 +19354,7 @@ Model complete
  l2cache_25.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_25.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_25.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_25.FetchInvX_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_25.FetchInvX_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l2cache_25.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_25.FetchXResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l2cache_25.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -19498,19 +19498,19 @@ Model complete
  l1cache_50.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_50.GetS_recv : Accumulator : Sum.u64 = 9320; SumSQ.u64 = 9320; Count.u64 = 9320; Min.u64 = 1; Max.u64 = 1; 
- l1cache_50.GetX_recv : Accumulator : Sum.u64 = 2071; SumSQ.u64 = 2071; Count.u64 = 2071; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_50.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_50.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_50.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_50.GetSResp_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
- l1cache_50.GetXResp_recv : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_50.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_50.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_50.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_50.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_50.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_50.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.MSHR_occupancy : Accumulator : Sum.u64 = 348277; SumSQ.u64 = 6466315; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -19668,13 +19668,13 @@ Model complete
  l1cache_51.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_51.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_51.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_51.GetS_recv : Accumulator : Sum.u64 = 9333; SumSQ.u64 = 9333; Count.u64 = 9333; Min.u64 = 1; Max.u64 = 1; 
- l1cache_51.GetX_recv : Accumulator : Sum.u64 = 2972; SumSQ.u64 = 2972; Count.u64 = 2972; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_51.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_51.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_51.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_51.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_51.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_51.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
- l1cache_51.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_51.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_51.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_51.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_51.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -19989,7 +19989,7 @@ Model complete
  l2cache_26.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_26.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_26.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_26.GetS_recv : Accumulator : Sum.u64 = 1238; SumSQ.u64 = 1238; Count.u64 = 1238; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_26.GetS_recv : Accumulator : Sum.u64 = 1237; SumSQ.u64 = 1237; Count.u64 = 1237; Min.u64 = 1; Max.u64 = 1; 
  l2cache_26.GetX_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l2cache_26.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_26.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -20005,7 +20005,7 @@ Model complete
  l2cache_26.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_26.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_26.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_26.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_26.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l2cache_26.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_26.FetchXResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l2cache_26.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -20149,19 +20149,19 @@ Model complete
  l1cache_52.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_52.GetS_recv : Accumulator : Sum.u64 = 9026; SumSQ.u64 = 9026; Count.u64 = 9026; Min.u64 = 1; Max.u64 = 1; 
- l1cache_52.GetX_recv : Accumulator : Sum.u64 = 2716; SumSQ.u64 = 2716; Count.u64 = 2716; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_52.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_52.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_52.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_52.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_52.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
  l1cache_52.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_52.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_52.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_52.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_52.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.MSHR_occupancy : Accumulator : Sum.u64 = 365748; SumSQ.u64 = 6729480; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -20319,13 +20319,13 @@ Model complete
  l1cache_53.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_53.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_53.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_53.GetS_recv : Accumulator : Sum.u64 = 9146; SumSQ.u64 = 9146; Count.u64 = 9146; Min.u64 = 1; Max.u64 = 1; 
- l1cache_53.GetX_recv : Accumulator : Sum.u64 = 3249; SumSQ.u64 = 3249; Count.u64 = 3249; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_53.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_53.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_53.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_53.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_53.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_53.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
- l1cache_53.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_53.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_53.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_53.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_53.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_53.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -20656,7 +20656,7 @@ Model complete
  l2cache_27.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_27.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_27.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_27.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_27.FetchInvX_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l2cache_27.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_27.FetchXResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l2cache_27.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -20800,19 +20800,19 @@ Model complete
  l1cache_54.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_54.GetS_recv : Accumulator : Sum.u64 = 9256; SumSQ.u64 = 9256; Count.u64 = 9256; Min.u64 = 1; Max.u64 = 1; 
- l1cache_54.GetX_recv : Accumulator : Sum.u64 = 3244; SumSQ.u64 = 3244; Count.u64 = 3244; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_54.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_54.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_54.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_54.GetSResp_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
- l1cache_54.GetXResp_recv : Accumulator : Sum.u64 = 254; SumSQ.u64 = 254; Count.u64 = 254; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_54.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_54.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_54.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_54.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_54.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_54.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.MSHR_occupancy : Accumulator : Sum.u64 = 368868; SumSQ.u64 = 6742002; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -20970,19 +20970,19 @@ Model complete
  l1cache_55.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_55.GetS_recv : Accumulator : Sum.u64 = 9501; SumSQ.u64 = 9501; Count.u64 = 9501; Min.u64 = 1; Max.u64 = 1; 
- l1cache_55.GetX_recv : Accumulator : Sum.u64 = 3573; SumSQ.u64 = 3573; Count.u64 = 3573; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_55.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_55.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_55.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_55.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
- l1cache_55.GetXResp_recv : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_55.GetSResp_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_55.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
  l1cache_55.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_55.FetchInvX_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_55.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l1cache_55.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.MSHR_occupancy : Accumulator : Sum.u64 = 367825; SumSQ.u64 = 6713487; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -21307,7 +21307,7 @@ Model complete
  l2cache_28.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_28.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_28.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_28.FetchInvX_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_28.FetchInvX_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l2cache_28.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_28.FetchXResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l2cache_28.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -21451,19 +21451,19 @@ Model complete
  l1cache_56.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_56.GetS_recv : Accumulator : Sum.u64 = 9008; SumSQ.u64 = 9008; Count.u64 = 9008; Min.u64 = 1; Max.u64 = 1; 
- l1cache_56.GetX_recv : Accumulator : Sum.u64 = 2629; SumSQ.u64 = 2629; Count.u64 = 2629; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_56.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_56.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_56.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_56.GetSResp_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
- l1cache_56.GetXResp_recv : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_56.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_56.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_56.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_56.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_56.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_56.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.MSHR_occupancy : Accumulator : Sum.u64 = 372712; SumSQ.u64 = 6845444; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -21621,19 +21621,19 @@ Model complete
  l1cache_57.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_57.GetS_recv : Accumulator : Sum.u64 = 9299; SumSQ.u64 = 9299; Count.u64 = 9299; Min.u64 = 1; Max.u64 = 1; 
- l1cache_57.GetX_recv : Accumulator : Sum.u64 = 3270; SumSQ.u64 = 3270; Count.u64 = 3270; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_57.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_57.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_57.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_57.GetSResp_recv : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; 
- l1cache_57.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_57.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_57.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_57.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_57.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_57.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_57.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.MSHR_occupancy : Accumulator : Sum.u64 = 374376; SumSQ.u64 = 6840844; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -21958,7 +21958,7 @@ Model complete
  l2cache_29.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_29.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_29.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_29.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_29.FetchInvX_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l2cache_29.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_29.FetchXResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l2cache_29.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -22102,19 +22102,19 @@ Model complete
  l1cache_58.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_58.GetS_recv : Accumulator : Sum.u64 = 9709; SumSQ.u64 = 9709; Count.u64 = 9709; Min.u64 = 1; Max.u64 = 1; 
- l1cache_58.GetX_recv : Accumulator : Sum.u64 = 2931; SumSQ.u64 = 2931; Count.u64 = 2931; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_58.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_58.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_58.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_58.GetSResp_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_58.GetSResp_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
  l1cache_58.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
  l1cache_58.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_58.FetchInvX_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_58.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l1cache_58.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.MSHR_occupancy : Accumulator : Sum.u64 = 384368; SumSQ.u64 = 7135460; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -22272,19 +22272,19 @@ Model complete
  l1cache_59.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_59.GetS_recv : Accumulator : Sum.u64 = 9813; SumSQ.u64 = 9813; Count.u64 = 9813; Min.u64 = 1; Max.u64 = 1; 
- l1cache_59.GetX_recv : Accumulator : Sum.u64 = 2956; SumSQ.u64 = 2956; Count.u64 = 2956; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_59.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_59.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_59.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_59.GetSResp_recv : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; 
- l1cache_59.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_59.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_59.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_59.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_59.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_59.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_59.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.MSHR_occupancy : Accumulator : Sum.u64 = 381850; SumSQ.u64 = 7118180; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -22780,12 +22780,12 @@ Model complete
  l1cache_60.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_60.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_60.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_60.GetS_recv : Accumulator : Sum.u64 = 9981; SumSQ.u64 = 9981; Count.u64 = 9981; Min.u64 = 1; Max.u64 = 1; 
- l1cache_60.GetX_recv : Accumulator : Sum.u64 = 3409; SumSQ.u64 = 3409; Count.u64 = 3409; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_60.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_60.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_60.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_60.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_60.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_60.GetSResp_recv : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_60.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l1cache_60.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_60.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_60.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -22950,13 +22950,13 @@ Model complete
  l1cache_61.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_61.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_61.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_61.GetS_recv : Accumulator : Sum.u64 = 9770; SumSQ.u64 = 9770; Count.u64 = 9770; Min.u64 = 1; Max.u64 = 1; 
- l1cache_61.GetX_recv : Accumulator : Sum.u64 = 2870; SumSQ.u64 = 2870; Count.u64 = 2870; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_61.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_61.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_61.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_61.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_61.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_61.GetSResp_recv : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; 
- l1cache_61.GetXResp_recv : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_61.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_61.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_61.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_61.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_61.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -23314,7 +23314,7 @@ Model complete
  l2cache_31.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_31.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_31.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_31.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_31.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l2cache_31.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_31.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_31.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -23458,13 +23458,13 @@ Model complete
  l1cache_62.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_62.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_62.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_62.GetS_recv : Accumulator : Sum.u64 = 9200; SumSQ.u64 = 9200; Count.u64 = 9200; Min.u64 = 1; Max.u64 = 1; 
- l1cache_62.GetX_recv : Accumulator : Sum.u64 = 2921; SumSQ.u64 = 2921; Count.u64 = 2921; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_62.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_62.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_62.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_62.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_62.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_62.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
- l1cache_62.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_62.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_62.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_62.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_62.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_62.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -23628,13 +23628,13 @@ Model complete
  l1cache_63.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_63.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_63.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_63.GetS_recv : Accumulator : Sum.u64 = 9306; SumSQ.u64 = 9306; Count.u64 = 9306; Min.u64 = 1; Max.u64 = 1; 
- l1cache_63.GetX_recv : Accumulator : Sum.u64 = 3037; SumSQ.u64 = 3037; Count.u64 = 3037; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_63.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_63.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_63.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_63.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_63.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_63.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
- l1cache_63.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_63.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_63.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_63.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_63.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_63.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -24109,12 +24109,12 @@ Model complete
  l1cache_64.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_64.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_64.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_64.GetS_recv : Accumulator : Sum.u64 = 9301; SumSQ.u64 = 9301; Count.u64 = 9301; Min.u64 = 1; Max.u64 = 1; 
- l1cache_64.GetX_recv : Accumulator : Sum.u64 = 3129; SumSQ.u64 = 3129; Count.u64 = 3129; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_64.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_64.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_64.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_64.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_64.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_64.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_64.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l1cache_64.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_64.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_64.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -24279,12 +24279,12 @@ Model complete
  l1cache_65.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_65.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_65.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_65.GetS_recv : Accumulator : Sum.u64 = 9226; SumSQ.u64 = 9226; Count.u64 = 9226; Min.u64 = 1; Max.u64 = 1; 
- l1cache_65.GetX_recv : Accumulator : Sum.u64 = 3000; SumSQ.u64 = 3000; Count.u64 = 3000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_65.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_65.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_65.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_65.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_65.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_65.GetSResp_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_65.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l1cache_65.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_65.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_65.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -24600,7 +24600,7 @@ Model complete
  l2cache_33.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_33.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_33.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_33.GetS_recv : Accumulator : Sum.u64 = 1239; SumSQ.u64 = 1239; Count.u64 = 1239; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_33.GetS_recv : Accumulator : Sum.u64 = 1235; SumSQ.u64 = 1235; Count.u64 = 1235; Min.u64 = 1; Max.u64 = 1; 
  l2cache_33.GetX_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l2cache_33.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_33.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -24760,13 +24760,13 @@ Model complete
  l1cache_66.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_66.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_66.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_66.GetS_recv : Accumulator : Sum.u64 = 9277; SumSQ.u64 = 9277; Count.u64 = 9277; Min.u64 = 1; Max.u64 = 1; 
- l1cache_66.GetX_recv : Accumulator : Sum.u64 = 2992; SumSQ.u64 = 2992; Count.u64 = 2992; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_66.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_66.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_66.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_66.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_66.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_66.GetSResp_recv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; 
- l1cache_66.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_66.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_66.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_66.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_66.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_66.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -24930,13 +24930,13 @@ Model complete
  l1cache_67.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_67.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_67.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_67.GetS_recv : Accumulator : Sum.u64 = 9089; SumSQ.u64 = 9089; Count.u64 = 9089; Min.u64 = 1; Max.u64 = 1; 
- l1cache_67.GetX_recv : Accumulator : Sum.u64 = 2815; SumSQ.u64 = 2815; Count.u64 = 2815; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_67.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_67.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_67.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_67.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_67.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_67.GetSResp_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
- l1cache_67.GetXResp_recv : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_67.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_67.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_67.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_67.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_67.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -25438,13 +25438,13 @@ Model complete
  l1cache_68.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_68.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_68.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_68.GetS_recv : Accumulator : Sum.u64 = 9306; SumSQ.u64 = 9306; Count.u64 = 9306; Min.u64 = 1; Max.u64 = 1; 
- l1cache_68.GetX_recv : Accumulator : Sum.u64 = 2911; SumSQ.u64 = 2911; Count.u64 = 2911; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_68.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_68.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_68.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_68.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_68.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_68.GetSResp_recv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; 
- l1cache_68.GetXResp_recv : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_68.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_68.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_68.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_68.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_68.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -25608,12 +25608,12 @@ Model complete
  l1cache_69.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_69.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_69.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_69.GetS_recv : Accumulator : Sum.u64 = 8803; SumSQ.u64 = 8803; Count.u64 = 8803; Min.u64 = 1; Max.u64 = 1; 
- l1cache_69.GetX_recv : Accumulator : Sum.u64 = 2262; SumSQ.u64 = 2262; Count.u64 = 2262; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_69.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_69.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_69.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_69.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_69.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_69.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_69.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l1cache_69.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_69.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_69.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -26116,13 +26116,13 @@ Model complete
  l1cache_70.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_70.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_70.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_70.GetS_recv : Accumulator : Sum.u64 = 9841; SumSQ.u64 = 9841; Count.u64 = 9841; Min.u64 = 1; Max.u64 = 1; 
- l1cache_70.GetX_recv : Accumulator : Sum.u64 = 2814; SumSQ.u64 = 2814; Count.u64 = 2814; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_70.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_70.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_70.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_70.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_70.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_70.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
- l1cache_70.GetXResp_recv : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_70.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_70.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_70.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_70.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_70.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -26286,13 +26286,13 @@ Model complete
  l1cache_71.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_71.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_71.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_71.GetS_recv : Accumulator : Sum.u64 = 9570; SumSQ.u64 = 9570; Count.u64 = 9570; Min.u64 = 1; Max.u64 = 1; 
- l1cache_71.GetX_recv : Accumulator : Sum.u64 = 2652; SumSQ.u64 = 2652; Count.u64 = 2652; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_71.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_71.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_71.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_71.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_71.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_71.GetSResp_recv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; 
- l1cache_71.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_71.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_71.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_71.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_71.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_71.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_MemoryCache_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_MemoryCache_MC.out
index a7557c803..d28131c7c 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_MemoryCache_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_MemoryCache_MC.out
@@ -2856,11 +2856,11 @@ Model complete
  l2cache_0.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_0.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_0.Inv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_0.Inv_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
  l2cache_0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_0.FetchInv_recv : Accumulator : Sum.u64 = 478; SumSQ.u64 = 478; Count.u64 = 478; Min.u64 = 1; Max.u64 = 1; 
- l2cache_0.FetchInvX_recv : Accumulator : Sum.u64 = 455; SumSQ.u64 = 455; Count.u64 = 455; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_0.FetchInv_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_0.FetchInvX_recv : Accumulator : Sum.u64 = 213; SumSQ.u64 = 213; Count.u64 = 213; Min.u64 = 1; Max.u64 = 1; 
  l2cache_0.FetchResp_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; 
  l2cache_0.FetchXResp_recv : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; 
  l2cache_0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3004,19 +3004,19 @@ Model complete
  l1cache_0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_0.GetS_recv : Accumulator : Sum.u64 = 21079; SumSQ.u64 = 21079; Count.u64 = 21079; Min.u64 = 1; Max.u64 = 1; 
- l1cache_0.GetX_recv : Accumulator : Sum.u64 = 4691; SumSQ.u64 = 4691; Count.u64 = 4691; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_0.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_0.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_0.GetSResp_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; 
- l1cache_0.GetXResp_recv : Accumulator : Sum.u64 = 369; SumSQ.u64 = 369; Count.u64 = 369; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_0.GetSResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_0.GetXResp_recv : Accumulator : Sum.u64 = 365; SumSQ.u64 = 365; Count.u64 = 365; Min.u64 = 1; Max.u64 = 1; 
  l1cache_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l1cache_0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.FetchInv_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
- l1cache_0.FetchInvX_recv : Accumulator : Sum.u64 = 767; SumSQ.u64 = 767; Count.u64 = 767; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_0.FetchInvX_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; 
  l1cache_0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_0.MSHR_occupancy : Accumulator : Sum.u64 = 420962; SumSQ.u64 = 9258030; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -3174,19 +3174,19 @@ Model complete
  l1cache_1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_1.GetS_recv : Accumulator : Sum.u64 = 21326; SumSQ.u64 = 21326; Count.u64 = 21326; Min.u64 = 1; Max.u64 = 1; 
- l1cache_1.GetX_recv : Accumulator : Sum.u64 = 5477; SumSQ.u64 = 5477; Count.u64 = 5477; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_1.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_1.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_1.GetSResp_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_1.GetSResp_recv : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; 
  l1cache_1.GetXResp_recv : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; 
  l1cache_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l1cache_1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_1.FetchInv_recv : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; 
- l1cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 443; SumSQ.u64 = 443; Count.u64 = 443; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_1.FetchInv_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; 
  l1cache_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.MSHR_occupancy : Accumulator : Sum.u64 = 432583; SumSQ.u64 = 9459335; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -3534,11 +3534,11 @@ Model complete
  l2cache_1.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_1.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_1.Inv_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_1.Inv_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
  l2cache_1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_1.FetchInv_recv : Accumulator : Sum.u64 = 480; SumSQ.u64 = 480; Count.u64 = 480; Min.u64 = 1; Max.u64 = 1; 
- l2cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 540; SumSQ.u64 = 540; Count.u64 = 540; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_1.FetchInv_recv : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 254; SumSQ.u64 = 254; Count.u64 = 254; Min.u64 = 1; Max.u64 = 1; 
  l2cache_1.FetchResp_recv : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; 
  l2cache_1.FetchXResp_recv : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; 
  l2cache_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3682,19 +3682,19 @@ Model complete
  l1cache_2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_2.GetS_recv : Accumulator : Sum.u64 = 21222; SumSQ.u64 = 21222; Count.u64 = 21222; Min.u64 = 1; Max.u64 = 1; 
- l1cache_2.GetX_recv : Accumulator : Sum.u64 = 5656; SumSQ.u64 = 5656; Count.u64 = 5656; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_2.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_2.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_2.GetSResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_2.GetSResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
  l1cache_2.GetXResp_recv : Accumulator : Sum.u64 = 362; SumSQ.u64 = 362; Count.u64 = 362; Min.u64 = 1; Max.u64 = 1; 
  l1cache_2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.Inv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l1cache_2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.FetchInv_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
- l1cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 877; SumSQ.u64 = 877; Count.u64 = 877; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; 
  l1cache_2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.MSHR_occupancy : Accumulator : Sum.u64 = 421448; SumSQ.u64 = 9191218; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -3852,19 +3852,19 @@ Model complete
  l1cache_3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_3.GetS_recv : Accumulator : Sum.u64 = 22456; SumSQ.u64 = 22456; Count.u64 = 22456; Min.u64 = 1; Max.u64 = 1; 
- l1cache_3.GetX_recv : Accumulator : Sum.u64 = 7198; SumSQ.u64 = 7198; Count.u64 = 7198; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_3.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_3.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_3.GetSResp_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
- l1cache_3.GetXResp_recv : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_3.GetSResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_3.GetXResp_recv : Accumulator : Sum.u64 = 362; SumSQ.u64 = 362; Count.u64 = 362; Min.u64 = 1; Max.u64 = 1; 
  l1cache_3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.Inv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l1cache_3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.FetchInv_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
- l1cache_3.FetchInvX_recv : Accumulator : Sum.u64 = 788; SumSQ.u64 = 788; Count.u64 = 788; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_3.FetchInvX_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; 
  l1cache_3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_3.MSHR_occupancy : Accumulator : Sum.u64 = 415145; SumSQ.u64 = 9024217; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -4185,11 +4185,11 @@ Model complete
  l2cache_2.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_2.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_2.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_2.Inv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_2.Inv_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
  l2cache_2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_2.FetchInv_recv : Accumulator : Sum.u64 = 484; SumSQ.u64 = 484; Count.u64 = 484; Min.u64 = 1; Max.u64 = 1; 
- l2cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 554; SumSQ.u64 = 554; Count.u64 = 554; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_2.FetchInv_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l2cache_2.FetchResp_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
  l2cache_2.FetchXResp_recv : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; 
  l2cache_2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -4333,19 +4333,19 @@ Model complete
  l1cache_4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_4.GetS_recv : Accumulator : Sum.u64 = 21224; SumSQ.u64 = 21224; Count.u64 = 21224; Min.u64 = 1; Max.u64 = 1; 
- l1cache_4.GetX_recv : Accumulator : Sum.u64 = 5580; SumSQ.u64 = 5580; Count.u64 = 5580; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_4.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_4.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_4.GetSResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
- l1cache_4.GetXResp_recv : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_4.GetSResp_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_4.GetXResp_recv : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; 
  l1cache_4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_4.FetchInvX_recv : Accumulator : Sum.u64 = 865; SumSQ.u64 = 865; Count.u64 = 865; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_4.FetchInvX_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; 
  l1cache_4.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_4.MSHR_occupancy : Accumulator : Sum.u64 = 418352; SumSQ.u64 = 9151918; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -4503,19 +4503,19 @@ Model complete
  l1cache_5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_5.GetS_recv : Accumulator : Sum.u64 = 21539; SumSQ.u64 = 21539; Count.u64 = 21539; Min.u64 = 1; Max.u64 = 1; 
- l1cache_5.GetX_recv : Accumulator : Sum.u64 = 5364; SumSQ.u64 = 5364; Count.u64 = 5364; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_5.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_5.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_5.GetSResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
- l1cache_5.GetXResp_recv : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_5.GetSResp_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_5.GetXResp_recv : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; 
  l1cache_5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_5.FetchInvX_recv : Accumulator : Sum.u64 = 868; SumSQ.u64 = 868; Count.u64 = 868; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_5.FetchInvX_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; 
  l1cache_5.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_5.MSHR_occupancy : Accumulator : Sum.u64 = 420979; SumSQ.u64 = 9255399; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -4836,11 +4836,11 @@ Model complete
  l2cache_3.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_3.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_3.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_3.Inv_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_3.Inv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l2cache_3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_3.FetchInv_recv : Accumulator : Sum.u64 = 486; SumSQ.u64 = 486; Count.u64 = 486; Min.u64 = 1; Max.u64 = 1; 
- l2cache_3.FetchInvX_recv : Accumulator : Sum.u64 = 541; SumSQ.u64 = 541; Count.u64 = 541; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_3.FetchInv_recv : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_3.FetchInvX_recv : Accumulator : Sum.u64 = 248; SumSQ.u64 = 248; Count.u64 = 248; Min.u64 = 1; Max.u64 = 1; 
  l2cache_3.FetchResp_recv : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; 
  l2cache_3.FetchXResp_recv : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; 
  l2cache_3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -4984,19 +4984,19 @@ Model complete
  l1cache_6.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_6.GetS_recv : Accumulator : Sum.u64 = 21467; SumSQ.u64 = 21467; Count.u64 = 21467; Min.u64 = 1; Max.u64 = 1; 
- l1cache_6.GetX_recv : Accumulator : Sum.u64 = 5807; SumSQ.u64 = 5807; Count.u64 = 5807; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_6.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_6.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_6.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_6.GetSResp_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; 
- l1cache_6.GetXResp_recv : Accumulator : Sum.u64 = 367; SumSQ.u64 = 367; Count.u64 = 367; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_6.GetSResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_6.GetXResp_recv : Accumulator : Sum.u64 = 365; SumSQ.u64 = 365; Count.u64 = 365; Min.u64 = 1; Max.u64 = 1; 
  l1cache_6.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_6.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_6.FetchInvX_recv : Accumulator : Sum.u64 = 786; SumSQ.u64 = 786; Count.u64 = 786; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_6.FetchInvX_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
  l1cache_6.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_6.MSHR_occupancy : Accumulator : Sum.u64 = 422135; SumSQ.u64 = 9248329; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -5154,19 +5154,19 @@ Model complete
  l1cache_7.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_7.GetS_recv : Accumulator : Sum.u64 = 21764; SumSQ.u64 = 21764; Count.u64 = 21764; Min.u64 = 1; Max.u64 = 1; 
- l1cache_7.GetX_recv : Accumulator : Sum.u64 = 5546; SumSQ.u64 = 5546; Count.u64 = 5546; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_7.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_7.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_7.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_7.GetSResp_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
- l1cache_7.GetXResp_recv : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_7.GetSResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_7.GetXResp_recv : Accumulator : Sum.u64 = 362; SumSQ.u64 = 362; Count.u64 = 362; Min.u64 = 1; Max.u64 = 1; 
  l1cache_7.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.Inv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l1cache_7.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.FetchInv_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; 
- l1cache_7.FetchInvX_recv : Accumulator : Sum.u64 = 844; SumSQ.u64 = 844; Count.u64 = 844; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_7.FetchInvX_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; 
  l1cache_7.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_7.MSHR_occupancy : Accumulator : Sum.u64 = 420619; SumSQ.u64 = 9226305; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -5514,11 +5514,11 @@ Model complete
  l2cache_4.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_4.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_4.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_4.Inv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_4.Inv_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l2cache_4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_4.FetchInv_recv : Accumulator : Sum.u64 = 499; SumSQ.u64 = 499; Count.u64 = 499; Min.u64 = 1; Max.u64 = 1; 
- l2cache_4.FetchInvX_recv : Accumulator : Sum.u64 = 515; SumSQ.u64 = 515; Count.u64 = 515; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_4.FetchInv_recv : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_4.FetchInvX_recv : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; 
  l2cache_4.FetchResp_recv : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; 
  l2cache_4.FetchXResp_recv : Accumulator : Sum.u64 = 227; SumSQ.u64 = 227; Count.u64 = 227; Min.u64 = 1; Max.u64 = 1; 
  l2cache_4.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -5662,19 +5662,19 @@ Model complete
  l1cache_8.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_8.GetS_recv : Accumulator : Sum.u64 = 21100; SumSQ.u64 = 21100; Count.u64 = 21100; Min.u64 = 1; Max.u64 = 1; 
- l1cache_8.GetX_recv : Accumulator : Sum.u64 = 4987; SumSQ.u64 = 4987; Count.u64 = 4987; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_8.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_8.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_8.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.GetSResp_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
- l1cache_8.GetXResp_recv : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_8.GetXResp_recv : Accumulator : Sum.u64 = 360; SumSQ.u64 = 360; Count.u64 = 360; Min.u64 = 1; Max.u64 = 1; 
  l1cache_8.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.Inv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_8.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.FetchInv_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
- l1cache_8.FetchInvX_recv : Accumulator : Sum.u64 = 822; SumSQ.u64 = 822; Count.u64 = 822; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_8.FetchInvX_recv : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; 
  l1cache_8.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_8.MSHR_occupancy : Accumulator : Sum.u64 = 425811; SumSQ.u64 = 9322747; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -5832,8 +5832,8 @@ Model complete
  l1cache_9.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_9.GetS_recv : Accumulator : Sum.u64 = 21423; SumSQ.u64 = 21423; Count.u64 = 21423; Min.u64 = 1; Max.u64 = 1; 
- l1cache_9.GetX_recv : Accumulator : Sum.u64 = 6851; SumSQ.u64 = 6851; Count.u64 = 6851; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_9.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_9.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_9.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -5843,8 +5843,8 @@ Model complete
  l1cache_9.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_9.FetchInv_recv : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; 
- l1cache_9.FetchInvX_recv : Accumulator : Sum.u64 = 887; SumSQ.u64 = 887; Count.u64 = 887; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_9.FetchInv_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_9.FetchInvX_recv : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; 
  l1cache_9.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_9.MSHR_occupancy : Accumulator : Sum.u64 = 417187; SumSQ.u64 = 9066599; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -6192,11 +6192,11 @@ Model complete
  l2cache_5.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_5.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_5.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_5.Inv_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_5.Inv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l2cache_5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_5.FetchInv_recv : Accumulator : Sum.u64 = 486; SumSQ.u64 = 486; Count.u64 = 486; Min.u64 = 1; Max.u64 = 1; 
- l2cache_5.FetchInvX_recv : Accumulator : Sum.u64 = 550; SumSQ.u64 = 550; Count.u64 = 550; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_5.FetchInv_recv : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_5.FetchInvX_recv : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; 
  l2cache_5.FetchResp_recv : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; 
  l2cache_5.FetchXResp_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; 
  l2cache_5.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -6340,19 +6340,19 @@ Model complete
  l1cache_10.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_10.GetS_recv : Accumulator : Sum.u64 = 21826; SumSQ.u64 = 21826; Count.u64 = 21826; Min.u64 = 1; Max.u64 = 1; 
- l1cache_10.GetX_recv : Accumulator : Sum.u64 = 5469; SumSQ.u64 = 5469; Count.u64 = 5469; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_10.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_10.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_10.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_10.GetSResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
- l1cache_10.GetXResp_recv : Accumulator : Sum.u64 = 368; SumSQ.u64 = 368; Count.u64 = 368; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_10.GetSResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_10.GetXResp_recv : Accumulator : Sum.u64 = 366; SumSQ.u64 = 366; Count.u64 = 366; Min.u64 = 1; Max.u64 = 1; 
  l1cache_10.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.Inv_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l1cache_10.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.FetchInv_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
- l1cache_10.FetchInvX_recv : Accumulator : Sum.u64 = 878; SumSQ.u64 = 878; Count.u64 = 878; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_10.FetchInvX_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
  l1cache_10.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_10.MSHR_occupancy : Accumulator : Sum.u64 = 430279; SumSQ.u64 = 9451261; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -6510,19 +6510,19 @@ Model complete
  l1cache_11.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_11.GetS_recv : Accumulator : Sum.u64 = 22328; SumSQ.u64 = 22328; Count.u64 = 22328; Min.u64 = 1; Max.u64 = 1; 
- l1cache_11.GetX_recv : Accumulator : Sum.u64 = 6515; SumSQ.u64 = 6515; Count.u64 = 6515; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_11.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_11.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_11.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_11.GetSResp_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
- l1cache_11.GetXResp_recv : Accumulator : Sum.u64 = 368; SumSQ.u64 = 368; Count.u64 = 368; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_11.GetSResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_11.GetXResp_recv : Accumulator : Sum.u64 = 365; SumSQ.u64 = 365; Count.u64 = 365; Min.u64 = 1; Max.u64 = 1; 
  l1cache_11.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.Inv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l1cache_11.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.FetchInv_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
- l1cache_11.FetchInvX_recv : Accumulator : Sum.u64 = 825; SumSQ.u64 = 825; Count.u64 = 825; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_11.FetchInvX_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
  l1cache_11.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_11.MSHR_occupancy : Accumulator : Sum.u64 = 424342; SumSQ.u64 = 9296262; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -6866,11 +6866,11 @@ Model complete
  l2cache_6.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_6.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_6.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_6.Inv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_6.Inv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l2cache_6.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_6.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_6.FetchInv_recv : Accumulator : Sum.u64 = 489; SumSQ.u64 = 489; Count.u64 = 489; Min.u64 = 1; Max.u64 = 1; 
- l2cache_6.FetchInvX_recv : Accumulator : Sum.u64 = 433; SumSQ.u64 = 433; Count.u64 = 433; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_6.FetchInv_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_6.FetchInvX_recv : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; 
  l2cache_6.FetchResp_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
  l2cache_6.FetchXResp_recv : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; 
  l2cache_6.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -7014,19 +7014,19 @@ Model complete
  l1cache_12.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_12.GetS_recv : Accumulator : Sum.u64 = 21705; SumSQ.u64 = 21705; Count.u64 = 21705; Min.u64 = 1; Max.u64 = 1; 
- l1cache_12.GetX_recv : Accumulator : Sum.u64 = 5577; SumSQ.u64 = 5577; Count.u64 = 5577; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_12.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_12.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_12.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_12.GetSResp_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; 
- l1cache_12.GetXResp_recv : Accumulator : Sum.u64 = 368; SumSQ.u64 = 368; Count.u64 = 368; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_12.GetSResp_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_12.GetXResp_recv : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; 
  l1cache_12.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_12.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_12.FetchInvX_recv : Accumulator : Sum.u64 = 752; SumSQ.u64 = 752; Count.u64 = 752; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_12.FetchInvX_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
  l1cache_12.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_12.MSHR_occupancy : Accumulator : Sum.u64 = 420026; SumSQ.u64 = 9211310; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -7184,19 +7184,19 @@ Model complete
  l1cache_13.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_13.GetS_recv : Accumulator : Sum.u64 = 20396; SumSQ.u64 = 20396; Count.u64 = 20396; Min.u64 = 1; Max.u64 = 1; 
- l1cache_13.GetX_recv : Accumulator : Sum.u64 = 4616; SumSQ.u64 = 4616; Count.u64 = 4616; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_13.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_13.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_13.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_13.GetSResp_recv : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; 
- l1cache_13.GetXResp_recv : Accumulator : Sum.u64 = 327; SumSQ.u64 = 327; Count.u64 = 327; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_13.GetSResp_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_13.GetXResp_recv : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; 
  l1cache_13.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_13.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_13.FetchInv_recv : Accumulator : Sum.u64 = 213; SumSQ.u64 = 213; Count.u64 = 213; Min.u64 = 1; Max.u64 = 1; 
- l1cache_13.FetchInvX_recv : Accumulator : Sum.u64 = 539; SumSQ.u64 = 539; Count.u64 = 539; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_13.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_13.FetchInvX_recv : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; 
  l1cache_13.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_13.MSHR_occupancy : Accumulator : Sum.u64 = 429963; SumSQ.u64 = 9403687; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -7517,11 +7517,11 @@ Model complete
  l2cache_7.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_7.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_7.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_7.Inv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_7.Inv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
  l2cache_7.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_7.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_7.FetchInv_recv : Accumulator : Sum.u64 = 482; SumSQ.u64 = 482; Count.u64 = 482; Min.u64 = 1; Max.u64 = 1; 
- l2cache_7.FetchInvX_recv : Accumulator : Sum.u64 = 517; SumSQ.u64 = 517; Count.u64 = 517; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_7.FetchInv_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_7.FetchInvX_recv : Accumulator : Sum.u64 = 255; SumSQ.u64 = 255; Count.u64 = 255; Min.u64 = 1; Max.u64 = 1; 
  l2cache_7.FetchResp_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
  l2cache_7.FetchXResp_recv : Accumulator : Sum.u64 = 246; SumSQ.u64 = 246; Count.u64 = 246; Min.u64 = 1; Max.u64 = 1; 
  l2cache_7.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -7665,19 +7665,19 @@ Model complete
  l1cache_14.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_14.GetS_recv : Accumulator : Sum.u64 = 21844; SumSQ.u64 = 21844; Count.u64 = 21844; Min.u64 = 1; Max.u64 = 1; 
- l1cache_14.GetX_recv : Accumulator : Sum.u64 = 6187; SumSQ.u64 = 6187; Count.u64 = 6187; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_14.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_14.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_14.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_14.GetSResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
- l1cache_14.GetXResp_recv : Accumulator : Sum.u64 = 365; SumSQ.u64 = 365; Count.u64 = 365; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_14.GetSResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_14.GetXResp_recv : Accumulator : Sum.u64 = 362; SumSQ.u64 = 362; Count.u64 = 362; Min.u64 = 1; Max.u64 = 1; 
  l1cache_14.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.Inv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l1cache_14.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.FetchInv_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; 
- l1cache_14.FetchInvX_recv : Accumulator : Sum.u64 = 787; SumSQ.u64 = 787; Count.u64 = 787; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_14.FetchInvX_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
  l1cache_14.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_14.MSHR_occupancy : Accumulator : Sum.u64 = 414035; SumSQ.u64 = 9069337; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -7835,19 +7835,19 @@ Model complete
  l1cache_15.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_15.GetS_recv : Accumulator : Sum.u64 = 20937; SumSQ.u64 = 20937; Count.u64 = 20937; Min.u64 = 1; Max.u64 = 1; 
- l1cache_15.GetX_recv : Accumulator : Sum.u64 = 4987; SumSQ.u64 = 4987; Count.u64 = 4987; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_15.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_15.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_15.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_15.GetXResp_recv : Accumulator : Sum.u64 = 378; SumSQ.u64 = 378; Count.u64 = 378; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_15.GetXResp_recv : Accumulator : Sum.u64 = 375; SumSQ.u64 = 375; Count.u64 = 375; Min.u64 = 1; Max.u64 = 1; 
  l1cache_15.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.Inv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_15.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.FetchInv_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
- l1cache_15.FetchInvX_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_15.FetchInvX_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  l1cache_15.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_15.MSHR_occupancy : Accumulator : Sum.u64 = 426012; SumSQ.u64 = 9315566; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -8168,11 +8168,11 @@ Model complete
  l2cache_8.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_8.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_8.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_8.Inv_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_8.Inv_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
  l2cache_8.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_8.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_8.FetchInv_recv : Accumulator : Sum.u64 = 476; SumSQ.u64 = 476; Count.u64 = 476; Min.u64 = 1; Max.u64 = 1; 
- l2cache_8.FetchInvX_recv : Accumulator : Sum.u64 = 519; SumSQ.u64 = 519; Count.u64 = 519; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_8.FetchInv_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_8.FetchInvX_recv : Accumulator : Sum.u64 = 262; SumSQ.u64 = 262; Count.u64 = 262; Min.u64 = 1; Max.u64 = 1; 
  l2cache_8.FetchResp_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; 
  l2cache_8.FetchXResp_recv : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; 
  l2cache_8.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -8316,19 +8316,19 @@ Model complete
  l1cache_16.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_16.GetS_recv : Accumulator : Sum.u64 = 21627; SumSQ.u64 = 21627; Count.u64 = 21627; Min.u64 = 1; Max.u64 = 1; 
- l1cache_16.GetX_recv : Accumulator : Sum.u64 = 6444; SumSQ.u64 = 6444; Count.u64 = 6444; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_16.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_16.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_16.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_16.GetSResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
- l1cache_16.GetXResp_recv : Accumulator : Sum.u64 = 376; SumSQ.u64 = 376; Count.u64 = 376; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_16.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_16.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; 
  l1cache_16.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l1cache_16.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.FetchInv_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
- l1cache_16.FetchInvX_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_16.FetchInvX_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
  l1cache_16.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_16.MSHR_occupancy : Accumulator : Sum.u64 = 416365; SumSQ.u64 = 9068239; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -8486,19 +8486,19 @@ Model complete
  l1cache_17.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_17.GetS_recv : Accumulator : Sum.u64 = 20794; SumSQ.u64 = 20794; Count.u64 = 20794; Min.u64 = 1; Max.u64 = 1; 
- l1cache_17.GetX_recv : Accumulator : Sum.u64 = 5090; SumSQ.u64 = 5090; Count.u64 = 5090; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_17.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_17.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_17.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_17.GetSResp_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
- l1cache_17.GetXResp_recv : Accumulator : Sum.u64 = 376; SumSQ.u64 = 376; Count.u64 = 376; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_17.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_17.GetXResp_recv : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; 
  l1cache_17.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l1cache_17.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.FetchInv_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
- l1cache_17.FetchInvX_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_17.FetchInvX_recv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; 
  l1cache_17.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_17.MSHR_occupancy : Accumulator : Sum.u64 = 418846; SumSQ.u64 = 9144288; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -8819,11 +8819,11 @@ Model complete
  l2cache_9.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_9.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_9.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_9.Inv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_9.Inv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l2cache_9.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_9.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_9.FetchInv_recv : Accumulator : Sum.u64 = 484; SumSQ.u64 = 484; Count.u64 = 484; Min.u64 = 1; Max.u64 = 1; 
- l2cache_9.FetchInvX_recv : Accumulator : Sum.u64 = 502; SumSQ.u64 = 502; Count.u64 = 502; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_9.FetchInv_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_9.FetchInvX_recv : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; 
  l2cache_9.FetchResp_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
  l2cache_9.FetchXResp_recv : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; 
  l2cache_9.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -8967,19 +8967,19 @@ Model complete
  l1cache_18.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_18.GetS_recv : Accumulator : Sum.u64 = 21190; SumSQ.u64 = 21190; Count.u64 = 21190; Min.u64 = 1; Max.u64 = 1; 
- l1cache_18.GetX_recv : Accumulator : Sum.u64 = 6226; SumSQ.u64 = 6226; Count.u64 = 6226; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_18.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_18.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_18.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.GetSResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
- l1cache_18.GetXResp_recv : Accumulator : Sum.u64 = 380; SumSQ.u64 = 380; Count.u64 = 380; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_18.GetXResp_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; 
  l1cache_18.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.Inv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l1cache_18.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.FetchInv_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
- l1cache_18.FetchInvX_recv : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_18.FetchInvX_recv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; 
  l1cache_18.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_18.MSHR_occupancy : Accumulator : Sum.u64 = 412775; SumSQ.u64 = 8974385; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -9137,19 +9137,19 @@ Model complete
  l1cache_19.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_19.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_19.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_19.GetS_recv : Accumulator : Sum.u64 = 20865; SumSQ.u64 = 20865; Count.u64 = 20865; Min.u64 = 1; Max.u64 = 1; 
- l1cache_19.GetX_recv : Accumulator : Sum.u64 = 4570; SumSQ.u64 = 4570; Count.u64 = 4570; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_19.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_19.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_19.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_19.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_19.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_19.GetSResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
- l1cache_19.GetXResp_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_19.GetSResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_19.GetXResp_recv : Accumulator : Sum.u64 = 369; SumSQ.u64 = 369; Count.u64 = 369; Min.u64 = 1; Max.u64 = 1; 
  l1cache_19.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_19.Inv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l1cache_19.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_19.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_19.FetchInv_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; 
- l1cache_19.FetchInvX_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_19.FetchInvX_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; 
  l1cache_19.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_19.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_19.MSHR_occupancy : Accumulator : Sum.u64 = 422845; SumSQ.u64 = 9231557; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -9470,11 +9470,11 @@ Model complete
  l2cache_10.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_10.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_10.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_10.Inv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_10.Inv_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
  l2cache_10.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_10.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_10.FetchInv_recv : Accumulator : Sum.u64 = 482; SumSQ.u64 = 482; Count.u64 = 482; Min.u64 = 1; Max.u64 = 1; 
- l2cache_10.FetchInvX_recv : Accumulator : Sum.u64 = 509; SumSQ.u64 = 509; Count.u64 = 509; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_10.FetchInv_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_10.FetchInvX_recv : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; 
  l2cache_10.FetchResp_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
  l2cache_10.FetchXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l2cache_10.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -9618,19 +9618,19 @@ Model complete
  l1cache_20.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_20.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_20.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_20.GetS_recv : Accumulator : Sum.u64 = 21907; SumSQ.u64 = 21907; Count.u64 = 21907; Min.u64 = 1; Max.u64 = 1; 
- l1cache_20.GetX_recv : Accumulator : Sum.u64 = 5267; SumSQ.u64 = 5267; Count.u64 = 5267; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_20.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_20.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_20.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_20.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_20.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_20.GetSResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
- l1cache_20.GetXResp_recv : Accumulator : Sum.u64 = 380; SumSQ.u64 = 380; Count.u64 = 380; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_20.GetSResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_20.GetXResp_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; 
  l1cache_20.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_20.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_20.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_20.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_20.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_20.FetchInvX_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_20.FetchInvX_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  l1cache_20.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_20.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_20.MSHR_occupancy : Accumulator : Sum.u64 = 419331; SumSQ.u64 = 9177161; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -9788,19 +9788,19 @@ Model complete
  l1cache_21.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_21.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_21.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_21.GetS_recv : Accumulator : Sum.u64 = 22026; SumSQ.u64 = 22026; Count.u64 = 22026; Min.u64 = 1; Max.u64 = 1; 
- l1cache_21.GetX_recv : Accumulator : Sum.u64 = 6979; SumSQ.u64 = 6979; Count.u64 = 6979; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_21.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_21.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_21.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_21.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_21.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_21.GetSResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
- l1cache_21.GetXResp_recv : Accumulator : Sum.u64 = 375; SumSQ.u64 = 375; Count.u64 = 375; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_21.GetSResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_21.GetXResp_recv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; 
  l1cache_21.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_21.Inv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l1cache_21.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_21.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_21.FetchInv_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
- l1cache_21.FetchInvX_recv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_21.FetchInvX_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l1cache_21.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_21.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_21.MSHR_occupancy : Accumulator : Sum.u64 = 416441; SumSQ.u64 = 9085153; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -10144,11 +10144,11 @@ Model complete
  l2cache_11.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_11.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_11.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_11.Inv_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_11.Inv_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
  l2cache_11.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_11.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_11.FetchInv_recv : Accumulator : Sum.u64 = 476; SumSQ.u64 = 476; Count.u64 = 476; Min.u64 = 1; Max.u64 = 1; 
- l2cache_11.FetchInvX_recv : Accumulator : Sum.u64 = 509; SumSQ.u64 = 509; Count.u64 = 509; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_11.FetchInv_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_11.FetchInvX_recv : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; 
  l2cache_11.FetchResp_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; 
  l2cache_11.FetchXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
  l2cache_11.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -10292,13 +10292,13 @@ Model complete
  l1cache_22.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_22.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_22.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_22.GetS_recv : Accumulator : Sum.u64 = 21956; SumSQ.u64 = 21956; Count.u64 = 21956; Min.u64 = 1; Max.u64 = 1; 
- l1cache_22.GetX_recv : Accumulator : Sum.u64 = 6255; SumSQ.u64 = 6255; Count.u64 = 6255; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_22.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_22.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_22.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_22.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_22.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_22.GetSResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
- l1cache_22.GetXResp_recv : Accumulator : Sum.u64 = 375; SumSQ.u64 = 375; Count.u64 = 375; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_22.GetXResp_recv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; 
  l1cache_22.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_22.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l1cache_22.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -10462,19 +10462,19 @@ Model complete
  l1cache_23.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_23.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_23.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_23.GetS_recv : Accumulator : Sum.u64 = 20879; SumSQ.u64 = 20879; Count.u64 = 20879; Min.u64 = 1; Max.u64 = 1; 
- l1cache_23.GetX_recv : Accumulator : Sum.u64 = 5073; SumSQ.u64 = 5073; Count.u64 = 5073; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_23.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_23.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_23.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_23.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_23.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_23.GetSResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
- l1cache_23.GetXResp_recv : Accumulator : Sum.u64 = 374; SumSQ.u64 = 374; Count.u64 = 374; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_23.GetSResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_23.GetXResp_recv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; 
  l1cache_23.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_23.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l1cache_23.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_23.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_23.FetchInv_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
- l1cache_23.FetchInvX_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_23.FetchInvX_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  l1cache_23.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_23.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_23.MSHR_occupancy : Accumulator : Sum.u64 = 421039; SumSQ.u64 = 9205715; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -10818,11 +10818,11 @@ Model complete
  l2cache_12.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_12.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_12.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_12.Inv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_12.Inv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
  l2cache_12.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_12.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_12.FetchInv_recv : Accumulator : Sum.u64 = 482; SumSQ.u64 = 482; Count.u64 = 482; Min.u64 = 1; Max.u64 = 1; 
- l2cache_12.FetchInvX_recv : Accumulator : Sum.u64 = 515; SumSQ.u64 = 515; Count.u64 = 515; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_12.FetchInv_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_12.FetchInvX_recv : Accumulator : Sum.u64 = 259; SumSQ.u64 = 259; Count.u64 = 259; Min.u64 = 1; Max.u64 = 1; 
  l2cache_12.FetchResp_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
  l2cache_12.FetchXResp_recv : Accumulator : Sum.u64 = 255; SumSQ.u64 = 255; Count.u64 = 255; Min.u64 = 1; Max.u64 = 1; 
  l2cache_12.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -10966,19 +10966,19 @@ Model complete
  l1cache_24.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_24.GetS_recv : Accumulator : Sum.u64 = 20616; SumSQ.u64 = 20616; Count.u64 = 20616; Min.u64 = 1; Max.u64 = 1; 
- l1cache_24.GetX_recv : Accumulator : Sum.u64 = 4575; SumSQ.u64 = 4575; Count.u64 = 4575; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_24.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_24.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_24.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
- l1cache_24.GetXResp_recv : Accumulator : Sum.u64 = 376; SumSQ.u64 = 376; Count.u64 = 376; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_24.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; 
  l1cache_24.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l1cache_24.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.FetchInv_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; 
- l1cache_24.FetchInvX_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_24.FetchInvX_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
  l1cache_24.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_24.MSHR_occupancy : Accumulator : Sum.u64 = 426467; SumSQ.u64 = 9303395; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -11136,19 +11136,19 @@ Model complete
  l1cache_25.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_25.GetS_recv : Accumulator : Sum.u64 = 20226; SumSQ.u64 = 20226; Count.u64 = 20226; Min.u64 = 1; Max.u64 = 1; 
- l1cache_25.GetX_recv : Accumulator : Sum.u64 = 4428; SumSQ.u64 = 4428; Count.u64 = 4428; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_25.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_25.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_25.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
- l1cache_25.GetXResp_recv : Accumulator : Sum.u64 = 379; SumSQ.u64 = 379; Count.u64 = 379; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_25.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; 
  l1cache_25.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.Inv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l1cache_25.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.FetchInv_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; 
- l1cache_25.FetchInvX_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_25.FetchInvX_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  l1cache_25.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_25.MSHR_occupancy : Accumulator : Sum.u64 = 421428; SumSQ.u64 = 9205362; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -11469,11 +11469,11 @@ Model complete
  l2cache_13.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_13.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_13.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_13.Inv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_13.Inv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l2cache_13.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_13.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_13.FetchInv_recv : Accumulator : Sum.u64 = 484; SumSQ.u64 = 484; Count.u64 = 484; Min.u64 = 1; Max.u64 = 1; 
- l2cache_13.FetchInvX_recv : Accumulator : Sum.u64 = 510; SumSQ.u64 = 510; Count.u64 = 510; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_13.FetchInv_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_13.FetchInvX_recv : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; 
  l2cache_13.FetchResp_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
  l2cache_13.FetchXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
  l2cache_13.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -11617,19 +11617,19 @@ Model complete
  l1cache_26.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_26.GetS_recv : Accumulator : Sum.u64 = 21909; SumSQ.u64 = 21909; Count.u64 = 21909; Min.u64 = 1; Max.u64 = 1; 
- l1cache_26.GetX_recv : Accumulator : Sum.u64 = 7083; SumSQ.u64 = 7083; Count.u64 = 7083; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_26.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_26.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_26.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
- l1cache_26.GetXResp_recv : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_26.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; 
  l1cache_26.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_26.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_26.FetchInvX_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_26.FetchInvX_recv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; 
  l1cache_26.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_26.MSHR_occupancy : Accumulator : Sum.u64 = 413386; SumSQ.u64 = 8971880; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -11787,19 +11787,19 @@ Model complete
  l1cache_27.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_27.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_27.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_27.GetS_recv : Accumulator : Sum.u64 = 20962; SumSQ.u64 = 20962; Count.u64 = 20962; Min.u64 = 1; Max.u64 = 1; 
- l1cache_27.GetX_recv : Accumulator : Sum.u64 = 5401; SumSQ.u64 = 5401; Count.u64 = 5401; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_27.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_27.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_27.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_27.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_27.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_27.GetSResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
- l1cache_27.GetXResp_recv : Accumulator : Sum.u64 = 375; SumSQ.u64 = 375; Count.u64 = 375; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_27.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_27.GetXResp_recv : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; 
  l1cache_27.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_27.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_27.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_27.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_27.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_27.FetchInvX_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_27.FetchInvX_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l1cache_27.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_27.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_27.MSHR_occupancy : Accumulator : Sum.u64 = 430828; SumSQ.u64 = 9367262; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -12120,11 +12120,11 @@ Model complete
  l2cache_14.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_14.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_14.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_14.Inv_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_14.Inv_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
  l2cache_14.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_14.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_14.FetchInv_recv : Accumulator : Sum.u64 = 488; SumSQ.u64 = 488; Count.u64 = 488; Min.u64 = 1; Max.u64 = 1; 
- l2cache_14.FetchInvX_recv : Accumulator : Sum.u64 = 499; SumSQ.u64 = 499; Count.u64 = 499; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_14.FetchInv_recv : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_14.FetchInvX_recv : Accumulator : Sum.u64 = 255; SumSQ.u64 = 255; Count.u64 = 255; Min.u64 = 1; Max.u64 = 1; 
  l2cache_14.FetchResp_recv : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; 
  l2cache_14.FetchXResp_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
  l2cache_14.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -12268,19 +12268,19 @@ Model complete
  l1cache_28.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_28.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_28.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_28.GetS_recv : Accumulator : Sum.u64 = 21558; SumSQ.u64 = 21558; Count.u64 = 21558; Min.u64 = 1; Max.u64 = 1; 
- l1cache_28.GetX_recv : Accumulator : Sum.u64 = 6333; SumSQ.u64 = 6333; Count.u64 = 6333; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_28.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_28.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_28.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_28.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_28.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_28.GetSResp_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
- l1cache_28.GetXResp_recv : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_28.GetSResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_28.GetXResp_recv : Accumulator : Sum.u64 = 367; SumSQ.u64 = 367; Count.u64 = 367; Min.u64 = 1; Max.u64 = 1; 
  l1cache_28.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_28.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_28.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_28.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_28.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_28.FetchInvX_recv : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_28.FetchInvX_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
  l1cache_28.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_28.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_28.MSHR_occupancy : Accumulator : Sum.u64 = 424538; SumSQ.u64 = 9197892; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -12438,19 +12438,19 @@ Model complete
  l1cache_29.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_29.GetS_recv : Accumulator : Sum.u64 = 22209; SumSQ.u64 = 22209; Count.u64 = 22209; Min.u64 = 1; Max.u64 = 1; 
- l1cache_29.GetX_recv : Accumulator : Sum.u64 = 7872; SumSQ.u64 = 7872; Count.u64 = 7872; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_29.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_29.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_29.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.GetSResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
- l1cache_29.GetXResp_recv : Accumulator : Sum.u64 = 374; SumSQ.u64 = 374; Count.u64 = 374; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_29.GetXResp_recv : Accumulator : Sum.u64 = 369; SumSQ.u64 = 369; Count.u64 = 369; Min.u64 = 1; Max.u64 = 1; 
  l1cache_29.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.Inv_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l1cache_29.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.FetchInv_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
- l1cache_29.FetchInvX_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_29.FetchInvX_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
  l1cache_29.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_29.MSHR_occupancy : Accumulator : Sum.u64 = 425669; SumSQ.u64 = 9202783; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -12771,11 +12771,11 @@ Model complete
  l2cache_15.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_15.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_15.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_15.Inv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_15.Inv_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l2cache_15.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_15.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_15.FetchInv_recv : Accumulator : Sum.u64 = 498; SumSQ.u64 = 498; Count.u64 = 498; Min.u64 = 1; Max.u64 = 1; 
- l2cache_15.FetchInvX_recv : Accumulator : Sum.u64 = 495; SumSQ.u64 = 495; Count.u64 = 495; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_15.FetchInv_recv : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_15.FetchInvX_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l2cache_15.FetchResp_recv : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; 
  l2cache_15.FetchXResp_recv : Accumulator : Sum.u64 = 245; SumSQ.u64 = 245; Count.u64 = 245; Min.u64 = 1; Max.u64 = 1; 
  l2cache_15.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -12919,19 +12919,19 @@ Model complete
  l1cache_30.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_30.GetS_recv : Accumulator : Sum.u64 = 21032; SumSQ.u64 = 21032; Count.u64 = 21032; Min.u64 = 1; Max.u64 = 1; 
- l1cache_30.GetX_recv : Accumulator : Sum.u64 = 6024; SumSQ.u64 = 6024; Count.u64 = 6024; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_30.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_30.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_30.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
- l1cache_30.GetXResp_recv : Accumulator : Sum.u64 = 374; SumSQ.u64 = 374; Count.u64 = 374; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_30.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; 
  l1cache_30.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.FetchInv_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
- l1cache_30.FetchInvX_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_30.FetchInvX_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
  l1cache_30.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_30.MSHR_occupancy : Accumulator : Sum.u64 = 426427; SumSQ.u64 = 9234481; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -13089,19 +13089,19 @@ Model complete
  l1cache_31.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_31.GetS_recv : Accumulator : Sum.u64 = 20785; SumSQ.u64 = 20785; Count.u64 = 20785; Min.u64 = 1; Max.u64 = 1; 
- l1cache_31.GetX_recv : Accumulator : Sum.u64 = 5897; SumSQ.u64 = 5897; Count.u64 = 5897; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_31.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_31.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_31.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
- l1cache_31.GetXResp_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_31.GetXResp_recv : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; 
  l1cache_31.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.Inv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_31.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.FetchInv_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
- l1cache_31.FetchInvX_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_31.FetchInvX_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; 
  l1cache_31.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_31.MSHR_occupancy : Accumulator : Sum.u64 = 428343; SumSQ.u64 = 9261987; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -13422,11 +13422,11 @@ Model complete
  l2cache_16.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_16.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_16.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_16.Inv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_16.Inv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
  l2cache_16.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_16.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_16.FetchInv_recv : Accumulator : Sum.u64 = 482; SumSQ.u64 = 482; Count.u64 = 482; Min.u64 = 1; Max.u64 = 1; 
- l2cache_16.FetchInvX_recv : Accumulator : Sum.u64 = 511; SumSQ.u64 = 511; Count.u64 = 511; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_16.FetchInv_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_16.FetchInvX_recv : Accumulator : Sum.u64 = 259; SumSQ.u64 = 259; Count.u64 = 259; Min.u64 = 1; Max.u64 = 1; 
  l2cache_16.FetchResp_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
  l2cache_16.FetchXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l2cache_16.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -13570,19 +13570,19 @@ Model complete
  l1cache_32.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_32.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_32.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_32.GetS_recv : Accumulator : Sum.u64 = 21012; SumSQ.u64 = 21012; Count.u64 = 21012; Min.u64 = 1; Max.u64 = 1; 
- l1cache_32.GetX_recv : Accumulator : Sum.u64 = 5317; SumSQ.u64 = 5317; Count.u64 = 5317; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_32.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_32.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_32.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_32.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_32.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_32.GetSResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
- l1cache_32.GetXResp_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_32.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_32.GetXResp_recv : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; 
  l1cache_32.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_32.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_32.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_32.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_32.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_32.FetchInvX_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_32.FetchInvX_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l1cache_32.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_32.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_32.MSHR_occupancy : Accumulator : Sum.u64 = 432702; SumSQ.u64 = 9407254; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -13740,19 +13740,19 @@ Model complete
  l1cache_33.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_33.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_33.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_33.GetS_recv : Accumulator : Sum.u64 = 21067; SumSQ.u64 = 21067; Count.u64 = 21067; Min.u64 = 1; Max.u64 = 1; 
- l1cache_33.GetX_recv : Accumulator : Sum.u64 = 5675; SumSQ.u64 = 5675; Count.u64 = 5675; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_33.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_33.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_33.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_33.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_33.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_33.GetSResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
- l1cache_33.GetXResp_recv : Accumulator : Sum.u64 = 376; SumSQ.u64 = 376; Count.u64 = 376; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_33.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_33.GetXResp_recv : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; 
  l1cache_33.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_33.Inv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l1cache_33.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_33.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_33.FetchInv_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
- l1cache_33.FetchInvX_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_33.FetchInvX_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  l1cache_33.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_33.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_33.MSHR_occupancy : Accumulator : Sum.u64 = 431139; SumSQ.u64 = 9384415; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -14096,11 +14096,11 @@ Model complete
  l2cache_17.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_17.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_17.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_17.Inv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_17.Inv_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
  l2cache_17.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_17.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_17.FetchInv_recv : Accumulator : Sum.u64 = 484; SumSQ.u64 = 484; Count.u64 = 484; Min.u64 = 1; Max.u64 = 1; 
- l2cache_17.FetchInvX_recv : Accumulator : Sum.u64 = 503; SumSQ.u64 = 503; Count.u64 = 503; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_17.FetchInv_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_17.FetchInvX_recv : Accumulator : Sum.u64 = 258; SumSQ.u64 = 258; Count.u64 = 258; Min.u64 = 1; Max.u64 = 1; 
  l2cache_17.FetchResp_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; 
  l2cache_17.FetchXResp_recv : Accumulator : Sum.u64 = 245; SumSQ.u64 = 245; Count.u64 = 245; Min.u64 = 1; Max.u64 = 1; 
  l2cache_17.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -14244,19 +14244,19 @@ Model complete
  l1cache_34.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_34.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_34.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_34.GetS_recv : Accumulator : Sum.u64 = 21726; SumSQ.u64 = 21726; Count.u64 = 21726; Min.u64 = 1; Max.u64 = 1; 
- l1cache_34.GetX_recv : Accumulator : Sum.u64 = 6314; SumSQ.u64 = 6314; Count.u64 = 6314; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_34.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_34.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_34.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_34.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_34.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_34.GetSResp_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
- l1cache_34.GetXResp_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_34.GetSResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_34.GetXResp_recv : Accumulator : Sum.u64 = 367; SumSQ.u64 = 367; Count.u64 = 367; Min.u64 = 1; Max.u64 = 1; 
  l1cache_34.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_34.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_34.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_34.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_34.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_34.FetchInvX_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_34.FetchInvX_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
  l1cache_34.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_34.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_34.MSHR_occupancy : Accumulator : Sum.u64 = 434702; SumSQ.u64 = 9407154; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -14414,19 +14414,19 @@ Model complete
  l1cache_35.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_35.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_35.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_35.GetS_recv : Accumulator : Sum.u64 = 21832; SumSQ.u64 = 21832; Count.u64 = 21832; Min.u64 = 1; Max.u64 = 1; 
- l1cache_35.GetX_recv : Accumulator : Sum.u64 = 7296; SumSQ.u64 = 7296; Count.u64 = 7296; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_35.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_35.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_35.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_35.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_35.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_35.GetSResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
- l1cache_35.GetXResp_recv : Accumulator : Sum.u64 = 374; SumSQ.u64 = 374; Count.u64 = 374; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_35.GetSResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_35.GetXResp_recv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; 
  l1cache_35.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_35.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_35.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_35.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_35.FetchInv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
- l1cache_35.FetchInvX_recv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_35.FetchInvX_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
  l1cache_35.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_35.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_35.MSHR_occupancy : Accumulator : Sum.u64 = 433197; SumSQ.u64 = 9315731; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -14774,7 +14774,7 @@ Model complete
  l2cache_18.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_18.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_18.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_18.FetchInvX_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_18.FetchInvX_recv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; 
  l2cache_18.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_18.FetchXResp_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; 
  l2cache_18.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -14918,13 +14918,13 @@ Model complete
  l1cache_36.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_36.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_36.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_36.GetS_recv : Accumulator : Sum.u64 = 10526; SumSQ.u64 = 10526; Count.u64 = 10526; Min.u64 = 1; Max.u64 = 1; 
- l1cache_36.GetX_recv : Accumulator : Sum.u64 = 3206; SumSQ.u64 = 3206; Count.u64 = 3206; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_36.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_36.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_36.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_36.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_36.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_36.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
- l1cache_36.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_36.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_36.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_36.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_36.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_36.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -15088,19 +15088,19 @@ Model complete
  l1cache_37.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_37.GetS_recv : Accumulator : Sum.u64 = 10928; SumSQ.u64 = 10928; Count.u64 = 10928; Min.u64 = 1; Max.u64 = 1; 
- l1cache_37.GetX_recv : Accumulator : Sum.u64 = 2506; SumSQ.u64 = 2506; Count.u64 = 2506; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_37.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_37.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_37.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_37.GetSResp_recv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_37.GetSResp_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; 
  l1cache_37.GetXResp_recv : Accumulator : Sum.u64 = 293; SumSQ.u64 = 293; Count.u64 = 293; Min.u64 = 1; Max.u64 = 1; 
  l1cache_37.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_37.FetchInvX_recv : Accumulator : Sum.u64 = 337; SumSQ.u64 = 337; Count.u64 = 337; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_37.FetchInvX_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; 
  l1cache_37.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_37.MSHR_occupancy : Accumulator : Sum.u64 = 366760; SumSQ.u64 = 6978750; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -15425,7 +15425,7 @@ Model complete
  l2cache_19.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_19.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_19.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_19.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_19.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  l2cache_19.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_19.FetchXResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l2cache_19.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -15569,19 +15569,19 @@ Model complete
  l1cache_38.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_38.GetS_recv : Accumulator : Sum.u64 = 9796; SumSQ.u64 = 9796; Count.u64 = 9796; Min.u64 = 1; Max.u64 = 1; 
- l1cache_38.GetX_recv : Accumulator : Sum.u64 = 2379; SumSQ.u64 = 2379; Count.u64 = 2379; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_38.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_38.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_38.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_38.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_38.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
  l1cache_38.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_38.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_38.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_38.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_38.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_38.MSHR_occupancy : Accumulator : Sum.u64 = 351766; SumSQ.u64 = 6574908; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -15739,19 +15739,19 @@ Model complete
  l1cache_39.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_39.GetS_recv : Accumulator : Sum.u64 = 9941; SumSQ.u64 = 9941; Count.u64 = 9941; Min.u64 = 1; Max.u64 = 1; 
- l1cache_39.GetX_recv : Accumulator : Sum.u64 = 2955; SumSQ.u64 = 2955; Count.u64 = 2955; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_39.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_39.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_39.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_39.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
- l1cache_39.GetXResp_recv : Accumulator : Sum.u64 = 254; SumSQ.u64 = 254; Count.u64 = 254; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_39.GetSResp_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_39.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
  l1cache_39.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_39.FetchInvX_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_39.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l1cache_39.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_39.MSHR_occupancy : Accumulator : Sum.u64 = 346282; SumSQ.u64 = 6441290; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -16076,7 +16076,7 @@ Model complete
  l2cache_20.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_20.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_20.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_20.FetchInvX_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_20.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l2cache_20.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_20.FetchXResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l2cache_20.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -16220,19 +16220,19 @@ Model complete
  l1cache_40.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_40.GetS_recv : Accumulator : Sum.u64 = 9474; SumSQ.u64 = 9474; Count.u64 = 9474; Min.u64 = 1; Max.u64 = 1; 
- l1cache_40.GetX_recv : Accumulator : Sum.u64 = 2465; SumSQ.u64 = 2465; Count.u64 = 2465; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_40.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_40.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_40.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_40.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
- l1cache_40.GetXResp_recv : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_40.GetSResp_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_40.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
  l1cache_40.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_40.FetchInvX_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_40.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l1cache_40.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_40.MSHR_occupancy : Accumulator : Sum.u64 = 347589; SumSQ.u64 = 6445089; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -16390,19 +16390,19 @@ Model complete
  l1cache_41.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_41.GetS_recv : Accumulator : Sum.u64 = 9618; SumSQ.u64 = 9618; Count.u64 = 9618; Min.u64 = 1; Max.u64 = 1; 
- l1cache_41.GetX_recv : Accumulator : Sum.u64 = 2683; SumSQ.u64 = 2683; Count.u64 = 2683; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_41.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_41.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_41.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_41.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
- l1cache_41.GetXResp_recv : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_41.GetSResp_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_41.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
  l1cache_41.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_41.FetchInvX_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_41.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l1cache_41.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_41.MSHR_occupancy : Accumulator : Sum.u64 = 344920; SumSQ.u64 = 6376180; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -16727,7 +16727,7 @@ Model complete
  l2cache_21.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_21.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_21.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_21.FetchInvX_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_21.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
  l2cache_21.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_21.FetchXResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l2cache_21.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -16871,19 +16871,19 @@ Model complete
  l1cache_42.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_42.GetS_recv : Accumulator : Sum.u64 = 9479; SumSQ.u64 = 9479; Count.u64 = 9479; Min.u64 = 1; Max.u64 = 1; 
- l1cache_42.GetX_recv : Accumulator : Sum.u64 = 2760; SumSQ.u64 = 2760; Count.u64 = 2760; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_42.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_42.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_42.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_42.GetSResp_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
- l1cache_42.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_42.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_42.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_42.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_42.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_42.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_42.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_42.MSHR_occupancy : Accumulator : Sum.u64 = 348158; SumSQ.u64 = 6440322; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -17041,19 +17041,19 @@ Model complete
  l1cache_43.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_43.GetS_recv : Accumulator : Sum.u64 = 9494; SumSQ.u64 = 9494; Count.u64 = 9494; Min.u64 = 1; Max.u64 = 1; 
- l1cache_43.GetX_recv : Accumulator : Sum.u64 = 2342; SumSQ.u64 = 2342; Count.u64 = 2342; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_43.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_43.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_43.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_43.GetSResp_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
- l1cache_43.GetXResp_recv : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_43.GetSResp_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_43.GetXResp_recv : Accumulator : Sum.u64 = 254; SumSQ.u64 = 254; Count.u64 = 254; Min.u64 = 1; Max.u64 = 1; 
  l1cache_43.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_43.FetchInvX_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_43.FetchInvX_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l1cache_43.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_43.MSHR_occupancy : Accumulator : Sum.u64 = 348062; SumSQ.u64 = 6459326; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -17378,7 +17378,7 @@ Model complete
  l2cache_22.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_22.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_22.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_22.FetchInvX_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_22.FetchInvX_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
  l2cache_22.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_22.FetchXResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l2cache_22.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -17522,19 +17522,19 @@ Model complete
  l1cache_44.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_44.GetS_recv : Accumulator : Sum.u64 = 9496; SumSQ.u64 = 9496; Count.u64 = 9496; Min.u64 = 1; Max.u64 = 1; 
- l1cache_44.GetX_recv : Accumulator : Sum.u64 = 2382; SumSQ.u64 = 2382; Count.u64 = 2382; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_44.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_44.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_44.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_44.GetSResp_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
- l1cache_44.GetXResp_recv : Accumulator : Sum.u64 = 262; SumSQ.u64 = 262; Count.u64 = 262; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_44.GetSResp_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_44.GetXResp_recv : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; 
  l1cache_44.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_44.FetchInvX_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_44.FetchInvX_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
  l1cache_44.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_44.MSHR_occupancy : Accumulator : Sum.u64 = 353838; SumSQ.u64 = 6580546; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -17692,19 +17692,19 @@ Model complete
  l1cache_45.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_45.GetS_recv : Accumulator : Sum.u64 = 9991; SumSQ.u64 = 9991; Count.u64 = 9991; Min.u64 = 1; Max.u64 = 1; 
- l1cache_45.GetX_recv : Accumulator : Sum.u64 = 2523; SumSQ.u64 = 2523; Count.u64 = 2523; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_45.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_45.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_45.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_45.GetSResp_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
- l1cache_45.GetXResp_recv : Accumulator : Sum.u64 = 254; SumSQ.u64 = 254; Count.u64 = 254; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_45.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_45.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_45.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_45.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_45.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_45.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_45.MSHR_occupancy : Accumulator : Sum.u64 = 350270; SumSQ.u64 = 6526862; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -18052,7 +18052,7 @@ Model complete
  l2cache_23.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_23.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_23.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_23.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_23.FetchInvX_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l2cache_23.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_23.FetchXResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l2cache_23.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -18196,19 +18196,19 @@ Model complete
  l1cache_46.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_46.GetS_recv : Accumulator : Sum.u64 = 10681; SumSQ.u64 = 10681; Count.u64 = 10681; Min.u64 = 1; Max.u64 = 1; 
- l1cache_46.GetX_recv : Accumulator : Sum.u64 = 2803; SumSQ.u64 = 2803; Count.u64 = 2803; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_46.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_46.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_46.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_46.GetSResp_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
- l1cache_46.GetXResp_recv : Accumulator : Sum.u64 = 254; SumSQ.u64 = 254; Count.u64 = 254; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_46.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_46.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_46.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_46.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_46.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_46.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_46.MSHR_occupancy : Accumulator : Sum.u64 = 361214; SumSQ.u64 = 6831296; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -18366,19 +18366,19 @@ Model complete
  l1cache_47.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_47.GetS_recv : Accumulator : Sum.u64 = 10216; SumSQ.u64 = 10216; Count.u64 = 10216; Min.u64 = 1; Max.u64 = 1; 
- l1cache_47.GetX_recv : Accumulator : Sum.u64 = 2305; SumSQ.u64 = 2305; Count.u64 = 2305; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_47.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_47.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_47.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_47.GetSResp_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
- l1cache_47.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_47.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_47.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_47.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_47.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_47.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_47.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_47.MSHR_occupancy : Accumulator : Sum.u64 = 356390; SumSQ.u64 = 6733782; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -18703,7 +18703,7 @@ Model complete
  l2cache_24.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_24.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_24.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_24.FetchInvX_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_24.FetchInvX_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; 
  l2cache_24.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_24.FetchXResp_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; 
  l2cache_24.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -18847,19 +18847,19 @@ Model complete
  l1cache_48.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_48.GetS_recv : Accumulator : Sum.u64 = 10736; SumSQ.u64 = 10736; Count.u64 = 10736; Min.u64 = 1; Max.u64 = 1; 
- l1cache_48.GetX_recv : Accumulator : Sum.u64 = 3435; SumSQ.u64 = 3435; Count.u64 = 3435; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_48.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_48.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_48.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_48.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
- l1cache_48.GetXResp_recv : Accumulator : Sum.u64 = 258; SumSQ.u64 = 258; Count.u64 = 258; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_48.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_48.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_48.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_48.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_48.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_48.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_48.MSHR_occupancy : Accumulator : Sum.u64 = 351786; SumSQ.u64 = 6597708; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -19017,19 +19017,19 @@ Model complete
  l1cache_49.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_49.GetS_recv : Accumulator : Sum.u64 = 10678; SumSQ.u64 = 10678; Count.u64 = 10678; Min.u64 = 1; Max.u64 = 1; 
- l1cache_49.GetX_recv : Accumulator : Sum.u64 = 2158; SumSQ.u64 = 2158; Count.u64 = 2158; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_49.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_49.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_49.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_49.GetSResp_recv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; 
- l1cache_49.GetXResp_recv : Accumulator : Sum.u64 = 292; SumSQ.u64 = 292; Count.u64 = 292; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_49.GetSResp_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_49.GetXResp_recv : Accumulator : Sum.u64 = 291; SumSQ.u64 = 291; Count.u64 = 291; Min.u64 = 1; Max.u64 = 1; 
  l1cache_49.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_49.FetchInvX_recv : Accumulator : Sum.u64 = 326; SumSQ.u64 = 326; Count.u64 = 326; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_49.FetchInvX_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; 
  l1cache_49.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_49.MSHR_occupancy : Accumulator : Sum.u64 = 363966; SumSQ.u64 = 6917936; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -19338,7 +19338,7 @@ Model complete
  l2cache_25.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_25.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_25.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_25.GetS_recv : Accumulator : Sum.u64 = 1244; SumSQ.u64 = 1244; Count.u64 = 1244; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_25.GetS_recv : Accumulator : Sum.u64 = 1243; SumSQ.u64 = 1243; Count.u64 = 1243; Min.u64 = 1; Max.u64 = 1; 
  l2cache_25.GetX_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l2cache_25.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_25.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -19354,7 +19354,7 @@ Model complete
  l2cache_25.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_25.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_25.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_25.FetchInvX_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_25.FetchInvX_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l2cache_25.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_25.FetchXResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l2cache_25.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -19498,19 +19498,19 @@ Model complete
  l1cache_50.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_50.GetS_recv : Accumulator : Sum.u64 = 9320; SumSQ.u64 = 9320; Count.u64 = 9320; Min.u64 = 1; Max.u64 = 1; 
- l1cache_50.GetX_recv : Accumulator : Sum.u64 = 2071; SumSQ.u64 = 2071; Count.u64 = 2071; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_50.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_50.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_50.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_50.GetSResp_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
- l1cache_50.GetXResp_recv : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_50.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_50.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_50.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_50.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_50.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_50.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_50.MSHR_occupancy : Accumulator : Sum.u64 = 348277; SumSQ.u64 = 6466315; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -19668,13 +19668,13 @@ Model complete
  l1cache_51.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_51.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_51.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_51.GetS_recv : Accumulator : Sum.u64 = 9333; SumSQ.u64 = 9333; Count.u64 = 9333; Min.u64 = 1; Max.u64 = 1; 
- l1cache_51.GetX_recv : Accumulator : Sum.u64 = 2972; SumSQ.u64 = 2972; Count.u64 = 2972; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_51.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_51.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_51.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_51.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_51.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_51.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
- l1cache_51.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_51.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_51.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_51.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_51.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -19989,7 +19989,7 @@ Model complete
  l2cache_26.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_26.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_26.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_26.GetS_recv : Accumulator : Sum.u64 = 1238; SumSQ.u64 = 1238; Count.u64 = 1238; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_26.GetS_recv : Accumulator : Sum.u64 = 1237; SumSQ.u64 = 1237; Count.u64 = 1237; Min.u64 = 1; Max.u64 = 1; 
  l2cache_26.GetX_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l2cache_26.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_26.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -20005,7 +20005,7 @@ Model complete
  l2cache_26.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_26.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_26.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_26.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_26.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l2cache_26.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_26.FetchXResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l2cache_26.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -20149,19 +20149,19 @@ Model complete
  l1cache_52.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_52.GetS_recv : Accumulator : Sum.u64 = 9026; SumSQ.u64 = 9026; Count.u64 = 9026; Min.u64 = 1; Max.u64 = 1; 
- l1cache_52.GetX_recv : Accumulator : Sum.u64 = 2716; SumSQ.u64 = 2716; Count.u64 = 2716; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_52.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_52.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_52.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_52.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_52.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
  l1cache_52.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_52.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_52.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_52.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_52.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_52.MSHR_occupancy : Accumulator : Sum.u64 = 365748; SumSQ.u64 = 6729480; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -20319,13 +20319,13 @@ Model complete
  l1cache_53.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_53.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_53.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_53.GetS_recv : Accumulator : Sum.u64 = 9146; SumSQ.u64 = 9146; Count.u64 = 9146; Min.u64 = 1; Max.u64 = 1; 
- l1cache_53.GetX_recv : Accumulator : Sum.u64 = 3249; SumSQ.u64 = 3249; Count.u64 = 3249; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_53.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_53.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_53.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_53.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_53.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_53.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
- l1cache_53.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_53.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_53.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_53.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_53.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_53.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -20656,7 +20656,7 @@ Model complete
  l2cache_27.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_27.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_27.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_27.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_27.FetchInvX_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l2cache_27.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_27.FetchXResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l2cache_27.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -20800,19 +20800,19 @@ Model complete
  l1cache_54.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_54.GetS_recv : Accumulator : Sum.u64 = 9256; SumSQ.u64 = 9256; Count.u64 = 9256; Min.u64 = 1; Max.u64 = 1; 
- l1cache_54.GetX_recv : Accumulator : Sum.u64 = 3244; SumSQ.u64 = 3244; Count.u64 = 3244; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_54.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_54.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_54.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_54.GetSResp_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
- l1cache_54.GetXResp_recv : Accumulator : Sum.u64 = 254; SumSQ.u64 = 254; Count.u64 = 254; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_54.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_54.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_54.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_54.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_54.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_54.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_54.MSHR_occupancy : Accumulator : Sum.u64 = 368868; SumSQ.u64 = 6742002; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -20970,19 +20970,19 @@ Model complete
  l1cache_55.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_55.GetS_recv : Accumulator : Sum.u64 = 9501; SumSQ.u64 = 9501; Count.u64 = 9501; Min.u64 = 1; Max.u64 = 1; 
- l1cache_55.GetX_recv : Accumulator : Sum.u64 = 3573; SumSQ.u64 = 3573; Count.u64 = 3573; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_55.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_55.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_55.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_55.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
- l1cache_55.GetXResp_recv : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_55.GetSResp_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_55.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
  l1cache_55.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_55.FetchInvX_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_55.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l1cache_55.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_55.MSHR_occupancy : Accumulator : Sum.u64 = 367825; SumSQ.u64 = 6713487; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -21307,7 +21307,7 @@ Model complete
  l2cache_28.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_28.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_28.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_28.FetchInvX_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_28.FetchInvX_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l2cache_28.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_28.FetchXResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l2cache_28.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -21451,19 +21451,19 @@ Model complete
  l1cache_56.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_56.GetS_recv : Accumulator : Sum.u64 = 9008; SumSQ.u64 = 9008; Count.u64 = 9008; Min.u64 = 1; Max.u64 = 1; 
- l1cache_56.GetX_recv : Accumulator : Sum.u64 = 2629; SumSQ.u64 = 2629; Count.u64 = 2629; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_56.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_56.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_56.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_56.GetSResp_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
- l1cache_56.GetXResp_recv : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_56.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_56.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_56.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_56.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_56.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_56.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_56.MSHR_occupancy : Accumulator : Sum.u64 = 372712; SumSQ.u64 = 6845444; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -21621,19 +21621,19 @@ Model complete
  l1cache_57.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_57.GetS_recv : Accumulator : Sum.u64 = 9299; SumSQ.u64 = 9299; Count.u64 = 9299; Min.u64 = 1; Max.u64 = 1; 
- l1cache_57.GetX_recv : Accumulator : Sum.u64 = 3270; SumSQ.u64 = 3270; Count.u64 = 3270; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_57.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_57.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_57.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_57.GetSResp_recv : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; 
- l1cache_57.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_57.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_57.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_57.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_57.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_57.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_57.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_57.MSHR_occupancy : Accumulator : Sum.u64 = 374376; SumSQ.u64 = 6840844; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -21958,7 +21958,7 @@ Model complete
  l2cache_29.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_29.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_29.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_29.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_29.FetchInvX_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  l2cache_29.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_29.FetchXResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l2cache_29.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -22102,19 +22102,19 @@ Model complete
  l1cache_58.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_58.GetS_recv : Accumulator : Sum.u64 = 9709; SumSQ.u64 = 9709; Count.u64 = 9709; Min.u64 = 1; Max.u64 = 1; 
- l1cache_58.GetX_recv : Accumulator : Sum.u64 = 2931; SumSQ.u64 = 2931; Count.u64 = 2931; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_58.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_58.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_58.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_58.GetSResp_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_58.GetSResp_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
  l1cache_58.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
  l1cache_58.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_58.FetchInvX_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_58.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l1cache_58.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_58.MSHR_occupancy : Accumulator : Sum.u64 = 384368; SumSQ.u64 = 7135460; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -22272,19 +22272,19 @@ Model complete
  l1cache_59.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_59.GetS_recv : Accumulator : Sum.u64 = 9813; SumSQ.u64 = 9813; Count.u64 = 9813; Min.u64 = 1; Max.u64 = 1; 
- l1cache_59.GetX_recv : Accumulator : Sum.u64 = 2956; SumSQ.u64 = 2956; Count.u64 = 2956; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_59.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_59.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_59.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_59.GetSResp_recv : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; 
- l1cache_59.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_59.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_59.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
  l1cache_59.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_59.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_59.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l1cache_59.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_59.MSHR_occupancy : Accumulator : Sum.u64 = 381850; SumSQ.u64 = 7118180; Count.u64 = 21543; Min.u64 = 0; Max.u64 = 23; 
@@ -22780,12 +22780,12 @@ Model complete
  l1cache_60.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_60.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_60.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_60.GetS_recv : Accumulator : Sum.u64 = 9981; SumSQ.u64 = 9981; Count.u64 = 9981; Min.u64 = 1; Max.u64 = 1; 
- l1cache_60.GetX_recv : Accumulator : Sum.u64 = 3409; SumSQ.u64 = 3409; Count.u64 = 3409; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_60.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_60.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_60.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_60.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_60.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_60.GetSResp_recv : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_60.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l1cache_60.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_60.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_60.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -22950,13 +22950,13 @@ Model complete
  l1cache_61.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_61.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_61.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_61.GetS_recv : Accumulator : Sum.u64 = 9770; SumSQ.u64 = 9770; Count.u64 = 9770; Min.u64 = 1; Max.u64 = 1; 
- l1cache_61.GetX_recv : Accumulator : Sum.u64 = 2870; SumSQ.u64 = 2870; Count.u64 = 2870; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_61.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_61.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_61.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_61.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_61.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_61.GetSResp_recv : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; 
- l1cache_61.GetXResp_recv : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_61.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_61.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_61.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_61.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_61.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -23314,7 +23314,7 @@ Model complete
  l2cache_31.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_31.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_31.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_31.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_31.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l2cache_31.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_31.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_31.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -23458,13 +23458,13 @@ Model complete
  l1cache_62.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_62.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_62.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_62.GetS_recv : Accumulator : Sum.u64 = 9200; SumSQ.u64 = 9200; Count.u64 = 9200; Min.u64 = 1; Max.u64 = 1; 
- l1cache_62.GetX_recv : Accumulator : Sum.u64 = 2921; SumSQ.u64 = 2921; Count.u64 = 2921; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_62.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_62.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_62.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_62.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_62.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_62.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
- l1cache_62.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_62.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_62.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_62.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_62.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_62.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -23628,13 +23628,13 @@ Model complete
  l1cache_63.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_63.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_63.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_63.GetS_recv : Accumulator : Sum.u64 = 9306; SumSQ.u64 = 9306; Count.u64 = 9306; Min.u64 = 1; Max.u64 = 1; 
- l1cache_63.GetX_recv : Accumulator : Sum.u64 = 3037; SumSQ.u64 = 3037; Count.u64 = 3037; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_63.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_63.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_63.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_63.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_63.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_63.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
- l1cache_63.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_63.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_63.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_63.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_63.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_63.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -24109,12 +24109,12 @@ Model complete
  l1cache_64.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_64.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_64.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_64.GetS_recv : Accumulator : Sum.u64 = 9301; SumSQ.u64 = 9301; Count.u64 = 9301; Min.u64 = 1; Max.u64 = 1; 
- l1cache_64.GetX_recv : Accumulator : Sum.u64 = 3129; SumSQ.u64 = 3129; Count.u64 = 3129; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_64.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_64.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_64.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_64.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_64.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_64.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_64.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l1cache_64.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_64.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_64.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -24279,12 +24279,12 @@ Model complete
  l1cache_65.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_65.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_65.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_65.GetS_recv : Accumulator : Sum.u64 = 9226; SumSQ.u64 = 9226; Count.u64 = 9226; Min.u64 = 1; Max.u64 = 1; 
- l1cache_65.GetX_recv : Accumulator : Sum.u64 = 3000; SumSQ.u64 = 3000; Count.u64 = 3000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_65.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_65.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_65.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_65.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_65.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_65.GetSResp_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_65.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l1cache_65.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_65.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_65.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -24600,7 +24600,7 @@ Model complete
  l2cache_33.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_33.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_33.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache_33.GetS_recv : Accumulator : Sum.u64 = 1239; SumSQ.u64 = 1239; Count.u64 = 1239; Min.u64 = 1; Max.u64 = 1; 
+ l2cache_33.GetS_recv : Accumulator : Sum.u64 = 1235; SumSQ.u64 = 1235; Count.u64 = 1235; Min.u64 = 1; Max.u64 = 1; 
  l2cache_33.GetX_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l2cache_33.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache_33.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -24760,13 +24760,13 @@ Model complete
  l1cache_66.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_66.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_66.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_66.GetS_recv : Accumulator : Sum.u64 = 9277; SumSQ.u64 = 9277; Count.u64 = 9277; Min.u64 = 1; Max.u64 = 1; 
- l1cache_66.GetX_recv : Accumulator : Sum.u64 = 2992; SumSQ.u64 = 2992; Count.u64 = 2992; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_66.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_66.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_66.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_66.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_66.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_66.GetSResp_recv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; 
- l1cache_66.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_66.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_66.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_66.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_66.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_66.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -24930,13 +24930,13 @@ Model complete
  l1cache_67.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_67.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_67.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_67.GetS_recv : Accumulator : Sum.u64 = 9089; SumSQ.u64 = 9089; Count.u64 = 9089; Min.u64 = 1; Max.u64 = 1; 
- l1cache_67.GetX_recv : Accumulator : Sum.u64 = 2815; SumSQ.u64 = 2815; Count.u64 = 2815; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_67.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_67.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_67.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_67.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_67.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_67.GetSResp_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
- l1cache_67.GetXResp_recv : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_67.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_67.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_67.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_67.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_67.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -25438,13 +25438,13 @@ Model complete
  l1cache_68.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_68.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_68.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_68.GetS_recv : Accumulator : Sum.u64 = 9306; SumSQ.u64 = 9306; Count.u64 = 9306; Min.u64 = 1; Max.u64 = 1; 
- l1cache_68.GetX_recv : Accumulator : Sum.u64 = 2911; SumSQ.u64 = 2911; Count.u64 = 2911; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_68.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_68.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_68.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_68.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_68.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_68.GetSResp_recv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; 
- l1cache_68.GetXResp_recv : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_68.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_68.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_68.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_68.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_68.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -25608,12 +25608,12 @@ Model complete
  l1cache_69.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_69.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_69.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_69.GetS_recv : Accumulator : Sum.u64 = 8803; SumSQ.u64 = 8803; Count.u64 = 8803; Min.u64 = 1; Max.u64 = 1; 
- l1cache_69.GetX_recv : Accumulator : Sum.u64 = 2262; SumSQ.u64 = 2262; Count.u64 = 2262; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_69.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_69.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_69.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_69.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_69.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_69.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_69.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l1cache_69.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_69.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_69.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -26116,13 +26116,13 @@ Model complete
  l1cache_70.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_70.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_70.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_70.GetS_recv : Accumulator : Sum.u64 = 9841; SumSQ.u64 = 9841; Count.u64 = 9841; Min.u64 = 1; Max.u64 = 1; 
- l1cache_70.GetX_recv : Accumulator : Sum.u64 = 2814; SumSQ.u64 = 2814; Count.u64 = 2814; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_70.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_70.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_70.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_70.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_70.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_70.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; 
- l1cache_70.GetXResp_recv : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_70.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_70.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_70.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_70.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_70.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -26286,13 +26286,13 @@ Model complete
  l1cache_71.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_71.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_71.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_71.GetS_recv : Accumulator : Sum.u64 = 9570; SumSQ.u64 = 9570; Count.u64 = 9570; Min.u64 = 1; Max.u64 = 1; 
- l1cache_71.GetX_recv : Accumulator : Sum.u64 = 2652; SumSQ.u64 = 2652; Count.u64 = 2652; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_71.GetS_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_71.GetX_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_71.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_71.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_71.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_71.GetSResp_recv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; 
- l1cache_71.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_71.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_71.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
  l1cache_71.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_71.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_71.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_1.out
index 2009d0b96..f6cd18126 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_1.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_1.out
@@ -154,9 +154,9 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (116296 clocks)
  l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetS_recv : Accumulator : Sum.u64 = 1676; SumSQ.u64 = 1676; Count.u64 = 1676; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetX_recv : Accumulator : Sum.u64 = 194; SumSQ.u64 = 194; Count.u64 = 194; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache0.GetS_recv : Accumulator : Sum.u64 = 1345; SumSQ.u64 = 1345; Count.u64 = 1345; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetX_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -515,9 +515,9 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (116296 clocks)
  l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 392; SumSQ.u64 = 392; Count.u64 = 392; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetS_recv : Accumulator : Sum.u64 = 1686; SumSQ.u64 = 1686; Count.u64 = 1686; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetX_recv : Accumulator : Sum.u64 = 206; SumSQ.u64 = 206; Count.u64 = 206; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache1.GetS_recv : Accumulator : Sum.u64 = 1337; SumSQ.u64 = 1337; Count.u64 = 1337; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetX_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -876,9 +876,9 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (116296 clocks)
  l1cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 383; SumSQ.u64 = 383; Count.u64 = 383; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetS_recv : Accumulator : Sum.u64 = 1697; SumSQ.u64 = 1697; Count.u64 = 1697; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetX_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache2.GetS_recv : Accumulator : Sum.u64 = 1347; SumSQ.u64 = 1347; Count.u64 = 1347; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetX_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1237,9 +1237,9 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (116296 clocks)
  l1cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 409; SumSQ.u64 = 409; Count.u64 = 409; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetS_recv : Accumulator : Sum.u64 = 1680; SumSQ.u64 = 1680; Count.u64 = 1680; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetX_recv : Accumulator : Sum.u64 = 229; SumSQ.u64 = 229; Count.u64 = 229; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache3.GetS_recv : Accumulator : Sum.u64 = 1328; SumSQ.u64 = 1328; Count.u64 = 1328; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetX_recv : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1598,9 +1598,9 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (116296 clocks)
  l1cache4.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 394; SumSQ.u64 = 394; Count.u64 = 394; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetS_recv : Accumulator : Sum.u64 = 1728; SumSQ.u64 = 1728; Count.u64 = 1728; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetX_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache4.GetS_recv : Accumulator : Sum.u64 = 1371; SumSQ.u64 = 1371; Count.u64 = 1371; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetX_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1959,9 +1959,9 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (116296 clocks)
  l1cache5.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 433; SumSQ.u64 = 433; Count.u64 = 433; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetS_recv : Accumulator : Sum.u64 = 1742; SumSQ.u64 = 1742; Count.u64 = 1742; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetX_recv : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache5.GetS_recv : Accumulator : Sum.u64 = 1343; SumSQ.u64 = 1343; Count.u64 = 1343; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetX_recv : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2320,9 +2320,9 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (116296 clocks)
  l1cache6.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache6.NULLCMD_recv : Accumulator : Sum.u64 = 421; SumSQ.u64 = 421; Count.u64 = 421; Min.u64 = 1; Max.u64 = 1; 
- l1cache6.GetS_recv : Accumulator : Sum.u64 = 1720; SumSQ.u64 = 1720; Count.u64 = 1720; Min.u64 = 1; Max.u64 = 1; 
- l1cache6.GetX_recv : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; 
+ l1cache6.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache6.GetS_recv : Accumulator : Sum.u64 = 1345; SumSQ.u64 = 1345; Count.u64 = 1345; Min.u64 = 1; Max.u64 = 1; 
+ l1cache6.GetX_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; 
  l1cache6.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2681,9 +2681,9 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (116296 clocks)
  l1cache7.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache7.NULLCMD_recv : Accumulator : Sum.u64 = 406; SumSQ.u64 = 406; Count.u64 = 406; Min.u64 = 1; Max.u64 = 1; 
- l1cache7.GetS_recv : Accumulator : Sum.u64 = 1690; SumSQ.u64 = 1690; Count.u64 = 1690; Min.u64 = 1; Max.u64 = 1; 
- l1cache7.GetX_recv : Accumulator : Sum.u64 = 216; SumSQ.u64 = 216; Count.u64 = 216; Min.u64 = 1; Max.u64 = 1; 
+ l1cache7.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache7.GetS_recv : Accumulator : Sum.u64 = 1345; SumSQ.u64 = 1345; Count.u64 = 1345; Min.u64 = 1; Max.u64 = 1; 
+ l1cache7.GetX_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; 
  l1cache7.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3113,7 +3113,7 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (116296 clocks)
  l3cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.GetS_recv : Accumulator : Sum.u64 = 3800; SumSQ.u64 = 3800; Count.u64 = 3800; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetS_recv : Accumulator : Sum.u64 = 3799; SumSQ.u64 = 3799; Count.u64 = 3799; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.GetX_recv : Accumulator : Sum.u64 = 383; SumSQ.u64 = 383; Count.u64 = 383; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_1_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_1_MC.out
index 7c7efb136..f5e59912a 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_1_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_1_MC.out
@@ -154,9 +154,9 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (116860 clocks)
  l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetS_recv : Accumulator : Sum.u64 = 1676; SumSQ.u64 = 1676; Count.u64 = 1676; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetX_recv : Accumulator : Sum.u64 = 194; SumSQ.u64 = 194; Count.u64 = 194; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache0.GetS_recv : Accumulator : Sum.u64 = 1345; SumSQ.u64 = 1345; Count.u64 = 1345; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetX_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -515,9 +515,9 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (116860 clocks)
  l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 392; SumSQ.u64 = 392; Count.u64 = 392; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetS_recv : Accumulator : Sum.u64 = 1686; SumSQ.u64 = 1686; Count.u64 = 1686; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetX_recv : Accumulator : Sum.u64 = 206; SumSQ.u64 = 206; Count.u64 = 206; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache1.GetS_recv : Accumulator : Sum.u64 = 1337; SumSQ.u64 = 1337; Count.u64 = 1337; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetX_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -876,9 +876,9 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (116860 clocks)
  l1cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 383; SumSQ.u64 = 383; Count.u64 = 383; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetS_recv : Accumulator : Sum.u64 = 1697; SumSQ.u64 = 1697; Count.u64 = 1697; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetX_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache2.GetS_recv : Accumulator : Sum.u64 = 1347; SumSQ.u64 = 1347; Count.u64 = 1347; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetX_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1237,9 +1237,9 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (116860 clocks)
  l1cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 409; SumSQ.u64 = 409; Count.u64 = 409; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetS_recv : Accumulator : Sum.u64 = 1680; SumSQ.u64 = 1680; Count.u64 = 1680; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetX_recv : Accumulator : Sum.u64 = 229; SumSQ.u64 = 229; Count.u64 = 229; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache3.GetS_recv : Accumulator : Sum.u64 = 1328; SumSQ.u64 = 1328; Count.u64 = 1328; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetX_recv : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1598,9 +1598,9 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (116860 clocks)
  l1cache4.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 394; SumSQ.u64 = 394; Count.u64 = 394; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetS_recv : Accumulator : Sum.u64 = 1728; SumSQ.u64 = 1728; Count.u64 = 1728; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetX_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache4.GetS_recv : Accumulator : Sum.u64 = 1371; SumSQ.u64 = 1371; Count.u64 = 1371; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetX_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1959,9 +1959,9 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (116860 clocks)
  l1cache5.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 433; SumSQ.u64 = 433; Count.u64 = 433; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetS_recv : Accumulator : Sum.u64 = 1742; SumSQ.u64 = 1742; Count.u64 = 1742; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetX_recv : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache5.GetS_recv : Accumulator : Sum.u64 = 1343; SumSQ.u64 = 1343; Count.u64 = 1343; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetX_recv : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2320,9 +2320,9 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (116860 clocks)
  l1cache6.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache6.NULLCMD_recv : Accumulator : Sum.u64 = 421; SumSQ.u64 = 421; Count.u64 = 421; Min.u64 = 1; Max.u64 = 1; 
- l1cache6.GetS_recv : Accumulator : Sum.u64 = 1720; SumSQ.u64 = 1720; Count.u64 = 1720; Min.u64 = 1; Max.u64 = 1; 
- l1cache6.GetX_recv : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; 
+ l1cache6.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache6.GetS_recv : Accumulator : Sum.u64 = 1345; SumSQ.u64 = 1345; Count.u64 = 1345; Min.u64 = 1; Max.u64 = 1; 
+ l1cache6.GetX_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; 
  l1cache6.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2681,9 +2681,9 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (116860 clocks)
  l1cache7.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache7.NULLCMD_recv : Accumulator : Sum.u64 = 406; SumSQ.u64 = 406; Count.u64 = 406; Min.u64 = 1; Max.u64 = 1; 
- l1cache7.GetS_recv : Accumulator : Sum.u64 = 1690; SumSQ.u64 = 1690; Count.u64 = 1690; Min.u64 = 1; Max.u64 = 1; 
- l1cache7.GetX_recv : Accumulator : Sum.u64 = 216; SumSQ.u64 = 216; Count.u64 = 216; Min.u64 = 1; Max.u64 = 1; 
+ l1cache7.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache7.GetS_recv : Accumulator : Sum.u64 = 1345; SumSQ.u64 = 1345; Count.u64 = 1345; Min.u64 = 1; Max.u64 = 1; 
+ l1cache7.GetX_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; 
  l1cache7.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3113,7 +3113,7 @@ TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (116860 clocks)
  l3cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.GetS_recv : Accumulator : Sum.u64 = 3800; SumSQ.u64 = 3800; Count.u64 = 3800; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetS_recv : Accumulator : Sum.u64 = 3799; SumSQ.u64 = 3799; Count.u64 = 3799; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.GetX_recv : Accumulator : Sum.u64 = 383; SumSQ.u64 = 383; Count.u64 = 383; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_2.out
index cc1f58da8..883ce2d6a 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_2.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_2.out
@@ -154,16 +154,16 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (126699 clocks)
  l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 430; SumSQ.u64 = 430; Count.u64 = 430; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetS_recv : Accumulator : Sum.u64 = 1695; SumSQ.u64 = 1695; Count.u64 = 1695; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetX_recv : Accumulator : Sum.u64 = 235; SumSQ.u64 = 235; Count.u64 = 235; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache0.GetS_recv : Accumulator : Sum.u64 = 1321; SumSQ.u64 = 1321; Count.u64 = 1321; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetX_recv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 1473; SumSQ.u64 = 1473; Count.u64 = 1473; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.Inv_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.Inv_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; 
@@ -367,7 +367,7 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (126699 clocks)
  l2cache0.PutM_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.PutE_recv : Accumulator : Sum.u64 = 1226; SumSQ.u64 = 1226; Count.u64 = 1226; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.Inv_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.Inv_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; 
@@ -515,9 +515,9 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (126699 clocks)
  l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetS_recv : Accumulator : Sum.u64 = 1672; SumSQ.u64 = 1672; Count.u64 = 1672; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetX_recv : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache1.GetS_recv : Accumulator : Sum.u64 = 1354; SumSQ.u64 = 1354; Count.u64 = 1354; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetX_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -876,16 +876,16 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (126699 clocks)
  l1cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 397; SumSQ.u64 = 397; Count.u64 = 397; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetS_recv : Accumulator : Sum.u64 = 1695; SumSQ.u64 = 1695; Count.u64 = 1695; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetX_recv : Accumulator : Sum.u64 = 202; SumSQ.u64 = 202; Count.u64 = 202; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache2.GetS_recv : Accumulator : Sum.u64 = 1338; SumSQ.u64 = 1338; Count.u64 = 1338; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetX_recv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 1482; SumSQ.u64 = 1482; Count.u64 = 1482; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.Inv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.Inv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
@@ -1089,7 +1089,7 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (126699 clocks)
  l2cache2.PutM_recv : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.PutE_recv : Accumulator : Sum.u64 = 1240; SumSQ.u64 = 1240; Count.u64 = 1240; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.Inv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.Inv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; 
@@ -1237,9 +1237,9 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (126699 clocks)
  l1cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 390; SumSQ.u64 = 390; Count.u64 = 390; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetS_recv : Accumulator : Sum.u64 = 1710; SumSQ.u64 = 1710; Count.u64 = 1710; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetX_recv : Accumulator : Sum.u64 = 180; SumSQ.u64 = 180; Count.u64 = 180; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache3.GetS_recv : Accumulator : Sum.u64 = 1348; SumSQ.u64 = 1348; Count.u64 = 1348; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetX_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1598,9 +1598,9 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (126699 clocks)
  l1cache4.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 393; SumSQ.u64 = 393; Count.u64 = 393; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetS_recv : Accumulator : Sum.u64 = 1727; SumSQ.u64 = 1727; Count.u64 = 1727; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetX_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache4.GetS_recv : Accumulator : Sum.u64 = 1377; SumSQ.u64 = 1377; Count.u64 = 1377; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetX_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1811,7 +1811,7 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (126699 clocks)
  l2cache4.PutM_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.PutE_recv : Accumulator : Sum.u64 = 1280; SumSQ.u64 = 1280; Count.u64 = 1280; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.Inv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.Inv_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.Fetch_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; 
@@ -1959,9 +1959,9 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (126699 clocks)
  l1cache5.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 418; SumSQ.u64 = 418; Count.u64 = 418; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetS_recv : Accumulator : Sum.u64 = 1696; SumSQ.u64 = 1696; Count.u64 = 1696; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetX_recv : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache5.GetS_recv : Accumulator : Sum.u64 = 1347; SumSQ.u64 = 1347; Count.u64 = 1347; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetX_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2320,9 +2320,9 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (126699 clocks)
  l1cache6.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache6.NULLCMD_recv : Accumulator : Sum.u64 = 392; SumSQ.u64 = 392; Count.u64 = 392; Min.u64 = 1; Max.u64 = 1; 
- l1cache6.GetS_recv : Accumulator : Sum.u64 = 1679; SumSQ.u64 = 1679; Count.u64 = 1679; Min.u64 = 1; Max.u64 = 1; 
- l1cache6.GetX_recv : Accumulator : Sum.u64 = 213; SumSQ.u64 = 213; Count.u64 = 213; Min.u64 = 1; Max.u64 = 1; 
+ l1cache6.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache6.GetS_recv : Accumulator : Sum.u64 = 1337; SumSQ.u64 = 1337; Count.u64 = 1337; Min.u64 = 1; Max.u64 = 1; 
+ l1cache6.GetX_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
  l1cache6.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2533,10 +2533,10 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (126699 clocks)
  l2cache6.PutM_recv : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; 
  l2cache6.PutE_recv : Accumulator : Sum.u64 = 1243; SumSQ.u64 = 1243; Count.u64 = 1243; Min.u64 = 1; Max.u64 = 1; 
  l2cache6.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache6.Inv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
+ l2cache6.Inv_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
  l2cache6.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache6.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache6.FetchInv_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; 
+ l2cache6.FetchInv_recv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; 
  l2cache6.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache6.FetchResp_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; 
  l2cache6.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2681,16 +2681,16 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (126699 clocks)
  l1cache7.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache7.NULLCMD_recv : Accumulator : Sum.u64 = 407; SumSQ.u64 = 407; Count.u64 = 407; Min.u64 = 1; Max.u64 = 1; 
- l1cache7.GetS_recv : Accumulator : Sum.u64 = 1726; SumSQ.u64 = 1726; Count.u64 = 1726; Min.u64 = 1; Max.u64 = 1; 
- l1cache7.GetX_recv : Accumulator : Sum.u64 = 181; SumSQ.u64 = 181; Count.u64 = 181; Min.u64 = 1; Max.u64 = 1; 
+ l1cache7.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache7.GetS_recv : Accumulator : Sum.u64 = 1356; SumSQ.u64 = 1356; Count.u64 = 1356; Min.u64 = 1; Max.u64 = 1; 
+ l1cache7.GetX_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; 
  l1cache7.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.GetSResp_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
  l1cache7.GetXResp_recv : Accumulator : Sum.u64 = 1485; SumSQ.u64 = 1485; Count.u64 = 1485; Min.u64 = 1; Max.u64 = 1; 
  l1cache7.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache7.Inv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
+ l1cache7.Inv_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
  l1cache7.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.FetchInv_recv : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; 
@@ -2894,7 +2894,7 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (126699 clocks)
  l2cache7.PutM_recv : Accumulator : Sum.u64 = 133; SumSQ.u64 = 133; Count.u64 = 133; Min.u64 = 1; Max.u64 = 1; 
  l2cache7.PutE_recv : Accumulator : Sum.u64 = 1270; SumSQ.u64 = 1270; Count.u64 = 1270; Min.u64 = 1; Max.u64 = 1; 
  l2cache7.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache7.Inv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
+ l2cache7.Inv_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
  l2cache7.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache7.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache7.FetchInv_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; 
@@ -3128,9 +3128,9 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (126699 clocks)
  l3cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 412; SumSQ.u64 = 412; Count.u64 = 412; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.GetS_recv : Accumulator : Sum.u64 = 4355; SumSQ.u64 = 4355; Count.u64 = 4355; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.GetX_recv : Accumulator : Sum.u64 = 457; SumSQ.u64 = 457; Count.u64 = 457; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache0.GetS_recv : Accumulator : Sum.u64 = 4029; SumSQ.u64 = 4029; Count.u64 = 4029; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetX_recv : Accumulator : Sum.u64 = 417; SumSQ.u64 = 417; Count.u64 = 417; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3375,9 +3375,9 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (126699 clocks)
  l3cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.NULLCMD_recv : Accumulator : Sum.u64 = 359; SumSQ.u64 = 359; Count.u64 = 359; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.GetS_recv : Accumulator : Sum.u64 = 3658; SumSQ.u64 = 3658; Count.u64 = 3658; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.GetX_recv : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache1.GetS_recv : Accumulator : Sum.u64 = 3379; SumSQ.u64 = 3379; Count.u64 = 3379; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetX_recv : Accumulator : Sum.u64 = 349; SumSQ.u64 = 349; Count.u64 = 349; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3622,9 +3622,9 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (126699 clocks)
  l3cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache2.NULLCMD_recv : Accumulator : Sum.u64 = 414; SumSQ.u64 = 414; Count.u64 = 414; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.GetS_recv : Accumulator : Sum.u64 = 4191; SumSQ.u64 = 4191; Count.u64 = 4191; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.GetX_recv : Accumulator : Sum.u64 = 489; SumSQ.u64 = 489; Count.u64 = 489; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache2.GetS_recv : Accumulator : Sum.u64 = 3858; SumSQ.u64 = 3858; Count.u64 = 3858; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetX_recv : Accumulator : Sum.u64 = 452; SumSQ.u64 = 452; Count.u64 = 452; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3869,9 +3869,9 @@ TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (126699 clocks)
  l3cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache3.NULLCMD_recv : Accumulator : Sum.u64 = 343; SumSQ.u64 = 343; Count.u64 = 343; Min.u64 = 1; Max.u64 = 1; 
- l3cache3.GetS_recv : Accumulator : Sum.u64 = 3341; SumSQ.u64 = 3341; Count.u64 = 3341; Min.u64 = 1; Max.u64 = 1; 
- l3cache3.GetX_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; 
+ l3cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache3.GetS_recv : Accumulator : Sum.u64 = 3063; SumSQ.u64 = 3063; Count.u64 = 3063; Min.u64 = 1; Max.u64 = 1; 
+ l3cache3.GetX_recv : Accumulator : Sum.u64 = 342; SumSQ.u64 = 342; Count.u64 = 342; Min.u64 = 1; Max.u64 = 1; 
  l3cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_2_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_2_MC.out
index 35b5b7aea..fa2174d14 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_2_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_2_MC.out
@@ -16,8 +16,8 @@ TrivialCPU cpu3 Finished after 1500 issued reads, 1500 returned (132635 clocks)
 TrivialCPU cpu0 Finished after 1500 issued reads, 1500 returned (129814 clocks)
 TrivialCPU cpu6 Finished after 1500 issued reads, 1500 returned (126699 clocks)
 TrivialCPU cpu1 Finished after 1500 issued reads, 1500 returned (129409 clocks)
-TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (128179 clocks)
 TrivialCPU cpu7 Finished after 1500 issued reads, 1500 returned (127644 clocks)
+TrivialCPU cpu2 Finished after 1500 issued reads, 1500 returned (128179 clocks)
  cpu0.pendCycle : Accumulator : Sum.u64 = 1285498; SumSQ.u64 = 12772134; Count.u64 = 129814; Min.u64 = 0; Max.u64 = 10; 
  l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1321; SumSQ.u64 = 1321; Count.u64 = 1321; Min.u64 = 1; Max.u64 = 1; 
@@ -154,16 +154,16 @@ TrivialCPU cpu7 Finished after 1500 issued reads, 1500 returned (127644 clocks)
  l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 430; SumSQ.u64 = 430; Count.u64 = 430; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetS_recv : Accumulator : Sum.u64 = 1695; SumSQ.u64 = 1695; Count.u64 = 1695; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetX_recv : Accumulator : Sum.u64 = 235; SumSQ.u64 = 235; Count.u64 = 235; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache0.GetS_recv : Accumulator : Sum.u64 = 1321; SumSQ.u64 = 1321; Count.u64 = 1321; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetX_recv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 1473; SumSQ.u64 = 1473; Count.u64 = 1473; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.Inv_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.Inv_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; 
@@ -367,7 +367,7 @@ TrivialCPU cpu7 Finished after 1500 issued reads, 1500 returned (127644 clocks)
  l2cache0.PutM_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.PutE_recv : Accumulator : Sum.u64 = 1226; SumSQ.u64 = 1226; Count.u64 = 1226; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.Inv_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.Inv_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; 
@@ -515,9 +515,9 @@ TrivialCPU cpu7 Finished after 1500 issued reads, 1500 returned (127644 clocks)
  l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetS_recv : Accumulator : Sum.u64 = 1672; SumSQ.u64 = 1672; Count.u64 = 1672; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetX_recv : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache1.GetS_recv : Accumulator : Sum.u64 = 1354; SumSQ.u64 = 1354; Count.u64 = 1354; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetX_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -876,16 +876,16 @@ TrivialCPU cpu7 Finished after 1500 issued reads, 1500 returned (127644 clocks)
  l1cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 397; SumSQ.u64 = 397; Count.u64 = 397; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetS_recv : Accumulator : Sum.u64 = 1695; SumSQ.u64 = 1695; Count.u64 = 1695; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetX_recv : Accumulator : Sum.u64 = 202; SumSQ.u64 = 202; Count.u64 = 202; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache2.GetS_recv : Accumulator : Sum.u64 = 1338; SumSQ.u64 = 1338; Count.u64 = 1338; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetX_recv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 1482; SumSQ.u64 = 1482; Count.u64 = 1482; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.Inv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.Inv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; 
@@ -1089,7 +1089,7 @@ TrivialCPU cpu7 Finished after 1500 issued reads, 1500 returned (127644 clocks)
  l2cache2.PutM_recv : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.PutE_recv : Accumulator : Sum.u64 = 1240; SumSQ.u64 = 1240; Count.u64 = 1240; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.Inv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.Inv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; 
@@ -1237,9 +1237,9 @@ TrivialCPU cpu7 Finished after 1500 issued reads, 1500 returned (127644 clocks)
  l1cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 390; SumSQ.u64 = 390; Count.u64 = 390; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetS_recv : Accumulator : Sum.u64 = 1710; SumSQ.u64 = 1710; Count.u64 = 1710; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetX_recv : Accumulator : Sum.u64 = 180; SumSQ.u64 = 180; Count.u64 = 180; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache3.GetS_recv : Accumulator : Sum.u64 = 1348; SumSQ.u64 = 1348; Count.u64 = 1348; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetX_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1598,9 +1598,9 @@ TrivialCPU cpu7 Finished after 1500 issued reads, 1500 returned (127644 clocks)
  l1cache4.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 393; SumSQ.u64 = 393; Count.u64 = 393; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetS_recv : Accumulator : Sum.u64 = 1727; SumSQ.u64 = 1727; Count.u64 = 1727; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetX_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache4.GetS_recv : Accumulator : Sum.u64 = 1377; SumSQ.u64 = 1377; Count.u64 = 1377; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetX_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1811,7 +1811,7 @@ TrivialCPU cpu7 Finished after 1500 issued reads, 1500 returned (127644 clocks)
  l2cache4.PutM_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.PutE_recv : Accumulator : Sum.u64 = 1280; SumSQ.u64 = 1280; Count.u64 = 1280; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.Inv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.Inv_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.Fetch_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; 
@@ -1959,9 +1959,9 @@ TrivialCPU cpu7 Finished after 1500 issued reads, 1500 returned (127644 clocks)
  l1cache5.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 418; SumSQ.u64 = 418; Count.u64 = 418; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetS_recv : Accumulator : Sum.u64 = 1696; SumSQ.u64 = 1696; Count.u64 = 1696; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetX_recv : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache5.GetS_recv : Accumulator : Sum.u64 = 1347; SumSQ.u64 = 1347; Count.u64 = 1347; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetX_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2320,9 +2320,9 @@ TrivialCPU cpu7 Finished after 1500 issued reads, 1500 returned (127644 clocks)
  l1cache6.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache6.NULLCMD_recv : Accumulator : Sum.u64 = 392; SumSQ.u64 = 392; Count.u64 = 392; Min.u64 = 1; Max.u64 = 1; 
- l1cache6.GetS_recv : Accumulator : Sum.u64 = 1679; SumSQ.u64 = 1679; Count.u64 = 1679; Min.u64 = 1; Max.u64 = 1; 
- l1cache6.GetX_recv : Accumulator : Sum.u64 = 213; SumSQ.u64 = 213; Count.u64 = 213; Min.u64 = 1; Max.u64 = 1; 
+ l1cache6.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache6.GetS_recv : Accumulator : Sum.u64 = 1337; SumSQ.u64 = 1337; Count.u64 = 1337; Min.u64 = 1; Max.u64 = 1; 
+ l1cache6.GetX_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; 
  l1cache6.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2533,10 +2533,10 @@ TrivialCPU cpu7 Finished after 1500 issued reads, 1500 returned (127644 clocks)
  l2cache6.PutM_recv : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; 
  l2cache6.PutE_recv : Accumulator : Sum.u64 = 1243; SumSQ.u64 = 1243; Count.u64 = 1243; Min.u64 = 1; Max.u64 = 1; 
  l2cache6.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache6.Inv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
+ l2cache6.Inv_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
  l2cache6.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache6.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache6.FetchInv_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; 
+ l2cache6.FetchInv_recv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; 
  l2cache6.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache6.FetchResp_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; 
  l2cache6.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2681,16 +2681,16 @@ TrivialCPU cpu7 Finished after 1500 issued reads, 1500 returned (127644 clocks)
  l1cache7.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache7.NULLCMD_recv : Accumulator : Sum.u64 = 407; SumSQ.u64 = 407; Count.u64 = 407; Min.u64 = 1; Max.u64 = 1; 
- l1cache7.GetS_recv : Accumulator : Sum.u64 = 1726; SumSQ.u64 = 1726; Count.u64 = 1726; Min.u64 = 1; Max.u64 = 1; 
- l1cache7.GetX_recv : Accumulator : Sum.u64 = 181; SumSQ.u64 = 181; Count.u64 = 181; Min.u64 = 1; Max.u64 = 1; 
+ l1cache7.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache7.GetS_recv : Accumulator : Sum.u64 = 1356; SumSQ.u64 = 1356; Count.u64 = 1356; Min.u64 = 1; Max.u64 = 1; 
+ l1cache7.GetX_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; 
  l1cache7.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.GetSResp_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
  l1cache7.GetXResp_recv : Accumulator : Sum.u64 = 1485; SumSQ.u64 = 1485; Count.u64 = 1485; Min.u64 = 1; Max.u64 = 1; 
  l1cache7.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache7.Inv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
+ l1cache7.Inv_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
  l1cache7.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache7.FetchInv_recv : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; 
@@ -2894,7 +2894,7 @@ TrivialCPU cpu7 Finished after 1500 issued reads, 1500 returned (127644 clocks)
  l2cache7.PutM_recv : Accumulator : Sum.u64 = 133; SumSQ.u64 = 133; Count.u64 = 133; Min.u64 = 1; Max.u64 = 1; 
  l2cache7.PutE_recv : Accumulator : Sum.u64 = 1270; SumSQ.u64 = 1270; Count.u64 = 1270; Min.u64 = 1; Max.u64 = 1; 
  l2cache7.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache7.Inv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
+ l2cache7.Inv_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
  l2cache7.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache7.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache7.FetchInv_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; 
@@ -3128,9 +3128,9 @@ TrivialCPU cpu7 Finished after 1500 issued reads, 1500 returned (127644 clocks)
  l3cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 412; SumSQ.u64 = 412; Count.u64 = 412; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.GetS_recv : Accumulator : Sum.u64 = 4355; SumSQ.u64 = 4355; Count.u64 = 4355; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.GetX_recv : Accumulator : Sum.u64 = 457; SumSQ.u64 = 457; Count.u64 = 457; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache0.GetS_recv : Accumulator : Sum.u64 = 4029; SumSQ.u64 = 4029; Count.u64 = 4029; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetX_recv : Accumulator : Sum.u64 = 417; SumSQ.u64 = 417; Count.u64 = 417; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3375,9 +3375,9 @@ TrivialCPU cpu7 Finished after 1500 issued reads, 1500 returned (127644 clocks)
  l3cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.NULLCMD_recv : Accumulator : Sum.u64 = 359; SumSQ.u64 = 359; Count.u64 = 359; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.GetS_recv : Accumulator : Sum.u64 = 3658; SumSQ.u64 = 3658; Count.u64 = 3658; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.GetX_recv : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache1.GetS_recv : Accumulator : Sum.u64 = 3379; SumSQ.u64 = 3379; Count.u64 = 3379; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetX_recv : Accumulator : Sum.u64 = 349; SumSQ.u64 = 349; Count.u64 = 349; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3622,9 +3622,9 @@ TrivialCPU cpu7 Finished after 1500 issued reads, 1500 returned (127644 clocks)
  l3cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache2.NULLCMD_recv : Accumulator : Sum.u64 = 414; SumSQ.u64 = 414; Count.u64 = 414; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.GetS_recv : Accumulator : Sum.u64 = 4191; SumSQ.u64 = 4191; Count.u64 = 4191; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.GetX_recv : Accumulator : Sum.u64 = 489; SumSQ.u64 = 489; Count.u64 = 489; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache2.GetS_recv : Accumulator : Sum.u64 = 3858; SumSQ.u64 = 3858; Count.u64 = 3858; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetX_recv : Accumulator : Sum.u64 = 452; SumSQ.u64 = 452; Count.u64 = 452; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3869,9 +3869,9 @@ TrivialCPU cpu7 Finished after 1500 issued reads, 1500 returned (127644 clocks)
  l3cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache3.NULLCMD_recv : Accumulator : Sum.u64 = 343; SumSQ.u64 = 343; Count.u64 = 343; Min.u64 = 1; Max.u64 = 1; 
- l3cache3.GetS_recv : Accumulator : Sum.u64 = 3341; SumSQ.u64 = 3341; Count.u64 = 3341; Min.u64 = 1; Max.u64 = 1; 
- l3cache3.GetX_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; 
+ l3cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3cache3.GetS_recv : Accumulator : Sum.u64 = 3063; SumSQ.u64 = 3063; Count.u64 = 3063; Min.u64 = 1; Max.u64 = 1; 
+ l3cache3.GetX_recv : Accumulator : Sum.u64 = 342; SumSQ.u64 = 342; Count.u64 = 342; Min.u64 = 1; Max.u64 = 1; 
  l3cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_PrefetchParams.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_PrefetchParams.out
index 18607a7f9..eea68a255 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_PrefetchParams.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_PrefetchParams.out
@@ -153,19 +153,19 @@ Completed @ 5450 ns
  l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.GetS_recv : Accumulator : Sum.u64 = 2715; SumSQ.u64 = 2715; Count.u64 = 2715; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetX_recv : Accumulator : Sum.u64 = 273; SumSQ.u64 = 273; Count.u64 = 273; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetS_recv : Accumulator : Sum.u64 = 1602; SumSQ.u64 = 1602; Count.u64 = 1602; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetX_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.Inv_recv : Accumulator : Sum.u64 = 167; SumSQ.u64 = 167; Count.u64 = 167; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 86095; SumSQ.u64 = 729125; Count.u64 = 13071; Min.u64 = 0; Max.u64 = 11; 
@@ -384,7 +384,7 @@ Completed @ 5450 ns
  l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.GetS_recv : Accumulator : Sum.u64 = 393; SumSQ.u64 = 393; Count.u64 = 393; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.GetS_recv : Accumulator : Sum.u64 = 416; SumSQ.u64 = 416; Count.u64 = 416; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.GetX_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -396,11 +396,11 @@ Completed @ 5450 ns
  l2cache0.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.Inv_recv : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.Inv_recv : Accumulator : Sum.u64 = 167; SumSQ.u64 = 167; Count.u64 = 167; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; 
- l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 202; SumSQ.u64 = 202; Count.u64 = 202; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -551,19 +551,19 @@ Completed @ 5450 ns
  l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.GetS_recv : Accumulator : Sum.u64 = 2717; SumSQ.u64 = 2717; Count.u64 = 2717; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetX_recv : Accumulator : Sum.u64 = 267; SumSQ.u64 = 267; Count.u64 = 267; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetS_recv : Accumulator : Sum.u64 = 1624; SumSQ.u64 = 1624; Count.u64 = 1624; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetX_recv : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.Inv_recv : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 92000; SumSQ.u64 = 787278; Count.u64 = 13071; Min.u64 = 0; Max.u64 = 11; 
@@ -782,8 +782,8 @@ Completed @ 5450 ns
  l2cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.GetS_recv : Accumulator : Sum.u64 = 414; SumSQ.u64 = 414; Count.u64 = 414; Min.u64 = 1; Max.u64 = 1; 
- l2cache1.GetX_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.GetS_recv : Accumulator : Sum.u64 = 439; SumSQ.u64 = 439; Count.u64 = 439; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.GetX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -794,11 +794,11 @@ Completed @ 5450 ns
  l2cache1.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.Inv_recv : Accumulator : Sum.u64 = 343; SumSQ.u64 = 343; Count.u64 = 343; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.Inv_recv : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; 
- l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -949,15 +949,15 @@ Completed @ 5450 ns
  l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.GetS_recv : Accumulator : Sum.u64 = 2715; SumSQ.u64 = 2715; Count.u64 = 2715; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetX_recv : Accumulator : Sum.u64 = 230; SumSQ.u64 = 230; Count.u64 = 230; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetS_recv : Accumulator : Sum.u64 = 1628; SumSQ.u64 = 1628; Count.u64 = 1628; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetX_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.Inv_recv : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.Inv_recv : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
@@ -1180,7 +1180,7 @@ Completed @ 5450 ns
  l2cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.GetS_recv : Accumulator : Sum.u64 = 398; SumSQ.u64 = 398; Count.u64 = 398; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.GetS_recv : Accumulator : Sum.u64 = 427; SumSQ.u64 = 427; Count.u64 = 427; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetX_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1192,11 +1192,11 @@ Completed @ 5450 ns
  l2cache2.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.Inv_recv : Accumulator : Sum.u64 = 349; SumSQ.u64 = 349; Count.u64 = 349; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.Inv_recv : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
- l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1347,15 +1347,15 @@ Completed @ 5450 ns
  l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.GetS_recv : Accumulator : Sum.u64 = 2665; SumSQ.u64 = 2665; Count.u64 = 2665; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetX_recv : Accumulator : Sum.u64 = 300; SumSQ.u64 = 300; Count.u64 = 300; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetS_recv : Accumulator : Sum.u64 = 1624; SumSQ.u64 = 1624; Count.u64 = 1624; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetX_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 177; SumSQ.u64 = 177; Count.u64 = 177; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.Inv_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.Inv_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
@@ -1578,8 +1578,8 @@ Completed @ 5450 ns
  l2cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.GetS_recv : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; 
- l2cache3.GetX_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.GetS_recv : Accumulator : Sum.u64 = 454; SumSQ.u64 = 454; Count.u64 = 454; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.GetX_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1590,11 +1590,11 @@ Completed @ 5450 ns
  l2cache3.PutM_recv : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.Inv_recv : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.Inv_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
- l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1745,13 +1745,13 @@ Completed @ 5450 ns
  l1cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.GetS_recv : Accumulator : Sum.u64 = 2625; SumSQ.u64 = 2625; Count.u64 = 2625; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetX_recv : Accumulator : Sum.u64 = 259; SumSQ.u64 = 259; Count.u64 = 259; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetS_recv : Accumulator : Sum.u64 = 1619; SumSQ.u64 = 1619; Count.u64 = 1619; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetX_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.Inv_recv : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1976,8 +1976,8 @@ Completed @ 5450 ns
  l2cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.GetS_recv : Accumulator : Sum.u64 = 394; SumSQ.u64 = 394; Count.u64 = 394; Min.u64 = 1; Max.u64 = 1; 
- l2cache4.GetX_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.GetS_recv : Accumulator : Sum.u64 = 431; SumSQ.u64 = 431; Count.u64 = 431; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.GetX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1988,11 +1988,11 @@ Completed @ 5450 ns
  l2cache4.PutM_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.Inv_recv : Accumulator : Sum.u64 = 337; SumSQ.u64 = 337; Count.u64 = 337; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.Inv_recv : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; 
- l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FetchResp_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FetchXResp_recv : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2143,19 +2143,19 @@ Completed @ 5450 ns
  l1cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.GetS_recv : Accumulator : Sum.u64 = 2673; SumSQ.u64 = 2673; Count.u64 = 2673; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetX_recv : Accumulator : Sum.u64 = 259; SumSQ.u64 = 259; Count.u64 = 259; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetS_recv : Accumulator : Sum.u64 = 1631; SumSQ.u64 = 1631; Count.u64 = 1631; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetX_recv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 177; SumSQ.u64 = 177; Count.u64 = 177; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.Inv_recv : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.Inv_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FetchInv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.FetchInvX_recv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.FetchInvX_recv : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.MSHR_occupancy : Accumulator : Sum.u64 = 96904; SumSQ.u64 = 841686; Count.u64 = 13071; Min.u64 = 0; Max.u64 = 11; 
@@ -2374,8 +2374,8 @@ Completed @ 5450 ns
  l2cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.GetS_recv : Accumulator : Sum.u64 = 414; SumSQ.u64 = 414; Count.u64 = 414; Min.u64 = 1; Max.u64 = 1; 
- l2cache5.GetX_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.GetS_recv : Accumulator : Sum.u64 = 450; SumSQ.u64 = 450; Count.u64 = 450; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.GetX_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2386,11 +2386,11 @@ Completed @ 5450 ns
  l2cache5.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.Inv_recv : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.Inv_recv : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; 
- l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.FetchResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.FetchXResp_recv : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2605,8 +2605,8 @@ Completed @ 5450 ns
  l3cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.GetS_recv : Accumulator : Sum.u64 = 530; SumSQ.u64 = 530; Count.u64 = 530; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.GetX_recv : Accumulator : Sum.u64 = 407; SumSQ.u64 = 407; Count.u64 = 407; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetS_recv : Accumulator : Sum.u64 = 328; SumSQ.u64 = 328; Count.u64 = 328; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetX_recv : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2625,7 +2625,7 @@ Completed @ 5450 ns
  l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.AckInv_recv : Accumulator : Sum.u64 = 361; SumSQ.u64 = 361; Count.u64 = 361; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.AckInv_recv : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 10042; SumSQ.u64 = 23122; Count.u64 = 7633; Min.u64 = 0; Max.u64 = 6; 
  l3cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2836,8 +2836,8 @@ Completed @ 5450 ns
  l3cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.GetS_recv : Accumulator : Sum.u64 = 561; SumSQ.u64 = 561; Count.u64 = 561; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.GetX_recv : Accumulator : Sum.u64 = 444; SumSQ.u64 = 444; Count.u64 = 444; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetS_recv : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetX_recv : Accumulator : Sum.u64 = 213; SumSQ.u64 = 213; Count.u64 = 213; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2856,7 +2856,7 @@ Completed @ 5450 ns
  l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.AckInv_recv : Accumulator : Sum.u64 = 357; SumSQ.u64 = 357; Count.u64 = 357; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.AckInv_recv : Accumulator : Sum.u64 = 327; SumSQ.u64 = 327; Count.u64 = 327; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 10485; SumSQ.u64 = 24221; Count.u64 = 7633; Min.u64 = 0; Max.u64 = 6; 
  l3cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3067,8 +3067,8 @@ Completed @ 5450 ns
  l3cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache2.GetS_recv : Accumulator : Sum.u64 = 575; SumSQ.u64 = 575; Count.u64 = 575; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.GetX_recv : Accumulator : Sum.u64 = 429; SumSQ.u64 = 429; Count.u64 = 429; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetS_recv : Accumulator : Sum.u64 = 344; SumSQ.u64 = 344; Count.u64 = 344; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetX_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3087,7 +3087,7 @@ Completed @ 5450 ns
  l3cache2.FetchResp_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 180; SumSQ.u64 = 180; Count.u64 = 180; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache2.AckInv_recv : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.AckInv_recv : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.MSHR_occupancy : Accumulator : Sum.u64 = 10452; SumSQ.u64 = 23906; Count.u64 = 7633; Min.u64 = 0; Max.u64 = 6; 
  l3cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_PrefetchParams_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_PrefetchParams_MC.out
index 2630bc504..eea68a255 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_PrefetchParams_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_PrefetchParams_MC.out
@@ -3,12 +3,12 @@ Completed @ 5450 ns
 streamCPU Finished after 1500 issued reads, 1500 returned
 Completed @ 5450 ns
 streamCPU Finished after 1500 issued reads, 1500 returned
-streamCPU Finished after 1500 issued reads, 1500 returned
-Completed @ 5450 ns
 Completed @ 5450 ns
 streamCPU Finished after 1500 issued reads, 1500 returned
+Completed @ 5450 ns
 streamCPU Finished after 1500 issued reads, 1500 returned
 Completed @ 5450 ns
+streamCPU Finished after 1500 issued reads, 1500 returned
 Completed @ 5450 ns
  l1cache0.Prefetch_requests : Accumulator : Sum.u64 = 255; SumSQ.u64 = 255; Count.u64 = 255; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.Prefetch_drops : Accumulator : Sum.u64 = 248; SumSQ.u64 = 248; Count.u64 = 248; Min.u64 = 1; Max.u64 = 1; 
@@ -153,19 +153,19 @@ Completed @ 5450 ns
  l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.GetS_recv : Accumulator : Sum.u64 = 2715; SumSQ.u64 = 2715; Count.u64 = 2715; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetX_recv : Accumulator : Sum.u64 = 273; SumSQ.u64 = 273; Count.u64 = 273; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetS_recv : Accumulator : Sum.u64 = 1602; SumSQ.u64 = 1602; Count.u64 = 1602; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetX_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.Inv_recv : Accumulator : Sum.u64 = 167; SumSQ.u64 = 167; Count.u64 = 167; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 86095; SumSQ.u64 = 729125; Count.u64 = 13071; Min.u64 = 0; Max.u64 = 11; 
@@ -384,7 +384,7 @@ Completed @ 5450 ns
  l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.GetS_recv : Accumulator : Sum.u64 = 393; SumSQ.u64 = 393; Count.u64 = 393; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.GetS_recv : Accumulator : Sum.u64 = 416; SumSQ.u64 = 416; Count.u64 = 416; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.GetX_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -396,11 +396,11 @@ Completed @ 5450 ns
  l2cache0.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.Inv_recv : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.Inv_recv : Accumulator : Sum.u64 = 167; SumSQ.u64 = 167; Count.u64 = 167; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; 
- l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 202; SumSQ.u64 = 202; Count.u64 = 202; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -551,19 +551,19 @@ Completed @ 5450 ns
  l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.GetS_recv : Accumulator : Sum.u64 = 2717; SumSQ.u64 = 2717; Count.u64 = 2717; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetX_recv : Accumulator : Sum.u64 = 267; SumSQ.u64 = 267; Count.u64 = 267; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetS_recv : Accumulator : Sum.u64 = 1624; SumSQ.u64 = 1624; Count.u64 = 1624; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetX_recv : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.Inv_recv : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 92000; SumSQ.u64 = 787278; Count.u64 = 13071; Min.u64 = 0; Max.u64 = 11; 
@@ -782,8 +782,8 @@ Completed @ 5450 ns
  l2cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.GetS_recv : Accumulator : Sum.u64 = 414; SumSQ.u64 = 414; Count.u64 = 414; Min.u64 = 1; Max.u64 = 1; 
- l2cache1.GetX_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.GetS_recv : Accumulator : Sum.u64 = 439; SumSQ.u64 = 439; Count.u64 = 439; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.GetX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -794,11 +794,11 @@ Completed @ 5450 ns
  l2cache1.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.Inv_recv : Accumulator : Sum.u64 = 343; SumSQ.u64 = 343; Count.u64 = 343; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.Inv_recv : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; 
- l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -949,15 +949,15 @@ Completed @ 5450 ns
  l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.GetS_recv : Accumulator : Sum.u64 = 2715; SumSQ.u64 = 2715; Count.u64 = 2715; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetX_recv : Accumulator : Sum.u64 = 230; SumSQ.u64 = 230; Count.u64 = 230; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetS_recv : Accumulator : Sum.u64 = 1628; SumSQ.u64 = 1628; Count.u64 = 1628; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetX_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.Inv_recv : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.Inv_recv : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
@@ -1180,7 +1180,7 @@ Completed @ 5450 ns
  l2cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.GetS_recv : Accumulator : Sum.u64 = 398; SumSQ.u64 = 398; Count.u64 = 398; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.GetS_recv : Accumulator : Sum.u64 = 427; SumSQ.u64 = 427; Count.u64 = 427; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetX_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1192,11 +1192,11 @@ Completed @ 5450 ns
  l2cache2.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.Inv_recv : Accumulator : Sum.u64 = 349; SumSQ.u64 = 349; Count.u64 = 349; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.Inv_recv : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
- l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1347,15 +1347,15 @@ Completed @ 5450 ns
  l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.GetS_recv : Accumulator : Sum.u64 = 2665; SumSQ.u64 = 2665; Count.u64 = 2665; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetX_recv : Accumulator : Sum.u64 = 300; SumSQ.u64 = 300; Count.u64 = 300; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetS_recv : Accumulator : Sum.u64 = 1624; SumSQ.u64 = 1624; Count.u64 = 1624; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetX_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 177; SumSQ.u64 = 177; Count.u64 = 177; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.Inv_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.Inv_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
@@ -1578,8 +1578,8 @@ Completed @ 5450 ns
  l2cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.GetS_recv : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; 
- l2cache3.GetX_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.GetS_recv : Accumulator : Sum.u64 = 454; SumSQ.u64 = 454; Count.u64 = 454; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.GetX_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1590,11 +1590,11 @@ Completed @ 5450 ns
  l2cache3.PutM_recv : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.Inv_recv : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.Inv_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
- l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1745,13 +1745,13 @@ Completed @ 5450 ns
  l1cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.GetS_recv : Accumulator : Sum.u64 = 2625; SumSQ.u64 = 2625; Count.u64 = 2625; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetX_recv : Accumulator : Sum.u64 = 259; SumSQ.u64 = 259; Count.u64 = 259; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetS_recv : Accumulator : Sum.u64 = 1619; SumSQ.u64 = 1619; Count.u64 = 1619; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetX_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.Inv_recv : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1976,8 +1976,8 @@ Completed @ 5450 ns
  l2cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.GetS_recv : Accumulator : Sum.u64 = 394; SumSQ.u64 = 394; Count.u64 = 394; Min.u64 = 1; Max.u64 = 1; 
- l2cache4.GetX_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.GetS_recv : Accumulator : Sum.u64 = 431; SumSQ.u64 = 431; Count.u64 = 431; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.GetX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1988,11 +1988,11 @@ Completed @ 5450 ns
  l2cache4.PutM_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.Inv_recv : Accumulator : Sum.u64 = 337; SumSQ.u64 = 337; Count.u64 = 337; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.Inv_recv : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; 
- l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FetchResp_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FetchXResp_recv : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2143,19 +2143,19 @@ Completed @ 5450 ns
  l1cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.GetS_recv : Accumulator : Sum.u64 = 2673; SumSQ.u64 = 2673; Count.u64 = 2673; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetX_recv : Accumulator : Sum.u64 = 259; SumSQ.u64 = 259; Count.u64 = 259; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetS_recv : Accumulator : Sum.u64 = 1631; SumSQ.u64 = 1631; Count.u64 = 1631; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetX_recv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 177; SumSQ.u64 = 177; Count.u64 = 177; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.Inv_recv : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.Inv_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FetchInv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.FetchInvX_recv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.FetchInvX_recv : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.MSHR_occupancy : Accumulator : Sum.u64 = 96904; SumSQ.u64 = 841686; Count.u64 = 13071; Min.u64 = 0; Max.u64 = 11; 
@@ -2374,8 +2374,8 @@ Completed @ 5450 ns
  l2cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.GetS_recv : Accumulator : Sum.u64 = 414; SumSQ.u64 = 414; Count.u64 = 414; Min.u64 = 1; Max.u64 = 1; 
- l2cache5.GetX_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.GetS_recv : Accumulator : Sum.u64 = 450; SumSQ.u64 = 450; Count.u64 = 450; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.GetX_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2386,11 +2386,11 @@ Completed @ 5450 ns
  l2cache5.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.Inv_recv : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.Inv_recv : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; 
- l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.FetchResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.FetchXResp_recv : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2605,8 +2605,8 @@ Completed @ 5450 ns
  l3cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.GetS_recv : Accumulator : Sum.u64 = 530; SumSQ.u64 = 530; Count.u64 = 530; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.GetX_recv : Accumulator : Sum.u64 = 407; SumSQ.u64 = 407; Count.u64 = 407; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetS_recv : Accumulator : Sum.u64 = 328; SumSQ.u64 = 328; Count.u64 = 328; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetX_recv : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2625,7 +2625,7 @@ Completed @ 5450 ns
  l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.AckInv_recv : Accumulator : Sum.u64 = 361; SumSQ.u64 = 361; Count.u64 = 361; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.AckInv_recv : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 10042; SumSQ.u64 = 23122; Count.u64 = 7633; Min.u64 = 0; Max.u64 = 6; 
  l3cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2836,8 +2836,8 @@ Completed @ 5450 ns
  l3cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.GetS_recv : Accumulator : Sum.u64 = 561; SumSQ.u64 = 561; Count.u64 = 561; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.GetX_recv : Accumulator : Sum.u64 = 444; SumSQ.u64 = 444; Count.u64 = 444; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetS_recv : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetX_recv : Accumulator : Sum.u64 = 213; SumSQ.u64 = 213; Count.u64 = 213; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2856,7 +2856,7 @@ Completed @ 5450 ns
  l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.AckInv_recv : Accumulator : Sum.u64 = 357; SumSQ.u64 = 357; Count.u64 = 357; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.AckInv_recv : Accumulator : Sum.u64 = 327; SumSQ.u64 = 327; Count.u64 = 327; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 10485; SumSQ.u64 = 24221; Count.u64 = 7633; Min.u64 = 0; Max.u64 = 6; 
  l3cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3067,8 +3067,8 @@ Completed @ 5450 ns
  l3cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache2.GetS_recv : Accumulator : Sum.u64 = 575; SumSQ.u64 = 575; Count.u64 = 575; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.GetX_recv : Accumulator : Sum.u64 = 429; SumSQ.u64 = 429; Count.u64 = 429; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetS_recv : Accumulator : Sum.u64 = 344; SumSQ.u64 = 344; Count.u64 = 344; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetX_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3087,7 +3087,7 @@ Completed @ 5450 ns
  l3cache2.FetchResp_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 180; SumSQ.u64 = 180; Count.u64 = 180; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache2.AckInv_recv : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.AckInv_recv : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.MSHR_occupancy : Accumulator : Sum.u64 = 10452; SumSQ.u64 = 23906; Count.u64 = 7633; Min.u64 = 0; Max.u64 = 6; 
  l3cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_1.out
index 5778cd1cf..729394b69 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_1.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_1.out
@@ -129,8 +129,8 @@ ScratchCPU cpu0 Finished after 1000 issued memory events, 1000 returned, 3785 cy
  l1_0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1_0.GetS_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; 
- l1_0.GetX_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; 
+ l1_0.GetS_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; 
+ l1_0.GetX_recv : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; 
  l1_0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -316,7 +316,7 @@ ScratchCPU cpu0 Finished after 1000 issued memory events, 1000 returned, 3785 cy
  l1_1.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_1.ForceInv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l1_1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1_1.FetchInv_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
+ l1_1.FetchInv_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
  l1_1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_1.AckPut_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_2.out
index 50ba01fba..40845c971 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_2.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_2.out
@@ -141,7 +141,7 @@ ScratchCPU cpu1 Finished after 1000 issued memory events, 1000 returned, 3940 cy
  l1_0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_0.GetS_recv : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; 
- l1_0.GetX_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
+ l1_0.GetX_recv : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; 
  l1_0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -349,9 +349,9 @@ ScratchCPU cpu1 Finished after 1000 issued memory events, 1000 returned, 3940 cy
  l2_0.PutE_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; 
  l2_0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2_0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2_0.ForceInv_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
+ l2_0.ForceInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
  l2_0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2_0.FetchInv_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; 
+ l2_0.FetchInv_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
  l2_0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2_0.FetchResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l2_0.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -519,7 +519,7 @@ ScratchCPU cpu1 Finished after 1000 issued memory events, 1000 returned, 3940 cy
  l1_1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1_1.GetS_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; 
+ l1_1.GetS_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; 
  l1_1.GetX_recv : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; 
  l1_1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -715,7 +715,7 @@ ScratchCPU cpu1 Finished after 1000 issued memory events, 1000 returned, 3940 cy
  l2_1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2_1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2_1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2_1.GetS_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; 
+ l2_1.GetS_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
  l2_1.GetX_recv : Accumulator : Sum.u64 = 182; SumSQ.u64 = 182; Count.u64 = 182; Min.u64 = 1; Max.u64 = 1; 
  l2_1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -728,9 +728,9 @@ ScratchCPU cpu1 Finished after 1000 issued memory events, 1000 returned, 3940 cy
  l2_1.PutE_recv : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; 
  l2_1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2_1.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2_1.ForceInv_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; 
+ l2_1.ForceInv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
  l2_1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2_1.FetchInv_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; 
+ l2_1.FetchInv_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; 
  l2_1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2_1.FetchResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
  l2_1.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_3.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_3.out
index 2d9253ccf..dbf530a5b 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_3.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_3.out
@@ -142,7 +142,7 @@ ScratchCPU cpu1 Finished after 1000 issued memory events, 1000 returned, 4670 cy
  l1_0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1_0.GetS_recv : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; 
+ l1_0.GetS_recv : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; 
  l1_0.GetX_recv : Accumulator : Sum.u64 = 167; SumSQ.u64 = 167; Count.u64 = 167; Min.u64 = 1; Max.u64 = 1; 
  l1_0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -339,7 +339,7 @@ ScratchCPU cpu1 Finished after 1000 issued memory events, 1000 returned, 4670 cy
  l2_0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2_0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2_0.GetS_recv : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; 
- l2_0.GetX_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; 
+ l2_0.GetX_recv : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; 
  l2_0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -353,7 +353,7 @@ ScratchCPU cpu1 Finished after 1000 issued memory events, 1000 returned, 4670 cy
  l2_0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2_0.ForceInv_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
  l2_0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2_0.FetchInv_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; 
+ l2_0.FetchInv_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
  l2_0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2_0.FetchResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
  l2_0.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -578,9 +578,9 @@ ScratchCPU cpu1 Finished after 1000 issued memory events, 1000 returned, 4670 cy
  l3_0.PutE_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l3_0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3_0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3_0.ForceInv_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; 
+ l3_0.ForceInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
  l3_0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3_0.FetchInv_recv : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; 
+ l3_0.FetchInv_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
  l3_0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3_0.FetchResp_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
  l3_0.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -749,7 +749,7 @@ ScratchCPU cpu1 Finished after 1000 issued memory events, 1000 returned, 4670 cy
  l1_1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_1.GetS_recv : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; 
- l1_1.GetX_recv : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; 
+ l1_1.GetX_recv : Accumulator : Sum.u64 = 182; SumSQ.u64 = 182; Count.u64 = 182; Min.u64 = 1; Max.u64 = 1; 
  l1_1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -959,7 +959,7 @@ ScratchCPU cpu1 Finished after 1000 issued memory events, 1000 returned, 4670 cy
  l2_1.Inv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l2_1.ForceInv_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
  l2_1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2_1.FetchInv_recv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; 
+ l2_1.FetchInv_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
  l2_1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2_1.FetchResp_recv : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; 
  l2_1.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1186,9 +1186,9 @@ ScratchCPU cpu1 Finished after 1000 issued memory events, 1000 returned, 4670 cy
  l3_1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3_1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3_1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3_1.NULLCMD_recv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; 
- l3_1.GetS_recv : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; 
- l3_1.GetX_recv : Accumulator : Sum.u64 = 216; SumSQ.u64 = 216; Count.u64 = 216; Min.u64 = 1; Max.u64 = 1; 
+ l3_1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l3_1.GetS_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; 
+ l3_1.GetX_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; 
  l3_1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1200,9 +1200,9 @@ ScratchCPU cpu1 Finished after 1000 issued memory events, 1000 returned, 4670 cy
  l3_1.PutE_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l3_1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3_1.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3_1.ForceInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
+ l3_1.ForceInv_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
  l3_1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3_1.FetchInv_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; 
+ l3_1.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
  l3_1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3_1.FetchResp_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; 
  l3_1.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ThroughputThrottling.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ThroughputThrottling.out
index de3bd28ce..e68bc88b0 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ThroughputThrottling.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ThroughputThrottling.out
@@ -153,20 +153,20 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetS_recv : Accumulator : Sum.u64 = 2411; SumSQ.u64 = 2411; Count.u64 = 2411; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetX_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache0.GetS_recv : Accumulator : Sum.u64 = 2263; SumSQ.u64 = 2263; Count.u64 = 2263; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetX_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 761; SumSQ.u64 = 761; Count.u64 = 761; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.Inv_recv : Accumulator : Sum.u64 = 258; SumSQ.u64 = 258; Count.u64 = 258; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.NACK_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 68681; SumSQ.u64 = 576675; Count.u64 = 8868; Min.u64 = 0; Max.u64 = 12; 
@@ -385,7 +385,7 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.GetS_recv : Accumulator : Sum.u64 = 1104; SumSQ.u64 = 1104; Count.u64 = 1104; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.GetS_recv : Accumulator : Sum.u64 = 1464; SumSQ.u64 = 1464; Count.u64 = 1464; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.GetX_recv : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -397,11 +397,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache0.PutM_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.PutE_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.Inv_recv : Accumulator : Sum.u64 = 671; SumSQ.u64 = 671; Count.u64 = 671; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.Inv_recv : Accumulator : Sum.u64 = 413; SumSQ.u64 = 413; Count.u64 = 413; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; 
- l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 209; SumSQ.u64 = 209; Count.u64 = 209; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.NACK_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; 
@@ -552,16 +552,16 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetS_recv : Accumulator : Sum.u64 = 2394; SumSQ.u64 = 2394; Count.u64 = 2394; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetX_recv : Accumulator : Sum.u64 = 176; SumSQ.u64 = 176; Count.u64 = 176; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache1.GetS_recv : Accumulator : Sum.u64 = 2250; SumSQ.u64 = 2250; Count.u64 = 2250; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetX_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 748; SumSQ.u64 = 748; Count.u64 = 748; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 747; SumSQ.u64 = 747; Count.u64 = 747; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.Inv_recv : Accumulator : Sum.u64 = 229; SumSQ.u64 = 229; Count.u64 = 229; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.Inv_recv : Accumulator : Sum.u64 = 227; SumSQ.u64 = 227; Count.u64 = 227; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
@@ -784,7 +784,7 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.GetS_recv : Accumulator : Sum.u64 = 1107; SumSQ.u64 = 1107; Count.u64 = 1107; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.GetS_recv : Accumulator : Sum.u64 = 1496; SumSQ.u64 = 1496; Count.u64 = 1496; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.GetX_recv : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -796,11 +796,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache1.PutM_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.PutE_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.Inv_recv : Accumulator : Sum.u64 = 648; SumSQ.u64 = 648; Count.u64 = 648; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.Inv_recv : Accumulator : Sum.u64 = 421; SumSQ.u64 = 421; Count.u64 = 421; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; 
- l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 133; SumSQ.u64 = 133; Count.u64 = 133; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.NACK_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; 
@@ -951,13 +951,13 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l1cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetS_recv : Accumulator : Sum.u64 = 2410; SumSQ.u64 = 2410; Count.u64 = 2410; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetX_recv : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache2.GetS_recv : Accumulator : Sum.u64 = 2257; SumSQ.u64 = 2257; Count.u64 = 2257; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetX_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 753; SumSQ.u64 = 753; Count.u64 = 753; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.Inv_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
@@ -1183,7 +1183,7 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.GetS_recv : Accumulator : Sum.u64 = 1129; SumSQ.u64 = 1129; Count.u64 = 1129; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.GetS_recv : Accumulator : Sum.u64 = 1518; SumSQ.u64 = 1518; Count.u64 = 1518; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetX_recv : Accumulator : Sum.u64 = 177; SumSQ.u64 = 177; Count.u64 = 177; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1195,11 +1195,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache2.PutM_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.PutE_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.Inv_recv : Accumulator : Sum.u64 = 691; SumSQ.u64 = 691; Count.u64 = 691; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.Inv_recv : Accumulator : Sum.u64 = 441; SumSQ.u64 = 441; Count.u64 = 441; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; 
- l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 220; SumSQ.u64 = 220; Count.u64 = 220; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.NACK_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
@@ -1350,20 +1350,20 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l1cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetS_recv : Accumulator : Sum.u64 = 2387; SumSQ.u64 = 2387; Count.u64 = 2387; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetX_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache3.GetS_recv : Accumulator : Sum.u64 = 2262; SumSQ.u64 = 2262; Count.u64 = 2262; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetX_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 757; SumSQ.u64 = 757; Count.u64 = 757; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 756; SumSQ.u64 = 756; Count.u64 = 756; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.Inv_recv : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.NACK_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 68183; SumSQ.u64 = 572155; Count.u64 = 8868; Min.u64 = 0; Max.u64 = 12; 
@@ -1582,8 +1582,8 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.GetS_recv : Accumulator : Sum.u64 = 1144; SumSQ.u64 = 1144; Count.u64 = 1144; Min.u64 = 1; Max.u64 = 1; 
- l2cache3.GetX_recv : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.GetS_recv : Accumulator : Sum.u64 = 1517; SumSQ.u64 = 1517; Count.u64 = 1517; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.GetX_recv : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1594,11 +1594,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache3.PutM_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.PutE_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.Inv_recv : Accumulator : Sum.u64 = 678; SumSQ.u64 = 678; Count.u64 = 678; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.Inv_recv : Accumulator : Sum.u64 = 435; SumSQ.u64 = 435; Count.u64 = 435; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; 
- l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 217; SumSQ.u64 = 217; Count.u64 = 217; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.NACK_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; 
@@ -1749,20 +1749,20 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l1cache4.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 75; SumSQ.u64 = 75; Count.u64 = 75; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetS_recv : Accumulator : Sum.u64 = 2402; SumSQ.u64 = 2402; Count.u64 = 2402; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetX_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache4.GetS_recv : Accumulator : Sum.u64 = 2271; SumSQ.u64 = 2271; Count.u64 = 2271; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetX_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 766; SumSQ.u64 = 766; Count.u64 = 766; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 762; SumSQ.u64 = 762; Count.u64 = 762; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.Inv_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.Inv_recv : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FetchInv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.FetchInvX_recv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.FetchInvX_recv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.NACK_recv : Accumulator : Sum.u64 = 246; SumSQ.u64 = 246; Count.u64 = 246; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.MSHR_occupancy : Accumulator : Sum.u64 = 71667; SumSQ.u64 = 604659; Count.u64 = 8868; Min.u64 = 0; Max.u64 = 12; 
@@ -1981,7 +1981,7 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.GetS_recv : Accumulator : Sum.u64 = 1198; SumSQ.u64 = 1198; Count.u64 = 1198; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.GetS_recv : Accumulator : Sum.u64 = 1547; SumSQ.u64 = 1547; Count.u64 = 1547; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.GetX_recv : Accumulator : Sum.u64 = 189; SumSQ.u64 = 189; Count.u64 = 189; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1993,11 +1993,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache4.PutM_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.PutE_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.Inv_recv : Accumulator : Sum.u64 = 672; SumSQ.u64 = 672; Count.u64 = 672; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.Inv_recv : Accumulator : Sum.u64 = 432; SumSQ.u64 = 432; Count.u64 = 432; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; 
- l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 231; SumSQ.u64 = 231; Count.u64 = 231; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FetchResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FetchXResp_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.NACK_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; 
@@ -2148,13 +2148,13 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l1cache5.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetS_recv : Accumulator : Sum.u64 = 2440; SumSQ.u64 = 2440; Count.u64 = 2440; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetX_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache5.GetS_recv : Accumulator : Sum.u64 = 2287; SumSQ.u64 = 2287; Count.u64 = 2287; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetX_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 782; SumSQ.u64 = 782; Count.u64 = 782; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 781; SumSQ.u64 = 781; Count.u64 = 781; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.Inv_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
@@ -2380,7 +2380,7 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.GetS_recv : Accumulator : Sum.u64 = 1163; SumSQ.u64 = 1163; Count.u64 = 1163; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.GetS_recv : Accumulator : Sum.u64 = 1546; SumSQ.u64 = 1546; Count.u64 = 1546; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.GetX_recv : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2392,11 +2392,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache5.PutM_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.Inv_recv : Accumulator : Sum.u64 = 676; SumSQ.u64 = 676; Count.u64 = 676; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.Inv_recv : Accumulator : Sum.u64 = 435; SumSQ.u64 = 435; Count.u64 = 435; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; 
- l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 203; SumSQ.u64 = 203; Count.u64 = 203; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.FetchResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.FetchXResp_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.NACK_recv : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; 
@@ -2611,8 +2611,8 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l3cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.GetS_recv : Accumulator : Sum.u64 = 1370; SumSQ.u64 = 1370; Count.u64 = 1370; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.GetX_recv : Accumulator : Sum.u64 = 618; SumSQ.u64 = 618; Count.u64 = 618; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetS_recv : Accumulator : Sum.u64 = 937; SumSQ.u64 = 937; Count.u64 = 937; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetX_recv : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2628,10 +2628,10 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l3cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.NACK_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.AckInv_recv : Accumulator : Sum.u64 = 898; SumSQ.u64 = 898; Count.u64 = 898; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.NACK_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.AckInv_recv : Accumulator : Sum.u64 = 836; SumSQ.u64 = 836; Count.u64 = 836; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 20359; SumSQ.u64 = 99135; Count.u64 = 5179; Min.u64 = 0; Max.u64 = 7; 
  l3cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2842,8 +2842,8 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l3cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.GetS_recv : Accumulator : Sum.u64 = 1416; SumSQ.u64 = 1416; Count.u64 = 1416; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.GetX_recv : Accumulator : Sum.u64 = 601; SumSQ.u64 = 601; Count.u64 = 601; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetS_recv : Accumulator : Sum.u64 = 972; SumSQ.u64 = 972; Count.u64 = 972; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetX_recv : Accumulator : Sum.u64 = 299; SumSQ.u64 = 299; Count.u64 = 299; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2860,9 +2860,9 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l3cache1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 248; SumSQ.u64 = 248; Count.u64 = 248; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 247; SumSQ.u64 = 247; Count.u64 = 247; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.NACK_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.AckInv_recv : Accumulator : Sum.u64 = 916; SumSQ.u64 = 916; Count.u64 = 916; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.AckInv_recv : Accumulator : Sum.u64 = 851; SumSQ.u64 = 851; Count.u64 = 851; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 19957; SumSQ.u64 = 97477; Count.u64 = 5179; Min.u64 = 0; Max.u64 = 7; 
  l3cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3073,8 +3073,8 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l3cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache2.GetS_recv : Accumulator : Sum.u64 = 1457; SumSQ.u64 = 1457; Count.u64 = 1457; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.GetX_recv : Accumulator : Sum.u64 = 614; SumSQ.u64 = 614; Count.u64 = 614; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetS_recv : Accumulator : Sum.u64 = 1027; SumSQ.u64 = 1027; Count.u64 = 1027; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetX_recv : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3091,9 +3091,9 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l3cache2.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FetchResp_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 237; SumSQ.u64 = 237; Count.u64 = 237; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.NACK_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.AckInv_recv : Accumulator : Sum.u64 = 904; SumSQ.u64 = 904; Count.u64 = 904; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 236; SumSQ.u64 = 236; Count.u64 = 236; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.NACK_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.AckInv_recv : Accumulator : Sum.u64 = 842; SumSQ.u64 = 842; Count.u64 = 842; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.MSHR_occupancy : Accumulator : Sum.u64 = 21136; SumSQ.u64 = 106020; Count.u64 = 5179; Min.u64 = 0; Max.u64 = 7; 
  l3cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ThroughputThrottling_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ThroughputThrottling_MC.out
index 37dfe760b..0e05f3657 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ThroughputThrottling_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ThroughputThrottling_MC.out
@@ -153,20 +153,20 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetS_recv : Accumulator : Sum.u64 = 2411; SumSQ.u64 = 2411; Count.u64 = 2411; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetX_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache0.GetS_recv : Accumulator : Sum.u64 = 2263; SumSQ.u64 = 2263; Count.u64 = 2263; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetX_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 761; SumSQ.u64 = 761; Count.u64 = 761; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.Inv_recv : Accumulator : Sum.u64 = 258; SumSQ.u64 = 258; Count.u64 = 258; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.NACK_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 68681; SumSQ.u64 = 576675; Count.u64 = 8868; Min.u64 = 0; Max.u64 = 12; 
@@ -385,7 +385,7 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.GetS_recv : Accumulator : Sum.u64 = 1104; SumSQ.u64 = 1104; Count.u64 = 1104; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.GetS_recv : Accumulator : Sum.u64 = 1464; SumSQ.u64 = 1464; Count.u64 = 1464; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.GetX_recv : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -397,11 +397,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache0.PutM_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.PutE_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.Inv_recv : Accumulator : Sum.u64 = 671; SumSQ.u64 = 671; Count.u64 = 671; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.Inv_recv : Accumulator : Sum.u64 = 413; SumSQ.u64 = 413; Count.u64 = 413; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; 
- l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 209; SumSQ.u64 = 209; Count.u64 = 209; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; 
+ l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; 
  l2cache0.NACK_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; 
@@ -552,16 +552,16 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetS_recv : Accumulator : Sum.u64 = 2394; SumSQ.u64 = 2394; Count.u64 = 2394; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetX_recv : Accumulator : Sum.u64 = 176; SumSQ.u64 = 176; Count.u64 = 176; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache1.GetS_recv : Accumulator : Sum.u64 = 2250; SumSQ.u64 = 2250; Count.u64 = 2250; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetX_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 748; SumSQ.u64 = 748; Count.u64 = 748; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 747; SumSQ.u64 = 747; Count.u64 = 747; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.Inv_recv : Accumulator : Sum.u64 = 229; SumSQ.u64 = 229; Count.u64 = 229; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.Inv_recv : Accumulator : Sum.u64 = 227; SumSQ.u64 = 227; Count.u64 = 227; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
@@ -784,7 +784,7 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.GetS_recv : Accumulator : Sum.u64 = 1107; SumSQ.u64 = 1107; Count.u64 = 1107; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.GetS_recv : Accumulator : Sum.u64 = 1496; SumSQ.u64 = 1496; Count.u64 = 1496; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.GetX_recv : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -796,11 +796,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache1.PutM_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.PutE_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.Inv_recv : Accumulator : Sum.u64 = 648; SumSQ.u64 = 648; Count.u64 = 648; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.Inv_recv : Accumulator : Sum.u64 = 421; SumSQ.u64 = 421; Count.u64 = 421; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; 
- l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
+ l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 133; SumSQ.u64 = 133; Count.u64 = 133; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; 
  l2cache1.NACK_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; 
@@ -951,13 +951,13 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l1cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetS_recv : Accumulator : Sum.u64 = 2410; SumSQ.u64 = 2410; Count.u64 = 2410; Min.u64 = 1; Max.u64 = 1; 
- l1cache2.GetX_recv : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache2.GetS_recv : Accumulator : Sum.u64 = 2257; SumSQ.u64 = 2257; Count.u64 = 2257; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetX_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 753; SumSQ.u64 = 753; Count.u64 = 753; Min.u64 = 1; Max.u64 = 1; 
+ l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; 
  l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache2.Inv_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; 
@@ -1183,7 +1183,7 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.GetS_recv : Accumulator : Sum.u64 = 1129; SumSQ.u64 = 1129; Count.u64 = 1129; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.GetS_recv : Accumulator : Sum.u64 = 1518; SumSQ.u64 = 1518; Count.u64 = 1518; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetX_recv : Accumulator : Sum.u64 = 177; SumSQ.u64 = 177; Count.u64 = 177; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1195,11 +1195,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache2.PutM_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.PutE_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.Inv_recv : Accumulator : Sum.u64 = 691; SumSQ.u64 = 691; Count.u64 = 691; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.Inv_recv : Accumulator : Sum.u64 = 441; SumSQ.u64 = 441; Count.u64 = 441; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; 
- l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 220; SumSQ.u64 = 220; Count.u64 = 220; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; 
+ l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; 
  l2cache2.NACK_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; 
@@ -1350,20 +1350,20 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l1cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetS_recv : Accumulator : Sum.u64 = 2387; SumSQ.u64 = 2387; Count.u64 = 2387; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.GetX_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache3.GetS_recv : Accumulator : Sum.u64 = 2262; SumSQ.u64 = 2262; Count.u64 = 2262; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetX_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 757; SumSQ.u64 = 757; Count.u64 = 757; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 756; SumSQ.u64 = 756; Count.u64 = 756; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.Inv_recv : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
- l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
+ l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.NACK_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; 
  l1cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 68183; SumSQ.u64 = 572155; Count.u64 = 8868; Min.u64 = 0; Max.u64 = 12; 
@@ -1582,8 +1582,8 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.GetS_recv : Accumulator : Sum.u64 = 1144; SumSQ.u64 = 1144; Count.u64 = 1144; Min.u64 = 1; Max.u64 = 1; 
- l2cache3.GetX_recv : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.GetS_recv : Accumulator : Sum.u64 = 1517; SumSQ.u64 = 1517; Count.u64 = 1517; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.GetX_recv : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1594,11 +1594,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache3.PutM_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.PutE_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.Inv_recv : Accumulator : Sum.u64 = 678; SumSQ.u64 = 678; Count.u64 = 678; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.Inv_recv : Accumulator : Sum.u64 = 435; SumSQ.u64 = 435; Count.u64 = 435; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; 
- l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 217; SumSQ.u64 = 217; Count.u64 = 217; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; 
+ l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; 
  l2cache3.NACK_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; 
@@ -1749,20 +1749,20 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l1cache4.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 75; SumSQ.u64 = 75; Count.u64 = 75; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetS_recv : Accumulator : Sum.u64 = 2402; SumSQ.u64 = 2402; Count.u64 = 2402; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.GetX_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache4.GetS_recv : Accumulator : Sum.u64 = 2271; SumSQ.u64 = 2271; Count.u64 = 2271; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetX_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 766; SumSQ.u64 = 766; Count.u64 = 766; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 762; SumSQ.u64 = 762; Count.u64 = 762; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache4.Inv_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.Inv_recv : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.FetchInv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
- l1cache4.FetchInvX_recv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; 
+ l1cache4.FetchInvX_recv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.NACK_recv : Accumulator : Sum.u64 = 246; SumSQ.u64 = 246; Count.u64 = 246; Min.u64 = 1; Max.u64 = 1; 
  l1cache4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache4.MSHR_occupancy : Accumulator : Sum.u64 = 71667; SumSQ.u64 = 604659; Count.u64 = 8868; Min.u64 = 0; Max.u64 = 12; 
@@ -1981,7 +1981,7 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.GetS_recv : Accumulator : Sum.u64 = 1198; SumSQ.u64 = 1198; Count.u64 = 1198; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.GetS_recv : Accumulator : Sum.u64 = 1547; SumSQ.u64 = 1547; Count.u64 = 1547; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.GetX_recv : Accumulator : Sum.u64 = 189; SumSQ.u64 = 189; Count.u64 = 189; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1993,11 +1993,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache4.PutM_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.PutE_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.Inv_recv : Accumulator : Sum.u64 = 672; SumSQ.u64 = 672; Count.u64 = 672; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.Inv_recv : Accumulator : Sum.u64 = 432; SumSQ.u64 = 432; Count.u64 = 432; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; 
- l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 231; SumSQ.u64 = 231; Count.u64 = 231; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; 
+ l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FetchResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.FetchXResp_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; 
  l2cache4.NACK_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; 
@@ -2148,13 +2148,13 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l1cache5.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetS_recv : Accumulator : Sum.u64 = 2440; SumSQ.u64 = 2440; Count.u64 = 2440; Min.u64 = 1; Max.u64 = 1; 
- l1cache5.GetX_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache5.GetS_recv : Accumulator : Sum.u64 = 2287; SumSQ.u64 = 2287; Count.u64 = 2287; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetX_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 782; SumSQ.u64 = 782; Count.u64 = 782; Min.u64 = 1; Max.u64 = 1; 
+ l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 781; SumSQ.u64 = 781; Count.u64 = 781; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; 
  l1cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache5.Inv_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; 
@@ -2380,7 +2380,7 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.GetS_recv : Accumulator : Sum.u64 = 1163; SumSQ.u64 = 1163; Count.u64 = 1163; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.GetS_recv : Accumulator : Sum.u64 = 1546; SumSQ.u64 = 1546; Count.u64 = 1546; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.GetX_recv : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2392,11 +2392,11 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l2cache5.PutM_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.Inv_recv : Accumulator : Sum.u64 = 676; SumSQ.u64 = 676; Count.u64 = 676; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.Inv_recv : Accumulator : Sum.u64 = 435; SumSQ.u64 = 435; Count.u64 = 435; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; 
- l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 203; SumSQ.u64 = 203; Count.u64 = 203; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; 
+ l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.FetchResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.FetchXResp_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; 
  l2cache5.NACK_recv : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; 
@@ -2611,8 +2611,8 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l3cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.GetS_recv : Accumulator : Sum.u64 = 1370; SumSQ.u64 = 1370; Count.u64 = 1370; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.GetX_recv : Accumulator : Sum.u64 = 618; SumSQ.u64 = 618; Count.u64 = 618; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetS_recv : Accumulator : Sum.u64 = 937; SumSQ.u64 = 937; Count.u64 = 937; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.GetX_recv : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2628,10 +2628,10 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l3cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.NACK_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
- l3cache0.AckInv_recv : Accumulator : Sum.u64 = 898; SumSQ.u64 = 898; Count.u64 = 898; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.NACK_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ l3cache0.AckInv_recv : Accumulator : Sum.u64 = 836; SumSQ.u64 = 836; Count.u64 = 836; Min.u64 = 1; Max.u64 = 1; 
  l3cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 20359; SumSQ.u64 = 99135; Count.u64 = 5179; Min.u64 = 0; Max.u64 = 7; 
  l3cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2842,8 +2842,8 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l3cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache1.GetS_recv : Accumulator : Sum.u64 = 1416; SumSQ.u64 = 1416; Count.u64 = 1416; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.GetX_recv : Accumulator : Sum.u64 = 601; SumSQ.u64 = 601; Count.u64 = 601; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetS_recv : Accumulator : Sum.u64 = 972; SumSQ.u64 = 972; Count.u64 = 972; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.GetX_recv : Accumulator : Sum.u64 = 299; SumSQ.u64 = 299; Count.u64 = 299; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -2860,9 +2860,9 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l3cache1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 248; SumSQ.u64 = 248; Count.u64 = 248; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 247; SumSQ.u64 = 247; Count.u64 = 247; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.NACK_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
- l3cache1.AckInv_recv : Accumulator : Sum.u64 = 916; SumSQ.u64 = 916; Count.u64 = 916; Min.u64 = 1; Max.u64 = 1; 
+ l3cache1.AckInv_recv : Accumulator : Sum.u64 = 851; SumSQ.u64 = 851; Count.u64 = 851; Min.u64 = 1; Max.u64 = 1; 
  l3cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 19957; SumSQ.u64 = 97477; Count.u64 = 5179; Min.u64 = 0; Max.u64 = 7; 
  l3cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3073,8 +3073,8 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l3cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache2.GetS_recv : Accumulator : Sum.u64 = 1457; SumSQ.u64 = 1457; Count.u64 = 1457; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.GetX_recv : Accumulator : Sum.u64 = 614; SumSQ.u64 = 614; Count.u64 = 614; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetS_recv : Accumulator : Sum.u64 = 1027; SumSQ.u64 = 1027; Count.u64 = 1027; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.GetX_recv : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -3091,9 +3091,9 @@ TrivialCPU cpu5 Finished after 1500 issued reads, 1500 returned (8695 clocks)
  l3cache2.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.FetchResp_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 237; SumSQ.u64 = 237; Count.u64 = 237; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.NACK_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; 
- l3cache2.AckInv_recv : Accumulator : Sum.u64 = 904; SumSQ.u64 = 904; Count.u64 = 904; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 236; SumSQ.u64 = 236; Count.u64 = 236; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.NACK_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; 
+ l3cache2.AckInv_recv : Accumulator : Sum.u64 = 842; SumSQ.u64 = 842; Count.u64 = 842; Min.u64 = 1; Max.u64 = 1; 
  l3cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache2.MSHR_occupancy : Accumulator : Sum.u64 = 21136; SumSQ.u64 = 106020; Count.u64 = 5179; Min.u64 = 0; Max.u64 = 7; 
  l3cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl2_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl2_1.out
index 46d4a6669..8af3ce376 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl2_1.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl2_1.out
@@ -129,8 +129,8 @@ TrivialCPU cpu Finished after 1000 issued reads, 1000 returned (104054 clocks)
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 906; SumSQ.u64 = 906; Count.u64 = 906; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_1.out
index 8714224ca..2a3ffb0b9 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_1.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_1.out
@@ -130,9 +130,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (104069 clocks)
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 920; SumSQ.u64 = 920; Count.u64 = 920; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -275,9 +275,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (104069 clocks)
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 923; SumSQ.u64 = 923; Count.u64 = 923; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -461,8 +461,8 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (104069 clocks)
  l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache.GetS_recv : Accumulator : Sum.u64 = 1823; SumSQ.u64 = 1823; Count.u64 = 1823; Min.u64 = 1; Max.u64 = 1; 
- l2cache.GetX_recv : Accumulator : Sum.u64 = 380; SumSQ.u64 = 380; Count.u64 = 380; Min.u64 = 1; Max.u64 = 1; 
+ l2cache.GetS_recv : Accumulator : Sum.u64 = 1357; SumSQ.u64 = 1357; Count.u64 = 1357; Min.u64 = 1; Max.u64 = 1; 
+ l2cache.GetX_recv : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; 
  l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_2.out
index 1c0e90fee..d9fb68da7 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_2.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_2.out
@@ -132,9 +132,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (104054 clocks)
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 911; SumSQ.u64 = 911; Count.u64 = 911; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -277,9 +277,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (104054 clocks)
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -463,8 +463,8 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (104054 clocks)
  l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache.GetS_recv : Accumulator : Sum.u64 = 1819; SumSQ.u64 = 1819; Count.u64 = 1819; Min.u64 = 1; Max.u64 = 1; 
- l2cache.GetX_recv : Accumulator : Sum.u64 = 393; SumSQ.u64 = 393; Count.u64 = 393; Min.u64 = 1; Max.u64 = 1; 
+ l2cache.GetS_recv : Accumulator : Sum.u64 = 1355; SumSQ.u64 = 1355; Count.u64 = 1355; Min.u64 = 1; Max.u64 = 1; 
+ l2cache.GetX_recv : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; 
  l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_3.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_3.out
index dad7126c4..b48a4b679 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_3.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_3.out
@@ -131,7 +131,7 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (104054 clocks)
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 908; SumSQ.u64 = 908; Count.u64 = 908; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -276,7 +276,7 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (104054 clocks)
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -461,8 +461,8 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (104054 clocks)
  l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache.GetS_recv : Accumulator : Sum.u64 = 1033; SumSQ.u64 = 1033; Count.u64 = 1033; Min.u64 = 1; Max.u64 = 1; 
- l2cache.GetX_recv : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; 
+ l2cache.GetS_recv : Accumulator : Sum.u64 = 928; SumSQ.u64 = 928; Count.u64 = 928; Min.u64 = 1; Max.u64 = 1; 
+ l2cache.GetX_recv : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; 
  l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_1.out
index 0715a131f..e3e2c89a0 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_1.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_1.out
@@ -131,7 +131,7 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 906; SumSQ.u64 = 906; Count.u64 = 906; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -276,7 +276,7 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 906; SumSQ.u64 = 906; Count.u64 = 906; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -461,8 +461,8 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache.GetS_recv : Accumulator : Sum.u64 = 349; SumSQ.u64 = 349; Count.u64 = 349; Min.u64 = 1; Max.u64 = 1; 
- l2cache.GetX_recv : Accumulator : Sum.u64 = 417; SumSQ.u64 = 417; Count.u64 = 417; Min.u64 = 1; Max.u64 = 1; 
+ l2cache.GetS_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; 
+ l2cache.GetX_recv : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; 
  l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_2.out
index d8a38fc9c..b309bedee 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_2.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_2.out
@@ -131,7 +131,7 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 905; SumSQ.u64 = 905; Count.u64 = 905; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -276,7 +276,7 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 905; SumSQ.u64 = 905; Count.u64 = 905; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -461,8 +461,8 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache.GetS_recv : Accumulator : Sum.u64 = 349; SumSQ.u64 = 349; Count.u64 = 349; Min.u64 = 1; Max.u64 = 1; 
- l2cache.GetX_recv : Accumulator : Sum.u64 = 417; SumSQ.u64 = 417; Count.u64 = 417; Min.u64 = 1; Max.u64 = 1; 
+ l2cache.GetS_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; 
+ l2cache.GetX_recv : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; 
  l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_2_ramulator.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_2_ramulator.out
index 9b39930f2..7a6a383ea 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_2_ramulator.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_2_ramulator.out
@@ -130,9 +130,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (9961 clocks)
  c0.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 1034; SumSQ.u64 = 1034; Count.u64 = 1034; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 1805; SumSQ.u64 = 1805; Count.u64 = 1805; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 230; SumSQ.u64 = 230; Count.u64 = 230; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 887; SumSQ.u64 = 887; Count.u64 = 887; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -275,9 +275,9 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (9961 clocks)
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 1105; SumSQ.u64 = 1105; Count.u64 = 1105; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 1909; SumSQ.u64 = 1909; Count.u64 = 1909; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 905; SumSQ.u64 = 905; Count.u64 = 905; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -461,8 +461,8 @@ TrivialCPU cpu0 Finished after 1000 issued reads, 1000 returned (9961 clocks)
  l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l2cache.GetS_recv : Accumulator : Sum.u64 = 1910; SumSQ.u64 = 1910; Count.u64 = 1910; Min.u64 = 1; Max.u64 = 1; 
- l2cache.GetX_recv : Accumulator : Sum.u64 = 230; SumSQ.u64 = 230; Count.u64 = 230; Min.u64 = 1; Max.u64 = 1; 
+ l2cache.GetS_recv : Accumulator : Sum.u64 = 1788; SumSQ.u64 = 1788; Count.u64 = 1788; Min.u64 = 1; Max.u64 = 1; 
+ l2cache.GetX_recv : Accumulator : Sum.u64 = 208; SumSQ.u64 = 208; Count.u64 = 208; Min.u64 = 1; Max.u64 = 1; 
  l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1.out
index 4efdebd4b..08aa587c2 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1.out
@@ -137,8 +137,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -282,8 +282,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -467,8 +467,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 426; SumSQ.u64 = 426; Count.u64 = 426; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -482,7 +482,7 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 270; SumSQ.u64 = 270; Count.u64 = 270; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
@@ -619,8 +619,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 908; SumSQ.u64 = 908; Count.u64 = 908; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -764,8 +764,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -949,8 +949,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 354; SumSQ.u64 = 354; Count.u64 = 354; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 211; SumSQ.u64 = 211; Count.u64 = 211; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -961,11 +961,11 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1141,8 +1141,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 350; SumSQ.u64 = 350; Count.u64 = 350; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 459; SumSQ.u64 = 459; Count.u64 = 459; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1_MC.out
index 084994ce7..edf207d31 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1_MC.out
@@ -137,8 +137,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -282,8 +282,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -467,8 +467,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 426; SumSQ.u64 = 426; Count.u64 = 426; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -482,7 +482,7 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 270; SumSQ.u64 = 270; Count.u64 = 270; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
@@ -619,8 +619,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 908; SumSQ.u64 = 908; Count.u64 = 908; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -764,8 +764,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -949,8 +949,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 354; SumSQ.u64 = 354; Count.u64 = 354; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 211; SumSQ.u64 = 211; Count.u64 = 211; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -961,11 +961,11 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1141,8 +1141,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 350; SumSQ.u64 = 350; Count.u64 = 350; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 459; SumSQ.u64 = 459; Count.u64 = 459; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1_ramulator.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1_ramulator.out
index b0267eb7f..5ecb9d8e0 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1_ramulator.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1_ramulator.out
@@ -137,8 +137,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -282,8 +282,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -467,8 +467,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 426; SumSQ.u64 = 426; Count.u64 = 426; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -482,7 +482,7 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 270; SumSQ.u64 = 270; Count.u64 = 270; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
@@ -619,8 +619,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 908; SumSQ.u64 = 908; Count.u64 = 908; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -764,8 +764,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -949,8 +949,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 354; SumSQ.u64 = 354; Count.u64 = 354; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 211; SumSQ.u64 = 211; Count.u64 = 211; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -961,11 +961,11 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1141,8 +1141,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 350; SumSQ.u64 = 350; Count.u64 = 350; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 458; SumSQ.u64 = 458; Count.u64 = 458; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1_ramulator_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1_ramulator_MC.out
index 32cba7c10..a1068734a 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1_ramulator_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1_ramulator_MC.out
@@ -137,8 +137,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -282,8 +282,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -467,8 +467,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 426; SumSQ.u64 = 426; Count.u64 = 426; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -482,7 +482,7 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 270; SumSQ.u64 = 270; Count.u64 = 270; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
@@ -619,8 +619,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 908; SumSQ.u64 = 908; Count.u64 = 908; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -764,8 +764,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -949,8 +949,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 354; SumSQ.u64 = 354; Count.u64 = 354; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 211; SumSQ.u64 = 211; Count.u64 = 211; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -961,11 +961,11 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1141,8 +1141,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104055 clocks)
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 350; SumSQ.u64 = 350; Count.u64 = 350; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 458; SumSQ.u64 = 458; Count.u64 = 458; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_1.out
index b6974324d..9b7b42097 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_1.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_1.out
@@ -129,9 +129,9 @@ TrivialCPU cpu Finished after 10000 issued reads, 10000 returned (1325350 clocks
  l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 8999; SumSQ.u64 = 8999; Count.u64 = 8999; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 1023; SumSQ.u64 = 1023; Count.u64 = 1023; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 8979; SumSQ.u64 = 8979; Count.u64 = 8979; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 1021; SumSQ.u64 = 1021; Count.u64 = 1021; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -511,8 +511,8 @@ TrivialCPU cpu Finished after 10000 issued reads, 10000 returned (1325350 clocks
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 8707; SumSQ.u64 = 8707; Count.u64 = 8707; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 1017; SumSQ.u64 = 1017; Count.u64 = 1017; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 8702; SumSQ.u64 = 8702; Count.u64 = 8702; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 1016; SumSQ.u64 = 1016; Count.u64 = 1016; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_3.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_3.out
index 357c78f42..b0629d09a 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_3.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_3.out
@@ -281,8 +281,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (469650 clocks)
  c1.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 892; SumSQ.u64 = 892; Count.u64 = 892; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 891; SumSQ.u64 = 891; Count.u64 = 891; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -467,7 +467,7 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (469650 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1784; SumSQ.u64 = 1784; Count.u64 = 1784; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1781; SumSQ.u64 = 1781; Count.u64 = 1781; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -483,7 +483,7 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (469650 clocks)
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -618,9 +618,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (469650 clocks)
  c2.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 895; SumSQ.u64 = 895; Count.u64 = 895; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 894; SumSQ.u64 = 894; Count.u64 = 894; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -763,9 +763,9 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (469650 clocks)
  c3.l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 912; SumSQ.u64 = 912; Count.u64 = 912; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -949,7 +949,7 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (469650 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1801; SumSQ.u64 = 1801; Count.u64 = 1801; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1798; SumSQ.u64 = 1798; Count.u64 = 1798; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 194; SumSQ.u64 = 194; Count.u64 = 194; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -961,11 +961,11 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (469650 clocks)
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1145,8 +1145,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (469650 clocks)
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 3509; SumSQ.u64 = 3509; Count.u64 = 3509; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 404; SumSQ.u64 = 404; Count.u64 = 404; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 3483; SumSQ.u64 = 3483; Count.u64 = 3483; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 403; SumSQ.u64 = 403; Count.u64 = 403; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_4.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_4.out
index 76a88d9d0..5579130d4 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_4.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_4.out
@@ -137,8 +137,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104241 clocks)
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -282,8 +282,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104241 clocks)
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -467,8 +467,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104241 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 426; SumSQ.u64 = 426; Count.u64 = 426; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -482,7 +482,7 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104241 clocks)
  n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 270; SumSQ.u64 = 270; Count.u64 = 270; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
@@ -619,8 +619,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104241 clocks)
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -764,8 +764,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104241 clocks)
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -949,8 +949,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104241 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 352; SumSQ.u64 = 352; Count.u64 = 352; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -961,11 +961,11 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104241 clocks)
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1145,8 +1145,8 @@ TrivialCPU cpu3 Finished after 1000 issued reads, 1000 returned (104241 clocks)
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 348; SumSQ.u64 = 348; Count.u64 = 348; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 415; SumSQ.u64 = 415; Count.u64 = 415; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 204; SumSQ.u64 = 204; Count.u64 = 204; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_1.out
index 82abf3cdd..c486aa3b9 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_1.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_1.out
@@ -132,7 +132,7 @@ TrivialCPU cpu Finished after 10000 issued reads, 10000 returned (1004997 clocks
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 8972; SumSQ.u64 = 8972; Count.u64 = 8972; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 8971; SumSQ.u64 = 8971; Count.u64 = 8971; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetX_recv : Accumulator : Sum.u64 = 1023; SumSQ.u64 = 1023; Count.u64 = 1023; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_1_MC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_1_MC.out
index 82abf3cdd..c486aa3b9 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_1_MC.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_1_MC.out
@@ -132,7 +132,7 @@ TrivialCPU cpu Finished after 10000 issued reads, 10000 returned (1004997 clocks
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 8972; SumSQ.u64 = 8972; Count.u64 = 8972; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 8971; SumSQ.u64 = 8971; Count.u64 = 8971; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetX_recv : Accumulator : Sum.u64 = 1023; SumSQ.u64 = 1023; Count.u64 = 1023; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_2.out
index 195a30b36..046eadd87 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_2.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_2.out
@@ -158,8 +158,8 @@ TrivialCPU cpu7 Finished after 1000 issued reads, 1000 returned (104578 clocks)
  c0.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 863; SumSQ.u64 = 863; Count.u64 = 863; Min.u64 = 1; Max.u64 = 1; 
- c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetS_recv : Accumulator : Sum.u64 = 853; SumSQ.u64 = 853; Count.u64 = 853; Min.u64 = 1; Max.u64 = 1; 
+ c0.l1cache.GetX_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; 
  c0.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -303,8 +303,8 @@ TrivialCPU cpu7 Finished after 1000 issued reads, 1000 returned (104578 clocks)
  c1.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 863; SumSQ.u64 = 863; Count.u64 = 863; Min.u64 = 1; Max.u64 = 1; 
- c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetS_recv : Accumulator : Sum.u64 = 853; SumSQ.u64 = 853; Count.u64 = 853; Min.u64 = 1; Max.u64 = 1; 
+ c1.l1cache.GetX_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; 
  c1.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -448,8 +448,8 @@ TrivialCPU cpu7 Finished after 1000 issued reads, 1000 returned (104578 clocks)
  c2.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 866; SumSQ.u64 = 866; Count.u64 = 866; Min.u64 = 1; Max.u64 = 1; 
- c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetS_recv : Accumulator : Sum.u64 = 853; SumSQ.u64 = 853; Count.u64 = 853; Min.u64 = 1; Max.u64 = 1; 
+ c2.l1cache.GetX_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; 
  c2.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -593,8 +593,8 @@ TrivialCPU cpu7 Finished after 1000 issued reads, 1000 returned (104578 clocks)
  c3.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 868; SumSQ.u64 = 868; Count.u64 = 868; Min.u64 = 1; Max.u64 = 1; 
- c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetS_recv : Accumulator : Sum.u64 = 853; SumSQ.u64 = 853; Count.u64 = 853; Min.u64 = 1; Max.u64 = 1; 
+ c3.l1cache.GetX_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; 
  c3.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -778,8 +778,8 @@ TrivialCPU cpu7 Finished after 1000 issued reads, 1000 returned (104578 clocks)
  n0.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 1212; SumSQ.u64 = 1212; Count.u64 = 1212; Min.u64 = 1; Max.u64 = 1; 
- n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 997; SumSQ.u64 = 997; Count.u64 = 997; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetS_recv : Accumulator : Sum.u64 = 541; SumSQ.u64 = 541; Count.u64 = 541; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.GetX_recv : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -790,15 +790,15 @@ TrivialCPU cpu7 Finished after 1000 issued reads, 1000 returned (104578 clocks)
  n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.Inv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 446; SumSQ.u64 = 446; Count.u64 = 446; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 176; SumSQ.u64 = 176; Count.u64 = 176; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 355; SumSQ.u64 = 355; Count.u64 = 355; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n0.l2cache.AckInv_recv : Accumulator : Sum.u64 = 258; SumSQ.u64 = 258; Count.u64 = 258; Min.u64 = 1; Max.u64 = 1; 
+ n0.l2cache.AckInv_recv : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; 
  n0.l2cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n0.l2cache.MSHR_occupancy : Accumulator : Sum.u64 = 861348; SumSQ.u64 = 8859192; Count.u64 = 209156; Min.u64 = 0; Max.u64 = 32; 
  n0.l2cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -930,8 +930,8 @@ TrivialCPU cpu7 Finished after 1000 issued reads, 1000 returned (104578 clocks)
  c4.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c4.l1cache.GetS_recv : Accumulator : Sum.u64 = 862; SumSQ.u64 = 862; Count.u64 = 862; Min.u64 = 1; Max.u64 = 1; 
- c4.l1cache.GetX_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; 
+ c4.l1cache.GetS_recv : Accumulator : Sum.u64 = 853; SumSQ.u64 = 853; Count.u64 = 853; Min.u64 = 1; Max.u64 = 1; 
+ c4.l1cache.GetX_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; 
  c4.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c4.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1075,8 +1075,8 @@ TrivialCPU cpu7 Finished after 1000 issued reads, 1000 returned (104578 clocks)
  c5.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c5.l1cache.GetS_recv : Accumulator : Sum.u64 = 863; SumSQ.u64 = 863; Count.u64 = 863; Min.u64 = 1; Max.u64 = 1; 
- c5.l1cache.GetX_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; 
+ c5.l1cache.GetS_recv : Accumulator : Sum.u64 = 853; SumSQ.u64 = 853; Count.u64 = 853; Min.u64 = 1; Max.u64 = 1; 
+ c5.l1cache.GetX_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; 
  c5.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c5.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1220,8 +1220,8 @@ TrivialCPU cpu7 Finished after 1000 issued reads, 1000 returned (104578 clocks)
  c6.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c6.l1cache.GetS_recv : Accumulator : Sum.u64 = 863; SumSQ.u64 = 863; Count.u64 = 863; Min.u64 = 1; Max.u64 = 1; 
- c6.l1cache.GetX_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; 
+ c6.l1cache.GetS_recv : Accumulator : Sum.u64 = 853; SumSQ.u64 = 853; Count.u64 = 853; Min.u64 = 1; Max.u64 = 1; 
+ c6.l1cache.GetX_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; 
  c6.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c6.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1365,8 +1365,8 @@ TrivialCPU cpu7 Finished after 1000 issued reads, 1000 returned (104578 clocks)
  c7.l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- c7.l1cache.GetS_recv : Accumulator : Sum.u64 = 865; SumSQ.u64 = 865; Count.u64 = 865; Min.u64 = 1; Max.u64 = 1; 
- c7.l1cache.GetX_recv : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; 
+ c7.l1cache.GetS_recv : Accumulator : Sum.u64 = 853; SumSQ.u64 = 853; Count.u64 = 853; Min.u64 = 1; Max.u64 = 1; 
+ c7.l1cache.GetX_recv : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; 
  c7.l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  c7.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1550,8 +1550,8 @@ TrivialCPU cpu7 Finished after 1000 issued reads, 1000 returned (104578 clocks)
  n1.l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 1045; SumSQ.u64 = 1045; Count.u64 = 1045; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 900; SumSQ.u64 = 900; Count.u64 = 900; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetS_recv : Accumulator : Sum.u64 = 471; SumSQ.u64 = 471; Count.u64 = 471; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.GetX_recv : Accumulator : Sum.u64 = 359; SumSQ.u64 = 359; Count.u64 = 359; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1562,15 +1562,15 @@ TrivialCPU cpu7 Finished after 1000 issued reads, 1000 returned (104578 clocks)
  n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.Inv_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 285; SumSQ.u64 = 285; Count.u64 = 285; Min.u64 = 1; Max.u64 = 1; 
- n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInv_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 279; SumSQ.u64 = 279; Count.u64 = 279; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- n1.l2cache.AckInv_recv : Accumulator : Sum.u64 = 333; SumSQ.u64 = 333; Count.u64 = 333; Min.u64 = 1; Max.u64 = 1; 
+ n1.l2cache.AckInv_recv : Accumulator : Sum.u64 = 331; SumSQ.u64 = 331; Count.u64 = 331; Min.u64 = 1; Max.u64 = 1; 
  n1.l2cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  n1.l2cache.MSHR_occupancy : Accumulator : Sum.u64 = 848215; SumSQ.u64 = 8879313; Count.u64 = 209156; Min.u64 = 0; Max.u64 = 32; 
  n1.l2cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -1746,8 +1746,8 @@ TrivialCPU cpu7 Finished after 1000 issued reads, 1000 returned (104578 clocks)
  l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l3cache.GetS_recv : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; 
- l3cache.GetX_recv : Accumulator : Sum.u64 = 941; SumSQ.u64 = 941; Count.u64 = 941; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetS_recv : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; 
+ l3cache.GetX_recv : Accumulator : Sum.u64 = 359; SumSQ.u64 = 359; Count.u64 = 359; Min.u64 = 1; Max.u64 = 1; 
  l3cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_1.out
index 939c5624e..e62cc56e4 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_1.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_1.out
@@ -127,9 +127,9 @@ TrivialCPU cpu Finished after 1000 issued reads, 1000 returned (109912 clocks)
  l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 976; SumSQ.u64 = 976; Count.u64 = 976; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 900; SumSQ.u64 = 900; Count.u64 = 900; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_2.out
index d66be9cac..bae9db041 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_2.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_2.out
@@ -128,8 +128,8 @@ TrivialCPU cpu Finished after 1000 issued reads, 1000 returned (104054 clocks)
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 905; SumSQ.u64 = 905; Count.u64 = 905; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_3.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_3.out
index 5b9d11a6b..86c90324c 100644
--- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_3.out
+++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_3.out
@@ -128,7 +128,7 @@ TrivialCPU cpu Finished after 1000 issued reads, 1000 returned (104054 clocks)
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 904; SumSQ.u64 = 904; Count.u64 = 904; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/miranda/tests/refFiles/test_miranda_copybench.out b/src/sst/elements/miranda/tests/refFiles/test_miranda_copybench.out
index 2cad0fae9..149869389 100644
--- a/src/sst/elements/miranda/tests/refFiles/test_miranda_copybench.out
+++ b/src/sst/elements/miranda/tests/refFiles/test_miranda_copybench.out
@@ -158,13 +158,13 @@
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 176952; SumSQ.u64 = 176952; Count.u64 = 176952; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 121951; SumSQ.u64 = 121951; Count.u64 = 121951; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 79362; SumSQ.u64 = 79362; Count.u64 = 79362; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 65536; SumSQ.u64 = 65536; Count.u64 = 65536; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetXResp_recv : Accumulator : Sum.u64 = 18597; SumSQ.u64 = 18597; Count.u64 = 18597; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetXResp_recv : Accumulator : Sum.u64 = 16384; SumSQ.u64 = 16384; Count.u64 = 16384; Min.u64 = 1; Max.u64 = 1; 
  l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/miranda/tests/refFiles/test_miranda_gupsgen.out b/src/sst/elements/miranda/tests/refFiles/test_miranda_gupsgen.out
index b28df5fe0..5a9e637f6 100644
--- a/src/sst/elements/miranda/tests/refFiles/test_miranda_gupsgen.out
+++ b/src/sst/elements/miranda/tests/refFiles/test_miranda_gupsgen.out
@@ -157,9 +157,9 @@
  l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 499; SumSQ.u64 = 499; Count.u64 = 499; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 15256; SumSQ.u64 = 15256; Count.u64 = 15256; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 10204; SumSQ.u64 = 10204; Count.u64 = 10204; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 14958; SumSQ.u64 = 14958; Count.u64 = 14958; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/miranda/tests/refFiles/test_miranda_inorderstream.out b/src/sst/elements/miranda/tests/refFiles/test_miranda_inorderstream.out
index cd2dc02c4..bec7e5a5d 100644
--- a/src/sst/elements/miranda/tests/refFiles/test_miranda_inorderstream.out
+++ b/src/sst/elements/miranda/tests/refFiles/test_miranda_inorderstream.out
@@ -158,13 +158,13 @@
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 43307; SumSQ.u64 = 43307; Count.u64 = 43307; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 19816; SumSQ.u64 = 19816; Count.u64 = 19816; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 23649; SumSQ.u64 = 23649; Count.u64 = 23649; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetXResp_recv : Accumulator : Sum.u64 = 4052; SumSQ.u64 = 4052; Count.u64 = 4052; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetXResp_recv : Accumulator : Sum.u64 = 3752; SumSQ.u64 = 3752; Count.u64 = 3752; Min.u64 = 1; Max.u64 = 1; 
  l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/miranda/tests/refFiles/test_miranda_randomgen.out b/src/sst/elements/miranda/tests/refFiles/test_miranda_randomgen.out
index 2d73dcd8e..0a4e02141 100644
--- a/src/sst/elements/miranda/tests/refFiles/test_miranda_randomgen.out
+++ b/src/sst/elements/miranda/tests/refFiles/test_miranda_randomgen.out
@@ -158,7 +158,7 @@
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 374852; SumSQ.u64 = 374852; Count.u64 = 374852; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 374824; SumSQ.u64 = 374824; Count.u64 = 374824; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetX_recv : Accumulator : Sum.u64 = 249940; SumSQ.u64 = 249940; Count.u64 = 249940; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/miranda/tests/refFiles/test_miranda_revsinglestream.out b/src/sst/elements/miranda/tests/refFiles/test_miranda_revsinglestream.out
index 6f601cf3a..9333340a4 100644
--- a/src/sst/elements/miranda/tests/refFiles/test_miranda_revsinglestream.out
+++ b/src/sst/elements/miranda/tests/refFiles/test_miranda_revsinglestream.out
@@ -162,7 +162,7 @@ ReverseSingleStreamGenerator[build]: Stride:                8
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 12288; SumSQ.u64 = 12288; Count.u64 = 12288; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 10240; SumSQ.u64 = 10240; Count.u64 = 10240; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/miranda/tests/refFiles/test_miranda_singlestream.out b/src/sst/elements/miranda/tests/refFiles/test_miranda_singlestream.out
index 96f627f95..643511493 100644
--- a/src/sst/elements/miranda/tests/refFiles/test_miranda_singlestream.out
+++ b/src/sst/elements/miranda/tests/refFiles/test_miranda_singlestream.out
@@ -158,13 +158,13 @@
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 1598900; SumSQ.u64 = 1598900; Count.u64 = 1598900; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 624026; SumSQ.u64 = 624026; Count.u64 = 624026; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetXResp_recv : Accumulator : Sum.u64 = 78136; SumSQ.u64 = 78136; Count.u64 = 78136; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetXResp_recv : Accumulator : Sum.u64 = 62510; SumSQ.u64 = 62510; Count.u64 = 62510; Min.u64 = 1; Max.u64 = 1; 
  l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/miranda/tests/refFiles/test_miranda_spmvgen.out b/src/sst/elements/miranda/tests/refFiles/test_miranda_spmvgen.out
index 7bd3721aa..c8cc9e1be 100644
--- a/src/sst/elements/miranda/tests/refFiles/test_miranda_spmvgen.out
+++ b/src/sst/elements/miranda/tests/refFiles/test_miranda_spmvgen.out
@@ -176,13 +176,13 @@ l2cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to
  l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.GetS_recv : Accumulator : Sum.u64 = 1684; SumSQ.u64 = 1684; Count.u64 = 1684; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetX_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetS_recv : Accumulator : Sum.u64 = 1542; SumSQ.u64 = 1542; Count.u64 = 1542; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetX_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.Inv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -336,19 +336,19 @@ l2cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to
  l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.GetS_recv : Accumulator : Sum.u64 = 1362; SumSQ.u64 = 1362; Count.u64 = 1362; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetX_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetS_recv : Accumulator : Sum.u64 = 1160; SumSQ.u64 = 1160; Count.u64 = 1160; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetX_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.Inv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.Inv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 24923; SumSQ.u64 = 399249; Count.u64 = 2741; Min.u64 = 0; Max.u64 = 21; 
diff --git a/src/sst/elements/miranda/tests/refFiles/test_miranda_stencil3dbench.out b/src/sst/elements/miranda/tests/refFiles/test_miranda_stencil3dbench.out
index 5c80bb508..039bd53fc 100644
--- a/src/sst/elements/miranda/tests/refFiles/test_miranda_stencil3dbench.out
+++ b/src/sst/elements/miranda/tests/refFiles/test_miranda_stencil3dbench.out
@@ -158,13 +158,13 @@
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 152740; SumSQ.u64 = 152740; Count.u64 = 152740; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 7136; SumSQ.u64 = 7136; Count.u64 = 7136; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 114152; SumSQ.u64 = 114152; Count.u64 = 114152; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 4032; SumSQ.u64 = 4032; Count.u64 = 4032; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetXResp_recv : Accumulator : Sum.u64 = 1363; SumSQ.u64 = 1363; Count.u64 = 1363; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetXResp_recv : Accumulator : Sum.u64 = 1303; SumSQ.u64 = 1303; Count.u64 = 1303; Min.u64 = 1; Max.u64 = 1; 
  l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/miranda/tests/refFiles/test_miranda_streambench.out b/src/sst/elements/miranda/tests/refFiles/test_miranda_streambench.out
index 74c3aa0f6..585fd2aff 100644
--- a/src/sst/elements/miranda/tests/refFiles/test_miranda_streambench.out
+++ b/src/sst/elements/miranda/tests/refFiles/test_miranda_streambench.out
@@ -158,13 +158,13 @@
  l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetS_recv : Accumulator : Sum.u64 = 45552; SumSQ.u64 = 45552; Count.u64 = 45552; Min.u64 = 1; Max.u64 = 1; 
- l1cache.GetX_recv : Accumulator : Sum.u64 = 17969; SumSQ.u64 = 17969; Count.u64 = 17969; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetS_recv : Accumulator : Sum.u64 = 25776; SumSQ.u64 = 25776; Count.u64 = 25776; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetX_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; 
  l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache.GetXResp_recv : Accumulator : Sum.u64 = 7536; SumSQ.u64 = 7536; Count.u64 = 7536; Min.u64 = 1; Max.u64 = 1; 
+ l1cache.GetXResp_recv : Accumulator : Sum.u64 = 7500; SumSQ.u64 = 7500; Count.u64 = 7500; Min.u64 = 1; Max.u64 = 1; 
  l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/shogun/tests/refFiles/test_shogun_basic_miranda.out b/src/sst/elements/shogun/tests/refFiles/test_shogun_basic_miranda.out
index ec92c2ab0..843c1415c 100644
--- a/src/sst/elements/shogun/tests/refFiles/test_shogun_basic_miranda.out
+++ b/src/sst/elements/shogun/tests/refFiles/test_shogun_basic_miranda.out
@@ -174,9 +174,9 @@
  l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 12419; SumSQ.u64 = 12419; Count.u64 = 12419; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetS_recv : Accumulator : Sum.u64 = 153683; SumSQ.u64 = 153683; Count.u64 = 153683; Min.u64 = 1; Max.u64 = 1; 
- l1cache0.GetX_recv : Accumulator : Sum.u64 = 109063; SumSQ.u64 = 109063; Count.u64 = 109063; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache0.GetS_recv : Accumulator : Sum.u64 = 145229; SumSQ.u64 = 145229; Count.u64 = 145229; Min.u64 = 1; Max.u64 = 1; 
+ l1cache0.GetX_recv : Accumulator : Sum.u64 = 100000; SumSQ.u64 = 100000; Count.u64 = 100000; Min.u64 = 1; Max.u64 = 1; 
  l1cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -334,9 +334,9 @@
  l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 8483; SumSQ.u64 = 8483; Count.u64 = 8483; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetS_recv : Accumulator : Sum.u64 = 151376; SumSQ.u64 = 151376; Count.u64 = 151376; Min.u64 = 1; Max.u64 = 1; 
- l1cache1.GetX_recv : Accumulator : Sum.u64 = 106399; SumSQ.u64 = 106399; Count.u64 = 106399; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
+ l1cache1.GetS_recv : Accumulator : Sum.u64 = 145343; SumSQ.u64 = 145343; Count.u64 = 145343; Min.u64 = 1; Max.u64 = 1; 
+ l1cache1.GetX_recv : Accumulator : Sum.u64 = 100000; SumSQ.u64 = 100000; Count.u64 = 100000; Min.u64 = 1; Max.u64 = 1; 
  l1cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
diff --git a/src/sst/elements/shogun/tests/refFiles/test_shogun_hierarchy_test.out b/src/sst/elements/shogun/tests/refFiles/test_shogun_hierarchy_test.out
index 5ce6e6414..a24a499f5 100644
--- a/src/sst/elements/shogun/tests/refFiles/test_shogun_hierarchy_test.out
+++ b/src/sst/elements/shogun/tests/refFiles/test_shogun_hierarchy_test.out
@@ -342,7 +342,7 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l1cache_1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_1.GetS_recv : Accumulator : Sum.u64 = 600005; SumSQ.u64 = 600005; Count.u64 = 600005; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_1.GetS_recv : Accumulator : Sum.u64 = 400000; SumSQ.u64 = 400000; Count.u64 = 400000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
@@ -512,7 +512,7 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated
  l1cache_2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
- l1cache_2.GetS_recv : Accumulator : Sum.u64 = 600005; SumSQ.u64 = 600005; Count.u64 = 600005; Min.u64 = 1; Max.u64 = 1; 
+ l1cache_2.GetS_recv : Accumulator : Sum.u64 = 400000; SumSQ.u64 = 400000; Count.u64 = 400000; Min.u64 = 1; Max.u64 = 1; 
  l1cache_2.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
  l1cache_2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; 
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