public void clock ( int /* cycle_count */ delta_t ) { // No operation if test bit is set. if ( test != 0 ) { return ; } int /* reg24 */ accumulator_prev = accumulator ; // Calculate new accumulator value; int /* reg24 */ delta_accumulator = delta_t * freq ; accumulator += delta_accumulator ; accumulator &= 0xffffff ; // Check whether the MSB is set high. This is used for synchronization. msb_rising = ! ( ( accumulator_prev & 0x800000 ) != 0 ) && ( ( accumulator & 0x800000 ) != 0 ) ; // Shift noise register once for each time accumulator bit 19 is set // high. // Bit 19 is set high each time 2^20 (0x100000) is added to the // accumulator. int /* reg24 */ shift_period = 0x100000 ; while ( delta_accumulator != 0 ) { if ( delta_accumulator < shift_period ) { shift_period = delta_accumulator ; // Determine whether bit 19 is set on the last period. // NB! Requires two's complement integer. if ( shift_period <= 0x080000 ) { // Check for flip from 0 to 1. if ( ( ( ( accumulator - shift_period ) & 0x080000 ) != 0 ) || ! ( ( accumulator & 0x080000 ) != 0 ) ) { break ; } } else { // Check for flip from 0 (to 1 or via 1 to 0) or from 1 via // 0 to 1. if ( ( ( ( accumulator - shift_period ) & 0x080000 ) != 0 ) && ! ( ( accumulator & 0x080000 ) != 0 ) ) { break ; } } } // Shift the noise/random register. // NB! The shift is actually delayed 2 cycles, this is not modeled. int /* reg24 */ bit0 = ( ( shift_register >> 22 ) ^ ( shift_register >> 17 ) ) & 0x1 ; shift_register <<= 1 ; shift_register &= 0x7fffff ; shift_register |= bit0 ; delta_accumulator -= shift_period ; } }
SID clocking - delta_t cycles .