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Granite polish and sealer As property costs start their ascent in the transfer in direction of the middle of the year, many house owners are thinking of constructing extensions to their properties. There are two major reasons for this; firstly, with stamp duties and agent charges, buying an even bigger dwelling can be an expensive exercise and secondly renovating and lengthening can be good alternate options to moving. But for many who undoubtedly are selling, upgrading their properties first may be one of the simplest ways of bettering the revenue they may make on it.
Having a Goal
If householders are making changes to go well with their existence, then ending up with a home to swimsuit their needs needs to be primary on their agenda. Making changes with a purpose to sell for profit requires extra strategic planning. Even when they are talented at interior design and full of ideas, it's critical that they know what actually adds value to a home and what doesn't.
Changes That Do Add Value
Kitchen upgrades: Cupboard doorways, wall tiles and ground covers. These days, you can purchase prepared-to-use prefabricated granite countertops to add value to your kitchen.
Toilet upgrades: Wall and floor tiles, tub resurfacing, new vanity.
Paintwork: A fresh coat invariably adds much more than it prices to do.
Flooring coverings: Steam clear carpets, polish timber flooring. Timber is nice in residing areas, however persist with carpets within the bedroom.
Gardening: Tidy gardens and flooring beds, mow lawns and prune shrubs; most landscaping ought to give a good return on the price.
Climate Management: Heating in chilly climates and air-conditioning in sizzling climates create a cushty and welcoming feeling.
Extra rooms: Be careful to keep the room in proportion. Do not add two additional bedrooms until creating more dwelling area as nicely.
Garaging: Offering automobile parking typically adds a number of worth. Go for direct entry from the parking space into the house, if doable.
A radical clear: Dwelling should be detailed before it's bought – – first impressions are important.
What Might Not Add Value
Swimming pool and spa: These are lifestyle features for enjoyment and are notorious for not returning the cash spent on them.
Costly fittings: Curtains and light fixtures can date quickly.
Robust style themes: Brightly colored partitions and wallpaper are a personal style, so an skilled's recommendation ought to be sought first.
Further storage: While it is a crucial function, most individuals wouldn't pay further due to its presence.
Safety alarms: It may be vital however one could not recoup the price at sale time.
Checking the Space
The information given forms the fundamental guide. Householders ought to start by checking the neighborhood, as the location of the property is a significant determinant as to what adds value to a home and what does not.
Family houses in prestigious areas are a distinct story from a small unit within the metropolis. It ought to be thought fastidiously as where they are and what are they making an attempt to do.


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BRICS bank: all eyes turn to Durban
14 March 2013The world will be watching closely to see whether the leaders of Brazil, Russia, India, China and South Africa can conclude negotiations for setting up a BRICS development bank when they meet in Durban in less than two weeks' time.The 5th BRICS summit will take place in Durban on 26 and 27 March.Emerging markets analysts believe a BRICS development bank – first mooted at last year's BRICS summit in Delhi, India – could help create jobs in South Africa and promote greater trade on the African continent by funding new infrastructure.Last week, International Relations Minister Maite Nkoana-Mashabane told City Press newspaper that South Africa was keen to host the development bank, saying the country had a history of sound financial expertise and that the African continent was home to seven of the 10 fastest growing economies.Trade and Industry Minister Rob Davies said this week that South Africa had a strategic interest in extending BRICS cooperation to support Africa's development agenda. He added that he believed Africa's relationship with BRICS had influenced growth on the continent.Finance ministers working on business planThe finance ministries from the five member countries have been working on a business plan for the development bank, and met on the sidelines of the G20 conference in Moscow last month to explore the bank's potential structure.World Bank chief economist Kaushik Basu has backed the idea for a BRICS development bank, but warned that it would be a "humongous task" to set up.While Martyn Davies, the chief executive of Frontier Advisory, said in January that there had been discussion of a fund of up to US$240-billion, Standard Bank expects each of the five member states to initially contribute $10-billion in seed capital for the bank, with further funds raised from the markets as necessary.However, Standard Bank research analysts Jeremy Stevens and Simon Freemantle cautioned that China's eventual contributions might outpace that of the other BRICS members and that, if this happened, Beijing would understandably demand commensurate influence over the fund's decision-making mechanisms.Challenge posed by Chinese dominanceIn a research note last month, Stevens and Freemantle pointed out that while for China $10-billion amounts to just 0.12% of gross domestic product (GDP) (as per 2012), the same contribution would constitute a far more hefty 2.5% of South Africa's total economic output.Added to this, China dominates BRICS trade and is the number one import partner for all four of its BRICS partners; its economy at the end of 2012 was almost 25% larger than the other four BRICS nations combined."Unless pragmatically managed, political strains similar to those faced within the IMF may emerge. An appreciation of this potential challenge should thus frame deliberations in Durban," said Stevens and Freemantle.They expect the development bank to focus on infrastructure development and providing auxiliary support for project preparation, such as feasibility studies. They said they expected a working group to be later tasked with establishing the necessary technical commitments and governance structures.The two believe that the development bank would not be a counterweight to multilateral development banks – notably the World Bank – but rather act an auxiliary funding institution.Benefits for South AfricaIn a parliamentary reply this week in response to a question from an opposition MP on what the impact had been of South Africa's membership of BRICS, Economic Development Minister Ebrahim Patel said the country had enjoyed several benefits.Patel said South Africa had grown its level of trade with the BRICS countries, had seen significant growth in tourism from other BRICS countries, was now a stronger destination for potential investment, and was able to influence the development of greater BRICS partnerships with the rest of the African continent.On trade, the four other BRICS countries now account for a larger share of South Africa's imports and exports. Measured in US dollars, exports from South Africa to its BRICS peers rose from $12.1-billion in 2010 to $15-billion in 2012, Patel said"This helped to compensate for reduced demand from traditional markets which are experiencing slower or negative growth."Source: SAnews.gov.za
Planning for high yielding soybeans
Share Facebook Twitter Google + LinkedIn Pinterest By Matt Hutcheson, CCA product manager, Seed Consultants, Inc.When planning for the upcoming growing season, it can be easy to focus more energy on corn production as it has traditionally been the more intensively managed crop. However, producers who put in the effort to manage their soybean crop have proven it is possible to attain high yields of 70+ bushels per acre. Below are some tips for planning to produce high-yielding soybeans in 2019.Quality seed: Planting the right seed sets the stage for the entire growing season. Growers should plant genetics with high yield potential. Choose varieties that have been tested at several locations and across multiple years. Growers should choose varieties adapted to their soil types and management practices. As with corn, choosing varieties with strong disease packages and agronomic traits with aid in achieving higher yields.Planting date: University research has proven that timely, early planting is one way to increase soybean yields. As with corn, planting soybeans by early May improves yield potential. This Ohio State University Study showed a 2.5-bushel per acre yield improvement when planting May 8 vs. May 29. Purdue University has also documented maximized soybean yields for early May plantings in this study.Seed treatments: Seed treatments are a critical component of a soybean management program, especially for growers who plant early or into no-till or minimum tillage situations. Early in the growing season when soils and weather conditions are cooler, germination and growth will be slowed down. Seed treatments provide protection from diseases and early season pests that can significantly reduce stands, decreasing yields and/or resulting in the need for replant.Fertility and pH: Adequate soil fertility is another important factor that allows soybeans to reach their maximum yield potential. Consulting soil tests and university recommendations for adequate levels of nutrients as well as crop removal rates will help determine how much potassium and phosphorus should be applied. When the proper pH range is maintained, soil nutrients will be available to the soybean plant for uptake. Generally, a pH range between 6.2 and 6.8 maximizes soybean yields. Adequate pH levels also improve the ability of Rhizobium bacteria to fix nitrogen.Inoculant: Inoculation of seed with Rhizobium will ensure that enough bacteria are present in the soil to fix adequate amounts of N. This is especially important in fields where soybeans have not been grown for multiple years.Row widths and seeding rates: Row widths and seeding rates go hand-in-hand. University research shows that narrower rows (15in or less) increase yields. Narrower rows allow for plants to canopy earlier and capture optimum levels of sunlight for photosynthesis. Seeding rates will vary based on row width, planting date, germ of soybean seed, and soil types. While some research recommends lower seeding rates, growers should take into consideration historical performance on their own farms. While seeding rates that are unnecessarily high, low seeding rates can result in reduced stands. Seeding rates may need to be higher in low yielding environments where emergence is a concern and plant stands can be diminished due to tough growing conditions. Proper seeding rates will improve emergence on the Eastern Corn Belt's tight clay soil types where adverse conditions exist.Disease and pest management: Growers should plant soybean varieties with adequate disease resistance. Scouting throughout the growing season will also be important to determine if rescue treatments including fungicides or insecticides need to be made.While it can be tempting to try the latest technology or new foliar product to drive yields, it is important to start with the important building blocks first. This Checklist from the University of Kentucky agronomist, Chad Lee is another resource for putting together a plan for producing soybeans in the 2019 growing season. Growers who take time to properly manage their soybeans will move closer to attaining the high-yield potential of today's soybean genetics.
Jimmy Wales Joins Open Textbook Organization
A Web Developer's New Best Friend is the AI Wai… dana oshiro Why Tech Companies Need Simpler Terms of Servic… Related Posts Wikipedia and Wikia co-founder Jimmy Wales has just joined the advisory board of CK-12 Foundation – a nonprofit organization that provides standards-aligned online textbooks to kindergarten to grade 12 students. One key element of the organization includes offering "FlexBooks" – a product that allows educators and students to create and edit their own open-content teaching materials. Users can add chapters to existing texts or create completely new material using the Flexr tool. Some key benefits over traditional textbooks include: wider distribution, lower costs, teacher recommendations and customizable texts. The latter is particularly significant as educators can adapt textbooks to ensure they are timely, aligned to state standards and culturally appropriate. Additionally, educators can even adapt texts to set students on independent learning programs with ease. This is especially important for those educators who work with gifted students and students with developmental disabilities. In addition to Wales, other CK-12 advisory board members include CEO of Sun Microsystems Vinod Khosla, CTO of JotSpot Graham Spencer and founding principal of the High Tech High charter school program, Larry Rosenstock. Tags:#E-Books#E-Learning#web CK-12 intends to make use of the Creative Commons Attribution-Share Alike license. Meanwhile, Wales' other open textbook project, Wikibooks, is licensed as GNU Free Documentation. Both licenses ensure that the book content is free to be copied, redistributed and modified for either commercial or non-commercial use with the only major stipulation being that author's receive attribution. Wikibooks currently has over 38,602 volunteer edited pages with subject matter in natural sciences, computing, humanities and social sciences. The project already includes books from at least 15 different languages. According to CK-12, the difference between Wikipedia and CK-12 is that the organization "specifically focuses on K-12 standards-based content centered around the STEM (science, technology, engineering, and math) subjects vs. serving as an encyclopedia of knowledge…CK-12 offers materials such as lesson objectives, vocabulary, and Q & A – similar to those found in textbooks." However, the group does not address comparisons with Wikibooks. At this early stage with CK-12, the key difference between Wikibooks and CK-12 appears to be that the latter organization envisions one day supplying printed textbooks via an on-demand press similar to Lulu or Blurb. Top Reasons to Go With Managed WordPress Hosting 8 Best WordPress Hosting Solutions on the Market
Baseband Hacking: A New Frontier for Smartphone Break-ins
Security researcher Ralf-Philipp Weinmann says he has found a new way to hack into mobile devices – by using a baseband hack that takes advantage of bugs found in the firmware on mobile phone chipsets sold by Qualcomm and Infineon Technologies. Weinmann will demonstrate the hack on both an iPhone and an Android device at this week's Black Hat conference in Washington D.C.Previously, mobile hacking attempts have involved the phone's operating system or other software, but this one focuses on breaking into a phone's baseband processor, which is the hardware that sends and receives radio signals to cell towers.Baseband Hacking DetailsIn an IDG News Service report as well as a report on LinuxInsider, this new hack is described in detail. In short, it's a very technical undertaking which involves setting up a fake cell tower to communicate with the target devices. In past years, that was an impossible task due the costs involved – tens of thousands of dollars. But now, thanks to new open-source software called OpenBTS, anyone can build a tower with $2,000 worth of computer equipment. Mobile carriers are also making the necessary hardware more affordable, too, by providing femtocells to consumers in an effort to broaden their mobile coverage. These femtocells, like AT&T's 3G MicroCell, are even less expensive; AT&T's is just $150.00.To perform the attack, Weinmann sets up a rogue base transceiver station which is used to send malicious code over the air to the target devices. The code exploits vulnerabilities found in the GSM/3GPP stacks on the phones' baseband processors. Says Weinmann, industry bodies like the GSM Association and the European Telecommunications Standards Institute have not considered the possibility of attacks like this.Should You Be Concerned?In addition to the cost of this particular hack – still a bit pricey – the code Weinmann wrote is notable because it involves in-depth knowledge of chipset firmware, something few hackers know much about, says the IDG news report.Essentially, Weinmann is helping open up a whole new vector for smartphone hacking, an avenue which is just now being explored by a handful of researchers. In August, for example, Chris Paget demonstrated cell tower spoofing at the Defcon hacking conference in Las Vegas, after getting last-minute permission from the U.S. Federal Communications Commission to do so. And in two months time, other researchers will demonstrate more baseband attacking techniques at Vancouver's CanSecWest conference.In other words, this is still an emerging area for hackers.It's too early to say what the ramifications are for this new baseband hacking technique, but for now security experts say that the general public shouldn't worry about attacks like this coming in the near future.According to Sophos security consultant Graham Cluley, "if someone wanted to spy on your mobile phone conversations it would be easier to trick the user into installing an app that spied on them or gain physical access to the mobile to install some spyware code," he said. "I would be surprised if anyone went to all of the effort that this researcher suggests." What it Takes to Build a Highly Secure FinTech … sarah perez Related Posts Why IoT Apps are Eating Device Interfaces Role of Mobile App Analytics In-App Engagement The Rise and Rise of Mobile Payment Technology Tags:#Apple#Google#mobile#news#NYT#security#web
Maharashtra govt. to provide relief to farmers hit by untimely rains
Maharashtra Chief Minister Devendra Fadnavis on Monday asked the Chief Secretary to carry out assessment of crops damaged due to untimely rains at the earliest so that immediate relief can be provided to farmers. Heavy post monsoon showers in some parts of the State in last few days damaged crops and inundated low-lying areas. Taking serious note of it, Mr. Fadnavis ordered completion of crop damage assessment at the earliest."CM @Dev_Fadnavis instructed Chief Secretary to provide immediate relief to farmers who were affected by the heavy rains in some parts of Maharashtra by completing survey at the earliest," the Chief Minister's Office (CMO) tweeted. Heavy rains lashed parts of Hingoli, Parbhani, Aurangabad and Jalgaon districts in last few days. A man and his son were killed when a wall of their house collapsed on them in Parbhani on Sunday, an official said. Besides, a person drowned in a canal while trying to cross it in Hingoli, he added.
FIFA U-17 World Cup: 10-L Maha kids to play football on Sep 8
Mumbai, Aug 4 (PTI) Ten lakh school students in Maharashtra will play football on September 8, ahead of the FIFA U-17 World Cup, state sports minister Vinod Tawde said here today.The FIFA U-17 World Cup is being held in India from October 6 to 28 this year."The September 8 event will be part of the Mission Million we are organising to mark the tournament," the minister told reporters at Mantralaya here."On that day, the entire Maharashtra will turn into one happy playground," he added."One lakh footballs have been distributed in one over 30,000 schools in Maharashtra as part of Mission Million," the minister said."Prime Minister Narendra Modi has called for ushering in sports culture in the country and we are organising the Mission Million event in response to his appeal," Tawde said.A football tournament for legislators is also being organised next week, Tawde said.Two teams, called the Speakers Eleven and the Chairmans Eleven will compete in it, the minister added. PTI VT NP
Tough Draw for Olympiacos
Olympiacos' hoopsters didn't get rewarded for winning its group in Euroleague play and were placed in a draw with the toughest opposition.The Reds begin European play on Dec. 29 while Panathinaikos, which finished third in its group, got a far easier set of opponents in its draw of 16.In a meaningless game, a listless Olympiacos, playing without Vassilis Spanoulis and Matt Lojeski, lost handily at home, 81-68, to the Turkish team Anadolu Efes.Olympiakos is now in the same group as Real Madrid, Barcelona, CSKA Moscow, Khimki, Zalgiris Kaunas, Laboral Kutxa and Bamberg.Panathinaikos will be grouped with Malaga, Red Star Belgrade, Lokomotiv Kuban, Cedevita Zagreb, and three Turkish teams: Fenerbahce, Darussafaka and Efes. The top four teams of each group of eight advance to the play-offs.TweetPinShare0 Shares

subset: commoncrawl


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Ted Lieu attended Stanford for his undergraduate degrees in Computer Science and Political Science, and then Georgetown University, where he received his law degree magna cum laude after serving as Editor-in-Chief of the law review. Ted also received four American Jurisprudence Awards.He joined the United States Air Force, where he served as a prosecutor in the JAG corps. After serving on active duty for four years, Ted wanted to continue to serve his country and joined the reserves. Currently, Ted wears a uniform in the JAG corps and was recently promoted to Lieutenant Colonel. Ted has received numerous medals for his outstanding military service, including the Air Force Humanitarian Service Medal and two Meritorious Service Medals.Ted's service at Los Angeles Air Force base is what brought him to Southern California. Professionally, Ted clerked on the Ninth Circuit Court of Appeals, practiced civil law at Munger, Tolles & Olson, and then worked at a financial services company before he joined the Legislature. Locally, Ted continued to serve his community. Ted served on the Rampart Independent Review Panel, the Torrance Environmental Quality and Energy Conservation Commission, and was later elected to the Torrance City Council. When the local Assemblymember passed away suddenly in 2005, Ted was overwhelmingly elected in a special election.After serving three terms in the Legislature, Ted was elected to the State Senate in February 2011 with 57% of the vote. This is his first race for Congress. Ted Lieu and his wife Betty live in Torrance with their two sons, Brennan and Austin.


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The Training Mode is a set of five missions available to play in Syphon Filter: Logan's Shadow. Gabe Logan is able to run through each course aided by Teresa Lipan in order to test functionality for recruits. Gabe will act as a recruit to insure the player is introduced to all of the game's basic controls.
TRAINING ONE: Basic Movement
Learn basic Agency movement and controls.
'Navigation and Movement'
Teresa has asked me to help her set up a new Agency Training Exercise. The goal is to teach the essentials of tactical movement, including climbing, crouching, ladders, shimmying, shimmying around corners and the Agency Rapid Traversal Line (RTL).
She's timing me and wants to know if I can beat the record completion time of 1:35. I told her I'd run through it a couple of times first before trying to break the record.
--Gabe Logan
The first training mission will cover basic movements for the player. These actions include running, climbing, crouching, use of the RTL, Nightvision Goggles, Infrared Goggles and Electronic Device Sensing Utility Goggles. The course is lined with bright blue arrows which will direct the player on where to go and prompts to hit the SELECT button will call Teresa to give you information on each obstacle. Gabe is also equipped with the Paintball Gun fashioned after the MARK 23 SD modified to fire paintballs and is used for training purposes.
Follow Teresa's Directions and basics needed later in the game will be explained to the player as they progress. Upon completion, she will notify Gabe of two hidden RTL Lines that can be used to beat the course faster.
If the player is able to beat the mission within record time of 1:35, they will unlock the SP-57. There are two methods to beating the time.
Method 1: Clean Run
This method requires you to follow the course as normal without using the shortcuts. The time frame for this is strict leaving little room for error.
- Immediately climb the first obstacle and turn to climb up the next one.
- Drop from here holding right so you can quickly crouch and go through the hole. Make sure to wait for the camera shift before pressing the crouch button again to stand up.
- Quickly climb the next two obstacles and shimmy along the edge to cross above the fence. Quickly equip your gun and let go of the ledge.
- Once you land skip the scene and aim at the small grey box above the door shooting it. Quickly equip "Bare Hands" to remove the gun.
- Follow the path climbing up obstacles and dropping to the left where you'll crawl into another hole. As with before, wait until the camera shifts up before hitting the crouch button again to stand.
- Access the control panel and type in "989" (the code will always be the same)
- Equip the nightvision goggles and kick open the door, navigating through the doorways in this dark area.
- When the X is reached use the RTL and make it over the fence. Quickly drop down and climb the ladder. Run along the path until the ending has been reached.
With few errors the goal can be reached in about 1:30.
Method 2: RTL Shortcuts
This method allows the player to shave time off their overall run.
- Climb the first two obstacles and head left after the drop. There will be a brown crate to climb as well as another shipping container. When on top, turn and climb up the next shipping container to the left.
- Immediately use the RTL button to hit the line and traverse it until above a set of crates ontop of a shipping container. Make sure to drop on the crate as dropping on the next path will result in a death.
- From here drop to the stairs and follow the path until outside the keypad. Go to the right of the keypad and climb the shipping container here and drop forward to where a set of crates are seen stacked in the middle of an open area. Climb to the top of these crates and use the RTL Line.
- Traverse it until above the walkway and head to the mission completion.
Successful completion under the time limit will reward the player with the SP-57.
- Unequipping the Paintball Gun will enable the player to avoid accidentally reloading it when needing to climb obstacles. It will automatically be pulled out after use of an RTL Line.
- The code will always be 989, so subsequent runs the player is not required to look through the hole in the wall with Nightvision equipped to see it.
TRAINING TWO: Basic Combat
Learn basic Agency combat techniques and controls.
'Basic Combat'
Teresa has asked me to help her test our new Agency Basic Combat Training Exercise. The goal is to teach the essentials of tactical combat, including weapon handling, aiming, HUD elements, and basic combat maneuvers such as snap to surface and melee attacks.
She also wants to time me. Eventually, I'm going to try to beat the course record time of 3:00, but for now, I'm going to pretend that I'm a raw recruit who doesn't know what the hell I'm doing.
--Gabe Logan
The first training mission will cover basic combat techniques for the player. These actions include finding a weapon from a Weapon Crate, explain the basics of where each gun is assigned, reticle explanation, crouching, snap to surface and aiming as well as target practice and melee attacks. Teresa will direct the player on The course features several boxes that will sprout targets the player can shoot and prompts to hit the SELECT button will call Teresa to give you information on each obstacle. Gabe is able to obtain the Paintball Gun fashioned after the MARK 23 SD modified to fire paintballs and is used for training purposes.
This is the first course where live recruits are used. They will not attack and simply move throughout the area until they've positioned themselves in set locations. Simply go through each segment of the course to complete it. Certain activities will be locked until you reach them such as the EDT and Knife.
If the player is able to beat the mission within record time of 3:00, they will unlock the FAMAS. Below is a rundown of how to complete it quickly:
- Approach the weapon box and grab the handgun. Equip it and crouch, forcing the targets to pop up. Shoot each of them quickly (accuracy does not matter) to move to the next section.
- For the Snap To Wall segment, make sure you are snapped as shots to the targets while not snapped will not count. Hit the one on the left, right then the low surface snap to end this segment.
- Run up and hit the guy in the face with an elbow. Repeat this with the next five, avoid getting behind them so that Gabe won't break their neck wasting an extra second or so.
- When the EDT section starts, equip it and taser the guy until he collapses.
- For the final section, equip the knife and run up to him using it real quick to end the course.
The timing for this mission is forgiving so there is room for error.
TRAINING THREE: MB 150 Rifle and darts
Learn basic Agency MB 150 rifle and darts.
TRAINING FOUR: Advanced Combat
Learn advanced AGency combat techniques and controls.
TRAINING FIVE: Water Training
Learn basic Agency underwater movement and combat controls
- The code used in Training Mission 1 is "989" which is a reference to 989 Studios, the developer behind the Playstation Trilogy.
- The trainees will speak after they've been taken out to suggest they haven't been killed. Examples include frying one with the EDT and striking another with the knife. This does not count for trainees where the player breaks their neck or hits them with any of the varying darts.


text: Great Travel Tips For All Trips Whether you have booked a trip out of town, out of the state, or even out of the country, there is a good chance that you will benefit from the useful advice found in this selection of handpicked travel tips. From packing your bags to shopping for souvenirs, enjoy these tips. If you're going to be travelling by air, make sure you don't put any valuables or electronics in your checked luggage. Luggage handlers aren't known to be gentle and any electronics may end up damaged during transport. Airlines are also known to lose luggage and you don't want to take a chance of losing something valuable. Before purchasing a package deal for travel, check out the prices of the individual components. Not always, even though in many cases, the package deals are cheaper than buying the pieces separately. It never hurts to check out pricing for yourself before becoming locked in to purchasing the whole package, and you might discover there's a part of the package you don't want, such as meals. When you arrive in a new hotel room, let the hot water run in the shower for a little while. Even the nicest of hotels can be somewhat dirty. Letting the hot water run will help kill spores that the regular cleaning might have missed. You aren't paying for the water bill in the room anyway. When traveling, never take an item from someone to transport it for them. No matter their situation or how nice they may seem, this is almost always a trap to convince an unwary tourist to transport drugs or other contraband into secure areas. Even "gifts" can fall into this category. Make multiple copies of your travel documents, before you leave home. Store these in separate bags. It may also be a good idea to scan them onto a flash drive, and carry it with you. Emailing them to yourself can be another method. Make sure you have several backups. You do not want to get stuck in a foreign country! The stark views offered by a desert have their own unique beauty, and you will enjoy experiencing their exotic fauna and flora. There is something especially memorable about deserts for the first-time visitor, and no one should go their entire lives without experiencing the austere majesty of the desert. Traveling with any kind of electronics means that you constantly have to charge batteries that you would normally charge at home. One of the most convenient means of doing this while on the road is to buy an inverter and plug it into your vehicle's cigarette lighter. That way you can use the same chargers you normally use at home. Before you arrive there, Try and get as much knowledge of the destination you're going to travel to. You want to have an idea of the things you want to do rather than finally getting to the hotel and feeling lost and bored. You can also ask hotel employees and locals where good places to check out are. Try to avoid jet lag during your trips by following these simple things. Start by resetting your watch before boarding your plane. Make sure that you stay incredibly hydrated after, before and during the flight. Before your trip, try exercising and sleeping well days. Fly on morning flights if you cannot sleep on a plane. Seek and avoid light as you need it until your body adjust to the time differences. Before you pack, it is wise to make a checklist. If you forgot something, this helps so that once you put away each item, you can check it off the list and not have to worry. It will also help the packing process go quicker, leaving time to do other last minute things. Bring a travel mug with you if you are traveling on a cruise ship. There is always an unlimited amount of tea and coffee on the ship, but the cups they have on board are usually very little. Taking a mug will prevent you from having to fill up several times each morning. You can also use it at the buffet line to stop spills. One way to makes sure that you don't get ill from eating and drinking during your travels is to pay attention to how your food is prepared. Try to avoid undercooked or raw meats. Generally anything boiled or fruits and veggies that require peeling are fairly safe things to eat. After getting settled in your hotel room, look for fire exits. It can save your life, although this may seem trivial. By knowing where the fire exits are - if the fire alarm goes off - you know which direction to leave. Also, try not to forget your hotel key or card in the event of a fire evacuation. When filling out your luggage tag, do not put your home address on it. Instead, fill in your business address. This is beneficial should your luggage get into the wrong hands-- you do not want a thief to know your home address. Also, put your business phone number on the tag instead of your home or cell number. A great travel tip is to be careful about how you show your money when you're in public. If you dig into your pockets and lift out a big wad of cash, thieves might take notice and lock onto you. It's best to be discrete at all times with your cash. When traveling through a busy airport with children, dress them in bright colored clothing. A bright color will be easier to recognize, should you become separated. It will also be easy to remember (and tell airport security) what your child is wearing if they are dressed in brighter, more unusual colors. While packing, try to keep your belongings as light as possible to reduce the amount of tension on your back. The last thing that you will want is to have to transport heavy bags from one place to another with items that you do not need. Stay practical to optimize your traveling experience. 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05-21-2020, 07:33 AM (This post was last modified: 05-21-2020, 07:42 AM by Luke_Kuechly_59.)
As we all know it's so common to get so frustrated and stressed while playing darts, like hitting an occasional 26 exactly where you don't need it
Then you are confident that you' re going to apply a fine practice performance of hitting a fair amount of tons on the 20 section right to a 501 game. But you can't hit, you are scoring 26s, 22s, 45s etc, frustration takes its toll to your mood to the point you ends up feeling like vacation is so much needed! First thought: it's the darts i'm using. They're the wrong darts for me, they are not fine tuned, the flights, the grip, my throw, etc.
Then you realize it's way more than that. It's just a personal battle with yourself. Battling with thoughts, ideas that come to mind, off-the shelve "universally"-applied word-of-mouth "dos and don'ts", things you read, things you hear you have to challenge, your responses to them, your knowledge of your body, the coordination of eyes with the arm, sight with the body, arm with the brain, mathematics , well anyone can tell how hard the whole process of setting up for just a round of 3 darts to the board could ever be.
So after a long period of frustration over my inconsistency issues all over the sport, i've started realize what everybody used to talk about being in a better position: make your throw a repetitive routine process. So i started to focus on observing my whole body and brain experience while practicing: trying different grips, different stances, etc until i reached a standard level of comfort and also learnt to reproduce it every time i'm preparing for a game.
If anybody asks me about my experience in Darts for that 1,5 year, the real answer would be like:
1st. Great sport to watch on TV, so emotional, so random, so unexpected, anyone could beat anyone on his day in a single leg of 501
2nd. A hobby that i love. Great pub darts & game memories, new friends, trips, jokes etc
3rd. (and most important) What A PAIN IN THE A** that is to do "well", what amount of detail and preparation is behind that "simple throwing move" from your hand to the board.
So it was about time to write down my whole "trip to the oche" process as a mean to understand details, rectify weaknesses, apply myself to new ideas and now, hopefully within the fellow community of online darts players, to share and talk about arguably what is the center of my attention when i play darts: myself! (sounds egocentric, but you should everyone know i mean the sport's character being an individual-based process). I will therefore share it with you, hoping that it could spark an idea that could attribute to any further improvement for each one of us.
Preparation routine for a 501 game
Pregame 9-dart routine: choose your personal 9-darts pregame routine you should always follow every time before games. Use it to create a level of alertness and be game-ready if needed. The goal is to establish a personal pregame routine to get used to.
Before setting up for a shot: always know your score left, either by subtracting your own score from 501, either by looking at the scoreboard right after your previous rounds. Do it as earlier as possible. It saves you some much time for preparation for other things.
Preparing for the trip to the oche: knowing your score gets you better prepared by visualizing the score you want to get to. E.g. When I have 261 left, I say to myself "261 minus 60 for 201, then if it's a s20 I'm thinking again 60 for 181 etc". Using mathematics for scoring visualization before i throw, i found to be such an ease. Then it works like a routine. I'm doing this when i know i have 310 left on the board.
Aiming (part 1): the aiming lasts for some moments, while doing other steps of the ritual. It starts for me when i go to the oche and look at the section/point i am about to aim. At this stage It's more a pre-aiming process: it's the moments where I have decided where to aim to and i'm preparing to "lock" to the target later (see part 2 later)
Feet stance position: the body slightly to the right side of the middle oche line, right foot on the center line of the oche. Let your heel feels like it's planted because if it's not it's very possible that you left foot could be in the air after each dart throw.
Right foot (i'm right-handed and right-eye dominant): the right foot feels right about at 40-45 degrees to the direction of the board, not too forward and not too sideways.
Plant-the-feet point: I usually make 2-3 lil swings with the front part of the right foot (like killing a cigarette on the road) to allow the heel and the front part of the foot to tune in for the most comfortable position. Like this i'm setting up the planting point. I find it good for my left foot then, to set up accordingly as well.
Right knee feel: very important. If my knee feels like I'm loading its muscles, I know I'm wrong there. My experience shows that this test can prevent from being over-fatigued over the course of a long practice/set of games. This is where I have a mental interrelation between the feel of the knee and the heel position. A good heel planting tells if the knee is bending comfortable. Sometimes i require to adjust where in-between throws, as the hand-off arm move to pick up the dart from the left had occasionally relocates the weight balance point, so i'm finding useful to move my right foot fingers so that they contribute in not letting the whole body lean towards right or left. It's a very useful in-game foot adjustment.
Left foot: it follows the planted foot with some distance so its big toe holds the whole left foot to the ground and support the overall lower section balance.
Body position: i'm trying to keep an upright body position with the chest and shoulders as wide open possible.
Breathing: natural. Do not hold air inside the lungs, better if you breathe out with a steady rhythm (equal amounts of air out of your mouth over the breathe out)
Aiming (part 2): for me is very important at the time of the breathing out process to lock the target you are aiming to. It's when I "lock" the target with my eyes and mind. Then it comes to the body to run the movement.
Left to right arm hand-off: i'm taking the dart with the right thumb by making two spins a-la-Suljovic with the minigrip section on the rear part of the barrel, then apply it to the thumb and index finger with a loose grip.
Dart weighting/balance: while the dart is loose, low in your right hand, make a Van Gerwen-like shake towards while bringing it up to prepare for the elbow move next.
Right hand pre-grip ritual: now i apply the middle finger on the dart point, where it makes a comfortable distance between the fingers feel (not too close, not too distant), while i lift the right arm.
Right hand lift: it's the part where I need to be comfortable with the dart balance feel and the middle finger grip. When I'm not I lower the right arm and prepare again the movement.
Elbow movement: In conjunction with the right hand lift, I am focused to set the elbow vertically to the dartboard but not too "locked". I'm trying not to bend the elbow much.
Grip: now after I feel good about the overall grip, I'm preparing for the final aiming.
Aiming (part 3): now that I have locked with my eyes and mind the target and I feel the comfortable grip in my right hand, I'm prepared to execute the final movement by bringing the dart near the head with that elbow movement.
Back-swing: very important for my throw as I feel like I want to have a continuous movement in my throwing routine to be aligned with the most important process for me, which is the dart weighting stage. By bringing the dart slightly backwards near the ear, I make a small movement forwards preparing for the throw, and then i propel the dart with a forward movement towards the target.
Release the dart: just do it and let your instincts tell when it's the right moment to let it go.
Follow through/ snap wrist: follow through is very important, I'm doing it naturally as i find it quite easy from previous my basketball experience. Wrist snap and follow through until the right hand finishes its natural movement.
(where needed) Readjust: be alert to adjust your aiming target for each dart, especially where vision is not possible of a dart blocks the area. Reset your feet if necessary, lower your body if necessary.
Final step: An 180 appears right front your eyes!!!
(Sorry for being too detailed and thank you for letting me share. There are so many things that comes to my attention while playing darts)
Final step: An 180 appears right front your eyes!!!
(Sorry for being too detailed and thank you for letting me share. There are so many things that comes to my attention while playing darts)
*couldn't make an edit for the paragraphs If anyone could help i would appreciate


text: jbaits 0 Posted December 5, 2019 Report Share Posted December 5, 2019 Is it possible to use a folder API key to manage all lists within the tree for folders with permissions propagating down? We do not want to have a global system API key available to users however we do have a need to automate use and creation of password lists and passwords within a single directory. This would include searching for an existing list, searching for a specific password entry in the list, and making the respective lists and entries if not found. Quote Link to post Share on other sites


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You may have noticed the other day that we posted about Tonight Alive announcing some exclusive UK dates
Following on from that, more dates have been revealed! Out of the eleven dates, four of them are '10 Year Anniversary Acoustic Performances', and tickets are set to go on sale THIS Friday over at Tonight Alive's Website.
Support (if there is any) has yet to be announced, and these shows will be taking place this November. A full list of the dates for your convenience:
Nov 8th – Glasgow / Oran Mur
Nov 9th – Newcastle / Northumbria Institute
Nov 10th – York / Fibbers
Nov 12th – Birmingham / O2 Institute 2
Nov 13th – Manchester / Club Academy
Nov 14th – Manchester / Club Academy *
Nov 15th – Birmingham / O2 Institute 2 *
Nov 17th – London / Islington Academy
Nov 18th – London / Bush Hall *
Nov 20th – Eindhoven / Dynamo
Nov 21st – Eindhoven / Dynamo *
(* Exclusive Acoustic Shows)
Excited? Let us know in the comments!


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Theresa May might not have appreciated it, but after the Brexit talks hit another wall, some of the most sympathetic reactions came from the European Commission (EC).
After her Brexit backtrack, Mrs May received supportive messages from her counterparts in the Belgian capital, with the commission saying it was waiting for a sign from her government before negotiations could resume.
"The show is now in London," said a spokesman for the EC president, Jean-Claude Juncker. Officials said that Mrs May had until Friday to hammer out a deal that could pave the way to opening trade talks in the new year – a four-day extension to the "absolute deadline" that the EU Council's president, Donald Tusk, had set on Monday.
Coverage in the European press noted the strains now tearing at the fabric of the UK itself. German daily Die Zeit described "a kingdom in disrepair… It is not the EU that is disintegrating, but Great Britain".
France's Le Figaro said the DUP could open "a Pandora's box for the other regions of the UK"


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Fast asynchronous resource master-slave combination
Resource master and slave combinations operating from separate local clocks asynchronously even though there may be wide speed variations among the devices, eliminating the need to synchronize the trailing edges of generated control signals with the local clock so as to free access to the resource as soon as possible without introducing timing or logic hazards.
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This application is related to co-pending patent application Ser. No. 07/589,718 filed on Sep. 28, 1993, now abandoned in favor of continuation patent application Ser. No. 07/908,931 filed on Jul. 6, 1992 ,titled ASYNCHRONOUS DAISY CHAIN ARBITER WITH FALSE SIGNAL LOCKOUT, assigned to the same assignee as the present patent application.BACKGROUND AND SUMMARY OF THE INVENTION
This invention relates to the control of data processing system resources by a plurality of devices using control masters and control slaves. It relates particularly to a network of devices of varying speeds and capacities where any control master must operate with any control slave for proper utilization of the resources. In a more specific application, it relates to bus control masters and bus control slaves in a system where the bus masters contend for access and control of a bus and, once gained through an arbitration controller, the bus control master and the bus control slave cooperate asynchronously to effect data transfers.
Electronic computer systems usually require that the processor have access to input and output devices for useful functioning. For most efficient operation, such devices operate independently from the central processor. That is, unlike early computer systems where the devices were controlled by the central processing unit, modern design moves the processing function into the device, permitting the central processor and the devices to function simultaneously and independently. At times, however, the devices must access resources shared with other devices and with the central processor. For example, a memory is often a shared resource and is accessed via a system bus. Various processors operate on data stored in the memory and some devices are used to store data from outside the system into the memory for processing while other devices read data from the memory for use outside the system, e.g., printing the results of computation and processing.
To reduce interference with the workings of the processor, a technique known as Direct Memory Access (DMA) is used to enable devices to read from or write to the memory without requiring processor intervention. The address of the data location in memory is stored in the device and used to address the memory during one or more cycles while the central processor and other devices are inhibited from accessing the memory. The DMA process operates as an interrupt procedure, so called because it doesn't always require access to the memory on a regular, periodic basis and interrupts the central system for access asynchronously. Such processes are also called cycle stealing.
All the devices cannot access the memory bus simultaneously because there would be no way to distinguish the separate signals. Therefore, resource requests must be arbitrated in a way that fulfills the requirements of all the devices. The problem of arbitrating multiple requests is covered in the cross-related, co-pending patent application Ser. No. 07/908,931. When a bus master gets control of the bus, a bus control master circuit operates together with a bus control slave at the system resource to perform the associated functions such as read or write from a DMA device to a memory.
Prior art bus control masters and bus control slaves sample the control signals and synchronize them to the local clock on both the leading and the trailing edges. This is a safe approach in that it avoids timing hazards and incorrect responses to false signals.
Such timing hazards are not always a problem in systems having bus control masters and bus control slaves that are designed to cooperate with one another and where there is a limited number of bus control masters and bus control slaves. In a system that comprises such devices of widely varying operating parameters or where the number of such devices are not to be limited in number, timing hazards create problems that have been avoided by synchronizing the leading and trailing edges of the control signals with the local clock, even in systems labelled asynchronous.
The bus control slave response to the deactivation of the signal that selected it is delayed until the asynchronous select signal is aligned with the local clock which takes two clock cycles. The synchronization to the local clock prevents the bus control slave from responding to a subsequent select signal before the slave's internal sequencing logic has completed aligning its clock with the external signal and returned to its initial state.
Similarly, the bus control master delays activating selection of the next bus control slave until the acknowledge signal from the previously selected bus control slave has been deactivated. This prevents the acknowledge signal from a previously selected bus control slave from being mistaken for the acknowledgement of the next select signal.
The synchronization of the trailing edges of the select and acknowledge signals prevents timing hazards and anomalies that can arise because of the differences in speeds among the masters and slaves that are coupled to a single bus. For example, a fast bus control master can overrun a slower bus control slave, causing the bus control master to remain linked with the slower bus control slave when another bus control slave was actually supposed to have been selected. On the other hand, a fast bus control slave can activate an acknowledge signal to an asynchronous select signal before a slow bus control master detected the deactivation of a previous acknowledge signal, leading to a false bus error indication because the deactivation of the synchronized acknowledge signal must comply with the interlock of the bus controls. Therefore, synchronization of the trailing edges as well as the leading edge has been considered necessary.
The prior art solutions to the problems are set forth in the following references.
U.S. Pat. No. 3,886,524 discloses the connection of several bus masters, each with logic circuits to arbitrate among several requests. The priority is self-determined among the bus masters which are connected by a bus of three lines common to all the logic circuits. The bus master having control of the bus transmits an "access granted" signal. This locks out the other bus masters until the controlling bus master has completed its data transfer.
U.S. Pat. No. 3,997,896 uses two cycles for transferring data between a bus master and a bus slave, one cycle for initiating the data transfer and the second for actually transferring the data. To eliminate the delay between the initiation and the transfer of data between the first pair, a second pair of bus master and bus slave can communicate between the first and second cycle of the first pair.
U.S. Pat. No. 4,084,233 discloses communication channels controlled by a processor to send or receive data from various devices, all of which operate from a common system clock to prevent timing hazards and anomalies.
U.S. Pat. No. 4,106,104 describes a common control unit to control access to a bus by several devices. The transfer process of a low priority device can be interrupted to allow higher priority device to use the bus. The connection of the devices to the common control unit is a special arrangement that allows some devices to be connected to both sides of the control unit.
The system of U.S. Pat. No. 4,148,011 uses a busy signal that is coupled to the devices competing for access to the bus. The control logic is distributed among the competing devices with the common busy line. The common busy line avoids timing hazards by holding off the other bus masters while the bus master controlling the bus is transferring data.
U.S. Pat. No. 4,390,969 discloses an asynchronous data transfer system using a four-cycle signal, also known as Return-to-Zero, scheme wherein the request and acknowledge signals do not overlap. To insure stability and to avoid timing hazards, the edges of the signals generate fixed duration pulses that provide time for the circuit states to stabilize. In contrast, the invention uses a two-cycle, also known as Nonreturn-to-Zero, scheme without the delay caused by a fixed duration pulse.
U.S. Pat. No. 4,660,169 discloses an asynchronous daisy chain arrangement that enables a bus master to seize control of the bus when a Bus Acknowledge (Grant) signal is received without incurring any synchronization delay. The bus master inhibits setting synchronization latches to prevent passing the bus grant signal to the next bus master in the chain by delaying the setting of the latches for a short time period before a Local Bus Request Required signal is issued to insure the stability of the bus grant signal passed when the bus master determines its need for the bus. If the bus master requires control of the bus, it continues to delay the synchronization latch setting long enough to complete its seizing control of the bus and to signal the bus arbiter that it has taken control. The invention in this application eliminates the delays in setting the latches as well as eliminates the timing problem that occurs when a limiting number of bus masters is exceeded.
U.S. Pat. No. 4,779,089 describes a system having asynchronous bus masters but using synchronization signals for controlling the bus to avoid timing hazards as described above when the bus master operation is asynchronous.
U.S. Pat. No. 4,803,481 relates to the use of a call line between a master unit and a slave unit, the master unit communicating when the logic levels of a master line and a slave line are at the same level and the slave unit communicating when the logic levels are different. The direct communication requirements limit the types of bus masters and bus slaves that can be used in a single system and precludes the need to avoid timing hazards.
U.S. Pat. No. 4,817,037 shows a system of overlapping bus cycle operations using a protocol that allows a bus slave to indicate to the designated bus master that a new bus master is to be designated for temporary communication. The communication with a different bus master takes place during the communication with the designated bus master. The operations are controlled by signals that synchronize the signals used for the communication process.
U.S. Pat. No. 4,821,170 shows a plurality of host processors with at least two system buses. DMA devices control the bus arbitration and allocate alternate bus clock cycles in response to request to exchange data between a dedicated microprocessor and a high speed bus. The bus clock cycles actually provide synchronous operation.
U.S. Pat. No. 4,847,750 shows still another approach to data acquisition that uses a dual port frame map memory for storing address of DMA devices in sequence. Data is rapidly transferred from various peripheral devices having nonsequential addresses to sequential locations of the computer and vice versa. This arrangement limits the number and speed variations of devices using the system.
U.S. Pat. No. 4,887,262 relates to asynchronous bus masters using messages comprising an arbitration field and a data field. It depends, however, on synchronizing the operation of the bus masters so that its operation is not wholly asynchronous.
The invention to be described herein is designed to be wholly asynchronous in that the clocks of each device are independent from each other and can run at widely varying rates. The number of bus masters and bus slaves is not limited.
In accordance with the invention, an access controller selects a resource controller to access the resource controlled by the resource controller. In response to a select signal, the resource controller allows access to the resource for utilization of the resource and supplies an acknowledge signal to indicate the resource is being utilized. The acknowledge signal is terminated as soon as the utilization is completed but the access controller retains the signal until it is in a stable state and terminates the select signal. The resource controller retains the select signal until it is in an initial state.
The two controllers operate asynchronously with respect to one another but prevent response to false signals by retaining the signals until they are in stable states.
To prevent system hang up, the access controller terminates the select signal after a predetermined time if no acknowledge signal is received. It also inhibits the select signal if it is possible for more than one resource controller to be selected, e.g., if there is a parity error in the select signal.BRIEF DESCRIPTION OF THE DRAWING
The invention is described in detail by referring to the various figures which illustrate specific embodiments of the invention, and wherein like numerals refer to like elements.
FIG. 1 is a block diagram of a daisy chain resource acquisition system.
FIG. 2 is a block diagram of a typical bus control master and bus control slave in which the invention is useful.
FIG. 3 is a state diagram of a bus control slave state machine for sequencing the latter's functions according to the invention.
FIG. 4 is a logic diagram of the asynchronous lockout circuit for a bus control slave according to the invention.
FIG. 5 is a state diagram of a bus control master state machine for sequencing the latter's functions according to the invention.
FIG. 6 is a logic diagram of the asynchronous XSEL circuit of a bus control master according to the invention.
FIG. 7 is a logic diagram of the asynchronous lockout circuit for a bus control master according to the invention.
FIGS. 8A-8E show the relationship among certain signals that occur in the operation of a system according to the invention.DESCRIPTION OF THE PREFERRED EMBODIMENT
In the following description, the illustrated embodiment is described in terms of gaining and controlling access to a system bus by one of several bus masters. It is not intended that the invention be limited to bus master operations. It is equally applicable to the access to any common system resource. That is, the invention applies to resource masters in general where requests are made for access to the resource and a resource grant signal is returned to indicate that access may be had to the resource.
FIG. 1, a bus master is shown composed of a control unit 101, a bus control master 103, and a bus control slave 105. Two other controllers 107 and 109 for other bus masters are also shown without the associated bus control masters and bus control slaves. A bus request signal is generated by ORing the REQ signals from each of the bus master controllers using serial OR gates 110-112 in the illustrated embodiment. Serial coupling of the OR function facilitates the addition of more bus masters in the system without the need to change the existing circuits.
A bus grant signal is coupled to the ACK input terminal of the first bus master controller in the chain. Thereafter, the PASS output terminal of each bus master controller is coupled to the ACK input terminals of its next bus master controller.
When a device needs access to the bus, its bus control master supplies a request signal, MRQ, to its bus master controller. When the bus master controller 101 has seized the bus, it sends an appropriate control granted signal to the bus control master. This is synchronized to the local clock in the bus master controller and is supplied to the bus master controller which shares the local clock with its associated bus master controller. The synchronized bus grant signal is labelled BG* in the figures of the drawing and is deactivated by the clock signal following the deactivation of the bus grant signal from the remote resource.
The above description relates to a daisy chain arbiter for bus access. The following description of the actual control of the bus is not limited to any particular type of access request arbiter but is equally applicable to any form of system resource arbitration.
The details of the bus control master and slave are explained as an operation in which a DMA device accesses a memory system either to write data to the memory or to read data from the memory. The particular operation in no way limits the scope of the invention inasmuch as the DMA device and the memory can be replaced by other system devices or resources. In FIG. 2, the bus control master 103 couples a DMA device 201 to a system bus 205. A bus control slave 105 couples the system bus 205 to a memory system 207. In a typical system, there will be many bus masters and many system resources. FIG. 2 illustrates only one bus control master and one bus control slave.
Typically, a DMA device supplies an address for the memory and data to be written into the addressed memory location. In case of a read operation, the address is supplied and the data retrieved from the memory is latched by the DMA device.
The bus control master 103, when it has received a CONTROL GRANTED signal, first addresses the appropriate bus control slave, in this case the bus control slave 105 for the memory 207 by coupling the latter's address from the DMA device 201 to the bus 205. The selection of the bus control slave 105 is accomplished by the bus control master 103 placing the unique slave address on the bus 205 and supplying a signal indicating the slave address is active. Each bus control slave coupled to the bus 205 includes a decoder 211. When the selected bus control slave receives its unique device address, its decoder 211, together with the slave address active signal, supplies a transfer select signal, XSEL, to the bus control slave's internal state machine, described in detail below.
The XSEL signal signifies that the address signals on the bus from the DMA device 201 to a memory location in the memory 207 are valid. If a write operation is being performed by the DMA device 201, the write data signals from the DMA on the bus are also valid.
When the bus control slave 105 has synchronized the XSEL signal from the bus control master 103 to the local clock of the bus control slave 105, the latter performs its assigned function, usually a read or write operation in the memory 207. When it has completed the function, it returns a transfer acknowledgement signal, XACK, to the bus control master 103. When the bus control master receives the XACK signal, it latches the data signals from the bus 205 if a read operation is in progress.
In a write operation, the bus control slave 105 couples the address from the bus 205 to the address input terminals of the memory 207, activates the memory write signal, and couples the data signals from the bus 205 to the data terminals of the memory 207. When the data has been transferred to the memory 207 or latched in the bus control slave 105 for later transfer, the bus control slave supplies an XACK signal. The address and data signals are coupled from the DMA device 201 to the bus 205 by the bus control master 103.
In a read operation, the bus control slave 105 retrieves the data from the memory at a location addressed by the address signals from the bus 205 supplied by the DMA device 201 and coupled to the memory 207 by the bus control slave 105. The XACK signal indicates to the bus control master 103 that the data is ready. The latter then latches the data signals from the bus 205 or causes the DMA device 201 to do so.
After the cycle is completed, the bus control master 103 may send another data word, i.e., a set of bits equal to the memory word size, to be written at a successive address, the address being incremented by the device 201 or by the bus control master. Successive cycles without additional arbitration is called bursting Fast, buffered DMA devices usually access the memory for bursts of several cycles to store or to read several data words in successive cycles. Slower devices usually access the memory for a single cycle to read or to store a single word.
The state machine that controls the bus control slave is set out in FIG. 3 in diagrammatic form from which a person of ordinary skill can construct the device. The signals used in the bus control slave state machine are:
ADRPAR--parity of the address signal is correct (ADRPAR' indicates an address parity error);
BG*--bus grant synchronized (see cross-related application for example of a source of this signal);
DATPAR--parity of the data is correct;
RDOP--read operation is being executed;
WROP--write operation is being executed;
XSEL--select signal from the active bus control master which can be the output signal generated by the decoded address and a "slave address active" signal; and
XSEL*--the select signal synchronized with the local bus control slave clock.
The last signal, i.e., XSEL*, is synchronized by a circuit such as shown in FIG. 4. The XSEL signal is received from the decoder and applied to an inverter 403 and an AND gate 405. When the XSEL signal is not present, a flip-flop 401 is reset by the reset output signal from another flip-flop 407. When the XSEL signal is applied to the AND gate 405, the D-input of the flip-flop 407 is primed and the flip-flop is set by the next CLK, local clock, signal. (The CLK signal is used in the bus control slave only and is independent from all other clocks in the system.) Setting the flip-flop 407 produces the XSEL* signal.
In FIG. 3, the first state is the A-state, or idle state. The state machine remains in the A-state so long as XSEL* is inactive or the address parity check is not valid (ADRPAR'). The latter condition prevents the bus control slave state machine from moving out of the idle state when the address has a parity error which means that the particular bus control slave is not actually being selected or that more than one bus control slave may have been selected because of the parity error.
When the XSEL* signal is generated at the first local clock signal after XSEL is received and the address is correct (ADRPAR), i.e., no parity error, the machine transits to the I-state. The I-state is an intermediate state that controls transition to one of three transient states.
If a read operation is being executed, i.e., the RDOP signal is active, then the machine moves from the I-state to the R-state which gates the read data to the bus and immediately goes to the B-state.
If a write operation is being executed, the machine goes to the W-state if the data from the bus, which is to be written to the resource, is valid (DATPAR), i.e., has no parity error. The data on the bus is latched and the machine moves immediately to the B-state.
If a write operation is being executed and the bus data is not valid (DATPAR'), then the machine goes to an E-state which does not latch the data from the bus but generates a data parity error signal. The error signal can be used by the system to initiate diagnostic or recovery procedures as necessary. The error signals are also supplied to the active bus control master. From the E-state the machine goes immediately to the B-state.
In the B-state, the machine generates an XACK signal to the active bus control master. The relation of the signals discussed is shown in FIG. 8. FIG. 8C shows the read data signals on the bus 205. The cross-hatched portion of the signal indicates that the data on the bus is not valid. FIG. 8E shows the XACK signal generated in the B-state to indicate the read data on the bus is valid.
During a write operation, the XACK signal indicates to the bus control master that the write data has been latched from the bus. The data error signal will indicate that the operation was not successful.
When the bus control slave has completed its operation, the XACK signal is deactivated. The bus control slave state machine remains in the B-state while the XSEL* is active. The XSEL* signal will remain active until the first local clock after the XSEL signal is deactivated. This is shown in FIG. 4. When the XSEL signal is deactivated, the output signal from the inverter 403 sets the flip-flop 401 which disables the AND gate 405. When the next CLK signal occurs, the flip-flop 407 is reset, terminating the XSEL* signal. The flip-flop 401 prevents another XSEL from keeping the XSEL* signal active if it occurs before the next local clock signal, CLK.
This circuit insures that the state machine of FIG. 3 returns to the A-state before another XSEL signal can be responded to by the same bus control slave.
The state machine for bus control master is shown in FIG. 5. Its operation begins in the D-state which is entered from the C-state of the arbitration logic of the cross-related application. The bus control master state machine remains in the D-state if the XACK* signal is active. The XACK signal from a bus control slave indicates that the bus control slave is still in an active state from a previous active cycle.
The XACK* signal is the XACK synchronized with the bus control master's local clock, which, like the other local clocks, is independent from any other clock and is used in the bus control master only. The circuit of FIG. 7 shows the generation of the XACK* signal from the XACK signal from the bus control slave.
The XACK signal from the bus control slave indicates the read data is valid on the bus or that the write data has been latched from the bus. At the bus control master, the XACK signal is applied to an inverter 703 and an AND gate 711. The circuit operates in a manner similar to that of FIG. 4 except that the set and reset signals of the flip-flop 709 are gated only during certain states of the bus control master state machine. The flip-flop 709 is set when the state machine is in the D-state when the flip-flop 715 is set. When the XACK signal is received, the AND gate 711 is activated so that the next local clock signal will set the flip-flop 715, generating the XACK* signal.
When the XACK signal is deactivated, the flip-flop 709 will be reset through an AND gate 707 if the bus control master state machine is in the D-, F-, or G-state. This will disable the AND gate 711 so that the next local clock signal will reset the flip-flop 715, cutting off the XACK* signal. As will be seen from the description of the bus control master state machine, below, the holdoff of the XACK* permits the bus control master state machine to return to a stable state and prevents it from responding to a XACK signal from a previous cycle.
In the state machine of FIG. 5, a LOCK signal is turned on if the bus master is to operate in the burst mode, i.e., the bus master will control the bus for more than one cycle to transfer several words of data. The burst mode will also set a signal ADRINC to cause the address of the data to be incremented when the D-state is entered. If the operation is a write function, the WROP signal will activate the PARACT signal. These signals are ancillary to the proper operation of the bus control master, but do not form part of the invention per se.
When the XACK* is deactivated in the burst mode--for a single cycle operation, it would already have been deactivated or not activated at all--the bus control master state machine transits to the E-state, a wait state. The machine remains in the E-state as long as neither the XACK* or TMOUT signals are active. The TMOUT is a signal that is activated a predetermined time period after the XSEL signal is generated by the bus control master if an XACK signal is not received. This prevents lock up if no XACK signal is received, e.g., if the address parity was incorrect or no bus control slave was selected or the selected bus slave is malfunctioning.
Activation of the XACK* signal will cause the machine to transit to the F-state if the TMOUT signal is not activated and there is no error, i.e., the NOERR signal is active.
The F-state is the action state in that the read data is latched from the bus if a read operation is being executed.
FIG. 6 shows the generation of the XSEL signal. If no XACK signal is active (the normal condition), an inverter 601 supplies an active output signal that primes an AND gate 603. The AND gate 603 will be activated to set a flip-flop 609 when the bus control master state machine is in the D-state. With the flip-flop 609 set, the XSEL signal is supplied by an AND gate 611 while the bus control master state machine is in the D-, E-, or H-states via an OR gate 607.
As shown in FIG. 8, the XSEL signal (FIG. 8A) indicates that the address signals on the bus are valid. If a write operation, the write data (FIG. 8D) is also valid. (As noted above, the cross-hatch portions of the signals indicate that the data is not valid.)
The deactivation of the XACK* signal and no LOCK signal causes the bus control master state machine to transit to the A-state, the initial state of the arbitration logic shown in the cross-related patent application.
If the LOCK signal is active in the F-state, the machine moves to the D-state if a read operation is being executed so that the bus control master takes the next cycle without going through the arbitration process. If a write operation is being executed, the machine passes through a transient G-state to the D-state. In the G-state, the write data is prefetched for application to the bus. If the ADRINC signal is active, the write data address is incremented.
The above-described process is repeated if the LOCK signal is active. The LOCK signal is supplied externally to the remote resource to inhibit another arbitration.
From the E-state, a time out signal, TMOUT or an error signal (ERR) when XACK* is active will cause the state machine to transit to an H-state. An error signal, ERROR, is an address parity error signal from the bus control slave or a data parity error during a write operation from the bus control slave. An address parity error may mean that more one bus control slave has responded, i.e., XACK* signal may have been received from more than one bus control slave.
The H-state may also be entered from the D-state if the XACK, TMOUT, and LOCK signals are all active.
The H-state deactivates the LOCK signal so that the next cycle will arbitrated. While the BG* signal remains active, the machine stays in the H-state. When the BG* signal is deactivated, the bus control master state machine transits to the F-state which moves to the A-state since the condition LOCK' is active.
FIG. 6 shows that the XSEL signal remains active during the D-, E-, and H-states. It is, however, cut off in the F-state. This indicates to the bus control slave that the operation has been completed and to deactivate the XACK signal. This releases the bus immediately after the bus control master and slave have completed their operations. It also holds off the setting of the flip-flop 609 until the XACK signal has been deactivated. This prevents the next cycle in the burst mode from bringing up the XSEL signal until the XACK signal from the previous cycle has signalled that the bus control slave operation has been completed.
The description of the preferred embodiment has shown the manner in which a plurality of bus control masters and bus control slaves can operate on an asynchronous basis and permit early release of the bus without synchronizing the trailing edge of the control signals with the local clock. It also shows an arrangement whereby bus control masters and bus control slaves of varying speeds can operate on the same bus.
While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes and modifications in form and details may be made therein without departing from the spirit and scope of the invention according to the following claims.
1. In a data processing system, the combination comprising:
- memory means for storing data;
- a plurality of data resource means for supplying and utilizing data;
- system bus means for transferring data between the memory means and the data resource means;
- a plurality of bus master controller means for controlling access to the system bus means by the data resource means, each bus master controller means further comprising
- clock means, independent of any other clock means employed in the system, for supplying local timing signals for use only in and by the respective means of its associated bus master controller means,
- bus control master means for coupling a data resource means to the system bus means,
- bus request means responsive to the bus control master means for supplying a control request signal indicating access to the system bus means is required, select means for receiving a bus grant signal representing access to the system bus means is granted,
- passing means responsive to the bus request means and to the select means for outputting the bus grant signal if the bus controller means did not supply a control request signal as gated solely by signals from the clock means, and
- bus control slave means responsive to the bus control master means for coupling the system bus means to the memory means and responsive to the bus request means and to the select means for controlling the system bus means in response to a bus grant signal if the bus controller means supplied a control request signal;
- means for coupling the bus request means together to a single bus, which bus will carry bus request signals from any of the bus request means;
- means for coupling the passing means of each bus master controller means to the select means of a successive bus controller means, the select means of a first one of said bus master controller means being coupled to receive a bus grant signal from the utilizing means;
- signal means in the bus control slave means for supplying a completion signal indicating a data transfer is completed; and
- termination means in the bus control master means responsive to the clock means and to the signal means for retaining control of the system bus until the bus master controller means has reached a predetermined state.
2. The system combination according to claim 1 wherein the termination means further comprises:
- setting means responsive to the clock means and to the absence of a completion signal for activating a continuation signal indicating retention of control of the system bus means; and resetting means responsive to the clock means and to the presence of a completion signal for deactivating the continuation signal.
3. The system combination according to claim 2 wherein each bus master controller means further comprises state control means having a plurality of distinct states for supplying signals to control operation of the bus master controller means in accordance with the current state of the state control means.
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|April 11, 1978
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|McLagan et al.
|January 1, 1980
|Lemay et al.
|May 17, 1983
|Conway et al.
|June 28, 1983
|April 21, 1987
|Norgren et al.
|October 18, 1988
|February 7, 1989
|Mueller et al.
|March 28, 1989
|Hoffman et al.
|April 11, 1989
|Bernick et al.
|July 11, 1989
|December 12, 1989
|van Veldhuizen
|December 19, 1989
|March 19, 1991
Type: Grant
Filed: Nov 10, 1992
Date of Patent: Dec 27, 1994
Assignee: International Business Machines Corporation (Armonk, NY)
Inventors: Gerald D. Boldt (Longmont, CO), Stephen D. Hanna (Tucson, AZ), Robert E. Vogelsberg (Boulder, CO)
Primary Examiner: Debra A. Chun
Attorneys: Carl M. Wright, Saul A. Seinberg
Application Number: 7/974,375
International Classification: G06F 13368;


text:
- Dairy Farming
- 22 (Registered)
Course Description
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Address Book A6 Moon Delight Red
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This address book from the Moon Delight collection lets you store all of your contact information in a well-organised manner. The cover is richly decorated with a symmetrical golden design featuring leaves, birds and zebras. You can write down the address, phone number and e-mail address for every contact. Also available in A5 format.
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