Align stroke to inside and outside greyed out with paths - Illustrator CC

Question: Just realised that it seems align stroke to inside and outside only works on circle and rectangles in Illustrator. I have tried to put a stroke on a path or any line but it the option becomes greyed out? I know offset path can be an alternative.
Comment: To be clear- you can change the stroke to inside or outside on any closed path. Try it with an abstract path created with the Pen tool that includes straight segments and curved segments- it will give the different stroke options but only if it is a single closed path. Your first picture must be 2 or more different paths with anchor points coincident. If you joined it into one path you would get the stroke options.
Comment: One can also "cheat" by using a **Stroke profile** which will move the stroke to one side of the path (spine).
Answer: Illustrator design team has made an decission that open paths can not have aligned strokes. Similarly they have decided that a open path gets offset on both sides of the path as if it was stroked.
Since a line is a open path theres no alignment.
Anyway there is no real reason why a software couldn't offset open paths just onto one side. Many, CAD applications have no problem doing this by default. But illustrator is designed with a heavy assumption that closed shapes are the only shapes you should be working with. For example pathfinder boolean tools cant work on lines just outlines (its not until shapebuilder that they even recognize its a possibility, even then a secondary consideration). So there is an assumption of you designing outlines. True or not.
Anyway, it is a valid way of designing a software. Likewise stroke side is a residue of pixel snapping per pixel, not per half pixel.
Answer: After outlines, convert to compound path.
Comment: I am struggling to see how this addresses the question in *any* way.


Watershed Analysis using DEM

Question: I stumbled upon your question regarding the mosaic feature in qgis, the thing is I'm also using Quantum and this is my first encounter with GIS this semester, so if you can please help me with a technical question.
For the watershed analysis I know the steps as a concept, like how I should first get the flow direction, then flow accumulation then the stream network etc.. but technically I don't know how to locate these functions in Quantum, if you have any knowledge about that matter can you please share it with me?
Answer: Have you worked in the GRASS environment in QGIS before?  If you want to perform a watershed analysis this is the place you will need to start.  The second part of this tutorial on creating heatmaps is useful for learning how to work in GRASS:  http://qgis.spatialthoughts.com/2012/07/tutorial-making-heatmaps-using-qgis-and.html?showComment=1349708404807#c2011177687204116089
This is how I taught myself to work in GRASS, but perhaps other members have better suggestions for you.  Once you are familiar with GRASS, you will be able to extract watersheds from a DEM.

Watershed Analysis using DEM


How can I compare the accuracy of imputation models if there is already missing dataset in the file?

Question: Let's say I have a dataset of 50,000 where about 2% were already missing from the beginning. From what I have learned, we need to use indicators to compare the imputation model with the ground truth value to check the accuracy of the imputed value. But, since, I already have some missing values in my raw dataset, how can I calculate the accuracy of different models and select the best?
Answer: 2 possible things:

you doubt the library and want to check the accuracy of that, then create custom fuction and check for some data if that imputation is accurate or not.- in general, its rare that standard libraby implementation will be wrong and will impute what it was not intended to do.
you want to compare the suitablity of imputed values from different methods-  best way is create same Model(with same architecure and configs) on different set of imputed data, whatever gives you better performance is the better one.
Comment: And what shall be the indicator to compare those different models? Since there are already some data missing, we can't use mean squared error to compare imputed value to ground value to select the best model, right?
Comment: we can use overall model accuracy, if you want you can use mean squared error for all different models the model have best performance overall in predicting target variable  had the best imputation
Comment: But, let's say I have the following raw data:
|    X    |    Y    |
|-------|------ |
|    2    |     3   |
|    3    |     3   |
|    4    |     3   |
|    5    |     2   |
|    6    |     ?   |
|    7    |     8   |
|    8    |      5  |
|    9    |     ?   |
|    10  |     3   |
Now, since I have raw data who already has missing data, how can calculate MSE for model A and B to choose one model as best for imputation process?
Comment: the data what you will impute, you will use that to calculae in respective scenario.


Why hypothyroidism causes body ache?

Question: In the condition of hypothyroidism the Thyroid Stimulating Hormone level is high in individuals. What signalling/metabolic pathway mediates this sensation of pain which is mostly experienced in feet and joints.
Answer: This isn't my field, and I'd love to see my answer surpassed by someone with expert knowledge.  But I should say a recent case report (Pantazis, 2016), though it dealt with an unusual situation, discusses some of the current thinking:

hypothyroidism is characterized by decreased synthesis and degeneration of collagen. Hypothyroidism also inhibits epimerase, which results in reduced chondroitin sulfate and elevated hyaluronic acid, hence weakening the matrix. Moreover, it causes accumulation of glycosaminoglycans (GAGs) in the extracellular matrix (ECM), being involved in the pathogenesis of carpal tunnel syndrome during hypothyroidism and predisposing patients to tendon calcification

THs have known effects at the cellular level on the proliferation and differentiation of bone and cartilage. The hypothyroid state appears to induce abnormalities in these tissues, which results in such clinical manifestations as epiphyseal dysgenesis, aseptic necrosis, possibly crystal-induced arthritis, and an arthropathy characterized by highly viscous non-inflammatory joint effusions primarily affecting the knees, wrists, and hands. Neuropathic and myopathic symptoms accompanying hypothyroidism may manifest as joint region abnormalities when in fact there is no underlying arthropathy.

These paragraphs cite three much older sources.  I don't see a tremendous amount of activity on this narrow issue in PubMed - the broader issue that this case illustrates is whether there are better ways of diagnosing and treating hypothyroidism to restore the balance more effectively; see Midgeley, 2019 for example.
Comment: Thank you so much :)

Why hypothyroidism causes body ache?


mysql process stopping install as cannot kill

Question: I am trying to install mariadb but install exits as fail as Mysql is running and it cannot stop.
MySql is not installed but there is a process running which I cannot kill
root@sonic-ubuntu ~ # ps aux | grep mysql
root      8639  0.0  0.0   9496  2244 pts/0    S+   08:55   0:00 grep --color=auto mysql

When i try to kill it respawns with a different PID
I have tried to identify what is starting the process using ptree but it isn't showing up.
Running Ubuntu 15.10
Any help appreciated.
Okay if i try and install mariadb i get the following
Preparing to unpack .../mariadb-server-10.1_10.1.12+maria-1~wily_amd64.deb ...
Failed to stop mysql.service: Unit mysql.service not loaded.
invoke-rc.d: initscript mysql, action "stop" failed.
invoke-rc.d returned 5
There is a MySQL server running, but we failed in our attempts to stop it.
Stop it yourself and try again!
dpkg: error processing archive /var/cache/apt/archives/mariadb-server-10.1_10.1.12+maria-1~wily_amd64.deb (--unpack):
 subprocess new pre-installation script returned error exit status 1
Selecting previously unselected package mariadb-server.
Preparing to unpack .../mariadb-server_10.1.12+maria-1~wily_all.deb ...
Unpacking mariadb-server (10.1.12+maria-1~wily) ...
Errors were encountered while processing:
 /var/cache/apt/archives/mariadb-server-10.1_10.1.12+maria-1~wily_amd64.deb
E: Sub-process /usr/bin/dpkg returned an error code (1)

Which suggests mysql is running
yes but i cant find or stop it!
Answer: The output of ps aux | grep ... will naturally contain the grep process itself:
root 8639 0.0 0.0 9496 2244 pts/0 S+ 08:55 0:00 grep --color=auto mysql

There seems to be no instance of MySQL running on the system in question.
Comment: okay...when i try to install mariadb i get the following


Recently bought new iPhone and notes were not transferred. Trying to find old files via Time Machine

Question: I recently bought the new iPhone 7 and backed it up via iCloud however, apparently all of the notes I had on my old phone were not saved to the cloud. (I already erased my phone so there's no going back that way). Is there a location on my MacBook (via Time Machine) where my Notes files were saved that I can locate via TimeMachine? I already checked the Notes app and it just has the 3 notes that were saved on the cloud. I'm running 10.10.5 Yosemite.
Comment: An obscure trick which I only learned relatively recently is to restore your phone twice.  Not sure how it relates to Notes but the first restore will fail to restore all your apps, for example.
Answer: As you would know, Time Machine backs up what's on your Mac. Because of this, it's not possible for your Time Machine backups to have copies of your iPhone notes unless you:

also backed up your old iPhone via iTunes on your MacBook, and/or
did have all your iPhone notes backed up to iCloud at some point in time

Scenario 1
This is a more difficult scenario to work with since all you want to recover is your Notes data.  It's not impossible, but to make it practical you would still need access to your old iPhone or use specialised data recovery software. If Scenario 2 applies, try that first. Otherwise, if you do still have access to your old iPhone then you could restore your old iPhone from an older iTunes Backup (located within your TM backups) and then access your old notes that way to either resync back to iCloud or to just copy from and paste into another app (e.g. Pages, Word, Evernote, etc) and then copy from their into new notes in iCloud or your iPhone 7.
Scenario 2
Your Notes data is stored in a Core Data database located in your user Library.  More specifically, it is located in the following path:
~/Library/Containers/com.apple.Notes/Data/Library/Notes
Therefore, within your Time Machine backups you would be looking for the above location to recover your notes from.
Notes:

The ~ indicates your User directory, not the root level of your drive.
Depending on your situation you may not see this directory by browsing your TM backups. If you don't know how to make this visible there are questions here on Stack Exchange that deal with this.
Within the Notes folder there will be files named as follows:  NotesVx.storedata-yyy where the x could be a 1 or 2 or 3 etc (depending on your version of Notes) and yyy denotes additional file name characters (e.g. shm, etc).

IMPORTANT - This is a database so you can't restore a single note - it's all or nothing! You could restore the whole database, but if you're syncing with iCloud, there is the chance that even if you restore it, that it will sync and then get deleted again.
Another option
You could also just copy the NotesVx.storedata file and edit the file extension by changing it to .html and then open that in Safari. By doing this you should be able to see all your old notes (assuming they were there to begin with). Then it's just a process of copying and pasting into new notes.


Create Windows shortcut with "Run as administrator" option enabled

Question: In Windows I can set up a shortcut to run application always as administrator:

I need to create such shortcut from the command line. How can I do that?
Answer: A StackOverflow answer shows how to accomplish this in Powershell. There's no easy interface to add the Run as administrator flag, so it involves flipping a bit in the .LNK binary file.
$WshShell = New-Object -comObject WScript.Shell
$Shortcut = $WshShell.CreateShortcut("$Home\Desktop\7-Zip File Manager.lnk")
$Shortcut.TargetPath = "C:\Program Files\7-Zip\7zFM.exe"
$Shortcut.Save()

$bytes = [System.IO.File]::ReadAllBytes("$Home\Desktop\7-Zip File Manager.lnk")
$bytes[0x15] = $bytes[0x15] -bor 0x20 #set byte 21 (0x15) bit 6 (0x20) ON
[System.IO.File]::WriteAllBytes("$Home\Desktop\7-Zip File Manager.lnk", $bytes)

Comment: Does this also work for non shortcut/lnk files?  (e.g.: EXE's)
Comment: @JuliusPIV , no, this only works for the LNK binary file.
Answer: try with shortcutJS.bat  - it can create a shortcut with "run as admin" tick from command line :
call shortcutJS.bat -linkfile "some.lnk" -target "%cd%\some.bat" -adminpermissions yes

this also changes 21st byte of the file.
More information can be found somewhere in this docs.


Failure to take a call for step in Pokemon

Question: If a mistake is made in a Pokemon game, and neither player catches it, does the player who failed to do the correct action lose the game, or is the game a draw, or do you continue to play the game since the mistake was overlook. Example: A coin was suppose to be toss and if tails the Pokemon could not attack. I failed to (overlook) the toss, several turns later I realize my mistake. This mistake may have put me ahead in the game (if the toss had been tails.) I forfeited the game and later try to look up an official rule on this to no avail.
Answer: It depends whether you are playing casually or in an official tournament. For tournaments, it also depends on its type - beginner-friendly Tier 1 tournaments like League Challenges are different to Tier 2 tournaments where players are expected to abide by the rules all the time.

In casual play, both players have to agree on the resolution of the game state, i.e.

ignore the mistake
try to rewind the game state to the point before the mistake
the opposing player draws a Prize card (or more of them)
player who made the mistake loses

In tournaments, everything depends on the official judge (or more of them) - they are the only ones who can rule the resolution of the game state. In addition to possible resolutions above, they can also give a Caution or a Warning to one or both players.
The main document for judges is Pokémon TCG Penalty Guidelines, available from Rules & Resources page of official website.

A coin was suppose to be toss and if tails the Pokemon could not attack. I failed to (overlook) the toss, several turns later I realize my mistake.

Using Penalty Guidelines from October 2019, the actual resolution depends on "rewindability" and overall damage of the game state. Because several turns have passed, the problem would probably fall into 8.1.2. Gameplay Error - Major, but might also be closer to 8.1.3. Gameplay Error - Severe.
Both players are responsible for maintaining the game state. If the game state is irreversibly broken, the opponent might get a penalty for 8.1. Gameplay Error as well.
The actual penalties strongly depend on the particular situation.
Comment: This is (now, anyway) very slightly incorrect - you do not "draw prize card(s) for free", you just don't have to take those prizes anymore - but otherwise a good answer.  It could be improved by linking to the penalty guidelines linked on [this page](https://www.pokemon.com/us/play-pokemon/about/tournaments-rules-and-resources/), though the specific guideline link now is a dated link which raises the possibility it will stale quickly sadly.
Answer: According to the Play! Pokemon Penalty Guidelines it depends on the severity of the mistake made, and the Tier in which you are playing. It can range from a Caution all the way up to a Game Loss.
For you example it would probably be a Game-Play Error - Major for "Using an Ability when a card prevents its use". For this error in a Tier 1 match you would get a Warning, in a Tier 2 your opponent has to take two fewer prize cards. In either case your opponent would get a Caution for failing to maintain game state.


Android USB device mode commands

Question: Hi
I am searching for but cannot find any Android USB device mode commands.  I am not looking for host mode in Android, just a device mode commands.  I do not find any in the developer.android site.  Anyone can help?
Thanks in advance.
Answer: The USB interface is not part of the Android SDK. Custom firmware can manipulate USB, of course, and you can learn more about that at http://source.android.com.

Android USB device mode commands


Learning as I go but needing help understanding the concept

Question: So my first and main question is how do you get bitcoins? Do you use money off a card to purchase them, do you win them, or what?
Answer: You can get bitcoins by mining them. This is currently done by special mining hardware. You can mine alone or as a part of a larger mining pool. Before that you should buy this relatively expensive hardware (for example AntMiner S9).
The usual way to get bitcoins is buying them with regular (so called fiat) currencies (like USD, EUR...) through bitcoin exchanges. More on the process: https://www.investopedia.com/terms/b/bitcoin-exchange.asp. To get more details you should check on particular exchanges mentioned in the article (like for example: https://www.kraken.com/).
Comment: You can earn bitcoin. If you have a product to sell or a service to provide, instead of asking for regular currencies in exchange, ask for bitcoin.


Does simulator time count as time in type?

Question: Can full-motion simulator training time (FSI) be counted towards the required 100 hours for a Part 135 High Minimums Captain?
Comment: A [substantially related question](http://aviation.stackexchange.com/questions/1768/how-should-simulator-time-be-logged-in-a-pilot-logbook)... although it does not have any answers as of yet.
Comment: If simulator/training device time is to be allowed/credited for (U.S.) training/ratings/certification etc., it will be specifically identified in the regulation involved.
Answer: Unfortunately, no.
135.225 - IFR: Takeoff, approach and landing minimums (e) requires:

The MDA or DA/DH and visibility landing minimums prescribed in part 97
  of this chapter or in the operator's operations specifications are
  increased by 100 feet and 1⁄2 mile respectively, but not to exceed the
  ceiling and visibility minimums for that airport when used as an
  alternate airport, for each pilot in command of a turbine-powered
  airplane who has not served at least 100 hours as pilot in command in
  that type of airplane.

So this means that our question becomes:  Can a pilot log PIC time when "flying" a simulator?
The answer to this question comes from 61.51 - Pilot logbooks, where you will notice that none of the bold parts (marked by me) have been met in the situation that you describe.  Generally, PIC time requires you to be PIC of an aircraft, and does not provide for PIC time when in a simulator unless you are providing instruction:

(e) Logging pilot-in-command flight time.
(1) A sport, recreational, private, commercial, or airline transport
  pilot may log pilot in command flight time for flights-
(i) When the pilot is the sole manipulator of the controls of an
  aircraft for which the pilot is rated, or has sport pilot privileges
  for that category and class of aircraft, if the aircraft class rating
  is appropriate;
(ii) When the pilot is the sole occupant in the aircraft;
(iii) When the pilot, except for a holder of a sport or recreational
  pilot certificate, acts as pilot in command of an aircraft for
  which more than one pilot is required under the type certification of
  the aircraft or the regulations under which the flight is conducted;
  or
(iv) When the pilot performs the duties of pilot in command while
  under the supervision of a qualified pilot in command provided—
...
(2) If rated to act as pilot in command of the aircraft, an airline
  transport pilot may log all flight time while acting as pilot in
  command of an operation requiring an airline transport pilot
  certificate.
(3) A certificated flight instructor may log pilot in command
  flight time for all flight time while serving as the authorized
  instructor in an operation if the instructor is rated to act as
  pilot in command of that aircraft.
(4) A student pilot may log pilot-in-command time only when the
  student pilot—
(i) Is the sole occupant of the aircraft or is performing the
  duties of pilot of command of an airship requiring more than one pilot
  flight crewmember;
(ii) Has a solo flight endorsement as required under §61.87 of this
  part; and
(iii) Is undergoing training for a pilot certificate or rating.
Comment: Don't forget the definition of aircraft in §1.1 -**Aircraft means a device that is used or intended to be used for flight in the air.**


2.6 Backports for Wheezy

Question: Why can't I find 2.6 kernel images in the wheezy backports for Debian Wheezy?
Does anybody knows any unofficial mirrors I can just add to apt?
Thanks.
Answer: The Debian Backports repository provides you with newer versions, not older.
The default Wheezy kernel is a 3.2 kernel. Hence any kernel packages in wheeyz-backports will be something newer than that. Currently the most recent kernel in wheezy-backports appear to be a 3.14 kernel.
If you really need 2.6 kernels the easiest is probably to reuse 2.6 kernels from Squeeze, which ought to work just fine with in a Wheezy environment. Given the Squeeze-LTS project they might even continue to be supported for a while longer.
Most likely you can simply add the regular Squeeze repos to your sources lists. Given that they contain older versions of everything you shouldn't have to worry about any apt repo pinning.
Answer: Wheezy repository does not include 2.6 kernel, only a transitional package (see here)
Squeeze has this particular version (reference), so you would need to add the Squeeze repository to your sources and install from there.

2.6 Backports for Wheezy


Length of 64 byte padded Ethernet II(aka DIX) frame after 802.1q payload is added?

Question: When a router receives a padded 64 byte Ethernet II(aka DIX) frame and it needs to send this over an dot1q sub-interface, then router will add a new Ethernet II header, IEEE 802.1q field and recalculate the FCS. The question is, should router put a 64 byte frame onto wire or 68 byte frame? For example router receives an ICMP "echo request" message which has 6+6+2 byte DIX header, 20 byte IPv4 header, 8 byte ICMP header, padding of zeros for 14 bytes and then the 4 byte FCS. Now if the router will forward this frame over 802.1q sub-interface, which means that 4-byte 802.1q field is added, then should the router preserve all the padding and send 68 byte frame to wire or should it cut off 4-bytes of padding and send the 64 byte frame? A reference to RFC would be great.
Answer: Routers work at layer-3. Your ICMP message would be extracted from it's layer-2 container (which is bigger than the l3 payload) and processed as such. The next-hop would be presented 28 bytes to be encoded for whatever layer-2 it might be. Thus, in theory, a 64byte padded frame would be transmit.
In a switch, yes, an 802.1q tag would be inserted into the otherwise as-is frame. (adding 4 bytes.)
Comment: I say "in theory" because a router that builds the frame *and then tags it* would emit a 68byte frame. I've never actually looked at what my various tech does.
Comment: Could you please explain this "The next-hop would be presented 28 bytes to be encoded for whatever layer-2 it might be"?
Comment: ROUTERS don't shuffle ethernet frames around, that's the realm of SWITCHES. A router will act on the 28 byte IP (ICMP) payload.
Comment: I see. So the routers will (1) add a new Ethernet II encapsulation to 28 bytes(20 byte IPv4 header and 8 byte ICMP header), (2) add 4 byte IEEE 802.1q filed, (3) pad the frame so it is 60 bytes in length, (4) calculate the CRC using the entire 60 bytes and (5) adds the calculated 32 bit value to the Ethernet II frame as a FCS field so that in total the frame is 64 bytes in length?
Answer: While DIX can't tell the exact payload length when padding is used, a router is going to decapsulate the IP packet.  When it is forwarded, the packet is encapsulated with a minimum payload requirement of 42 octets.  So 64 octets should be send out at layer 2 on the dot1q interface.
Of course, it's entirely possible that one or two vendors don't vary the padding ... so I would include the same "in theory" caveat as Ricky.


How can I debug SSL traffic between nginx and an Apache backend with a pre-master key?

Question: I am trying to troubleshoot 502 Bad Gateway errors logged by nginx (used as a load balancer) when communicating with our back-end Apache application servers. The nginx proxy_pass module is being used to configure nginx as a reverse proxy to a cluster of Apache servers, and when capturing traffic via tcpdump I am unable to decrypt the HTTPS communication between nginx and Apache because the cyphersuite in Wireshark is TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 and I do not have the ephemeral Diffie-Hellman pre-master key.
(The issue I am trying to debug is "upstream prematurely closed connection while reading response header from upstream" seen in nginx error log when there's no corresponding error in the Apache logs, making me suspect network issues causing the connection to be closed prematurely, or something)
Is there a way to make Nginx nog the Diffie-Hellman pre-master key when communicating with a proxy_pass backend over SSL? If not, is there any way to decrypt / debug this traffic?
Answer: Since you control everything here why not just change it to a plaintext HTTP connection and try to repeat the issue?
Alternatively change to a simpler non-DHE cipher.
Comment: I can't change to HTTP as this violates company security policy. Changing to a non-DHE cipher is what I am going to try next, as per https://stackoverflow.com/questions/14881039/how-to-read-ssl-tls-encrypted-alert-code-under-ephemeral-rsa


References for computation of 2-primary stable 64-stem ${_2\pi_{64}^s}$?

Question: I want to learn about the $2$-primary component of the stable homotopy groups of spheres in dimension $64$. Since the triviality of $61$-st stem has been proved just recently, I thought that either I am unable to find about ${_2\pi_{64}^s}$ or still there is something unknown about this. I did not find anything in Ravenel's Green book about his, and not sure if there is anything in Toda's book? I will be very grateful for any advise on this!?!
Answer: An answer is given in Theorem 3.5 'On the computation of stable stems' by Kochman and Mahowald. In light of the recent work of Isaksen, Xu, Wang and others, I'm not sure how reliable this result is.
Comment: @Drew Heard Do you mean the results themselves could affect computations of Kochman and Mahowald, or do you mean that the methods employed by Isaken, Wang, Xu, and others could result in a different result for the $64$-th stem?
Comment: @user51223 See the bottom of page 4 of https://arxiv.org/pdf/1407.8418.pdf - there are some inconsistencies with the latest calculations and the Kochman/Mahowald calculations. Thus, I'm not sure if the calculation in the 64 stem is correct.
Answer: This is the result from Kochman and Mahowald:

Which you can get from "On the Computation of Stable Stems", Contemporary Mathematics Volume 181, 1995.


Rules and guidelines for drawing good schematics

Question: There are a lot of poorly drawn schematics here. A few times people have actually asked for critiques of their schematics. This question is intended as a single repository on schematic drawing rules and guidelines can point people to. The question is
What are the rules and guidelines for drawing good schematics?

Note: This is about schematics themselves, not about the circuits they represent.
Answer: A schematic is a visual representation of a circuit.  As such, its
purpose is to communicate a circuit to someone else.  A schematic in a
special computer program for that purpose is also a machine-readable
description of the circuit. This use is easy to judge in absolute terms.
Either the proper formal rules for describing the circuit are followed and
the circuit is correctly defined or it isn't. Since there are hard rules
for that and the result can be judged by machine, this isn't the point of
the discussion here.  This discussion is about rules, guidelines, and
suggestions for good schematics for the first purpose, which is to
communicate a circuit to a human.  Good and bad will be
judged here in that context.
Since a schematic is to communicate information, a good schematic does
this quickly, clearly, and with a low chance of misunderstanding.  It is
necessary but far from sufficient for a schematic to be correct.  If a
schematic is likely to mislead a human observer, it is a bad schematic
whether you can eventually show that after due deciphering it was in fact
correct.  The point is clarity. A technically correct but
obfuscated schematic is still a bad schematic.
Some people have their own silly-ass opinions, but here are the rules
(actually, you'll probably notice broad agreement between experienced
people on most of the important points):

Use component designators
This is pretty much automatic with any schematic capture program, but we still often see schematics here without them.  If you draw your schematic on a napkin and then scan it, make sure to add component designators. These make the circuit much easier to talk about.  I have
skipped over questions when schematics didn't have component designators
because I didn't feel like bothering with the second 10 kΩ
resistor from the left by the top pushbutton.  It's a lot easier to
say R1, R5, Q7, etc.
Clean up text placement
Schematic programs generally plunk down part names and values based on a generic part definition.  This means they often end up in
inconvenient places in the schematic when other parts are placed nearby.
Fix it.  That's part of the job of drawing a schematic.  Some schematic capture programs make this easier than others.  In Eagle for example,
unfortunately, there can only be one symbol for a part. Some parts are commonly placed in different orientations, horizontal and vertical in the case of resistors for example.  Diodes can be placed in at least 4
orientations since they have direction too.  The placement of text around a part, like the component designator and value, probably won't work in other orientations than it was originally drawn in.  If you rotate a stock part, move the text around afterward so that it is easily readable, clearly belongs to that part, and doesn't collide with other parts of the drawing.  Vertical text looks stupid and makes the schematic hard to read.
I make separate redundant parts in Eagle that differ only in the symbol orientation and therefore the text placement.  That's more work upfront but makes it easier when drawing a schematic.  However, it doesn't matter how you achieve a neat and clear end result, only that you do.  There is no excuse.  Sometimes we hear whines like " But
CircuitBarf 0.1 doesn't let me do that".  So get something that does.  Besides, CircuitBarf 0.1 probably does let you do it, just that you were too lazy to read the manual to learn how and too sloppy to care. Draw it (neatly!) on paper and scan it if you have to.  Again,
there is no excuse.
For example, here are some parts at different orientations.  Note how
the text is in different places relative to parts to make things neat
and clear.

Don't let this happen to you:

Yes, this is actually a small snippet of what someone dumped on us
here.
Basic layout and flow
In general, it is good to put higher voltages towards the top, lower
voltages towards the bottom and logical flow left to right.  That's
clearly not possible all the time, but at least a generally higher level
effort to do this will greatly illuminate the circuit to those reading
your schematic.
One notable exception to this is feedback signals.  By their very
nature, they feed "back" from downstream to upstream, so they
should be shown sending information opposite of the main flow.
Power connections should go up to positive voltages and down to negative voltages.  Don't do this:

There wasn't room to show the line going down to ground because other stuff was already there.  Move it.  You made the mess, you can unmake
it.  There is always a way.
Following these rules causes common subcircuits to be drawn similarly most of the time.  Once you get more experience looking at schematics,
these will pop out at you and you will appreciate this.  If stuff is drawn every which way, then these common circuits will look visually different every time and it will take others longer to understand your schematic.  What's this mess, for example?

After some deciphering, you realize "Oh, it's a common emitter amplifier.  Why didn't that #%&^$@#$% just draw it like one in the first
place!?":

Draw pins according to function
Show pins of ICs in a position relevant to their function, NOT HOW THEY
HAPPEN TO STICK OUT OF THE CHIP.  Try to put positive power pins at the top,
negative power pins (usually grounds) at the bottom, inputs at left, and outputs at right.  Note that this fits with the general schematic layout as described above. Of course, this isn't always reasonable and possible.
General-purpose parts like microcontrollers and FPGAs have pins that can
be input and output depending on use and can even vary at run time.  At
least you can put the dedicated power and ground pins at top and bottom,
and possibly group together any closely related pins with dedicated
functions, like crystal driver connections.
ICs with pins in physical pin order are difficult to understand. Some people use the excuse that this aids in debugging, but with a little thought you can see that's not true.  When you want to look at something
with a scope, which question is more common "I want to look at the
clock, what pin is that?" or "I want to look at pin 5, what
function is that?". In some rare cases, you might want to go around a
IC and look at all the pins, but the first question is by far more common.
Physical pin order layouts obfuscate the circuit and make debugging more difficult.  Don't do it.
Direct connections, within reason
Spend some time with placement reducing wire crossings and the like.
The recurring theme here is clarity.  Of course, drawing a direct connection line isn't always possible or reasonable. Obviously, it can't
be done with multiple sheets, and a messy rats nest of wires is worse
than a few carefully chosen "air wires".
It is impossible to come up with a universal rule here, but if you
constantly think of the mythical person looking over your shoulder
trying to understand the circuit from the schematic you are drawing,
you'll probably do alright. You should be trying to help people
understand the circuit easily, not make them figure it out despite the
schematic.
Design for regular size paper
The days of electrical engineers having drafting tables and being set up to work with D size drawings are long gone.  Most people only have access to regular page-size printers, like for 8 1/2 x 11-inch paper here in the US.  The exact size is a little different all around the world, but they are all roughly what you can easily hold in front of you or place on your desk. There is a reason this size evolved as a
standard. Handling larger paper is a hassle.  There isn't room on the desk, it ends up overlapping the keyboard, pushes things off your desk when you move it, etc.
The point is to design your schematic so that individual sheets are nicely readable on a single normal page, and on the screen at about the same size.  Currently, the largest common screen size is 1920 x 1080.
Having to scroll a page at that resolution to see necessary detail is
annoying.
If that means using more pages, go ahead.  You can flip pages back and forth with a single button press in Acrobat Reader.  Flipping pages
is preferable to panning a large drawing or dealing with outsized paper.
I also find that one normal page at reasonable detail is a good size to show a subcircuit.  Think of pages in schematics like paragraphs in a
narrative.  Breaking a schematic into individually labeled sections by pages can actually help readability if done right.  For example, you might have a page for the power input section, the immediate microcontroller connections, the analog inputs, the H bridge drive power outputs, the ethernet interface, etc.  It's actually useful to break up the schematic this way even if it had nothing to do with drawing size.
Here is a small section of a schematic I received.  This is from a
screenshot displaying a single page of the schematic maximized in
Acrobat Reader on a 1920 x 1200 screen.

In this case, I was being paid in part to look at this schematic so I
put up with it, although I probably used more time and therefore charged
the customer more money than if the schematic had been easier to work
with.  If this was from someone looking for free help like on this web
the site, I would have thought to myself screw this and gone on to
answer someone else's question.
Label key nets
Schematic capture programs generally let you give nets nicely readable names. All nets probably have names inside the software, just
that they default to some gobbledygook unless you explicitly set them.
If a net is broken up into visually unconnected segments, then you absolutely have to let people know the two seemingly disconnected nets are really the same.  Different packages have different built-in ways to show that.  Use whatever works with the software you have, but in any case, give the net a name and show that name at each separately drawn segment.  Think of that as the lowest common denominator or using "air wires" in a schematic.  If your software supports it and you think it helps with clarity, by all means, use little "jump point" markers or whatever.  Sometimes these even give you the sheet and coordinates of one or more corresponding jump points.  That's all great but label any such net anyway.
The important point is that the little name strings for these nets
are derived automatically from the internal net name by the software.
Never draw them manually as arbitrary text that the software doesn't understand as the net name. If separate sections of the net ever get disconnected or separately renamed by accident, the software will automatically show this since the name shown comes from the actual net name, not something you type in separately.  This is a lot like a
variable in a computer language. You know that multiple uses of the variable symbol refer to the same variable.
Another good reason for net names is short comments.  I sometimes name and then show the names of nets only to give a quick idea what the purpose of that net is.  For example, seeing that a net is called "5V"
or "MISO" could help a lot in understanding the circuit.  Many short nets don't need a name or clarification, and adding names would hurt more due to clutter than they would illuminate.  Again, the whole point is clarity.  Show a meaningful net name when it helps in understanding the circuit, and don't when it would be more distracting than useful.
Keep names reasonably short
Just because your software lets you enter 32 or 64 character net names, doesn't mean you should.  Again, the point is about clarity.  No names
is no information, but lots of long names are clutter, which then
decreases clarity.  Somewhere in between is a good tradeoff.  Don't get
silly and write "8 MHz clock to my PIC", when simply "CLOCK", "CLK", or
"8MHZ" would convey the same information.
See this ANSI/IEEE standard for recommended pin name abbreviations.
Upper case symbol names
Use all caps for net names and pin names.  Pin names are almost always shown upper case in datasheets and schematics.  Various schematic programs, Eagle included, don't even allow for lower case names.  One advantage of this, which is also helped when the names aren't too long,
is that they stick out in the regular text.  If you do write real comments in the schematic, always write them in mixed case but make sure to upper case symbol names to make it clear they are symbol names and not part of your narrative.  For example, "The input signal TEST1 goes high to
turn on Q1, which resets the processor by driving MCLR low.".  In this case, it is obvious that TEST1, Q1, and MCLR refer to names in the schematic and aren't part of the words you are using in the description.
Show decoupling caps by the part
Decoupling caps must be physically close to the part they are decoupling due to their purpose and basic physics.  Show them that way.
Sometimes I've seen schematics with a bunch of decoupling caps off in a
corner.  Of course, these can be placed anywhere in the layout, but by placing them by their IC you at least show the intent of each cap.  This makes it much easier to see that proper decoupling was at
least thought about, more likely a mistake is caught in a design review,
and more likely the cap actually ends up where intended when the layout is
done.
Dots connect, crosses don't
Draw a dot at every junction.  That's the convention.  Don't be lazy.
Any competent software will enforce this any way, but surprisingly we still see schematics without junction dots here occasionally.  It's a rule. We don't care whether you think it's silly or not.  That's how it's done.
Sort of related, try to keep junctions to Ts, not 4-way crosses.  This isn't as hard a rule, but stuff happens.  With two lines crossing, one vertical the other horizontal, the only way to know whether they are connected is whether the little junction dot is present.  In past days when schematics were routinely photocopied or otherwise optically reproduced, junction dots could disappear after a few generations, or could sometimes even appear at crosses when they weren't there originally.  This is less important now that schematics are generally in a computer, but it's not a bad idea to be extra careful.  The way to do
that is to never have a 4-way junction.
If two lines cross, then they are never connected, even if after some reproduction or compression artifacts it looks like there maybe is a dot there.  Ideally connections or crossovers would be unambiguous without junction dots, but in reality, you want as little chance of misunderstanding as possible.  Make all junctions Ts with dots, and all
crossing lines are therefore different nets without dots.

Look back and you can see the point of all these rules is to make it as
easy as possible for someone else to understand the circuit from the
schematic, and to maximize the chance that understanding is correct.

Good schematics show you the circuit.  Bad schematics make you
decipher them.

There is another human point to this too.  A sloppy schematic
shows lack of attention to detail and is irritating and insulting to anyone
you ask to look at it.  Think about it.  It says to others "Your
aggravation with this schematic isn't worth my time to clean it up"
which is basically saying "I'm more important than you are".  That's
not a smart thing to say in many cases, like when you are asking for free
help here, showing your schematic to a customer, teacher, etc.
Neatness and presentation count.  A lot.  You are judged
by your presentation quality every time you present something, whether you
think that's how it should be or not.  In most cases, people won't bother
to tell you either. They'll just go on to answer a
different question, not look for some good points that might make the
grade one notch higher, or hire someone else, etc.  When you give someone a sloppy schematic (or
any other sloppy work from you), the first thing they're going to think is
"What a jerk".  Everything else they think of you and your work
will be colored by that initial impression.  Don't be that loser.
Comment: My ten cents: though I love to use colour to disambiguate on-screen, I prefer the way monochrome schematics look *in print* (or PDF). Conventions and æsthetics evolved for monochrome work, and not everyone has access to a colour printer/photocopier so colour information may be lost. I also like to not **depend** on colour (one of my co-workers is colour-blind, which occasionally leads to semi-amusing incidents involving colour-coded LED status lights. So I've become very sensitive to this).
Comment: Maybe it's because of my programming background, but I find that I often prefer "air wires" for many things.  If I see two pins on the CPU labeled "DATA_TO_FTDI" and "DATA_FROM_FTDI", I can tell at a glance that those pins go to (or at least should) the data RX/TX pins on the FTDI chip. A glance at the FTDI chip can confirm that. I can then check those names against the definitions of the pins on the device (since some devices which behave as communication bridges use TX as an output (they transmit data on that pin), while others use it as an input (accepting data to be transmitted elsewhere).
Comment: @supercat - The issue with air-wires is that even if where they go seems apparent, you can never be sure (without an exhaustive search), that you have found *everywhere* they go. For your "DATA_TO_FTDI" example, what if there is a serial activity LED on that bus? Or another device sharing the serial interface? I can never be sure without manually looking over **EVERY** net-label on the entire schematic.
Comment: One additional rule you should consider adding: "Use the same signal names in the schematic as in the source code of your firmware". This makes the whole project easier to document and maintain, and also makes communication easier between the hw designer(s) and the sw designer(s) in case they are different people.
Comment: While air-wires may work ok on simple projects, as soon as you have more then a few ICs, or your schematic grows to more then one page, it completely falls apart. Also, it's absolute poison in any environment where you have multiple people working with the schematics. The analogy between air-wires and GOTO is very apt. They both let you make short-cuts, and both make the resultant system FAR harder to maintain.
Comment: "Why didn't that #%&^$@#$% just draw it like one in the first place!?"  Ugh, yes.  Every single time I get a schematic from our Chinese factories it is like this.  You don't win a prize for cramming the entire schematic onto on page!
Comment: The TIA schematics found at http://www.atariage.com/2600/archives/schematics_tia/index.html make heavy use of air wires, but I can't imagine that drawing in all the "air wired" connections would make them any clearer.  Even without automated systems to find net connections, I can't imagine that drawing in all the connections to HΦ1/HΦ2, or D0-D7, or the write-address decodes from the bottom of page 2, etc. would make the schematics any clearer.  Actually, I'm rather impressed with those schematics; indeed, they're better than a lot of newer ones.
Comment: As in programming, readability counts. From the Zen of Python: "Beautiful is better than ugly."
Comment: @supercat - You are correct in that drawing in all the air-wires on that schematic would be confusing. That is because that schematic should be using a **bus**. It *would* be much more readable with a bus instead of half a dozen air-wires.
Comment: This is a really long answer with lots of independent points.  It would be best if each point were its own answer so we could comment and vote on each individually.
Comment: I know this is already quite old and still good, but some people are more the visual kind, and maybe someone of those who know the dos and donts could add some more really good do and donts examples. For the existing ones, it is almost enough to read the heading, look at the image and know what you mean.
Comment: I'm curious how far you would go to group together like pins on a microcontroller. For instance: http://imgur.com/82K8VwQ This nicely puts the power pins at the top, the ground pins at the bottom, and groups together the dedicated crystal pins. Grouping together the IO ports like this is nice for a general-use part, but for this particular application, it could be a little tidier if the programming and SPI pins were each grouped together. But is that worth it? Especially when things like the CS pins can change from revision to revision?
Comment: I've got into a new habit (it keeps me honest and perhaps helps the end-user realize a safe assumption) of adding small text showing logic level threshold values (Vin H/L and Vout H/L) parked next to the relevant IC's, FETs, etc.  For example, in mixed logic families, a 5V ACT buffer feeding a 3.3V LVC buffer showing the V levels and that due diligent was exercised.
Comment: @FakeName: Which signals would you combine into what buses?  D0-D7 could perhaps be a bus, though I'm not sure that would clarify much since it's mostly used piecemeal.  There are 45 write addresses decoded on page 2, each of which is used on one other page (the reference near the write-decode circuitry notes which one); should those be buses?  Incidentally, how do you like the use of boxes for repeated circuit elements?  I think it aids comprehension, but I've not seen things drawn like that on any computer-assisted schematics (I've seen simulation tools with user-defined parts, but...
Comment: ...never drawn as they are on the TIA schematics).  I think they make things a lot clearer than they would be if everything was simply "copied out".
Comment: +1 I realy like it. But one question: In one of your answers you complained about a schematic, that was colored. Would you say, that it is good practice to always make the schematic monochrome? Link to the mentioned answer: http://electronics.stackexchange.com/a/26487/4950
Comment: Well done. +1 I find it interesting that my school lacks a course on proper circuit drafting. It should be a required course for freshman. I guess they just assume people will catch on.
Comment: In some cases of high complexity, Schematics should list in a small table, last Ref Des used,for each type. and unused Ref Des, (if deleted.) e.g. Highest REFDES: but for mult-page complex instruments, REFDES should be zoned for each functional of physical block zones.  i.e. U1~99  even if there are only a few,,, then U100~.. with dotted lines for each zone and Function Label.  so Physical Zones and Logical RefDes make sense. e.g. PLL U400~U412, C400~C428, R400~R433,, etc PLL is zone PCA400 with ref des for that card in same block.
Comment: +1 for *CircuitBarf*. Also, @Olin, this is a really great reference and answer.
Comment: There is one point I don't think was mentioned in the text. An alternative to depicting lines that cross but do not join is to show it as a small bridge as in [this image, top right](https://www.dummies.com/wp-content/uploads/307565.image0.jpg) taken from "Electronics for Dummies". This may be a bit old school, but effective and may still available in some CAD packages. One other thing I was taught back in the day was to keep lines horizontal and vertical as far as possible, use diagonals sparingly.
Answer: 1. Show Your Work
A Schematic Diagram is intended to be the documentation of a circuit. As such, I highly recommend including any simple equations that may be used. This includes LED current calculations, filter corner frequencies, etc. Show your work, so that the next guy who has to read the schematic can check it easily.
2. Indicate UART Direction
Since UART lines are not always clear which way they are flowing, add a little arrow next to each line to show the direction.
3. Be Consistent
Don't use VDD in one place and 3V3 in another. Standardize.
4. Annotate Liberally
This is like comments in source code. If you copied a circuit from a datasheet, put the reference on the schematic so that someone else (or you) can check it later.
Answer: Here's my two cents
1. Break it down
Break down your design into modules. Put a block diagram of the system on the first page of the schematic
2. Answer who, what, where, when, why
Who - For each module page, label "who" the module connects to. Lay it out left to right so it reads like English.
What - In the title, indicate what the module is. For instances where there are multiple I/O blocks (i.e. UART and USB), label it as such on the page.
Where - Use free text in the CAD program to indicate component placement. For example - a decoupling cap should be placed as close to the IC as possible. This will act as a quicker reference when laying out the board than referring to some other documentation.
When - Are there any timing considerations such as power supply sequencing or power fail circuitry? Put these requirements not only in a design doc but in free text on the pertinent module page.
Why and How - This belongs in an accompanying design document to verify such things as
a. Scope - what does the circuit do, what does it not do as agreed upon by the stakeholders for the project.
b. Theory of operation
c. Rationale of why the approach was taken as opposed to others. This is crucial as it serves as a history for the circuit down the road when you (or someone else) inherits/ports the design to be mindful of the same decisions as the original designer.
d. Layout considerations
e. References to other documentation.
f. Power dissipation calculations - prove not only that it works, but that calculated power dissipation for all components is some degree less than the rating for the component AND at all operational temperatures.
3. Style
This is up to you and the rest of the team, but in general I prefer the following
a. Title page/block diagram
b. One "block" per page, partitioning large pin-count components (i.e. a microcontroller) into meaningful discrete symbols. This takes some time to do, but is well worth the readability.
The modularization also allows you to "tear a page out" and re-use it in other designs
c. For each component indicate the reference designator, whether or not is is a no-pop, the value/tolerance of the component, the power rating where applicable, and the package size and some way of determining the manufacturer part number. The last point will help you to make common some of the components to reduce setup manufacturing costs and to make a judgement call if some of the design parameters can be relaxed to reduce the number of different components used on the board. For vertically aligned components, place this text on the left. For horizontally aligned components, place this text above the component.
d. Lay out the circuit from left to right indicating where the module interfaces are with text
e. For power rails clarity, DO NOT USE VDD or VCC as they are ambiguous. Make a new symbol for explicitly declaring what the voltage is. Same thing for ground (i.e. GND for ground and AGND for analog ground).
Answer: R100, R101, R102 Instead of R1, R2, R3
I would like to share my experience in assigning names for components.
Identify the blocks of circuits according to the functions. Even if it is a complex circuit, you can identify them such as main power stage, pre-amplifier, amplifier, A/D conversion section, indicator/transducer blocks, synchronizing section, timer or any other logical operation sections.
My suggestion is name the components using larger numbers like R100, R101, R102 instead of R1, R2, R3... etc.
You can assign 100, 200, 300 ... etc for each block you identified. For example, you can assign 100 to 199 numbers for power section. Then all components in the power section in 1xx form such as Q100, R101, R103, C100, D100, D106.
Advantage

Its easy to identify the sections of a circuit by function wise in a
complex schematic diagram.
Easy to troubleshoot.
Its easy to name the parts when you have to add new components to a
section later. Because you have about 100 name options to select.
Easy to drawing PCB layouts in any cad software manually. Because at
the very beginning of the PCB drawing each type of components are
gathered at one place.

You can easily separate them into different
   places by its number without looking many times at the schematic.
Answer: A couple of points in addition to the ones posted above. The first answer is fairly heroic but there's one thing I don't agree with.
Pin order in schematic symbol.
Why to reorder pins
It makes aesthetically more pleasing schematic that may be easier to interpret depending on how the pins are laid out.
Why not to reorder pins
It's asking for trouble, period. In the datasheet the pins are given as they are in the physical chip so you create a significant source of error if you start rearranging them. Not only it makes prototyping more difficult, you're also inviting errors in the physical pinout. In a design review pinouts are compared and if they're mishmash, it's easy to get mixed up.
Another comment on "air wires"
Just don't do it. Instead use ports which require you to explicitly make a connection between two nets in same or separate schematic sheets. If you allow nets to connect without ports/off-pages, you open a huge can of worms as apparently unrelated nets may be shorted in layout.
Don't pack too much stuff on a page
People may start complaining if you schematic is thirty pages but the alternative is having rats nest of confusing wiring between parts. Break up the schematic into logical blocks of circuits and stick them to separate pages as necessary.
Leave enough space between pins
Many premade schematic symbols pack the device pins as tightly as possible. While this minimizes the area of a symbol, it also makes the circuit more difficult to read as you have connections converging from "outside" into the tightly packed pins. You should leave enough space so you can add series resistors staggered.
Reference designators
You should obviously have reference designators in schematic and layout. For anything more complex these need to be ordered. There are two approaches to it.

You can ask the schematic capture program to label these so each page has it's own prefix. This way it's easy to find any given part in the BOM from the schematic. And also ECO is easier to follow as you know which page the changes are for. The downside of this is that you end up with long reference designators and finding the part in the layout can be difficult.
You can ask the layout program to label these. This way you will have ordered references on the PCB which makes it much easier to locate resistor R347. Preferably on a larger PCB this should be cordoned into quadrants (sextants, octants..). The downside is that it's not obvious where the part is in the schematic. You just can't win here, either schematic is easier to read or the layout is.
Comment: I just disagree about pin order.  Schematics shouldn't necessarily have anything to do with the physical layout of the chip.  For example, op amps should look like op amps in a schematic.  A quad op amp should look NOTHING like the chip.  Also, when dealing with complicated high pin counts, the gates should be split up into functional units.
Comment: Good points, but I agree with Scott that avoiding reordering pins is nonsense. With small chips, sure, but schematics are 100% less confusing if instead of having wires criss crossing everywhere, you reorder the pins on a chip and just make sure they are labeled properly. If out of order pins on a schem is enough to confuse someone, they probably shouldn't be messing around with the board to begin with. His op amp point is also very valid.
Comment: Opamps are a special case as I'm sure you'll agree, similar to transistors etc. If you end up with a respin because your rearranging of schematic pins led into an invalid footprint, you didn't exactly do anyone favours.
Comment: [Answer in a newer thread.](https://electronics.stackexchange.com/a/421655/7036)  To your point, @ScottSeidman .
Comment: Footprints should be compared to the data-sheet. Symbols as well. That is the only reference that counts. It makes no sense to use a self-drawn symbol as reference for the footprint. Sure there should be a consistency check between the two, but any decent software will do that and show you unconnected pins on either side.
Comment: @cx05 Yes, which is why it makes sense to follow the datasheet representation/order with the pinout to minimize the chance of error. Obviously for a 388-pin BGA you have to break the symbols apart but still creating the symbol with the same pinout as the chip has makes it more likely you've not swapped pins. Yes, software can help if you actually can find a CAD symbol for your part. This tends to not happen with that BGA package so you're into an evening of checking and triple checking a long list of pins against your symbol.
Comment: Depending on your schematic capture tool you may be able to view the component pinout in schematic format where you can order it by pin number / name which allows you to break parts apart by ports etc while having an easy way to verify the pinout. For something simple like 16-pin SMPS controller when I keep the physical chip pin order I can immediately see from the schematic at a glance which pin I should be probing on the PCB.
Comment: Well, I prefer e.g. to have the port pins of a µC or FPGA in logical order (PA1,PA2...). Many manufacturers assign pin functions according to this ordering. This is what concerns me on a day-to-day basis. With your BGA example it would actually be impossible to mimic the pinout in the schematic. Also, pin assignment is only verified once. Many software packages will give a pin report that can be ordered in any way the user sees fit or exported and sorted in Excel. Once a component is verified, I should never need to verify the pinout again. But I guess it all comes down to use-case and taste.
Comment: @cx05 with bga you're not going to probe anything anyways so most of the advantage is lost. For QFP et al I like to maintain the actual physical pinout, for BGAs usually whatever they use in the datasheet.
Comment: For me it depends, there are some parts that have conventions for how they are drawn, Opamps obviously, but also D type FF (D, Clk on the left, S/R on top/bottom Q & Q* on the right), and indeed most jellybean logic where in any case you are usually drawing a single gate and doing the pin swapping once you start the layout.  Same thing with linear regulators, input on the left, ground (or reference) on the bottom and output on the right, even when the part is one with a weird pinning (7905). Obviously there are parts that do not have defined conventions and for these 1:1 is not unreasonable.
Comment: @DanMills I don't know how many people actually do electronics for living here but getting two pins swapped is an unfortunate fact of life and anything that makes it harder to pick up in the review process makes things more painful. It's hard enough not to get cross-eyed on even something relatively minor like QFP-48, never mind large BGAs. You got a thousand parts done perfectly and the layout is rubbished plus you chalk in extra month to do a respin because you got two pins swapped. It's not like software. It's not really helpful that things like MSP430 microcontrollers mix'n'match pinouts.
Comment: My usual respin trigger is either mechanical, getting the footprint wrong on something funky (Some connectors have the worlds worst datasheets to dimension off), or a straightforward design thinko. I don't think I have ever had a respin due to swaps between designator and label in several hundred boards, that is what a shell script and the manufacturers BSDL file is for. I tell our software weanies that they will understand hardware designers when they understand that pressing compile costs ~£1,000 and takes 6 weeks to run....
Comment: @DanMills A thousand? Pretty cheap stuff then.. You can avoid a lot of problems with footprints if you use STEP models. I got fired actually from one job because I was "wasting time" adding step models to component symbols but those have brought out quite a few problems on mis-interpreting dimensions etc. You don't always have BDSL (or most of the time). Sometimes you get pre-made eCAD symbols which tend to be crap. Often you get nothing except datasheet with 48 pins for that PHY. I have had pins swapped and the guys looking in review specifically looking for that for that part and not get it.
Comment: Some eCAD programs let you at least copy the pinout from a datasheet assuming the manufacturer made the datasheet in a way that allows you to cut and paste them. Some do not, unless Mentor has changed PADS in recent years I had quality time with a ruler and a pencil..
Comment: Physical pinout is just one side of the problem.. You may have bunch of functions available for each pin so a second layer of problems arises of having all the signals going to correct ports which have matching functions. With FPGAs you may be able to respec but with microcontrollers you're hosed. MSP430 is one obnoxious example with at least three different functions per pin possible. My personal favourite are LSI chips that have regular G-S-G-S style pinout except in the middle they go G-S-S-G-G-S to check if you're paying attention.
Comment: In creating a new symbol from a datasheet, I try to import the pin list from the original doc into a spreadsheet. For OrCAD, this can be easily massaged into a form where it can be used to create a new symbol. This is MUCH less error-prone than typing in the pin list from a diagram. All bets are off though if the manufacturer locks their PDF so you can't copy-paste it. Some manufacturers will even provide you a pin list in Excel (e.g., Broadcom for their set-top-box chips) which saves a lot of time.
Comment: @hacktastical Yes, this is a must for large packages. I created a 176-pin BGA microcontroller part recently that would have been very difficult to do manually. It takes a bit of trial and error to find the correct dialog where you can paste pins, Altium has part pin list in several places and not all of them are editable. WRT reordering pins, it's a matter of opinion and depends. On a BGA it's out of the question since ports tend to be ordered in staggered fashion 1-4 rows deep into the package. For >100 pin packages you won't be trying to locate pins visually from schematic anyways.
Comment: Pin counts of over 1000, 1500, 2000 are not uncommon for big microprocessors or SoCs these days, the lion's share of the pins being memory and power.
Comment: @hacktastical Depends what you work on, obviously. I mostly work on embedded devices which usually use either small-ish microcontroller (e.g. that 176-BGA Synergy µCU) or some kind of FPGA. I've worked with 488-pin packages, that's big enough for me :-p Taking the time to painstakingly copy pinouts from datasheet and hashing them in Excel definitely does reduce "oops" moments, especially if you create a processor pinout with pin functions at the same time.
Answer: A few more:

(1) Draw on normal grid.

I really hate having to deal with other people's work that's drawn on half-grid. It's a huge waste of time and doesn't add any value to the drawing.

(2) Use 'physical' style for smaller devices.

Drawing ICs and small components with the pins in order helps with conveying your intent to layout, and makes debugging much easier. This goes double for transistors and diodes in sot-23: I draw them showing the pin order, and as a result haven't had to rework a mis-laid-out one in years.

(3) Realize the limits of (2) above.

It's not possible to draw a big BGA physically, or even as one symbol. But you can at least separate by function and show how pins relate to each other spatially. For example, an FPGA can be drawn and divided to show blocks that represent logic tiles, and the tiles themselves placed / ordered on the schematic to show how they route out.
Historically, multipart symbols for elements like op-amps or gates made sense. But these are becoming more rare in designs.

(4) Intra-page named aliases are ok, but don't push it.

Named aliases are the same as off-pages really: it means you still have to scan the page to look for its other instances. With a PDF schematic and Ctrl-F this isn't as big a chore as it used to be (and shame on you manufacturers who make non-searchable PDFs. That's just lame.) That said, off-pages are more rigorously checked by DRC than aliases.

(5) Block diagrams and mechanical plans are worth the effort

The effort you spend conveying your thinking here will save lots of time over the life of your design - from layout to repair. Yes, your mechanical designer will make the 'official' board outline, but at the very least you can convey where you expect stuff to be placed - and why - by doing these two kinds of diagrams.

(6) When you export your schematic to PDF, make it searchable.

Is it really too much to ask?

(7) Have just enough component information.

Besides the reference designator, some designers are tempted to have all the part attributes on the schematic. But do you really need them? No, you don't. Tolerance, sometimes. Voltage, sometimes, when you have a section that's at a higher voltage. Footprint - maybe. Manufacturer part number? Rarely - you'd want to multiple source usually. Corporate AVL/MRP number? Nope, never.
All this other stuff is what a BOM is for.

(7a) Think ahead to BOM generation.

That said, developing some kind of part number system even in your early days allows you to create detailed BOMs even if you don't have an MRP system. Each part type should have a unique ID that is set as a hidden attribute in your schematic that corresponds to an entry in your master parts list (AVL list.) You use that ID later to merge in the expanded info from your AVL list to create the detailed BOM.
Even later, you can import this stuff into a real MRP or PLM system such as Oracle Agile.

(8) Power is a signal, too!

It used to be that you'd draw a schematic with 'hidden' power / ground pins which would be automatically aliased to VCC or GND. It's still an option when you create a symbol in Orcad for example. Don't hide those power connections! Show 'em! Especially considering today's designs with multiple power domains, high power density, routing, bypassing, loop area, and so forth.
Power is so important, that if you're not spending at least 1/3 of your time on power design you should consider another line of work.

(9) Comments are your friend.

Highlighting key elements with text can save a lot of time in debugging. I will typically comment things that relate to software (e.g., addresses, bit locations) and power design (current typical/max, voltage).

(10) Size matters.

Use 11x8.5 (A size) for really simple stuff, 17x11 (B size) for most other things. Go larger only if you really need to.
17x11 (or its nearest metric equivalent) is a reasonable size for viewing on an HD screen or for printing even at 11x8.5. It's a good go-to size to work with.
On the other hand I find that I can't get enough stuff on 11x8.5. And on the other, other hand is the other extreme when I've used 23.5 x 15.2 (scaled-up B, not C) for a really complex drawing that groups together (e.g., DRAM banks): this needs to be printed at 17x11 to be reasonably easy to read in hard copy.
As it is I rarely print anything anymore, so worrying about how hard copy comes out is more trouble than it's worth most of the time.

(11) Left-right signal flow, top-to-bottom power flow. Mostly.

This is the general standard to make understanding the relationships of elements easier. But sometimes giving more more weight to architecture flow than this old rule yields a clearer schematic.

(12) Organize off-pages / ports in vertical groups.

It's not necessary or useful to drag ports to the edges of the schematic. But at least line them up in organized columns so that they're easy to scan visually.
Answer: The biggest dispute I see in the discussion is about pin order, but this is only a question about the bigger topics: Functional vs physical! If I make a good schematic to prepare my layout work, then it is far better to make the schematic looking as close as possible to the layout, e.g. draw the pin order not according to what someone else does in the datasheet, but as it really is. Also consider to leave a bit more space around big elements, like power devices, e.g. also draw a heatsink "symbol". If ground should be anyway a large plane, then also better go for connections by name, which also helps to avoid having many crossings.
On the other hand if nobody can avoid a crossing of sensitive lines, then draw the schematic so that is becomes a guidance for good layout, e.g. the high-impedance side of a resistor divider should have usually a short connection, whereas the driving wires can be often longer without problems.
For digital IC's I tend to use automatic routers and sticking to functional order.
Another controverse topic could be how to draw a differential amplifier, and e.g. a multistage amplifier, like should we draw each stage in the usual way and then wire to next stage (which often ends up in many crossings), or should we really draw the diff pairs in a symmetrical way (often done in old Tectronics osci schematics)? Here it depends also on the purpose, and how critical keeping symmetry really is. In RF circuits, having often not so many elements, I prefer again drawings very close to layout.
Answer: The schematic is a symbolic description of the function of an electronic circuit, while a layout diagram is a physical diagram clearly describing the location of components and nodes of the circuit. Schematics serve analysis, Layout displays function and assembly. A symbolic electrical diagram and a mechanical drawing, if you will. If you can clearly see the goals for those purposes, and where the overlap is, guidelines are much easier.
If I can't quickly and easily abstract the critical circuit information from the schematic, the design will be more buggy, less reliable, and more difficult to troubleshoot. If the layout doesn't show critical mechanical parameters, particularly where those impact circuit function, that drawing will be much less useful.
Where possible:

Clearly decompose the function of the assembly into blocks and interfaces.
Remember that power, power distribution, and decoupling are functions.
Place components into blocks that are organized for analysis and completion.
Signal flow left to right, power supply top to bottom, on each sheet.
Interfaces on board are air connections at the edge of each sheet. Lord on the top/left, peon on the lower/right.
Enumerate the sink connections on the source of each air connector.
Notes, including default tolerance should appear on every page. Notes should clearly identify specific reference designators on schematic.
Minimize crossing signal lines.
Group related signals.
Maintain order among enumerated lines.
Overlap
Blocks on the schematic should be located close on the assembly.
Decoupling caps on the schematic should be close to the component they protect in the layout.
Interface signals should be routed together.
Connector pins should be numbered per the datasheet, and laid out to match the physical position of the physical connector, viewed from the top of the board.


How often does target hash change and how to find it?

Question: So basically I was researching target hash and trying to figure out how I can find it. I know there are posts out there that have said that Bitcoins target hash is a 256 bit number with 32 bits of leading zeros. But, where can I find this information. Basically is there an equation I can use to find how many leading zeros are currently in the target hash or a direct source where I can find this? Also, how often and by how much does this target change?
Answer: Bitcoin's network has several specialized nodes called "miners" who use specialized equipment to solve cryptographically hard puzzles. If they are successful, then they will get the opportunity to add blocks to the BTC blockchain successfully.
This is how it works:

The miner picks up transactions waiting in the mempool and hashes
them.
They add a random hexadecimal value to the front of the hash and hashes the entire value.
This hash needs to be less than a particular value, which is called "target"

Difficulty is a measure of how difficult it is to find a hash below a given target.
The Bitcoin network has a global block difficulty. Valid blocks must have a hash below a target. This Difficulty changes every 2016 blocks (Approximately every two weeks). The level of Bitcoin mining difficulty increases or decreases according to the ease of mining within the protocol. Remember, Bitcoin needs to have a consistent block time of 10 minutes.
The problem is that targets are hard for people to comprehend. The difficulty is inversely proportional to the target and easier to understand.
The specific formula is: difficulty = [0xFFFF x 256^(0x1D - 3)] / target, to find the target you just rearrange the formula.
The difficulty of Bitcoin at the genesis block was 1. The difficulty can be thought of as how much more difficult mining is now than it was at the start. The current difficulty level is: 28.6 x 10^12.
You can check the current difficulty rate at: Clark Moody's Dashboard
Comment: I appreciate the deep dive but I just wanted that formula you gave me there. Although, I am a bit confused if you could clear up what the values in the brackets are specifically that would be awesome.
Comment: Fixed a typo in the formula, the correct one is with 256 not 255, `difficulty = [65535 x (256^26)] / target`


Five cubic dice were rolled

Question: Five cubic dice were rolled, and the product of the numbers obtained was 432. What is the largest possible sum of five such numbers?
Answer: If we assume these are regular dice being rolled one at a time, the answer would be

 6+6+6+2+1=21

...unless, of course,

 the method of rolling the dice was left intentionally vague: one could throw three dice at once followed by two single rolls and get 18+6+4=28 instead.
Answer: ...unless, of course

 Using 'existing' dice: Backgammon uses a doubling dice with value 16 on one of its sides. Mix that with 4 normal dice to get 16+3+3+3+1 = 26

However:

 The maximum is unbounded. It seems obvious that it is not intended as a trick question, but you only need (for example) one face with value 1/n (rolled 4 times) and another with value n^4*432.
Comment: Our answers can be combined for a score of gjb uhaqerq rvtugrra...
Comment: Not sure how you got that total, but: Gur onpxtnzzba qbhoyvat qvpr vf n phor nf erdhrfgrq gung bayl tbrf gb guvegl-gjb. Rvtugl-bar vf gur pbzovarq znk
Comment: oeps that should be 64 and 148
Comment: Ah, a sixth cube must have slipped in while I was calculating
Answer: The regular cubic backgammon dice have a number of dots from 1 to 6. The divisors of 432 are 1,2,3,4,6 the best chance to obtain the maximum sum is if the the combination has the most divisors. If we assume we throw  one or two dice at a time we obtain the following combinations and their sum.
6,6,6,2,1        the sum is   21
4,4,3,3,3        the sum is 17
6,6,4,3,1        the sum is 20
6,4,3,3,2        the sum is  18
To obtain the maximum sum 6+6+6+6+6=30 we have the least probability. In addition to that $6^5$ is far greater than 432.
So I will bet as maximum sum 20.

Five cubic dice were rolled


How can I use a smartphone/tablet without being distracted by it in classrooms?

Question: I want to use an android phone without being distracted. I want to be able to block calling applications such as the calling feature in whatsapp, facebook messenger, viber calls, as well as google hangouts. There are some of my friends who directly call me when seeing my online.
Answer: Just simply remove the apps from your tablet or disable them if you cant delete them.
If you want them to stay on the tablet then go into the app settings and configure them respectively.
Also Do Not Disturb is your friend, I'd put it on a schedule and set it.
Comment: Exactly. I have tried the "DO NOT DISTURB" feature but it just appear that it cannot block facebook calls. So when I use my tablet to go online and search a word from google translate, I receive an incoming call which is highly annoying.


Expressing multivariate functions as tensor product of univariate functions

Question: I am coming across many instances where multivariate functions are being represented by tensor products of univariate functions.  The basic idea seems to be as follows: Let $\phi_j$ be a univariate function in the variable $x_j$.  Then the rank one tensor $\phi_1\otimes \phi_2 \otimes \dots \otimes \phi_d$ is the multivariate function $\Phi$ defined by $$\Phi(x_1, ..., x_d) = \phi_1(x_1) \cdots \phi_d(x_d) $$ Everywhere I'm seeing this it is stated without justification, and I am wondering how one justifies it.  My attempt at justification requires fixing some bases (assuming that one can) for the $\phi_j$, i.e. suppose $\phi_j \in$ span$\{e_{\ell}\}_{\ell=1}^{p_j}$ with $\phi_j = \sum_{\ell=1}^{p_j} \alpha_{j \ell} e_{\ell}$ for some coefficients $\alpha_{j\ell}$, then by expanding $\phi_1\otimes \phi_2 \otimes \dots \otimes \phi_d$  into the basis, and applying multi-linearity, one would arrive at a sum of the sort $$\sum \alpha_{1 k_1} \cdots \alpha_{d k_d}e_{k_1} \otimes \cdots \otimes e_{k_d} $$ Is this the right idea? Perhaps there is a construction via the universal property, but I only understand this in the case of vector spaces of linear maps.  This is not a homework question, I am just interested in tensors.  Thanks!
Comment: Ryan (Introduction to Tensor Products of Banach Spaces, 2012) proves on p. 50 that $C(K_1 \times K_2) = C(K_1) \hat \otimes_\epsilon C(K_2)$, where $K_{1,2}$ are compact and $\hat \otimes_\epsilon$ denotes the injective tensor product. Perhaps this might help.
Answer: It depends on what functions you are looking at, consider a function space:
$$\mathcal F(A)=\{f:A\to\mathbb K\mid f\text{ satisfies some conditions}\}$$
If these conditions are nice enough $\mathcal F(A)$ is closed under addition and multiplication with $\mathbb K$ and you have a vector space. Examples of nice conditions are compactly supported, continuos, differentiable, bounded, integrable etc.
If you consider a function $f:A\to\mathbb K$ and $g:B\to\mathbb K$ then
$$(f\cdot g)(a,b):=f(a)g(b)$$
defines a function on $A\times B$. If your conditions are nice enough, then from $f\in\mathcal F(A), g\in\mathcal F(B)$ it follows that $f\cdot g\in\mathcal F(A\times B)$. Again, all examples I gave above are nice enough.
Well if $f_i\cdot g_i$ are in $\mathcal F(A\times B)$, so is $\sum_i f_i\cdot g_i$. Also you have:
$$(f_1+f_2)\cdot g = f_1\cdot g+f_2\cdot g\qquad f\cdot(g_1+g_2)=f\cdot g_1+f\cdot g_2\\
(\lambda f)\cdot g=\lambda(f\cdot g)=f\cdot (\lambda g)$$
So basically, the following map is well defined:
$$\iota:\mathcal F(A)\otimes\mathcal  F(B)\to\mathcal F(A\times B)$$
given on the generating set of pure tensors by $f\otimes g\mapsto f\cdot g$.
Its also simple to check, if $\iota(\sum_i f_i\otimes g_i)=\iota(\sum_i \tilde f_i\otimes \tilde g_i)$ that you already must have $\sum_i f_i\otimes g_i = \sum_i \tilde f_i\otimes \tilde g_i$, so this map is an inclusion.
This is the reason why the tensor product of the appropriate function space on $A$ with that of the function space of $B$ is the usual first approximation of that of $A\times B$.
However in most cases $\mathcal F(A)\otimes\mathcal F(B)\neq\mathcal F(A\times B)$, but it is often true (ie for $\mathcal F=C_0, L^p$) that
$$\overline{\iota(\mathcal F(A)\otimes\mathcal F(B))}=\mathcal F(A\times B)$$
ie the closure of the inclusion is the whole space, or the "first approximation" was dense. This requires a topology on the function spaces.
Comment: So given a polynomial $\Phi(x,y) = \phi_1(x)\phi_2(y) \in L^2(X,Y)$, identified with $\phi_1 \otimes \phi_2$ (via the bilinear and linear maps you gave inducing the tensor product), in the case where, say $X = Y = [-1, 1] \subset \mathbb{R}$, we can expand $\phi_1 \otimes \phi_2$ into a basis of orthonormal polynomials and represent $\Phi$ as a multi-dimensional array as per usual?  Do you know of a reference/source for proofs and studies of the injectivity, surjectivity relations you've mentioned, esp. for the $L^p$ spaces?  Thanks for your help.
Comment: Sorry, I had forgotten about the question. For $L^p$ you could look at a standard generating set like continuous functions and try to see why the completion of such products will give you any function. I don't know any references, and didnt find any by quick searching.


Incorrect answer: repeat question again or come back later?

Question: I'm creating an app to teach foreign language. If the user gets the question wrong, should it repeat (if so, how many times) or come back later (ie shuffle back into the deck)?
Comment: Do you assume a limited number of question per session? When and how often will things shuffled back into the deck appear?
Comment: Can you please edit your question to make it clear that you are not looking for personal opinions but factual arguments, possibly even evidence?
Answer: Actually this depends on the system requirements. However, why don't you just adjust the system so that allows the learner to choose if they want to shuffle or repeat. You can go further by also add an option to show the answer. But in language learning coming back to the information later on regular intervals provides continuous activation to the responsible neurons which helps with the information retention.


Is web browsing in a remote session on windows server 2008 safe?

Question: I am thinking about having employees use a remote desktop connection to connect to the server running windows server 2008 r2 to access programs and run programs from the server. The majority of their work and time would be running on the actual server through the RDC. The number of clients would be somewhere around 10-15 total. I do plan on Installing some form of Anti-virus software however, I am skeptical as to whether or not I should allow users to browse the internet on the main server computer but I don't have any other logical alternatives besides having them minimize the remote session and browse on their client PC. The question is whether or not it is recommended, or safe to browse the web on the server? I know that I could allow only certain websites that are trusted but I don't want to jump into limiting employees to 10 total websites right away. If it is not recommended to use the server for web browsing what kind of alternative can I use to allow them free-range access to browse the web?
Answer: This is my opinion, but you should never be browsing the web from a server.
Can you? Yeah. Should you? Absolutely not.
If you want a proper set up for your users, you want to plan out either a virtual desktop infrastructure, or a RemoteApp deployment.
Comment: Ok, this is the reassurance that I was looking for because while I was trying to research this a little I couldn't really find anything that said specifically if you should or shouldn't.
Comment: I will look into VDI and remoteApp but quickly, do they act the same as RDC? will each user have to connect in essentially the same way as they would with RDC?
Comment: @user3841709 No they are separate, complex technologies of their own, and you'll want to do a lot of learning and testing if you want to deploy them.
Comment: Sounds good, this offers the alternative I was looking for and probably steering me away from doing something stupid like browsing the internet on the server. Just personally, do you have a preference between VDI and RemoteApp?
Comment: @user3841709 Browsing from a server is generally as safe as browsing from a client PC.  (And hopefully we all realize how safe... or not... that is.)  Difference and problem being that when you browse form a server, any infections or "data leakage" impacts all the users of the server, which is generally a lot more than you have on a client PC.
Comment: @HopelessN00b Yes that's true, I was also thinking about the fact that all of the data and files as well would be located mainly on the server and that an infection would then wipe out possibly all of the data rather than just data on one PC.
Answer: As @HopelessN00b stated, browsing the internet from a server is about as safe/risky as doing it from a client workstation. The difference being that the scope of impact of a malware infection, hack, etc. is potentially much greater on the server. That being said, you are running an RDS server whose purpose is to host user sessions and run user applications. Users browse the internet. Asking them to minimize their RDS session every time they need to browse the internet strikes me as inefficient and may impact their productivity if they need to browse the internet as part of their job or business process(es). Many users us web based tools and applications as more and more vendors put their applications "in the cloud" (QuickBooks Online being just one example).
My recommendation would be to sufficiently secure the server (AV software, user and software restrictions, etc.) and make sure you're backing it up completely and regularly.
Comment: Thanks for the answer. I have began looking into RemoteApp as @RyanRies suggested and It looks pretty good to me. Once I create an installer package and deploy it, the users won't know the difference that its a remote app and not running on their local machine. This will then allow me to let IE or google chrome run on their local machine without risking internet browsing on the server. One question I have that maybe you could answer, I don't know how much you know about RemoteApp but, If I have 10 RemoteApps each on 10 computers, does this cause any major performance issues?
Comment: On the Client PC's I mean, Since they are running on the server I know that it depends on the hardware of the server but will the remote connections cause the client PC to slow if say multiple remote programs are opened at once.
Comment: With multiple RemoteApp's running on each client you'll likely have more data traversing the network (server to client screen data and client to server keystrokes and mouse clicks) and you'll have more graphics redraws on the clients but I don't think that should be cause to worry. Granted, I haven't yet deployed RemoteApp yet so I'm basing this comment on my knowledge of RDS in general. I'm sure that there are optimizations done on the client and the server
Comment: Yea I didn't really think about that at first but I will need to make sure my internet connection is stable and reliable so that it's not constantly being disconnected with a large number of remote connections right?
Comment: Any type of RDS session (Desktop or RemoteApp) is fairly intolerant of network issues, whether they be bandwidth saturation, latency, packet loss or whatever. You'll have issues with screen lag, delayed characters when typing, etc.
Comment: Ok Thanks, I will start doing a lot more research on remoteApps and everything else I can find and go from there.
Comment: Glad to help...


NIM game variant - one pile, taking square number of objects

Question: There are $n$ objects on the table. Two players take turns. In one move player can take $x^2$ ($x$ is any integer, players can change it) objects. Player who can't do any move loses and the other one wins. How many $n$ are there such that the second player has a winning strategy? I think there are infinitely many $n$, but I have no idea how to prove it.
Comment: What is $x$????
Comment: $x$ is any integer.
Comment: since taking $1$ is a valid move, do I understand correctlly that who takes the last object wins?
Comment: Yes, the one who takes the last object wins.
Comment: Incidentally, this game is very well known/studied. See https://en.wikipedia.org/wiki/Subtract_a_square for a lot of information going beyond the scope of this question.
Answer: Define "position $k$" as a scenario where there are $k$ objects on the table at a player's turn to move.

Call position $k$ winning if a player with that position has a winning strategy (i.e., a strategy which can guarantee a win, regardless of the moves chosen by the opponent).

If a position is not winning, call it losing.

Let $W$ be the set of all winning positions, and let $L$ be the set of all losing positions.

For example, $1, 3, 4  \in W$ and $0, 2, 5  \in L$.

If the game starts in a losing position, then player $2$ has a winning strategy.

The question being asked is: How many elements does the set $L$ have?

Claim $L$ is infinite.

Suppose otherwise.

Then $L$ has a largest element, $m$, say.

Clearly we must have $m >2$ (since $5 \in L$).

Now consider the position $n = m^2-1$.

Since $n > m$, position $n$ must be winning.

It follows that for some positive integer $k < m^2$, we must have $n - k^2 \in L$.

But $n-k^2$ can't be in $L$, since
$$n - k^2 \ge n - (m-1)^2 = (m^2-1)-(m-1)^2 = 2m - 2 > m$$
Thus, we have a contradiction.

Therefore, as claimed, $L$ must be infinite.
Comment: Since $n = m^2 - 1$, the player can't subtract $m^2$.
Comment: It was obvious... well done!
Answer: The game can be completely define recursively. Start at $n=1$, the first player takes that object and wins. At $n=2$, the first player has only one valid move, that is taking $1$ object, leaving the second player in a situation that has already been proven being a winning one. So first player loses. At $n=3$ the first player has at least one move (again, taking $1$ object) that sends the second player in a situation that has ben proven a losing one, so the first player wins. At higher $n$'s you go on checking whether the first player has at least one valid move to send the second player in a situation that has already been proven losing. If he doesn't have such a move, he is forced leaving the second player in a winning position so he loses.
Here is the winning table for $n$ up to $100$ (the rightmost number is one possible winning move for the first player):
Comment: This doesn't really address how to prove there are infinitely many losing positions.
Comment: For sure. It just wanted to be a contribution to get the whole picture of the game.


What does COM object mean?

Question: What is it? As I understood it's a kind of Microsoft special technology for some objects. But what exactly?
Answer: A COM object is basically a black box that implements some known interface.  It can also register itself with Windows so that programs can get a hold of it.
For example, let's say there is some interface ICalculator, that I write my program to  use.  I can now swap in any object, written in any programming language (since it is a binary interface) that implements ICalculator.  Then at runtime, I can provide some sort of option to my users so that they can choose to use the FooCorpCalculator COM object, written in Python, or perhaps if they need more speed they can choose a NinjaCalculator written in C.  The point is, I write my program to depend on an interface, not an implementation, and then choose to use the actual COM object that implements the interface later.
There's a lot more to it, of course, but that may be an example that makes it more concrete for you.
Answer: See this Wikipedia article: Component Object Model

Component Object Model (COM) is a binary-interface standard for software componentry introduced by Microsoft in 1993. It is used to enable interprocess communication and dynamic object creation in a large range of programming languages. The term COM is often used in the Microsoft software development industry as an umbrella term that encompasses the OLE, OLE Automation, ActiveX, COM+ and DCOM technologies.

A COM object is often implemented in a DLL file.  They can be used by programs for a variety of functions.  The term "object" as used here refers to objects in object-oriented programming.
Comment: that's why I asked this question. because the Wikipedia didn't answer it. The definition is very abstract and I don't see any real example.
Answer: It's basically an old technology used for writing programs in the Windows environment. It's big and complex and wasn't enjoyable to manage/support. The .NET framework is its replacement.
Comment: They can be called from .NET, but they are a completely different system. It's called COM Interop. You can explore them a bit on your computer - under Control Panel >> Administrative Tools >> Component Services.
Comment: aren't COM objects used in .NET framework?
Comment: COM isn't going anywhere any time soon. It's extensively used by Microsoft's own products. I think it's therefore a bit misleading that you call it "basically an old technology". Yes, it was first introduced in the early 90s, so technically it is "old" in the sense that it's been around a while, but you need to take care *not* to indicate that it is obsolete or outdated.
Answer: COM is set of Windows-specific technologies to enable code reuse and interoperability, primarily at the level of the binary (not necessarily at the level of the source code).
In the early 1990s Bill Gates didn't permit that the Powerpoint development team implement an own charting subsystem for the Powerpoint product, because Microsoft already had Excel. So they developed a specification to enable their in-house products to exchange data and call each others functions. Microsoft generalized these APIs, published them and a lot more code design guidelines.
See this video from 2006: Tony Williams: Co-inventor of COM
I think, that now in 2012, COM is still at the core of WMI and Office.

What does COM object mean?