Observing stale instruction fetching on x86 with self-modifying code

Question: I've been told and have read from Intel's manuals that it is possible to write instructions to memory, but the instruction prefetch queue has already fetched the stale instructions and will execute those old instructions. I have been unsuccessful in observing this behavior. My methodology is as follows.
The Intel software development manual states from section 11.6 that

A write to a memory location in a code segment that is currently cached in the processor causes the associated  cache line (or lines) to be invalidated. This check is based on the physical address of the instruction. In addition, the P6 family and Pentium processors check whether a write to a code segment may modify an instruction that has  been prefetched for execution. If the write affects a prefetched instruction, the prefetch queue is invalidated. This latter check is based on the linear address of the instruction.

So, it looks like if I hope to execute stale instructions, I need to have two different linear addresses refer to the same physical page. So, I memory map a file to two different addresses.
int fd = open("code_area", O_RDWR | O_CREAT, S_IRWXU | S_IRWXG | S_IRWXO);
assert(fd>=0);
write(fd, zeros, 0x1000);
uint8_t *a1 = mmap(NULL, 0x1000, PROT_READ | PROT_WRITE | PROT_EXEC,
        MAP_FILE | MAP_SHARED, fd, 0);
uint8_t *a2 = mmap(NULL, 0x1000, PROT_READ | PROT_WRITE | PROT_EXEC,
        MAP_FILE | MAP_SHARED, fd, 0);
assert(a1 != a2);

I have an assembly function that takes a single argument, a pointer to the instruction I want to change.
fun:
    push %rbp
    mov %rsp, %rbp

    xorq %rax, %rax # Return value 0

# A far jump simulated with a far return
# Push the current code segment %cs, then the address we want to far jump to

    xorq %rsi, %rsi
    mov %cs, %rsi
    pushq %rsi
    leaq copy(%rip), %r15
    pushq %r15
    lretq

copy:
# Overwrite the two nops below with `inc %eax'. We will notice the change if the
# return value is 1, not zero. The passed in pointer at %rdi points to the same physical
# memory location of fun_ins, but the linear addresses will be different.
    movw $0xc0ff, (%rdi)

fun_ins:
    nop   # Two NOPs gives enough space for the inc %eax (opcode FF C0)
    nop
    pop %rbp
    ret
fun_end:
    nop

In C, I copy the code to the memory mapped file. I invoke the function from linear address a1, but I pass a pointer to a2 as the target of the code modification.
#define DIFF(a, b) ((long)(b) - (long)(a))
long sz = DIFF(fun, fun_end);
memcpy(a1, fun, sz);
void *tochange = DIFF(fun, fun_ins);
int val = ((int (*)(void*))a1)(tochange);

If the CPU picked up the modified code, val==1. Otherwise, if the stale instructions were executed (two nops), val==0.
I've run this on a 1.7GHz Intel Core i5 (2011 macbook air) and an Intel(R) Xeon(R) CPU X3460 @ 2.80GHz. Every time, however, I see val==1 indicating the CPU always notices the new instruction.
Has anyone experience with the behavior I want to observe? Is my reasoning correct? I'm a little confused about the manual mentioning P6 and Pentium processors, and what the lack of mentioning my Core i5 processor. Perhaps something else is going on that causes the CPU to flush its instruction prefetch queue? Any insight would be very helpful!
Comment: What is the manual your used (check the "order number" on the first page and write it here)?
Comment: Also check "8.1.3 Handling Self- and Cross-Modifying Code" section of instruction manual - http://download.intel.com/products/processor/manual/325462.pdf
Comment: Hmm, try to unset PROT_EXEC from a2... This can affect some Intel Atoms
Comment: "Pentium" or P5 is a particular implemention, sold 1993-1996.  P6 is another implementation and was marketed/sold as "PentiumPro", 1995-1999.  You'll have a tough time finding either today.
Answer: I think, you should check the MACHINE_CLEARS.SMC performance counter (part of MACHINE_CLEARS event) of the CPU (it is available in Sandy Bridge 1, which is used in your Air powerbook; and also available on your Xeon, which is Nehalem 2 - search "smc"). You can use oprofile, perf or Intel's Vtune to find its value:
http://software.intel.com/sites/products/documentation/doclib/iss/2013/amplifier/lin/ug_docs/GUID-F0FD7660-58B5-4B5D-AA9A-E1AF21DDCA0E.htm

Machine Clears
Metric Description
Certain events require the entire pipeline to be cleared and restarted from just after the last retired instruction. This metric measures three such events: memory ordering violations, self-modifying code, and certain loads to illegal address ranges.
Possible Issues
A significant portion of execution time is spent handling machine clears. Examine the MACHINE_CLEARS events to determine the specific cause.

SMC: http://software.intel.com/sites/products/documentation/doclib/stdxe/2013/amplifierxe/win/win_reference/snb/events/machine_clears.html

MACHINE_CLEARS Event Code: 0xC3
  SMC  Mask: 0x04
Self-modifying code (SMC) detected.
Number of self-modifying-code machine clears detected.

Intel also says about smc http://software.intel.com/en-us/forums/topic/345561 (linked from Intel Performance Bottleneck Analyzer's taxonomy

This event fires when self-modifying code is detected. This can be typically used by folks who do binary editing to force it to take certain path (e.g. hackers). This event counts the number of times that a program writes to a code section. Self-modifying code causes a severe penalty in all Intel 64 and IA-32 processors. The modified cache line is written back to the L2 and LLC caches. Also, the instructions would need to be re-loaded hence causing performance penalty.

I think, you will see some such events. If they are, then CPU was able to detect act of self-modifying the code and raised the "Machine Clear" - full restart of pipeline. First stages are Fetch and they will ask L2 cache for new opcode. I'm very interested in the exact count of SMC events per execution of your code - this will give us some estimate about latencies.. (SMC is counted in some units where 1 unit is assumed to be 1.5 cpu cycles - B.6.2.6 of intel optimization manual)
We can see that Intel says "restarted from just after the last retired instruction.", so I think last retired instruction will be mov; and your nops are already in the pipeline. But SMC will be raised at mov's retirement and it will kill everything in pipeline, including nops.
This SMC induced pipeline restart is not cheap, Agner has some measurements in the Optimizing_assembly.pdf - "17.10 Self-modifying code (All processors)" (I think any Core2/CoreiX is like PM here):

The penalty for executing a piece of code immediately after modifying it is approximately 19 clocks for P1, 31 for PMMX, and 150-300 for PPro, P2, P3, PM. The P4 will purge the entire trace cache after self-modifying code. The 80486 and earlier processors require a jump between the modifying and the modified code in order to flush the code cache.
  ...
Self-modifying code is not considered good programming practice. It should be used only if
  the gain in speed is substantial and the modified code is executed so many times that the
  advantage outweighs the penalties for using self-modifying code.

Usage of different linear addresses to fail SMC detector was recommended here:
https://stackoverflow.com/a/10994728/196561 - I'll try to find actual intel documentation... Can't actually answer to your real question now.
There may be some hints here: Optimization manual, 248966-026, April 2012 "3.6.9 Mixing Code and Data":

Placing writable data in the code segment might be impossible to distinguish
  from self-modifying code. Writable data in the code segment might suffer the
  same performance penalty as self-modifying code.

and next section

Software should avoid writing to a code page in the same 1-KByte subpage that is
  being executed or fetching code in the same 2-KByte subpage of that is being
  written. In addition, sharing a page containing directly or speculatively executed
  code with another processor as a data page can trigger an SMC condition that causes
  the entire pipeline of the machine and the trace cache to be cleared. This is due to the
  self-modifying code condition.

So, there is possibly some schematics which controls intersections of writable and executable subpages.
You can try to do modification from the other thread (cross-modifying code) -- but the very careful thread synchronization and pipeline flushing is needed (you may want to include some brute-forcing of delays in writer thread; CPUID just after the synchronization is desired). But you should know that THEY already fixed this using "nukes" - check US6857064 patent.

I'm a little confused about the manual mentioning P6 and Pentium processors

This is possible if you had fetched, decoded and executed some stale version of intel's instruction manual. You can reset the pipeline and check this version: Order Number: 325462-047US, June 2013  "11.6 SELF-MODIFYING CODE". This version still not says anything about newer CPUs, but mentions that when you are modifying using different virtual addresses, the behavior may be not compatible between microarchitectures (it may work on your Nehalem/Sandy Bridge and may not work on .. Skymont)

11.6 SELF-MODIFYING CODE
  A write to a memory location in a code segment that is currently cached in the processor causes the associated  cache line (or lines) to be invalidated. This check is based on the physical address of the instruction. In addition,  the P6 family and Pentium processors check whether a write to a code segment may modify an instruction that has  been prefetched for execution. If the write affects a prefetched instruction, the prefetch queue is invalidated. This  latter check is based on the linear address of the instruction. For the Pentium 4 and Intel Xeon processors, a write  or a snoop of an instruction in a code segment, where the target instruction is already decoded and resident in the trace cache, invalidates the entire trace cache. The latter behavior means that programs that self-modify code can cause severe degradation of performance when run on the Pentium 4 and Intel Xeon processors.
In practice, the check on linear addresses should not create compatibility problems among IA-32 processors. Applications that include self-modifying code use the same linear address for modifying and fetching the instruction.
Systems software, such as a debugger, that might possibly modify an instruction using a different linear address than that used to fetch the instruction, will execute a serializing operation, such as a CPUID instruction, before the modified instruction is executed, which will automatically resynchronize the instruction cache and prefetch queue.  (See Section 8.1.3, "Handling Self- and Cross-Modifying Code," for more information about the use of self-modifying code.)
For Intel486 processors, a write to an instruction in the cache will modify it in both the cache and memory, but if  the instruction was prefetched before the write, the old version of the instruction could be the one executed. To  prevent the old instruction from being executed, flush the instruction prefetch unit by coding a jump instruction  immediately after any write that modifies an instruction

REAL Update, googled for "SMC Detection" (with quotes) and there are some details how modern Core2/Core iX detects SMC and also many errata lists with Xeons and Pentiums hanging in SMC detector:

http://www.google.com/patents/US6237088 System and method for tracking in-flight instructions in a pipeline @ 2001
DOI 10.1535/itj.1203.03  (google for it, there is free version at citeseerx.ist.psu.edu) - the "INCLUSION FILTER" was added in Penryn to lower number of false SMC detections; the "existing inclusion detection mechanism" is pictured on Fig 9
http://www.google.com/patents/US6405307 - older patent on SMC detection logic

According to patent US6237088 (FIG5, summary) there is "Line address buffer" (with many linear addresses one address per fetched instruction -- or in other word the buffer full of fetched IPs with cache-line precision). Every store, or more exact  "store address" phase of every store will be feed into parallel comparator to check, will store intersects to any of currently executing instructions or not.
Both patents don't clearly say, will they use physical or logical address in SMC logic... L1i in Sandy bridge is VIPT (Virtually indexed, physically tagged, virtual address for the index and physical address in the tag. ) according to http://nick-black.com/dankwiki/index.php/Sandy_Bridge so we have the physical address at time when L1 cache returns data. I think intel may use physical addresses in SMC detection logic.
Even more, http://www.google.com/patents/US6594734 @ 1999 (published 2003, just remember that CPU design cycle is around 3-5 years) says in the "Summary" section that SMC now is in TLB and uses physical addresses (or in other word - please, don't try to fool SMC detector):

Self modifying code is detected using a translation lookaside buffer .. [which] has physical page addresses stored therein over which snoops can be performed using the physical memory address of a store into memory. ... To provide finer granularity than a page of addresses, FINE HIT bits are included with each entry in the cache associating information in the cache to portions of a page within memory.

(portion of page, referred to as quadrants in the patent US6594734, sounds like 1K subpages, isn't it?)
Then they says

Therefore snoops, triggered by store instructions into memory, can perform SMC detection by comparing the physical address of all instructions stored within the instruction cache with the address of all instructions stored within the associated page or pages of memory. If there is an address match, it indicates that a memory location was modified. In the case of an address match, indicating an SMC condition, the instruction cache and instruction pipeline are flushed by the retirement unit and new instructions are fetched from memory for storage into the instruction cache.
Because snoops for SMC detection are physical and the ITLB  ordinarily accepts as an input a linear address to translate into a physical address, the ITLB  is additionally formed as a content-addressable memory on the physical addresses and includes an additional input comparison port (referred to as a snoop port or reverse translation port)

-- So, to detect SMC, they force the stores to forward physical address back to instruction buffer via snoop (similar snoops will be delivered from other cores/cpus or from DMA writes to our caches....), if snoop's phys. address conflicts with cache lines, stored in instruction buffer, we will restart pipeline via SMC signal delivered from iTLB to retirement unit. Can imagine how much cpu clocks will be wasted in such snoop loop from dTLB via iTLB and to retirement unit (it can't retire next "nop" instruction, although it was executed early than mov and has no side effects). But WAT? ITLB has physical address input and second CAM (big and hot) just to support and defend against crazy and cheating self-modifying code.
PS: And what if we will work with huge pages (4M or may be 1G)? The L1TLB has huge page entries, and there may be a lot of false SMC detects for 1/4 of 4 MB page...
PPS: There is a variant, that the erroneous handling of SMC with different linear addresses was present only in early P6/Ppro/P2...
Comment: If you look further, you will see patents relating to SMC on which I am an inventor.  AFAIK I invented the I$ and ITLB inclusion mechanisms of P6 to snoop "instructions in flight".  // I consider these to be mistakes.  I think that it would have been easier to create to create a fully associative CAM with the instruction blocks of all instructions in the pipeline, physical.  With a bloom filter if you want to save power.  // I think they were mistakes (a) because complicated and hard to get correct, even though they saved a lot of gates, and (b) glass jaws in performance.
Comment: What if the code you modified was always, say, 1k bytes ahead of the current execution address? Would that avoid the problem?
Comment: +1 for throwing "air powerbook" into such a precise discussion of Intel minutiae :)
Answer:
I've been told and have read from Intel's manuals that it is possible
  to write instructions to memory, but the instruction prefetch queue
  has [may have] already fetched the stale instructions and will [may]
  execute those old instructions. I have been unsuccessful in observing this behavior.

Yes, you would be.
All or almost all modern Intel processors are stricter than the manual:
They snoop the pipeline based on physical address, not just linear.
Processor implementations are allowed to be stricter than the manuals.
They may choose to be so because they have encountered code that does not adhere to the rules in the manuals, that they do not want to break.
Or... because the easiest way to adhere to the architectural specification (which in the case of SMC used to be officially "up until the next serializing instruction" but in practice, for legacy code, was "up until the next taken branch that is more than ??? bytes away") might be to be stricter.
Comment: Another interesting example of CPUs going above and beyond the requirements specified in the x86 ISA manual: [Coherent page-walks for TLB entries that could only have been speculatively loaded](http://blog.stuffedcow.net/2015/08/pagewalk-coherence/), to avoid breaking Win9x.  AMD dropped coherency with Bulldozer, since I guess they decided Win9x and other software that depended on this was no longer relevant.
Comment: (2a') one of the most embarrassing bugs was related to add-with-carry to memory. In early microcode. The load would go, the carry flag would be updated, and the store could fault -but the carry flag had already been updated, so the instruction could not be restarted.  // it was  a simple microcode fix, doing the store before the carry flag was written - but one extra uop was enough to make that instruction not fit in the "medium speed" ucode system.
Comment: Something similar applies to self modifying code: it was not so much that we wanted to make self modifying code run fast, as that trying to make the legacy mechanisms for self modifying code - draining the pipe for serializing instructions like CPUID - were slower than just snooping the Icache and pipeline. But, again, this applies to a high end machine: on a low end machine, the legacy mechanisms are fast enough and cheap.
Comment: I've been meaning to elaborate @PeterCordes' comment about "coherent" page table walking for TLB misses, but I will be quick: (1) the main reason Intel started running the page table walks through the cache, rather than bypassing the cache, was performance. Prior to P6 page table walks were slow, not benefitting from cache, and were non-speculative. Slow enough that software TLB miss handling was a performance win. P6 sped TLB misses up by doing them speculatively, using the cache, and also by caching intermediate nodes like page directory entries.
Comment: Thanks, Andy.  This is some great history!  I feel like it belongs in an answer somewhere, either this one as a giant aside, or maybe a self-answered Q&A if we can think of a good "question" that has this as the answer :P  Holy crap, so *that's* where that extra ALU uop comes from in memory-destination ADC, even on Core2 and SnB-family?  Never would have guessed, but had been puzzled by it.
Comment: (1b) recall that when P6 was started P5 was not shipping: the existing x86es all did cache bypass page table walking in-order, non-speculatively, no asynchronous prefetches, but on write through caches.  I.e. They WERE cache coherent, and the OS could rely on deterministic replacement of TLB entries.  IIRC I wrote those architectural rules about speculative and non-deterministic cacheability, both for TLB entries and for data and instruction caches. You can't blame OSes like Windows and UNIX and Netware for not following page table and TLB management rules that did not exist at the time.
Comment: (2) one of my biggest regrets wrt P6 is that we did not provide Intra-instruction TLB consistency support. Some instructions access the same page more than once. It was possible for different uops in the same instruction to get different translations for the same address. If we had given microcode the ability to save a physical address translation, and then use that, things would have been better IMHO.
Comment: (4'') because MP TLB shoot downs using interprocessor interrupts were expensive, OS performance guys (like I used to be) are always making arguments like "we don't need to invalidate the TLB after changing a PTE from invalid to valid" or "from valid read-only to valid writable with a different address". Or "we don't need to invalidate the TLB after changing a PDE to point to a different PT whose PTEs are exactly the same as the original PT...". // Lots of great ingenious arguments. Unfortunately not always correct.
Comment: Some of my computer architect friends now espouse coherent TLBs: TLBs that snoop writes just like data caches. Mainly to allow us to build even more aggressive TLBs and page table caches, if both valid and invalid entries of leaf and interior nodes. And not to have to worry about OS guys' assumptions. // I am not there yet: too e pensive for low end hardware.  But might be worth doing at high end.
Comment: (1a) By the way, AMD was reluctant to do TLB miss handling speculatively. I think because they were influenced by DEC VAX Alpha architects. One of the DEC Alpha architects told me rather emphatically that speculative handling of TLB misses, such as P6 was doing, was incorrect and would never work. When I arrived at AMD circa 2002 they still had something called a "TLB Fence" - not a fence instruction, but a point in the rop or microcode sequence where TLB misses either could or could not be allowed to happen - I am afraid that I do not remember exactly how it worked.
Comment: (1a') so I think that it is not so much that Bulldozer abandoned TLB and page table walking coherency, whatever that means, as that Bulldozer may have been the first AMD machine to do moderately aggressive TLB miss handling.
Comment: (2a) I was a RISC proponent when I joined P6, and my attitude was "let SW (microcode) do it".
Comment: (3) Anyway - the main "support" P6 and its descendants gave to handling TLB coherency issues was to rewalk the page tables at retirement before reporting a fault.   This avoided confusing the OS by reporting a fault when the page tables said there should not be one.
Comment: (4) meta comment: I don't think that any architecture has properly defined rules for caching of invalid TLB entries. // AFAIK most processors do not cache invalid TLB entries - except possibly Itanium with its NAT (Not A Thing) pages. But there's a real need: speculative memory accesses may be to wild addresses, miss the TLB, do an expensive page table walk, slowing down other instructions and threads - and then doing it over and over again because the fact that "this is a bad address, no need to walk the page tables" is not remembered. // I suspect that DOS attacks could use this.
Comment: (4') worse, OSes may make implicit assumptions that invalid translations are never cached, and therefore not do a TLB invalidation or MP TLB shoot down when transitioning from invalid to valid. // Worse^2: imagine that you are caching interior nodes of the page table cache. Imagine that  PD contains all invalid PDE; worse^3, that the PD contains valid d PDEs that point to PTs that are all invalid. Are you still allowed to cache those PDEs? Exactly when does the OS need to invalidate an entry?
Comment: Yep: often when you "do the RISC thing" extra instructions or micro instructions are required, in a careful order. Whereas if you have "CISCy" support, like special hardware support so that a single instruction is a transaction, either all done or all not done, shorter code sequences can be used.
Comment: Ditto memory ordering. High end snooping faster; low end draining cheaper.
Comment: It is hard to maintain this dichotomy.
Comment: It is pretty common that a particular implementation has to implement rules compatible with but stronger than the architectural statement. But not all implementations have to do it the same way.
Comment: Cute: what I said about "DOS Attacks" relating to caching of invalid translations can go both ways. I meant that malware running on one thread could try to deny service to a different thread on the same CPU.  // But also: the recent IoT DOS attack on dyn.com might have been helped by DNS servers caching, not just a single invalid hostname, but something like a Bloom filter where valid addresses were concentrated in a few bits, and the invalid host names that the attackers generated wound hopefully map to zero bits in the Bloom filter.
Comment: I quoted your comments into [an old answer of mine about TLB miss handling](https://stackoverflow.com/questions/32256250/what-happens-after-a-l2-tlb-miss), where maybe more people will see this interesting stuff.  Thanks again for the look behind the scenes of why stuff was designed the way it is, and the history.
Answer: Sandybridge-family (at least Skylake) still has the same behaviour, apparently snooping on physical address.
Your test is somewhat overcomplicated, though.  I don't see the point of the far jump, and if you assemble (and link if necessary) the SMC function into a flat binary you can just open + mmap it twice.  Make a1 and a2 function pointers, then main can return a1(a2) after mapping.
Here's a simple test harness, in case anyone wants to try on their own machine: (The open/assert/mmap block was copied from the question, thanks for the starting point.)
(Downside, you have to rebuild the SMC flat binary every time, because mapping it with MAP_SHARED actually modifies it.  IDK how to get two mappings of the same physical page that won't modify the underlying file; writing to a MAP_PRIVATE would COW it to a different physical page.  So writing the machine code to a file and them mapping it makes sense now that I realize this.  But my asm is still a lot simpler.)
// smc-stale.c
#include <sys/mman.h>
#include <fcntl.h>
#include <stdlib.h>
#include <unistd.h>
#include <assert.h>

typedef int (*intfunc_t)(void *);   // __attribute__((sysv_abi))  // in case you're on Windows.

int main() {
    int fd = open("smc-func", O_RDWR);

    assert(fd>=0);
    intfunc_t a1 = mmap(NULL, 0x1000, PROT_READ | PROT_WRITE | PROT_EXEC,
                MAP_FILE | MAP_SHARED, fd, 0);
    intfunc_t a2 = mmap(NULL, 0x1000, PROT_READ | PROT_WRITE | PROT_EXEC,
                MAP_FILE | MAP_SHARED, fd, 0);
    assert(a1 != a2);
    return a1(a2);
}

NASM source for the test function:
(See How to generate plain binaries like nasm -f bin with the GNU GAS assembler? for an as+ld alternative to nasm -f)
;;build with nasm smc-func.asm     -fbin is the default.
bits 64
entry:   ; rdi = another mapping of the same page that's executing
    mov  byte [rdi+dummy-entry], 0xcc       ; trigger any copy-on-write page fault now

    mov  r8, rbx    ; CPUID steps on call-preserved RBX
    cpuid               ; serialize for good measure
    mov  rbx, r8
;    mfence
;    lfence

    mov   dword [rdi + retmov+1 - entry],  0       ; return 0 for snooping
retmov:
    mov   eax, 1      ; opcode + imm32             ; return 1 for stale
    ret

dummy:  dd 0xcccccccc

On an i7-6700k running Linux 4.20.3-arch1-1-ARCH, we do not observe stale code fetch.  The mov that overwrote the immediate 1 with a 0 did modify that instruction before it ran.
peter@volta:~/src/experiments$ gcc -Og -g smc-stale.c
peter@volta:~/src/experiments$ nasm smc-func.asm && ./a.out; echo $?
0
# remember to rebuild smc-func every time, because MAP_SHARED modifies it

Comment: This was initially a little confusing to me because in the original question and code, a return value of 0 indicates the stale instruction was executed, but you have flipped it in your code so that 1 indicates the stale instruction, 0 indicates that the instruction was modified before execution. However, the conclusion is the same: no stale instruction execution is observed. Thanks for the contribution!
Answer: It targets a much older CPU (the Intel 8088) but the 4 channel music player at the end of the 8088 MPH demo not only executes stale instructions but depends on them being stale! https://www.reenigne.org/blog/8088-pc-speaker-mod-player-how-its-done/
Comment: Fun fact: stale instruction fetch was one way to detect 8086 vs. 8088, as mentioned in an answer on [Why did x86 support self-modifying code in the 80s and 90s?](https://retrocomputing.stackexchange.com/a/25755).  8086 had a 6 byte prefetch queue, vs. 4 on 8088.


Why is meniscus formed?

Question: Why does water tends to form meniscus (as it increases the surface area) if it has the tendency to lower the amount of free surface?
Comment: [See](https://van.physics.illinois.edu/qa/listing.php?id=2220)
Answer: A meniscus is formed because the adhesive and cohesive forces don't balance each other perfectly,so there can be extra pull/push due to the force between the surface of the container and the fluid, which forms a meniscus
Answer: Adhesion is responsible for a meniscus and this has to do in part with fluid's fairly high surface tension. Fluid molecules are attracted to the molecules in the wall of the glass beaker and since fluid molecules like to stick together, when the molecules touching the fluid cling to it, other molecules of fluid cling to the molecules touching the glass, which forms a meniscus.
If you want more clarification about this topic, then consult online tutors of TutorEye.

Why is meniscus formed?


What is Proof Load of Bolts?

Question: I seem to be getting conflicting information. Shigley's Mechanical Engineering Design textbook states that, "proof load is the maximum load (force) that a bolt can withstand without acquiring a permanent set". Other sources online say that proof load is approximately 90% of yield strength. Based on Shigley's definition, a bolt begins to yield before reaching the yield point?
Answer: First of all, I'd like to point out that you are mixing (not without reason) the concept of proof load which is intended for bolts and the concept of proof stress and yield stress that is intended for materials.
Yield stress vs proof stress (and others)
Typically, the stress needed to produce 0.2% of plastic deformation is considered proof stress (sometimes Proof stress is also called offset yield stress). It's important to determine the value or level of stress that can be applied before a material "yields" or changes its composition, size, or shape, when a material does not have a distinct yield point (see below comparison of mild steel with aluminium).

In my opinion the reason that the 0.2% strain was used for proof stress, is that it offers a more straight forward comparison with the yield stress of hot worked and annealed steel. You can see more on that in the question.
So by definition, when a material reaches proof stress then plastic deformation has started (although very small levels of plastic deformation). So the terms of proof stress and yield stress are used respectively for materials that do not or do exhibit yield points respectively.
Despite being different, in most applications yield stress and proof stress are used interchangeably without any significant consequences.
If you wanted to be absolutely pedantic, you'd need to look at the following diagram, where proportionality and elastic limit are also defined.

Proportionality limit, is the region in the mild steel stress strain curve that $\sigma = E \epsilon$

Elastic limit: between the proportionality limit and the elastic limit, the stress is not strictly proportional to E  (i.e. $\sigma \ne E\epsilon$), AND the material does not exhibit plastic deformation.

yield point is a very clear feature on the stress/strain curve of mild steel, and it coincides with 0.2% permanent deformation.

As you can see there is some breathing room (arguably very very small) between elastic limit and the definition of yield point (which usually sets the upper yield stress). However, again the differences between proportionality/elastic/lower yield/upper yield stress are so small, that they basically collectively merge in the consciousness of engineers as yield stress.
From that merging, all these conflicting accounts for proof stress and yield stress emerge.
Proof load of bolts
Now, coming onto Proof load for bolts. Bolts are a structural element. As such they can be made from different materials and/or different treatments. So you could have bolts from a how worked steel with a clear yield point, but you could also have a bolt from titanium  (or a cold worked steel) which does not have a yield point, so proof stress is more appropriate.
The most general approach is to use the proof stress and thus proof load.
Regarding Shigley's statement that "proof load is the maximum load (force) that a bolt can withstand without acquiring a permanent set", my interpretation is that its extending the simplified version of the concept of proof stress (and yield stress) to bolts. To clarify it further, by simplified version, I mean that proof (and yield) stress are the stress at which there is no (in the sense that 0.2% is very very small) plastic deformation on material.
To put this into perspective, an 80mm bolt, assuming its stresses along its entire length would need to deform about 0.160mm.
Answer: Proof load is the maximum load the bolt can carry without exceeding deformation criteria.
Below are quotes from two sources:

Proof load is an amount of force that a fastener must be able to withstand without permanently deforming.

Proof load is defined as the maximum tensile force that can be applied to a bolt that will not result in plastic deformation. A material must remain in its elastic region when loaded up to its proof load typically between 85-95% of the yield strength. Acceptable clamp load is typically 75% of proof load.

What is Proof Load of Bolts?


What's does poetry mean in 'Leave the poetry in what you make'?

Question: I'm reading Jason Fried's book Rework, and I don't understand what poetry means in these sentences:

Pare down to the essence, but don't remove the poetry.
Leave the poetry in what you make.
Comment: Here *poetry* is used to represent the art or craft, or more generally what is fine or magical about a thing.
Comment: @Robusto I'm suddenly reminded of Johnny Tillotson and *Poetry in Motion* from the pre-Beatles era of 1960s music; before Liverpool took over as the world capital of popular music. Historians of the genre have looked for influences upon the Fab Four. Buddy Holly was certainly one. Maybe Tillotson could have been another. Sorry if I digress. All this was before your time.
Answer: The word poetry is used figuratively in those quotes, presumably to suggest leaving (not removing) what is beautiful, elegant, layered and evocative.  Usability of poetry in that way is hinted at in explanations of what poetry is, in en.wikipedia's Poetry article and in
etymonline's Poetry entry.  From wikipedia:

Poetry is a form of literature that uses aesthetic and rhythmic  qualities of language — such as phonaesthetics, sound symbolism, and metre — to evoke meanings in addition to, or in place of, the prosaic ostensible meaning.
Answer: Without having read Fried's book, and not knowing the sentence's larger context, the prescription seems to recommend removing what is unnecessary while yet bringing "art" or "creativity" to the task at hand. For instance, whereas one does not generally wish for "poetry" in a set of instructions, some instructions are more successful than others. What accounts for the distinction? I would suggest that the author of the more successful set of instructions employed greater creativity. When Fried's advice is applied to poetry his meaning is less clear to me because, while my goal as a poet is certainly to avoid or remove anything unnecessary from my poetry--because what is unnecessary detracts from a poem's success--the act of poetry is, by nature, a creative or artistic endeavor, and cannot be composed by rote or without employing "art" or "creativity". Though, like a set of instructions, some poems are more successful (or fulfill their intent) than others. I believe that, in both examples, the distinction hinges upon the degree of art or creativity one brings to bear.
Answer: When people speak of something as having the quality of poetry that isn't poetry, they often juxtapose it with the word prosaic, which means 'prose like.' Prose was in earlier times considered second to the more refined poetry, but prose can in fact sometimes be very poetic in nature.
There are two ideas at work here - one is the idea of craftsmanship, and the other of something higher, of a poetic nature. The distinction becomes the notion that there is, in any creative process, two ways you can go - one is workmanlike, the other aspires to art. 'Leave the poetry in what you make' implies not discarding flashes of pure inspiration that convey a striving toward art in the process of working on a creative project.
Paul McCartney cites the example of telling John Lennon he would change the words, from the initial draft, of Hey Jude, 'the movement you need is on your shoulder,' because he thought they were too vague, or nonsense words.  Lennon said, 'No you won't, that's the best line!' Lennon was saving the poetic, not discarding it for the sake of clarity or better workmanship. He saw the poetry in those words, and McCartney kept them in. This is a very good example of what Fried is talking about in "Rework" in the quote above.


remove the word "out stock" in the label of product

Question: How we remove the word "out stock" in the label of product in the catalog, although haven't in the inventory this product.
Answer: Go to Catalog > Manage Products and search for the product you want to update.
In General Tab you'll find at the bottom of the list the custom stock status menu. Choose the right information.
I think with this you'll be able to select the good info for you.


Fast render animation?

Question: Hi I should make a video for a project of a hydroponic containers but the rendering time is over 30 hours ... how can I reduce it while maintaining good graphics ? Thanks !
Comment: Render without textures. That will reduce the time.You can also reduce fps, if it won't affect appearance of the final animation.
Answer: As a first you need to know what is your priority: time or quality? You can't have both.
This is very complex "problem" and need a lot of study. What is good in one situation may not be good in another.
Generally:
In "Sampling":

set Clamp to higher value
use "Branched Path Tracing" - check noise in every pass in compositor and adjust Samples by render pass.

In "Light Paths":

turn off caustic.
reduce light bounces.

In "Performance":

set Tilles according to your hardware (usually 64x64 for CPU, 256x256 for GPU).
tick "Persistent images" if your textures does not change in full length of animation
try using "Spatial Splits".

In Material node editor:
Use "Light path" for determine rays you don't need. For example disable shadow ray in glass can speed up render quite a lot.
I mentioned only most used features. There is not a general "golden rule" that work always and in every case. All settings depend of your scene and your preferences.
BTW: render animation about 30 hours is not unusual.
Comment: PS: one user here wrote very smart adage: There are quality, time and money. You can have two of them. My answer is about ratio between quality and time. If we add money, you can buy better HW or pay for render farm. There are no other way, because of technology limits and physical laws.
Comment: I have to second the 30 hours not being unusual.  I have had projects 5-6 minutes long take ~125 hours to render, and that's not even in Cycles!  I will also mention that for render farms, Sheep It is a free one that is community based, so the more your render other's projects, the higher priority your project has in the render queue (I've had 24x speedup on some projects, but of course it varies).
Answer: I found that setting the render style under Render -> Performance -> Tiles to Left to Right instead of Center cut my render time to 25 mins a frame, whereas before i was getting about 45-50 mins a frame for animation. I was also rendering at 720 by 1920 pixels, mainly because i was doing an animation test with only one character in frame at a time.

EDIT: Duarte Farrajota Ramos pointed out that only changing one setting shouldn't have such a large affect on the render time. When i looked through my settings and files that i had before and after the decreased amount of time, i realized that i had rendered still images of the animation before the final animated version was rendered, and had Persistant Images enabled.
Comment: Those are bold claims, are you sure you didn't change any other settings? I strongly doubt just changing tile direction would reduce render times by a magnitude of 50%

Fast render animation?


Two Humid rooms

Question: We built our home two years ago. Had trouble with the air conditioner, but a new company created zones and now the temps in each room are all withing 3 degrees of each other. However, we are fighting humidity in two of the rooms. Our den has one window and one french door which leads out to our deck. Attic is above it, bathroom, family room/fireplace next to it, guest bedroom below it. Our bedroom has double french doors that lead out to our front porch. The bedroom is over basement storage space with a dehumidifier which runs continuously. Has bathroom, hallway and foyer on the other sides. No leaks have been found. If we turn off the dehumidifier so it doesn't keep me awake, it is humid and smells musty the next morning. Same thing in the den. That dehumidifier must be running all of the time or it smells musty and feel icky. Any suggestions?
Comment: Hello, and welcome to Home Improvement. Where are you located? Are you sure there are no actual water leaks (e.g. roof, pipe, groundwater, etc)? And, you should probably [take our tour](//diy.stackexchange.com/tour) so you'll know how best to participate here.
Comment: We need more info: what kind of air conditioner, and does it feed every room in your house?  Are any of the rooms with high humidity being left with closed doors (which would lead to inability of the A/C to pump air into the room)?
Comment: Also -- do you have a layer of insulation on the basement ceiling? If not, the air in the basement is quite likely leaking into the rooms over it.
Answer: to me it sounds like your moisture problem is from the basement. You may not see leaks but to moisture concrete can be permeable. To find out if this is the source of moisture tape a trash bag to the floor for 24 hours. When you pull the bag the next day if you have moisture on the bag or this area of the slab looks wet you have found the source of the moisture.
I have had this same issue and found an epoxy floor coating drastically reduced the moisture. We still used a dehumidifier but it was only collecting a small amount of moisture compared to untreated slab. If you go this route you may have to wait until late summer so the ground water is less and the epoxy will bond. Or find one that will seal with moisture in the slab. I have done this on a full basement and a daylight basement and had great results on my own homes.
Answer: Air conditioned air is much dryer than outside air, because it is chilled down to about 50 degrees.  Cold air can't hold nearly as much moisture as warm air, so this "wrings the moisture out of it". By the time it mixes and rises to 75 degrees again, it is quite dry (for 75 degree air).

The sun is a huge fusion reactor. Every square metre of sunbeam has about 1000 watts of heat in it.  (100W per square foot). Some of it reflects, but this varies by the reflectivity (albedo) of the surface - pure white paint reflects 91%, most colors are quite poor, and a lot of roofs are practically black. Think about how big your house is from the sun's angle/perspective, subtract out reflectivity (which on a common roof will be nearly zero), and you see your house is absorbing many thousands of watts of energy.  Multiply by 3 for BTUs/hr.  This is far and away the heaviest load on your A/C. Humans, computers and even cooking pales by comparison.
Here's the important part: solar gain is not equal.  It punishes top floor, south and west facing rooms much more han others.
So, previously, your A/C distributed cooling evenly throughout the house.  This meant the dehumidification inherent in A/C was evenly distributed, however, the rooms suffering from solar gain were much hotter.  You had the A/C balanced, to put much more cooling on the rooms with solar gain, so the temperature equalized. Since the north/east/low rooms get no solar gain, they also get little A/C - and thus, little dehumidification.

Against that, you have a rather wet basement.  Concrete is porous.  Water can move through it.  Typically water which permeates through concrete immediately evaporates, so you don't see wet concrete - but if you lay a plastic sheet down on it, or set a cardboard box on it, that evaporation will stop and it will be seen under the plastic or damaging the box bottom.
Concrete has no tensile strength, so putting a coating on the inside of concrete is a lost cause.  Th concrete the paint is sticking to will just crumble, and the coating will be pushed off by water pressure.  The only place a barrier coat will work on a basement is on the outside, i.e. The plastic barrier you laid down before you poured the concrete, or a coating put on the walls before they are buried.   Nobody was thinking about that in the old days, so it wasn't done and it's impracticable to do now.
The best way I know to dry out a basement is to use French or Buckeye drains to remove the water from the soil outside the basement - i.e. Lower the water table locally around the basement.  It really helps to have land on a slope so you have somewhere for the water to go.
Comment: I have coated slabs in 2 of my own homes. The worst one went from almost 2 gallons a day to less than a quart with just the floor being painted so it is not a lost cause.
Comment: If it's a whole-house A/C system, then the dehumidification takes place at the heat exchanger, and operates on **all** the air pulled through the returns.  If the North/East rooms are receiving air from the A/C, they'll have the same low humidity as everywhere else.

Two Humid rooms


If Lord Voldemort had succeeded in killing Harry Potter, would he have died?

Question: Since Voldemort was resurrected using Harry's blood, part of him would be Harry. Therefore, if he had succeeded with Avada Kadavra and killed Harry, would he have inadvertently killed the blood of Harry within him and therefore broken the very spell that allowed him to be alive? If not, would it have weakened him in any way?
Comment: Welcome to the site! Tremendous first question!
Answer: Voldemort wasn't threatened in any way by using Avada Kedavra. Harry's blood helped give Voldemort a body but did not sustain him. The Resurrection Spell wasn't dependant on Harry being alive.
I think this is a fascinating and quite complex question. If I understand the question correctly, it's pondering whether Voldemort would have died had he succeeded in killing Harry, since he had used Harry's blood in his regeneration. My answer is no. If he had succeeded in killing Harry then Voldemort would have been unaffected by the fact that he took Harry's blood. The blood helped him regenerate; it did not sustain him. He needed it once and once only, not moment by moment. Harry's death would not have affected Voldemort's lifeforce since the spell which gave him a body had been performed many years beforehand.
Voldemort certainly tried to use Avada Kedavra on Harry on multiple occasions. The final confrontation between Voldemort and Harry at Hogwarts in Deathly Hallows (The Flaw in the Plan) referred to in the question is the only time they met where Voldemort actually had a chance of finishing Harry off (and vice versa, coincidentally). This is the only meeting between the pair where both characters are mortal. Before this moment, Voldemort was sustained by his Horcruxes and could not be killed. And Harry was sustained by the portion of soul embedded within him which tethered him to life whilst Voldemort lived.

"He took my blood," said Harry.
"Precisely!" said Dumbledore. "He took your blood and rebuilt his living body with it! Your blood in his veins, Harry, Lily's protection inside both of you! He tethered you to life while he lives!"
(Deathly Hallows, Chapter 35, King's Cross).

Note that Harry could not die as long as Voldemort lived. The same does not work in reverse. Voldemort did not depend on Harry's lifeforce in that way. Voldemort's immortality is dependent solely on his Horcruxes. He has no other hope of surviving death.
Of course, when he finally does use Avada Kedavra on Harry he comes down with a bad case of the jitters.

Voldemort seemed to be getting to his feet. Various Death Eaters were hurrying away from him, returning to the crowd lining the clearing. Bellatrix alone remained behind, kneeling beside Voldemort.
Harry closed his eyes and considered what he had seen. The Death Eaters had been huddled round Voldemort, who seemed to have fallen to the ground. Something had happened when he had hit Harry with the Killing Curse. Had Voldemort, too, collapsed? It seemed like it. And both of them had fallen briefly unconscious and both of them had now returned...
(Deathly Hallows, Chapter 36, The Flaw in the Plan).

So he falls unconscious whilst the portion of his soul within Harry dies. Then when Harry returns to consciousness Voldemort does too. This is the only damage Voldemort sustains. In all other regards he used Harry's blood as a one-time thing. Voldemort's body wasn't affected, whether Harry lived or died. All his blood does is give Voldemort a body.

"B-blood of the enemy...forcibly taken...you will...resurrect your foe."
(Goblet of Fire, Chapter 32, Flesh, Blood and Bone).

That's all the blood does. No more, no less.
Comment: If I were you, I would write that in *first person point of view*
Comment: @atayenel  The Dark Lord doesn't refer to Himself  in the first person
Comment: @atayenel Why does it matter?
Comment: @AniketChowdhury check the username of the answer owner.
Comment: @atayenel Ah! Perhaps
Answer: It actually weakened him. You can remember from the movie that he falls down after avada kedavra, and avada kedavra actually breaks the spell. But he still has two horcruxes with him(the snake and himself) which die after the Avada Kedavra, so no he won't die and his weakness is as same as losing a horcrux.

Voldemort seemed to be getting to his feet. [...] Bellatrix alone remained behind, kneeling beside Voldemort.
Harry Potter and the Deathly Hallows - The Flaw in the Plan

The clip from the last movie where Voldemort falls down
Comment: @TheDarkLord `If not, would it have weakened him in any way?`
Comment: I have edited the question to show the scene where he falls down in the movie. I can't add the quote as my books are not in english but **if someone has the quote from the book, please edit**.
Comment: He falls to the ground but that's not what the question is asking. It's asking about whether or not Voldemort would die if Harry did.
Comment: @atayenel. Fair enough but it's not the main question.


Why doesn't the Field Calculator work in ArcGis 10?

Question: When I try to calculate a field nothing happens.  I have always been able to just select the field, open the field calculator and type = and the new number. This is frustrating because the other GIS person can do it with no problem. I've tried several different tables, numeric and string fields.
I don't know Python and shouldn't need to use it just to change a field of numbers to a different number.  I have uninstalled ArcGis 10 and reinstalled it and SP1.
Comment: In most languages that initial "=" should produce a syntax error.
Comment: What whuber said. Try typing just the number, it should work so long as it's a numeric (long, float, double, etc.) field type.
Comment: Mtrombley--you said you got a solution. Can you post it?
Answer: Don't know if this applies to your situation, but there's a known bug in ArcGIS 10 when using a personal geodatabase (.mdb). If you use the field calculator, at least in an edit session, you have to save the edits on each field before you can use FC on another field.
Comment: It's been a year since this was last commented on, but I just ran into the same problem with the Field Calculator acting on a Shapefile. At first, nothing happened, and I finally realized that I needed to start an editing session first. Then it did work, only to obliterate all the values upon closing the editing session (with Save Changes). So I take it this has still not been dealt with.
Comment: Thanks - but this is a problem with shapefiles too. I just can't seem to get the field calculator to work. Been checking ESRI for help but none yet.
Comment: Mine works but only after sitting for about 2-3 mins
Comment: Mine looks like it is working then stops and nothing changes in the field.
Comment: Ithe problem is now fixed.  I finally asked ESRI support and they helped me.  Thanks so much to all that made suggestions.
Comment: What was the solution that ESRI provided? I have been dealing with ESRI support for over a week and the still can't solve the problem.
Answer: I had this problem too. I was using fields to calculate the value. Turned out that it didn't work with VB. Had to change to Python (and use ! by the Field names : !Field!)
Answer: I've run into issues with the Field Calculator not working as expected in ArcGIS 10 SP2 if your layer contains forward slashes in its name. For ex. if you name a layer "Parcels 9/14/11" you'll get an error message. Remove the slashes and it'll work. Figured this out through trial and error.
Answer: Because layer names double as SQL table names, you should never use punctuation besides underscores. Don't begin them with numbers, either, or use spaces.


Linux drains battery

Question: I have a Lenovo ThinkPad L412 with a non-overclocked i5 2nd gen, 4GB RAM, and a Radeon HDv545. Whenever I use Windows and have possibly battery intensive applications running, the battery still lasts a minimum of 2.5 hours.
However, I've noticed that when I switch to Linux (I'm currently using openSUSE with power management enabled) I notice a rapid drain in battery life. Linux automatically enables Bluetooth and I must make sure it's always off when I boot my system. Does Linux enable any other features I must turn off to conserve battery?
Why does Linux drain my battery and how do I overcome this?
Comment: You might want to have a look on https://01.org/powertop/
Answer: Torcellite, besides turning off Bluetooth, make sure you have CPUFreq or similar installed:
Package: cpufreqd
Priority: optional
Section: universe/admin
Description-en: fully configurable daemon for dynamic frequency and voltage scaling
 cpufreqd is meant to be a replacement of the speedstep applet you can find on
 some other OS, it monitors the system status and selects the most appropriate
 CPU level.  It is fully configurable and easily extensible through the many
 available plug-ins (more to come).
 Despite its name it can be used to control also the NForce2-Atxp1 voltage
 regulator and the core and memory clock for NVidia cards (see README.Debian).
 .
 You need a CPUFreq driver and either APM, ACPI (a recent version) or PMU
 enabled in your kernel in order for this daemon to work.
Homepage: http://sourceforge.net/projects/cpufreqd

Basically it would drop your CPU speed when your system is idle. This will be a huge power saver, and it will cool your CPU significantly as well.
The default setting in Debian/Ubuntu is on demand, which is the best setting for personal use.

Linux drains battery


Is it possible to have open source software such that binaries can only be distributed by the official builder?

Question: I want to build an Android ROM for myself and the ROM i picked has an "official maintainer". On the website it states that if a device has an "official maintainer", it is forbidden to share an "unofficial build". If someone builds and shares it, they will send a dmca request. is that possible with open source software?
Comment: Forbidden to share at all, or just forbidden to share on that website?
Comment: Does the ROM include the (GPLv2-licensed) Linux kernel?
Answer: Not according to the definition of open source we use here, which is the OSI's.  That requires that

The license shall not restrict any party from selling or giving away the software

and that

The license must allow modifications and derived works, and must allow them to be distributed under the same terms as the license of the original software

So if I can't modify the program to make my own "unofficial build", and then share it, we don't consider the software to be open source.  That said, the term "open source" isn't a restricted one, so anyone can distribute their software under any old hideous proprietary licence and yet claim it's "open source".   They can even start DMCA takedowns for violation of their proprietary licence, and still claim with a straight face that their software is open source.  To my mind, they're wrong, and their claim is a lie, but they're not forbidden from making it.
However, the idea that you can restrict the use of a trademarked name is much more normal, and acceptable within the free software community.  So a site that said, eg, "we distribute the official build of FooBarOSTM for the Google BazBar Developer Phone; if you distribute your own build for this phone, you must not call it FooBarOS" is fine.
Comment: Apparently, there is also a DMCA Takedown procedure for trademark violations.
Comment: @BartvanIngenSchenau I did not know that!  Thank you!


Translation of the Sator Square

Question: The wikipedia page on the Sator Square (https://en.wikipedia.org/wiki/Sator_Square) says that the sentence "SATOR AREPO TENET OPERA ROTAS" is a grammatical sentence and translates it as "The farmer Arepo uses a plough as a form of work".
However, I don't really get how they obtained the translation. The word "Arepo" is probably the name of the sower (even though it could have a different meaning), but that is not the main issue.
"Tenere" means "to hold" and "opera" is the accusative plural of "opus", that is "work". Also, "rotas" is the accusative plural of "rota", or "wheel". But I don't really know, which word relates to which. "Tenere" takes an accusative object, but there are 2 in the sentence. Could someone explain, or offer a better translation?
Comment: Could it perhaps hold the same meaning as, what you sow is what you will reap or what goes around comes around just as a wheel keeps turning. Perhaps was used as a curse in a ritual.
Answer: I think the intention is that opera is a singular ablative of the feminine noun opera, not a form of opus.
Among other things, opera means "work".
Starting with the other words, Sator Arepo tenet rotas means "the sower Arepo has/holds wheels".
Adding an ablative to describe circumstances, we get something like "the sower Arepo has/holds wheels for (the purpose of) work".
The translation "as a form of work" makes sense, too.
It is not more specific than "there is a work-related reason that the sower Arepo holds wheels", but that feels clumsy as a translation.
Interpreting a sower as a farmer is reasonable, but taking wheels to stand for a plough seems to be a farther fetch.
Having specifically a plough seems to come more from sator (what tools could one use in such work?) than rotas.
The translation is a little forced; the restriction of making the words go nicely in a square is too much for fluent language unless one has extraordinary luck.
Therefore one might have to be a little flexible or creative with grammar to make it work.
The square looks nice, though:

S A T O R
  A R E P O
  T E N E T
  O P E R A
  R O T A S
Comment: llmavirta: a primitive plough consisted of a blade between two wheels; "wheels" as a slang term for plough is easy to understand; but, not easy to prove. That the square violates grammar in order to "work" is well-known.
Comment: The 1938 interpretation in *S.Paul* by J Carcopino was very influential and probably fixed the association with Christianity AND with plough.
Comment: @tony Indeed, some flexibility and creativity is needed to parse the sentence. I agree that "wheels" could make a reasonable reference to a plough, but the dictionary entries I consulted for *rota* made no such mention. Therefore I thought the translation is more honest as "wheels". If the reader interprets the wheels as a plough or a carriage or something else, that is their judgement. I get the impression that the interpretation as a plough comes mainly from the word *sator*, as that work restricts the possible set of tools.
Comment: @Hugh Can you add that as a separate answer? That is crucial insight into how the square is usually translated.
Answer: The farmer Arepo possesses (tenet) the wheels (accusative-plural of "rota" ="rotas" [presumably a plough]) as the works (his job; noun "opus") opera (acc. pl.).
It may be that in order to make the square work a word was missed out e.g. "pro" = "for", as in "for (his) work", giving "pro opere"; which would have compromised the square.
Answer: The letters can be rearranged to spell "PaterNostre" from left to right and top to bottom sharing the "N".  The "A" and an "O" are left over which are a reference to the Greek letters for Alpha and Omega. The Latin words were simply what could be created from the available letters and don't mean anything other than the words themselves.
Comment: Isn't it "pater noster", not "pater nostras"? There are four Es in the square and only two As.
Comment: Welcome to the site! Could you illustrate this with a picture or something? I can't quite follow your description of how to read *pater noster* and have A and O left over.
Comment: The paternoster interpretation is an invention of the 1920s and doesn't show up in the Christian traditions that claim the Sator Square. It's not clear that the Sator Square *was* originally Christian.
Answer: 'A' - from/away
Repo, sneak, creep or crawl,
Earliest version known begins with rotas.
The wheel away I creep holds the works of the farmer or as some like to translate sator as father
Thus
The wheel away I creep holds the works 'of' the father
Or as a sator square
The father the works holds away I crawl the wheel.
But I may also be wrong.
Comment: *Ab-* as a verbal prefix only loses its *b* when it precedes *m* or *v*. Neither *arepo* nor *abrepo* is attested historically, and it wouldn't really make any grammatical sense either. (The first word can't be *rotas* without also switching *arepo* and *opera*, or you'd have *ratos orepa tenet apero sotar* vertically.)

Translation of the Sator Square


Can I do an impdp with a file on my local computer

Question: I was given a dump file which is currently on my local computer.  I want to import this to our Oracle 11G DB which is hosted on a server.  Do I need to move this file to the server to do the impdp or is there a way that I can do the impdp while referencing that the file is on my local PC?
Answer: Should be possible, provided the user that the DB service is running as can access the file share.
If the above is true, then you would have to create the directory object:
create directory MYIMPORTDIR as '\\mycomp\mydir';

then run your impdp like:
impdp [username]/[pass] directory=MYIMPORTDIR dumpfile=expdat_1234.dat

Answer: You need to move the dump-file to an area where the database has access to it referenced inside the database as a directory object. You can run impdp from your local computer.


How does FIFA 14 selects a player when manually changing the control?

Question: I usually suffer when there is a pair of players running toward the ball and one of them is more suitable to get the ball but FIFA chooses the other one... On which criteria does FIFA 14 choose the next selected player?
Comment: I "think" it's closest in the direction the ball is moving. I do know you can adjust how it changes the players to your liking.
Comment: If one of the players is in an offside position, he appears to always run back to play the ball rather than leaving it for the onside player.
Answer: When you have the ball possession:

Air pass selects the closest player depending on the power of the pass.
i.e if you have two players standing in the same line and you play an air pass, long pressing the air pass button plays it to the who is at a farther distance where as normal press and release plays it to the nearer player and the appropriate player gets selected.
Same goes for short pass and long pass(the ground passes), but here the direction is of more importance.
When you don't have ball possession and you're tackling press the player run/modifier key and the direction key where the player you want to select is positioned with respect to the current selected player.


How can I visually represent the concepts "invincible" or "winning without fighting"?

Question: If you were asked to represent "invincible" or "winning without fighting" in pictures, how would you do it?
Comment: Maybe add some more context and detail? Like a hint what kind of a client/project you are looking to do this, what is out of bounds etc...
Answer: For invincible, perhaps a projectile richoceting off some sort of barrier and for winning without fighting I might use a white dove wearing a gold medal
Comment: haha white dove + gold medal = hilarious
Answer: It's a bird, it's a plane, no, it's.. SUPERMAN!
Go for something bold and simple, like the Superman logo! Although this specific logo may have certain associations with invincibility built up over many decades, the imagery of bold logos also has the same, and will inspire the message you're trying to get through.
Also for winning without fighting, personally I'd go the Asian route and try to evoke the martial arts way of looking at it, perhaps with an Asian style font or architecture in the logo/picture.
Although this might end up looking like some brave Noodle shop.. But this is what I'd go for first if given such words to work with :)
Hope that helps some :)
Comment: Superman is obvious, but also comes with major, probably insurmountable, copyright issues.
Comment: A generic superhero illustration could work well, though.
Comment: @Phillip regan: Yes, I would never condone the use of the actual superman logo, that'd just be setting yourself up for a lawsuit, but my advice was more to take inspiration from it :)
Answer: For invincible, a piece of armor or a robot. Anything chromed.
For winning without fighting, a robed man (gives a nod to eastern philosophy, Ghandi, Jesus, less aggressive martial arts, gurus, etc).
Answer: Chess pieces? The King? A bit cliché but you can infer winning without fighting as it were. Or not.
Answer: A little flag on a mountain top, or the highest step on the podium. Those represent winning and a great feeling of invincibility. I see it as winning a competition like crossing the finish line on first. To me, winning and be invincible means to be the first... I hardly see how you can win without «fighting» at least against yourself, in a non violent way though...


How to create a horizontally-centered DIV which has a minimum width but can stretch out as needed?

Question: I have a site layout with a fixed header, a fixed footer and a central content section; this is a sample HTML:

        Header Text

        Content Text

        Footer Text

And this is my current CSS:
.Header
{
    border:1px solid black;
    height:50px;
    left:0;
    margin-left:auto;
    margin-right:auto;
    position:fixed;
    right:0;
    top:0;
    width:1000px;
}

.Content
{
    border:1px solid black;
    bottom:60px;
    left:0;
    overflow:auto;
    position:fixed;
    right:0;
    top:60px;
}

.Footer
{
    border:1px solid black;
    bottom:0;
    height:50px;
    left:0;
    margin-left:auto;
    margin-right:auto;
    position:fixed;
    right:0;
    width:1000px;
}

This works well for the header and footer, which have a fixed width; however, I can't find a way to make the content section stick in the center of the screen, unless I give it a fixed width too.
I need the content section to have a minimum size equal to the header and footer, but sometimes it needs to display wider content, thus I also need it to be able to stretch horizontally if needed, up to the full browser width; in all situations, it has to stay horizontally centered.
I tried various combinations of positioning parameters (including min-width,margin-left,margin-right,width:auto and so on), but nothing seems to work unless I give the DIV a fixed width too; but then, when wider content is displayed, this will force horizontal scrolling even if the browser window is actually large enough to display all of it.
How can this be accomplished?
Answer: Give the content a min-width and center it with margin
.Content {
  display: block;
  position: relative;
  min-width: 1000px;
  margin: 0 auto;
}

Here is a fiddle
Comment: Doesn't work, with this it always stretches to the full browser width, even if the content is small; I need it to stay at the minimum width unless the content is actually wider than that.


Clustering vs. transactional replication vs. availability groups

Question: Assuming you need to make sure your application that relies on SQL Server 2012 as its database backend is available around the clock, even if one server machine fails.
As a developer and not a DBA, I am struggling to understand when to use which scenario for my failover / high availability:

Two (or more) servers in a Windows Failover cluster, SQL Server as a clustered instance
Two (or more) SQL Server instances that are kept up to date with transactional replication
Two (or more) SQL Servers in a SQL Server Availability Group, configured in a synchronous commit mode

Which of each of those scenarios works for what kind of workload, and what kind of failure / outage can be handled by those scenarios? Are they even comparable / exchangable?
Answer: The way I always like to visualize high availability solutions is the following:
SQL Server Failover Cluster Instance (FCI)
What is highly available?  The entire instance.  That includes all server-objects (logins, SQL Server Agent jobs, etc.).  This also includes databases and their containing entities.  It's a great solution for highly available SQL Server instances, because that is going to be the level of containment with this given solution.
What about reporting?  None, NULL, nonexistent.  A failover cluster instance has an active node delivering the cluster group containing the instance, VNN, etc. and all other nodes are passive, sitting idle (as far as the current cluster group is concerned) and waiting for a failover.
What happens when there is failover?  The downtime for an FCI is going to be determined by the amount of time that the passive node takes to grab the cluster resource and bring the SQL Server instance in a running state.  This is typically minimal in time.
Any client abstraction?  Yes, this is going to be innately built in with the virtual network name for the failover cluster instance.  This will always point to the active node that is currently delivering the SQL Server cluster resource.
AlwaysOn Availability Groups
What is highly available?  An availability group is going to be the logical containment of high availability here, whereas an availability group consists of a number of databases and a virtual network name (the listener, an optional cluster resource).  It is worth noting that server objects such as logins and SQL Server Agent jobs will not be part of the HA solution, and special consideration needs to be taken to ensure that these are properly implemented with an availability group.  Not an overly burdening requirement, but needs to be cared for.
What about reporting? This is a great solution for reporting, although I probably wouldn't use a synchronous replica as my reporting instance.  There are two commit relationships, synchronous and asynchronous.  In my opinion and from what I've seen in practice, is that your synchronous secondary replica is there waiting for a disaster.  Think of it as that replica that's ready to take a no-data-loss failover in the event of an issue.  Then there are asynchronous replicas that can handle that reporting workload.  You aren't using this replica as the aforementioned solution, but moreso for things like reporting.  Reporting workloads can be pointed to this replica (either directly, or indirectly through read-only routing via the listener).
What happens when there is failover?  For a synchronous commit secondary replica that is paired with automatic failover, this will be the replica role state change from SECONDARY_NORMAL to PRIMARY_NORMAL.  In order for there to be automatic failover, you need to have a synchronous secondary replica that is currently synchronized, and what's implemented is the Flexible Failover Policy to determine when in fact this failover should occur.  That policy is indeed configurable.
Any client abstraction?  Yes, you could optionally configure an AlwaysOn Availability Group listener.  This is basically just a virtual network name (can be seen through WSFC as a cluster resource in the AG's cluster group) that points to the current primary replica.  This is a key part of shifting your reporting workload around, as well as setting up a read-only routing list on any servers that you want to redirect ReadOnly traffic (this is set through the connection string, with the .NET Framework Provider for SQL Server, this will be the Application Intent parameter, set to ReadOnly).  You would also need to set a read-only routing URL for each replica that you want to receive this reporting workload while in the secondary replica role.
Transactional Replication
What is highly available? This is arguable, but I'm going to say nothing.  I don't see replication as a high availability solution whatsoever.  Yes, data modifications are being pushed to subscribers but we're talking at the publication/article level.  This is going to be a subset of the data (could include all the data, but that won't be enforced.  I.e. you create a new table in the publisher database, and that will not automatically be pushed to the subscribers).  As far as HA goes, this is bottom-of-the-barrel and I will not group it in there with a rock-solid HA solution.
What about reporting?  A great solution for reporting on a subset of data, no question about that.  If you have a 1 TB database that is highly transactional and you want to keep that reporting workload off the OLTP database, transactional replication is a great way to push a subset of data to a subscriber (or subscribers) for the reporting workload.  What happens if out of that 1 TB of data your reporting workload is only about 50 GB?  This is a smart solution, and relatively configurable to meet your business needs.
Summary
What it boils down to are a handful of questions that need to be answered (partly by the business):

What needs to be highly available?
What does the SLA dictate for HA/DR?
What kind of reporting will be taking place and what latencies are acceptable?
What do we need to handle with geographically dispersed HA? (storage replication is expensive, but a must with an FCI.  AGs don't require shared storage from standalone instances, and you could use a file share witness for quorum potentially eliminating the need for shared storage)
Comment: @marc_s Glad to help! You are correct in your understanding about an FCI, provided that the WSFC itself doesn't go down (i.e. loses quorum) and that there is a passive node able to take the SQL Server cluster resource group in the event of failover.  As for an AlwaysOn AG, yes there is possible automatic failover.  I've edited my answer to include that information, but basically you need a synchronized secondary replica configured for automatic failover.  You could have a manual failover as well with no data loss to a synchronized second replica.
Comment: Thanks for a great answer, Thomas! So if I understand correctly, FCI would automatically switch over to a "hot standby" server if the main machine goes down - right? What about AlwaysOn? Does that offer some kind of automatic "failover", too, or is it just a secondary copy of the database, but some admin needs to manually switch over, in case of a failure?
Comment: @ThomasStringer - this is very helpful.  Thank you! I wonder if you could address making schema changes for each of three options.  We set up Transactional Replication only to find out that making schema changes is *really* hard on the publisher. What about AlwaysOn?  Would we run into the same issue here as well?
Answer:
two (or more) servers in a Windows Failover cluster, SQL Server as a
  clustered instance

What Kind of workload? "It depends" - but seriously, this is useful for an online application where you need to have local in data center High Availability. You are protected against a failure of one machine, or of one operating system. The logins, jobs, new databases, maintenance, etc. all are automatically kept in sync by the fact that it is a cluster with two nodes that are exactly the same sharing the same storage so they have all the same system databases. Very fast failover, but there is still a hiccup that looks like a SQL Server restart when the failover occurs.
Cons/Concerns - Single point of failure is your storage and all of it's components. SAN vendors always say "SANs don't fail" but there are lot of moving parts in a storage area network and as I blogged about here, they can. Also - you are paying for a secondary server that can't do anything but hang around and wait.. Now you can do Active/Active/Multi-Node and have two active instances that can failover in either direction and use the second node.
Automatic Failover? The "most" automatic. No witness needed, it's a cluster. This is the job of a cluster, to make it as seamless as possible. Now with any of these, when a failover happens you will "feel" it, because SQL has to start up or connections have to point. Here when it happens, you'll basically feel like a restart of SQL, DBs come back up and run recovery/etc.

If I have a client say "I want to be fully up with all databases, all logins, etc" in a High Availability environment in my local data center because I have an incredibly low tolerance for downtime I would consider Failover Cluster Instances (though the last option you mention is a strong contender, save for having to do some management overhead). I would probably do a local FCI and an AG async secondary to protect against site failure or SAN failure.

two (or more) SQL Server instances that are kept up to date with
  transactional replication

What Kind of workload? I honestly wouldn't go here for a lot of cases of a need for High Availability or Disaster Recovery as a first choice. Not in SQL 2012 for sure. But basically this is good if you had to go to a data center that wasn't close, you couldn't use an AG (maybe a domain issue preventing you from using the windows cluster required for the AG), perhaps you wanted to be in SQL Server standard which can do replication, but not AGs but you still wanted to have the ability to read on the secondary side and be asynchronous.
Cons/Concerns - It's replication. It has overhead, it can get out of sync, you can develop problems with performance on the source side, etc.
Automatic Failover - No. You have to manage it yourself. Either through CNAMEs that point to one or the other, and you could theoretically write your own process to do this, but out of the box? Note here.

two (or more) SQL Servers in a SQL Server Availability Group, configured
  in a synchronous commit mode

This is what I've been helping people implement more and more lately, though sometimes I still go to clustering.

What Kind of Workload? This is great when I have a manageable set of databases to keep in sync, and the resources and time to make sure that jobs, logins, new databases, etc stay in sync (though the team at SQL Skills have built a great add in to automate some of this for you making it even stronger of an option). I like this when I want to keep things completely separate. I am protecting against hardware issues, OS issues, SQL installation issues, patching issues and SAN/Storage issues. I also get the benefit of the ability to have a secondary (If I want to pay an enterprise license for it) to be an active secondary that I can read from, take backups on, etc. Plus in the future I can add a third secondary that is asynchronous at a remote site and have failover/DR.
Cons/Concerns Licensing, maximum number of replicas, licensing costs to take advantage of some of the biggest benefit (active secondary), requires enterprise, requires twice as much storage than clustering.
Automatic Failover - Yes. This can occur with a witness setup, and your app developers can connect to the listener instead of a node so the failover happens with where the listener points and you should be good there. So yes you can do that here - and should - but of course you should test it well.

Summary
HA and DR are different. And these technologies help provide pieces of either. High Availability means (to me) that you can quickly recover if something bad happens to one machine, you are up with a short Recovery Point Objective and Recovery Time Objective. That is clustering and a synchronous AG.
Disaster Recovery is "you can get up when you have a failure even in your HA solution. To me that can be AGs when you go to another data center, mirroring or even replication.
Comment: @marc_s clustering(FCI) and AG are not mutually exclusive. You can have Node1 and Node2 clustered in same datacenter(sharing storage) and do AG to a third stand alone instance in remote data center(in same cluster but not sharing storage)
Comment: Great stuff - thanks! So given the choice between failover clustering and AG - which do you choose when? Clustering seems to be more mature (been around longer), but AG seems to offer more flexibility (in that the "secondary" can be used for e.g. reporting etc.). So when and why would you still use failover clustering then?
Comment: It depends but where I see it more is someone is either more comfortable with it, there is a lot of transition on the server and they just want to cover (for HA) Every database, every job, etc. It's "easier" in that regard.. And then for those folks they may want to use an Async AG to a DR site for that extra DR protection. I see it there. I'll see it if they passed out when they see Enterprise licensing prices and don't need features but still want HA - Clustering a single instance works in standard with FCI, etc.
Comment: I feel compelled to mention that if you have a local active-passive FCI and a remote passive server using AlwaysOn you will have 2 passive servers and will have to pay for a full license for one of them. :(
Answer: It is also important to consider what is shared.
Failover Clustering uses two or more server nodes sharing one disk array. If the disk array goes down then you lose service, regardless of how many server nodes there are. If the server room where that disk array is located catches fire or floods then you lose service.
AlwaysOn Availability Groups and Database Mirroring are a "shared nothing" clustering technology. The database is present on multiple disk arrays in multiple servers. If you have good network links then the multiple serves can be in multiple server rooms, protecting you against fires and floods.
Answer: Just for completeness, there is the option of using plain old mirroring.  The advantages here include having two copies of the database without the complexity of using Availability Groups, and without needing shared storage for Failover Clustering.  Disadvantage, although slight, is mirroring is deprecated.
Failover times with mirroring are on the order of 10 seconds, although the application code needs to be able to retry any transactions that are occurring at the time of failover.
Comment: +1 for bringing it up separately and specifically :)

That said - yes you can certainly argue that mirroring is less complex and it doesn't have the cluster requirements, the domain requirements that come with that, etc. that AGs have. So there is still certainly complexity, and a need to keep logins, jobs, new databases, etc. in sync like with AGs. So it has some of those same costs and, like you said, is deprecated. But I still setup and deploy new mirrors today for folks :)


asp.net interact with .mdf files

Question: How can I interact with a .mdf or.ldf file? When I say interact, I mean view/edit fields, records on the desktop.
Its inside a websites App_Data folder.
Answer: These are SQL Server files. MDF is the data file and LDF is the log file.
Basically, I think your web site is using SQL Server for it's data storage, and the database is stored in that APP_DATA folder.
Usually SQL Server installations come with Management Studio or Enterprise Manager (called Client Tools) unless the administrator chose not to install it on that machine.
Look under START / Programs / Microsoft SQL Server 2000/2005/2008.  Then look for Enterprise Manager or SQL Server Management Studio.
In the ServerName, just put a period or dot, and use Windows Authentication to connect. If that does not work, you will need a username and password to connect to the database. You should be able to find either in the configuration files of the web project, or the website code.
If the Tools are not installed, then you will need the installation CD / DVD to install the client tools.
Alternately, you can install Tools (only Tools, you don't need the database engine) from SQL Express Edition from http://www.microsoft.com/express/sql/default.aspx?wa=wsignin1.0 on a different machine and access the database from there.
Answer: To "interact" with an mdf file, you need to attach the database to an MS SQL Server.
After located the mdf file you can use follwing stored procedures:
sp_attach_db
ex:
EXEC sp_attach_db

      @dbname = N'MyDatabase',

      @filename1 = N'D:\DataFiles\MyDatabase_Data.mdf',

      @filename2 = N'E:\LogFiles\MyDatabase_Log.ldf';

Wehn DB is attached you can connect with your connection string and do classical operations on database.
You can detach your DB with sp_detach_db
ex:
EXEC sp_detach_db

      @dbname = N'MyDatabase';

MSDN sample : http://msdn.microsoft.com/fr-fr/library/ms179877.aspx
Answer: Use linq2sql to access the mdf.
There's an example in an answer here

asp.net interact with .mdf files


how to visit every computer on the network and modify the hosts file in windows xp

Question: We need to append a line to the hosts file for every user on our network. I have admin privileges, but don't know the first thing about windows scripting. Can someone point me in the right direction on this? I don't have the list of all the machine names, so I'd prefer a script that would discover all the machines on the network and do the update.
Answer: I realize the question is about modifying the host file via vbscript.
Would it be more effective to create a new internal DNS entry for the hostname you're trying to resolve? If you truly want EVERY user/machine on the network to see this change, perhaps this would be easier?

Adding DNS Services to your Windows 2003 Server at Petri.
The Microsoft walkthrough on Installing and Configuring DNS
Comment: "How do I do that on windows server 2003" - that's a bit of a "plz send teh codes". You will need to plan and research it. It's not just as simple as installing the DNS and off you go, but it's likely to be a simpler, better and easier to maintain solution than editing dozens of hosts files.
Comment: that's a good idea.  How do I do that on windows server 2003?
Comment: Just have to make sure that you would have some sort of sanity checking.  I usually want to account for the systems having the change made afterwords.
Comment: IF you have a Windows domain that is newer than NT4 then you already have to have DNS, it's a fundamental part of an Active Directory Domain. There are very few legitimate reasons for taking the host file route when you already have a DNS infrastructure that you control.
Answer: If you've got a domain, simply use the login script (group policy object) method others suggest and tell everyone to reboot.
Better: add the entry to your local DNS server instead.
Failing that, VBScript still isn't required. Consider a batch file with lines like this:
<code>echo 10.20.30.40 fishsticks >> \\hostname\c$\windows\system32\drivers\etc\hosts
</code>
An aside: You don't sound organized.
It isn't the problem you asked about, but it's the problem you really should be fixing first.
Get a spreadsheet out and count the machines if you have to.
Answer: Don't use "HOSTS" files. Period. Any "solution" that users HOSTS files is just creating a new problem.
I presume you've got an Active Directory domain. Fire up the "DNS Management" management console on a domain controller (which, odds are, is also one of your DNS servers), open the server node, the "Forward Lookup Zones" node, and highlight the zone that corresponds to your Active Directory domain. Click "Action" (in the menu) and "New Host". Enter the hostname and IP address of the new host.
Within 5 minutes the clients of that DNS server will be able to resolve that hostname.
Presumably you're a sysadmin. It sounds like you need to spend some time learning about DNS, because it will save you a lot of headaches in the future.
Answer: Puppet is a configuration management solution that says it supports windows :)
Answer: Short of a tool like SCCM you are not going to be able to discover an exact listing of machines on the network.
First task will be finding the hosts:

If you can use a startup script in a GPO this is easy
If not, then if you are not too skillful with scripting, I would do a laymans approach.  First use a tool like angryIP to get a listing of all of the windows desktops you want to modify the tool with

Then...

If you have the GPO, I would just write a batch file that has something like  <code> echo 192.168.0.2 hostname > %systemroot%\system32\drivers\etc\hosts.  </code>
If you don't have a GPO, look at PStools (specifically PSexec). Copy the hostnames discovered with angryIP into a hostfile and then use psexec to run the command with the hostname file as the array it would look something like this psexec @hostfile "echo 192.168.0.2 hostname > %systemroot%\system32\drivers\etc\hosts"
Answer: Maybe, it's time to setup local DNS there? :)
Answer: Agreed at the recommendation to look at DNS, but let's not forget that there might be some horrible old legacy apps that still require hosts name resolution on this network.
Answer: If you are using a gateway server then modify the hosts there and all is well. Other wise if your Router(cisco/juniper) allow for a text version of the hosts file put it there. That will circumvent having to put a host file on every client.


Why is the disney logo in Hercules the cgi intro while the Emperor's New Groove uses older logo?

Question: I was re-watching The Emperor's New Groove and noticed that it used the old Disney castle intro where the castle is filled in on a blue background from the top down.  This is different than the Disney castle intro to Hercules which uses the CGI landscape castle.  I checked and found Hercules came out 3 years before Emperor's New Groove and almost a decade before that intro was used on another movie for the first time.   Did Disney change the intro to Hercules when it was released on blu-ray or was the CGI logo first introduced with this movie?
Comment: Because they choose which logo to use for each movie. Just depends on how they feel.
Comment: I'm totally confident - though I have no evidence other than my memory - that when *Hercules* was released in 1997, it used the older Disney logo.  They must have changed this for the reissue.
Comment: This would be an easy check if someone has a VHS copy of Hercules (and a VCR to play the tape).
Answer: This page documents the evolution of the intro logo. The full cgi logo was first used in 2006 with Pirates of the Caribbean: Dead Man's Chest. Further down under the 2011 variant it says this:

Later reissues of classic Disney movies released on DVD and Blu-ray
began using this or the original 2006 variant.

So Hercules originally used the 2D version, but was later changed for rereleases.