Abstract

A programmable gate array comprising: a plurality of logic modules, each logic module having at least one output coupled to an isolation transistor, each isolation transistor
having a gate coupled to a respective one of the logic modules; and a plurality of isolation transistors, each isolation transistor having a gate coupled to a respective one of the logic modules, the plurality of isolation transistors being coupled to the plurality of logic modules such that the plurality of isolation transistors are controlled by the plurality of logic modules