FPGA-based object detection using classification circuits
In the machine learning area, classification is a process of mapping a new observation to a certain category. Classifiers which implement classification algorithms have been studied widely over the past decades. Traditional classifiers are based on algorithms such as SVM and neural nets, and are usually run by software on CPUs which cause the system to suffer low performance and high power consumption. Although GPUs can be used to accelerate the computation of some classifiers, its high power consumption prevents the technology from being implemented on portable devices such as embedded systems or wearable hardware. To make a lightweight classification system, classifiers should be able to run on a more compact hardware system instead of a group of CPUs/GPUs, and classifiers themselves should be optimized to fit that hardware. In this thesis, we explore the implementation of a novel classifier on a FPGA-based hardware platform. The classifier, devised by Alain Tapp (Université de Montréal), is based on a large amount of look-up tables that form tree-structured circuits to do classification tasks. The FPGA appears to be a tailor-made component to implement this classifier with its rich resources of look-up tables and the highly parallel architecture. Our work shows that a single FPGA can implement multiple classifiers to do classification on high definition images at a very high speed.
FPGA Machine learning Classifier Look-up tables