BACKGROUND OF THE DISCLOSURE

Field of the Disclosure

Embodiments of the present disclosure generally relate to applying LDPC coding to memory cells with an arbitrary number of levels.

Description of the Related Art

Memory devices, such as NAND memory cells, are multi-state objects that store binary information. To simplify binary arithmetic, the number of levels in a cell is chosen as an integer power of 2 (e.g., 2, 4, 8, 16, etc.). Efforts have been made to create cells with any number of levels so that non-integer power of 2 number of cell levels can be achieved.

For such a non-integer power of 2 situation, user data encoding can be simple by changing the user database from 2-ary to L-ary where L is the number of cell levels. The user data is thus easily encoded. However, the LDPC parity calculation is binary, not non-integer power of 2. Thus, LDPC parity information presents a problem in a non-integer power of 2 number of cell levels situation.

Because the LDPC parity calculation is binary, there is a problem of how to write binary information in an L-level cell without encoding and loosing data capacity. The LDPC parity for a non-integer power of 2 number of cell levels situation requires additional storage capacity than would be needed in an integer power of 2 number of cell levels situation. Alternatively, the LDPC parity data can be encoded, which is not desirable.

Therefore, there is a need in the art for a manner of storing LDPC parity data for non-integer power of 2 number of cell levels without encoding the LDPC parity data or utilizing too much storage capacity.

SUMMARY OF THE DISCLOSURE

The present disclosure generally relates to applying LDPC coding to memory cells with an arbitrary number of levels. Modulation code is applied to a first portion of user bits. The coded user data is stored in a first modulation block. Parity bits are then generated for the first portion of user bits. The parity bits are then stored in a second modulation block different from the first modulation block. Modulation code is then applied to a second portion of user bits which are stored in the second modulation block. Parity bits are then generated for the second portion of user bits and stored in a third modulation block. The parity bits are thus embedded in a separate modulation block from the modulation block where the user data is stored.

In one embodiment, a data storage device comprises: one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller is configured to: apply modulation coding to a first set of user data; write the modulated first set of user data to a first modulation block; generate first parity data for the modulated first set of user data; and write the first parity data to a second modulation block.

In another embodiment, a data storage device comprises: one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller is configured to: generate parity data for a first set of modulated user data; and embed the parity data with a second set of modulated user data that is different from the first set of modulated user data.

In another embodiment, a data storage device comprises: one or more memory devices; means to store modulated first user data; and means to store parity data for the modulated first user data in a location different than the modulated first user data.

