TECHNICAL FIELD

The subject matter disclosed herein is directed generally to electronic circuitry and more particularly to semiconducting dies upon which functional circuits are fabricated.

BACKGROUND

Integrated circuit (IC) packages are small blocks of semiconducting material upon which semiconducting dies and/or functional circuits are fabricated, e.g., via lithography, additive manufacturing, etc. For example, when a functional circuit is built on the active side of the package, remnant internal stresses will be induced in the substrate causing warping in the direction of the active layer. Warping of up to 25% of the package thickness has been observed. Warping in the package or its components may lead to further manufacturability issues, e.g., during lithography or spin-on operations. Additionally, warped packages integrated into end products may experience opens, head-on-pillow defects, and other die interconnect issues which may lead to electrical failures. Finally, package warping may complicate or prevent z-height miniaturization efforts by requiring mechanical designs to accommodate the warping. There is currently no method for addressing these challenges via the flattening of warped packages.

SUMMARY

An integrated circuit (IC) package is disclosed. In embodiments, the IC package includes one or more electronic substrate layers having an active side (e.g., face) and an inactive side opposite the active side, one or more semiconducting dies and/or functional circuitry fabricated on the active side. The IC package is subject to a degree of inherent warping toward the active side, the warping associated with the fabrication of the die and functional circuitry. To induce a desired degree of counter-warping of the electronic substrates toward the inactive side, the inactive side (e.g., face) may have one or more corrective layers deposited thereon via thin film deposition (TFD) instrumentation and techniques.

A method for induced warping of an IC package or its components is also disclosed. In embodiments, the method includes determining a degree of inherent warping toward an active side of an electronic substrate of the IC package, the inherent warping associated with the fabrication of semiconducting die/s and functional circuitry upon the active side. The method includes determining a degree of desired induced warping stress (e.g., counter-warping) toward an inactive side of the electronic substrate, the inactive side opposite the active side. The method includes implementing the desired induced warping stress by applying, via thin film deposition (TFD), at least one corrective layer to the inactive side.

This Summary is provided solely as an introduction to subject matter that is fully described in the Detailed Description and Drawings. The Summary should not be considered to describe essential features nor be used to determine the scope of the Claims. Moreover, it is to be understood that both the foregoing Summary and the following Detailed Description are example and explanatory only and are not necessarily restrictive of the subject matter claimed.

