CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 U.S.C. § 119(a) of European Application No. 19175165.0 filed May 17, 2019 the contents of which are incorporated by reference herein in their entirety.

BACKGROUND OF THE DISCLOSURE

1. Field of the Disclosure

The present disclosure relates to a cascode semiconductor device and associated method of manufacture. In particular, this disclosure relates to a cascode arrangement of a depletion mode transistor die with an enhancement mode transistor die, and an associated method of assembling such an arrangement.

2. Description of the Related Art

Cascode arrangements of transistors are well known, in particular for controlling normally on (or depletion mode), at zero gate-source voltage, high voltage semiconductor devices. Single package cascode arrangements can be used in switched mode applications, especially in power supplies, where efficient energy switching is required. Typically, as illustrated inFIGS.1aand1bthe cascode arrangement100may comprise a normally off (or enhancement mode) low voltage device102is placed in series with a high voltage depletion mode device104, by the common connection of a gate of the high voltage device104to a source of the low voltage device102, and a drain of the low voltage device102to the source of the high voltage device104. The high voltage depletion mode device104can thus be switched off when the drain source voltage of the low voltage enhancement mode device102reaches the threshold voltage of the high voltage device104. The addition of a low voltage device enhancement mode device102in a cascode arrangement with the high voltage depletion mode device104therefore allows the normally on high voltage device to operate as a normally off, or enhancement mode device.

Typically, the high voltage depletion mode device104may be a Gallium Nitride (GaN) or Silicon Carbide (SiC) based JFET or HEMT, and the low voltage enhancement mode device102may be a silicon (Si) based MOSFET and both the high and low voltage device are integrated into a single semiconductor device package100.

As shown in more detail inFIG.1a, where both high and low voltage devices are integrated into a single semiconductor device package100, it is common to mount the high voltage device104on to die pad110. The low voltage device102is then mounted, or stacked, on the high voltage device104. However, such mounting requires the use of an insulating material106between the die pad110and the high voltage device104to electrically insulate the high voltage device104from the die pad110. The insulating material106may be a ceramic material. Ceramic based insulators are preferred over glass or porcelain insulators because they are more robust at high operating temperatures. In addition ceramic is also compatible with copper deposition processes to form so-called direct bond plated copper (DBPC) substrates.

Typically the insulating material106may be soldered108to the die pad110and likewise the high voltage device104may be soldered to the die pad110. Drain and source connections112may made to the high voltage104device using appropriate wire bonds. Likewise, the carrier110may be electrically connected to the high voltage device104or the low voltage device102by way of electrical vias (not illustrated) through the insulating material106to the die pad110.

Furthermore, the above mentioned cascode device connections between the respective gate, source and drain of the high and low voltage devices102,104are currently formed by wire bonds114,116to achieve the cascode configuration ofFIG.1b. Such wire bond connections suffer from the problem of DC power and switching losses due to the inductance effects in the wires during operation. Using wire-bonded connections can result in higher parasitic inductances and capacitances, which can result in so-called gate bounce. Gate bounce is a false turn on mechanism where during high frequency switching operation, the high voltage device is switched to an “on” state when it should be in an “off” state. Moreover, device resistances such as RDson may increase and wire connections can be subject to failure particularly at high voltage operation of the high voltage device.

First and second cascode arrangements100,100′, as shown in the circuit diagram ofFIG.1b, may be arranged in a half-bridge configuration as shown in the circuit diagram ofFIG.1c. In the half bridge arrangement the drain of the second cascode100′ arrangement is connected to the source terminal, common with the gate of the high voltage device104, of the low voltage device102.

Yet further, the known arrangements described above are complex to manufacture and require large package sizes to accommodate the multiple wire bonds and the die pad.

SUMMARY

Various example embodiments are directed to issues such as those addressed above and/or others which may become apparent from the following disclosure concerning improving the electrical and thermal performance of cascode connected high voltage and low voltage transistors.

In certain example embodiments, aspects of the present disclosure involve the placement of a high voltage transistor die with respect to the low voltage transistor die in a cascode arrangement and the manner of the electrical connections therebetween.

According to an embodiment there is provided a discrete cascode semiconductor device comprising: a high voltage depletion mode device die having gate, source and drain terminals arranged on a first major surface thereof; a low voltage enhancement mode device die having a gate and a source terminals formed on a first major surface thereof and a drain terminal formed on a second major surface opposite the first major surface; wherein the drain terminal of the high voltage device die is mounted on a drain connection; the source terminal of the low voltage device die and the gate terminal of the high voltage device are mounted on a common source connection; and the drain terminal of the low voltage device die is mounted on the source terminal of the high voltage device.

The gate terminal of the low voltage device die may be mounted on a gate connection. The drain connection, common source connection and gate connection may be clip bond lead connections. The clip bond lead connections may comprise a bend intermediate a first and a second end, such that the connections are formed as gull wing leads. The clip bond lead connections may comprise mechanical support for the high voltage depletion mode device die and the low voltage enhancement mode device die.

A carrier may be mounted on a second major surface of the high voltage device, wherein the carrier comprises a insulating core arranged between two outer metal layers. A top surface of the carrier may be exposed through a top surface of a mould material.

There is also provided a semiconductor device comprising first and second cascode semiconductor devices according to an embodiment, wherein the first and second cascode semiconductor devices are arranged in a half bridge configuration.

According to an embodiment there is also provided a method of manufacturing discrete cascode semiconductor device, the method comprising: providing a high voltage depletion mode device die having gate, source and drain terminals arranged on a first major surface thereof; providing a low voltage enhancement mode device die having a gate and a source terminals formed on a first major surface thereof and a drain terminal formed on a second major surface opposite the first major surface; mounting the drain terminal of the high voltage device die on a drain connection; mounting the source terminal of the low voltage device die the gate terminal of the high voltage device on a common source connection; and mounting the drain terminal of the low voltage device die on a gate connection.

The method may further comprise mounting the drain terminal of the low voltage device die on a gate connection. The drain connection, common source connection and gate connection may be clip bond lead connections.

The method may further comprise further comprise providing a bend intermediate a first and a second end of the clip bond lead connections such that the connections are formed as gull wing leads. The clip bond lead connections may comprise mechanical support for the high voltage depletion mode device die and the low voltage enhancement mode device die.

The method may further comprise mounting a carrier on a second major surface of the high voltage device, wherein the carrier comprises a insulating core arranged between two outer metal layers. A top surface of the carrier may be exposed through a top surface of a mould material.

