CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2020-0022771, filed on Feb. 25, 2020, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments may generally relate to a variable resistive memory device and a method of operating the same, more particularly, a phase change memory device and a method of writing the phase change memory device.

2. Related Art

Recently, next-gen memory devices, replacing a DRAM device and a flash memory device, are being widely developed. The next-gen memory devices may include a variable resistive memory device by using a material that may include a resistance that rapidly changes based on an applied bias to switch at least two resistance states, i.e., a variable resistive material. The variable resistive memory device may include a phase change random access memory (PCRM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), etc.

The variable resistive memory device may include a memory cell array with a cross point array structure and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines that intersect with the word lines, and memory cells that are formed at intersection points of the word lines and the bit lines.

The memory cells may include a variable resistance. The variable resistance may be changed based on a voltage difference between the word line and the bit line.

The word line and the bit line with a uniform width and a uniform length may be extended to generate an RC delay. Thus, memory characteristics of the memory cell may be different from each other based on distances between the memory cell and the control circuit block for providing a voltage.

SUMMARY

In example embodiments of the present disclosure, a variable resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of memory cells that are connected between a global word line and a global bit line. The control circuit block may be positioned on at least one of edge portions of the memory cell array. The memory cell array may be classified into a first group with the memory cells that are adjacent to the control circuit block and a second group with the memory cells remote in relation to the control circuit block. The second group is farther from the control circuit block than the first group. The control circuit block may include a write control unit that is configured to generate a control signal for writing on the memory cell in the first group in a different way compared to writing on the memory cell in the second group.

In example embodiments of the present disclosure, a variable resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of memory cells that are connected between a global word line and a global bit line. The control circuit block may be configured to control operations of the memory cells. The control circuit block may include a write circuit and a detection circuit. The write circuit may be configured to apply a pre-selection current to the memory cell and to apply a write current to the memory cell after turning-on the memory cell based on a position of a selected memory cell. The write circuit may be configured to apply a pre-charge current, which may be different from the pre-selection current, to the memory cell and to apply the write current to the memory cell after turning-on the memory cell based on the position of the selected memory cell. The detection circuit may be connected to the global word line to detect a current of the selected memory cell. The detection circuit may be configured to enable a detection signal when turning-on the selected memory cell.

In example embodiments of the present disclosure, based on a method of operating a variable resistive memory device, a position of a selected memory cell may be identified when a write operation is initiated. A pre-selection voltage and a pre-selection current may be provided to the selected memory cell when the selected memory cell is positioned in a first group. A write voltage and a write current may be provided to the selected memory cell after stopping the supplying of the pre-selection voltage and the pre-selection current when the selected memory cell is turned-on or a snapback may be generated in the selected memory cell. A pre-selection voltage and a pre-selection current may be provided to the selected memory cell when the selected memory cell is positioned in a second group. The write voltage and the write current may be provided to the selected memory cell after stopping the supplying of the pre-selection voltage and the pre-selection current when the selected memory cell is turned-on or the snapback may be generated in the selected memory cell. The pre-selection voltage may be different from the pre-charge voltage.

