BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to technology to fabricate semiconductor device and more particularly relates to a transistor structure and the fabrication method thereof.

Description of Related Art

The metal-oxide-semiconductor (MOS) transistor has been proposed and widely used in the integrated circuit based on the semiconductor fabrication technology. As the development is continuously made, the integrated circuit is not just limited to the operation with low voltage, such as 3V to 10V. The integrate circuit with more driving capability, such as the power source circuit, may involve some operation at the high voltage level.

The MOS transistor in high voltage operation needs to have high break down voltage. At the same time, the turning on current needs to be effectively brought down for easy operation. The high voltage (HV) transistor usually needs a thicker gate insulating layer however, the gate structure needs to be properly designed to have relatively low turn-on voltage.

A lateral diffusion metal-oxide-semiconductor field effect transistor (LDMOSFET) is a field effect transistor having a drift region between a gate and a drain region in order to avoid a high electric field at a drain junction, i.e., at the p-n junction between a body and the drain region. An LDMOSFET is typically employed in high voltage power applications involving voltages in the range from about 5 V to about 500 V, which is applied across the drain region and the source region. A substantial fraction of the high voltage may be consumed within the drift region in the LDMOSFET so that the electric field generated across the gate dielectric does not cause breakdown of the gate dielectric.

However, the transistor structure for the HV operation in an example based on the LDMOSFET is still under development.

SUMMARY OF THE INVENTION

The invention provides a transistor structure and the method to fabricate the transistor device. The transistor is based on the structure of LDMOSFET, in which the breakdown voltage may remain high and the turn-on voltage may remain low.

In an embodiment, the invention provides a transistor structure, including a substrate. The substrate has a gate region and a first trench in the substate at a first side of the gate region. In addition, a first gate insulating layer is disposed on a first portion of the gate region, opposite to the first trench. A second gate insulating layer is disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer. A gate layer is disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench. A first doped region is in the substrate at least under the first trench. A second doped region is in the substrate at a second side of the gate region.

In an embodiment, as to the transistor structure, the substrate further comprises a second trench in the substrate at a second side of the gate region, wherein the second doped region is at least within the second trench.

In an embodiment, as to the transistor structure, in a cross-section view, a radius of a first bottom corner of the first trench for adapting the downward protruding portion of the gate layer is larger than a radius of a second bottom corner of the second trench adjacent to the gate layer.

In an embodiment, as to the transistor structure, it further includes a first spacer on a first sidewall of the downward protruding portion of the gate layer extending into the first trench and on the second gate insulating layer and a second spacer on a second sidewall of the gate layer extending into the second trench and on the substrate. A bottom surface of the second spacer is lower than a bottom surface of the first spacer.

In an embodiment, as to the transistor structure, it further includes a trench isolation structure in the substrate abut to the first trench opposite to the gate region.

In an embodiment, as to the transistor structure, the first doped region in the substrate extends to an interface between the first gate insulating layer and the second gate insulating layer.

In an embodiment, as to the transistor structure, the first doped region serves as a drain region and the second doped region serves as a source region.

In an embodiment, as to the transistor structure, the first doped region comprises: a first region under the first trench of the substrate and also extending to an edge of the first gate insulating layer; and a second region as heavily doped in the first trench of the substrate at a second portion not covered by the second gate insulating layer. The second region is used to receive a drain voltage.

In an embodiment, as to the transistor structure, the substrate further comprises a second trench in the substrate at the second side of the gate region, wherein the second doped region comprises: a body region of a first conductive type, within the second trench of the substrate. In addition, a first heavily doped region of a second conductive type is disposed on the body region. A second heavily doped region of the first conductive type is disposed on the body region and penetrating through the first heavily doped region, to receive a source voltage.

In an embodiment, as to the transistor structure, the substrate includes a deep doped well of the first conductive type under the first dopes region, the second doped region and the gate region. The first conductive type is P-type and the second conductive type is N-type.

In an embodiment, the invention also provides a method for fabricating a transistor, including providing a substrate, having a gate region and a first trench in the substate at a first side of the gate region. In addition, a first gate insulating layer is formed and disposed on a first portion of the gate region, opposite to the first trench. A second gate insulating layer is formed and disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer. A gate layer is formed and disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench. A first doped region is formed in the substrate at least under the first trench. A second doped region is formed in the substrate at a second side of the gate region.

In an embodiment, as to the method for fabricating a transistor, the substrate as provided further comprises a second trench in the substrate at a second side of the gate region, wherein the second doped region is at least within the second trench.

In an embodiment, as to the method for fabricating a transistor, in a cross-section view, a radius of a first bottom corner of the first trench for adapting the downward protruding portion of the gate layer is larger than a radius of a second bottom corner of the second trench adjacent to the gate layer.

In an embodiment, as to the method for fabricating a transistor, it further includes forming a first spacer on a first sidewall of the downward protruding portion of the gate layer extending into the first trench and on the second gate insulating layer. In addition, a second spacer on a second sidewall of the gate layer extending into the second trench and on the substrate. A bottom surface of the second spacer is lower than a bottom surface of the first spacer.

In an embodiment, as to the method for fabricating a transistor, it further includes forming a trench isolation structure in the substrate abut to the first trench opposite to the gate region.

In an embodiment, as to the method for fabricating a transistor, the first doped region in the substrate is extending to an interface between the first gate insulating layer and the second gate insulating layer.

In an embodiment, as to the method for fabricating a transistor, the first doped region as formed serves as a drain region and the second doped region serves as a source region.

In an embodiment, as to the method for fabricating a transistor, the first doped region as formed comprises: a first region under the first trench of the substrate and also extending to an edge of the first gate insulating layer; and a second region as heavily doped in the first trench of the substrate at a second portion not covered by the second gate insulating layer. The second region is used to receive a drain voltage.

In an embodiment, as to the method for fabricating a transistor, the substrate as provided further comprises a second trench in the substrate at the second side of the gate region, wherein the second doped region comprises a body region of a first conductive type, within the second trench of the substrate. In addition, a first heavily doped region of a second conductive type is disposed on the body region. A second heavily doped region of the first conductive type is disposed on the body region and penetrating through the first heavily doped region, to receive a source voltage.

In an embodiment, as to the method for fabricating a transistor, the substrate as provided includes a deep doped well of the first conductive type under the first dopes region, the second doped region and the gate region. The first conductive type is P-type and the second conductive type is N-type.

