TECHNICAL FIELD

The present disclosure generally relates to semiconductor memory devices, and more particularly relates to methods for mitigating power loss events during operation of memory devices and memory devices employing the same.

BACKGROUND

Memory devices are frequently provided as internal, semiconductor, integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory, including random-access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others, may require a source of applied power to maintain its data. Non-volatile memory, by contrast, can retain its stored data even when not externally powered. Non-volatile memory is available in a wide variety of technologies, including flash memory (e.g., NAND and NOR) phase change memory (PCM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), among others.

Flash memory devices can include an array of memory cells that each store data in a charge storage structure, such as a conductive floating gate or a dielectric charge trap. Flash memory devices frequently use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption during use. Memory cells in a flash memory device can be programmed to a target state to represent information. For instance, electric charge can be placed on, or removed from, the charge storage structure (e.g., the charge trap or the floating gate) of a memory cell to program the cell to a particular data state. The amount of charge stored on the charge storage structure of the memory cell can be indicated by a threshold voltage (VT) of the cell.

For example, a single level cell (SLC) can be programmed to a targeted one of two different data states, which can be represented by the binary units 1 or 0. Other flash memory cells can be programmed to a targeted one of more than two data states. For example, a flash memory cell which can be programmed to any one of four states (e.g., represented by the binary values 00, 01, 10, 11) can be used to store two bits of data, and may be referred to as a multilevel cell (MLC). Still other flash memory cells can be programmed to any one of eight data states (e.g., 000, 001, 010, 011, 100, 101, 110, 111), permitting the storage of three bits of data in a single cell. Such cells may be referred to as triple level cells (TLC). Even higher number of data states are possible, such as those found in quad level cells (QLC), which can be programmed to any one of 16 data states (e.g., 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111) to store four bits of data. The use of memory cells capable of storing higher numbers of data states can provide higher density memories without increasing the number of memory cells, since each cell can represent more than one digit (e.g., more than one bit).

Memory cells configured to store multiple bits of information can be programmed in multiple passes. For example, a less significant bit can be programmed to the cell with a first programming operation to modify the charge stored on the charge storage structure to one of two targeted charge storage levels (e.g., threshold voltage or VTlevels). A more significant bit can be subsequently programmed to the cell with a second programming operation to modify the charge stored on the charge storage structure to one of four target charge storage levels. For example,FIG. 1illustrates the charge stored on the charge storage structures of one or more memory cells at various states of a multi pass programming operation. At time110, charge112is stored on the memory cell, indicating that the cell is in an un-programmed or empty state (e.g., an erased state). A first programming operation is utilized at time120to program the cell to one of two possible target states on either side of threshold voltage V1. For example, if the less significant bit is a 1, the cell can be programmed to state122by programming operation121(which, in the illustrated example, may not require the addition of any charge to the cell's charge storage structure). If the less significant bit is a 0, the cell can be programmed to state124above threshold voltage V1by programming operation123(e.g., by the addition of charge to the cell's charge storage structure). A second programming operation can be utilized at time130, to subsequently program the cell to one of four possible target states, separated by threshold voltages V2, V3and V4, respectively. If the more significant bit is a 1, the cell can be programmed to either of state132or138(depending upon the value of the less significant bit) by one of programming operation131or137, respectively. If the more significant bit is a 0, the cell can be programmed to either of state134or136(depending upon the value of the less significant bit) by one of programming operation133or135, respectively. A third programming operation can be utilized at time140, to subsequently program the cell to one of eight possible target states, separated by threshold voltages V5through V11. Depending upon both the most significant bit to be programmed and the intermediate state at time130, one of programming operations141through148may be used to modify the charge on the cell until the desired target state is reached (e.g., one of the eight data states corresponding to the logical values of 111, 011, 001, 101, 100, 000, 010, or 110). AlthoughFIG. 1uses histograms to illustrate the distribution of stored charges on multiple memory cells programmed to the same threshold voltages at the same time, similar programming operations may be applied to a single memory cell.

Flash programming operations can use a series of programming pulses to increase the charge stored on the charge storage structure of one or more memory cells by a known increment, with each programming pulse being followed by a verification step to determine the cumulative amount of charge stored on the charge storage structures of the one or more memory cells. The programming operation normally continues until a verification step indicates that the targeted charge storage level has been reached. For example,FIG. 2illustrates the charge stored on the charge storage structure of one or more memory cells at a various states of one such incremental programming operation. The charge212stored at time210is below a desired target state Vtargetwhen the incremental programming operation begins. To program the one or more memory cells to the desired target state, a series of programming steps221,231and241can be used at each of time220,230and240to increase the charge stored on the charge storage structures of the one or more memory cells to charges222,232and242, respectively. After each programming pulse, the stored charge can be verified to determine whether it has reached the desired target state Vtarget. At time240, as the charge241has been increased to the desired target state, the programming operation is completed.

For programming more significant bits to a cell that already has been programmed with less significant bits, the number of programming pulses (and verification steps) used in a programming operation may be larger (e.g., due to the addition of a smaller increment of charge with each programming pulse), such that programming more significant bits to a cell can take more time and/or energy than programming less significant bits. Memory devices can be provided with energy storage structures, such as capacitors, to provide a sufficient amount of power for a sufficient amount of time to complete in-process programming operations that might otherwise be interrupted by a loss of externally applied power. As memory devices are designed with cells that store ever more bits of information, which may take more time and power to program, the size and cost of these energy storage structures may be significantly increased.

