CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2020-0006824, filed on Jan. 17, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

BACKGROUND

1. Technical Field

The present disclosure generally relates to a semiconductor memory device and a manufacturing method thereof, and more particularly, to a semiconductor memory device including a line disposed on a memory cell array and a manufacturing method thereof.

2. Related Art

A semiconductor memory device includes a memory cell array and a peripheral circuit. The memory cell array includes memory cells that are capable of storing data, and the peripheral circuit controls an operation of the memory cell array. The memory cell array and the peripheral circuit may be connected to lines through which driving signals are transmitted. The lines for transmitting the driving signals are disposed on the memory cell array so that the degree of integration of the semiconductor memory device can be improved.

SUMMARY

In accordance with an embodiment of the present disclosure, a semiconductor memory device may include: bit lines and a common source line connected to a memory cell array, wherein the bit lines and the common source line are spaced apart from each other in a first level; a pad pattern spaced apart from the bit lines and the common source line in the first level; a first insulating layer covering the bit lines, the common source line, and the pad pattern; a shielding pattern overlapping with the bit lines and disposed on the first insulating layer; a first upper line and a second upper line spaced apart from each other above the shielding pattern; a first contact plug extending from the pad pattern to be in contact with the first upper line; a second contact plug extending from the common source line to be in contact with the second upper line; a first spacer insulating layer extending toward the first upper line from between the shielding pattern and the first contact plug; and a second spacer insulating layer extending toward the second upper line from between the shielding pattern and the second contact plug.

In accordance with an embodiment of the present disclosure, a method of manufacturing a semiconductor memory device may include: forming bit lines, a common source line, and a pad pattern spaced apart from each other; forming a first insulating layer that covers the bit lines, the common source line, and the pad pattern; sequentially stacking a shielding metal layer and a second insulating layer on the first insulating layer; forming a first hole that overlaps with the pad pattern by etching the second insulating layer and the shielding metal layer; forming a first spacer insulating layer on a sidewall of the first hole; forming a first contact plug on the first spacer insulating layer by filling the first hole, wherein the first contact plug extends to be in contact with the pad pattern; and forming a first upper line that is connected to the first contact plug, wherein the first upper line extends onto the second insulating layer.

In accordance with an embodiment of the present disclosure, a semiconductor memory device may include: bit lines and a common source line connected to a memory cell array, wherein the bit lines and the common source line are spaced apart from each other in a first level; a pad pattern spaced apart from the bit lines and the common source line in the first level; a first insulating layer covering the bit lines, the common source line, and the pad pattern; a shielding pattern overlapping with the bit lines and disposed on the first insulating layer; a first upper line and a second upper line spaced apart from each other above the shielding pattern; a plurality of contact plugs extending from the first and second upper lines toward the bit lines, common source line, and pad pattern, wherein one or more of the plurality of contact plugs connect the shielding pattern to the second upper line.

