This application claims priority from Korean Patent Application No. 10-2019-0167984 filed on Dec. 16, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

Example embodiments relate to a System on Chip (SoC), a memory device, an electronic device, and/or a method for storing data in the electronic device.

Data bits which move through a data bus may be sensitive to a cross-talk, a simultaneous switching noise (SSN), an inter-symbol interference (ISI) and/or the like, depending on a state of data or a frequency of data transition. A data encoding method such as a data bus inversion (DBI) may be used to reduce such adverse effects.

Meanwhile, in order to support various systems such as graphics, servers, supercomputers, and/or networks that require high performance and low power consumption, a high-bandwidth memory (HBM) which provides a multi-channel interface type of wide input and output is used.

The HBM may execute DBI on a channel including a plurality of data bits, for example, on a byte basis. There is a desire and/or need for a research on a method for determining the DBI bit to improve an operating speed of the HBM.

SUMMARY

Aspects of example embodiments provide an electronic device with an improved data storage speed.

Aspects of example embodiments also provide a method for storing data in an electronic device with an improved data storage speed.

Aspects of example embodiments also provide a memory device with an improved data storage speed.

Aspects of example embodiments also provide a SoC that calculates a DBI bit and provides the DBI bit to a memory device so that a data storage speed may be improved.

However, aspects of example embodiments are not restricted to the one set forth herein. The above and other aspects of example embodiments will become more apparent to one of ordinary skill in the art to which example embodiments pertains by referencing the detailed description of example embodiments given below.

According to some example embodiments, there is provided an electronic device comprising a host configured to output data, and a memory device including a memory storage configured to receive the data and to store the data. The host is configured to generate data bus inversion (DBI) information on the data to be provided to the memory device in accordance with a data parallelizing system, the data parallelizing system being inside the memory device, and to provide the DBI information to the memory device. The memory device is configured to provide the data to the memory storage, the data output from the host, the data encoded in accordance with the DBI information, the providing the data being in accordance with the data parallelizing system.

According to some example embodiments, there is provided a method for storing data in an electronic device comprising providing, to a host by a memory device, information on a data parallelizing system, the information inside the memory device, calculating, by the host, an external DBI bit on the basis of data to be provided to the memory device, providing, by the host, the external DBI bit to the memory device, encoding, by the host, the data to be stored in the memory device using the external DBI bit, providing, by the host, the data to the memory device, calculating, by the host, an internal DBI bit on the basis of the data provided to the memory device and information on a data parallelizing system provided from the memory device, and providing, by the host, the internal DBI bit to the memory device.

According to some example embodiments, there is provided a memory device comprising a memory storage configured to store data provided through a first input port, and control logic configured to receive the data from outside through a second input port, to rearrange the data provided through the second input port in accordance with a data parallelizing system, and to provide the data to the memory storage through the first input port. The control logic is configured to receive an internal DBI bit of the data from the outside, the internal DBI generated on the basis of the data parallelizing system, to encode the data using the internal DBI bit, and to provide the encoded data and the internal DBI bit to the memory storage.

According to some example embodiments, there is provided an SoC comprising an output port configured to output a plurality of sub-data in accordance with a first array, and a data bus inversion (DBI) controller configured to receive information on a data parallelizing system from outside, to generate DBI bits of a plurality of sub-data which is output through the output port on the basis of information on the provided data parallelizing system, and to output the generated DBI bit together with the plurality of sub-data. The information on the data parallelizing system is information relating to a rearrangement of the plurality of sub-data into a second array different from the first array. The DBI bit is associated with a decoding of the plurality of sub-data rearranged into the second array.

