CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2020-0148221, filed on Nov. 9, 2020, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally illustrate an integrated circuit technology, and more particularly, describe a memory apparatus and a semiconductor system using the same.

2. Related Art

In some embodiments electronic apparatuses may include a large number of electronic components. Among the electronic apparatuses, a computer system may include a large number of semiconductor apparatuses which include a plurality of semiconductors. The computer system includes semiconductor apparatuses which may communicate with one another by transmitting or receiving a clock and data. The semiconductor apparatuses are synchronized with a clock signal and a strobe signal. The data strobe signal may be a clock signal which toggles in synchronization with a timing at which data is transmitted. Thus, in order for the semiconductor apparatuses to accurately transmit and/or receive data, it is important to match the timings of the data and the data strobe signal. However, a skew may occur in the timings of the data and the data strobe signal due to various internal factors of the semiconductor apparatuses.

SUMMARY

In an embodiment, a memory apparatus may include an active monitoring circuit and a mode register circuit. The active monitoring circuit may generate a plurality of selection control signals by monitoring an interval at which a memory bank of a memory cell array is accessed. The mode register circuit may set a threshold value for performing a refresh operation, as one of a plurality of values, based on the plurality of selection control signals.

In an embodiment, a memory apparatus may include a first memory bank, a second memory bank, and a row hammer control circuit. The row hammer control circuit may set a first threshold value as a reference for refreshing the first memory bank, and may monitor an active interval at which the first memory bank is accessed and configured to set a second threshold value as a reference for refreshing the second memory bank, by tracking access of an active interval of the second memory bank.

In an embodiment, a semiconductor system may include a memory apparatus and a memory controller, wherein the memory apparatus may use an active command signal to track an active interval and may change a threshold value based on the active interval. The active command signal is then generated by the memory controller and is used to access the memory apparatus by generating the active command signal and configured to generate a refresh command signal for refreshing the memory apparatus, by comparing an accumulated counting value, obtained by counting the number of generations of the active command signal, with the threshold value.

In an embodiment, a semiconductor system may include a memory apparatus and a memory controller. A memory bank is located in the memory apparatus. Refreshing is accomplished by using the memory controller to generate a refresh command signal based on the number of generations of an active command signal for the memory bank and a generation interval of the active command signal. The memory apparatus may perform a refresh operation for the memory bank, based on the refresh command signal.

In an embodiment, a memory apparatus may include an active monitoring circuit and a mode register circuit. The active monitoring circuit may generate a plurality of selection control signals by monitoring an interval at which a memory bank of a memory cell array is accessed. The mode register circuit may implement a request/threshold value for performing a minimized number of refresh operations based on the request/threshold value and the plurality of selection control signals.

