This application is the U.S. national phase of International Application No. PCT/KR2018/013583 filed 9 Nov. 2018, which designated the U.S. and claims priority to KR Patent Application No. 10-2017-0182364 filed 28 Dec. 2017, the entire contents of each of which are hereby incorporated by reference.

TECHNICAL FIELD

Embodiments of the disclosure relate to a structure of a processor's internal memory, and relate to a memory apparatus and a method for processing data the same for processing the data in 10-bit or 12-bit units.

BACKGROUND ART

Wide color gamut (high color reproduction) to increase the color gamut to reproduce an image similar to the actual color on a recent video display, or 10-bit or 12-bit High Dynamic Range (HDR) expressing the ratio of brightness that can be felt while watching the real natural environment, are utilized more frequently. Processors that perform such image processing tend to use frequency of pixel information of an image from 8 bits to 10 bits or 12 bits.

An internal memory of current processor is stored in 8-bit (byte) units using byte unit addresses, and non-8-bit data is processed and stored in 8-bit units.

As such, since the internal memory of the current processors stores data in 8-bit units, 16-bit memory space must be allocated and stored in order to store 10-bit or 12-bit data. For example, in order to store 10-bit data, an additional 8-bit memory capacity is required to store 2 out of 10 bits, resulting in inefficient memory usage. Such inefficient use of memory can result in an increase in cost and performance degradation of a system operating by using a small resource such as an embedded processor.

SUMMARY

One aspect of the embodiment in order to solve the above-mentioned problems suggests a memory apparatus capable of efficiently storing 10-bit or 12-bit data and a data processing method and a recording medium for executing the same.

In accordance with an aspect of the disclosure, a memory apparatus comprises, a plurality of memory banks storing data; and a memory controller configured to allocate addresses for accessing the plurality of memory banks according to a bit unit of the data, and the memory controller may process 10-bit data by allocating addresses in 8-bit units for some of the plurality of the memory banks, and allocating addresses in 2-bit units for the other memory banks.

The plurality of memory banks may further include: a first memory bank to which addresses are allocated in the 8-bit unit, and a second memory bank to which addresses are allocated in the 2-bit unit, and the memory controller may determine whether to access only the first memory bank or access the first memory bank and the second memory bank according to the bit unit of the data.

The memory controller may process the 8-bit unit data by accessing only the first memory bank when the data is in 8-bit units.

The memory controller may access the first memory bank and the second memory bank to combine and process the 8-bit unit data of the first memory bank and the 2-bit unit data of the second memory bank when the data is in 10-bit units.

The first memory bank may include an 8-bit operation area for accessing the 8-bit unit data and a 10-bit operation area for accessing the 10-bit unit data.

The second memory bank may include a 10-bit operation area for accessing the 10-bit unit data.

The memory controller may access the first memory bank and the second memory bank by dividing the 10-bit unit data into upper 8-bit unit data and lower 2-bit unit data

The memory controller may access the upper 8-bit unit data to the 10-bit operation area of the first memory bank, and access the lower 2-bit unit data to the 10-bit operation area of the second memory bank and then combine the accessed upper 8-bit unit data and the accessed lower 2-bit unit data.

The first memory bank may use an 8-bit unit address in the 10-bit operation area, and is composed of the plurality of memory banks, and the plurality of memory banks includes bank 0, bank 1, and bank 3.

The second memory bank may use a 2-bit unit address in the 10-bit operation area, and is composed of bank 4.

The memory controller may allocate 8-bit memory space at a 3rdposition of bank 2 when the memory controller stores the 10-bit unit data in addresses 10 to 11 of the 8-bit operation area, and may all use 16-bit memory space by allocating 8-bit memory space at a 4thposition of the bank 2.

The memory controller may allocate 8-bit memory space at a 2ndposition of the bank 1 when the memory controller stores the 10-bit unit data in addresses 10 to 11 of the 10-bit operation area, and may all use 10-bit memory space by allocating 2-bit memory space at a 6thposition of the bank 4.

The first memory bank and the second memory bank may further include a 12-bit operation area for accessing 12-bit unit data, and the memory controller may access to the first memory bank and the second memory bank by dividing the 12-bit unit data into upper 8-bit unit data and lower 4-bit unit data.

The memory controller may access the upper 8-bit unit data to the 12-bit operation area of the first memory bank, and may access the lower 4-bit unit data to the 12-bit operation area of the second memory bank and then may combine the accessed upper 8-bit unit data and the accessed lower 2-bit unit data.

In accordance with an aspect of the disclosure, a data processing method of a memory apparatus including a plurality of memory banks for storing data includes: allocating an address in 8-bit units to a first memory bank of the plurality of memory banks; allocating the address in 2-bit units to a second memory bank of the plurality of memory banks; and processing 10-bit unit data by using the first memory bank and the second memory bank.

Also, in accordance with an aspect of the data processing method, the method further includes: determining whether to access only the first memory bank or access the first memory bank and the second memory bank according to the bit unit of the data.

Processing the 10-bit unit data may include: dividing the 10-bit unit data into upper 8-bit unit data and lower 2-bit unit data; accessing the upper 8-bit unit data to the first memory bank; accessing the lower 2-bit unit data to the second memory bank; and combining and processing the upper 8-bit unit data and the lower 2-bit unit data.

In accordance with an aspect of the disclosure, a computer-readable recording medium may include: an instruction allocating an address in 8-bit units to a first memory bank of a plurality of memory banks storing data; allocating the address in 2-bit units to a second memory bank of the plurality of memory banks; and causing a processor to perform an operation of processing 10-bit unit data using the first memory bank and the second memory bank.

According to a memory apparatus and a method for processing data the same, a processor that uses 10-bit or 12-bit data can efficiently store 10-bit or 12-bit data and provide a flexible memory access method that reduces memory usage. To this end, by adding a new memory bank that is ¼ of the size of an existing memory bank word, when storing data in 10-bit units, 2 out of 10 bits can be stored in a new memory bank to reduce memory waste. In addition, when 8-bit data is stored using a flexible memory structure, data can be stored in the same way as a previously operated memory bank.

