CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Patent Application No. 10-2020-0058448, filed on May 15, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

The inventive concept relates to a data processing system, and more particularly, to a system for predicting a faulty memory based on a page fault and managing the predicted faulty memory and a method of handling an operating system (OS) of the system.

A data processing system like a data center is hosted by many companies and their computer systems. The data center is used to distribute hosted applications and/or transactions and includes networked computer resources that are often referred to as clouds, e.g., servers, disks, virtual machines, etc. In this configuration, companies are clients of the data center. Data centers offer clients a number of advantages, including reduced cost, easy expansion, and reduced management load.

Demands for high-capacity memories for data centers for stable and fast real-time processing of large amounts of data have increased. However, the performance quality of a memory may change over time. For example, when an application and/or a transaction is allocated and uses a memory, a page fault may occur due to a fault in the memory. When such a page fault occurs frequently, the normal flow execution of instructions may be disrupted, and thus availability constraints of a data center, e.g., aborting and restarting a started operation, may occur. The page fault may arise from a single bit failure or two or more bits failures. Therefore, when a faulty memory may be identified based on a page fault, it will be possible to predict a memory fault due to the faulty memories. Also, managing a predicted memory fault in advance will be desirable for maintaining the availability of a data center.

SUMMARY

The inventive concept provides a system for predicting a memory fault based on a page fault and managing the predicted memory fault and a method of handling an operating system of the system.

According to an exemplary embodiment of the present invention, a method of operating a system running a virtual machine that executes an application and an operating system (OS) includes performing, by the OS, first address translation from a plurality of first virtual addresses processed by the application to a plurality of first physical addresses for accessing a memory, identifying, by the OS, a plurality of faulty physical addresses among the plurality of first physical addresses, wherein each of the plurality of faulty physical addresses corresponds to a corresponding first physical address, among the plurality of first physical addresses, associated with a faulty memory cell of the memory, analyzing, by the OS, a row address and a column address of each of the plurality of faulty physical addresses and specifying, by the OS, a fault type of the plurality of faulty physical addresses based on the analyzing of the row address and the column address of each of the plurality of faulty physical addresses, wherein the fault type includes a row failure, a column failure or a block failure, and performing, by the OS, second address translation from a plurality of second virtual addresses to a plurality of second physical addresses based on a faulty address, thereby excluding the faulty address from the plurality of second physical addresses. The faulty address corresponds to the fault type of the plurality of faulty physical addresses, and includes a faulty row address of the row failure, a faulty column address of the column failure, or a faulty block address of the block failure.

According to an exemplary embodiment of the present invention, a non-transitory computer-readable recording medium storing computer-executable instructions for performing a method of operating a system running a virtual machine that executes an application and an operating system (OS) includes executing the application using a processor and a memory of the system, performing first address translation from a plurality of first virtual addresses allocated to the application to a plurality of first physical addresses for accessing the memory, identifying, during a time when the application is executed, a plurality of faulty physical addresses among the plurality of first physical addresses translated from the plurality of first virtual addresses, specifying a fault type of the plurality of faulty physical addresses, wherein the fault type includes a row failure, a column failure, or a block failure, and performing second address translation from a plurality of second virtual addresses to a plurality of second physical addresses based on a faulty address, thereby excluding the faulty address from the plurality of second physical addresses. The faulty address corresponds to the fault type of the plurality of faulty physical addresses, and includes a faulty row address of the row failure, a faulty column address of the column failure or a faulty block address of the block failure.

According to an exemplary embodiment of the present invention, a system operating in a virtual machine environment includes a memory, and a processor operatively coupled to the memory. The processor executes an application in cooperation with the memory, performs first address translation from a plurality of first virtual addresses processed by the application to a plurality of first physical addresses for accessing the memory, identifies a plurality of faulty physical addresses among the plurality of first physical addresses, wherein each of the plurality of faulty physical addresses corresponds to a corresponding first physical address, among the plurality of first physical addresses, associated with a faulty memory cell of the memory, specifies a fault type of the plurality of faulty physical addresses of the memory, wherein the fault type includes a row failure, a column failure, or a block failure, and performs second address translation from a plurality of second virtual addresses to a plurality of second physical addresses based on a faulty address to prevent the faulty address from being used for the second address translation. The faulty address corresponds to the fault type of the plurality of faulty physical addresses, and includes a faulty row address of the row failure, a faulty column address of the column failure or a faulty block address of the block failure. The processor is further configured to, without causing the system to be rebooted, specify the fault type, store the faulty address, and perform the second address translation.

According to an exemplary embodiment of the present invention, a memory device includes a memory cell array comprising a plurality of memory cells, and a repair control circuit configured to repair a plurality of faulty memory cells from among the plurality of memory cells by using a plurality of redundancy memory cells in the memory cell array. The repair control circuit is configured to receive, during rebooting of the memory device, a source address of the plurality of faulty memory cells from a processor to which the memory device is operatively coupled and repair the source address with a destination address of the plurality of redundancy memory cells. The source address of the plurality of faulty memory cells corresponds to a faulty address including a common row address of the plurality of faulty memory cells, a common column address of the plurality of faulty memory cells, or a block address of the plurality of faulty memory cells. The plurality of faulty memory cells are identified during execution of a virtual machine running on the processor. The faulty address of the plurality of faulty memory cells is included in a plurality of physical addresses for accessing the memory device by a system. The plurality of physical addresses are translated from a plurality of virtual addresses used by the processor.

