CROSS-REFERENCE TO RELATED APPLICATION

This application is a national stage application under 35 U.S.C. § 371 of International Application No. PCT/CN2019/086425 filed May 10, 2019, which claims priority to Chinese Patent Application No. 201810725147.5, filed Jul. 4, 2018, the contents of which are incorporated by reference in the entirety.

TECHNICAL FIELD

The present invention relates to display technology, more particularly, to a pixel circuit and driving method thereof, a pixel unit, and a display panel.

BACKGROUND

Micro LED technology is a technology to form array of miniaturized light-emitting diodes all integrated on a chip with high density. It has many advantages in high emission efficiency, high luminance, high resolution, and fast response time. Application on the Micro LED technology to display panel has become a trend of state-of-art display technologies.

A display panel includes a plurality of pixel units surrounded by a plurality of data lines and a plurality of gate lines. The plurality of pixel units is arranged in an array. When the display panel is implemented with Micro LEDs, each pixel unit includes a LED device and a pixel circuit. The pixel circuit is configured to supply a voltage to the LED in the pixel unit to control its light emission, driving image display. Improved pixel circuit associated with Micro LED is desired to simplify the circuitry structure in the display panel.

SUMMARY

In an aspect, the present disclosure provides a pixel circuit. The pixel circuit includes an input circuit respectively connected with N gate lines, a control line, and N control nodes. The input circuit is configured to control voltage levels of the N control nodes under control of a respective one gate-driving signal from a respective one of the N gate lines and under control of a first control signal from the control line. The pixel circuit further includes a control circuit respectively connected with the N control nodes and 2N switching nodes. The control circuit is configured to control a voltage level of a respective one of the 2N switching nodes under control of the N control nodes. Additionally, the pixel circuit includes 2N output circuits respectively connected with 2N data-signal terminals. The 2N output circuits are connected with the 2N switching nodes, wherein an i-th output circuit of the 2N output circuits is coupled respectively with an i-th switching node of the 2N switching nodes, an i-th data-signal terminal of the 2N data-signal terminals, and an emission circuit. The i-th output circuit is configured to output an i-th data signal from the i-th data-signal terminal under control of the i-th switching node. N is a positive integer, i is a positive integer no greater than N.

Optionally, for the case that N is 2, the control circuit includes a latch subcircuit, a first control subcircuit, and a second control subcircuit. The 2Nswitching nodes include a first switching node, a second switching node, a third switching node, and a fourth switching node. The N control nodes include a first control node and a second control node. The latch subcircuit is connected respectively to the first control node and a latch node configured to set a voltage level thereof under control of the first control node. The first control subcircuit is connected respectively to the latch node, the second control node, the first switching node, and a second switching node. The first control subcircuit is configured to respectively set voltage levels of the first switching node and the second switching node under control of the latch node and the second control node. The second control subcircuit is connected respectively to the first control node, the second control node, the third switching node, and the fourth switching node. The second control subcircuit is configured to respectively set voltage levels of the third switching node and the fourth switching node under control of the first control node and the second control node.

Optionally, the first control subcircuit includes a first control unit-circuit and a second control unit-circuit. The second control subcircuit includes a third control unit-circuit and a fourth control unit-circuit. The first control unit-circuit is connected respectively to the latch node, the second control node, the first switching node, and the second switching node. The first control unit-circuit is configured to respectively set voltage levels of the first switching node and the second switching node under control of the latch node and the second control node. The second control unit-circuit is connected respectively to the latch node, a pull-down power supply, the first switching node, and the second switching node. The second control unit-circuit is configured to respectively set voltage levels of the first switching node and the second switching node under control of a pull-down voltage from the pull-down power supply. The third control unit-circuit is connected respectively to the first control node, the second control node, the third switching node, and the fourth switching node. The third control unit-circuit is configured to respectively set voltage levels of the third switching node and the fourth switching node under control of the first control node and the second control node. The fourth control unit-circuit is connected respectively to the first control node, the pull-down power supply, the third switching node, and the fourth switching node. The fourth control unit-circuit is configured to respectively set voltage levels of the third switching node and the fourth switching node under control of the first control node and the pull-down voltage.

Optionally, the first control unit-circuit includes a first latch having an input terminal connected to the second control node and an output terminal connected to the first switching node. The third control unit-circuit includes a second latch having an input terminal connected to the second control node and an output terminal connected to the third control node.

Optionally, the first latch includes a first tri-state gate and a second tri-stage gate. The second latch includes a third tri-state gate and a fourth tri-state gate. The first tri-state gate includes a control terminal connected to the latch node, an input terminal connected to the second control node, and an output terminal connected to the first switching node. The second tin-state gate includes a control terminal connected to the latch node, an input terminal connected to the first switching node, and an output terminal connected to the second control node. The third tri-state gate includes a control terminal connected to the first control node, an input terminal connected to the second control node, and an output terminal connected to the third switching node. The fourth tri-state gate includes a control terminal connected to the first control node, an input terminal connected to the third switching node, and an output terminal connected to the second control node.

Optionally, the second control unit-circuit includes a first transistor and a second transistor. The fourth control unit-circuit includes a third transistor and a fourth transistor. The first transistor has a gate terminal connected to the latch node, a first terminal connected to the pull-down power supply, and a second terminal connected to the first switching node. The second transistor has a gate terminal connected to the latch node, a first terminal connected to the pull-down power supply, and a second terminal connected to the second switching node. The third transistor has a gate terminal connected to the first control node, a first terminal connected to the pull-down power supply, and a second terminal connected to the third switching node. The fourth transistor has a gate terminal connected to the first control node, a first terminal connected to the pull-down power supply, and a second terminal connected to the fourth switching node.

Optionally, the latch subcircuit includes a third latch having an input terminal connected to the first control node and an output terminal connected to the latch node.

Optionally, the third latch includes a first non-gate and a second non-gate. The first non-gate has an input terminal connected to the first control node and an output terminal connected to the latch node. The second non-gate has an input terminal connected to the latch node and an output terminal connected to the first control node.

Optionally, for the case that N is 1, the 2Nswitching nodes includes a first switching node and a third switching node, the N control node is a first control node. The control circuit is connected respectively to the first control node, the first switching node, and the third switching node. The control circuit is configured to set voltage levels of the first switching node and the third switching node under control of the first control node.

Optionally, the i-th output circuit includes an i-th output transistor having a gate terminal connected to the i-th switching node, a first terminal connected to the i-th data-signal terminal, and a second terminal connected to the emission circuit.

Optionally, the input circuit includes N input transistors among which a j-th input transistor having a gate terminal connected to a j-th gate line, a first terminal connected to the control line, and a second terminal connected to a j-th control node, wherein j is a positive integer no greater than N.

In another aspect, the present disclosure provides a driving method of a pixel circuit described herein. The method includes providing a gate-driving signal at a turn-on voltage level to a j-th gate line of the N gate lines so that the input circuit transports a first control signal in the control line to a corresponding j-th control node of the N control nodes. Here j is a positive integer no greater than N. Additionally, the method includes setting one switching node of the 2Nswitching nodes to a turn-on voltage level under control of the N control nodes so that a corresponding one output circuit connected to the one switching node is to input a data signal from a corresponding data-signal terminal connected to the corresponding one output circuit to the emission circuit. The 2Noutput circuits are connected respectively to the 2Nswitching nodes. The 2Noutput circuits are connected respectively to data-signal terminals. The 2Ndata-signal terminals supply different data signals.

Optionally, the 2Ndata-signal terminals supply different data signals with different amplitudes.

Optionally, the 2Ndata-signal terminals supply different data signals with different duty cycles.

Optionally, for the case that N is 2, the control circuit includes a latch subcircuit, a first control subcircuit, and a second control subcircuit. The 2Nswitching nodes includes a first switching node, a second switching node, a third switching node, and a fourth switching node. The N control nodes includes a first control node and a second control node. The method includes setting the first control node at a turn-off voltage level and the second control node at a turn-off voltage level, so that the control circuit sets the first switching node to the turn-off voltage level, the second switching node to the turn-off voltage level, the third switching node to a turn-on voltage level, and the fourth switching node to the turn-off voltage level. The method further includes setting the first control node at a turn-off voltage level and the second control node at a turn-on voltage level, so that the control circuit sets the first switching node to the turn-off voltage level, the second switching node to the turn-off voltage level, the third switching node to the turn-off voltage level, and the fourth switching node to the turn-on voltage level. Additionally, the method includes setting the first control node at a turn-on voltage level and the second control node at a turn-off voltage level, so that the control circuit sets the first switching node to the turn-on voltage level, the second switching node to the turn-off voltage level, the third switching node to the turn-off voltage level, and the fourth switching node to the turn-off voltage level. Furthermore, the method includes setting the first control node at a turn-on voltage level and the second control node at the turn-on voltage level, so that the control circuit sets the first switching node to a turn-off voltage level, the second switching node to the turn-on voltage level, the third switching node to the turn-off voltage level, and the fourth switching node to the turn-off voltage level.

Optionally, for the case that N is 1, the 2Nswitching nodes includes a first switching node and a third switching node, the N control node is a first control node. The method includes setting the first control node to a turn-on voltage level, so that the control circuit sets the first switching node to a turn-off voltage level and the third switching node to the turn-on voltage level. Additionally, the method includes setting the first control node to a turn-off voltage level, so that the control circuit sets the first switching node to a turn-on voltage level and the third switching node to the turn-off voltage level.

In yet another aspect, the present disclosure provides a pixel unit including an emission circuit and a pixel circuit described herein. The pixel circuit includes an output circuit coupled to the emission circuit.

Optionally, the emission circuit includes a switching subcircuit and an emitting subcircuit. The switching subcircuit is connected respectively to a second control-signal terminal. The output circuit is connected to the emitting subcircuit. The switching subcircuit is configured to input a signal from the output circuit to the emitting subcircuit under control of a second control signal from the second control-signal terminal.

Optionally, the emission circuit includes a switching subcircuit and an emitting subcircuit. The switching subcircuit is connected respectively to a second control-signal terminal, a pull-up power supply, the output circuit, and the emitting subcircuit. The switching subcircuit is configured to input a pull-up voltage signal from the pull-up power supply to the emitting subcircuit under control of a second control signal from the second control-signal terminal.

In still another aspect, the present disclosure provides a display panel including a plurality of pixel units. Each of the plurality of pixel units is the pixel unit described herein.

