BACKGROUND

Cache memories in microprocessors may have a significant impact on their performance. A cache memory is a memory within a processor that is small and fast relative to system memory, also referred to as main memory. The cache memory holds a copy of a small subset of the contents of system memory so that the processor can access the subset faster than the processor can access system memory. Generally, the cache tends to hold most recently used data by evicting least recently used data when allocating space for newly used data. In this manner, a cache memory reduces the execution time of load/store instructions by alleviating the need to read system memory to access the data specified by a load instruction and enabling a store instruction to immediately write its data to the cache memory without having to wait to write the data to system memory, for example. Generally, a cache memory stores a copy of system memory data in a quantum of a cache line, or cache block, e.g., 64 bytes. That is, when a cache memory allocates an entry for a memory address, the cache memory brings in an entire cache line implicated by the memory address, and when the cache memory has modified a copy of system memory, the cache memory writes back to system memory the entire modified cache line rather than merely the modified data.

The cache memories may significantly improve processor performance since a system memory access may require an order of magnitude more clock cycles than a cache memory access. Importantly, a load instruction, for example, may be stalled in its execution waiting for the data to be read from memory. To further exacerbate the situation, instructions dependent upon the load data may be prevented from being issued for execution, and instructions dependent upon the dependent instructions may also be prevented from being issued for execution, and so forth. If enough dependent instructions are stalled or waiting to issue and sufficient independent instructions are not within the execution window, execution units of the processor may sit idle, significantly reducing the instruction execution rate of the processor.

Even though a cache memory may improve load/store execution time by mitigating the need for memory accesses, nevertheless the time required to access the cache memory also affects the performance of the processor. This is particularly true for the cache memory that is directly accessed by load/store units of the processor, i.e., the cache memory at the lowest level in a processor that includes a cache hierarchy of multiple cache memories. That is, the performance of the processor may be significantly improved by reducing even a single clock cycle from the access time to the first level cache memory and/or enabling the cycle time of the processor to be made shorter by reducing the first level cache memory access time.

Finally, the performance of the processor is also significantly affected by the hit rate of the cache memory, which is affected by the capacity of the cache memory in terms of the number of bytes the cache memory is designed to hold. Cache memories hold other information besides the actual cache line data such as tags, status, and replacement policy information. Reducing the amount of other information held by the cache may enable the capacity of the cache to be bigger, i.e., to store more bytes of copies of memory data, thereby improving its hit rate. Furthermore, reducing the amount of other information held by the cache may enable the physical size of the cache—i.e., the area on the integrated circuit—to be smaller and to reduce the physical size of accompanying logic, e.g., comparators, again potentially enabling the capacity of the cache to be bigger, thereby improving its hit rate and improving the performance of the processor.

Another issue arises in the context of a system that includes multiple processors that share system memory and that each include a cache memory. In such systems, the processors must cooperate to ensure that when a processor reads from a memory address it receives the value most recently written to the address by any of the processors. For example, assume processors A and B each have a copy of a cache line at a memory address in their respective caches, and assume processor A modifies its copy of the cache line. The system needs to ensure that processor B receives the modified value when it subsequently reads from the address. This is commonly referred to as cache coherency.

A frequently employed protocol for attaining cache coherency is commonly referred to as a write-invalidate protocol that involves each processor snooping a shared bus used to access system memory. Using the example above, processor A broadcasts on the bus an invalidate transaction to announce that it intends to modify its copy of the cache line at the memory address. Processor B snoops the bus and sees the invalidate transaction. In response, processor B invalidates its copy of the cache line. When processor B later reads from the memory address, it broadcasts a read transaction on the bus. Processor A snoops the bus and sees the read transaction. In response, processor A provides the modified cache line to processor B and cancels the read transaction to the system memory. Processor A may also write back the modified cache line to system memory at this time.

As described above, cache memories hold and process other information besides the actual cache line data, some of which involves information for handling snooping the shared bus to attain cache coherency. By reducing the amount of cache coherence-related information held and processed by the cache, performance of the processor may be improved by increasing the speed of the cache and reducing its physical size.

SUMMARY

In one embodiment, the present disclosure provides a microprocessor that includes a physically-indexed physically-tagged second-level set-associative cache. Each entry in the second-level cache is uniquely identified by a set index and a way number of the second-level cache. The microprocessor also includes a store queue of entries. Each entry in the store queue holds information for a store instruction. The information includes store data to be written to a store physical address. A portion of the store physical address is a store physical line address. The information also includes a store physical address proxy (PAP) for the store physical line address. The store PAP specifies the set index and the way number of the entry in the second-level cache into which a cache line specified by the store physical line address is allocated. The microprocessor also includes a load unit configured to, during execution of a load instruction, use the store PAP held in an entry of the store queue in making a decision whether to forward to the load instruction the store data held in the entry of the store queue.

In another embodiment, the present disclosure provides a method for use in a microprocessor that includes a physically-indexed physically-tagged second-level set-associative cache. Each entry in the second-level cache is uniquely identified by a set index and a way number of the second-level cache. The microprocessor also includes a store queue of entries and a load unit. The method includes holding information for a store instruction in each entry of the store queue of entries. The information includes store data to be written to a store physical address. A portion of the store physical address is a store physical line address. The information also includes a store physical address proxy (PAP) for the store physical line address. The store PAP specifies the set index and the way number of the entry in the second-level cache into which a cache line specified by the store physical line address is allocated. The method also includes using, by the load unit during execution of a load instruction, the store PAP held in an entry of the store queue in making a decision whether to forward to the load instruction the store data held in the entry of the store queue.

In yet another embodiment, the present disclosure provides a non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a microprocessor. The microprocessor includes a physically-indexed physically-tagged second-level set-associative cache. Each entry in the second-level cache is uniquely identified by a set index and a way number of the second-level cache. The microprocessor also includes a store queue of entries. Each entry in the store queue holds information for a store instruction. The information includes store data to be written to a store physical address. A portion of the store physical address is a store physical line address. The information also includes a store physical address proxy (PAP) for the store physical line address. The store PAP specifies the set index and the way number of the entry in the second-level cache into which a cache line specified by the store physical line address is allocated. The microprocessor also includes a load unit configured to, during execution of a load instruction, use the store PAP held in an entry of the store queue in making a decision whether to forward to the load instruction the store data held in the entry of the store queue.

