BACKGROUND

The present disclosure relates in general to hardware with analog-digital mixed mode architecture that can be implemented to perform various operations and algorithms.

In some examples, computer systems can include hardware that can be implemented to perform various operations, such as multiplication, addition, multiply and accumulate (MAC) operations, or other polynomial related operations. The inputs to such hardware can be in digital form, and the hardware can include digital-to-analog converters (DACs) configured to convert the inputs into analog signals for further processing. MACs can be implemented with filters, such as reconstruction filters, to counter aliasing that can be caused by the conversion process.

SUMMARY

In some examples, a device for implementing multiple and accumulate (MAC) operations is generally described. The device can include a current mode digital-to-analog converter (DAC) configured to multiply an input digital signal with an input current to generate a current signal. The device can further include a current divider coupled to the current mode DAC. The current divider can be configured to divide the current signal into a plurality of currents. The device can further include a plurality of switches configured to sample the plurality of currents sequentially using the same clock frequency. The device can further include a circuit configured to combine the plurality of sampled currents to generate an output current signal

In some examples, a system for implementing multiple and accumulate (MAC) operations is generally described. The system can include a memory comprising a plurality of memory elements. The system can further include a device configured to be in communication with the memory. The device can include a plurality of circuit blocks connected to the plurality of memory elements. A circuit block can include a current mode digital-to-analog converter (DAC) configured to multiply an input digital signal with an input current to generate a current signal. The circuit block can further include a current divider coupled to the current mode DAC, the current divider being configured to divide the current signal into a plurality of currents. The circuit block can further include a plurality of switches configured to sample the plurality of currents sequentially using the same clock frequency. The circuit block can further include a circuit configured to combine the plurality of sampled currents to generate an output current signal. The circuit can be further configured to send the output current signal to a memory element connected to the circuit block.

In some examples, a method for implementing a multiply and accumulate (MAC) operation. The method can include multiplying an input digital signal with an input current to generate a current signal. The method can further include dividing the current signal into a plurality of currents. The method can further include sampling the plurality of currents sequentially using the same clock frequency. The method can further include combining the plurality of sampled currents to generate an output current signal

Further features as well as the structure and operation of various embodiments are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements.

