BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to an image sensor, and particularly relates to a column analog-to-digital converter (column ADC) and its local counting method.

2. Description of Related Art

A conventional CMOS image sensor (CMOS Image sensor, CIS) generally adopts a column analog-to-digital converter (CADC). CADC is usually composed of multiple successive-approximation register analog-to-digital converters (SAR ADC) or multiple single-slope analog-to-digital converters (single-slope ADC). Each single-slope ADC receives a column signal corresponding to a row of pixels, and the multiple single-slope ADCs share a digital-to-analog converter (DAC), a high-speed clock generator and a sense amplifier.

The single-slope ADC uses a counter to calculate an output length of the signal generated by comparing a ramp voltage and the column signal as the output of the ADC. Therefore, the resolution of the ADC depends on available counting time and a counting frequency. Nevertheless, the counting frequency is often limited by a loading of the clock tree, which increases the counting time at high resolution of ADC. In addition, the CADC counter is faced with a serious challenge of power consumption due to high counting frequency.

Since Correlated Double Sampling (CDS) and High Dynamic Range Imaging (HDR) are widely spread in the applications such as touch control, image sensing, and fingerprint recognition, it results in reduced available counting time. Moreover, the frame rate is limited by conversion time of ADC.

A conventional technology adopts phase delays to increase the resolution of ADC without raising the counting frequency. For example, 3 phase delays are added to the Least Significant Bit (LSB) of the high-speed clock. That is, the half cycle of bit[0] is cut into four equal parts, so as to add 2 bits to the resolution of ADC. However, the phase delay of the LSB is usually generated by a delay-locked loop (DLL) or a phase-locked loop (PLL), which would enlarge the layout area and the power consumption. Besides, different phase delays require a path balance in the layout to avoid increasing the differential nonlinearity (DNL) of the ADC, yet it will step up the difficulty of layout design.

Another conventional technology uses a local delay line to generate multiple phases in LSB, and a logic circuit determines which phase the transition time of an input signal locates in, so as to output the corresponding binary code according to the determination result. Nevertheless, it requires additional trim circuits to eliminate the PVT variation.

SUMMARY OF THE INVENTION

The invention provides a column analog-to-digital converter (CADC) with a local counting method which enables a local counting by means of a local delay circuit to improve the counting resolution.

An embodiment of the invention provides a column analog-to-digital converter. The column analog-to-digital converter includes a plurality of analog-to-digital converters in parallel. Each of the analog-to-digital converters includes a comparator and a counting circuit. The comparator compares the ramp voltage with one of the plurality of column signals to generate a comparator output signal. The counting circuit triggers a delay line circuit of the counting circuit to generate first delay data according to the comparator output signal, re-triggers the delay line circuit to generate first re-trigger delay data according to a base clock, and compares the first delay data with the first re-trigger delay data to generate a first counting output.

An embodiment of the invention provides a local counting method. A column analog-to-digital converter includes a plurality of analog-to-digital converters in parallel. The local counting method of the each analog-to-digital converter comprises as below. Each analog-to-digital converter compares a ramp voltage with one of column signals to generate a comparator output signal. Each analog-to-digital converter triggers a delay line circuit of the counting circuit to generate first delay data according to the comparator output signal. Each analog-to-digital converter re-triggers the delay line circuit to generate first re-trigger delay data according to a base clock. Each analog-to-digital converter compares the first delay data with the first re-trigger delay data to generate a first counting output.

Based on the above, in the embodiments of the invention, in order to cope with the frequency limit caused by a timing violation and a long wire and to reduce a system complexity, the embodiments of the invention provide a column analog-to-digital converter (CADC) with a local counting method which enables a local counting by means of comparing the triggered result and re-triggered result of a local delay line circuit, so as to raise the counting resolution and perform a self-compensation without trim circuits.

To make the above features and advantages of the invention more comprehensible, embodiments accompanied with drawings are described in detail as follows.

