FIELD

The present disclosure generally relates to a correction of a photomask pattern for fabricating a semiconductor device. More specifically, the present disclosure relates to a correction of a photomask pattern for fabricating a semiconductor device with a corrected photomask pattern.

BACKGROUND

Overlay control is critical in forming contact holes during photo-etching process in semiconductor manufacturing. Specifically, wafers are manufactured through a sequence of processes that each forms a pattern on the wafer to create various circuits with transistors, contacts, etc. To ensure functioning of all of the circuits, the patterns on the wafer must be aligned properly. In other words, contacts, lines and transistors on the wafer must be precisely lined up or overlapped with each other. Overlay control is referred to as the control of pattern-to-pattern alignment, and plays a critical role in monitoring layer-to-layer alignment on multi-layered semiconductor structures. Misalignment of the patterns may cause short circuits and connection failures, which in turn may impact fabrication yield and profit margins.

Overlay control has become increasingly more challenging due to the increase in pattern density and the reduction in pattern size on wafers. For example, small contact area of patterns increases overlay error (e.g., pattern is not properly aligned) and thus yields drop. Therefore, higher order overlay control is required to reduce the overlay errors. In other words, the overlay between two adjacent patterns needs to be precisely controlled.

SUMMARY

The present disclosure is directed to a method for correcting a designed pattern of a photomask for fabricating a semiconductor device and a method for fabricating a semiconductor device with a designed pattern of a photomask.

In a first aspect of the present application, a method for correcting a designed pattern of a photomask for fabricating a semiconductor device is provided. The method comprises providing a substrate of the photomask; conceiving a first mask pattern of the photomask designed to form a first contact pattern on the substrate, wherein the first mask pattern includes a plurality of mask holes each having a hole size; adjusting the first mask pattern to expand the hole sizes of the plurality of mask holes along a horizontal direction and to rotate the plurality of mask holes to conceive a second mask pattern of the photomask designed to form a second contact pattern having a plurality of contact holes; verifying a plurality of device gaps between the plurality of contact holes; and verifying an overlay margin between the second contact pattern and an adjacent pattern in the semiconductor device to determine the designed pattern of the photomask.

In a second aspect of the present application, a method for fabricating a semiconductor device with a designed pattern of a photomask is provided. The method comprises providing a substrate of the photomask; conceiving a first mask pattern of the photomask designed to form a first contact pattern on the substrate of the semiconductor device, wherein the first mask pattern includes a plurality of mask holes each having a hole size; adjusting the first mask pattern to expand the hole sizes of the plurality of mask holes along a horizontal direction and to rotate the plurality of mask holes to conceive a second mask pattern of the photomask designed to form a second contact pattern having a plurality of contact holes; verifying the plurality of contact holes of the second contact pattern; and photolithographing by using the second mask pattern of the photomask to generate a third contact pattern on the substrate.

