FIELD OF THE INVENTION

The present disclosure relates to a non-volatile transistor embedded in a memory cell, and more particularly, to a circuit and method for a non-volatile transistor embedded in a static random access memory (SRAM) cell and methods of operation.

BACKGROUND

Memory devices are employed as internal storage areas in a computer or other electronic equipment. One specific type of memory used to store data in a computer is random access memory (RAM). RAM is typically used as the major on-chip as well as off-chip storage unit in a computing system, and is generally volatile in that once power is turned off, all data stored in the RAM is lost.

A static random access memory (SRAM) is one example of RAM. An SRAM has the advantage of holding data without a need for refreshing. A typical SRAM device includes an array of individual SRAM cells. Each SRAM cell is capable of storing a binary voltage value that represents a logical data bit (e.g., “0” or “1”).

Charge trap transistor (CTT) based storage arrays are typically standalone arrays which have a large overhead area. For example, applications need both the advantages of a high speed SRAM and CTT non-volatile storage separate arrays, which can incur a high separate peripheral cost.

SUMMARY

In an aspect of the disclosure, a structure includes a latch circuit, a first non-volatile field effect transistor (FET) connecting to a first side of the latch circuit and a bit line, and a second non-volatile field effect transistor (FET) connecting to a second side of the latch circuit and a complementary bit line.

In another aspect of the disclosure, a circuit includes a latch circuit which comprises a first PMOS transistor in series with a first NMOS transistor and a second PMOS transistor in series with a second NMOS transistor, a first non-volatile transistor connected to the first PMOS transistor in series with the first NMOS transistor, a second non-volatile transistor connected to the second PMOS transistor in series with the second NMOS transistor, and a wordline connected to the first non-volatile transistor and the second non-volatile transistor.

In another aspect of the disclosure, a method includes writing data in at least one non-volatile field effect transistor (FET) of a memory bitcell circuit by changing a threshold voltage of the at least one non-volatile FET, and reading the data in the at least one non-volatile FET of the memory bitcell circuit by using differential sensing of the at least one non-volatile FET.

