BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to a memory device and an operating method thereof, and particularly relates to a memory device and a method for multiple physical cells error correction in the memory device.

Description of Related Art

In a usage of memory device, a multiple non-volatile memories (NVM) with different type memories which are integrated in a single chip, and the NVM respectively have different data retention and different cycling endurances in ECC message bits and ECC parity bits. For integrating the memories, a suitable ECC method is necessary for enhancing data reliability.

SUMMARY OF THE INVENTION

The disclosure is directed to multiple cells error correction method in a memory device and the memory device integrates a plurality of memory cells with different types of physical cells and a memory control circuit.

The disclosure provides the memory device includes a plurality of memory cells and a memory control circuit. Each of the memory cells includes a first type physical cell and a second type physical cell. The memory control circuit is coupled to each of the memory cells. The memory control circuit writes a writing data into the first type physical cell and verifies the data stored in the first type physical cell is same as the writing data or not. The writing data is set and processed by performing a write operation. The memory control circuit writes the writing data into the second type physical cell when the data stored in the first type physical cell is not same as the writing data.

The disclosure provides a method for a multiple cells error correction in a memory cell. The method comprising the steps of: performing a write operation by writing a writing data into a first type physical cell, verifying the data stored in the first type physical cell is same as the writing data or not, re-performing the write operation by writing the writing data into a second type physical cell when the data stored in the first type physical cell is not same as the writing data.

According to the above descriptions, the present disclosure provides the method for error correction on the first type physical cell by verifying the data stored in the first type physical cell is same as the writing data or not and re-performing the write operation by writing the writing data into a second type physical cell when the data stored in the first type physical cells is not same as the writing data, thus the multiple physical cells error correction in a memory cell is achieved. The multiple cells error correction method may apply to the memory device having different data retention and cycling endurance in the message bit and also to the memory device having different data retention and cycling endurance in the parity bit. Thus, a cycling rate of the memory device may be improved accordingly.

In order to make the aforementioned and other features and advantages of the invention comprehensible, several exemplary embodiments accompanied with figures are described in detail below.

