TECHNICAL FIELD

The present invention relates to a method of processing a wiring substrate that includes a configuration in which conductors locally disposed on a substrate are coated with resin having inorganic members that form a filler and are dispersed in an organic member, and the wiring substrate is preferably used for a multi-layer wiring substrate.

This application claims priority from Japanese Patent Application No. 2016-235054 filed on Dec. 2, 2016, the contents of which are incorporated herein by reference in their entirety.

BACKGROUND ART

As a method of processing a wiring substrate suitable to a multi-layer wiring substrate, for example, a method disclosed in Patent Document 1 or Patent Document 2 is known.

Patent Document 1 discloses a method of manufacturing a multi-layer wiring substrate by use of a ceramic wiring substrate as a base substrate. Particularly, paragraph 0078 of Patent Document 1 shows that, in the middle of a manufacturing process, there is a case where the foregoing multi-layer wiring substrate is covered with an insulating film and top surfaces of conductors are not exposed.

The above-mentioned situation is due to the reasons, such that a surface of a die cannot practically and completely be flat, a surface of a die is difficult to be completely brought into close contact with upper faces of wirings, heights of a wiring layer are difficult to be completely aligned with each other, or the like. Consequently, there is an explanation that the upper faces of the wirings are necessary to be exposed by removing a surface of an insulating film by a wet etching method, a dry etching method, a mechanical polishing method, or a method of combining the aforementioned methods. However, a specific solution is not disclosed in Patent Document 1.

Generally, the aforementioned insulating film does not have a simple structure made of a single member but is formed of resin having inorganic members that form a filler and are dispersed in an organic member. Therefore, as shown inFIG. 12, for example, in the case of sequentially removing the insulating film from a surface of the insulating film by carrying out dry etching, since the inorganic members and the organic member are etched together, the processed surface becomes a rough surface.

That is, in a state where the surface of the wiring layer is exposed, the surface of the wiring layer is not flatly exposed, residues (inorganic members or organic member) of the insulating film randomly remain on the surface of the wiring layer, and furthermore the surface of the wiring layer is in a state of being rough. For this reason, in the case where a coating is formed on the exposed wiring layer, the surface of the coating stacked on the wiring layer is also in a state of being rough. Therefore, in the case of manufacturing a multi-layer wiring substrate, since it is necessary to repeat the above-described steps at various times, the closer to the upper layer of the multilayer wiring structure the wiring layer is located, the less flat of the coating surface of the wiring layer is.

Patent Document 2 discloses a method of electroless plating a wiring layer. A first wiring layer and a solder resist layer in which acid soluble filler and acid insoluble filler which are made of an inorganic substance are mixed are provided on an insulating substrate in this order, the surface of the solder resist layer is subjected to plasma ashing and the both fillers thereby remain, and the surface of the solder resist layer is selectively removed. Thereafter, the acid soluble filler exposed from the surface of the solder resist layer is dissolved, the surface of the solder resist layer is subjected to roughening, and then a second wiring layer is electroless-plated using metal on the solder resist layer.

Consequently, according to the description of Patent Document 2, in the manufacturing method thereof, since a plurality of recesses are formed on the surface of the solder resist layer, the adhesion strength of the second wiring layer provided thereon is improved. That is, Patent Document 2 has an object to rough the surface of the solder resist layer and discloses a reverse technique to a method of planarizing the surface of the solder resist layer.

Currently, in multi-layer wiring substrates, there is a tendency that the number of stacked layers increases more than ever in order to increase a degree of integration per unit area. Therefore, as described above, a problem is becoming obvious in that the closer to the upper layer of the multilayer wiring structure the wiring layer is located, the less flat of the coating surface of the wiring layer is, and therefore a method of solving this has been developed.

PRIOR ART DOCUMENTS

Patent Documents

(Patent Document 1) Japanese Unexamined Patent Application, First Publication No. H09-241419(Patent Document 2) Japanese Unexamined Patent Application, First Publication No. H05-007079

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

The invention was made in view of the above-described conventional situation, and has an object to provide a method of processing a wiring substrate which can carry out a process so that the surfaces of exposed conductors and the surface of the resin surrounding the conductors are on the same plane in order to manufacture a layered structure.

Means for Solving the Problems

A method of processing the wiring substrate according to an aspect of the invention is a method of processing a wiring substrate that includes a configuration in which conductors locally disposed on a substrate are coated with resin having inorganic members that form a filler and are dispersed in an organic member, the method includes: removing the organic member from a surface layer side of the resin by use of an ashing method (step A); and removing, by use of a wet cleaning method, the inorganic members remaining the surface layer side of the resin from which the organic member is removed (step B).

In the method of processing the wiring substrate according to the aspect of the invention, removal of the organic member from the surface layer side of the resin may be repeatedly carried out via the resin located at a position at which the conductors are covered therewith until surface layer portions of the conductors is observed.

In the method of processing the wiring substrate according to the aspect of the invention, an ashing method used in removal of the organic member from the surface layer side of the resin may be carried out while applying high-frequency power to the substrate, and a bias RF output (W) of the high-frequency power may be 0 to 1500.

In the method of processing the wiring substrate according to the aspect of the invention, an ashing method used in removal of the organic member from the surface layer side of the resin may be carried out while applying high-frequency power to the substrate, and a bias RF output density (W/cm2) of the high-frequency power may be 0.2 to 0.8.

In the method of processing the wiring substrate according to the aspect of the invention, an ashing method used in removal of the organic member from the surface layer side of the resin may use, as a processing gas, a mixed gas containing a gas selected from the group consisting of oxygen (O2), nitrogen (N2), and carbon tetrafluoride (CF4).

In the method of processing the wiring substrate according to the aspect of the invention, a seed layer may be formed which serves foundation used to form conductors in a layered structure so that at least part thereof overlaps conductors having a surface layer portion that is exposed due to removal of the inorganic members (step C), and whether or not surfaces of the exposed conductors and a surface of resin surrounding the conductors are on the same plane may be evaluated by measuring a surface profile of the seed layer (step D).

Effects of the Invention

An aspect of the invention is a method of processing a wiring substrate that includes a configuration in which conductors locally disposed on a substrate are coated with resin having inorganic members that form a filler and are dispersed in an organic member.

In the processing method according to the aspect of the invention, firstly, by removing the organic member from the surface layer side of the resin by use of an ashing method, the organic member is only removed while leaving inorganic members of the resin until reaching a desired depth. By carrying out the above-described removal of the organic member in multiple steps (a plurality of times), the removal of the organic member gradually proceeds until a state where the organic member is only removed is obtained at a deeper position of the resin. Subsequently, until a state where the organic member is only removed is obtained at the surfaces of the conductors locally disposed on the substrate, the removal of the organic member from the surface layer side of the resin (step A) is repeatedly carried out.

As a result, a state is obtained where organic member does not mostly remain in the resin located above the surfaces of the conductors and inorganic members forming a filler only remain. On the other hand, the resin located lower than the surfaces of the conductors is in a state of not being changed from before ashing is carried out, that is, a state is maintained where the inorganic members forming a filler are dispersed in the organic member.

Next, in the aspect of the invention, after the organic member is removed from the surface layer side of the resin by use of a wet cleaning method (after step A), the inorganic members that remain at the surface layer of the resin are removed. Therefore, the inorganic members that form a filler and remain in the resin located above the surfaces of the conductors are removed by wet cleaning. On the other hand, the resin located lower than the surfaces of the conductors is in an original state, that is, it is maintained in a state where the inorganic members forming a filler are dispersed in the organic member without being affected by wet cleaning.

Accordingly, the aspect of the invention contributes to provision of a method of processing a wiring substrate which can carry out a process so that the surfaces of exposed conductors and the surface of the resin surrounding the conductors are on the same plane in order to manufacture a layered structure.

