CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to Korean Patent Application No. 10-2019-0178427, filed on Dec. 30, 2019, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field

Various embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device and a method for fabricating the same.

2. Description of the Related Art

Recently, the size of the memory cell continues to be reduced in order to increase the net die of a memory device.

As the size of memory cells becomes miniaturized, parasitic capacitance Cb decreases and capacitance increases. However, it is difficult to increase the net die due to the structural limitations of memory cells.

SUMMARY

Embodiments of the present invention are directed to highly integrated memory cells, a memory device including the integrated memory cells, and a method for fabricating the memory device.

In accordance with an embodiment of the present invention, a memory device includes a substrate; an active layer that is spaced apart from the substrate and laterally oriented, a word line that is laterally oriented in parallel to the active layer along one side of the active layer, an active body that is vertically oriented by penetrating through the active layer, a bit line that is vertically oriented by penetrating through the active layer to be spaced apart from one side of the active body, and a capacitor that is vertically oriented by penetrating through the active layer to be spaced apart from another side of the active body.

In accordance with another embodiment of the present invention, a memory device includes memory cells arranged vertically, wherein each of the memory cells includes an active layer including a first source/drain region, a second source/drain region, and a channel body laterally oriented between the first source/drain region and the second source/drain region, a word line laterally oriented in parallel to one side of the active layer, an active body penetrating through the channel body, a bit line vertically oriented by penetrating through the active layer to be coupled to the first source/drain region, and a capacitor vertically oriented by penetrating through the active layer to be coupled to the second source/drain region.

In accordance with yet another embodiment of the present invention, a method for fabricating a memory device includes forming a plurality of active layers arranged vertically with respect to a substrate, forming a vertically oriented active body that penetrates through the active layers to interconnect the active layers to each other, forming a vertically oriented bit line that is spaced apart from one side of the active body and penetrates through the active layers, forming a vertically oriented capacitor that is spaced apart from another side of the active body and penetrates through the active layers, and forming a plurality of word lines that are laterally oriented adjacent to one side of each of the active layers.

These and other features and advantages of the present invention will become apparent to those with ordinary skill in the art of the invention from the following detailed description and drawings.

