CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No. 10-2018-0168376, filed on Dec. 24, 2018, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field

Various embodiments of the present invention relate generally to a semiconductor device and, more particularly, to a semiconductor device including a test pattern structure. The present invention also relates to a method for manufacturing the semiconductor device.

2. Description of the Related Art

While a semiconductor device is fabricated, a process of forming a thin film and/or a process of etching the thin film may be performed several times. Various treatments using plasma may be used for the process of forming a thin film and the process of etching the thin film.

In the plasma treatments, a line layer electrically connected to a gate electrode may collect charges from the plasma. As a result, a plasma-induced damage (PID) may occur in the gate dielectric layer.

Also, typically, when a semiconductor device is developed, the characteristics of a transistor may be checked by using a test pattern. However, it is still difficult to avoid the plasma-induced damage (PID) that may occur when the test pattern is formed.

Therefore, it is required to develop improved technology capable of preventing plasma induced damage during the testing of a transistor.

SUMMARY

Various embodiments of the present invention are directed to a semiconductor device capable of preventing a plasma-induced damage.

In accordance with an embodiment of the present invention, a semiconductor device includes: a test element; a test pattern structure; and a protection element which is operatively positioned between the test pattern structure and the test element for protecting the test element from a plasma induced damage.

In accordance with an embodiment of the present invention, a method for fabricating a semiconductor device includes forming a test transistor over a first region of a substrate; forming a protection transistor coupled to the test transistor and the protection transistor is formed over a second region of the substrate; and forming a test pattern structure coupled to the protection transistor and the test pattern structure is formed over the protection transistor, wherein a plasma-induced damage caused from the test pattern structure is discharged to the substrate through the protection transistor.

These and other features and advantages of the present invention will become better understood from the following detailed description of preferred embodiments in conjunction with the accompanying drawings.

