BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method for fabricating semiconductor device, and more particularly to a method for fabricating a dynamic random access memory (DRAM) device.

2. Description of the Prior Art

As electronic products develop toward the direction of miniaturization, the design of dynamic random access memory (DRAM) units also moves toward the direction of higher integration and higher density. Since the nature of a DRAM unit with buried gate structures has the advantage of possessing longer carrier channel length within a semiconductor substrate thereby reducing capacitor leakage, it has been gradually used to replace conventional DRAM unit with planar gate structures.

Typically, a DRAM unit with buried gate structure includes a transistor device and a charge storage element to receive electrical signals from bit lines and word lines. Nevertheless, current DRAM units with buried gate structures still pose numerous problems due to limited fabrication capability. Hence, how to effectively improve the performance and reliability of current DRAM device has become an important task in this field.

SUMMARY OF THE INVENTION

According to an embodiment of the present invention, a method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.

According to another aspect of the present invention, a buried word line of a dynamic random access memory (DRAM) includes a gate structure in a substrate. Preferably, the gate structure further includes: a first conductive layer on the substrate; a second conductive layer on the first conductive layer, wherein the second conductive layer comprises a horizontal portion and two vertical portions and the horizontal portion and one of the two vertical portions comprise different thickness; and a third conductive layer on the second conductive layer.

According to yet another aspect of the present invention, a buried word line of a dynamic random access memory (DRAM) includes a gate structure in a substrate. Preferably, the gate structure includes: a first conductive layer in the substrate; a second conductive layer on the first conductive layer, wherein the second conductive layer is I-shaped; and a third conductive layer on the second conductive layer.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

