CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. Patent Application titled RISC PROCESSOR HAVING SPECIALIZED REGISTERS, Ser. No. 16/941,499, filed herewith, which is incorporated herein by reference in its entirety for all purposes.

TECHNICAL FIELD

The subject matter described herein relates to a RISC processor architecture, and more particularly to a RISC processor architecture having a data path interacting with specialized registers.

BACKGROUND

RISC processors typically have a number of registers which act as temporary memory storage locations for calculations performed by data path circuits. The registers are used for storing various types of calculation variables for the data path calculations, and are therefore each configured to be used for each type of calculation variable. Because each register is capable of being used for each type of calculation variable, each register is implemented in a register file circuit having all of the features needed for each of the calculation variables. Accordingly, the data path interacts with each type of register file identically. Registers requiring less die area and data paths interacting therewith are needed in the art.

SUMMARY

One inventive aspect is a data path block circuit. The data path block circuit includes a first data path circuit having a plurality of a logic circuits, each configured to receive data to be used as first and second operands, and to perform a data path operation to generate a result based on the first and second operands. The data path block circuit also includes a first operand multiplexer, having a first plurality of data inputs, each connected to one of a first register file, including a first quantity of read and write ports, and a second register file, including a second quantity of read and write ports, where the first quantity of read and write ports is different from the second quantity of read and write ports. The data path block circuit also includes a second operand multiplexer, having a second plurality of data inputs, each connected to one of the first register file, and the second register file, where at least one of the first operand multiplexer and the second operand multiplexer includes a data input connected to the first register file. At least one of the first operand multiplexer and the second operand multiplexer includes a data input connected to the second register file.

In some embodiments, the data path block circuit includes an operation signal port configured to receive an operation signal including data identifying a first read port of one of the first and second register files for the first operand, and a second read port of one of the first and second register files for the second operand, where the first operand multiplexer is configured to receive data identifying the first read port and to select a first data input based on the received data identifying the first read port, and where the second operand multiplexer is configured to receive data identifying the second read port and to select a second data input based on the received data identifying the second read port.

In some embodiments, the first read port is connected to the first register file, and the second read port is connected to the second register file.

In some embodiments, the first operand multiplexer is configured to provide data from the first data input to the first data path circuit as the first operand, and the second operand multiplexer is configured to provide data from the second data input to the first data path circuit as the second operand.

In some embodiments, the operation signal further identifies a particular data path operation of the first data path circuit, and the first data path circuit is configured to select a particular logic circuit based on the operation signal.

In some embodiments, the selected particular logic circuit is configured to perform the particular data path operation on the first and second operands to generate the result.

In some embodiments, the operation signal further identifies a particular write port for the result, and where the first data path circuit is configured to provide the result to the particular write port.

In some embodiments, the first read port is connected to the first register file, and the second read port is connected to the second register file.

In some embodiments, the first read port and the second read port are connected to the first register file, and the particular write port is connected to the second register file.

In some embodiments, the data path block circuit includes a second data path circuit including a plurality of logic circuits, each configured to receive data to be used as third and fourth operands, and to perform a second data path operation to generate a second result based on the third and fourth operands, and an operation signal port configured to receive an operation signal identifying a first read port of one of the first and second register files for the third operand, and a second read port of one of the first and second register files for the fourth operand.

In some embodiments, the first read port is connected to the first register file, and the second read port is connected to the second register file.

In some embodiments, the operation signal further identifies a particular data path operation of the second data path circuit, and the second data path circuit is configured to select a particular logic circuit based on the operation signal.

In some embodiments, the selected particular logic circuit is configured to perform the particular data path operation on the third and fourth operands to generate the result, the operation signal further identifies a particular write port for the result, and the second data path circuit is configured to provide the result to the particular write port.

In some embodiments, the first read port is connected to the first register file, and the second read port is connected to the second register file.

In some embodiments, the first read port and the second read port are connected to the first register file, and the particular write port is connected to the second register file.

Another inventive aspect is a method of using a data path block circuit. The method includes receiving an operation signal including data identifying a first read port of one of first and second register files for a first operand, and identifying a second read port of one of the first and second register files for a second operand, where the first register file includes a first quantity of read and write ports, where the second register file includes a second quantity of read and write ports, and where the first quantity of read and write ports is different from the second quantity of read and write ports. The method also includes, with a first operand multiplexer, receiving data from the operation signal identifying the first read port, with the first operand multiplexer, selecting a first data input based on the received data identifying the first read port, with a second operand multiplexer, receiving data from the operation signal identifying the second read port, with the second operand multiplexer, selecting a second data input based on the received data identifying the second read port, with a logic circuit of a first data path circuit, receiving data from the first and second operand multiplexers to be used as first and second operands, and with the logic circuit, and performing a data path operation to generate a result based on the first and second operands, where at least one of the first operand multiplexer and the second operand multiplexer includes a data input connected to the first register file, and where at least one of the first operand multiplexer and the second operand multiplexer includes a data input connected to the second register file.

In some embodiments, the method also includes, with the first operand multiplexer, providing data from the first data input to the logic circuit as the first operand, and with the second operand multiplexer, providing data from the second data input to the logic circuit as the second operand.

In some embodiments, the operation signal further identifies a particular write port for the result, and the method further includes, with the logic circuit providing the result to the particular write port.

In some embodiments, the first read port is connected to the first register file, and the second read port is connected to the second register file.

In some embodiments, the first read port and the second read port are connected to the first register file, and the particular write port is connected to the second register file.

