CROSS-REFERENCE TO RELATED APPLICATION

This application claims benefit of priority to Korean Patent Application No. 10-2019-0055468 filed on May 13, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to a semiconductor package, for example, to a fan-out semiconductor package.

BACKGROUND

As smart electronic devices have been developed in recent years, specifications of components used in the device have also advanced. For example, specifications of an application processor (AP), a key component of a smart electronic device, have rapidly advanced. Various methods have been used for advanced performance of the AP, and a functional partitioning of the AP is one recent method. For example, when partitioning a semiconductor chip die of the AP for each function, and then designing and packaging each semiconductor chip to be optimized for process and features thereof, the AP may implement more advanced performance than a conventional single AP. However, in this case, a high-level packaging method is required. Therefore, there is demand for a semiconductor package structure in which a plurality of partitioned semiconductor chips may be packaged to have optimal signal and power characteristics.

SUMMARY

An aspect of the present disclosure may provide a new type of a semiconductor package having a structure in which a plurality of semiconductor chips may be packaged to have optimal signal and power characteristics.

According to an aspect of the present disclosure, there may be provided a semiconductor package having a structure in which a plurality of semiconductor chips are disposed after being partitioned into upper and lower packages based on specifications thereof and then the semiconductor chip of the lower package transmits power to the semiconductor chip of the upper package through a through via penetrating through the semiconductor chip of the lower package.

According to an aspect of the present disclosure, a semiconductor package may include: a the first semiconductor package including: a first frame having a first through portion, a first semiconductor chip disposed in the first through portion of the first frame and having a first surface on which a first connection pad is disposed and a second surface opposing the first surface and on which a second connection pad is disposed, and a through via connected to the second connection pad, a first connection structure disposed on the first surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pad of the first semiconductor chip, and a backside redistribution layer disposed on the second surface of the first semiconductor chip and electrically connected to the second connection pad of the first semiconductor chip; and a second semiconductor package disposed on the first semiconductor package and including: a second connection structure including a second redistribution layer electrically connected to the first redistribution layer, a second frame disposed on the second connection structure and having a second through portion, and a second semiconductor chip disposed in a second through portion of the second frame and having a third surface on which a third connection pad is disposed, the third connection pad electrically connected to the second redistribution layer.

