CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority based on Japanese Patent Application No. 2020-005051 filed Jan. 16, 2020, the content of which is incorporated herein by reference.

BACKGROUND

Field of the Invention

The present invention relates to a semiconductor device.

Description of Related Art

A semiconductor device such as a flash memory includes a page buffer circuit for parallel access for reading or writing of data in units of pages that are predetermined data lengths and access is allowed in units of pages (for example, refer to Japanese Unexamined Patent Application, First Publication No. 2000-100181).

SUMMARY

However, in such a semiconductor device in the related art described above, for example, a bit line of a memory cell and the page buffer circuit are connected to each other through a wiring on a flat surface of a semiconductor chip. Therefore, the data length that can be access in parallel is restricted by a wiring pitch on the flat surface. For this reason, in the semiconductor device in the related art, it is difficult to increase an access speed.

An object of an aspect of the present invention is to provide a semiconductor device capable of increasing an access speed.

An aspect of the present invention is a semiconductor device including: a memory semiconductor chip having a plurality of memory cells; a planar buffer chip which is a semiconductor chip that comprises a plurality of buffer circuits which hold data read from the memory cell and data written to the memory cell and which output the held data in accordance with the number of bit lines of the plurality of memory cells; an electrical connection structure which electrically connects the bit lines of the memory cells of the memory semiconductor chip and the buffer circuits of the planar buffer chip to each other in a thickness direction of the memory semiconductor chip and the planar buffer chip; and a plurality of bit wiring layers provided in accordance with the respective buffer circuits and electrically connected to the bit lines of the buffer circuits. The bit wiring layers are laminated on the planar buffer chip.

In the foregoing semiconductor device, on the planar buffer chip, the bit wiring layers respectively provided for the bit lines of the buffer circuits may be laminated through interlayer insulating layers.

The foregoing semiconductor device may further include a buffer decoder part which selectively connect one of the bit lines of a predetermined number of the memory cells with the buffer circuit.

In the foregoing semiconductor device, in the memory semiconductor chip, a plurality of semiconductor tips including the memory cells may be laminated in the thickness direction, and the electrical connection structure may electrically connects the laminated semiconductor tips with the planar buffer chip.

In the foregoing semiconductor device, the electrical connection structure may include a penetration electrode which penetrates the memory semiconductor chip and the planar buffer chip in the thickness direction and connects the memory semiconductor chip to the planar buffer chip using a conductor.

According to an aspect of the present invention, an access speed can be increased.

