CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0067560 filed in the Korean Intellectual Property Office on Jun. 4, 2020, the entire contents of which are incorporated herein by reference.

BACKGROUND

Technical Field

The present disclosure relates to a memory device which operates by sampling a sneak current and canceling the sampled sneak current. This work was supported in part by the Ministry of Trade, Industry and Energy under Grant 10080590, in part by the Korea Semiconductor Research Consortium Support Program for the Development of the Future Semiconductor Device (NO. K_G011008059005) .

Description of the Related Art

The contents described in this section merely provide background information on the exemplary embodiment of the present disclosure, but do not constitute the related art.

A DRAM is a volatile memory which has a fast processing speed, but cannot permanently store data and a NAND flash memory has a non-volatility, but has a slow processing speed. A resistive random access memory (also, referred to as a RRAM) is a memory with a new structure which is expected to have both a fast processing speed of the DRAM and a non-volatility of the NAND flash and have a high capacity beyond both the DRAM and NAND flash.

According to an operating principle of the RRAM, data is stored by means of a resistance by allowing an element to be in a high resistance state or a low resistance state.

Among the RRAM, as compared with an RRAM which imitates a structure of the existing DRAM to have a unit memory cell with one transistor and one resistor (1T1R) structure, a crossbar RRAM having a unit memory cell with one selector and one resistor (1S1R) structure is expected to drastically increase a capacity.

However, in the case of the crossbar RRAM, a current which flows through an unselected cell cannot be perfectly controlled due to an incomplete switch characteristic so that it has a sneak current problem which flows through an unselected cell. Specifically, the sneak current causes a serious problem when a read operation of data stored in the memory is performed.

In order to read data stored in the RRAM, after applying a predetermined voltage to a selected cell, a current which flows through the selected cell is sensed to determine a resistance of the corresponding cell. However, in this case, not only the current flowing through the selected cell, but also a current (a sneak current) flowing through the unselected cell is sensed so that exact data cannot be read.

A magnitude of the sneak current is proportional to a capacity of the RRAM and in order to suppress the data read error, the sneak current needs to be reduced by reducing the capacity so that the sneak current makes it difficult to make an RRAM with a large capacity.

As a general read scheme for a crossbar RRAM, a floating read scheme which select only one cell by applying voltages (a read voltage VR and a sensing voltage VSS) to only one bit line and one word line is used.

However, in order to reduce a data read error due to the sneak current, a new read scheme specified to the RRAM has been proposed. Among them, as a representative scheme, there is a V/2 read scheme which applies half the voltage ((VR−VSS)/2) to all unselected beat lines and word lines, differently from the floating read scheme. Even though in the floating read scheme, the sneak current flowing through all unselected cells is added to the current of the selected cell to be sensed, according to the V/2 read scheme, only a current flowing through cells connected to the bit line to which the VR is applied is added to the current of the selected cell to be sensed. Therefore, it is advantageous in that an amount of sneak current which is undesirably sensed is reduced, but it is disadvantageous in that a consumed power is several tens of times larger than that of the floating read scheme.

According to both the schemes, the read voltage VR and the sense voltage VSS are applied to the selected bit line and word line to sense a current flowing to a point (a read point) applied with a sensing voltage to read data stored in the selected cell.

According to the VR read scheme, in order to reduce a sneak current flowing into a sensing point, VR/2 is applied to all bit lines and word lines which are not selected, to allow only the sneak current flowing through cells connected to the selected bit line to flow into the read point. Accordingly, the remaining cells which are connected to the selected word lines do not affect the read operation so that the influence of the sneak current is comparatively reduced. However, since a forward bias is applied to these cells so that a lot of current flows, according to the V/2 read scheme, the power consumption is large.

In contrast, according to the floating read scheme, a voltage is not applied to all unselected bit lines and word lines, but the unselected bit lines and word lines are floated, so that a reverse current which is significantly smaller than the forward current is applied to all the unselected cells, thereby significantly reducing the power consumption. However, all the reverse current flowing through all the unselected cells is sensed at the read point, so that a possibility of causing a data read error may be increased.

SUMMARY

A main object of the present disclosure is to provide a memory device which samples a sneak current using a dummy cell by a first switching control step and cancels the sampled sneak current by a second switching control step to cancel a sneak current which reads data stored in the memory cell.

According to an aspect of the present disclosure, in order to achieve the above-described object, a memory device includes: a memory cell array which includes a plurality of word lines and a plurality of bit lines intersecting each other and memory cells disposed at intersections of the word lines and the bit lines; and a sensing circuit which supplies a bit line current to all or some of the bit lines, cancels a sneak current based on the bit line current by at least one switching control, and senses and amplifies data stored in the memory cell to output the sensed and amplified data.

As described above, according to the present disclosure, a problem in that a read failure in a read operation is increased due to the sneak current in a cross-point array structure can be solved.

Further, according to the present disclosure, a problem in that read failure is increased due to an offset voltage in a sensing circuit of a memory device may be solved.

Further, according to the present disclosure, the sneak current is identified without using a current mirror so that the sneak current may be exactly identified without causing a sneak current variation due to threshold voltage mismatching (Vth mismatch) of a current mirror.

Further, according to the present disclosure, in a reference current and read current generating and transmitting path, a sensing circuit is configured using the same transistor so that the read failure probability of a voltage variation in the reference current and read current path may be significantly reduced.

