BACKGROUND

Field

This disclosure relates generally to phase locked loops, and more specifically, to a built-in self-test (BIST) for an all-digital phase locked loop allowing functional tests of analog components.

Related Art

Phase-locked loop (PLL) circuits and, in many applications, all-digital PLLs (ADPLL) are used in a wide variety of high frequency applications, including, for example, clock generation, clock clean-up circuits, local oscillators for high performance radio communication links, and ultrafast switching frequency synthesizers in vector network analyzers. A PLL is a feedback system that combines a controlled oscillator and a phase comparator connected in a matter that the oscillator maintains a constant phase angle relative to a reference signal. An ADPLL incorporates a digitally-controlled oscillator (DCO) controlled by a digital control loop and feedback path that includes a time-to-digital converter and at least one divider. In a typical configuration, a PLL compares the phase of the reference signal to the phase of an adjustable feedback signal. When the comparison is in a steady state, and the output frequency and phase are matched to the incoming frequency and phase of a phase detector, the PLL is said to be locked.

Well-designed ADPLLs are characterized by high performance, but production testing and field testing of the ADPLL can be complex and resource intensive. Typical ADPLL production testing can include functional testing of the analog parts of the circuitry executed using testers external to a system on a chip (SoC) incorporating the ADPLLs. Support blocks on the ADPLL can impact the size of the ADPLL. In addition, with externally-controlled testing it is impossible to conduct testing in the field or by customers incorporating SoCs into their products. It is therefore desirable to provide a built-in self-test mechanism that provides a reliable test of an ADPLL and that is located completely on chip without need for external support.

