BACKGROUND

Power consumption continues to be a driver for development in memory and logic circuits. To that end, research in magnetoelectric systems with electrical control of magnetic properties including, but not limited to, spin polarization, magnetic ordering, and magnetic anisotropy, has resulted in identification of device structures with behavior that indicate the suitability of magnetoelectric devices as a practical alternative to conventional CMOS (complementary metal oxide semiconductor) devices.

With the identification of magnetoelectric device structures, attention has now turned to how to use and configure these devices for logic operations.

BRIEF SUMMARY

Circuits based on magnetoelectric (ME) transistor devices are described herein. ME transistor devices can be in the form of ME field-effect transistors (ME-FETs). The ME-FETs can be anti-ferromagnetic spin-orbit read (AFSOR) devices or non-AFSOR devices. The circuits described herein can form logic gates (e.g., inverter, XOR, XNOR, majority gate), which can further be combined, and even optimized, to form a variety of more complex logic circuits such as a full adder.

The gates and logic circuits described herein can be included as standard cells in a design library. For example, a computer-readable storage medium can have stored thereon a cell library, where the cell library includes instructions for representing and optionally simulating devices when executed by a computing device. Cells of the cell library can include standard cells for a ME inverter device, a ME minority gate device, a ME majority gate device, a ME full adder, a ME XNOR device, a ME XOR device, or a combination thereof.

In some cases, a ME logic gate device can include at least one conducting device; and at least one ME transistor coupled to the at least one conducting device. The conducting device can include two-terminal devices such as a resistor as well as multi-terminal devices such as MOS, bipolar transistors and ME-FET.

In some cases, the ME logic gate device can include at least one CMOS logic gate, such as a CMOS inverter; and at least one ME transistor coupled to the CMOS logic gate. In some cases, a CMOS inverter can be coupled to a source terminal of a ME transistor in order to drive the ME transistor.

A ME-XNOR device is provided that includes a conducting device and a ME transistor. When the conducting device is in the form of a pull-up transistor, the pull-up transistor can be coupled to receive a clocking signal at a gate terminal and coupled at a source terminal to a voltage source. The ME transistor can include a split gate, with a first gate terminal coupled to a first portion of the split gate for receiving a first input signal, a second gate terminal coupled to a second portion of the split gate for receiving a second input signal, a source terminal coupled to a ground line, and a drain terminal coupled to a drain terminal of the pull-up transistor.

A ME majority gate device is provided that includes a conducting device, a ME AND gate device, a ME-transmission gate, and a ME-XNOR gate device. When the conducting device is in the form of a pull-up transistor, the pull-up transistor can be coupled to receive a clocking signal at a gate terminal and coupled at a source terminal to a voltage source. The ME AND gate has a downward interface polarization and can include a gate, a first terminal coupled to the gate for receiving a first input signal, a second terminal coupled to the gate for receiving a second input signal, a source terminal coupled to a ground line, and a drain terminal coupled to a drain terminal of the pull-up transistor. The ME-transmission gate also has downward interface polarization and can include a gate terminal coupled to receive a third input signal, a drain terminal coupled to the drain of the pull-up transistor, and a source terminal. The ME-XNOR gate device can include a split gate with a first gate terminal coupled to a first portion of the split gate for receiving the first input signal, a second gate terminal coupled to a second portion of the split gate for receiving the second input signal, a source terminal coupled to the ground line, and a drain terminal coupled to the source terminal of the ME-transmission gate device.

A ME full adder device is provided that can include a ME majority gate device and a stacked ME-XNOR device. The ME majority gate device can be coupled to receive a first input signal, a second input signal, and a third input signal and output a “carry” signal. The stacked ME-XNOR device can include a first ME-XNOR device and a second ME-XNOR device. The first ME-XNOR device can be coupled to receive the first input signal and second input signal and output an intermediate signal. The second ME-XNOR device can be coupled to receive a third input signal and the intermediate signal and output a “sum” signal.

This Summary is provided to introduce a selection of concepts, in a simplified form, that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

