CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from European Patent Application No. 18181015.1 filed Jun. 29, 2018. The entire contents of the prior application are incorporated herein by reference.

The present invention relates to interface circuits, for example forming part or all of an output stage (driver) and/or an input stage (receiver) of signal processing circuitry.

Such an output stage, for example of a digital-to-analogue converter (DAC), may be configured to drive a signal (i.e. an analogue signal) over a transmission line. Such an input stage, for example of an analogue-to-digital converter (ADC), may be configured to receive or recover a signal (i.e. an analogue signal) from a transmission line. Interface circuits may thus form part of a DAC or ADC. DACs and ADCs are of course merely convenient examples of signal processing circuitry. Interface circuits and circuitry comprising them may be implemented as integrated circuitry, for example on are IC chip.

Interface circuits in the context of an output stage may thus comprise driver circuitry along with additional circuitry for connection to a transmission line. Interface circuits in the context of an input stage may thus comprise buffering circuitry along with additional circuitry for connection to a transmission line.

Existing interface circuits have been found to be unsatisfactory, particularly in the context of high-speed input and output stages where wideband performance is key. With increasing speeds of e.g. DACs and ADCs, there is ever increasing pressure on performance of interface circuits.

According to an embodiment of a first aspect of the present invention, there is provided an interface circuit, comprising: a signal line having signal, auxiliary and connection nodes defined therealong, the connection node for connection to a transmission line; signal-handling circuitry connected to the signal line at the signal node so that an effective capacitance of the signal-handling circuitry is experienced (e.g. presented or applied) at the signal node; an auxiliary circuit connected to the signal line at the auxiliary node so that an effective capacitance of the auxiliary circuit is experienced (e.g. presented or applied) at the auxiliary node; a signal pair of inductors connected in series along the signal line (e.g. immediately) adjacent to and either side of the signal node; and an auxiliary pair of inductors connected in series along the signal line (e.g. immediately) adjacent to and either side of the auxiliary node, wherein: the signal pair of inductors are configured to have a mutual coupling defined by a coupling coefficient kS; the auxiliary pair of inductors are configured to have a mutual coupling defined by a coupling coefficient kA; for each said pair of inductors, the inductors of the pair are arranged such that a current flowing along the signal line in a given direction through one of those inductors induces a current in the other one of those inductors and flowing in the same direction along the signal line given a positive coupling coefficient; and kS has a positive value and kA has a negative value.

Such inductor arrangements can enable the effective capacitance of the signal-handling circuitry and of the auxiliary circuit to be compensated for to ensure wideband performance (taking into account a number of performance measures together, as explained later) of circuitry comprising the interface circuit.

In alternative arrangements, kS and kA may have other polarities. That is, in other arrangements kS and kA may both have positive values, or kS and kA may both have negative values. In other arrangements kS and kA may simply have opposite polarities from one another—i.e. kS may have a positive value and kA may have a negative value, or kS may have a negative value and kA may have a positive value in those arrangements. Such other combinations of polarities may have particular associated advantages.

The auxiliary node may be defined along the signal line between the signal and connection nodes; and/or the signal pair of inductors may be connected along the signal line (e.g. immediately) adjacent to the auxiliary pair of inductors; and/or the auxiliary pair of inductors may be connected along the signal line (e.g. immediately) adjacent to the connection node.

The auxiliary circuit may be an electrostatic discharge protection circuit. For example, the auxiliary circuit may comprise a network of diodes.

The coupling coefficients kS and kA may both have a magnitude greater than 0.1; and/or the coupling coefficients kS and kA both have a magnitude between 0.1 and 0.4. The performance may be particularly advantageous within these ranges.

The effective capacitance of the signal-handling circuitry may be larger than the effective capacitance of the auxiliary circuit, the inductances of the signal pair of inductors may be larger than the inductances of the auxiliary pair of inductors, and the magnitude of kS may be greater than the magnitude of kA. For example, the effective capacitance of the signal-handling circuitry may be at least twice the effective capacitance of the auxiliary circuit, the inductances of the signal pair of inductors may be at least twice the inductances of the auxiliary pair of inductors, and the magnitude of kS may be at least twice the magnitude of kA.

The connection node may be configured as a signal pad, such as a bond pad.

The signal line may further have a termination node defined therealong, and the interface circuit may comprise a termination resistor connected to the signal line at the termination node. The termination node may be defined along the signal line on the opposite side of the signal node from the auxiliary node.

For example, the termination resistor, signal-handling circuit and auxiliary circuit may each be connected between the relevant node of the signal line and ground (e.g. RF ground).

It may be that bridging capacitors are not provided to bridge each of the pairs of inductors.

The interface circuit may be a differential circuit comprising positive and negative said signal lines each having its own set of said nodes and pairs of inductors, for connection to a differential transmission line at the connection nodes of the positive and negative signal lines. The coupling coefficients for the pairs of inductors of the positive signal line may have the same polarities as the corresponding coupling coefficients for the corresponding pairs of inductors of the negative signal line.

For example, the termination resistor, signal-handling circuit and auxiliary circuit may each be connected between the relevant nodes of the positive and negative signal lines.

The coupling coefficients for the pairs of inductors of the positive signal line may be substantially the same as the corresponding coupling coefficients for the corresponding pairs of inductors of the negative signal line.

The signal-handling circuitry may be connected to the positive and negative signal lines at their signal nodes; and the auxiliary circuit may be connected to the positive and negative signal lines at the auxiliary nodes of those signal lines.

The signal-handling circuitry may be: driver circuitry for driving an output signal on the signal line or on the positive and negative signal lines; and/or buffer circuitry for receiving an input signal from the signal line or from the positive and negative signal lines.

According to an embodiment of a second aspect of the present invention, there is provided a signal transmission system, comprising: a transmission line having first and second ends; a first interface circuit being an interface circuit of the aforementioned first aspect of the present invention and connected to the transmission line at its first end; and a second interface circuit being an interface circuit of the aforementioned first aspect of the present invention and connected to the transmission line at its second end.

That is, the first interface circuit may be an interface circuit comprising driver circuitry for driving an output signal on the signal line or on the positive and negative signal lines, and ultimately the transmission line, and the second interface circuit may be an interface circuit comprising buffer circuitry for receiving an input signal from the signal line or from the positive and negative signal lines, and ultimately from the transmission line.

According to an embodiment of a third aspect of the present invention, there is provided an output circuit for use in digital-to-analogue converter circuitry, the output circuit comprising the interface circuit of the aforementioned first aspect of the present invention.

According to an embodiment of a fourth aspect of the present invention, there is provided digital-to-analogue converter circuitry comprising the output circuit of the aforementioned third aspect of the present invention.

According to an embodiment of a fifth aspect of the present invention, there is provided an input circuit for use in analogue-to-digital converter circuitry, the input circuit comprising the interface circuit of the aforementioned first aspect of the present invention.

According to an embodiment of a sixth aspect of the present invention, there is provided analogue-to-digital converter circuitry comprising the input circuit of the aforementioned fifth aspect of the present invention.

According to an embodiment of a seventh aspect of the present invention, there is provided integrated circuitry such as an IC chip (e.g. flip chip) comprising the interface circuit of the aforementioned first aspect of the present invention, or the signal transmission system of the aforementioned second aspect of the present invention, or the output circuit of the aforementioned third aspect of the present invention, or the digital-to-analogue converter circuitry of the aforementioned fourth aspect of the present invention, or the input circuit of the aforementioned fifth aspect of the present invention, or the analogue-to-digital converter circuitry of the aforementioned sixth aspect of the present invention.

