BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to memory control, and more particularly, to a method for performing data access management of an all flash array (AFA) server, and associated apparatus such as the AFA server, a control circuit thereof, etc.

2. Description of the Prior Art

A data storage server may be arranged to store user data of one or more users, and various control methods regarding the data storage server have been proposed in the related art in order to bring good user experience to the users. As non-volatile (NV) memories such as Flash memories have been widely applied to various data storage device such as solid state drives (SSDs), etc., it is proposed in the related art to implement the data storage server to be a non-volatile (NV) memory type data storage server using NV memories as storage media thereof, such as an AFA server having multiple SSDs installed therein. However, some problems may occur. For example, the management of accessing the Flash memory in any SSD of the multiple SSDs is complicated. To ensure that the access control of the Flash memory in this SSD conforms to associated specifications, the controller of the Flash memory in this SSD is usually equipped with some management mechanisms to properly manage the internal operations thereof. Although SSD manufactures may have tried to make SSDs seem to be a good solution for replacing hard disk drives (HDDs), some characteristics of the SSDs are quite different from that of the HDDs. As a result, the control methods mentioned above may become improper or invalid, causing the overall performance of the AFA server to be degraded. Thus, a novel method and associated architecture are needed for solving the problems without introducing any side effect or in a way that is less likely to introduce a side effect.

SUMMARY OF THE INVENTION

It is therefore an objective of the present invention to provide a control method of a server, to solve the above-mentioned problems.

According to one embodiment of the present invention, a server comprising SSD, a first node and a second node is disclosed. The first node comprises a first memory, a first processor and a first communication circuit, wherein the first memory comprises a first register and a second register, the first processor is configured to control the first register and the second register to have a first value and a second value, respectively. The second node comprises a second memory, a second processor and a second communication circuit, wherein the second memory comprises a third register and a fourth register, the second processor is configured to control the third register and the fourth register to have a third value and a fourth value, respectively, and the second communication circuit is coupled to the second processor, the second memory and the first communication circuit. The first register and the fourth register are synchronized with each other, the second register and the third register are synchronized with each other, the first value controlled by the first processor is different from the fourth value controlled by the second processor, and the second value controlled by the first processor is different from the third value controlled by the second processor; and the second processor periodically checks if the third register has the third value and the fourth register has the fourth value to determine if the first node fails to work.

According to another embodiment of the present invention, a control method of a server comprises the steps of: setting a first node within the server as a master device; periodically controlling a first register and a second register of the first node to have a first value and a second value, respectively; setting a second node within the server as a slave device; periodically controlling a third register and a fourth register of the second node to have a third value and a fourth value, respectively; controlling the first register and the fourth register to synchronize with each other, wherein the first value controlled by the first node is different from the fourth value controlled by the second node; controlling the second register and the third register to synchronize with each other, wherein the second value controlled by the first node is different from the third value controlled by the second node; and periodically checking if the third register has the third value and the fourth register has the fourth value to determine if the first node fails to work.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

