This application claims the benefit of French Patent Application No. 2002311, filed on Mar. 9, 2020, which application is hereby incorporated herein by reference in its entirety.

TECHNICAL FIELD

Implementations of the invention relate to a method and device for detecting the possible presence of at least one digital pattern within a signal.

BACKGROUND

One particularly interesting application of the invention relates to the analysis of a beacon signal received by a connected object of a network of connected objects deployed by the telecommunications operator Sigfox, so as to determine the Sigfox radio configuration (Sigfox RC) applicable to this connected object. This radio configuration corresponds in practice to a geographic region.

The Sigfox network of connected objects, which is well known to a person skilled in the art, is a worldwide narrowband network with a low data rate and a long range allowing objects, for example simple sensors, to communicate with a transmitter or base station. The frequency band is in the sub-gigahertz range.

Before an object can enter into dialogue with a base station, it must know in which region it is operating. To do this, before any dialogue with a base station, the object must receive and analyze a beacon signal emitted by the base station, because it is this beacon signal which will indicate to the object which region it is in and thus in which region it will be required to operate.

This beacon signal sent by the Sigfox network is called the “Monarch” signal. The “Monarch” beacon signal is emitted at the RF frequency defined by the region in which the emitter is situated. This beacon signal is a carrier modulated by an on-off keying modulation, by a succession of two repetitive digital patterns. These two patterns are chosen from a group of several different patterns, typically three.

The carrier frequency, also called the central frequency, is one of a list of possible “Monarch” central frequencies. The central frequency as well as the two patterns define the radio configuration or region in which the base station is situated.

An object scans all the possible “Monarch” central frequencies to search for the first pattern. Once it finds the first pattern at the correct central frequency, it will search for the second pattern at the same central frequency. Once it has found the second pattern, the object then knows the central frequency (carrier frequency) and the two patterns, and consequently it knows the region in which it is located.

As indicated above, the “Monarch” beacon signal is modulated by an OOK modulation. Consequently, a connected object which does not include an OOK demodulator cannot currently demodulate a signal and thus detect the digital patterns contained in the signal.

However, implementing an OOK demodulator has drawbacks, for example in terms of complexity and/or space requirement, which can prove difficult to reconcile in certain applications, for example with simple architectures of simple sensors.

SUMMARY

In accordance with an embodiment, a method detects a possible presence of at least one digital pattern within a signal. The at least one pattern belongs to a group of J reference patterns, J being greater than or equal to 2, comprising respectively Nj samples sequenced at a frequency F, Nj being a different integer for each reference pattern, and the J integers Nj being co-prime integers. The signal originates from a carrier modulated by the Nj samples of the at least one digital pattern by an on-off keying modulation at frequency F for a modulation period during which the pattern repeats at a frequency equal to F/Nj. Each reference pattern has a single sample authorizing an emission of the carrier and Nj−1 logic samples prevent the emission of the carrier. The method includes receiving the signal and processing the received signal. Processing includes (a) at frequency F and during an acquisition time, successive circular addressing of memory locations of J memory circuits having respectively Nj memory locations, and successive accumulative storing of values indicative of a signal intensity, in parallel in the J addressed memory locations of the J memory circuits, and (b) detecting the possible presence of the at least one pattern comprising analyzing cumulative values contained in the memory locations of the J memory circuits.

In accordance with another embodiment, a device for detecting a possible presence of at least one digital pattern within a signal. The at least one pattern belongs to a group of J reference patterns, J being greater than or equal to 2, comprising respectively Nj samples sequenced at a frequency F, Nj being a different integer for each reference pattern, and the J integers Nj being co-prime integers. The signal originates from a carrier modulated by the Nj samples of the at least one digital pattern by an on-off keying modulation at frequency F for a modulation period during which the pattern repeats at a frequency equal to F/Nj. Each reference pattern has a single sample authorizing an emission of the carrier and Nj−1 logic samples prevent the emission of the carrier. The device includes an input interface configured to receive the signal; J memory circuits having respectively Nj memory locations; and processing circuitry comprising: an accumulator configured to successively address the memory locations of the J memory circuits in a circular manner at frequency F and during an acquisition time, and successively accumulate and store values indicative of a signal intensity in parallel in the J addressed memory locations of the J memory circuits, and a detector configured to detect the possible presence of the at least one pattern, wherein the detector comprises an analyzer configured to analyze the accumulated values contained in the memory locations of the J memory circuits.

In accordance, with a further embodiment, a connected object includes a device configured to detect a presence of at least one digital pattern within a signal. The device includes: an input interface configured to receive the signal; J memory circuits having respectively Nj memory locations; and processing circuitry comprising: an accumulator configured to successively address the memory locations of the J memory circuits in a circular manner at frequency F and during an acquisition time, and successively accumulate and store values indicative of a signal intensity in parallel in the J addressed memory locations of the J memory circuits, and a detector configured to detect the possible presence of the at least one pattern, wherein the detector comprises an analyzer configured to analyze the accumulated values contained in the memory locations of the J memory circuits, wherein the at least one pattern belongs to a group of J reference patterns, J being greater than or equal to 2, comprising respectively Nj samples sequenced at a frequency F, Nj being a different integer for each reference pattern, and the J integers Nj being co-prime integers.

