CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Japan application serial no. 2020-107885, filed on Jun. 23, 2020. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

1. Technical Field

The disclosure relates to a memory technology, in particular, to a memory controller.

2. Description of Related Art

A pseudo static random access memory (hereinafter referred to as pSRAM) uses a dynamic random access memory (DRAM) as a memory cell array to store data. Furthermore, an access interface of the DRAM is redesigned to be compatible with an access interface of a static random access memory (SRAM), and a characteristic of an access timing sequence of the DRAM is also similar to that of the SRAM.

In the conventional memory technology, the memory controller is usually used to determine whether a self-refresh collision occurs in the pSRAM, and the memory controller is used to control the state of the latency control signal LTCX2_t generated by the mode register and the latency type control signal LTNCY2_t generated by the latency controller to set the latency type of the pSRAM access latency.

FIG. 1AandFIG. 1Bare diagrams illustrating signal timing sequences of conventional pSRAMs. Please refer toFIG. 1AandFIG. 1B, which are signal timing sequence diagrams respectively corresponding to the pSRAM, when the pSRAM performs a mode register writer (MRW) operation and is in a write mode and the memory controller determines that a self-refresh collision has not occurred and adjusts the access latency of the pSRAM to different latency types.

In the scenario ofFIG. 1A, when the memory controller is to adjust the access latency of the pSRAM from 2 times the latency time to 1 times the latency time (that is, to switch the latency type from a fixed latency type to a variable latency type), the inverted chip select signal (CS#) of the pSRAM is set to a low voltage level, and the latency control signal LTCX2_t and the latency type control signal LTNCY2_t at this time will be set to a high voltage level first.

However, in the conventional technology, because of the short reaction time of the time interval (i.e. tCSH and tCSHI) for the inverted chip select signal CS# to switch from the low voltage level to the high voltage level, the latency control signal LTCX2_t and the latency type control signal LTNCY2_t cannot be immediately switched to the low voltage level in the time interval.

In this case, a malfunction may occur in the read/write data strobe signal RWDS output by the read/write data strobe pin (hereinafter referred to as the RWDS pin) when the memory cell array performs a write operation.

In contrast, in the scenario ofFIG. 1B, when the memory controller is to adjust the access latency of the pSRAM from 1 times the latency time to 2 times the latency time (that is, to switch the latency type from a variable latency type to a fixed latency type), the inverted chip select signal (CS#) of the pSRAM is set to a low voltage level, and the latency control signal LTCX2_t and the latency type control signal LTNCY2_t at this time will be set to the low voltage level first.

However, because of the short reaction time of the time interval (i.e. tCSH and tCSHI) for the inverted chip select signal CS# to switch from the low voltage level to the high voltage level, the latency control signal LTCX2_t and the latency type control signal LTNCY2_t cannot be immediately switched to the high voltage level in the time interval.

In this case, a malfunction may also occur in the read/write data strobe signal RWDS output by the RWDS pin when the memory cell array performs a write operation.

In other words, in the case ofFIG. 1AandFIG. 1Bdescribed above, the read/write data strobe signal RWDS output by the RWDS pin is affected by the time interval (i.e. tCSH and tCSHI) being too short, a malfunction may occur in the read/write data strobe signal RWDS when the memory cell array performs a write operation, which further causes the pSRAM to fail to write valid data under correct timing sequence control and causes the overall memory system to fail to operate normally.

SUMMARY

The disclosure provides a memory controller that effectively reduces the malfunction of the memory controller when the memory controller is setting the latency type of the access latency of a pSRAM, thereby improving the operation quality of the memory system.

The memory controller is suitable for a pSRAM. The memory controller includes a mode register, a mode register write controller and a latency controller. The mode register is configured to generate a latency control signal according to a write instruction signal. The mode register write controller is configured to generate the write instruction signal during a mode register write operation and generate a write mask signal according to a chip selection signal. The latency controller is coupled to the mode register and the mode register write controller and generates a latency type control signal according to the latency control signal and the write mask signal.

In summary, the memory controller of the embodiments allows the latency controller to control the latency type control signal to be maintained in the enabled state according to the write mask signal with a high voltage level when the memory cell array performs a write operation and the inverted chip select signal is disabled. In this way, a malfunction does not occur in the read/write data strobe signal output by the RWDS pin when the memory cell array performs a write operation, thereby effectively improving the operation quality of the memory system.

