CROSS REFERENCE TO RELATED APPLICATIONS

This application is a U.S. National Phase Application under 35 U.S.C. § 371 of International Application PCT/IB2018/053629, filed on May 23, 2018, which is incorporated by reference, and which claims the benefit of a foreign priority application filed in Japan on Jun. 5, 2017, as Application No. 2017-111144.

TECHNICAL FIELD

The present invention relates to, for example, a memory device and a semiconductor device. Alternatively, the present invention relates to, for example, manufacturing methods of the memory device and the semiconductor device. Alternatively, the present invention relates to a memory transistor included in a memory device and a manufacturing method of the memory transistor. Alternatively, the present invention relates to, for example, a processor and an electronic device. Alternatively, the present invention relates to manufacturing methods of the processor and the electronic device. Alternatively, the present invention relates to driving methods of the memory device, the processor, and the electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter.

Note that in this specification and the like, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics in general. A display device, a light-emitting device, a lighting device, an electro-optical device, a memory device, a semiconductor circuit, and an electronic device include a semiconductor device in some cases.

BACKGROUND ART

In recent years, with the increase in the amount of data handled, a semiconductor device having a larger storage capacity has been required. To increase storage capacity per unit area, stacking and forming memory cells is effective (see Patent Document 1 and Patent Document 2). Stacking memory cells can increase storage capacity per unit area depending on the number of stacked memory cells.

PRIOR ART DOCUMENTS

Patent Documents

[Patent Document 1] United States Patent Application No. 2011/0065270A1[Patent Document 2] U.S. Pat. No. 9,634,097B2

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

In Patent Document 1, a semiconductor pattern provided in a columnar form is in direct contact with an insulator including a charge accumulation layer. In Patent Document 2, a semiconductor pattern provided in a columnar form is in direct contact with an insulator functioning as a tunnel dielectric. When the semiconductor is indirect contact with the insulator, trap centers might be formed at the interface between them. The trap centers formed at the interface between the semiconductor and the insulator trap electrons and change the threshold voltage of the transistor in the positive direction and thus might adversely affect the current driving power in the on state of the transistor, that is, the on-state current, the field-effect mobility, and the reliability.

In view of the above problems, an object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics in which the formation of trap centers is suppressed.

An object is to provide a semiconductor device having a large storage capacity per unit area. Alternatively, an object is to provide a semiconductor device having a novel structure in which memory cells (also referred to as memory transistors) are stacked. Alternatively, an object is to provide a semiconductor device having high productivity.

Alternatively, an object is to provide a module including the semiconductor device. Alternatively, an object is to provide an electronic device including the semiconductor device or the module. Alternatively, an object is to provide a novel semiconductor device. Alternatively, an object is to provide a novel module. Alternatively, an object is to provide a novel electronic device.

Note that the descriptions of these objects do not preclude the existence of other objects. One embodiment of the present invention does not need to achieve all the objects. Other objects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

Means for Solving the Problem

One embodiment of the present invention is a semiconductor device including a memory transistor. The memory transistor includes a conductor including an opening, a first insulator provided in contact with an inner side of the opening, a second insulator provided in contact with an inner side of the first insulator, a third insulator provided in contact with an inner side of the second insulator, a first oxide provided in contact with an inner side of the third insulator, and a second oxide provided in contact with an inner side of the first oxide. An energy gap of the second oxide is narrower than an energy gap of the first oxide.

Another embodiment of the present invention is a semiconductor device including a memory transistor. The memory transistor includes a conductor including an opening, a first insulator provided in contact with an inner side of the opening, a second insulator provided in contact with an inner side of the first insulator, a third insulator provided in contact with an inner side of the second insulator, a first oxide provided in contact with an inner side of the third insulator, a second oxide provided in contact with an inner side of the first oxide, and a third oxide provided in contact with an inner side of the second oxide. An energy gap of the second oxide is narrower than an energy gap of the first oxide, and an energy gap of the second oxide is narrower than an energy gap of the third oxide.

In the above, the first oxide and the second oxide preferably include In, an element M (M is Al, Ga, Y, or Sn), and Zn.

In the above, the atomic ratio of the element M to In in the first oxide is preferably greater than the atomic ratio of the element M to In in the second oxide.

In the above, preferably, the semiconductor device further includes a base, the semiconductor device includes a plurality of memory transistors over the base, and the plurality of memory transistors are stacked in a direction perpendicular to one surface included in the base.

In the above, the first insulator is preferably an oxide containing any one of silicon, aluminum, and hafnium.

In the above, the third insulator is preferably an oxide containing any one of silicon, aluminum, and hafnium.

In the above, the memory transistor may further include a fourth insulator and the fourth insulator is preferably provided in contact with an inner side of the third oxide.

Effect of the Invention

According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics in which the formation of trap centers is suppressed can be provided.

A semiconductor device having a large storage capacity per unit area can be provided. Alternatively, a semiconductor device having a novel structure in which memory cells (also referred to as memory transistors) are stacked can be provided. Alternatively, a semiconductor device having high productivity can be provided.

Alternatively, a module including the semiconductor device can be provided. Alternatively, an electronic device including the semiconductor device or the module can be provided. Alternatively, a novel semiconductor device can be provided. Alternatively, a novel module can be provided. Alternatively, a novel electronic appliance can be provided.

Note that the descriptions of the effects do not preclude the existence of other effects. One embodiment of the present invention does not necessarily achieve all the effects. Other effects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

