CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit under 35 U.S.C. § 119(a) of Korean Patent Application No. 10-2012-0141266, filed on Dec. 6, 2012, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.

BACKGROUND

1. Field

The following description relates to a multichip package and a fabricating method thereof, and to, for example, a multichip package provided in a form of a single package in which a plurality of semiconductor chips are arranged in a small outline package (SOP) as a surface mount device or in a quad flat package (QFP).

2. Description of Related Art

Semiconductor chip packaging technologies are actively being researched, with efforts to reduce the overall size of the devices, and to increase the packaging densities of the devices. Packaging technologies relate to appropriate arrangements of semiconductor elements such as ICs and switching elements in a smaller packages mounted onto a printed circuit board of a limited size, and with the arrangements that allow a greater number of packages to be mounted on the printed circuit board.

Active researches are taking place to develop a multichip package to mount a plurality of semiconductor devices on one package. The ‘multichip package’ refers to a structure with two or more semiconductor devices of different functions arranged on a lead frame pad as a single package.

An example of a package with a plurality of chips mounted thereon is a package constructed with a lead frame pad and two to four chips mounted thereon. The chips are connected to a lead frame and a bonding wire surrounding the periphery of the lead frame pad.

However, when a package is fabricated by simply arranging a plurality of semiconductor chips on a lead frame pad, thermal and/or electrical interference may occur among the neighboring chips within the package. Because the lead frame pad is made from a metallic material, without a separate structure to insulate or isolate the chips from each other, thermal and/or electrical interference is generated. Such thermal and/or electrical interferences may cause chips to malfunction, and may result in a defect in a product that is produced with such a package.

A a structure to insulate or isolate the chips from each other may be provided to minimize the potential thermal and/or electric interferences. However, this complicates the manufacturing process as well as increase the size of the package.

Another suggestion is to fabricate each chip in the form of a package and mount several packages on a PCB. However, these individual packages of chips also have their shortcomings.

Because PCBs are used for the respective individual packages, the PCB size increases. Further, if individual packages are mounted on the PCBs, the need for lead frames increases soldering works that must be performed on the lead frames, compared to the packages with two to four chips mounted thereon. Additional works are also necessary to connect the PCBs with individual packages mounted thereon to each other.

Thus, the mounting of individual packages go against the purpose of packaging technologies that aim to improve performance by integrating as many devices as possible onto a PCB of a limited size.

As explained above, various multichip packaging technologies have been suggested, including packages having a plurality of chips designed and arranged on one lead frame pad, or mounting individual packages. However, the proposed package technologies exhibit their associated shortcomings, and the demand to design a multichip package that is compact and light-weight has not been satisfied. The associated shortcomings are themselves the reasons that hinder the designing of optimal multichip packages, and researches are taking place to resolve these issues. However, much improvement is necessary to design the optimal multichip package technology for certain package applications.

SUMMARY

In one general aspect, there is provided a multichip package, including: a plurality of semiconductor chips each mounted on corresponding lead frame pads; lead frames connected to the semiconductor chips by a bonding wire; and fixed frames integrally formed with at least one of the lead frame pads and configured to support the lead frame pads on a package-forming substrate.

The multichip package may be implementable on a small outline package (SOP) or a quad flat package (QFP).

The fixed frames may include a stepped portion formed on a connecting portion to the lead frame pads.

The semiconductor chips may include one control integrated circuit (IC) chip and a plurality of MOSFET chips.

In another general aspect, there is provided a multichip package for use in a small outline package (SOP), the multichip package including: a first lead frame pad; a second lead frame pad and a third lead frame pad arranged on two opposite sides the first lead frame pad; a first to third semiconductor chips attached onto the first to third lead frame pads; a lead frame connected to the first to third semiconductor chips by a bonding wire; and a fixed frames integrally formed with the first to third lead frame pads to support the first to third lead frame pads on a package-forming substrate.

The first semiconductor chip may be a control IC chip, and the second and third semiconductor chips may be MOSFET chips.

The fixed frames and the lead frame connected to the drains of the MOSEFT chips may include a stepped portion that is partially bent.

In another general aspect, there is provided a multichip package for use with a quad flat package (QFP), the multichip package including: a first lead frame pad; a second to fourth lead frame pads aligned on one side of the first lead frame pad; a first to fourth semiconductor chips bonded onto the first to fourth lead frame pads; a plurality of lead frames connected to the first to fourth semiconductor chips by a bonding wire; and a fixed frames integrally formed with the first to fourth lead frame pads to support the first to fourth lead frame pads so that the first to fourth lead frame pads are placed on a package-forming substrate.

The first semiconductor chip may be a control integrated circuit (IC) chip, and the second to fourth semiconductor chips may be MOSFET chips.

The fixed frames and the lead frame connected to drains of the MOSFET chips may include a stepped portion that is partially bent.

The lead frame connected to the control IC chip may be partially formed in a zigzag pattern.

The lead frames connected to the drains of the MOSFET chips each may have a greater width than each of the lead frames connected to sources of the MOSFET chips and each of the lead frame connected to the control IC chip.

An adhesive may be attached to an upper surface of each of the lead frames connected to the control IC chip, in an orthogonal relationship with respect to a lengthwise direction of the lead frames.

The adhesive may include a heat tape.

In yet another general aspect, there is provided a method of manufacturing a multichip package, involving: mounting a first chip on a first lead frame pad; mounting a second chip on a second lead frame pad; positioning the first and second lead frame pads on a package-forming substrate by integrating portions of the lead frame pads with fixed frames; and forming a mold over the first and second chips and the first and second lead frame pads.

The general aspect of the method may further involve: wiring the first and second chips to lead frames such that the first and second chips are positioned in a center portion of the package-forming substrate, the lead frames extending radially outward from the center portion, and a number of the chips being the same as a number of the lead frame pads.

The mountings of the first and second chips on the first and second lead frame pads may involve bonding the first and second chips to the corresponding lead frame pads with Ag epoxy.

The first chip may be a control IC chip, and the second chip may be a MOSFET chip.

The lead frames connected to a drain of the MOSFET chip each may have a greater width than the lead frames connected to a source of the MOSFET chip, and the fixed frames may have a stepped portion so that the lead frame pads are positioned lower than the fixed frames.

Other features and aspects may be apparent from the following detailed description, the drawings, and the claims.

