TECHNICAL FIELD

The present disclosure generally relates to a verification system for integrated circuit (IC) design, and more particularly, to a system and method for providing convergence centric coverage for clock domain crossing (CDC) jitter in simulation.

BACKGROUND

Static timing verification systems are designed to verify data coherency by detecting setup and hold violations caused by metastability.FIG. 1shows a pair of flip-flop chains20,30supplying data to logic cloud50. Assume bits D0 and B0 are correlated, e.g., bits of the same multi-bit data. Assume that both bits D0 and B0 transition from 0 to 1 during a given clock cycle. Assume further that a 0 to 1 transition on signal D0 causes a transition of 0 to 1 of signal D1. However, due to cycle uncertainty caused by timing violation, the 0 to 1 transition on signal B0 is assumed not to propagate to signal B1. Accordingly, the 00 to 11 transition on bits B0D0 will appears as 10 on signals D1B1 and D2B2 as shown.

SUMMARY

A method of verifying functionality of a circuit design, in accordance with one embodiment of the present disclosure, includes, in part, defining one or more design constraints associated with the circuit design, determining at least one group of converging signals associated with the circuit design using the one or more design constraints, applying a multitude of jitters to clock domain crossing (CDC) paths of the at least one group of converging signals, and storing the jitters in a jitter database.

In one embodiment, the method further includes, in part, compiling the circuit design, a test bench associated with the design, and the jitter database, applying the test bench and the jitters to the compiled circuit design using a simulation tool, determining the number of counts that two or more signals in the at least one group of signals toggle jointly, determining the number of jitters associated with each of the counts of the jointly toggling signals, and determining the test bench coverage from the number of jitters and their associated counts of the jointly toggling signals.

A system, in accordance with one embodiment of the present disclosure, includes, in part, a memory storing instructions, and a processor coupled with the memory to execute the instructions. The instructions, when executed, cause the processor to define one or more design constraints associated with the circuit design, determine at least one group of converging signals associated with the circuit design, apply a multitude of jitters to clock domain crossing (CDC) paths of the at least one group of converging signals, and store the multitude jitters in a jitter database.

In one embodiment, the instructions further cause the processor to compile the circuit design, a test bench associated with the design, and the jitter database. The instructions further cause the processor to apply the test bench and the multitude of jitters to the compiled circuit design using a simulation tool, determine the number of counts that two or more signals in the at least one group of signals toggle jointly, determine the number of jitters associated with each of the counts of the jointly toggling signals, and determine the test bench coverage from the number of jitters and their associated counts of the jointly toggling signals.

A non-transitory computer readable medium stores instructions, which when executed by a processor, cause the processor to define one or more design constraints associated with the circuit design, determine at least one group of converging signals associated with the circuit design, apply a multitude of jitters to clock domain crossing (CDC) paths of the at least one group of converging signals, and store the multitude of jitters in a jitter database.

In one embodiment, the instructions further cause the processor to compile the circuit design, a test bench associated with the design, and the jitter database. The instructions further cause the processor to apply the test bench and the multitude of jitters to the compiled circuit design using a simulation tool, determine the number of counts that two or more signals in the at least one group of signals toggle jointly, determine the number of jitters associated with each of the counts of the jointly toggling signals, and determine the test bench coverage from the number of jitters and their associated counts of the jointly toggling signals.

