CROSS REFERENCE TO RELATED APPLICATIONS

This application is the National Stage of PCT/CN2020/109937 filed on Aug. 19, 2020, which claims priority under 35 U.S.C. § 119 of Chinese Application No. 201910782667.4 filed on Aug. 23, 2019, the disclosure of which is incorporated by reference.

TECHNICAL FIELD

Embodiments of the present disclosure relate to an array substrate, a light control panel and a display device.

BACKGROUND

A liquid crystal display device includes a backlight module and a liquid crystal panel, the backlight module is disposed on a non-display side of the liquid crystal panel to provide a light source for a display operation of the display panel. The liquid crystal panel includes a polarizer, an array substrate, an opposite substrate and a liquid crystal molecular layer filled between the two substrates. The liquid crystal display device rotates the liquid crystal molecules in the liquid crystal molecular layer by forming an electric field between the array substrate and the opposite substrate, and the liquid crystal molecules upon being rotated can be aligned with the polarizer to form a liquid crystal light valve. Since the liquid crystal molecular layer itself does not emit light, it is necessary to realize a display function with the aid of the backlight module. With the continuous development of display technology, users put forward increasingly higher requirements on a contrast ratio and a brightness uniformity of the display device.

SUMMARY

At least one embodiment of the present disclosure provides an array substrate. The array substrate includes a plurality of gate lines respectively extending along a first direction, a plurality of data lines respectively extending along a second direction intersected with the first direction, and a plurality of light control pixel units. Each of the plurality of gate lines includes a plurality of grid parts arranged side by side along the first direction and connected in sequence, and each of the plurality of grid parts includes a grid line and an opening area surrounded by the grid line.

For example, in at least one example of the array substrate, the grid line of each of the plurality of grid parts includes a first polygonal-line shaped trace and a second polygonal-line shaped trace; a starting point of the first polygonal-line shaped trace is connected with a starting point of the second polygonal-line shaped trace; an ending point of the first polygonal-line shaped trace is connected with an ending point of the second polygonal-line shaped trace; and a vertex of the first polygonal-line shaped trace and a vertex of the second polygonal-line shaped trace are spaced apart in the second direction.

For example, in at least one example of the array substrate, the first polygonal-line shaped trace includes a first line segment and a second line segment which are sequentially connected, and a connection point between the first line segment and the second line segment is the vertex of the first polygonal-line shaped trace; the second polygonal-line shaped trace includes a third line segment and a fourth line segment which are sequentially connected, and a connection point between the third line segment and the fourth line segment is the vertex of the second polygonal-line shaped trace; and an absolute value of an acute angle between the first line segment and the first direction, an absolute value of an acute angle between the second line segment and the first direction, an absolute value of an acute angle between the third line segment and the first direction, and an absolute value of an acute angle between the fourth line segment and the first direction are between 38 degrees and 55 degrees.

For example, in at least one example of the array substrate, the absolute value of the acute angle between the first line segment and the first direction, the absolute value of the acute angle between the second line segment and the first direction, the absolute value of the acute angle between the third line segment and the first direction, and the absolute value of the acute angle between the fourth line segment and the first direction are between 42 degrees and 48 degrees.

For example, in at least one example of the array substrate, the first polygonal-line shaped trace and the second polygonal-line shaped trace are symmetrical with respect to a connecting line between the starting point of the first polygonal-line shaped trace and the ending point of the first polygonal-line shaped trace.

For example, in at least one example of the array substrate, the first line segment and the second line segment are symmetrical with respect to a connecting line between the vertex of the first polygonal-line shaped trace and the vertex of the second polygonal-line shaped trace; and the third line segment and the fourth line segment are symmetrical with respect to the connecting line between the vertex of the first polygonal-line shaped trace and the vertex of the second polygonal-line shaped trace.

For example, in at least one example of the array substrate, each of the plurality of data lines has two overlapping positions with the grid line of one corresponding grid part in a direction perpendicular to the array substrate, or each of the plurality of data lines is overlapped with a connecting position between two adjacent grid parts in the direction perpendicular to the array substrate.

For example, in at least one example of the array substrate, the array substrate further includes common electrode lines extending along the second direction. Each of the common electrode lines is overlapped with the connecting position between the two adjacent grid parts in the direction perpendicular to the array substrate, or each of the common electrode lines has two overlapping positions with the grid line of one corresponding grid part in the direction perpendicular to the array substrate.

For example, in at least one example of the array substrate, the opening area surrounded by each of the plurality of grid parts is partly overlapped with one or two of the plurality of light control pixel units in a direction perpendicular to the array substrate.

For example, in at least one example of the array substrate, a boundary trace of each of the plurality of light control pixel units is formed by corresponding data lines and the first polygonal-line shaped traces of the grid parts of corresponding gate lines; and the second polygonal-line shaped trace of the grid part of each of the plurality of gate lines passes through an interior of a corresponding light control pixel unit.

For example, in at least one example of the array substrate, the array substrate further includes common electrode lines extending along the second direction. Each of the common electrode lines is overlapped with a connecting position between two adjacent grid parts in a direction perpendicular to the array substrate; a boundary trace of each of the plurality of light control pixel units is formed by corresponding common electrode lines and the first polygonal-line shaped traces of the grid parts of corresponding gate lines; and the second polygonal-line shaped trace of the grid part of each of the plurality of gate lines passes through an interior of a corresponding light control pixel unit.

For example, in at least one example of the array substrate, each of the plurality of light control pixel units further includes a switching element and a pixel electrode; the switching element includes a gate electrode, a source electrode and a drain electrode, the gate electrode of the switching element is electrically connected with a corresponding second polygonal-line shaped trace, and one of the source electrode and the drain electrode of the switching element is electrically connected with the pixel electrode; and the switching element and the second polygonal-line shaped trace have the same amount as each other.

For example, in at least one example of the array substrate, a width of the first polygonal-line shaped trace and a width of the second polygonal-line shaped trace both are between 9 microns and 11 microns.

For example, in at least one example of the array substrate, the grid line of each of the plurality of grid parts includes a first polygonal-line shaped trace and a second polygonal-line shaped trace; a starting point of the first polygonal-line shaped trace is connected with a starting point of the second polygonal-line shaped trace; an ending point of the first polygonal-line shaped trace is connected with an ending point of the second polygonal-line shaped trace; a vertex of the first polygonal-line shaped trace and a vertex of the second polygonal-line shaped trace are spaced apart in the second direction; the first polygonal-line shaped trace includes a first line segment and a second line segment which are sequentially connected, and a connection point between the first line segment and the second line segment is the vertex of the first polygonal-line shaped trace; the second polygonal-line shaped trace includes a third line segment and a fourth line segment which are sequentially connected, and a connection point between the third line segment and the fourth line segment is the vertex of the second polygonal-line shaped trace; an absolute value of an acute angle between the first line segment and the first direction, an absolute value of an acute angle between the second line segment and the first direction, an absolute value of an acute angle between the third line segment and the first direction, and an absolute value of an acute angle between the fourth line segment and the first direction are between 42 degrees and 48 degrees; the first polygonal-line shaped trace and the second polygonal-line shaped trace are symmetrical with respect to a connecting line between the starting point of the first polygonal-line shaped trace and the ending point of the first polygonal-line shaped trace; the first line segment and the second line segment are symmetrical with respect to a connecting line between the vertex of the first polygonal-line shaped trace and the vertex of the second polygonal-line shaped trace; the third line segment and the fourth line segment are symmetrical with respect to the connecting line between the vertex of the first polygonal-line shaped trace and the vertex of the second polygonal-line shaped trace; each of the plurality of data lines has two overlapping positions with the grid line of one corresponding grid part in a direction perpendicular to the array substrate; the array substrate further includes common electrode lines extending along the second direction; each of the common electrode lines is overlapped with a connecting position between two adjacent grid parts in the direction perpendicular to the array substrate; the opening area surrounded by each of the plurality of grid parts is partly overlapped with two of the plurality of light control pixel units in the direction perpendicular to the array substrate; a boundary trace of the light control pixel unit is formed by corresponding data lines and the first polygonal-line shaped traces of the grid parts of corresponding gate lines; the second polygonal-line shaped trace of the grid part of each of the plurality of gate lines passes through an interior of a corresponding light control pixel unit; and each of the plurality of light control pixel units further includes a switching element and a pixel electrode; the switching element includes a gate electrode, a source electrode and a drain electrode; the gate electrode of the switching element is electrically connected with a corresponding second polygonal-line shaped trace; one of the source electrode and the drain electrode of the switching element is electrically connected with the pixel electrode; and the switching element and the second polygonal-line shaped trace have the same amount as each other.

At least one embodiment of the present disclosure also provides a light control panel including an array substrate, an opposite substrate and a liquid crystal layer. The array substrate and the opposite substrate are disposed opposite to each other; the liquid crystal layer is sandwiched between the array substrate and the opposite substrate; the array substrate includes a plurality of gate lines respectively extending along a first direction, a plurality of data lines respectively extending along a second direction intersected with the first direction, and a plurality of light control pixel units; each of the plurality of gate lines includes a plurality of grid parts arranged side by side along the first direction and connected in sequence; and each of the plurality of grid parts includes a grid line and an opening area surrounded by the grid line.

At least one embodiment of the present disclosure also provides a display device, including a display panel, a light control panel and a backlight unit. The display panel is located at a light exiting side of the light control panel; the backlight unit is located at a side of the light control panel away from the display panel. The light control panel includes an array substrate, an opposite substrate and a liquid crystal layer; the array substrate and the opposite substrate are disposed opposite to each other; the liquid crystal layer is sandwiched between the array substrate and the opposite substrate; the array substrate includes a plurality of gate lines respectively extending along a first direction, a plurality of data lines respectively extending along a second direction intersected with the first direction, and a plurality of light control pixel units; each of the plurality of gate lines includes a plurality of grid parts arranged side by side along the first direction and connected in sequence; and each of the plurality of grid parts includes a grid line and an opening area surrounded by the grid line.

For example, in at least one example of the display device, the display panel includes a plurality of display pixel units arranged in an array; a size of each of the plurality of grid parts in the first direction is equal to twice a size of each of the plurality of display pixel units in the first direction; and a size of each of the plurality of grid parts in the second direction is less than or equal to twice a size of each of the plurality of display pixel units in the second direction.

For example, in at least one example of the display device, a size of each of the plurality of light control pixel units in the first direction is equal to twice a size of each of the plurality of display pixel units in the first direction; and a size of each of the plurality of light control pixel units in the second direction is equal to 2.5 times to 3 times the size of each of the plurality of display pixel units in the first direction.

At least one embodiment of the present disclosure also provides a manufacturing method of an array substrate, including: forming a plurality of gate lines respectively extending along a first direction; and forming a plurality of data lines respectively extending along a second direction intersected with the first direction. The plurality of gate lines and the plurality of data lines are intersected to define a plurality of light control pixel units, each of the plurality of gate lines includes a plurality of grid parts arranged in parallel along the first direction and connected in sequence, and each of the plurality of grid parts includes a grid line and an opening area surrounded by the grid line.

