TECHNICAL FIELD

This disclosure relates to data caches and in particular, data caches implementing hybrid writebacks and writethroughs when the data cache is in a shared or an exclusive coherence state.

BACKGROUND

Data caches are hardware and/or software components that store data so that future requests for that data can be served faster. Typically, the data caches are either a writeback or a writethrough data cache type, where the data cache type control when the data stored in the data cache is written to a backing store, memory, or the like. A writeback write policy delays writes to the backing store until modified content in the data cache is about to be replaced by another cache block or based on other policies. A writethrough write policy writes to the backing store synchronously when writing to the data cache.

Data caches in a shared memory multiprocessor system typically operate subject to cache coherence protocols and coherence mechanisms, which ensure that changes in the values of shared data are propagated throughout the shared memory multiprocessor system in a timely fashion. Two common cache coherence protocols are, for example, the Modified, Exclusive, Shared, Invalid (MESI) protocol and the Modified, Shared, Invalid (MSI) protocol. In implementations, the exclusive coherence protocol state may be referred to as a unique coherence protocol state. Typically, in the modified coherence protocol state, a cache line is present only in the current cache and is dirty. That is, the data in the cache line is different from the data in the backing store. In this instance, the data cache is required to write the data back to backing store at some time in the future, before permitting any other read of the (no longer valid) backing store. Upon performance of the writeback, the cache line changes to the shared coherence protocol state. In the exclusive coherence protocol state, the cache line is present only in the current data cache and is clean. That is, the data in the cache line matches the data in the backing store. The cache line may be changed to the shared coherence protocol state at any time, in response to a read request. Alternatively, the cache line may be changed to a modified coherence protocol state when writing to the cache line. In the shared coherence protocol state, the cache line may be stored in other caches of the system and is clean. That is, the data in the cache line matches the data in the backing store. The cache line may be discarded (changed to the invalid coherence protocol state) at any time. In the invalid coherence protocol state, the cache line is invalid (unused).

In a writeback data cache, a store (or many stores) may be issued to a cache line(s) or cache block(s) in a “clean” (invalid, shared, or exclusive) coherence protocol state, which is classically defined to have read-only permissions. A write may only be performed freely if the cache line is established or upgraded to the modified coherence protocol state. Cache lines in the exclusive coherence protocol state also have to be upgraded to the modified coherence protocol state to be globally visible.

Coherence protocol upgrades can be done using coherent mechanisms such as snooping, where each data cache monitors address lines for accesses to memory locations that they have cached, or directory, where a backing controller remembers which cache(s) have which coherence permission(s) on which cache block(s). This coherence protocol upgrade process takes time in an interconnect network to probe snoop downgrade other caches, leading to delayed store instruction retirement and reduced performance.

