CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Japan application serial no. 2020-066573, filed on Apr. 2, 2020. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

Field of the Disclosure

The invention relates to a semiconductor storing apparatus such as a NAND flash memory, and more particularly relates to error detection/correction during a read operation.

Description of Related Art

Some NAND flash memories equipped with serial peripheral interface (SPI) that input/output data in synchronization with an external clock signal have the function of continuously reading pages. During continuous reading of the page, while the data read out from the selected page of the memory cell array is held in one of the latches of the page buffer/sense circuit, the read data held in the previous page of another latch circuit can be output, for example, as described in Patent Reference 1 (Japanese Laid-Open No. 5323170), Patent Reference 2 (Japanese Laid-Open No. 5667143), Patent Reference 3 (US Patent Application US2014/0104947A1).

SUMMARY

In NAND flash memory, as data is written or erased repeatedly, the charge retention characteristics are deteriorated due to deterioration of the tunnel insulating film, etc., or the threshold value changes due to the charge trapped by the tunnel insulating film, which causes bit errors. As a countermeasure against such bit errors, an error correcting code (ECC) circuit is provided.

FIG. 1shows the schematic structure of a conventional NAND flash memory equipped with an on-chip ECC function. The flash memory10includes a memory cell array20, a page buffer/sense circuit30, an error correcting code circuit (hereinafter referred to as an ECC circuit)40, and an input/output circuit50. The ECC circuit40includes a transmission circuit42, an ECC core44, an error register46and a write circuit48.

In the read operation, the data read out from a selected page of the memory cell array20is held in the page buffer/sense circuit30, and the data in units of bytes held in the page buffer/sense circuit30is transmitted to the ECC core44through the transmission circuit42. The ECC core44performs an ECC operation on the transmitted data, and holds the error information obtained by the operation in the error register46. The write circuit48writes the corrected data back to the page buffer/sense circuit30based on the error information held in the error register46. After the ECC processing of a page is completed, the data held in the page buffer/sense circuit30is read out to the data bus60according to the column address, and the read data is provided to the external input/output circuit50. The input/output circuit50outputs the read data from an input/output terminal that is not shown.

FIG. 2AandFIG. 2Bshow time charts of a duration in which continuous read operation of pages is performed. The page buffer/sense circuit30includes two latches L1and L2(one latch holds, for example, 2 KB of page data), the latches L1and L2each include a first cache memory (cache) C0and the second cache memory C1(a cache memory is, for example, 1 KB). The data held by the first cache memory C0and the second cache memory C1of the latch L1are independently transmitted respectively to the first cache memory C0and the second cache memory C1of the latch L2.

In the beginning, the array read operation is performed on the page0, and the data of page0is held in the first cache memory C0and the second cache memory C1(P0C0, P0C1) of the latch L1. Next, the data of the first cache memory C0and the second cache memory C1of the latch L1are transmitted to the first cache memory C0and the second cache memory C1of the latch L2, and the ECC core42performs ECC processing on the data in the first cache memory C0and the second cache memory C1. If an error is detected, the write circuit48writes the corrected data to the first cache memory C0and the second cache memory C1of the latch L2according to the error information held in the error register46.

In continuous read operation, the row address counter is automatically incremented, reads out the next page1, and transmits the read data to the first cache memory C0and the second cache memory C1of the latch L1. During this period, the data in the first cache memory C0of the latch L2is transmitted to the input/output circuit50, and the data held by the input/output circuit50is output in synchronization with the external clock signal ExCLK supplied externally. Thereafter, from the input/output circuit50, the data in the second cache memory C1of the latch L2is output in synchronization with the external clock signal ExCLK, and during this period, the data in the first cache memory C0of the latch L1is transmitted to the latch L2, and the ECC circuit40performs ECC processing.

The data in the second cache memory C1of the latch L1is transmitted to the latch L2, and while the data in the first cache memory C0of the latch L2is output from the input/output circuit50, ECC processing is performed on the data in the second cache memory C1of the second latch L2. Then, while the data in the second cache memory C1of the latch L2is output from the input/output circuit50, the next page2is read out from the array, and transmitted to the first cache memory C0and the second cache memory C1of the latch L1, and the data in the first cache memory C0is transmitted to the latch L2for ECC processing.

While outputting data from the latch L2, the pages of the memory cell array are read continuously. During this period, the ECC processing is performed on the second cache memory C1while the data in the first cache memory C0is output. The ECC processing is performed on the first cache memory C0while the data in the second cache memory C1is output.

The read operation of the memory cell array is performed in synchronization with the internal clock signal according to the determined timing. On the other hand, the output of the read data is performed in synchronization with the external clock signal ExCLK which is not synchronized with the internal clock signal. Therefore, in the continuous read operation of the page, there is a limitation shown in the following equation (1).
tPRE+tDIS+tECC<tDOUT  (1)
tPRE: Precharge time of the bit line,
tDIS: the discharge time of the memory cell
tECC: ECC processing time for ½ page
tDOUT: the data output time of a page.

tPRE and tDIS are fixed. If the frequency of the external clock signal ExCLK is increased for high-speed read operation, tDOUT becomes smaller. Accordingly, tECC must be reduced. For example, when reading 2 KB page data, tPRE+tDIS is about 16.2 μs. The frequency of the external clock signal ExCLK is 166 MHz. When the data of one page is output from the ×4 external terminal, tDOUT is about 24.6 μs. According to equation (1), ECC processing time has the limitation of equation (2).
tECC<8.4 μs  (2)

When the ECC circuit performs 1-bit error detection/correction, Hamming code can be adopted under the circumstances, and its processing time is relatively short, so there is a margin in the frequency of the external clock signal ExCLK. On the other hand, in the case of multi-bit error detection/correction, Bose-Chaudhuri-Hocquenghem (BCH) code is required. In the processing of BCH code, the processing time is longer than the processing time of Hamming codes. Under the circumstances, the ECC processing time (tECC) of equation (2) may be a bottleneck.

FIG. 3illustrates a conventional flow for decoding a BCH code. As an example, one page (2 KB) includes two cache memories C0and C1, and one cache memory includes two sectors. ECC is performed in units of sectors (for example, 512 bytes). A cache memory requires two times of ECC processing. Through the BCH code, four-bit error detection/correction for each cache memory can be realized. Furthermore, the ECC processing is performed in synchronization with the ECC clock signal, and the clock frequency is set to 50 MHz.

Step1: The syndrome of the data read from the first sector and the second sector is evaluated. This step includes the following processing, that is, accessing the page buffer/sense circuit30through the transmission circuit42and reading data therefrom, and140clock cycles are required for each sector.

Step2: After the evaluation of the syndrome of the first sector, the error location polynomial (ELP) of the first sector is calculated. After the evaluation of the syndrome of the second sector, the second error location polynomial (ELP) of the second sector is calculated. The calculations require 81 clock cycles respectively.

Step3: The root of the ELP of the first sector is calculated, and its error location is determined. The root of the ELP of the second sector is calculated, and its error location is determined. These calculations require 135 clock cycles respectively.

Step4: Based on the error location, the corrected data is written back to the page buffer/sense circuit. This processing requires 20 clock cycles.

As long as the same step is not repeated, the processing on the first sector and the second sector in steps1to4can be performed in parallel. The ECC processing on a cache memory requires 516 clock cycles. If the clock cycles are converted into time, tECC=10.32 μs.

In the case of using Hamming code, the steps2and3in the case of using the BCH code are not required, and a total of 288 clock cycles (ECC=5.8 μs) are required. Therefore, if Hamming code is adopted, the limitation of tECC<8.4 μs shown in the equation (2) can be satisfied. However, in the case that the BCH code is adopted, then tECC(=10.32)>8.4 μs, which cannot satisfy the limitation of tECC<8.4 μs. That is, the maximum frequency of the external clock signal ExCLK at tECC=10.32 μs is 154.4 MHz, and it is not possible to perform high-speed reading which adopts the 166 MHz external clock signal ExCLK. The rectangular region illustrated as the shaded region shown inFIG. 2Brepresents a state where tECC=10.32 μs does not satisfy the limitation.

When continuous read operation is performed in the conventional flash memory, there is a problem: If the ECC processing time is long, the frequency of the external clock signal ExCLK is limited, and high-speed reading cannot be performed.

A purpose of the invention is to solve the conventional problem and provide a semiconductor storing apparatus and a readout method capable of reducing the ECC processing time during a read operation.

The semiconductor storing apparatus of the invention includes a memory cell array; a page buffer/sense circuit holding data read out from a selected page of the memory cell array; an ECC circuit receiving data that is held in the page buffer/sense circuit and detecting the data, and holding error address information related to the error address that is detected; an output circuit selecting data from the page buffer/sense circuit based on a column address, and outputting the selected data to a data bus; and an error correction part correcting data on the data bus based on the error address information.

The readout method of the flash memory of the invention includes the following steps: during the read operation, receiving data held in the page buffer/sense circuit, detecting the data; holding the error address information related to the error address that is detected; selecting data from the page buffer/sense circuit based on the column address, and outputting the selected data to the data bus; correcting the data on the data bus based on the error address information; and outputting the corrected data to the outside.

According to the invention, the data on the data bus output from the page buffer/sense circuit is corrected based on the error address information. Therefore, compared with conventional technology, the time required for error detection/correction can be shortened. In this manner, the time for read operation can be reduced. Furthermore, when performing continuous reading of pages, the reading speed can be increased compared to conventional technology.

