BACKGROUND

This application claims the priority of Chinese Patent Application No. 201910983741.9, entitled “GOA DEVICE AND GATE DRIVING CIRCUIT”, filed on Oct. 16, 2019 in the CNIPA (National Intellectual Property Administration, PRC), the disclosure of which is incorporated herein by reference in its entirety.

FIELD

The present disclosure relates to the display panel manufacturing field, and more particularly to a GOA device and a gate driving circuit.

BACKGROUND

In the gate drive on array (GOA) technology, scan line driving circuits are integrated on an array substrate of a liquid crystal display, so that a product cost can be decreased due to a material cost and a manufacturing process.

For a display panel having a high resolution and a high frequency (e.g., 120 Hz), a charge time is short, and capacitive loads of scan lines are heavy. Accordingly, distortions of gate pulse signals are serious. A value of a falling time of an output signal of a gate signal line is large, so that a risk of wrong charging is high. In the prior art, a time interval from a transition time point of a scan line to a transition time point of a data line is lengthened, and thus the charging time is shortened. A technical problem that a charging ability is not sufficient occurs.

Consequently, there is a need to provide a gate driving circuit to solve the above-mentioned technical problem in the prior art.

SUMMARY OF DISCLOSURE

The present disclosure provides a GOA device and a gate driving circuit to solve the technical problem that a charging ability is not sufficient.

The present disclosure provides a GOA device including at least two GOA units which are cascaded. An Nth stage GOA unit of the GOA units is configured to output a gate driving signal to an Nth horizontal scan line. The Nth stage GOA unit includes a pull-up control unit, a bootstrap unit, a pull-up unit, a pull-down unit, and a pull-down holding unit.

The pull-up control unit receives a starting signal to pull up a control node (Qn) of the Nth stage GOA unit to a first high voltage level in a first phase.

The bootstrap unit pulls up, according to a clock signal, the control node (Qn) of the Nth stage GOA unit to a second high voltage level in a second phase.

The pull-up unit outputs, according to the first high voltage level and the second high voltage level of the control node (Qn) of the Nth stage GOA unit and the clock signal outputted by the bootstrap unit, the gate driving signal to a gate signal terminal (Gn) of the Nth stage GOA unit, and a pulse width of the gate driving signal is twice a pulse width of the clock signal.

The pull-down unit pulls down the control node (Qn) of the Nth stage GOA unit and the gate signal terminal (Gn) of the Nth stage GOA unit to a first direct current low voltage level in a third phase.

The pull-down holding unit maintains the control node (Qn) of the Nth stage GOA unit as the first direct current low voltage level and maintains the gate signal terminal (Gn) of the Nth stage GOA unit as a second direct current low voltage level in a fourth phase.

In the GOA device of the present disclosure, the pull-up control unit is electrically coupled to a stage transfer signal terminal (STn−4) and a gate signal terminal (Gn−4) of an (N−4)th stage GOA unit and the control node (Qn) of the Nth stage GOA unit.

In the first phase, the pull-up control unit receives the starting signal from the stage transfer signal terminal (STn−4) of the (N−4)th stage GOA unit to pull up the control node (Qn) of the Nth stage GOA unit to the first high voltage level.

In the GOA device of the present disclosure, the pull-up control unit comprises an eleventh thin film transistor (T11).

A gate of the eleventh thin film transistor (T11) is electrically coupled to the stage transfer signal terminal (STn−4) of the (N−4)th stage GOA unit, a source of the eleventh thin film transistor (T11) is electrically coupled to a gate signal terminal (Gn−4) of the (N−4)th stage GOA unit, and a drain of the eleventh thin film transistor (T11) is electrically coupled to the control node (Qn) of the Nth stage GOA unit.

In the GOA device of the present disclosure, the bootstrap unit is electrically coupled to the control node (Qn) of the Nth stage GOA unit, a clock signal terminal (CK), and a stage transfer signal terminal (STn) of the Nth stage GOA unit.

The clock signal terminal (CK) is configured to provide the clock signal.

The second phase starts when the control node (Qn) of the Nth stage GOA unit is pulled up to the first high voltage level.

In the GOA device of the present disclosure, the bootstrap unit comprises a bootstrap capacitor and a twenty-second thin film transistor (T22).

The bootstrap capacitor is electrically coupled to the control node (Qn) of the Nth stage GOA unit and the stage transfer signal terminal (STn) of the Nth stage GOA unit.

A gate of the twenty-second thin film transistor (T22) is electrically coupled to the control node (Qn) of the Nth stage GOA unit, a source of the twenty-second thin film transistor (T22) is electrically coupled to the clock signal terminal (CK), and a drain of the twenty-second thin film transistor (T22) is electrically coupled to the stage transfer signal terminal (STn) of the Nth stage GOA unit.

In the GOA device of the present disclosure, the pull-up unit is electrically coupled to the control node (Qn) of the Nth stage GOA unit, the stage transfer signal terminal (STn) of the Nth stage GOA unit, and the gate signal terminal (Gn) of the Nth stage GOA unit.

The stage transfer signal terminal (STn) of the Nth stage GOA unit is configured to provide a starting signal to control a thin film transistor in the pull-up unit to be turned on and off.

In the GOA device of the present disclosure, the pull-up unit comprises a twenty-first thin film transistor (T21).

A gate of the twenty-first thin film transistor (T21) is electrically coupled to the control node (Qn) of the Nth stage GOA unit, a source of the twenty-first thin film transistor (T21) is electrically coupled to the stage transfer signal terminal (STn) of the Nth stage GOA unit, and a drain of the twenty-first thin film transistor (T21) is electrically coupled to the gate signal terminal (Gn) of the Nth stage GOA unit.

In the GOA device of the present disclosure, the pull-down unit is electrically coupled to the control node (Qn) of the Nth stage GOA unit, the gate signal terminal (Gn) of the Nth stage GOA unit, a transfer signal terminal (STn+4) of an (N+4)th stage GOA unit, and a first direct current low voltage level terminal (VSSQ).

The first direct current low voltage level terminal (VSSQ) is configured to provide the first direct current low voltage level.

The third phase starts when the transfer signal terminal (STn+4) of the (N+4)th stage GOA unit is at a high voltage level.

In the GOA device of the present disclosure, the pull-down unit comprises a thirty-first thin film transistor (T31) and a forty-first thin film transistor (T41).

A source of the thirty-first thin film transistor (T31) is electrically coupled to the gate signal terminal (Gn) of the Nth stage GOA unit, and a source of the forty-first thin film transistor (T41) is electrically coupled to the control node (Qn) of the Nth stage GOA unit.

A drain of the thirty-first thin film transistor (T31) and a drain of the forty-first thin film transistor (T41) are electrically coupled to the first direct current low voltage level terminal (VSSQ), and a gate of the thirty-first thin film transistor (T31) and a gate of the forty-first thin film transistor (T41) are electrically coupled to the transfer signal terminal (STn+4) of the (N+4)th stage GOA unit.

The present disclosure further provides a gate driving circuit. The gate driving circuit includes a GOA device including at least two GOA units which are cascaded. An Nth stage GOA unit of the GOA units is configured to output a gate driving signal to an Nth horizontal scan line. The Nth stage GOA unit includes a pull-up control unit, a bootstrap unit, a pull-up unit, a pull-down unit, and a pull-down holding unit.

The pull-up control unit receives a starting signal to pull up a control node (Qn) of the Nth stage GOA unit to a first high voltage level in a first phase.

The bootstrap unit pulls up, according to a clock signal, the control node (Qn) of the Nth stage GOA unit to a second high voltage level in a second phase.

The pull-up unit outputs, according to the first high voltage level and the second high voltage level of the control node (Qn) of the Nth stage GOA unit and the clock signal outputted by the bootstrap unit, the gate driving signal to a gate signal terminal (Gn) of the Nth stage GOA unit, and a pulse width of the gate driving signal is twice a pulse width of the clock signal.

The pull-down unit pulls down the control node (Qn) of the Nth stage GOA unit and the gate signal terminal (Gn) of the Nth stage GOA unit to a first direct current low voltage level in a third phase.

The pull-down holding unit maintains the control node (Qn) of the Nth stage GOA unit as the first direct current low voltage level and maintains the gate signal terminal (Gn) of the Nth stage GOA unit as a second direct current low voltage level in a fourth phase.

In the gate driving circuit of the present disclosure, the pull-up control unit is electrically coupled to a stage transfer signal terminal (STn−4) and a gate signal terminal (Gn−4) of an (N−4)th stage GOA unit and the control node (Qn) of the Nth stage GOA unit.

In the first phase, the pull-up control unit receives the starting signal from the stage transfer signal terminal (STn−4) of the (N−4)th stage GOA unit to pull up the control node (Qn) of the Nth stage GOA unit to the first high voltage level.

In the gate driving circuit of the present disclosure, the pull-up control unit comprises an eleventh thin film transistor (T11).

A gate of the eleventh thin film transistor (T11) is electrically coupled to the stage transfer signal terminal (STn−4) of the (N−4)th stage GOA unit, a source of the eleventh thin film transistor (T11) is electrically coupled to a gate signal terminal (Gn−4) of the (N−4)th stage GOA unit, and a drain of the eleventh thin film transistor (T11) is electrically coupled to the control node (Qn) of the Nth stage GOA unit.

In the gate driving circuit of the present disclosure, the bootstrap unit is electrically coupled to the control node (Qn) of the Nth stage GOA unit, a clock signal terminal (CK), and a stage transfer signal terminal (STn) of the Nth stage GOA unit.

The clock signal terminal (CK) is configured to provide the clock signal.

The second phase starts when the control node (Qn) of the Nth stage GOA unit is pulled up to the first high voltage level.

In the gate driving circuit of the present disclosure, the bootstrap unit comprises a bootstrap capacitor and a twenty-second thin film transistor (T22).

The bootstrap capacitor is electrically coupled to the control node (Qn) of the Nth stage GOA unit and the stage transfer signal terminal (STn) of the Nth stage GOA unit.

A gate of the twenty-second thin film transistor (T22) is electrically coupled to the control node (Qn) of the Nth stage GOA unit, a source of the twenty-second thin film transistor (T22) is electrically coupled to the clock signal terminal (CK), and a drain of the twenty-second thin film transistor (T22) is electrically coupled to the stage transfer signal terminal (STn) of the Nth stage GOA unit.

In the gate driving circuit of the present disclosure, the pull-up unit is electrically coupled to the control node (Qn) of the Nth stage GOA unit, the stage transfer signal terminal (STn) of the Nth stage GOA unit, and the gate signal terminal (Gn) of the Nth stage GOA unit.

The stage transfer signal terminal (STn) of the Nth stage GOA unit is configured to provide a starting signal to control a thin film transistor in the pull-up unit to be turned on and off.

In the gate driving circuit of the present disclosure, the pull-up unit comprises a twenty-first thin film transistor (T21).

A gate of the twenty-first thin film transistor (T21) is electrically coupled to the control node (Qn) of the Nth stage GOA unit, a source of the twenty-first thin film transistor (T21) is electrically coupled to the stage transfer signal terminal (STn) of the Nth stage GOA unit, and a drain of the twenty-first thin film transistor (T21) is electrically coupled to the gate signal terminal (Gn) of the Nth stage GOA unit.

In the gate driving circuit of the present disclosure, the pull-down unit is electrically coupled to the control node (Qn) of the Nth stage GOA unit, the gate signal terminal (Gn) of the Nth stage GOA unit, a transfer signal terminal (STn+4) of an (N+4)th stage GOA unit, and a first direct current low voltage level terminal (VSSQ).

The first direct current low voltage level terminal (VSSQ) is configured to provide the first direct current low voltage level.

The third phase starts when the transfer signal terminal (STn+4) of the (N+4)th stage GOA unit is at a high voltage level.

In the gate driving circuit of the present disclosure, the pull-down unit comprises a thirty-first thin film transistor (T31) and a forty-first thin film transistor (T41).

A source of the thirty-first thin film transistor (T31) is electrically coupled to the gate signal terminal (Gn) of the Nth stage GOA unit, and a source of the forty-first thin film transistor (T41) is electrically coupled to the control node (Qn) of the Nth stage GOA unit.

A drain of the thirty-first thin film transistor (T31) and a drain of the forty-first thin film transistor (T41) are electrically coupled to the first direct current low voltage level terminal (VSSQ), and a gate of the thirty-first thin film transistor (T31) and a gate of the forty-first thin film transistor (T41) are electrically coupled to the transfer signal terminal (STn+4) of the (N+4)th stage GOA unit.

In the present disclosure, the pull-up control unit and the bootstrap unit sequentially control the control node of the Nth stage GOA unit to be pulled up to the first high voltage level and the second high voltage level. The pull-up unit outputs the gate driving signal according to the change of the voltage level of the control node and the stage transfer signal of the Nth stage GOA unit. As such, the pulse width of the gate driving signal is increased, and the problem that the charging ability is not sufficient can be solved.

