BACKGROUND

Technical Field

The disclosure relates to a semiconductor structure and a manufacturing method thereof, and particularly relates to a package structure and a manufacturing method thereof.

Description of Related Art

The key to heterogeneous chiplet integration is the electrical connection between two chips. At present, Intel uses the embedded multi-die interconnect bridge (EMIB) to connect two chips, so as to achieve partial or local high-density interconnection. However, the issue encountered by the technology is that a bridge must be embedded in an organic substrate through the lamination technology, so the surface needs to be flat enough to perform the subsequent flip-chip packaging of the chips.

SUMMARY

The disclosure provides a package structure, which has better structural reliability, especially a flat surface for flip chip bonding.

The disclosure also provides a manufacturing method of a package structure, which is used to manufacture the package structure.

The package structure of the disclosure includes a bridge, an interposer, a first redistribution structure layer, a second redistribution structure layer, and multiple chips. The bridge includes a silicon substrate, a redistribution circuit layer, and multiple bridge pads. The redistribution circuit layer is disposed on the silicon substrate. The bridge pads are disposed on the redistribution circuit layer and are electrically connected to the redistribution circuit layer. The interposer includes an intermediate layer, multiple conductive vias, multiple first pads, and multiple second pads. The intermediate layer has an upper surface and a lower surface opposite to each other. The conductive vias penetrate the intermediate layer and are respectively connected to the first pads located on the upper surface and the second pads located on the lower surface. The bridge is embedded in the intermediate layer and the bridge pads are aligned with the upper surface. The first redistribution structure layer is disposed on the upper surface of the interposer and is electrically connected to the first pads and the bridge pads of the bridge. The second redistribution structure layer is disposed on the lower surface of the interposer and is electrically connected to the second pads. The chips are disposed on the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The chips are electrically connected to each other through the bridge.

In an embodiment of the disclosure, the package structure further includes a multiple chip pads, which are disposed on the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The chips are electrically connected to the first redistribution structure layer and the bridge through the chip pads.

In an embodiment of the disclosure, the package structure further includes multiple copper pillars, multiple solders, and multiple solder balls. The copper pillars are respectively disposed on the chips. The solders are respectively disposed on the copper pillars. The copper pillars are respectively located between the chips and the solders. The chips are electrically connected to the bridge through the copper pillars and the solders. The solder balls are disposed on the chips. The chips are electrically connected to the first redistribution structure layer through the solder balls.

In an embodiment of the disclosure, the package structure further includes multiple solder ball pads and multiple solder balls. The solder ball pads are disposed on the second redistribution structure layer and are electrically connected to the second redistribution structure layer. The solder balls are respectively disposed on the solder ball pads.

The manufacturing method of the package structure of the disclosure includes the following steps. A bridge is provided. The bridge includes a silicon substrate, a redistribution circuit layer, and multiple bridge pads. The redistribution circuit layer is disposed on the silicon substrate. The bridge pads are disposed on the redistribution circuit layer and are electrically connected to the redistribution circuit layer. The bridge is embedded in an interposer. The interposer includes an intermediate layer, multiple conductive vias, multiple first pads, and multiple second pads. The intermediate layer has an upper surface and a lower surface opposite to each other. The conductive vias penetrate the intermediate layer and are respectively connected to the first pads on the upper surface and the second pads on the lower surface. The bridge pads are aligned with the upper surface. A first redistribution structure layer is formed on the upper surface of the interposer. The first redistribution structure layer is electrically connected to the first pads and the bridge pads of the bridge. A second redistribution structure layer is formed on the lower surface of the interposer. The second redistribution structure layer is electrically connected to the second pads. Multiple chips are disposed on the first redistribution structure layer. The chips are electrically connected to the first redistribution structure layer. The chips are electrically connected to each other through the bridge.

In an embodiment of the disclosure, the step of embedding the bridge in the interposer includes the following steps. The bridge is disposed on a temporary substrate. The bridge pads face the temporary substrate. The intermediate layer is formed on the temporary substrate. The intermediate layer covers the bridge. The temporary substrate is removed to expose the upper surface of the intermediate layer. Multiple vias penetrating the intermediate layer are formed. The conductive vias, the first pads, and the second pads are formed on the intermediate layer. The conductive vias are respectively located in the vias and connect the first pads and the second pads.

In an embodiment of the disclosure, the manufacturing method of the package structure further includes the following step. Multiple chip pads electrically connected to the first redistribution structure layer are formed on the first redistribution structure layer after forming the first redistribution structure layer on the upper surface of the interposer.

In an embodiment of the disclosure, before disposing the chips on the first redistribution structure layer, the manufacturing method further includes the following steps. Multiple copper pillars are respectively formed on the chips. Multiple solders are respectively formed on the copper pillars. The copper pillars are located between the chips and the solders. The chips are electrically connected to the bridge through the copper pillars and the solders. Multiple solder balls are formed on the chips. The chips are electrically connected to the first redistribution structure layer through the solder balls.

In an embodiment of the disclosure, the manufacturing method of the package structure further includes the following steps. Multiple solder ball pads electrically connected to the second redistribution structure layer are formed on the second redistribution structure layer after forming the second redistribution structure layer on the lower surface of the interposer. Multiple solder balls are respectively formed on the solder ball pads.

In an embodiment of the disclosure, the bridge is formed by singulated cutting of a wafer.

Based on the above, in the design of the package structure of the disclosure, the bridge having the redistribution circuit layer and the bridge pads is embedded in the interposer, and the bridge pads are aligned with the upper surface of the intermediate layer. Therefore, the first redistribution structure layer subsequently formed on the interposer may have better flatness. In addition, when the chips are subsequently bonded onto the first redistribution structure layer in a flip-chip manner, each chip may not only be electrically connected to an external circuit through the first redistribution structure layer, the interposer, and the second redistribution circuit layer, two chips may also be electrically connected to each other through the bridge, so as to achieve partial or local high-density interconnection. In short, the package structure of the disclosure can have better structural reliability (due to flatness) and chip-to-chip interconnect densities in a way that is cost-effective.

In order for the features and advantages of the disclosure to be more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

