CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit of priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0170409, filed on Dec. 19, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

The present disclosure relates to memory devices.

A memory device may provide functions including writing data, reading written data, and/or erasing data. A memory device may include a plurality of memory cells and a memory controller, and the memory cells may be connected to the memory controller through wordlines and bitlines. As the integration density of memory devices is increased, various failures may occur or may potentially occur in the memory cells, the memory controller, and/or in the wordlines and bitlines.

SUMMARY

Aspects of the present disclosure provide memory devices which may effectively detect internal potential failures to improve quality thereof.

According to some example embodiments, a memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a wordline driving circuit including a plurality of sub-wordline decoders connected respectively to the plurality of wordlines, wherein each of the sub-wordline decoders is configured to input a first driving signal to the respectively connected wordline when the wordline is selected, and each sub-wordline decoder is configured to input a predetermined power supply voltage to the respectively connected wordline when the wordline is unselected. A sense amplifier circuit including sense amplifiers is connected to the bitlines, and a logic circuit is configured to determine a failure of at least one of the memory cell array and the wordline driving circuit by floating unselected sub-wordline decoders while the first driving signal is input to the selected wordline, and detecting data of unselected memory cells connected to the unselected wordlines using at least one of the sense amplifiers.

According to some example embodiments, a memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a wordline driving circuit including sub-wordline decoders connected to the wordlines, wherein each of the sub-wordline decoders is connected to a power line, and is configured to output a predetermined power supply voltage, through a power switch, and a logic circuit configured to control the power switch.

According to some example embodiments, a memory device includes a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, connection circuits configured to generate a driving signal to drive the memory cells, sub-wordline decoders connected between the connection circuits and the plurality of wordlines and configured to determine a selected wordline and unselected wordlines from the plurality of wordlines, and a logic circuit configured to control the sub-wordline decoders such that a power supply voltage is input to the plurality of wordlines during a first time and to control the sub-wordline decoders such that a driving voltage, higher than the power supply voltage, is input to the selected wordline and the unselected wordlines are floated during a second time subsequent to the first time.

