CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0032344, filed on Mar. 21, 2019, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

Exemplary embodiments of the present invention relate to a display device.

Discussion of the Related Art

A light emitting diode display has a self-emissive characteristic, and unlike a liquid crystal display, does not require a separate light source. As a result, the thickness and the weight of the display can be reduced. In addition, a light emitting diode display has high-grade characteristics such as, for example, low power consumption, high luminance, and a high response speed.

In general, a light emitting diode display includes a substrate, a plurality of thin film transistors disposed on the substrate, a plurality of insulation layers disposed between wires that form the thin film transistors, and a light emitting element that is connected to the thin film transistor. The light emitting element may be, for example, an organic light emitting element.

SUMMARY

Exemplary embodiments provide a display device of which resistance of wires can be reduced and display quality can be improved.

According to an exemplary embodiment, a display device includes a substrate, a first conductive layer disposed on the substrate, a first insulation layer disposed on the first conductive layer, and a plurality of active patterns disposed on the first insulation layer. The active patterns include a source region, a channel region, and a drain region. The display device further includes a second conductive layer disposed on the active patterns and including a first gate electrode that overlaps the channel region and a driving gate electrode, a second insulation layer disposed on the second conductive layer, a third conductive layer including a capacitor electrode and at least one scan line disposed on the second insulation layer, a third insulation layer disposed on the third conductive layer, and an electrode layer including a first electrode disposed on the third insulation layer. The first electrode is connected to the capacitor electrode, the capacitor electrode overlaps the driving gate electrode, and the capacitor electrode and the driving gate electrode form a capacitor.

In an exemplary embodiment, the capacitor electrode is electrically connected to the first conductive layer.

In an exemplary embodiment, the second conductive layer further includes an overlapped gate pattern that overlaps the at least one scan line.

In an exemplary embodiment, the third insulation layer includes an organic material.

In an exemplary embodiment, the display device further includes a fourth conductive layer disposed between the third insulation layer and the electrode layer. The fourth conductive layer includes a data line, a driving voltage line, a common voltage line, an initialization voltage line, and a plurality of connection patterns.

In an exemplary embodiment, the at least one scan line includes a first scan line and a second scan line, the second conductive layer further includes a second gate electrode, and the first scan line and the second gate electrode are connected to each other by one connection pattern from among the plurality of connection patterns.

In an exemplary embodiment, the first electrode and the capacitor electrode are connected to each other through one of the plurality of connection patterns.

In an exemplary embodiment, the third conductive layer further includes a plurality of connection electrodes, the plurality of active patterns include a first active pattern, a second active pattern, and a third active pattern, and each active pattern is connected to at least one of the plurality of connection electrodes of the third conductive layer.

In an exemplary embodiment, a resistance of the third conductive layer is lower than a resistance of the second conductive layer.

According to an exemplary embodiment, a display device includes a substrate, a first conductive layer disposed on the substrate, a first insulation layer disposed on the first conductive layer, and a plurality of active patterns disposed on the first insulation layer and including a source region, a channel region, and a drain region. The display device further includes a second conductive layer disposed on the active patterns and including a plurality of data overlapped lines, a second insulation layer disposed on the second conductive layer, a third conductive layer disposed on the second insulation layer and including a plurality of data lines, a common voltage line and at least one scan line, a third insulation layer disposed on the third conductive layer, and an electrode layer including a first electrode disposed on the third insulation layer. The plurality of data lines overlap the plurality of data overlapped lines, respectively, and the at least one scan line overlaps the first conductive layer.

In an exemplary embodiment, the second conductive layer further includes a common voltage overlapped line, the common voltage line overlaps the common voltage overlapped line and the first conductive layer, and the common voltage line is electrically connected to the common voltage overlapped line and the first conductive layer.

In an exemplary embodiment, the third conductive layer further includes a driving voltage line and an initialization voltage line, the second conductive layer includes a plurality of gate patterns, and the plurality of gate patterns, the driving voltage line, and the initialization voltage line respectively overlap each other.

In an exemplary embodiment, the first conductive layer includes a plurality of lower patterns, and one of the plurality of lower patterns is disposed in a direction that crosses the common voltage line and is connected to the common voltage line.

In an exemplary embodiment, the plurality of active patterns include a first active pattern, a second active pattern, and a third active pattern, the at least one scan line includes a first scan line and a second scan line, an extending portion of the first scan line extends in a direction that is different from a remaining portion of the first scan line, and the extending portion of the first scan line overlaps the channel regions of the first active pattern and the third active pattern.

In an exemplary embodiment, an extending portion of the second scan line extends in a direction that is different from a remaining portion of the second scan line, and the extending portion of the second scan line overlaps the channel region of the second active pattern.

In an exemplary embodiment, the display device further includes a pad electrode disposed on a same layer as the third conductive layer, and a pad connection electrode disposed on a same layer as the second conductive layer. The pad electrode is electrically connected to the first conductive layer, and the pad electrode is electrically connected to the pad connection electrode.

In an exemplary embodiment, the second conductive layer further includes a driving gate electrode, and the third conductive layer further includes a capacitor that overlaps the driving gate electrode.

In an exemplary embodiment, the first conductive layer includes a plurality of lower patterns, and at least one of the plurality of lower patterns overlaps the capacitor electrode.

In an exemplary embodiment, the display device further includes a first electrode connected to the capacitor electrode.

According to an exemplary embodiment, a display device includes a substrate, a first conductive layer disposed on the substrate, and a transistor disposed on the first conductive layer and including a gate electrode and an overlapped gate electrode. The gate electrode is formed in a second conductive layer disposed on the first conductive layer, and the overlapped gate electrode is formed in a third conductive layer disposed on the second conductive layer. The display device further includes a capacitor including a driving gate electrode and a capacitor electrode, and a scan line formed in the third conductive layer. The capacitor electrode overlaps the driving gate electrode, the capacitor electrode is formed in the third conductive layer, and the driving gate electrode is formed in the second conductive layer.

