This application claims priority to Chinese Patent Application No. CN201821823522.1, filed with the Chinese Patent Office on Nov. 6, 2018, and entitled “DISPLAY PANEL AND DISPLAY APPARATUS”, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

This application relates to the field of display technologies, and in particular, to a display panel and a display apparatus.

BACKGROUND

It should be understood that descriptions herein merely provide background information related to this application, and do not necessarily constitute the prior art. With development and advancement of science and technologies, owing to hot spots such as thin body, power saving, and low radiation, displays become mainstream products of displays and are widely applied. A flat panel display includes a thin film transistor-liquid crystal display (TFT-LCD), an organic light-emitting diode (OLED) display, and the like. The TFT-LCD controls rotating directions of liquid crystal molecules, to enable light in a backlight module to be refracted out to generate a picture, and the TFT-LCD has various advantages such as thin body, power saving, and no radiation. The OLED display is manufactured by using an organic electroluminescent diode, and has various advantages such as self-luminescent, short response time, high resolution and contrast, flexible display, and large area full color display.

A frame of a display has a lot of wires, a short circuit occurs between two signal lines when a particle drops onto the wires and causes a misoperation, with a result that a circuit transmission fails and a yield is reduced.

SUMMARY

An objective of this application is to provide a display panel and a display apparatus, so as to enhance a display yield.

This application provides a display panel. The display panel comprises a first signal line and a second signal line, wherein the first signal line and the second signal line are different metal layers; an overlapping region is formed at an intersection of the second signal line and the first signal line; and the first signal line comprises a connection line, the connection line comprises at least two sub-connection lines, and the connection line crosses the overlapping region.

Optionally, the first signal line further comprises at least two sub-signal lines, two neighboring sub-signal lines are respectively arranged at two sides of the overlapping region, and the two neighboring sub-signal lines are connected through the connection line.

Optionally, the connection line comprises a first sub-connection line, a second sub-connection line, and a third sub-connection line, and the first sub-connection line and the third sub-connection line are arranged symmetrically relative to the second sub-connection line.

Optionally, a line length of the second sub-connection line is less than a line length of the first sub-connection line and a line length of the third sub-connection line, and the line length of the first sub-connection line is equal to the line length of the third sub-connection line.

Optionally, a clearance between the two neighboring sub-signal lines is equal to a width of the overlapping region.

Optionally, a clearance between the two neighboring sub-signal lines is greater than a width of the overlapping region.

Optionally, a clearance between an outer edge of the first sub-connection line and an outer edge of the third sub-connection line is greater than a line width of the signal line.

Optionally, the connection line comprises a first sub-connection line and a third sub-connection line, and the first sub-connection line and the third sub-connection line are arranged symmetrically relative to the neighboring sub-signal lines.

Optionally, a line length of the first sub-connection line is equal to a line length of the third sub-connection line.

Optionally, the connection line comprises a first sub-connection line and a second sub-connection line, and the first sub-connection line and the second sub-connection line are arranged in parallel; and a length of the first sub-connection line and a length of the second sub-connection line are equal to a length of the first signal line.

Optionally, the display panel comprises a timing control circuit configured to provide drive timing of a scanning drive circuit; and the scanning drive circuit configured to drive a scan line of the display panel, wherein one end of the first signal line is connected to the scanning drive circuit and the other end of the first signal line is connected to the second signal line; and the second signal line is connected to the timing control circuit.

Optionally, the scanning drive circuit comprises a plurality of shift register chips; each shift register chip corresponds to a group of first signal lines; each group of first signal lines comprises a first transmission signal line and a second transmission signal line; and starting from an end away from the shift register chips, the second signal line comprises a power line, a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line in sequence;

the first transmission signal line is connected to the power line; the first transmission signal line crosses the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line to respectively form four overlapping regions; every four neighboring shift register chips form one group, and the second transmission signal line is connected to the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line sequentially; and the connection line is arranged corresponding to each overlapping region.

Optionally, the scanning drive circuit comprises a plurality of shift register chips; each shift register chip corresponds to a group of first signal lines; each group of first signal lines comprises a first transmission signal line, a second transmission signal line, and a third transmission signal line; and the second signal line comprises a power line, a first clock signal line, and a second clock signal line;

the power line is connected to the first transmission signal line; the first transmission signal line crosses the first clock signal line and the second clock signal line to respectively form two of the overlapping regions, the second transmission signal line is connected to the first clock signal line to form an overlapping region, the third transmission signal line is connected to the second clock signal line, and the connection line is arranged corresponding to each overlapping region.

This application further discloses a display panel. The display panel comprises a first signal line and a second signal line; an overlapping region is formed at an intersection of the second signal line and the first signal line; the first signal line comprises a connection line, the connection line comprises at least two sub-connection lines, and the first signal line further comprises two neighboring sub-signal lines, and the two neighboring sub-signal lines are connected through the connection line; a clearance between the two neighboring sub-signal lines is equal to a width of the overlapping region; the connection line comprises a first sub-connection line, a second sub-connection line, and a third sub-connection line; the first sub-connection line and the third sub-connection line are arranged symmetrically relative to the second sub-connection line; a line length of the second sub-connection line is less than a line length of the first sub-connection line and a line length of the third sub-connection line, and the line length of the first sub-connection line is equal to the line length of the third sub-connection line; and a clearance of the connection line is greater than a line width of the signal line, a clearance between a first edge of the first sub-connection line and a first edge of the third sub-connection line is greater than the line width of the signal line, and the connection line is arranged corresponding to each overlapping region.

This application further discloses a display panel.

The display apparatus comprises a display panel.

The display panel comprises:

a first signal line; and

a second signal line, wherein the first signal line and the second signal line are different metal layers;

an overlapping region is formed at an intersection of the second signal line and the first signal line; and

the first signal line comprises a connection line, the connection line comprises at least two sub-connection lines, and the connection line crosses the overlapping region.

Optionally, the first signal line further comprises at least two sub-signal lines, two neighboring sub-signal lines are respectively arranged at two sides of the overlapping region, and the two neighboring sub-signal lines are connected through the connection line.

Optionally, the connection line comprises a first sub-connection line, a second sub-connection line, and a third sub-connection line;

the first sub-connection line and the third sub-connection line are arranged symmetrically relative to the second sub-connection line; and

a clearance between an outer edge of the first sub-connection line and an outer edge of the third sub-connection line is greater than line widths of both the two neighboring sub-signal lines.

Optionally, a clearance between the two neighboring sub-signal lines is greater than and equal to a width of the overlapping region.

Optionally, the connection line comprises a first sub-connection line and a second sub-connection line, and the first sub-connection line and the second sub-connection line are arranged in parallel; and a length of the first sub-connection line and a length of the second sub-connection line are equal to a length of the first signal line.

If only one horizontal path of the first signal line is provided in an example, only one path exists when a conductive particle drops onto these wires, and therefore, a signal received by a shift register chip is incorrect, causing transmission to fail. The first signal line in this application includes at least two sub-connection lines that also cross the overlapping region where a particle is easily dropped off, and therefore, a signal can be transmitted to a circuit of the shift register chip correctly from other paths. In this way, the circuit of the shift register chip can operate normally and a yield can be enhanced.

