FIELD OF INVENTION

The present invention relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a method for manufacturing the array substrate.

BACKGROUND OF INVENTION

As shown inFIG. 1, an array substrate90at a peripheral wiring of a current liquid crystal display panel includes a first metal layer91, a gate insulating layer92, a second metal layer93, a passivation layer94, and a conductive layer95that are stacked. In order to realize the first metal layer91and the second metal layer93to conduct electrical signals, it is generally necessary to provide a first via96and a second via97to conduct the conductive layer95to the first metal layer91and the second metal layer93.

There are currently two ways to set vias, one is a dual-hole design (that is, the first via96and the second via97are separated), and the other is a single deep-shallow hole design (that is, the first via96adjacent to the second via97, it looks like a via).

As shown inFIG. 2, it is a top view of a dual-hole design, and in combination withFIG. 1, it can be seen that the first via96is specifically provided on the first metal layer91, and the first via96penetrates the passivation layer94and the gate insulating layer92. The second via97is provided on the second metal layer93, and the second via97penetrates the passivation layer94. Then, a conductive layer95is provided to connect the first metal layer91and the second metal layer93through the first via96and the second via97, but in this way, two holes need to be provided, so an occupied area is large and a pixel aperture ratio will be reduced.

As shown inFIG. 3, it is a top view of the single deep-shallow hole design, in conjunction withFIG. 1, it can be simply understood as a distance between the first via96and the second via97is reduced, so that the passivation layer94between the first via96and the second via97disappears. Therefore, the manufactured first via96and the second via97connect to each other as one via. Since a depth of the first via96is greater than a depth of the second via97, it is called a single deep-shallow hole. Many processing problems and display problems will occur in the deeper first via96, such as the poor lapping connection problem of the undercut of the gate insulating layer92, the bird's beak, and the conductive layer95being broken, etc. caused by a side of the gate insulating layer92being etched, which causes a contact resistance between the first metal layer91and the second metal layer93to increase.

For another example, in a three thin film transistor (TFT)-charge-sharing eight-domain viewing angle improvement technology, where the three TFTs includes a main TFT, a secondary TFT, and a shared TFT, in order to ensure a sufficient aperture ratio, it is necessary to use a single deep-shallow hole structure to increase the aperture ratio, and in the case of a limited size of the deep-shallow hole, the poor lapping connection of the conductive layer will cause current leakage, poor conductivity, and charge accumulation of the shared TFT, which will cause a series of display problems and increase manufacturing costs.

Therefore, it is necessary to design a new array substrate, a display panel, and a manufacturing method of the array substrate to solve the problems in the conventional art.

SUMMARY OF INVENTION

Technical Problem

In view of the shortcomings and deficiencies in the conventional art, the present invention provides an array substrate, a display panel, and an array substrate manufacturing method. By improving a single deep-shallow hole technology, the problem of poor lapping connection of a conductive layer at a deep-shallow hole can be solved, which can further reduce a contact resistance between a first metal layer and a second metal layer in the deep-shallow hole, improving product yield, and reducing production costs.

Technical Solutions

The objective of the present invention is achieved by the following technical solutions.

An object of the present invention is to provide an array substrate including a first metal layer, a gate insulating layer, a second metal layer, a passivation layer, and a conductive layer which are disposed in a stack, and the conductive layer conducts the first metal layer and the second metal layer. Specifically, the gate insulating layer is disposed on the first metal layer, the second metal layer is disposed on the gate insulating layer, the passivation layer is disposed on the second metal layer, and the conductive layer is disposed on the passivation layer.

The array substrate further includes a first via and a second via. Specifically, the first via penetrates the passivation layer and the gate insulation layer, and exposes the first metal layer. The second via penetrates the passivation layer and exposes the second metal layer, wherein the conductive layer fills the first via and the second via to electrically connect the first metal layer and the second metal layer, the first via is disposed on a side of the second via, and the passivation layer partially extends between the first via and the second via.

Furthermore, a distance between the first via and the second via is less than two times a photoresist layer etching fade distance, and the photoresist layer etching fade distance is an etching fade distance of a photoresist layer provided to protect the passivation layer when the first via and the second via are made.

Furthermore, material of the first metal layer or the second metal layer includes one or a stacked combination of copper, aluminum, and molybdenum.

Furthermore, the gate insulating layer or the passivation layer is made of silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride.

Furthermore, material of the conductive layer includes indium tin oxide.

Another object of the present invention is to provide a display panel including the array substrate according to any one of the above.

Another object of the present invention is to provide a method for manufacturing an array substrate, including the following steps:

forming a first metal layer, wherein a glass substrate is provided, and a first metal layer is formed on the glass substrate;

forming a gate insulating layer, wherein the gate insulating layer is formed on the first metal layer;

forming a second metal layer, wherein the second metal layer is formed and patterned on the gate insulating layer;

forming a passivation layer, wherein the passivation layer is formed on the gate insulating layer, the passivation layer covers the second metal layer, and the passivation layer partially extends on the first metal layer;

forming a photoresist layer, wherein the photoresist layer is formed on the passivation layer, the photoresist layer includes a first etching hole and a second etching hole, and the second etching hole is disposed opposite to the second metal layer and the first etching hole is disposed on a side of the second etching hole;

an etching and digging hole step, etching on a side of the photoresist layer, and forming a first via corresponding to the first etching hole and a second via corresponding to the second etching hole after etching; wherein the first via penetrates the passivation layer and the gate insulation layer and exposes the first metal layer, the second via penetrates the passivation layer and exposes the second metal layer, and the passivation layer partially extends between the first via and the second via;

a photoresist layer removing step, removing the remaining photoresist layer; and

forming a conductive layer, wherein the conductive layer is formed on a side of the passivation layer, the conductive layer is disposed in the first via and the second via and conducts the first metal layer and the second metal layer.

Furthermore, a method of removing the remaining photoresist layer is to dry and bake the photoresist layer to make the photoresist layer fall off.

Furthermore, the step of forming the photoresist layer includes:

setting a photomask, disposing the photomask above the photoresist layer, wherein the photomask includes a first through hole and a second through hole; and

photolithographing, wherein the photoresist layer forms a first etching hole corresponding to the first through hole and a second etching hole corresponding to the second through hole after photolithographing.

Furthermore, the photomask includes a half tone mask.

Beneficial Effect

The beneficial effect of the present invention is to provide an array substrate, a display panel, and a method for manufacturing the array substrate. By improving the via structure of the single deep-shallow hole to adjust the distance between the first via and the second via to realize that the passivation layer between the first via and the second via is retained in the manufacturing process, which can avoid poor lapping connection problems easily encountered in the deeper first via such as the undercut of the gate insulating layer, the bird's beak, and the conductive layer being broken, etc. caused by a side of the gate insulating layer being etched. It can solve the poor lapping connection problem of the conductive layer in the deep-shallow hole (that is, the combination of the first via and the second via), and further reduce the contact resistance between the first metal layer and the second metal layer in the single deep-shallow hole, improving product yield, and reducing production costs.

