FIELD OF THE DISCLOSURE

The present disclosure relates to a semiconductor chip and a process for making the same, and more particularly to a semiconductor chip suitable for 2.5-dimensional (2.5D) and 3D packaging integration and a fabrication process of the semiconductor chip utilizing selective substrate removal.

BACKGROUND

The market for portable and mobile data access devices is growing rapidly, driving the demand for increased functional convergence. Integrated circuit (IC) packaging has evolved, such that multiple IC chips may be vertically stacked in so-called three-dimensional (3D) packages in order to save horizontal area over a substrate. An alternative packaging technique, referred to as a 2.5D package, may utilize a semiconductor interposer for coupling one or more IC chips to a substrate. Herein, the IC chips mounted on the semiconductor interposer may be of heterogeneous technologies. Connections among the various ICs are routed through conductive patterns in the semiconductor interposer.

Typically, metal pillar bumps with heights in the range of 50 μm to 100 μm are used in IC chips for 2.5D or 3D packaging. However, metal pillar bumps face design and uniformity issues due to various process limitations, especially for monolithic microwave integrated circuit (MMIC) chips with a microstrip design. The MMIC chips are typically thinned to 100 μm or 50 μm. It is significantly challenging and expensive to fabricate metal pillar bumps with a height between 50 μm and 100 μm. The metal pillar bumps also have size and shape constraints. Further, significant portions of the substrates of the MMIC chips are removed and wasted in standard fabrication processes due to thin thickness requirements.

Accordingly, the object of the present disclosure is to provide an improved chip design suitable for 2.5D and 3D packaging integration without metal pillar challenges and limitations. In addition, the present chip design utilizes the substrate material to enhance cost effectiveness and design flexibility.

SUMMARY

The present disclosure relates to a fabrication process of a semiconductor chip utilizing selective substrate removal. The disclosed process starts with providing a precursor wafer mounted on a carrier. The precursor wafer includes a precursor substrate and a number of component portions between the carrier and the precursor substrate. The precursor substrate is then thinned down to provide a thinned substrate, which includes a substrate base adjacent to the component portions and an etchable region over the substrate base. Next, the etchable region is selectively etched to generate a number of protrusions over the substrate base. Herein, the substrate base is retained, and portions of the substrate base are exposed through the protrusions. Each protrusion protrudes from the substrate base and has a same height. A metal layer is then applied to provide a semiconductor wafer. The metal layer selectively covers the exposed portions of the substrate base and covers at least a portion of each protrusion.

According to another embodiment, the process further includes demounting the semiconductor wafer from the carrier.

In one embodiment of the process, the precursor substrate is formed of silicon carbide (SiC), diamond, silicon (Si), or gallium arsenide (GaAs). The component portions include electronic components, which are formed of at least one of gallium nitride (GaN), GaAs, diamond, Si, silicon nitride, silicon oxide, tantalum nitride and nichrome.

In one embodiment of the process, the precursor substrate has a thickness between 400 μm and 700 μm, the thinned substrate has a thickness between 50 μm and 250 μm, the substrate base has a thickness between 25 μm and 100 μm, and each protrusion has a same height between 25 μm and 150 μm.

In one embodiment of the process, the metal layer is formed of gold (Au), copper (Cu), gold-tin (AuSn), or copper-tin (CuSn), with a thickness between 4 μm and 25 μm.

In one embodiment of the process, thinning down the precursor substrate is provided by at least one of a mechanical grinding process and a polishing process.

In one embodiment of the process, selectively etching the etchable region is provided by a reactive ion etching process.

In one embodiment of the process, applying the metal layer is provided by a combination of sputtering and electroplating.

According to another embodiment, the process further includes forming of at least one via hole that extends vertically through one of the protrusions and the substrate base. Herein, the metal layer fully covers inner surfaces of the at least one via hole, and a certain one of the component portions is electrically coupled to a portion of the metal layer within the at least one via hole.

In one embodiment of the process, forming the at least one via hole is provided by a reactive ion etching process.

In one embodiment of the process, the protrusions include a number of bias pillar bases, the at least one via hole includes a number of bias via holes, and the exposed portions of the substrate base include a number of isolation areas. Herein, each bias via hole is located at the center of a corresponding bias pillar base, and extends vertically through the corresponding bias pillar base and the substrate base. Each isolation area surrounds a corresponding bias pillar base. The metal layer fully covers exposed surfaces of each bias pillar base, fully covers inner surfaces of each bias via hole, and fully covers the exposed portions of the substrate base except the isolation areas.

In one embodiment of the process, the protrusions include a periphery ridge base that resides over a perimeter of the substrate base, and the at least one via hole includes a number of periphery via holes. Herein, the periphery via holes are scattered within the periphery ridge base and each periphery via hole extends vertically through the periphery ridge base and the substrate base. The metal layer fully covers exposed surfaces of the periphery ridge except outward side surfaces of the periphery ridge, and fully covers inner surfaces of each of the plurality of periphery via holes.

In one embodiment of the process, the periphery ridge base is continuous.

In one embodiment of the process, the periphery ridge base is discontinuous and includes separate periphery portions. Herein, the periphery via holes are located in certain ones of the periphery portions. The metal layer fully covers exposed surfaces of each periphery portion except outward side surfaces of each periphery portion.

In one embodiment of the process, the protrusions include an inner ridge base that resides over an interior portion of the substrate base, and the at least one via hole includes a number of inner via holes. Herein, the inner via holes are scattered within the inner ridge base and each inner via hole extends vertically through the inner ridge base and the substrate base. The metal layer fully covers exposed surfaces of the inner ridge base and inner surfaces of each inner via hole to form an inner ridge structure, which is configured to provide RF signal isolation between adjacent component portions located at opposite sides of the inner ridge structure.

In one embodiment of the process, the protrusions include a number of bias pillar bases and a number of ground pillar bases, the at least one via hole includes a number of bias via holes, and the exposed portions of the substrate base include a number of isolation areas. Herein, each bias via hole is located at a center of a corresponding bias pillar base, and extends vertically through the corresponding bias pillar base and the substrate base. Each isolation area surrounds a corresponding bias pillar base. The metal layer fully covers exposed surfaces of each bias pillar base, fully covers inner surfaces of each bias via hole, fully covers exposed surfaces of each ground pillar base, and fully covers the exposed portions of the substrate base except the isolation areas.

In one embodiment of the process, the at least one via hole further includes a number of ground via holes. Herein, each ground via hole is located at the center of a corresponding ground pillar base, and extends vertically through the corresponding ground pillar base and the substrate base. The metal layer fully covers inner surfaces of each ground via hole.

In one embodiment of the process, each bias pillar base has a cylinder shape with a diameter between 10 μm and 150 μm, or has a cuboid shape with a bottom area between 10 μm×10 μm and 100 μm×100 μm. Each bias via hole is a circular via hole with a diameter between 5 μm and 60 μm, or a rectangular via hole with a bottom size between 5 μm×5 μm and 50 μm×50 μm. Each ground pillar base has a cylinder shape with a diameter between 10 μm and 150 μm, or has a cuboid shape with a bottom area between 10 μm×10 μm and 100 μm×100 μm.

In one embodiment of the process, each bias pillar base and each ground pillar base have a same shape and a same size.

In one embodiment of the process, the protrusions include a mesa base, and the at least one via hole includes a number of mesa via holes. The mesa via holes are scattered within the mesa base, and each mesa via hole extends vertically through the mesa base and the substrate base. The metal layer fully covers exposed surfaces of the mesa base and inner surfaces of each mesa via hole to form a mesa structure, which is electrically coupled to one component portion, and configured to provide integrated thermal management of the corresponding component portion.

In one embodiment of the process, a size of the mesa structure is not smaller than the corresponding component portion, such that the mesa structure fully covers the corresponding component portion.

In one embodiment of the process, the protrusions provide at least one shape of a cylinder, a cube, and a cuboid.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

