BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure relates to the inspection of manufactured components or devices using automated apparatus and methods.

2. Description of the Background Art

Integrated circuit packaging technologies have evolved and become more complex over time. Two-dimensional integrated circuit packaging has developed to accommodate increasingly dense connections and now includes, for example, dual-in-line packages, quad flat packages, pin grid arrays, and ball grid arrays.

Furthermore, three-dimensional (3D) integration is increasingly being employed in advanced packaging of integrated circuits. One example of such 3D packaging technology provides interconnections by way of an interposer between two or more semiconductor devices, a semiconductor device and a printed circuit board, or a semiconductor device and some other package component. The interposer may be a silicon wafer in which vias that pass through the silicon, and are filled with electrically conductive material, such as copper or tungsten, have been manufactured. An active silicon device may also function as an interposer.

When integrated circuits are bonded to both sides of the interposer, the through-silicon vias (TSVs) allow signals from one IC to travel a relatively short distance vertically from one integrated circuit to another. When integrated circuits are bonded to a PCB using an interposer, the TSVs allow signals from the integrated circuits on one side of the interposer to connect the PCB. Such TSVs may have an aspect ratio of 10:1 or more.

In certain advanced packaging solutions, a single interposer may serve as the interconnection between memory integrated circuits, which contain billions of memory cells, and a logic integrated circuit for a microprocessor. Such an interposer may need many thousands of TSVs. These TSVs form vital communication links between logic and memory and their proper functioning is of critical importance.

SUMMARY

The present disclosure provides methods and apparatus for rapidly classifying detected defects in subcomponents of a manufactured component or device. The defect classification may occur after defect detection or, because the classification may be sufficiently rapid to be performed in real-time, during defect detection, as part of the defect detection process.

In an exemplary implementation, the presently-disclosed technology may be utilized to enable real-time classification of detected defects in multiple subcomponents of the component. The component may be, for example, a multi-chip package with silicon interposers, and the subcomponents may include, for example, through-silicon vias and solder joints. Defects in subcomponents of other types of components may be also be classified.

One embodiment relates to a method of classifying detected defects in subcomponents of a manufactured component. Another embodiment relates to a product manufactured using a disclosed method of inspecting multiple subcomponents of a component for defects. Other embodiments, aspects and features are also disclosed.

