TECHNICAL FIELD

The present invention relates generally to operating of quantum devices. More particularly, the present invention relates to simultaneously driving adjacent qubit pairs.

BACKGROUND

Hereinafter, a “Q” or “q” prefix in a word of phrase is indicative of a reference of that word or phrase in a quantum computing context unless expressly distinguished where used.

Molecules and subatomic particles follow the laws of quantum mechanics, a branch of physics that explores how the physical world works at the most fundamental levels. At this level, particles behave in strange ways, taking on more than one state at the same time, and interacting with other particles that are very far away. Quantum computing harnesses these quantum phenomena to process information.

The computers we use today are known as classical computers (also referred to herein as “conventional” computers or conventional nodes, or “CN”). A conventional computer uses a conventional processor fabricated using semiconductor materials and technology, a semiconductor memory, and a magnetic or solid-state storage device, in what is known as a Von Neumann architecture. Particularly, the processors in conventional computers are binary processors, i.e., operating on binary data represented in 1 and 0.

A quantum processor (q-processor) uses the odd nature of entangled qubit devices (compactly referred to herein as “qubit,” plural “qubits”) to perform computational tasks. In the particular realms where quantum mechanics operates, particles of matter can exist in multiple states—such as an “on” state, an “off” state, and both “on” and “off” states simultaneously. Where binary computing using semiconductor processors is limited to using just the on and off states (equivalent to 1 and 0 in binary code), a quantum processor harnesses these quantum states of matter to output signals that are usable in data computing.

Conventional computers encode information in bits. Each bit can take the value of 1 or 0. These 1s and 0s act as on/off switches that ultimately drive computer functions. Quantum computers, on the other hand, are based on qubits, which operate according to two key principles of quantum physics: superposition and entanglement. Superposition means that each qubit can represent both a 1 and a 0 at the same time. Entanglement means that qubits in a superposition can be correlated with each other in a non-classical way; that is, the state of one (whether it is a 1 or a 0 or both) can depend on the state of another, and that there is more information that can be ascertained about the two qubits when they are entangled than when they are treated individually.

Using these two principles, qubits operate as more sophisticated processors of information, enabling quantum computers to function in ways that allow them to solve difficult problems that are intractable using conventional computers. IBM has successfully constructed and demonstrated the operability of a quantum processor (IBM is a registered trademark of International Business Machines corporation in the United States and in other countries.)

A superconducting qubit may include a Josephson junction. A Josephson junction is formed by separating two thin-film superconducting metal layers by a non-superconducting material. When the metal in the superconducting layers is caused to become superconducting—e.g. by reducing the temperature of the metal to a specified cryogenic temperature—pairs of electrons can tunnel from one superconducting layer through the non-superconducting layer to the other superconducting layer. In a superconducting qubit, the Josephson junction—which has a small inductance—is electrically coupled in parallel with one or more capacitive devices forming a nonlinear resonator.

SUMMARY

The illustrative embodiments provide for simultaneously driving adjacent qubit pairs. An embodiment includes a quantum computing system comprising a first cross-resonance (CR) gate having a first control qubit and a first target qubit, wherein the first control qubit is coupled with the first target qubit. The embodiment also includes a second CR gate having a second control qubit and a second target qubit, wherein the second control qubit is coupled with the second target qubit and the first control qubit. The embodiment also includes controller circuitry comprising a processor and a memory having computer readable code, wherein the processor, in response to retrieving and executing the computer readable code, causes the controller circuitry to perform operations comprising first and second iterations of: during a first time period, directing respective CR pulses to the first and second control qubits; during a second time period, directing respective single qubit pulses to the first control qubit and to the second target qubit; during a third time period, directing respective CR pulses to the first and second control qubits; and during a fourth time period, directing respective single qubit pulses to the second control qubit and to the first target qubit. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the embodiment. Thus, the embodiment provides a quantum structure that avoids errors arising from simultaneously pulsing neighboring qubits without the need for an intervening idle qubit.

In some such embodiments, the single qubit pulses of the second time period end before the third time period. In some such embodiments, the CR pulses of the first time period end before the second time period. In some such embodiments, the CR pulses of the third time period end before the fourth time period.

In another embodiment, the processor designates the first CR gate sequence as a first type of CR gate sequence that is applied to the first CR gate and the second CR gate sequence as a second type of CR gate sequence that is applied to the second CR gate.

In another embodiment, the designating of the first CR gate sequence as the first type of CR gate sequence for the first CR gate comprises detecting that the first control qubit is coupled with the second control qubit.

In another embodiment, the designating of the second CR gate sequence as the second type of CR gate sequence for the second CR gate comprises detecting that the second control qubit is coupled with the first control qubit and detecting that the first CR gate is the first type of CR gate.

In another embodiment, during the first and third time periods, the CR pulses to the first control qubit are in phase with each other and the CR pulses to the second control qubit are 180 degrees out of phase with each other.

In another embodiment, a system comprises a processor, one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media, the program instructions executable by the processor to cause the processor to perform operations comprising directing, in a system comprising a first CR gate having a first control qubit and a first target qubit and a second CR gate having a second control qubit and a second target qubit, simultaneous CR pulses to the first and second control qubits during first, third, fifth, and seventh time periods. In the embodiment, the first control qubit is coupled with the first target qubit, and the second control qubit is coupled with the second target qubit and the first control qubit. In the embodiment, during the first and third time periods, the CR pulses to the first control qubit are in phase with each other and the CR pulses to the second control qubit are 180 degrees out of phase with each other. In the embodiment, during the fifth and seventh time periods, the CR pulses to the first control qubit are in phase with each other and the CR pulses to the second control qubit are 180 degrees out of phase with each other. The embodiment also includes directing, following the CR pulses, simultaneous primary pulses to the first control qubit o0f the first CR gate and the second target qubit of the second CR gate during second and sixth time periods and simultaneous secondary pulses to the first target qubit of the first CR gate and the second control qubit of the second CR gate during fourth and eighth time periods.

Another embodiment includes a computer usable program product. The computer usable program product includes a computer-readable storage medium, and program instructions stored on the storage medium.

Another embodiment includes a plurality of CR gates having respective pairs of qubits that are arranged such that the qubits define vertices of a lattice structure and connections between qubits of neighboring CR gates define edges of the lattice structure, where each of the CR gates includes a respective target qubit and a respective control qubit. The embodiment also includes controller circuitry comprising a processor and a memory having computer readable code, where the processor, in response to retrieving and executing the computer readable code, causes the controller circuitry to perform operations comprising generating a first type of echo sequence that generates a CR pulse during a first and fifth time periods, operates on a first control qubit during second and sixth time periods, generates a CR pulse during third and seventh time periods, and operates on a first target during fourth and eighth time periods. The embodiment further includes generating a second type of echo sequence that generates a CR pulse during the first and fifth time periods, operates on a second target qubit during the second and sixth time periods, generates a CR pulse during the third and seventh time periods, and operates on a second control qubit during the fourth and eighth time periods. The embodiment further includes designating each of a first group of the plurality of CR gates as first types of CR gates that receive the first type of echo sequence. The embodiment further includes designating each of a second group of the plurality of CR gates as second types of CR gates that receive the second type of echo sequence.

Thus, the embodiment provides a quantum computing device having a lattice structure and control circuitry that avoids errors arising from simultaneously pulsing neighboring qubits in a lattice arrangement without the need for an intervening idle qubit.

