CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority to Japanese Patent Application No. 2019-092411, filed on May 15, 2019, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The art disclosed herein relates to a semiconductor device.

BACKGROUND

Japanese Patent Application Publication No. 2009-146950 describes a semiconductor device. This semiconductor device is provided with a semiconductor chip, an encapsulant encapsulating the semiconductor chip therein, and a conductor member joined to the semiconductor chip within the encapsulant. The semiconductor chip and the conductor member are joined by a solder layer.

SUMMARY

When a semiconductor chip and a conductor member are soldered together, excessive solder may overflow from between the semiconductor chip and the conductor member. If the excessive solder spreads toward the semiconductor chip in such a circumstance, there is a risk of occurrence of defects such as short circuiting and insufficient insulation in the semiconductor chip. Due to this, it is preferable for the excessive solder to spread over the conductor member. However, if a surface of the conductor member is broadly covered by the solder, an adhering degree between the conductor member and an encapsulant may decrease, by which durability of a semiconductor device may be degraded, for example. The description herein provides an art configured to suppress such a circumstance from occurring and improve durability of a semiconductor device.

A semiconductor device disclosed herein may comprise: a semiconductor chip; an encapsulant encapsulating the semiconductor chip therein; and a conductor member joined to the semiconductor chip via a solder layer within the encapsulant. The conductor member comprises a joint surface being in contact with the solder layer and a side surface extending from a peripheral edge of the joint surface. The side surface comprises an unroughened area and a roughened area that is greater in surface roughness than the unroughened area. Further, the unroughened area is located adjacent to the peripheral edge of the joint surface.

With the aforementioned semiconductor device, the roughened area and the unroughened area are provided on the side surface of the conductor member. Since the roughened area has large surface roughness, its solder wettability is low. As such, when the semiconductor chip and the conductor member are soldered together, excessive solder primarily spreads on the unroughened area while on the other hand it is suppressed from spreading onto the roughened area. According to this, the surface of the conductor member is suppressed from being broadly covered by the solder, and durability of the semiconductor device can thereby be improved. In addition, since the roughened area not covered by the solder has the large surface roughness, it can firmly adhere to the encapsulant. With an adhering degree between the conductor member and the encapsulant being improved, the durability of the semiconductor device is further improved.

