CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims benefit to U.S. Non-Provisional application Ser. No. 16/884,869, entitled “SYSTEM AND METHOD FOR WIRELESS RECEIVER COMMUNICATION BASED ON VARIABLE LEADING BIT ORTHOGONAL CODE SETS”, filed on May 27, 2020, the contents of which are incorporated by reference herein in their entirety.

FIELD OF THE INVENTION

The present invention generally relates to the field of wireless communication system and, in particular, to systems and methods for wireless receiver communication based on variable leading orthogonal code sets.

BACKGROUND

Various wireless communication systems are configured to receive multiple analog signals that have been previously encoded and modulated. These multiple analog signals may then be combined using a code having a higher frequency than the modulation frequency of the analog signals. This combination of analog signals yields an output signal that is spread across a wide bandwidth. The use of high code rates to spread the data signals enables the sharing of receiver hardware resources by combining multiple input signals to a single signal before being sampled by analog-to-digital (ADC) converter, while also providing a greater resistance to interference as well as promoting increased reliability (e.g., lower error vector magnitude (EVM) values).

However, it will be appreciated that the encoding of multiple analog signals at a higher code rate presents certain challenges to wireless receiver systems. One such challenge is that such receiver systems need to employ hardware, software, and firmware elements that are capable of operating at higher speeds to properly process the high code rate signals.

These challenges may be exacerbated by certain proposed enhancements to existing wireless communication systems as well as next-generation wireless communication designs. Such enhancements and designs include the deployment of high speed encoder, high sampling rate ADCs to sample high code rate signals, etc. Such enhancements and designs potentially strain the receiver hardware and software processing resources that are currently implemented.

SUMMARY

Embodiments of the present technology have been developed based on developers' appreciation of at least one technical problem associated with the prior art solutions.

Hence, it can be said that in at least some embodiments of the present technology, the developers of the present technology have devised wireless receiver and wireline communication system. By virtue of devised wireless receiver and wireline communication system, a hardware/software processing speeds is reduced, lower-bandwidth resources may be implemented, power consumption is decreased, and synchronization can be performed in a simplified manner.

An object of the present disclosure is to provide a method of processing wireless received signals, comprising: receiving a plurality of analog signals; encoding the plurality of received analog signals into a single encoded analog composite signal in accordance with a variable leading element orthogonal coding scheme; converting the single encoded analog composite signal into a single encoded digital composite signal containing constituent digital signals; and decoding the single encoded digital composite signal containing the constituent digital signals in accordance with the variable leading element orthogonal coding scheme, to output a plurality of digital signals containing desired information content of the received plurality of analog signals.

In accordance with other aspects of the present disclosure, the method, wherein a variable leading element in the variable leading element orthogonal coding scheme is one or more of: a real number; and a complex number.

Another object of the present disclosure is to provide a transmitter comprising: a signal encoder configured to encode a plurality of received digital signals into a single encoded digital composite signal, in accordance with a variable leading element orthogonal coding scheme; and a digital-to-analog converter (DAC) configured to convert the single encoded digital composite signal into a single encoded analog composite signal containing constituent analog signals.

In accordance with other aspects of the present disclosure, the transmitter, wherein a leading element in the variable leading element orthogonal coding scheme is programmable.

In accordance with other aspects of the present disclosure, the transmitter, wherein except for the leading element remaining variable leading element orthogonal coding scheme is orthogonal in nature.

In accordance with other aspects of the present disclosure, the transmitter, wherein a variable leading element in the variable leading element orthogonal coding scheme is one or more of: a real number; and a complex number.

In accordance with other aspects of the present disclosure, the transmitter, wherein the transmitter is at least one of: a wireline transmitter; and a wireless transmitter.

Another object of the present disclosure is to provide a receiver comprising: an analog-to-digital converter (ADC) configured to convert a single encoded analog composite signal into a single encoded digital composite signal containing constituent digital signals; and a signal decoder configured to decode the single encoded digital composite signal in accordance with a variable leading element orthogonal coding scheme, to output a plurality of digital signals.

In accordance with other aspects of the present disclosure, the receiver, wherein a leading element in the variable leading element orthogonal coding scheme is programmable.

In accordance with other aspects of the present disclosure, the receiver, wherein except for the leading element remaining variable leading element orthogonal coding scheme is orthogonal in nature.

In accordance with other aspects of the present disclosure, the receiver, wherein a variable leading element in the variable leading element orthogonal coding scheme is one or more of: a real number; a complex number.

In accordance with other aspects of the present disclosure, the receiver, wherein the receiver is at least one of: a wireline receiver; and a wireless receiver.

In accordance with other aspects of the present disclosure, the receiver, further comprising a synchronization module, implemented on a processor, configured to provide the variable leading element orthogonal coding scheme to the signal encoder, wherein the synchronization module comprises: a variable leading bit orthogonal code set generator configured to generate the variable leading element orthogonal coding scheme; a control module configured to program the leading element in the variable leading element orthogonal coding scheme; a delay module configured to adjust a delay of clock signal generated by a clock generator and provide the delay to the ADC, in accordance with input from the control module; a masking module configured to mask the orthogonal codes in the variable leading element orthogonal coding scheme; and a leading bit analyzer configured to detect and process the leading element in the variable leading element orthogonal coding scheme.

In accordance with other aspects of the present disclosure, the receiver, wherein the control module is further configured to provide a code type and a code rate to the variable leading bit orthogonal code set generator for generating the variable leading element orthogonal coding scheme.

In accordance with other aspects of the present disclosure, the receiver, further comprising performing offline synchronization, wherein performing the offline synchronization further comprises: masking, by the masking module, the orthogonal codes in the variable leading element orthogonal coding scheme; adjusting, by the delay module, a delay of a clock signal for converting the single encoded analog composite signal into the single encoded digital composite signal; adjusting, by the leading bit analyzer, a delay of the single encoded digital composite signal; detecting, by the leading bit analyzer, the leading element in the single encoded digital composite signal; measuring, by the leading bit analyzer a power associated with the detected element; and if the power associated with the detected element is more than a pre-defined threshold, unmasking, by the masking module, the orthogonal codes in the variable leading element orthogonal coding scheme; if the power associated with the detected element is less than the predefined threshold, again adjusting, by the delay module, the delay of the clock signal and again adjusting, by the leading element analyzer, the delay of the single encoded digital composite signal.

In accordance with other aspects of the present disclosure, the receiver, wherein the delay adjustment of the clock signal is by a fractional factor.

In accordance with other aspects of the present disclosure, the receiver, wherein the delay adjustment of the single encoded digital composite signal is by at least one of: an integer factor; and a fractional factor.

In accordance with other aspects of the present disclosure, the receiver, further comprising performing an online synchronization, wherein performing the online synchronization further comprises: programming, by the control module, the leading element value greater than the current value in the variable leading element orthogonal coding scheme; adjusting, by the delay module, a delay of a clock signal for converting the single encoded analog composite signal into a single encoded digital composite signal; adjusting, by the leading bit analyzer, a delay of the single encoded digital composite signal; detecting, by the leading bit analyzer, the leading element in the single encoded digital composite signal; measuring, by the leading bit analyzer a power associated with the detected element; and if the power associated with the detected element is more than a pre-defined threshold, unmasking, by the masking module, the orthogonal codes in the variable leading element orthogonal coding scheme; if the power associated with the detected element is less than the predefined threshold, again adjusting, by the delay module, the delay of the clock signal and again adjusting, by the leading element analyzer, the delay of the single encoded digital composite signal.

In accordance with other aspects of the present disclosure, the receiver, wherein the delay adjustment of the clock signal is by a fractional factor.

In accordance with other aspects of the present disclosure, the receiver, wherein the delay adjustment of the single encoded digital composite signal is by at least one of: an integer factor; and a fractional factor.

