BACKGROUND

In data networks, input/output (I/O) systems such as switches, routers, and network interface cards receive packets at input interfaces, process the received packets, and then forward the packets to one or more output interfaces. It is important that such I/O systems operate as quickly as possible in order to keep pace with a high rate of incoming packets. One challenge associated with I/O systems relates to providing the flexibility to adapt to changes in desired feature sets, networking protocols, operating systems, applications, and hardware configurations.

SUMMARY

Methods and system for processing data in a programmable processing pipeline are disclosed. In an embodiment, a method for processing packets in a programmable packet processing pipeline is disclosed. The method involves processing data corresponding to a packet through a match-action pipeline of a programmable packet processing pipeline, and diverting the processing of data corresponding to the packet from the match-action pipeline to a processor core for out-of-pipeline processing.

In an embodiment, the method further involves returning a result of the out-of-pipeline processing back to the match-action pipeline for further processing. In an embodiment, returning a result of the out-of-pipeline processing back to the match-action pipeline involves queuing the result for use by a next stage of the match-action pipeline.

In an embodiment, diverting the processing of data corresponding to the packet from the match-action pipeline to a processor core involves reading a field in a packet header vector that is processed in the match-action pipeline and diverting the processing of data corresponding to the packet in response to reading the field in the packet header vector. In an embodiment, diverting the processing of data corresponding to the packet from the match-action pipeline to a processor core involves queuing at least a portion of the packet header vector for use by the processor core.

In an embodiment, diverting the processing of data corresponding to the packet from the match-action pipeline to a processor core comprises providing a packet header vector to the processor core via direct memory access (DMA).

In an embodiment, the method further involves parsing header information corresponding to the packet to generate a packet header vector and providing the packet header vector to the match-action pipeline.

In an embodiment, processing data through a match-action pipeline involves processing a packet header vector that is generated from header information of the packet.

In an embodiment, the programmable packet processing pipeline is programmable according to the P4 language specification as provided by the P4 Language Consortium.

In an embodiment, the method further involves programming the programmable packet processing pipeline according to the P4 language specification as provided by the P4 Language Consortium.

In an embodiment, the method further involves diverting the processing of data corresponding to multiple packets from a flow of packets to maintain packet ordering of the flow of packets. In an embodiment, the multiple packets from the flow of packets are diverted to the same processor core for out-of-pipeline processing. In an embodiment, a flow of packets are packets that have common header values. In an embodiment, a flow of packets consists of packets that have the same source IP address, source port number, destination IP address, destination port number, and protocol.

A system for processing packets is also disclosed. The system includes a programmable packet processing pipeline that includes a match-action pipeline, multiple processor cores, a pipeline-processor interface that connects the programmable packet processing pipeline to the multiple processor cores, and diversion logic configured to divert the processing of data corresponding to a packet from the match-action pipeline to at least one processor core of the multiple processor cores via the pipeline-processor interface for out-of-pipeline processing.

In an embodiment, the pipeline-processor interface is configured to return a result of the out-of-pipeline processing back to the match-action pipeline for further processing.

In an embodiment, the pipeline-processor interface includes memory configured to queue data corresponding to the packet as the processing transitions between the programmable packet processing pipeline and the processor cores.

In an embodiment, the diversion logic is configured to read a value of a packet header vector and to divert the processing from the match-action pipeline to at least one processor core of the multiple processor cores in response to the read value.

In an embodiment, the diversion logic comprises programmable decision logic and select logic, wherein the programmable decision logic is configured to read a value of a packet header vector and to control the select logic to select between available options of a match-action unit of the programmable packet processing pipeline and at least one processor core of the multiple processor cores.

In an embodiment, the programmable packet processing pipeline includes a programmable parser and a programmable deparser, and the match-action pipeline includes a series of programmable match-action units located in a process flow between the programmable parser and the programmable deparser.

In an embodiment, the match-action pipeline includes a series of match-action units and wherein the match-action units of the match-action pipeline include a match unit having key construction logic and a match table.

In an embodiment, the programmable packet processing pipeline is programmable according to the P4 language specification as provided by the P4 Language Consortium.

A method for processing data in a programmable data processing pipeline is also discloses. The method involves processing data corresponding to a data set through a match-action pipeline of a programmable processing pipeline and diverting the processing of data corresponding to the data set from the match-action pipeline to a processor core for out-of-pipeline processing.

In an embodiment, the method further includes returning a result of the out-of-pipeline processing back to the match-action pipeline for further processing.

Other aspects in accordance with the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrated by way of example of the principles of the invention.

