CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2020-0015694, filed on Feb. 10, 2020, in the Korean Intellectual Property Office, and entitled: “Semiconductor Package and Method of Manufacturing Semiconductor Package,” is incorporated by reference herein in its entirety.

BACKGROUND

1. Field

Embodiments relate to a semiconductor package and a method of manufacturing the semiconductor package.

2. Description of the Related Art

A memory module may include fan out semiconductor packages mounted therein. Channel lengths between solder balls of the semiconductor package and input/output terminals of a module substrate may affect high speed characteristics.

SUMMARY

Embodiments are directed to a semiconductor package, including a semiconductor chip having chip pads on a first surface and having first and second side surfaces extending in a direction parallel with a first direction perpendicular to the first surface and opposite to each other and third and fourth side surfaces extending in a direction parallel with a second direction perpendicular to the first direction and opposite to each other, a molding member covering the third and fourth side surfaces and exposing the first and second side surfaces of the semiconductor chip, a redistribution wiring layer on a lower surface of the molding member to cover the first surface of the semiconductor chip and including a plurality of redistribution wirings electrically connected to the chip pads, and outer connection members arranged in a connection region defined on an outer surface of the redistribution wiring layer and electrically connected to the redistribution wirings. When viewed in plan view, the first and second side surfaces of the semiconductor chip may be positioned outside the connection region, and the third and fourth side surfaces of the semiconductor chip may be positioned within the connection region.

Embodiments are also directed to a semiconductor package, including a semiconductor chip having chip pads on a first surface, having first and second side surfaces extending in a direction parallel with a first direction perpendicular to the first surface and opposite to each other, and having third and fourth side surfaces extending in a direction parallel with a second direction perpendicular to the first direction and opposite to each other, a molding member covering the third and fourth side surfaces and exposing the first and second side surfaces of the semiconductor chip, a redistribution wiring layer on a lower surface of the molding member to cover the first surface of the semiconductor chip and including a plurality of redistribution wirings electrically connected to the chip pads, and outer connection members arranged in a connection region defined on an outer surface of the redistribution wiring layer, and electrically connected to the redistribution wirings. A length in the second direction of the connection region may be less than a distance between the first and second side surfaces of the semiconductor chip, and a length in the first direction of the connection region may be greater than a distance between the third and fourth side surfaces.

Embodiments are also directed to a semiconductor package, including a redistribution wiring layer including a plurality of redistribution wirings, a semiconductor chip arranged on an upper surface of the redistribution wiring layer, having chip pads on a first surface, having first and second side surfaces extending in a direction parallel with a first direction perpendicular to the first surface and opposite to each other, and having third and fourth side surfaces extending in a direction parallel with a second direction perpendicular to the first direction and opposite to each other, a molding member on the upper surface of the redistribution wiring layer, covering the third and fourth side surfaces and exposing the first and second side surfaces of the semiconductor chip, and outer connection members arranged in a connection region defined on a lower surface of the redistribution wiring layer, and electrically connected to the redistribution wirings.

Embodiments are also directed to a semiconductor package as a fan out package, including a molding member provided on a redistribution wiring layer to expose a first side surface and a second side surface of a semiconductor chip extending in a first direction and opposite to each other and to cover a third side surface and a fourth side surface of the semiconductor chip extending in a second direction and opposite to each other. A connection region of the redistribution wiring layer on which solder balls are disposed may have a fan-in region corresponding to a region between the first side surface and the second side surface of the semiconductor chip and a fan-out region corresponding to a region between the third side surface and the fourth side surface of the semiconductor chip.

