TECHNICAL FIELD

The present disclosure relates to the field of semiconductor memory technologies, and more particularly, to a read operation circuit, a semiconductor memory, and a read operation method.

BACKGROUND

A semiconductor memory includes a static random-access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a read-only memory (ROM), and a flash memory, etc.

In a DRAM protocol of the Joint Electron Device Engineering Council (JEDEC), there are requirements for speed and power saving of the DRAM. How to ensure the DRAM to be more power-saving while ensuring the integrity of a signal and the reliability of data transmission and storage is a problem to be solved urgently in the industry.

SUMMARY

Embodiments of the present disclosure provide a read operation circuit, a semiconductor memory, and a read operation method to solve or alleviate one or more technical problems in the existing technologies.

In a first aspect, the embodiments of the present disclosure provide a read operation circuit used in a semiconductor memory, wherein the semiconductor memory comprises a Data Queue (DQ) port, a data bus inversion (DBI) port, and a memory bank. The read operation circuit comprising:

a DBI encoder connected to the memory bank, wherein the DBI encoder is configured to read data from the memory bank, and determine whether to invert the read data according to number of bits of high data in the read data to output global bus data for transmission through a global bus and DBI data for transmission through a DBI signal line, wherein the DBI port is configured to receive the DBI data;

a parallel-to-serial conversion circuit connected between the DQ port and the DBI encoder through the global bus and configured to perform parallel-to-serial conversion on the global bus data to generate output data of the DQ port;

a data buffer module connected to the memory bank through the global bus; and

a precharge module connected to a precharge signal line and configured to set an initial state of the global bus to Low.

In one embodiment, the DBI encoder is configured to output inverted data of the read data as the global bus data and set the DBI data to High if the number of bits of the high data in the read data is greater than a preset value, and output original read data as the global bus data and set the DBI data to Low if the number of bits of the high data in the read data is less than or equal to the preset value.

In one embodiment, the M-bit DBI data is corresponding to the M groups of read data one to one, and the M-bit DBI data is corresponding to the M groups of global bus data one to one. The parallel-to-serial conversion circuit is also connected between the DBI encoder and the DQ port to output the M-bit DBI data processed by parallel-to-serial conversion to the DQ port, wherein the M is an integer greater than 1.

In one embodiment, each group of read data has N bits, the N being an integer greater than 1. The DBI encoder is configured to output inverted data of a group of read data inputted as a corresponding group of global bus data and set 1-bit DBI data corresponding to the group of read data inputted to High if the number of bits of high data in the group of read data inputted is greater than N/2, and output a group of read data inputted as a corresponding group of global bus data and set 1-bit DBI data corresponding to the group of read data inputted to Low if the number of bits of the high data in the group of read data inputted is less than or equal to N/2.

In one embodiment, the DBI encoder comprises:

a DBI encoder unit, an input terminal of the DBI encoder unit is connected to the memory bank, an output terminal of the DBI encoder unit being connected to the DBI signal line, and the DBI encoder unit is configured to set the DBI data to High if the number of bits of the high data in the read data is greater than a preset value, and set the DBI data to Low if the number of bits of the high data in the read data is less than or equal to the preset value; and

a data selector, an input terminal of the data selector being connected to the DBI encoder unit to receive the read data through the DBI encoder unit, the input terminal of the data selector being configured to receive the DBI data through the DBI signal line, and an output terminal of the data selector being connected to the parallel-to-serial conversion circuit through the global bus. The data selector is configured to output inverted data of the read data as the global bus data if the DBI data is High, and output original read data as the global bus data if the DBI data is Low.

In one embodiment, the data selector comprises a plurality of data selection units, each of the plurality of data selection units comprising:

a first inverter, an input terminal of the first inverter being configured to receive the DBI data through the DBI signal line;

a second inverter, an input terminal of the second inverter being connected to the DBI encoder unit to receive the read data from the DBI encoder unit;

a first transmission gate, an input terminal of the first transmission gate being connected to an output terminal of the second inverter, an output terminal of the first transmission gate being connected to the global bus to output the global bus data, a negative control terminal of the first transmission gate being connected to an output terminal of the first inverter, and a positive control terminal of the first transmission gate being configured to receive the DBI data through the DBI signal line; and

a second transmission gate, an input terminal of the second transmission gate being connected to the DBI encoder unit to receive the read data from the DBI encoder unit, an output terminal of the second transmission gate being connected to the global bus to output the global bus data, a negative control terminal of the second transmission gate being configured to receive the DBI data through the DBI signal line, and a positive control terminal of the second transmission gate is connected to the output terminal of the first inverter.

In one embodiment, the data selector comprises a plurality of data selection units, and each of the plurality of data selection units comprising:

a third inverter, an input terminal of the third inverter being configured to receive the DBI data through the DBI signal line;

a fourth inverter, an input terminal of the fourth inverter being connected to the DBI encoder unit to receive the read data from the DBI encoder unit;

a first logic AND gate, a first input terminal of the first logic AND gate being connected to the DBI encoder unit to receive the read data from the DBI encoder unit, and a second input terminal of the first logic AND gate being connected to an output terminal of the third inverter;

a second logic AND gate, a first input terminal of the second logic AND gate being configured to receive the DBI data through the DBI signal line, and a second input terminal of the second logic AND gate being connected to an output terminal of the fourth inverter; and

a logic OR gate, two input terminals of the logic OR gate being respectively connected to an output terminal of the first logic AND gate and an output terminal of the second logic AND gate, and an output terminal of the logic OR gate being connected to the global bus to output the global bus data.

In one embodiment, the data buffer module comprises a plurality of PMOS transistors, wherein a gate of each of the plurality of PMOS transistors being connected to the memory bank, and a drain of each of the plurality of PMOS transistors being connected to the global bus. The precharge module comprises a plurality of NMOS transistors and a plurality of hold circuits, a gate of each of the plurality of NMOS transistors being connected to the precharge signal line, and a drain each of the plurality of NMOS transistors being connected to the global bus. An input terminal and an output terminal of each of the plurality of hold circuits being connected to the global bus.

In a second aspect, the embodiments of the present disclosure provide a semiconductor memory, comprising a DQ port, a DBI port, a memory bank, and any one of the read operation circuits mentioned above.

In a third aspect, the embodiments of the present disclosure provide a read operation method used in a semiconductor memory. The read operation method comprises:

setting an initial state of a global bus to Low;

reading read data from the memory bank;

determining whether to invert the read data according to the number of bits of high data in the read data to output global bus data for transmission through the global bus and DBI data for transmission through a DBI signal line; and

performing parallel-to-serial conversion on the global bus data to generate output data of the DQ port.

In one embodiment, the determining whether to invert the read data according to the number of bits of high data in the read data to output global bus data for transmission through the global bus and DBI data for transmission through a DBI signal line comprises:

outputting inverted data of the read data as the global bus data and setting the DBI data to High if the number of bits of the high data in the read data is greater than a preset value; and

outputting original read data as the global bus data and setting the DBI data to Low if the number of bits of the high data in the read data is less than or equal to the preset value.

In one embodiment, the determining whether to invert the read data according to the number of bits of high data in the read data to output global bus data for transmission through the global bus and DBI data for transmission through a DBI signal line comprises:

dividing the read data into M groups, wherein each group of read data has N bits, and both the M and the N being integers greater than 1;

outputting inverted data of a group of read data inputted as a corresponding group of global bus data and setting 1-bit DBI data corresponding to the group of read data inputted to High if the number of bits of high data in the group of read data inputted is greater than N/2; and

outputting a group of read data inputted as a corresponding group of global bus data and setting 1-bit DBI data corresponding to the group of read data inputted to Low if the number of bits of the high data in the group of read data inputted is less than or equal to N/2.

According to the technical solutions of the embodiments of the present disclosure, more data “0” can be transmitted through a global bus having a precharge low architecture, such that the number of inversions of the internal global bus can be reduced. In this way, electric current is reduced significantly, and power consumption is decreased.

The above summary is for the purpose of illustration only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present disclosure will be readily apparent by reference to the drawings and the following detailed description.

