FIELD OF THE DISCLOSURE

The technology of the disclosure relates to computer processors (“processors”), and more particularly to fetching instructions into an instruction pipeline of a processor to be executed.

BACKGROUND

Microprocessors, also known as “processors,” perform computational tasks for a wide variety of applications. A microprocessor includes a central processing unit (CPU) that includes one or more processor cores, also known as “CPU cores.” The CPU executes computer program instructions (“instructions”), also known as “software instructions,” to perform operations based on data and generate a result, which is a produced value. The CPU can include instruction pipelining where a series of instructions are fetched into one or more instruction pipelines each having a number of processing stages to perform tasks towards their execution. This allows multiple instructions to be processed at the same time and in different stages to increase instruction processing throughput, as opposed to each instruction being processed sequentially and fully executed before processing a next instruction. In this regard, the CPU can include an instruction fetch circuit that fetches instructions into an instruction pipeline. The instructions are then subsequently decoded in a decoding stage and further processed in other pipeline stages for execution. The instructions are eventually executed in an execution stage of an instruction pipeline. Power is consumed in the CPU as a result of the instruction fetch circuit fetching instructions processed in an instruction pipeline.

Repetitive patterns can be received in an instruction pipeline of a CPU as a result of fetching and processing instructions to be executed. For example, the fetched instructions to be executed may be in a programming construct, such as a software loop. Software loops may be re-executed a number of times before the loop is exited, thus causing instructions in the loop to be repetitively fetched and processed. Not only may the same instructions be repeated, fetched, and processed in an instruction pipeline, but the data consumed for processing these instructions may also result in the repetition of data in the instruction pipeline. Each repetitive fetching of instructions into an instruction pipeline of a CPU to be processed and executed consumes power in the instruction fetch circuit of the CPU.

SUMMARY

Exemplary aspects disclosed herein include detecting a repetitive pattern in an instruction pipeline of a processor to reduce repeated fetching. The processor includes an instruction processing circuit configured to fetch instructions into an instruction pipeline as part of an instruction data stream to be processed and executed as a part of instruction pipelining. Data specified by source operands in the fetched instructions is also fetched into the instruction pipeline and used to execute the instructions in the data stream in the instruction pipeline. The instructions and/or its source data fetched into the instruction pipeline may repeat (i.e., are repetitively fetched into the instruction pipeline). In exemplary aspects, it is desired to detect these repeated patterns of data (e.g., instructions and/or source data) occurring in the instruction pipeline so that previously recorded patterns of such data can be inserted into the instruction pipeline without having to re-fetch this data.

In exemplary aspects, the processor includes a pattern record circuit. The pattern record circuit is configured to receive information in a data stream (e.g., instructions and/or source data) in the instruction pipeline. In one example, the pattern record circuit includes a first in, first out (FIFO) table circuit. The pattern record circuit contains an input record column and plurality of additional adjacent record columns. The number of record columns defines the width of the pattern record circuit. As new data occur in the data stream, a pattern record circuit is configured to sequentially record next incoming data from the data stream into a next input entry of an input record column of the pattern record circuit and then store (e.g., shift) previously recorded data into adjacent entries of adjacent record columns of the pattern record circuit. Thus, if data repeats in the data stream in a frequency equal to or less than the width of the pattern record circuit, the incoming data recorded in the input record column in the pattern record circuit will match a previous occurrence of the data previously shifted into an additional record column. The distance between the input record column and the additional record column, that includes matching data, is the distance in the data stream between a reoccurrence (i.e., repeat) of data in the data stream. The additional record columns also include respective frequency indicators that are updated by the pattern record circuit for detected matches between data in one or more additional record columns and new input data recorded in the input record column.

In this manner, the frequency indicators indicating an occurrence of a repetitive data pattern can be consulted by a pattern fetch circuit in the processor to determine potential data patterns occurring in a data stream in the instruction pipeline. Detecting a repetitive pattern in the instruction pipeline of the processor can be used to reduce repeated re-fetching. For example, the pattern fetch circuit can be configured to receive an indication of new data fetched into the instruction pipeline. The pattern fetch circuit can be configured to consult the frequency indicators previously recorded for the new fetched data to determine the likelihood that the new fetched data is the start of a previously recorded repetitive data pattern. If the new fetched data is determined to be the start of a previously recorded repetitive data pattern, the pattern fetch circuit is configured to insert the data from the previously recorded repetitive data pattern into the instruction pipeline such that the fetching of new data can be temporarily disabled.

In this regard, in one exemplary aspect, a processor is disclosed, comprising an instruction processing circuit configured to fetch data into an instruction pipeline as a data stream, and a pattern record circuit comprising an input record column comprising an input data entry, and one or more additional input record columns each comprising a data entry and a frequency indicator. The pattern record circuit is configured to receive a next incoming data from the data stream and store the next incoming data in the input data entry in the input record column. In response to receiving the next incoming data from the data stream, the pattern record circuit is also configured to store the next incoming data from the input data entry of the input record column to an additional record column among the one or more additional record columns adjacent to the input record column, and store data in each data entry of the one or more additional record columns into the data entry of a respective adjacent additional record column among the one or more additional record columns. In response to the data stored in the data entry of an additional record column among the one or more additional record columns matching the next incoming data the pattern record circuit is also configured to update a frequency indicator of the additional record column to a repetition frequency state indicating a repetition frequency of the next incoming data in the data stream.

In another exemplary aspect, a method of detecting a repetitive pattern in an instruction pipeline of a processor is disclosed. The method comprises receiving a next incoming datum from a data stream fetched into the instruction pipeline, and storing the next incoming data in an input data entry in an input record column in a pattern record circuit. The method also comprises storing the next incoming data from the input data entry of the input record column to an additional record column among one or more additional record columns in the pattern record circuit adjacent to the input record column, storing data in each data entry of the one or more additional record columns into a data entry of a respective adjacent additional record column among the one or more additional record columns, and determining if the data stored in the data entry of an additional record column among the one or more additional record columns matches the incoming data. In response to the data stored in the data entry of an additional record column among the one or more additional record columns matching the incoming data, the method also comprises updating a frequency indicator of the additional record column to a repetition frequency state indicating a repetition frequency of the incoming data in the data stream.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

