BACKGROUND

RF amplifiers are widely used in cellular communications systems and other applications. RF amplifiers are typically formed as semiconductor integrated circuit chips. Most RF amplifiers are implemented in silicon or using wide bandgap semiconductor materials, such as silicon carbide (“SiC”) and Group III nitride materials. As used herein, the term “Group III nitride” refers to those semiconducting compounds formed between nitrogen and the elements in Group III of the periodic table, usually aluminum (Al), gallium (Ga), and/or indium (In). The term also refers to ternary and quaternary compounds, such as AlGaN and AlInGaN. These compounds have empirical formulas in which one mole of nitrogen is combined with a total of one mole of the Group III elements.

Silicon-based RF amplifiers are typically implemented using laterally diffused metal oxide semiconductor (“LDMOS”) transistors. Silicon LDMOS RF amplifiers can exhibit high levels of linearity and may be relatively inexpensive to fabricate. Group III nitride-based RF amplifiers are typically implemented using High Electron Mobility Transistors (“HEMT”) and are primarily used in applications requiring high power and/or high frequency operation where LDMOS transistor amplifiers may have inherent performance limitations.

RF amplifiers may include one or more amplification stages, with each stage typically implemented as a transistor amplifier. In order to increase the output power and current handling capabilities, RF amplifiers are typically implemented in a “unit cell” configuration in which a large number of individual “unit cell” transistors are arranged electrically in parallel. The RF amplifier may be implemented as a single integrated circuit chip or “die,” or may include a plurality of dies. When multiple RF amplifier die are used, they may be connected in series and/or in parallel.

RF amplifiers often include matching circuits, such as impedance matching circuits, that are designed to improve the impedance match between an RF amplifier die and transmission lines connected thereto for RF signals at the fundamental operating frequency and harmonic termination circuits that are designed to at least partly terminate harmonics that may be generated during device operation such as second and third order harmonics. The RF amplifier die(s) as well as the impedance matching and harmonic termination circuits may be enclosed in a package. Electrical leads may extend from the package that are used to electrically connect the RF amplifier to external circuit elements such as input and output RF transmission lines and bias voltage sources.

As noted above, Group III nitride-based RF amplifiers are often used in high power and/or high frequency applications. Typically, high levels of heat are generated within the Group III nitride-based RF amplifier die(s) during operation. If the RF die(s) become too hot, the performance (e.g., output power, efficiency, linearity, gain, etc.) of the RF amplifier may deteriorate and/or the RF amplifier die(s) may be damaged. As such, Group III nitride-based RF amplifiers are typically mounted in packages that may be optimized for heat removal.FIGS.1A and1Billustrate a conventional packaged Group III nitride-based RF amplifier. In particular,FIG.1Ais a schematic side view of a conventional packaged Group III nitride-based RF amplifier100, andFIG.1Bis a schematic cross-sectional view of the RF transistor amplifier die that is included in the packaged Group III nitride-based RF transistor amplifier100, where the cross-section is taken along line1B-1B ofFIG.1A. It will be appreciated thatFIGS.1A-1B(and various of the other figures) are highly simplified diagrams and that actual RF amplifiers may include many more unit cells and various circuitry and elements that are not shown in the simplified figures herein.

As shown inFIG.1A, the Group III nitride-based RF amplifier100includes an RF amplifier die110that is mounted within an open cavity package170. The package170includes a gate lead172, a drain lead174, a metal flange176and a ceramic sidewall and lid178. The RF transistor amplifier die110is mounted on the upper surface of the metal flange176in a cavity formed by the metal flange176and the ceramic sidewall and lid178. The RF amplifier die110has a top side112and a bottom side114. The RF amplifier die110includes a bottom side (also referred to as a “back” side) metallization structure120, a semiconductor layer structure130and a top side metallization structure140that are sequentially stacked. The back side metallization structure120comprises a source terminal126. The RF amplifier100may be a HEMT-based RF amplifier, in which case the semiconductor layer structure130may include at least a channel layer and a barrier layer, which are typically formed on a semiconductor or insulating growth substrate (such as a SiC or sapphire substrate). The top side metallization structure140includes, among other things, a gate terminal142and a drain terminal144.

Input matching circuits190and/or output matching circuits192may also be mounted within the housing170. The matching circuits190,192may be impedance matching circuits that match the impedance of the fundamental component of RF signals input to or output from the RF transistor amplifier100to the impedance at the input or output of the RF transistor amplifier die110, respectively, and/or harmonic termination circuits that are configured to short to ground harmonics of the fundamental RF signal that may be present at the input or output of the RF transistor amplifier die110, such as second order or third order harmonics. As schematically shown inFIG.1A, the input and output matching circuits190,192may be mounted on the metal flange176. The gate lead172may be connected to the input matching circuit190by one or more first bond wires182, and the input matching circuit190may be connected to the gate terminal142of RF amplifier die110by one or more second bond wires183. Similarly, the drain lead174may be connected to the output matching circuit192by one or more fourth bond wires185, and the output matching circuit192may be connected to the drain terminal144of RF amplifier die110by one or more third bond wires184. The source terminal126of RF transistor amplifier die110may be mounted directly on the metal flange176. The metal flange176may provide the electrical connection to the source terminal126and may also serve as a heat dissipation structure. The first through fourth bond wires182-185may form part of the input and/or output matching circuits. The housing178may comprise a ceramic housing, and the gate lead172and the drain lead174may extend through the housing178. The housing178may comprise multiple pieces, such as a frame that forms the lower portion of the sidewalls and supports the gate and drain leads172,174, and a lid that is placed on top of the frame. The interior of the device may comprise an air-filled cavity.

FIG.1Bis a schematic cross-sectional view of the RF amplifier die110that is taken through a portion of the top side metallization structure140. Dielectric layers that isolate the various conductive elements of the top-side metallization structure140from each other are not shown inFIG.1Bto simplify the drawing.

As shown inFIG.1B, the RF amplifier die110comprises a Group III nitride-based HEMT RF amplifier that has a plurality of unit cell transistors116that each include a gate finger152, a drain finger154and a source finger156. The gate fingers152are electrically connected to a common gate bus146, and the drain fingers154are electrically connected to a common drain bus148. The gate bus146is electrically connected to the gate terminal142(e.g., through a conductive via that extends upwardly from the gate bus146) which is implemented as a gate bond pad (seeFIG.1A), and the drain bus148is electrically connected to the drain terminal144(e.g., through a conductive via that extends upwardly from the drain bus148) which is implemented as a drain bond pad (seeFIG.1A). The source fingers156are electrically connected to the source terminal126via a plurality of conductive source vias166that extend through the semiconductor layer structure130. The conductive source vias166may comprise metal-plated vias that extend completely through the semiconductor layer structure130.

Referring again toFIG.1A, the metal flange176may act as a heat sink that dissipates heat that is generated in the RF amplifier die110. The heat is primarily generated in the upper portion of the RF amplifier die110where relatively high current densities are generated in, for example, the channel regions of the unit cell transistors116. This heat may be transferred though both the source vias166and the semiconductor layer structure130to the metal flange176.

FIG.1Cis a schematic cross-sectional view of a conventional HEMT device1000. For example,FIG.1Ccan be a cross section ofFIG.1Bas outlined by the unit cell transistors116. A semiconductor structure1090, such as a semiconductor structure for a Group III nitride semiconductor HEMT, may be formed on a substrate1022such as a SiC substrate or a sapphire substrate. The substrate1022may be a semi-insulating SiC substrate that may be, for example, the4H polytype of silicon carbide. Other silicon carbide candidate polytypes may include the3C,6H, and15R polytypes. The substrate may be a High Purity Semi-Insulating (HPSI) substrate, available from Cree, Inc. The term “semi-insulating” is used descriptively herein, rather than in an absolute sense.

In some embodiments of the present invention, the SiC bulk crystal of the substrate1022may have a resistivity equal to or higher than about 1×105ohm-cm at room temperature. Exemplary SiC substrates that may be used in some embodiments of the present invention are manufactured by, for example, Cree, Inc., of Durham, N.C., the assignee of the present invention. Methods for producing such substrates are described, for example, in U.S. Pat. No. Re. 34,861, U.S. Pat. Nos. 4,946,547, 5,200,022, and 6,218,680, the disclosures of which are incorporated by reference herein in their entireties. Although SiC can be used as a substrate material, embodiments of the present application may utilize any suitable substrate. The substrate1022can be an SiC wafer, and the HEMT device1000can be formed, at least in part, via wafer-level processing, and the wafer can then be diced to provide a plurality of individual HEMTs1000.

As shown inFIG.1C, a channel layer1024is formed on an upper surface1022B of the substrate1022, and a barrier layer1026is formed on an upper surface of the channel layer1024. The channel layer1024and the barrier layer1026can each be formed by epitaxial growth in some embodiments. Techniques for epitaxial grown of Group III nitrides have been described in, for example, U.S. Pat. Nos. 5,210,051, 5,393,993, and 5,523,589, the disclosures of which are also incorporated by reference herein in their entireties. The channel layer1024and the barrier layer1026can include Group III nitride-based materials.

While semiconductor structure1090is shown with channel layer1024and barrier layer1026for purposes of illustration, semiconductor structure1090can include additional layers/structures/elements such as a buffer and/or nucleation layer(s) between channel layer1024and substrate1022, and/or a cap layer on barrier layer1026. HEMT structures including substrates, channel layers, barrier layers, and other layers are discussed by way of example in U.S. Pat. Nos. 5,192,987, 5,296,395, 6,316,793, 6,548,333, 7,544,963, 7,548,112, 7,592,211, 7,615,774, and 7,709,269, the disclosures of which are hereby incorporated herein in their entirety by reference. For example, an AlN buffer layer may be formed on the upper surface1022B of the substrate1022to provide an appropriate crystal structure transition between the SiC substrate1022and the reminder of the HEMT device1000. Additionally, strain balancing transition layer(s) can also and/or alternatively be provided as described, for example, in commonly assigned U.S. Pat. No. 7,030,428, the disclosure of which is incorporated herein by reference as if set forth fully herein. The optional buffer/nucleation/transition layers may be deposited by MOCVD, MBE, and/or HYPE.

A source contact1015and a drain contact1005can be formed on an upper surface1026A of the barrier layer1026and can be laterally spaced apart from each other. A gate contact1010can be formed on the upper surface1026A of the barrier layer1026between the source contact1015and the drain contact1005. The material of the gate contact1010can be chosen based on the composition of the barrier layer1026, and may, in some embodiments, be a Schottky contact.

The source contact1015can be coupled to a reference signal such as, for example, a ground voltage. The coupling to the reference signal can be provided by a via1025that extends from a lower surface1022A of the substrate1022, through the substrate1022to an upper surface1026A of the barrier layer. The via1025can expose a bottom surface of the ohmic portion1015A of the source contact1015. A backmetal layer1035can be formed on the lower surface1022A of the substrate1022and on the side walls of the via1025. The backmetal layer1035can directly contact the ohmic portion1015A of the source contact1015. The backmetal layer1035and a signal coupled thereto can be electrically connected to the source contact1015.

The HEMT device1000can include a first insulating layer1050and a second insulating layer1055. The first insulating layer1050can directly contact the upper surface of the semiconductor structure1090(e.g., contact the upper surface1026A of the barrier layer1026). The second insulating layer1055can be formed on the first insulating layer1050. It will also be appreciated that more than two insulating layers can be included in some embodiments. The first insulating layer1050and the second insulating layer1055can serve as passivation layers for the HEMT device1000.

The source contact1015, the drain contact1005, and the gate contact1010can be formed in the first insulating layer1050. In some embodiments, at least a portion of the gate contact1010can be on the first insulating layer. In some embodiments, the gate contact1010can be formed as a T-shaped gate and/or a gamma gate, the formation of which is discussed by way of example in U.S. Pat. Nos. 8,049,252, 7,045,404, and 8,120,064, the disclosures of which are hereby incorporated herein in their entirety by reference. The second insulating layer1055can be formed on the first insulating layer1050and on portions of the drain contact1005, gate contact1010, and source contact1015.

In some embodiments, field plates1060can be formed on the second insulating layer1055. At least a portion of a field plate1060can be on the gate contact1010. At least a portion of the field plate1060can be on a portion of the second insulating layer1055that is between the gate contact1010and the drain contact1005. Field plates and techniques for forming field plates are discussed, by way of example, in U.S. Pat. No. 8,120,064, the disclosure of which is hereby incorporated herein in its entirety by reference.

Metal contacts1065can be disposed in the second insulating layer1055. The metal contacts1065can provide interconnection between the drain contact1005, gate contact1010, and source contact1015and other parts of the HEMT device1000. Respective ones of the metal contacts1065can directly contact respective ones of the drain contact1005and/or source contact1015.

FIG.1Dis a schematic side view of a conventional packaged Group III nitride-based RF transistor amplifier100′ that is similar to the RF transistor amplifier discussed above with reference toFIG.1A. RF transistor amplifier100′ differs from RF transistor amplifier100in that it includes a different package170′. The package170′ includes a metal submount176(which acts as a metal heat sink and can be implemented as a metal slug), as well as gate and drain leads172′,174′. In some embodiments, a metal lead frame may be formed that is then processed to provide the metal submount176and/or the gate and drain leads172′,174′. RF transistor amplifier100′ also includes a plastic overmold170′ that at least partially surrounds the RF transistor amplifier die110, the leads172′,174′ and the metal submount176. The plastic overmold170′ replaces the ceramic sidewalls and lid178included in RF transistor amplifier100.

Depending on the embodiment, the packaged transistor amplifier100′ can include, for example, a monolithic microwave integrated circuit (MMIC) as the RF transistor amplifier die110in which case the RF transistor amplifier die110incorporates multiple discrete devices. When the RF transistor amplifier die110is a MMIC implementation, the input matching circuits190and/or the output matching circuits192may be omitted (since they may instead be implemented within the RF transistor amplifier die110) and the bond wires182and/or185may extend directly from the gate and drain leads172′,174′ to the gate and drain terminals142,144. In some embodiments, the packaged RF transistor amplifier100can include multiple RF transistor amplifier die that are connected in series to form a multiple stage RF transistor amplifier and/or may include multiple transistor die that are disposed in multiple paths (e.g., in parallel) to form an RF transistor amplifier with multiple RF transistor amplifier die and multiple paths, such as in a Doherty amplifier configuration

In other cases, Group III nitride-based RF amplifiers may be implemented as MMIC devices in which one or more RF amplifier die(s) are implemented together with their associated impedance matching and harmonic termination circuits in a single, integrated circuit die. Examples of such Group III nitride-based RF amplifiers are disclosed, for example, in U.S. Pat. No. 9,947,616, the entire content of which is incorporated herein by reference.

FIG.1Eis a cross-sectional view illustrating an example of a thermally enhanced integrated circuit device package, more specifically a T3PAC package100″. The T3PAC package100″ ofFIG.1Ecan be a ceramic-based package that includes a base1201and an upper housing with a lid member178and sidewall members1204. The lid member178and sidewalls1204similarly define an open cavity surrounding the amplifier die110on the conductive base or flange1201, which likewise provides both an attachment surface1201and thermal conductivity (e.g., a heat sink) for dissipating or otherwise transmitting heat outside of the package100″.

The flange1201can be an electrically conductive material, for example, a copper layer/laminate or an alloy or metal-matrix composite thereof. In some embodiments, the flange1201may include a copper-molybdenum (CuMo) layer, CPC (Cu/MoCu/Cu), or other copper alloys, such copper-tungsten CuW, and/or other laminate/multi-layer structures. In the example ofFIG.1E, the flange1201is illustrated as a copper-molybdenum (RCM60)-based structure to which the sidewalls1204and/or lid member178are attached, e.g., by a conductive glue1208.

The flange1201also provides the source lead102sfor the package100″. The gate lead102gand drain lead102dare provided by respective conductive wiring structure1214which is attached to the flange1201and supported by the sidewall members1204.

An example of a conventional Doherty amplifier200A is schematically illustrated in the circuit diagram ofFIG.2A. In this example, the Doherty amplifier200A comprises a main transistor210A, a peaking transistor220A, and first and second phase shifters240A,245A.

The Doherty amplifier200A is configured to receive an input signal, split equally into two signals, one of which is directed towards a main transistor210A and the other of which is directed towards a peaking transistor220A. The signal directed toward the peaking transistor220A passes through a first phase shifter240A before reaching the peaking transistor220A, such that the signals received at the main transistor210A and peaking transistor220A are out-of-phase. The outputs of the main transistor210A and peaking transistor220A are combined in-phase by passing the output of the main transistor210A through a second phase shifter245A. In this regard, the phase shifters240A,245A may be quarter-wave transmission lines of characteristic impedance respectively configured to introduce and remove a 90 degree phase shift between the signals.

As discussed above, the main transistor210A and the peaking transistor220A may be differently biased. In particular, the peaking transistor210A may be much more heavily biased than the main transistor220A. In this regard, the main transistor210A may be a class AB or class B amplifier, whereas the peaking transistor220A may be a class C amplifier. Accordingly, there may be an offset in the gate bias voltages between the transistors210A,220A. Notwithstanding, the main transistor210A and peaking transistor220A are designed to have matching operational threshold voltages. Among other things, the matching threshold voltages may enable the same bias offset between the transistors210A,220A to be used in a wide variety of products without having to adjust the Doherty amplifier on a product-by-product basis.

Integrated Doherty amplifiers are Doherty amplifiers that can have all or part of the amplifiers, matching networks, and/or combining networks integrated on one semiconductor chip. Doherty amplifiers can be one integrated die on a monolithic microwave integrated circuit (MMIC) or at a package level on discrete components. With higher levels of integration, integrated Doherty amplifiers can provide the customers with ease of use and faster cycle time. For example, having the main and peaking transistors210A,220A on the same die with matching turn-on characteristics may enable better and more consistent performance.

FIG.2Billustrates an example layout of circuitry as used in a traditional outphasing amplifier200B. The outphasing amplifier200B comprises a signal separator210B that provides input signals to a pair of transistor amplifiers220B,225B that produce amplified output signals that are out-of-phase from each other.

The output of each transistor220B,225B is coupled in parallel to a branch240B,245B towards ground and to a phase shifter230B,235B. The phase shifters230B,235B enable the outputs of the transistors220B,225B to be combined in-phase before proceeding to an output port250B. The branches240B,245B provide load regulation so that the transistors220B,225B operate with higher efficiency. One of the branches may comprise a capacitor and the other may comprise an inductor, for example.

FIG.2Cillustrates an example layout of circuitry as used in a traditional feed forward amplifier200C. The feed forward amplifier comprises two amplification stages, each comprising one transistor amplifier210C,220C. In the first stage, an input signal is split towards a first transistor210C and a phase shifter230C. The first transistor210C provides primary amplification of the signal, whereas the first stage phase shifter230C shifts the original signal by approximately 180 degrees. The amplified signal is sampled and combined in combiner250C with the output of the phase shifter230C to cancel out the original signal and obtain an error signal representing the distortion introduced by the primary amplification step. This error signal is passed to the second transistor220C for amplification. The amplified signal from the first transistor210C is sent to another phase shifter240C for combination with combiner260C out-of-phase with the amplified error from the second transistor to cancel the error from the amplified signal and produce an amplified, error-corrected signal at the output port. BothFIG.2Cfeed forward amplifier200C andFIG.2Boutphasing amplifier200B can be implemented at the die level and at the package level.

BRIEF SUMMARY

Embodiments of the present disclosure generally relate to added isolation between transistors in a multiple path amplifier circuit.

In particular, one or more embodiments include a multiple path amplifier circuit including a substrate, a first transistor on the substrate in a first path, and a second transistor on the substrate in a second path. The multiple path amplifier circuit also includes at least one electrical connection associated with the first and the second transistors and positioned to at least partially extend between the first path and the second path.

In some embodiments, the first path can include an input phase shift, wherein the input phase shift is deposited between the first transistor and the second transistor. In some embodiments, the first path can include an output phase shift, wherein the output phase shift is deposited between the first transistor and the second transistor. In some embodiments, the first path can include an output combiner, wherein the output combiner is deposited between the first transistor and the second transistor. For example, the first path can include an output phase shift, wherein the output phase shift is deposited between the first transistor and the second transistor. In some embodiments, the first path can be deposited on a surface of the substrate. In some embodiments, the first path is deposited in the substrate. In some embodiments, the multiple path amplifier circuit can be a Doherty amplifier. In some embodiments, the distance between the first transistor and the second transistor is in a range of 500 to 3000 μm. In some embodiments, the multiple path amplifier circuit further includes a third transistor and a second path, wherein the second path is associated with the third transistor and the first transistor and/or the second transistor, and a second distance between the third transistor and the first transistor and/or the second transistor provides for the second path.

One or more other embodiments include an RF amplifier circuit, the RF amplifier circuit can include a substrate, a first transistor, and a second transistor. The RF amplifier circuit can also include a first path associated with both the carrier transistor and the peaking transistor, wherein a distance between the carrier transistor and the peaking transistor provides for the first path.

In some embodiments, the first path includes an input phase shift, wherein the input phase shift is deposited between the first transistor and the second transistor. In some embodiments, the first path includes an output phase shift, wherein the output phase shift is deposited between the first transistor and the second transistor. In some embodiments, the RF amplifier circuit can operate at a frequency of over 1 GHz. In some embodiments, the first transistor can be a gallium nitride (GaN) based high electron mobility transistor (HEMT). In some embodiments, the first transistor can include a silicon-based laterally-diffused metal-oxide semiconductor (LDMOS). In some embodiments, the first transistor includes a complementary metal-oxide-semiconductor (CMOS). In some embodiments, the first transistor can be a gallium arsenide (GaAs) transistor. In some embodiments, the first path can include splitting, combining, matching, and/or harmonic circuitry.

One or more other embodiments include a Doherty amplifier circuit, the Doherty amplifier circuit including a substrate, a main transistor on the substrate in a first path, and a peaking transistor on the substrate in a second path. The Doherty amplifier can also include at least one electrical connection associated with the first and the second transistors and positioned to at least partially extend between the first path and the second path.

Of course, those skilled in the art will appreciate that the present embodiments are not limited to the above contexts or examples, and will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings.

