CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0104157, filed on Aug. 19, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device, and more particularly, to a non-planar field effect transistor (FET).

DISCUSSION OF THE RELATED ART

To reduce the size of semiconductor devices of a given structure, the size of each transistor therein may be reduced. However, the reduction in the size of a transistor may causes a short channel effect. In order to mitigate this short channel effect, a FinFET, in which a gate contacts three sides of a channel, has been developed. In addition, a gate-all-around FET, in which a gate surrounds four sides of a channel, and a nanosheet FET have been developed.

SUMMARY

A semiconductor device includes a channel. A first source or drain structure is disposed on a first side surface of the channel. A second source or drain structure is disposed on a second side surface of the channel that is spaced apart from the first side surface of the channel in a first horizontal direction. A gate structure including a gate electrode layer at least partially surrounds an upper surface of the channel, a third side surface of the channel, a fourth side surface of the channel110spaced apart from the third side surface of the channel in a second horizontal direction, and a gate insulating layer disposed between the gate electrode layer and the channel. An inner spacer layer is disposed on a side surface of the gate structure. An outer spacer layer is disposed on an outer surface of the inner spacer layer. The first source or drain structure includes a first source or drain layer disposed on the channel and a second source or drain layer disposed on the first source or drain layer, and on a plane of the semiconductor device that passes through the channel and is parallel to the first horizontal direction and the second horizontal direction, at least one of a first boundary line of the first source or drain layer in contact with the second source or drain layer and a second boundary line of the first source or drain layer in contact with the channel is convex, extending toward the channel.

A semiconductor device includes a channel. A first source or drain structure including a first source or drain layer is disposed on a first side surface of the channel and a second source or drain layer is disposed on the first source or drain layer. A second source or drain structure including a third source or drain layer is disposed on a second side surface of the channel spaced apart from the first side surface of the channel in a first horizontal direction and a fourth source or drain layer is disposed on the third source or drain layer. A gate structure including a gate electrode layer at least partially surrounding an upper surface of the channel, a third side surface of the channel, a fourth side surface of the channel spaced from the third side surface of the channel in a second horizontal direction, and a gate insulating layer disposed between the gate electrode layer and the channel. A first inner spacer layer is disposed on a first side surface of the gate structure. A second inner spacer layer is disposed on a second side surface of the gate structure spaced apart from the first side surface of the gate structure in the first horizontal direction. A first outer spacer layer is disposed on an outer surface of the first inner spacer layer. A second outer spacer layer is disposed on an outer surface of the second inner spacer layer. On a plane of the semiconductor device that passes through the channel and is parallel to the first horizontal direction and the second horizontal direction, a first distance between the second source or drain layer and the fourth source or drain layer along a first horizontal line that passes through the third side surface of the channel110and is parallel to the first horizontal direction is greater than a second distance between the second source or drain layer and the fourth source or drain layer along a second horizontal line that passes between the third side surface of the channel110and the fourth side surface of the channel110and is parallel to the first horizontal direction.

A semiconductor device includes a plurality of channels spaced apart from each other in a vertical direction. A first source or drain structure is in contact with a first side surface of each of the plurality of channels. A second source or drain structure in contact with a second side surface of each of the plurality of channels is spaced apart from the first side surface of each of the plurality of channels in a first horizontal direction. A gate structure includes a gate electrode layer at least partially surrounding an upper surface of each of the plurality of channels, a lower surface of each of the plurality of channels, a third side surface of each of the plurality of channels, and a fourth side surface of each of the plurality of channels spaced apart from the third side surface of each of the plurality of channels in a second horizontal direction, and a gate electrode layer disposed between the gate electrode layer and each of the plurality of channels. An inner spacer layer is disposed on a side surface of the gate structure perpendicular to the first horizontal direction. An outer spacer layer is disposed on the outer surface of the inner spacer layer. The first source or drain structure includes a first source or drain layer in contact with the gate insulating layer and a second source or drain layer in contact with the first source or drain layer, and on a plane of the semiconductor device that passes through a portion of the gate electrode layer between the plurality of channels and is perpendicular to the vertical direction, at least one of a first boundary line of the first source or drain layer in contact with the second source or drain layer and a second boundary line of the first source or drain layer in contact with the gate insulating layer is convex, extending toward the gate insulating layer.

