FIELD OF THE INVENTION

The present invention relates to the field of digital demodulation of signals.

PRIOR ART

In a manner known per se, a digital demodulator takes as input digital signal samples, these samples being for example obtained by digitization of an analog radio signal.

A digital demodulator can be implemented in hardware or software form.

For example, an Application-Specific Integrated Circuit (ASIC) or else a programmable logic circuit (such as an FPGA) can be used as a hardware digital demodulator. These circuits both share the property of being dedicated to demodulation. With such circuits, it is possible to achieve very high demodulation throughputs. However, these logic circuits have many drawbacks: they of course require a dedicated hardware configuration that requires considerable development and qualification time, at start-up and in the event of updates. Their architecture is designed to process a continuous stream of samples at the input and has a maximum throughput characteristic. It is currently not possible to run several hardware digital demodulators in parallel for the purpose of increasing throughput except for special cases of “burst” modulation or pilot-symbol assisted modulation, no more than it is possible to share one to process several carriers of lower throughput.

A software digital demodulator is a computer program dedicated to digital demodulation and is able to be executed by a generic processor, i.e. a processor not specifically designed for this task. A known example of a software digital demodulator is GNU Radio.

The heavy restrictions on implementation, “modularity” and porting that are encountered with a hardware digital demodulator are removed when a software digital demodulator is used.

However, the maximum demodulation throughput that can be achieved by a generic processor executing such a program is limited and proportional to its clock frequency, given the fact that the samples are processed sequentially. Thus, there is still a maximum throughput that cannot be exceeded by a single software demodulator.

It could be envisioned to use several software digital demodulators in parallel to raise this throughput limit. However, the use of several digital demodulators, even software ones, causes a new problem to appear.

To understand this problem, it should be recalled that a digital demodulator must perform a synchronization of carrier and/or symbol rate on the basis of digital signal samples that it receives as input before being able to produce demodulated symbols from samples. Such a synchronization is in certain implementations implemented by means of a phase-locked loop (PLL). Whatever the chosen implementation, it is only once this synchronization is effective that the digital demodulator can start to convert digital signal samples received as input into demodulated symbols. Furthermore, the digital demodulator must consume digital signal samples to successfully complete this synchronization. Thus, symbols corresponding to digital signal samples consumed by the digital demodulator before the synchronization is effective are of necessity lost, or at least productive of symbols with a sub-optimal error probability.

In a conventional architecture with a single digital demodulator, the loss of a few initial symbols from a signal caused by the time taken by the demodulator to synchronize itself on the input samples that it receives is not very damaging. This is because, once the synchronization is effective, this loss is not repeated.

In an architecture comprising several independent digital demodulators working in parallel, things would be very different. If a digital input signal to be demodulated was divided into blocks of samples and these blocks were processed in parallel by the different digital demodulators, it would then be necessary for each digital demodulator to implement a new synchronization on a new block it receives. Consequently, the number of signal symbols lost would increase with the number of digital demodulators used in parallel, and the losses would be repeated with each block demodulated.

The invention in question proposes to solve this problem while preserving the parallel computing power.

SUMMARY OF THE INVENTION

One aim of the invention is to digitally demodulate a signal with an increased throughput, without loss of symbols, or more generally to optimize the computing power required at a given throughput.

Provision is thus made, according to a first aspect of the invention, for a method for processing a sequence of digital signal samples coming from at least one modulated analog signal, the sample sequence comprising a first sample sub-sequence and a second sample sub-sequence separate from the first sample sub-sequence, the method comprising steps of:forming a first sample block comprising the first sample sub-sequence, and a second sample block comprising header samples followed by the second sample sub-sequence,demodulating the first block of digital signal samples by a first digital demodulator, so as to produce a first symbol block,demodulating the second block of digital signal samples by a second digital demodulator independent of the first digital demodulator so as to produce a second symbol block, the second digital demodulator implementing a carrier and/or symbol rate synchronization, and taking as input the second sample block starting with the header samples, the header samples comprising a suitable number of synchronization samples for the synchronization to be effective before the second digital demodulator starts to demodulate the second sample sub-sequence,reconstructing an output symbol sequence by concatenating a symbol sequence coming from the first symbol block with a symbol sequence coming from the second symbol block.

Moreover, the first sample sub-sequence comprises tail samples of the first sample block, and the header samples of the second sample block correspond to the tail samples. In other words, there is an overlap between the end of the first sample block processed by the first digital demodulator and the start of the second sample block processed by the second digital demodulator. The fact of using an overlap between the last samples of the first sample block and the header samples of the second sample block has the advantage of being particularly simple to implement.

As the two digital demodulators are independent, they can be used in parallel to demodulate the blocks that are supplied to them. Using them in conjunction therefore makes it possible to obtain a higher demodulator throughput in a less expensive way than by increasing the power of a single demodulator.

In addition, thanks to the presence of the header samples, the carrier and/or symbol rate synchronization is effective before the second digital demodulator starts to demodulate the second sub-sequence of samples contained in the second sample block. This makes it possible to avoid certain symbols being missing from the output signal when it is finally reconstructed.

The method according to the first aspect of the invention can be completed using the following features taken alone or in combination when this is technically possible.

The header samples can further comprise guard samples (E7-E9) located, in the second sample block, between the synchronization samples (E6) and the second sample sub-sequence (E10-E14), the guard samples being of a number greater than a maximum number of samples per symbol in the sequence of digital signal samples. To understand the effect provided by these features, it should be recalled that the sampling of the modulated analog signal is asynchronous, i.e. its rate is governed by a clock independent of the transmitter, and that the number of samples per analog signal sample can vary over time (in particular by Doppler effect, when the analog signal has been transmitted by a transmitter then acquired by a receiver in relative motion with respect to the transmitter). Consequently, the number of header samples consumed by synchronization can also vary. The guard samples then have the effect of guaranteeing that no symbol contained in the second sample set will be consumed by the loop before being locked even in these situations.

The second digital demodulator having received the second sample block can be configured to not produce symbols as long as the header samples have not been consumed by the second demodulator.

The method can comprise the generation, by the first digital demodulator, of a first set of metadata relating to the first symbol block, and the generation, by the second digital demodulator, of a second set of metadata relating to the second symbol block, wherein the reconstruction is implemented using the first set of metadata and the second set of metadata.

The method can further comprise steps of detecting a redundancy between at least one symbol of the first symbol block and at least one symbol of the second symbol block, using the first set of metadata and the second set of metadata, and retaining in the output sequence only one out of two symbols detected as being redundant. These steps make it possible to avoid the appearance of redundant symbols in the output signal, whatever the size chosen for the sample blocks processed by the first digital demodulator and the second digital demodulator respectively.

In a first variant, the method comprises the estimation of a signal-to-noise ratio associated with the first symbol block, and a signal-to-noise ratio associated with the second symbol block, the symbol retained in the output signal out of two redundant symbols being the one that comes from the symbol block associated with the highest signal-to-noise ratio out of the two estimated signal-to-noise ratios. This has the effect of minimizing the risk of errors being present in the included symbol.

In a second variant, the symbol retained in the output sequence out of two symbols detected as being redundant is the redundant symbol of the first symbol block, it being understood that the symbol sequence coming from the second symbol block follows the symbol sequence coming from the first symbol block in the output symbol sequence.

Provision can furthermore be made for the following features:the first set of metadata comprises a first position determined by the first demodulator and making it possible to locate the final symbol in the first sample block,the second set of metadata comprises a second position determined by the first demodulator and making it possible to locate the initial symbol in the second sample block,the number of redundant blocks between the first symbol block and the second symbol block is computed as a function of a separation between the first position and the second position.

The method can further comprise the generation, by the first digital demodulator, of a first frame comprising the first symbol block and the first set of metadata, and the generation, by the second digital demodulator, of a second frame comprising the second symbol block and the second set of metadata. The fact of including these positions in the frames that comprise the demodulated symbols has the advantage of requiring only a single linking of data from the digital demodulator to a reconstructing module implementing the reconstruction of the output signal.

The first set of metadata can form a suffix that follows the first symbol block in the first frame, and the second set of metadata can form a prefix followed by the second symbol block in the second frame. The fact of placing the metadata in the prefix and in the suffix of the frames also comprising demodulated symbols has the advantage of reducing the latency phenomena induced by implementing demodulations in parallel. The reconstructing module in charge of reconstructing the output signal is in particular capable of detecting any redundancy between the first symbol block and the second symbol block without having received the entirety of the second frame.

The method can further comprise steps of:estimating, by the first digital demodulator, a first synchronized carrier phase associated with the first symbol block,estimating, by the second digital demodulator, a second synchronized carrier phase associated with the second symbol block,if the two phases of synchronized carrier synchronization differ, adjusting one of the symbol blocks in relation to the other symbol blocks so as to eliminate this phase difference, before reconstructing the output signal.

These features have the effect of allowing the correct demodulation of samples coming from a signal previously modulated by a constellation having a phase ambiguity.

The first phase is for example included in the first set of metadata and the second phase is for example included in the second set of metadata.

The method can further comprise the generation of metadata relating to the second sample block formed, said metadata being transmitted to the second digital demodulator and comprising the total number of samples of the second sample block and/or the number of synchronization samples of the block and/or a center frequency of the sequence of digital signal samples. Owing to these metadata, the second digital demodulator is capable of determining autonomously if first samples coming from the set have been unduly consumed before the synchronization is effective, in other words if the header samples were in sufficient number to avoid symbol losses at the demodulator output. These metadata therefore offer the possibility for the second digital demodulator to itself escalate an alert or take any other appropriate measure, where applicable.

The method can comprise steps of:determining a frequency separation between a center frequency of the sequence of digital signal samples and an expected center frequency,correcting the sequence of digital signal samples according to the frequency separation to remove this separation in the sample sequence, before implementing the step of forming sample blocks, or else correcting one of the sample blocks by one of the digital demodulators.

As the correction is made before the forming of the sample blocks, this correction is done a single time per sample block to be processed. This solution is more economic of resources than that consisting in having the determination of the frequency separation or even the ensuing correction done by each of the digital demodulators used.

Provision is also made, according to a second aspect of the invention, for a computer program product comprising program code instructions for executing the steps of the method according to the first aspect of the invention, when this program is executed by at least one processor.

Provision is also made, according to a third aspect of the invention, for a device for processing a sequence of digital signal samples coming from at least one modulated analog signal, the sample sequence comprising a first sample sub-sequence and a second sample sub-sequence separate from the first sample sub-sequence, the processing device comprising:a distributor configured to form a first sample block comprising the first sample sub-sequence, and to form a second sample block comprising header samples followed by the second sample sub-sequence,a first digital demodulator configured to demodulate the first block of digital signal samples so as to produce a first symbol block,a second digital demodulator independent of the first digital demodulator and configured to demodulate the second block of digital signal samples so as to produce a second symbol block, the second digital demodulator being configured to implement a carrier and/or symbol rate synchronization, and to take as input the second sample block starting with the header samples, the header samples comprising synchronization samples in a suitable number for the synchronization to be effective before the second digital demodulator starts to demodulate the second sample sub-sequence,a reconstructing module configured to reconstruct an output symbol sequence by concatenating a symbol sequence coming from the first symbol block with a symbol sequence coming from the second block.

The first sample sub-sequence comprises tail samples of the first sample block, and the header samples of the second sample block correspond to the tail samples.

