BACKGROUND

Integrated isolated power products are packaged electronic devices having semiconductor dies and integrated transformers with electrical connections to externally accessible leads (e.g., pins or pads) for soldering to a printed circuit board (PCB). Isolated DC to DC converters can be built using integrated high voltage isolation transformers, there the transformer coils can be fabricated in a lamination structure for integration in a packaged electronic device. Many DC to DC converters have design specifications for electromagnetic interference (EMI), such as CISPR32 and CISPR25 EMI emission requirements for multimedia equipment (MME) with a rated rms AC or DC supply voltage not exceeding 600 V set by the Comite International Special des Perturbations Radioelectriques (CISPR). Switching of primary and/or secondary side transistors in a DC to DC converter can cause conducted and/or emitted EMI, for example, there the transformer of an isolated DC to DC converter can be a path of electromagnetic energy due to its inter-winding capacitance. EMI can be controlled using ferrite beads, additional capacitors, or other external (e.g., board level) components, but this increases circuit area, weight and cost. In addition, each design has different specifications with respect to electric fields, efficiency and electromagnetic interference (EMI) performance. Other EMI control approaches include spread spectrum modulation (SSM) for controlling the DC to DC converter switching, but this requires additional die space and often only provides incremental EMI improvement.

SUMMARY

In accordance with one aspect, a packaged electronic device includes conductive leads at least partially exposed to an exterior of a package structure, second conductive leads at least partially exposed to the exterior of the package structure, and a multilevel lamination structure in the package structure. The multilevel lamination structure includes first and second patterned conductive feature, and a conductive shield trace. The first patterned conductive feature has multiple turns in a first level of the multilevel lamination structure to form a first winding coupled to at least one of the first conductive leads in a first circuit. The second patterned conductive feature has multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit. The conductive shield trace has multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature. The conductive shield trace is coupled in the first circuit.

In one example, the multilevel lamination structure includes a second conductive shield trace having multiple turns in another level between the first patterned conductive feature and the second patterned conductive feature. The second conductive shield trace is coupled in the second circuit, and the second conductive shield trace is spaced apart from the first conductive shield trace. In one example, the first conductive shield trace is coupled to a ground reference node of the first circuit, and the second conductive shield trace is coupled to a second ground reference node of the second circuit. The shield or shields can be peripherally located with respect to the patterned conductive features in certain implementations. In one example, the first conductive shield trace includes a turn laterally spaced outward from an outermost lateral extent of the first patterned conductive feature in the first level, and the second conductive shield trace includes a turn laterally spaced outward from an outermost turn of the second patterned conductive feature in the different level. In certain implementations, the shield or shields can be interleaved with the patterned conductive features. In one example, the first conductive shield trace is interleaved with a turn of the first patterned conductive feature in the first level, and the second conductive shield trace is interleaved with a turn of the second patterned conductive feature in the different level.

In accordance with another aspect, a multilevel lamination structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding, as well as a second patterned conductive feature having multiple turns in a different level to form a second winding, and a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature. In one example, the multilevel lamination structure further includes a second conductive shield trace having multiple turns in another level between the first patterned conductive feature and the second patterned conductive feature. In one example, the first conductive shield trace includes a turn laterally spaced outward from an outermost lateral extent of the first patterned conductive feature in the first level, and the second conductive shield trace includes a turn laterally spaced outward from an outermost turn of the second patterned conductive feature in the different level. In one example, the first conductive shield trace is interleaved with a turn of the first patterned conductive feature in the first level, and the second conductive shield trace is interleaved with a turn of the second patterned conductive feature in the different level.

In accordance with another aspect, a method includes attaching a magnetic assembly with a multilevel lamination structure to a support structure, attaching a first semiconductor die to a first die attach pad, and attaching a second semiconductor die to a second die attach pad, as well as performing an electrical connection process and a molding process. The electrical connection process couples the first semiconductor die, a first winding of the multilevel lamination structure, a first conductive shield trace of the multilevel lamination structure, and at least one of a set of first conductive leads in a first circuit. In addition, the electrical connection process couples the second semiconductor die, a second winding of the multilevel lamination structure, a second conductive shield trace of the multilevel lamination structure, and at least one a set of second conductive leads in a second circuit isolated from the first circuit. The molding process encloses the magnetic assembly, the die attach pads, the semiconductor dies, portions of the first and second conductive leads in a package structure. In one example, the electrical connection process couples the first conductive shield trace to a ground reference node of the first circuit, and couples the second conductive shield trace to a second ground reference node of the second circuit.

