TECHNICAL FIELD

The present disclosure relates to the filed of data processing, and in particular to a system architecture of data processing.

BACKGROUND

A traditional server mainly uses CPU as its computing power provider. CPU, as a general-purpose processor, adopts a serial architecture and is good at logic computations. Since CPU can process and access different types of data, and logic determination requires the introduction of a large amount of branch, jump, and interrupt processing, the internal structure of CPU is often complex. Therefore, the increase in the computing power of CPU is mainly achieved by increasing the number of cores.

With the application of technologies such as cloud computing, big data, artificial intelligence (AI), and the Internet of Things, data has grown exponentially in the past few years. IDC statistics show that 90% of the world's data have been generated in recent years, which poses challenges to the processing capabilities of CPU. The physical technology and numbers of cores of the current CPU are close to the limit, but the growth of data will not stop. In this case, the processing capacity of the server must be improved. Therefore, in the AI era, the traditional server with only CPU as the computing power provider cannot meet demands.

Different from CPU, GPU/TPU/ASIC adopts a parallel computing mode and has more than a thousand cores in a single card. GPU/TPU/ASIC is good at processing intensive computing applications, such as graphics rendering, computing vision, and machine learning. Therefore, in order to solve the problem of insufficient CPU computing power, a common method is to insert a dedicated accelerator card into an extended PCIE slot of CPU. The accelerator card will deal with the large amount of data computing work so that the burden on the CPU can be reduced, thereby significantly improving the performance of the traditional server.

The above approach can improve the computing performance of the traditional server. However, being limited by the number of extended PCIE slots of CPU, when the amount of data processing increases sharply, the approach above may not support the insertion of a sufficient number of accelerator cards and cannot meet the computing power requirements. Moreover, since a plurality of accelerator cards are connected to a PCIE bus of the same CPU, the resources cannot be deployed flexibly.

SUMMARY

Aiming to overcome the defect in the prior art that accelerator cards cannot be used flexibly, the present disclosure provides a technical solution that can deploy computing resources flexibly.

According to a first aspect of the present disclosure, a system for data accelerated processing is provided, which includes: a data exchange unit100and an accelerated processing unit200. The data exchange unit100is configured to be communicatively connected to an external host. The accelerated processing unit200is configured to be communicatively connected to the data exchange unit100to process data from the data exchange unit100. The acceleration processing unit200can be scheduled to meet the needs of different processing capabilities.

According to a second aspect of the present disclosure, a board is provided, which includes the system as described above.

According to a third aspect of the present disclosure, an electronic device is provided, which includes the system or the board card as described above.

The technical solution of the present disclosure can ensure that there are sufficient computing resources to meet the requirements of computing power. Moreover, the technical solution only needs to occupy one PCIE slot of a traditional server, which may overcome the problem of limited PCIE slots of a traditional server.

