BACKGROUND

Technical Field

The present disclosure relates to a capacitance structure and a manufacturing method of the capacitance structure.

Description of Related Art

For a capacitor array, a contact short is easily found due to a localized stress, which is caused by asymmetry container profile. The localized stress damages a semiconductor structure where the capacitor array is formed within.

Therefore, a low stress capacitance structure including capacitor array is needed to improve such phenomenon.

SUMMARY

One aspect of the present disclosure is related to a capacitance structure. A capacitance structure includes a substrate, a plurality of rod capacitors and an oxide layer. The rod capacitors are located on a top surface of the substrate and form a capacitor array. The oxide layer covers a top and a side of the capacitor array and a portion of the substrate. The rod capacitors extend along a first direction perpendicular to a second direction where the top surface of the substrate extends and form a capacitor array. The oxide layer extends from the top of the capacitor array to the substrate along a third direction, and an angle is formed between the first and third directions.

In one or more embodiments, the capacitance structure further includes a first supporting layer and a second supporting layer. The first and second supporting layers connect sides of the rod capacitors and are covered by the oxide layer. Each of the first and second supporting layers protrudes from the side of the capacitor array in the second direction. The first supporting layer is located between the second supporting layer and the top surface of the substrate. The first supporting layer has an extra length with respect to the second supporting layer in the second direction such that a length of the first support layer is greater than a length of the second supporting layer and the oxide layer extends along the third direction.

In some embodiments, the second supporting layer is located at the top of the capacitor array.

In one or more embodiments, each rod capacitor includes an insulating tube filled with conductive material.

In some embodiments, the conductive material of the rod capacitors is a film covering and contacting the insulating tubes.

In some embodiments, the capacitance structure further includes a plurality of third supporting layers connecting sides of the insulating tubes. The film further covers the third supporting layers.

In one or more embodiments, a plurality of transistors is formed within the substrate. Each transistor has a contact exposed to the top surface of the substrate. Each rod capacitor is connected to the contact of a corresponding one of the transistors.

In one or more embodiments, the capacitance structure further includes a conductive layer located between the capacitor array and the oxide layer and electrically connected to the rod capacitors.

In some embodiment, the capacitance structure further includes an insulating material and a conductive line. The insulating material covers the oxide layer and the capacitor array. The conductive line extends to the conductive layer through the insulating material along the first direction.

One aspect of the present disclosure is related to a method of capacitance structure manufacturing. The method includes following operations. Etch the second supporting material to form a second supporting layer connecting the insulating tubes. Anisotropically etch second insulating material to form a second insulating layer protruding from the second supporting layer in the second direction. Etch the first supporting material along the second insulating layer to form a first supporting layer protruding from the second supporting layer in second direction and connects the insulating tubes. Remove the second insulating layer and the first insulating material to expose the substrate. Fill up conductive material in the insulating tubes to form rod capacitors forming a capacitor array and covering an oxide layer from a top of the capacitor array to the substrate. The oxide layer is formed along the first and second supporting layer such that the oxide layer extends along a third direction having an angle with respect to the first direction.

In one or more embodiments, a plurality of transistors is formed within the substrate and has a plurality of exposed contacts on a top surface of the substrate, and each exposed contact is connected to a corresponding one of the rod capacitors.

In one or more embodiments, the method further includes following operations. Form a conducting layer electrical connected to the capacitor array before the oxide layer is formed, and the oxide layer further covers the conducting layer.

In some embodiments, the method further includes following operations. Form insulating material covering the oxide layer.

In some embodiments, the method further includes following operations. Flatten a top side of the insulating material by a chemical mechanical planarization process.

In some embodiments, the method further includes following operations. Form a conductive line extending from a top side of the insulating material to the conductive layer through the oxide layer.

In summary, the capacitance structure of the present disclosure has a slope oxide layer covering the capacitor array, and it avoids undesired damages by reducing localized stress.

The above description is only used to explain the problems to be solved by the present disclosure, the technical means for solving the problems and the produced effects. The specific details of the present disclosure are described in detail in the following embodiments and related drawings.

