FIELD OF INVENTION

The present disclosure generally relates to methods and systems suitable for forming a layer on a surface of a substrate and to structures including the layer. More particularly, the disclosure relates to methods and systems for forming layers that include vanadium and/or indium and to structures formed using the methods and systems.

BACKGROUND OF THE DISCLOSURE

The scaling of semiconductor devices, such as, for example, complementary metal-oxide-semiconductor (CMOS) devices, has led to significant improvements in speed and density of integrated circuits. However, conventional device scaling techniques face significant challenges for future technology nodes.

For example, one challenge has been finding a suitable conducting material for use as a gate electrode in the CMOS devices. CMOS devices have conventionally used n-type doped polysilicon as the gate electrode material. However, doped polysilicon may not be an ideal gate electrode material for advanced node applications. Although doped polysilicon is conductive, there may still be a surface region which can be depleted of carriers under bias conditions. This region may appear as an extra gate insulator thickness, commonly referred to as gate depletion, and may contribute to the equivalent oxide thickness. While the gate depletion region may be thin, on the order of a few angstroms (Å), the gate depletion region may become significant as the gate oxide thicknesses are reduced in advanced node applications. As a further example, polysilicon does not exhibit an ideal effective work function (eWF) for both NMOS and PMOS devices. To overcome the non-ideal effective work function of doped polysilicon, a threshold voltage adjustment implantation may be utilized. However, as device geometries reduce in advanced node applications, the threshold voltage adjustment implantation processes may become increasingly complex and impractical.

To overcome problems associated with doped polysilicon gate electrodes, polysilicon gate material may be replaced with an alternative material, such as, for example, a metal, such as a titanium nitride layer. The titanium nitride layer may provide a more ideal effective work function for CMOS applications. However, in some cases, where higher work function values than those obtained with titanium nitride layers—e.g., in PMOS regions of a CMOS device—are desired, improved materials for gate electrodes are desired. Such materials may also be suitable for other applications, such as threshold voltage tuning or as a p-dipole shifter. In addition, improved layers for applications, such as diffusion barriers or liners (e.g., for back-end-of-line (BEOL) processing), etch stop layers, electrodes, and the like, are also desired.

Any discussion, including discussion of problems and solutions, set forth in this section has been included in this disclosure solely for the purpose of providing a context for the present disclosure. Such discussion should not be taken as an admission that any or all of the information was known at the time the invention was made or otherwise constitutes prior art.

SUMMARY OF THE DISCLOSURE

This summary may introduce a selection of concepts in a simplified form, which may be described in further detail below. This summary is not intended to necessarily identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

Various embodiments of the present disclosure relate to methods of forming structures including vanadium and/or indium layers, to structures and devices formed using such methods, and to apparatus for performing the methods and/or for forming the structures and/or devices. The vanadium and/or indium layers can be used in a variety of applications, including gate metal stack layers, logic (e.g., DRAM) electrode layer applications (e.g., as an electrode layer), as an etch stop layer (in front (FEOL), middle (MEOL), and/or back (BEOL) end of line processing), and/or as a diffusion barrier layer or liner (e.g., for FEOL, BEOL and/or MEOL applications). By way of particular examples, the vanadium and/or indium layers can be used as work function adjustment layers, voltage threshold adjustment layers, as (e.g., p) dipole or flatband shifter layers, as etch stop layers and/or as diffusion layers or liners in FEOL, MEOL and/or BEOL processing, and the like.

In accordance with exemplary embodiments of the disclosure, a method of forming a structure is disclosed. Exemplary methods of forming the structure include providing a substrate within a reaction chamber of a reactor and, using a cyclical deposition process, depositing a vanadium or indium layer onto a surface of the substrate. The cyclical deposition process can include (e.g., sequentially and separately) providing a vanadium and/or indium precursor to the reaction chamber and providing a reactant to the reaction chamber. The vanadium precursor can include, for example, one or more of a vanadium halide and a vanadium oxyhalide, a vanadium beta-diketonate compound, a vanadium cyclopentadienyl compound, a vanadium alkoxide compound, a vanadium dialkylamido compound, a vanadium amidinate compound, a vanadium “heteroleptic” or mixed ligand compound, or DAD type ligand compounds, where DAD can be represented by 1,4-diaza-1,3-butadiene (RN═CR′CR′═NR, R=alkyl, aryl, R′═H, alkyl), or the like. The vanadium halide can be selected from the group consisting of a vanadium fluoride, a vanadium chloride, a vanadium bromide, a vanadium iodide, and the like. The vanadium oxyhalide can be selected from the group consisting of a vanadium oxyfluoride, a vanadium oxychloride, a vanadium oxybromide, a vanadium oxyiodide, and the like. The indium precursor can include one or more of an indium alkyl compound, an indium cyclopentadienyl compound, an indium beta-diketonate compound, an indium acetate compound, or the like. The reactant can include one or more of an oxygen reactant, a nitrogen reactant, a sulfur reactant, and a carbon reactant. Exemplary oxygen reactants include water, ozone, dihydrogen dioxide (H2O2), oxygen (O2), nitrous oxide (N2O), dinitrogen pentoxide (N2O5), and the like. Exemplary nitrogen reactants can be selected from one or more of amines, such as NH3, alkyl amines of the formula NR3, where R is independently any of the following H, Me, Et, iPr, tBu, Ph, Bz, SiMe3, Cy, as well as other typical alkyl, aryl, or silyl substituents; hydrazines, such as N2H4, tBuNHNH2, Me2NNH2, as well as other hydrazine co-reactants of the formula R2NNR2, where each R is, for example, independently one of the following: H, Me, Et, iPr, tBu, Ph, Bz, SiMe3, Cy, as well as other typical alkyl, aryl, or silyl substituents; azides, such as HN3, (SiMe3)N3, RN3, where R is any common alkyl or aryl group; or other compounds, such as urea and alkyl variants thereof, carbodimides of the formula RN═C═NR, where R is any common alkyl or aryl group, guanidine and its common alkyl or aryl derivatives, hydrazones and their common alkyl or aryl derivatives; or other nitrogen and hydrogen-containing gases (e.g., a mixture of nitrogen gas and hydrogen gas), and the like.

Exemplary sulfur reactants include hydrogen sulfide (H2S), sulfur (e.g., S8), sulfur halides, thiols (e.g., alkyl and aryl thiols), compounds including disulfide bonds, compounds including sulfur-alkyl group bonds, and compounds represented by the formula R—S—S—R′, wherein R and R′ are independently selected from aliphatic (e.g., C1-C8) and aromatic groups. Exemplary carbon reactants include acetylene, ethylene, alkyl halide compounds, alkene halide compounds, metal alkyl compounds, and the like. In addition to providing one or more precursors and one or more reactants to the reaction chamber, a hydrogen-containing precursor or reactant can be flowed to the reaction chamber. In some cases, the addition of hydrogen-containing precursor and/or reactant is thought to enable formation of films with more desirable properties.

The cyclical deposition process can include one or more of an atomic layer deposition process and a cyclical chemical vapor deposition process. The cyclical deposition process can include a thermal process—i.e., a process that does not use plasma-activated species. In some cases, a reactant can be exposed to a plasma to form activated reactant species.

In accordance with yet further exemplary embodiments of the disclosure, a structure is formed using a method as described herein. The structure can include a substrate and a vanadium and/or indium layer formed overlying a surface of the substrate. Exemplary structures can further include one or more additional layers, such as an additional metal or conducting layer overlying the vanadium and/or indium layers and/or one or more insulating or dielectric layers underneath or overlying the vanadium and/or indium layers. The structure can be or form part of a CMOS structure, such as one or more of a PMOS and NMOS structure, or other device structure.

In accordance with yet additional embodiments of the disclosure, a device or portion thereof can be formed using a method and/or a structure as described herein. The device can include a substrate, an insulating or dielectric layer, a vanadium and/or indium layer overlying the insulating or dielectric layer, and optionally an additional metal layer overlying the vanadium and/or indium layer. The device can be or form part of, for example, a CMOS device.

In accordance with yet additional examples of the disclosure, a system to perform a method as described herein and/or to form a structure, device, or portion of either, is disclosed.

These and other embodiments will become readily apparent to those skilled in the art from the following detailed description of certain embodiments having reference to the attached figures. The invention is not being limited to any particular embodiments disclosed.

