CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2020-0020558, filed on Feb. 19, 2020, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field of Invention

Various embodiments of the present invention disclosure generally relate to an electronic device and, more particularly, to a memory device and a method of operating the memory device.

2. Description of Related Art

Generally, a storage device stores data under the control of a host device such as, for example, a computer or a smartphone. The storage device may include a memory device configured to store data, and a memory controller configured to control the memory device. Memory devices are chiefly classified into volatile and nonvolatile memory devices.

A volatile memory device stores data only when power is supplied thereto, and loses the stored data when power is turned off. Examples of a volatile memory device include a static random-access memory (SRAM), and a dynamic random-access memory (DRAM).

A nonvolatile memory device maintains stored data even when power to the device is turned off. Examples of a nonvolatile memory device include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), and a flash memory.

SUMMARY

Various embodiments of the present invention disclosure are directed to a memory device exhibiting improved program performance including forming improved threshold voltage distributions, and to a method of operating the memory device.

An embodiment of the present invention disclosure provides a memory device including: a plurality of memory cells; a peripheral circuit configured to verify a program operation on the plurality of memory cells using a first verify voltage; and a control logic configured to control the peripheral circuit to suspend the program operation in response to a suspend command and verify the program operation on the plurality of memory cells using a second verify voltage in response to a resume command input after the suspend command. The second verify voltage may have a lower voltage level than the first verify voltage.

An embodiment of the present invention disclosure provides a memory device including: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program operation on the plurality of memory cells; and a control logic configured to suspend the program operation in response to a suspend command and change, in response to a resume command input after the suspend command, at least one operating voltage to be used in the program operation depending on an amount by which threshold voltages of the plurality of memory cells are changed while the program operation is suspended.

An embodiment of the present invention disclosure provides a method of operating a memory device including a plurality of memory cells. The method may include: suspending a program operation on the plurality of memory cells in response to a suspend command; changing a voltage level of a verify voltage to be used in an operation of verifying the program operation based on shift information indicating a degree by which threshold voltages of the plurality of memory cells are shifted while the program operation is suspended; and resuming the program operation using a verify voltage having a changed voltage level in response to a resume command.

An embodiment of the present invention disclosure provides a memory device including: a storage unit, a first memory for storing information indicating a first set of one or more initial verify voltages, a second memory for storing information indicating second sets respectively corresponding to degrees of suspension, each set representing one or more verify voltages, and an operational circuit suitable for detecting one or more programmed states of failed verification in a program loop suspended due to a suspension command for an ongoing program operation on the storage unit, detecting the degree of suspension caused between time points of the suspension command and a resumption command for the suspended program operation, and resuming the suspended program operation with the verify voltages for the programmed states of failed verification within the second set corresponding to the detected degree and the verify voltages for remaining programmed states within the first set.

These and other features and advantages of the present invention may become better understood by the following detailed description and drawings.

