TECHNICAL FIELD

The disclosure, in various embodiments, relates generally to the field of microelectronic device design and fabrication. More specifically, the disclosure relates to material deposition systems, and to related methods, microelectronic devices, and electronic systems.

BACKGROUND

Microelectronic device designers often desire to increase the level of integration or density of features within a microelectronic device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features. In addition, microelectronic device designers often desire to design architectures that are not only compact, but offer performance advantages, as well as simplified designs, facilitating fabrication and reducing costs.

One example of a microelectronic device is a memory device. Memory devices are generally provided as internal integrated circuits in computers or other electronic devices. There are many types of memory including, but not limited to, random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), flash memory, and resistance variable memory. Non-limiting examples of resistance variable memory include resistive random access memory (RRAM), conductive bridge random access memory (conductive bridge RAM), magnetic random access memory (MRAM), phase change material (PCM) memory, phase change random access memory (PCRAM), spin-torque-transfer random access memory (STTRAM), oxygen vacancy-based memory, and programmable conductor memory.

A typical memory cell of a memory device includes a transistor and a memory storage structure. The transistor of the memory cell generally includes a channel region between a source region and a drain region, and a gate configured to electrically connect the source region and the drain region to one another through the channel region. The source region and the drain region of the transistor typically comprise a conductively doped semiconductive material, and the channel region typically comprises an undoped semiconductive material or an oppositely conductively doped (e.g., relative to the dopant conductivity type of the source/drain regions) semiconductive material. Current challenges related to transistor fabrication include achieving desirable dopant concentrations and dopant distributions in the source region, the drain region, and the channel region thereof, and reducing fabrication costs.

Two common processes forming the different regions (e.g., the source region, the drain region, and the channel region) of a transistor include physical vapor deposition (PVD), and chemical vapor deposition (CVD). Of the two, PVD has the advantage of relatively lower processing temperatures, relatively low cost source materials, and relatively high deposition rates. In a conventional PVD process, a glow discharge plasma is generated in an inert gas atmosphere by applying a radiofrequency (RF) or direct current (DC) potential across a two electrode assembly. Ions of the plasma travel to and collide with a conductively-doped semiconductive target structure to sputter (e.g., eject) neutral atoms of the conductively-doped semiconductive target structure. The sputtered atoms travel across the plasma and deposit on a substrate (e.g., a semiconductive wafer) to be coated. Unfortunately, conductively-doped semiconductive target structures can be challenging and costly to produce, and frequently lack sufficient dopant concentrations to achieve desirable (e.g., relatively heavy) dopant concentrations in the source region and the drain region of a transistor. In addition, creating a heterogeneous dopant distribution within the source region and the drain region of a transistor using conventional PVD systems and processes can be very complex, inefficient, and costly (e.g., requiring the use of multiple conductively-doped semiconductive target structures having ditferent dopant concentrations than one another, as well as a prohibitively large number of processing steps).

A need, therefore, exists for new material deposition systems and methods of forming microelectronic devices, as well as for new microelectronic devices, memory devices, and electronic systems.

