CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Chinese patent application serial no. 201911350921.X, filed on Dec. 24, 2019. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

Technical Field

The disclosure relates to a decoding technology, and more particularly, relates to a video decoding method and a video decoding device.

Description of Related Art

With the development and spread of hardware capable of reproducing and storing high-resolution or high-definition video content, the demand for video codecs capable of effectively encoding or decoding high-resolution or high-definition video content is on the rise. In an effort to satisfy such demand, the Video Coding Experts Group (VCEG) of the International Telecommunication Union (ITU-T) joins hands with the Moving Picture Experts Group (MPEG) of the International Organization for Standardization (ISO/IEC) to develop the H.265/High Efficiency Video Coding (H.265/HEVC) project, with an aim to provide greater encoding efficiency than the encoding efficiency provided by the H.264/Advanced Video Coding (H.264/AVC) video compression standard.

In the H.265/HEVC video compression standard, an image is divided into blocks of a predetermined size, and residual data of the blocks is obtained through inter prediction or intra prediction. Residual data is compressed by transforming, quantizing, scanning, run-length encoding, and entropy encoding. In entropy coding, a syntax element of a transform coefficient or a prediction mode is entropy-encoded to output a bin string. The syntax element from the bin string is parsed and retrieved at the decoding end, and the bin string is decoded to reconstruct the image based on the retrieved syntax element (or called as a codeword). When H.265/HEVC is applied to decode a syntax element, the decoding end has to complete decoding of one syntax element before decoding the next syntax element. That is because the decoding end has to obtain the decoding result of the syntax element currently being decoded first, so as to learn how to decode the next syntax element.

For instance, referring toFIG. 1,FIG. 1is a schematic diagram of a conventional decoding syntax element code_sub_block_flag (CSBF) and a syntax element sig_coeff_flag (SIG). According to the current H.265/HEVC specification, it can be known that if the decoding result of the syntax element CSBF1 is “0”, the next to-be-decoded syntax element is CSBF2, and if the decoding result of the syntax element is CSBF1 is “1”, the next to-be-decoded syntax element is SIG1. In other words, not until decoding of the syntax element CSBF1 is completed does decoding of one of the syntax element CSBF2 and the syntax element SIG1begin. As such, decoding efficiency is limited and cannot be further improved.

SUMMARY

Accordingly, the disclosure provides a video decoding method and a video decoding device through which standby time required to decode a syntax element is reduced, so that decoding efficiency is improved.

An embodiment of the disclosure provides a video decoding method, and the method includes the following steps. A to-be-decoded bin string is received. A plurality of first current syntax elements in the to-be-decoded bin string are decoded based on a first context model until a decoding output value of the last one of the first current syntax elements matches a specific bin pattern. When the first current syntax elements are decoded, in response to that a state machine is switched from a first decoding operation mode to a second decoding operation mode, a second current syntax element that exists based on the last one of the first current syntax elements is decoded.

From another aspect, an embodiment of the disclosure provides a video decoding device including one circuit or a plurality of circuits. The circuit is configured to: receive a to-be-decoded bin string, decode a plurality of first current syntax elements in the to-be-decoded bin string based on a first context model until the last one of the first current syntax elements matches a specific bin pattern, and decode a second current syntax element that exists based on the last one of the first current syntax elements in response to that a state machine is switched from a first decoding operation mode to a second decoding operation mode when the first current syntax elements are decoded.

To sum up, in the embodiments of the disclosure, when decoding the plurality of first current syntax elements, the decoding device may decode the second current syntax element at the same time. Herein, the second current syntax element exists reflecting the decoding output value of the last one of the first current syntax elements matching the specific bin pattern. It thus can be seen that decoding of the first current syntax elements and decoding of the second current syntax element may be performed in parallel, idle time of a hardware circuit may be reduced and decoding efficiency is improved.

To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.

