TECHNICAL FIELD

The present disclosure relates to semiconductor devices.

BACKGROUND

A semiconductor device, such as a transistor, a thyristor, etc., may enter a failure state. The failure state may correspond to a short-circuit between power terminals of the semiconductor device. The failure state may cause an explosion of the semiconductor device, production of arcs and/or damage to one or more surrounding components.

SUMMARY

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key factors or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

In an embodiment, a semiconductor device is provided. The semiconductor device may comprise a control region, a first power region, a second power region, an isolation region and/or a short circuit structure. The control region may comprise a control terminal. The first power region may comprise a first power terminal. The second power region may comprise a second power terminal. The isolation region may be between the control region and the first power region. The short circuit structure may extend from the first power region, through the isolation region, to the control region. The short circuit structure may be configured to form a low-resistive connection between the control region and the first power region during a failure state of the semiconductor device.

In an embodiment, a semiconductor device is provided. The semiconductor device may comprise a semiconductor substrate, a control region, a first power region, a second power region, an isolation region and/or a failure structure. The semiconductor substrate may comprise silicon carbide (SiC). The control region may comprise a control terminal. The first power region may comprise a first power terminal. The second power region may comprise a second power terminal. The isolation region may be between the control region and the first power region. The isolation region may overly the semiconductor substrate. The failure structure may extend from the first power region, through the isolation region, to the control region. The failure structure may be configured to change a characteristic of at least some material between the control region and the first power region during a failure state of the semiconductor device.

In an embodiment, a semiconductor device is provided. The semiconductor device may comprise a semiconductor substrate, a control region, a first power region, a second power region, an isolation region, a transition structure and/or a dielectric structure. The semiconductor substrate may comprise SiC. The control region may comprise a control terminal. The first power region may comprise a first power terminal. The second power region may comprise a second power terminal. The isolation region may be between the control region and the first power region. The isolation region may overly the semiconductor substrate. The transition structure may extend from the first power region, through the isolation region, to the control region. The dielectric structure may surround a portion of the first power region. The dielectric structure may define an opening between the first power region and the transition structure.

To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth certain illustrative aspects and implementations. These are indicative of but a few of the various ways in which one or more aspects may be employed. Other aspects, advantages, and novel features of the disclosure will become apparent from the following detailed description when considered in conjunction with the annexed drawings.

