FIELD

This innovation relates to hardware security based on novel materials and devices.

BACKGROUND

Information security can be achieved at the software level using mathematical algorithms called one-way functions, such as prime factorization, discrete logarithm, hashing, etc., that allow seamless data encryption in polynomial time and require resource extensive computation in nondeterministic exponential time for data decryption by brute force trials (BFTs). One-way functions are often considered to be robust security measures.

Physically unclonable functions (PUFs) have also been used for hardware security. PUFs exploit natural variations in the physical microstructures of the actual hardware component and their complex interactions with various physical stimuli such as voltage, magnetic field, light, etc. These stimuli, when applied to a given microstructure, produce a unique and unpredictable result, one which repeats every time the same stimulus is applied to the same microstructure but differs drastically among the different microstructures. The applied stimulus is referred to as the challenge, the microstructure is referred to as the PUF, and the result is called the response. A specific challenge and its corresponding response together consist a challenge response pair, or CRP, which can efficiently be exploited for authentication of hardware devices. PUFs are a frugal hardware investment and can also be used as secure keys and on-chip source of random numbers.

PUFs are currently implemented by the semiconductor industry where stochastic fluctuations in the physical microstructures of the individual devices originating from manufacturing process variations are used as PUFs. Various incarnations of silicon (Si) PUFs exist, including static random-access memory (SRAM) and dynamic random-access memory (DRAM) based PUFs, arbiter PUFs, butterfly PUFs, flip-flop PUFs, ring oscillator PUFs, metal resistance PUFs, digital PUFs, etc. Si PUFs, however, suffer from small capacity, low entropy, high power consumption, and expensive area overhead and also often need to accommodate additional error-correcting pre- and/or post-processing units, such as majority voting, fuzzy logic, etc., in order to compensate for rather small device to device mismatches, which can make them vulnerable to noise and environmental fluctuations leading to false authentication.

SUMMARY

We have determined that known types of PUFs (e.g. Si PUFs) lack reconfigurability and show vulnerability against various machine learning (ML) attacks. Furthermore, we have determined that the Si-based technologies that may utilize Si PUFs can be incompatible with flexible and/or printable technologies. We have also determined that a new approach to PUFs can be utilized to better address noise and environmental fluctuations so that false authentication can be better avoided, if not eliminated.

Some embodiments can include a reliable, stable, high entropy, low cost, low power, scalable, area efficient, reconfigurable, and ML resilient PUF based on two dimensional (2D) materials such as graphene, MoS2, WS2, WSe2, black phosphorus, etc. Some embodiments can include field effect transistors (FETs) based on 2D materials that can be configured for harnessing the device to device variation. Embodiments utilizing our approach can embrace natural randomness, easing out typically stringent growth requirements, which can provide cost benefits. Some example embodiments include at least one graphene field effect transistor (GFET) based PUF. Utilization of an embodiment of our GFET-based generation of cryptographic primitives can be relatively effortless, self-supporting, and can be seamlessly integrated with any substrate—rigid or flexible. For instance, we found that the transfer characteristics (i.e. source-to-drain current (IDS) versus gate voltage (VBG)) of a large population of GFETs could demonstrate significant device to device variation that can be exploited as a near ideal and non-volatile physical entropy source for on-chip secure key generation, as well as challenge response pairs (CRPs) for physically unclonable functions (PUFs) for device authentication. Some embodiments of our GFET population (e.g. an array of GFETs, etc.) can allow low power reconfiguration that does not involve physical replacement of the devices and/or integration of additional hardware components. We believe this is a unique feature which is unprecedented when compared to any conventional state-of-the-art and emerging hardware PUFs. Some embodiments of graphene-based PUFs are stable over time and the utilized reconfiguration procedure has little-to-no impact on the PUF reliability. Some embodiments of graphene-based PUFs are resilient to ML attacks based on predictive regression models as well as generative adversarial networks (GANs). Note that Si and other nanomaterial-based PUFs face difficulty in resisting ML attacks. In contrast, some embodiments of our graphene-based PUFs can meet all of the requirements for state-of-the-art PUFs, including entropy, uniqueness, and correlation, as well as demonstrate reliable operation over a wide temperature range and against supply voltage variations.

In some embodiments, a physically unclonable function (PUF) includes at least one field effect transistor (FET). Each FET can include a first layer connected to a source and a drain and a gate oxide layer positioned between the first layer and a back-gate electrode.

The at least one FET can be a single FET or can include a plurality of FETs. When multiple FETs are provided, the FETs can be positioned in an array.

The first layer can include graphene or can consist of graphene or can consist essentially of graphene. In other embodiments, the first layer can include a different suitable 2D material such as molybdenum disulfide (MoS2), tungsten disulfide (WS2), tungsten diselenide (WSe2), or black phosphorus (BP). In other embodiments, the first layer can consist of or can consist essentially of MoS2, WS2, WSe2, or BP.

The PUF can also include circuitry. For instance, the PUF can include circuitry connected to the FETs. The circuitry can include resistors, transistors, switches, and other circuit components. In some embodiments, the circuitry can be positioned so that the analog output current (km) from each individual FET is convertible to an analog output voltage (VOUT). For instance, the circuitry can include at least one operational amplifier (Op-Amp) to convert the IOUTfrom each individual FET to VOUT. The circuitry can also includes at least one analog-to-digital converter (ADC) to convert the VOUTto a binary output or a voltage comparator to convert VOUTfrom each GFET into a binary output.

There can be any suitable number of FETs in the PUF to meet a particular set of design criteria. For instance, there can be 8 FETs, 64 FETs, 128 FETs, or 256 FETs.

Embodiments of the PUF can be incorporated into a sensor device, a detector device, a nanoelectronic device, an optoelectronic device, a plasmonic device, or a biomedical device. In yet other embodiments, the PUF can be incorporated into a chip used in such devices or some other device. The PUF can be configured to provide an on-chip security feature for the chip.

The circuitry of the PUF can be configured to detect analog current responses from the FETs to digitize the analog current responses to binary numbers appendable to generate challenge response pairs (CRPs). For example, the analog current response for each of the FETs can be measured at a gate voltage and digitized to an 8-bit binary number to be appended to the CRPs. For instance, for an embodiment that includes 8 FETs, the analog current responses for each and every one of the e8 FETs can be digitized to form the CRPs, where the CRPs are 64-bit.

Methods of fabricating a physically unclonable function (PUF) is also provided. Embodiments of the method can include forming a plurality of field effect transistors (FETs). Each FET can include a first layer connected to a source and a drain. The first layer can comprise graphene, molybdenum disulphide (MoS2), tungsten disulfide (WS2), tungsten diselenide (WSe2), or black phosphorus (BP). Each FET can also include a gate oxide layer positioned between the first layer and a back-gate electrode. The method can also include positioning an array of the FETs on a chip.

Embodiments of the method can also include other steps. For instance, the method can also include connecting circuitry to the FETs. The circuitry can be configured so that analog output current (IOUT) from each individual FET is convertible to analog output voltage (VOUT). For instance, the circuitry can include at least one operational amplifier (Op-Amp) to convert the IOUTfrom each individual FET to the VOUT. The circuitry can also include at least one analog-to-digital converter (ADC) to convert the VOUTto a binary output or a voltage comparator to convert the VOUTfrom each FET into a binary output.

Embodiments of the method can also include steps for forming the first layer. For instance, in some embodiments that utilize graphene in the first layer, the method can include growing graphene for the first layer on a foil so that a film of graphene is formed on the foil, transferring the graphene onto a substrate to introduce wrinkles into the graphene film, removing material of the foil from the film of graphene; and reducing a size of the wrinkles. Of course, other methods of growing and forming a graphene layer can also be used in other embodiments. Further, for embodiments in which the first layer is a different type of material, another type of formatting process can be used to form the first layer.

The forming of the FETs can include other steps. For instance, the forming of the FETs can include defining channels in the first layer (e.g. a graphene film, or a film of another suitable material) and writing a source contact for the source and a drain contact for the drain.

Embodiments of the method can also include reconfiguring the FETs. The reconfiguration of the FETs can occur a number of different times or just a single time. For instance, embodiments of the method can include reconfiguring the FETs. In some embodiments, the reconfiguring can include performing a first reconfiguration of the FETs by application of a first preselected voltage to the FETs for a first preselected period of time, and performing a second reconfiguration of the FETs after the first reconfiguration of the FETs is performed by application of a second pre-selected voltage to the FETs for a second preselected period of time. In yet other embodiments, there can be multiple other reconfigurations (e.g. third, fourth, fifth, etc. reconfigurations). Each reconfiguration can be performed after it is determined a reconfiguration is needed or may be performed as a pre-selected time period to provide updated security.

Embodiments of the method can also include preventing machine learning attacks from affecting the chip via the FETs. Of course, other security features can also be provided by the FETs as well in addition to preventing machine learning attacks from affecting a chip or other element that the PUF is protecting via at least one security feature of the PUF.

Other details, objects, and advantages of 2D material PUFs, graphene-based PUFs having one or more GFETs, 2D material PUFs having one or more FETs, devices utilizing at least one graphene-based PUF, sensor devices, nanoelectronic devices, optoelectronic devices, plasmonic devices, biomedical devices, and methods of making and using the same will become apparent as the following description of certain exemplary embodiments thereof proceeds.

