BACKGROUND

(1) Technical Field

The invention relates to electronic circuits, and more particularly to radio frequency circuitry fabricated with silicon-on-insulator technology.

(2) Background

Modern radio frequency (RF) transceivers have become ubiquitous, with manifestations found in cellular telephones, wireless networks (e.g., WiFi, Bluetooth), laptop computers, tablets, computer peripheral devices (e.g., printers, keyboards, mice), etc. That ubiquity has increased demand for smaller and lower power RF transceiver circuit designs.

FIG. 1is a block diagram of a typical prior art transceiver100such as the type that might be used in a cellular telephone. As illustrated, the transceiver100includes a mix of RF analog circuitry for directly conveying and/or transforming signals on an RF signal path, non-RF analog circuity for operational needs outside of the RF signal path (e.g., for bias voltages and switching signals), and digital circuitry for control and user interface requirements. In this example, a receiver path Rx includes RF Front End, IF Block, Back-End, and Baseband sections (noting that in some implementations, the lines between sections may be blurred).

The receiver path Rx receives over-the-air RF signals through an antenna102and a switching unit104, which may be implemented with active switching devices (e.g., field effect transistors or FETs), or with passive devices that implement frequency-domain multiplexing, such as a diplexer or duplexer. An RF filter106passes desired received RF signals to a low noise amplifier (LNA)108, the output of which is combined in a mixer110with the output of a first local oscillator112to produce an intermediate frequency (IF) signal. The IF signal may be amplified by an IF amplifier114and subjected to an IF filter116before being applied to a demodulator118, which may be coupled to a second local oscillator120. The output of the demodulator118is transformed to a digital signal by an analog-to-digital converter122and provided to one or more system components124(e.g., a video graphics circuit, a sound circuit, memory devices, etc.). The converted digital signal may represent, for example, images (video or still), sounds, or symbols, such as text or other characters.

In the illustrated example, a transmitter path Tx includes Baseband, Back-End, IF Block, and RF Front End sections (again, in some implementations, the lines between sections may be blurred). Digital data from one or more system components124is transformed to an analog signal by a digital-to-analog converter126, the output of which is applied to a modulator128, which also may be coupled to the second local oscillator120. The output of the modulator128may be subjected to an IF filter130before being amplified by an IF amplifier132. The output of the IF amplifier132is then combined in a mixer134with the output of the first local oscillator112to produce an RF signal. The RF signal may be amplified by a driver136, the output of which is applied to a power amplifier (PA)138. The amplified RF signal may be coupled to an RF filter140, the output of which is coupled to the antenna102through the switching unit104.

The operation of the transceiver100is controlled by a microprocessor142in known fashion, which interacts with system control components (e.g., user interfaces, memory/storage devices, application programs, operating system software, power control, etc.). In addition, the transceiver100will generally include other circuitry, such as bias circuitry146(which may be distributed throughout the transceiver100in proximity to transistor devices), electro-static discharge (ESD) protection circuits (not shown), testing circuits (not shown), factory programming interfaces (not shown), etc.

As should be apparent to one of ordinary skill in the art, some components of the transceiver100may be positioned in a different order (e.g., filters), and some of the components may be implemented as distinct integrated circuits (ICs). For example, the RF front end may be separately embodied from the rest of the circuitry (although there is a trend to try to integrate as much of the transceiver functionality as possible in a single IC). Other components can be (and usually are) added (e.g., additional filters, impedance matching networks, variable phase shifters/attenuators, power dividers, etc.). Importantly, in modern transceivers, there are often more than one receiver path Rx and transmitter path Tx—for example, to accommodate multiple frequencies and/or signaling modalities—so switching and control becomes more complex.

A challenge with electronic circuit design in general is that ideal components do not exist, particularly when dealing with RF signals. For example, the operational characteristics of many passive and active components in an RF signal path are frequency dependent. As another example, a significant problem with RF circuit design is eliminating or controlling unwanted cross-effects (“cross-talk”) and self-effects, such as parasitic capacitances and inductances, undesired signal coupling, performance changes due to environment temperature changes as well as self-heating, and others. The problems of RF design become more acute when embodying RF circuits as ICs, where components materials, circuit juxtaposition, and power constraints add to the difficulties of optimizing operational parameters for all components. As one example, FETs are inherently designed to operate with fields, but fields do not have distinct edges and often cause cross-effects and self-effects. As another example, FETs have operating parameters that are subject to process, voltage, and temperature (PVT) variations. Accordingly, RF circuit designs embodied as ICs generally require optimizations of some circuit parameters at the expense of other parameters.

As an example of such trade-offs, as noted above, a transceiver100will generally include bias circuitry.FIG. 2is a block diagram of a prior art bias voltage generation circuit200. In this example, a stable reference voltage source202provides a reference voltage VBG. The reference voltage source202may be, for example, a band-gap voltage reference, which is a temperature-independent voltage reference circuit widely used in ICs that produces an essentially constant voltage regardless of power supply variations, temperature changes, and load. The reference voltage VBGis applied to a voltage-to-current converter circuit204, which essentially divides the reference voltage VBGby a resistance R to generate a reference current IREF. The reference current IREFmay be applied to a bias generator circuit206which generates a specific bias voltage VBIASsuitable for a particular amplifier208. The bias generator circuit206may be simple or complex, depending on the needs of the overall circuit; examples of a variety of bias generator circuits are described in U.S. patent application Ser. No. 15/268,229, filed Sep. 16, 2016, entitled “Cascode Amplifier Bias Circuits”, assigned to the assignee of the present invention and hereby incorporated by reference.

A notable characteristic of RF circuits in general is that different components may require different optimizations. For example, the amplifier208is in the RF signal path and is generally an analog circuit optimized for performance at RF frequencies. Conversely, while the components of the bias voltage generation circuit200are also generally analog circuitry, they generally do not operate at RF frequencies and they may need optimizations that differ from RF signal path components. A distinct challenge of RF circuit design is that optimization for some circuitry may adversely affect optimization of other circuitry.

In general, for most transceivers, the RF signal path components are the most important circuitry to optimize. It was recognized some time ago that semiconductor-on-insulator (SOI) IC technology is particularly useful for such optimization. An important aspect of SOI technology is that the semiconductor region in which circuitry is formed is isolated from the bulk substrate by an electrically insulating layer. An advantage of isolating circuitry from the bulk substrate is a dramatic decrease in cross-talk and parasitic capacitance, which significantly improves speed and power characteristics for RF components.

FIG. 3is block diagram showing a typical prior art SOI IC structure300for a single FET. The SOI structure300includes a substrate302, an insulator layer304, and an active layer306. The substrate302is typically a semiconductor material such as silicon. The insulator layer304is a dielectric which is often silicon dioxide formed through the oxidation of a silicon substrate302; the insulator layer304is often referred to as a buried oxide (or “BOX”) layer. The active layer306may include some combination of implants and/or layers that include dopants, dielectrics, polysilicon, metal wiring, passivation, and other materials to form active and/or passive electronic components and/or mechanical structures. For example, in the illustrated embodiment, a FET is shown comprising a source S, a drain D, and a gate G atop an insulating layer308. Additional elements, not shown, may include contacts, conductive interconnections to other components and/or external connections, and protective coatings.

While the basic SOI IC structure300ofFIG. 3works reasonably well up to a point for RF circuitry such as transceiver components, as frequency increases and power specifications are reduced, cross-talk and parasitic elements again begin to affect such parameters as linearity and switching speed. Accordingly, other optimizations may be required. For example,FIG. 4is block diagram showing an improved prior art SOI IC structure400for a single FET. The SOI structure400includes a high resistivity substrate402, a trap rich layer404, a BOX insulator layer406, and an active layer408that includes a single example FET410.

The high resistivity of the substrate402makes the impedance of the parasitic paths through the substrate402higher. Materials used for the high resistivity substrate402typically include very lightly doped silicon such that the high resistivity substrate402takes on some of the characteristics of an insulator. The use of high resistivity substrates alone has proven capable of extending the benefit of SOI structures for RF communication circuits by roughly two orders of frequency magnitude.

The trap rich layer404is a solution to another problem. Although high resistivity substrates alone are capable of reducing substrate loss when used in SOI IC structures, they are highly susceptible to another phenomenon called parasitic surface conduction. The problem of parasitic surface conduction occurs because the high resistivity substrate402is capable of terminating field lines, but a thin surface region of the high resistivity substrate402can be formed into an inversion or accumulation region as charge carriers are affected by changes in signal voltages in the active layer408. The degree to which charge carriers in the thin surface region are displaced is directly altered by signals in the active layer408. As a result, without the trap layer404, the capacitance of the junction between the high resistivity substrate402and the active layer408, as seen by the active layer408, depends on the voltage applied, resulting in nonlinearity and a loss of signal purity. In addition, an applied voltage can invert this interface on the side of the high resistivity substrate402and create a channel-like layer within the thin surface region where charge can move very easily in a lateral direction despite the fact that the substrate layer402is highly resistive. Therefore, this effect can also lead to signal-degrading cross-talk in RF communication circuits.

Forming a trap rich layer404on top of the substrate layer402substantially mitigates parasitic surface conduction. The trap rich layer404is typically formed as a layer of amorphous or polycrystalline silicon on a top surface of the substrate402, and significantly degrades the mobility of the charge carriers in the thin surface region of the substrate402. Since the carriers cannot travel far, the effective resistance of the substrate402is preserved and the capacitance as seen by the active layer408is not as dependent upon the signals in the active layer408. The improved RF performance of SOI IC substrates with a trap rich layer404is so marked that wafers having that configuration are commercially available.

Thus, SOI based IC technology improves RF performance, to a point; high resistivity SOI substrates further improve RF performance, to a point; and high resistivity SOI substrates with trap rich layers further still improves RF performance. However, the improved performance of SOI-based RF circuitry formed in the active layer408above the trap rich layer404can adversely affect desired operational characteristics of non-RF circuitry formed in the active layer408above the trap rich layer404, such as switches and bias circuits.

For example, for some components (e.g., a power amplifier for use in a WiFi transceiver, such as one conforming to the IEEE 802.11ax or 802.11ac standards), the component is active for only short bursts of time (e.g., ˜4 mS in a WiFi power amplifier) and in a low power mode (e.g., “sleep” or “standby” mode) for most of the time to save power. In the WiFi example, the standby power consumption for a power amplifier may be very low (e.g., <10 μA), but the amplifier may be required to have a very quick sleep-to-active transition time (e.g., <1 μS) and to achieve a very stable gain very soon (e.g., <30 μS) after becoming active. The low power standby mode may be achieved by essentially switching some of the active circuitry OFF. More generally, many radio-based systems, particularly battery-operated systems (e.g., cellular telephones and WiFi radios) make significant use of standby modes to conserve power usage and/or to preserve battery life. Transitioning from a standby mode to an active mode introduces transient effects, especially in bias circuits, which can take a long time to settle out. However, many RF and analog performance requirements typically do not allow a lot of recovery (“buffer”) time. In general, such radio systems are designed to start transmitting a maximum amount of data as soon as possible. This requires that the radio system waken from standby mode back to active mode and be ready for full performance without significant transient effects.

Compounding the challenges of IC design is the fact that an SOI FET can develop an accumulated charge over time. For example, one type of accumulated charge depends upon the potentials at the source S, drain D, and gate G of the FET410. More particularly, when used in certain SOI circuit implementations, conventional FETs may operate in an accumulated charge regime. This phenomenon is also referred to as a “floating body effect” or “kink effect”, and more generally is the effect of dependence of the body potential of an SOI FET on the history of its biasing and carrier recombination processes. The body of the FET forms a capacitor with respect to the insulated substrate, and accordingly charge accumulates on this capacitor. The accumulated charge may cause adverse effects, such as opening of parasitic transistors in the structure and causing OFF-state leakages (resulting in higher current consumption), and also causes a history effect, which is the dependence of the threshold voltage VTHof a FET on the previous states of the FET.

Another aspect of accumulated charge is related to the OFF state of a FET and the resultant effect on device linearity, and is described in U.S. Pat. No. 7,910,993 B2, issued Mar. 22, 1011, entitled “Method and Apparatus for use in Improving Linearity of MOSFET'S using an Accumulated Charge Sink” and assigned to the assignee of the present invention.

A trap rich layer404on an SOI substrate402can be a separate source of accumulated charge. For example, when FETs in the active layer switch between ON and OFF states, the changing electrical fields accompanying such change in state can cause charge to accumulate between the trap rich layer404and the BOX insulator layer406. The high impedance nature of the trap rich layer404hinders dissipation of that trapped accumulated charge.

Regardless of source, accumulated charge can take a long time to equilibrate (e.g., >4 mS), and can affect the intrinsic properties of a FET device (e.g., the threshold voltage of the device, VTH). Thus, turning most or all switch FETs OFF to achieve a standby mode power level specification—as in the WiFi example above—results in accumulated charge in or near the trap rich layer404which takes time to dissipate when the FETs are turned back ON to the point of stable gain; that time may exceed a required sleep-to-active transition specification.

Anything that affects the operating point of a FET (e.g., VTH, biasing, current IDS, etc.) generally adversely impacts the performance of circuits based on such devices, such as the gain stability of an amplifier circuit. Because of the accumulated charge phenomenon, SOI FETs essentially have “memory”: that is, changing the operating point of a FET involves also settling the body of the FET and the substrate to a new potential. Further, neighboring FETs and charged nodes can affect the intrinsic properties of a FET. Under such conditions, turning a FET completely OFF and then getting it to turn ON and be completely stable immediately is quite challenging.

Even providing substrate contacts (S-contacts) to mitigate accumulated charges of various types, as taught in U.S. patent application Ser. No. 14/964,412 referenced above, does not fully mitigate the problem during operation (even if the contacts are ohmic), due to the high resistivity of the substrate402restricting the flow of charge. Moreover, anything coupling to the substrate402may change its potential, thereby affecting nearby FET devices.

Prior attempts to mitigate the accumulated charge problem for FETs fabricated on SOI substrates having a trap rich layer include improving the effectiveness of body ties (such as by interspersing ties on the source side of a FET), using shorter width and/or longer length FETs to lessen accumulated charge (noting that longer length FETs generally do not work for power amplifiers), or adopting process techniques to reduce body-tie resistance. Attempts have also been made at the circuit level to compensate for the effects of the accumulated charge problem (rather than actually mitigate the problem), such as by creating replica circuits to try to track out gain variation due to accumulated charge. However, such circuit specific solutions are generally inadequate as a general solution.

Accordingly, there is a need for methods and circuits that eliminate or reduce the formation of accumulated charge in SOI substrates having a trap rich layer, or which mitigate the effects of accumulated charge on the performance of FETs fabricated on SOI substrates having a trap rich layer. The present invention addresses these and other needs.

SUMMARY OF THE INVENTION

The invention encompasses several types of radio frequency (RF) integrated circuits (ICs) that avoid or mitigate creation of accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer, by avoiding a fully OFF state for at least some field effect transistors (FETs) within the circuit. By keeping the standby operating conditions of such critical FETs at the active state or as close to the active state as possible, accumulated charge is stabilized at a near-constant level. An important insight into the functioning of such FETs was the realization that the less that certain node voltages of FETs within an SOI IC change, the more stable the charge that may accumulate as a result of circuit activity in the active layer of an IC.

In a first general embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDSas during an active mode, thereby eliminating or reducing changes in accumulated charge.

In a second general embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGSas during the active mode, thereby eliminating or reducing changes in accumulated charge.

In a third general embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGSand VDSclose to their respective active mode operational voltages, thereby reducing changes in accumulated charge.

In some embodiments, S-contacts are formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects. More specifically, S-contacts substantially surround each circuit to be protected, essentially creating corresponding “wells” surrounded at least in part by S-contact “rings”. The rings of S-contacts reduce substrate impedance and thus settling time of the substrate voltage under the circuits, help in shielding the circuits from electrical interference, help in draining accumulated charge from certain layers of the IC, and help to improve impedance matching for the circuits within the wells by preventing uneven substrate potential between circuits.

Notably, embodiments of the invention, particularly the “trickle current” approach described below, help resolve a number of accumulated charge effects of SOI substrates (particularly SOI substrates having a trap rich layer), including floating body effects.

The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.

