BACKGROUND

Technological Field

The present technology relates to configuration of reconfigurable architectures, can be particularly applied to control flow logic for coarse-grain reconfigurable architectures and other distributed execution systems.

Description of Related Art

Reconfigurable processors, including field programmable gate arrays (FPGAs), can be configured to implement a variety of functions more efficiently or faster than might be achieved using a general purpose processor executing a computer program.

So-called coarse-grain reconfigurable architectures (e.g. CGRAs) are being developed in which the configurable units in the array are more complex than used in typical, more fine-grained FPGAs, and may enable faster or more efficient execution of various classes of functions. For example, CGRAs have been proposed that can enable implementation of energy-efficient accelerators for machine learning and artificial intelligence workloads. See, Prabhakar, et al., “Plasticine: A Reconfigurable Architecture for Parallel Patterns,” ISCA '17, Jun. 24-28, 2017, Toronto, ON, Canada.

In CGRAs and other processing systems that comprise a plurality of processing units that participate in a data processing operation, part of the data processing operation to be executed in one processing unit may need to be synchronized with other parts being executed in processing units distributed across the system. For example, several parts of the data processing operation may need to complete before a next part can safely begin. Thus, techniques for distributing control signals among elements of the processing system are required.

In order to maximize operating efficiency, and to be able to coordinate among processing units on a processing system, a means of efficiently managing control signaling is needed.

SUMMARY

A technology is described which enables efficient control signaling among processing units of a data processing system, including among reconfigurable processing units of a Coarse-Grained Reconfigurable Array processor.

A processing system is described that comprises an array of processing units arranged to perform execution fragments of a data processing operation. A processing unit in the array is arranged to respond to an enable signal to enable execution of an execution fragment by the processing unit, and generates a status signal usable to indicate status of the execution fragment performed in the processing unit. A control barrier network is coupled to processing units in the array. The control barrier network comprises a control bus configurable to form signal routes in the control barrier network; and a plurality of control barrier logic units having inputs and outputs connected to the control bus and to the array of processing units.

The control barrier network is configurable in configurable and reconfigurable architectures to provide signal routing suitable to support complex data processing operations in an array of configurable units, including for example in configurable units of a Coarse-Grained Reconfigurable Array processor.

The control barrier network provides the ability to register or record inbound tokens and status signals from several distinct sources, which can be defined in configuration data, and produce output barrier tokens, and other signals, based on specified combinations of the inbound tokens and status signals. Examples described herein are flexible enough to support control barriers across an arbitrary number of sources by decomposing the barrier logic into multiple levels.

The logic units in the plurality of control barrier logic units are configurable in technology described herein to consume source tokens and status signals on the inputs by, for example, registering the source tokens and status signals on the inputs. The logic units in the plurality of control barrier logic units are configurable in technology described herein to produce barrier tokens on the outputs based on the consumed source tokens and status signals. Also, the logic units can produce enable signals for the array of processing units based on the source tokens and status signals on the inputs.

The control bus can comprise a configurable interconnect configurable by configuration data to connect lines on the control bus carrying barrier tokens produced on the outputs of control barrier logic units to inputs of logic units that consume source tokens. The control bus can be configurable to form signal routes connecting the barrier token output of one logic unit in the plurality of logic units as a source token to inputs of more than one logic unit in the plurality of logic units. The control bus can be configurable to form signal routes providing barrier tokens sourced from more than one logic unit in the plurality of logic units to inputs of one logic unit in the plurality of logic units.

A control barrier logic unit in the plurality of logic units can be operatively coupled to, or a part of, an associated processing unit in the array of processing units.

In a technology described herein, the logic unit includes a token store having inputs and outputs; a configurable input circuit configurable to connect selected lines in the control bus and to a status signal line of the associated processing unit to inputs of the token store; and a barrier token output circuit configurable to provide a barrier token to the control bus in response to a first configurable combination of the outputs of the token store.

A logic unit in the plurality of logic units can include a feedback circuit configurable to provide a feedback signal in response to a second configurable combination of the outputs of the token store, to clear the token store. In some embodiments, the first and second configurable combinations can be the same. The logic units can include an enable signal output circuit to provide an enable signal for an associated configurable unit in response to a third configurable combination of the outputs of the token store. In some embodiments, the first and third configurable combinations can be the same.

In some embodiments, the processing system includes a data bus interconnecting the array of processing units, separate from the control bus. In a technology described herein, the data bus comprises a packet switched network and the control bus is configurable to form signal routes that are static during execution of corresponding execution fragments. In other embodiments, the control bus may be a packet-switched network. In still other embodiments, the control bus and data bus may operate on the same physical network, on different virtual channels.

Other aspects and advantages of the technology described herein can be seen on review of the drawings, the detailed description and the claims, which follow.

