BACKGROUND

1. Technical Field

The present disclosure relates to display technical field, and particularly relates to a dual-gate array substrate and a display device.

2. Description of the Related Art

With increase of resolution of a display panel, performance and cost of a drive integrated circuit (IC) necessarily increase. Thus, in order to reduce cost of the drive integrated circuit (IC) while increasing binding yield of the drive integrated circuit (IC), a design scheme of dual-gate drive is commonly used in a display panel. However, it is still needed to further improve an opening ratio and transmission of the display panel.

SUMMARY

Embodiments of the present disclosure provide a dual-gate array substrate and a display device, which have increased transmission relative to the dual-gate array substrate in related art.

Embodiments of the present disclosure include the following technical solutions.

A dual-gate array substrate includes:

a plurality of gate lines arranged in a first direction, each of the gate lines being extended in a second direction that is perpendicular to the first direction;

a plurality of primary signal lines and secondary signal lines arranged alternately in the second direction and extended in the first direction;

a plurality of pixel units being enclosed and defined by jointing adjacent two of the gate lines insulatively with the primary signal lines or the secondary signal lines, the primary signal lines being connected to a drive unit, and being connected respectively to the pixel units that are adjacent thereto;

wherein the dual-gate array substrate further includes common electrodes including a plurality of main electrodes and a plurality of branching electrodes;

wherein the secondary signal lines being connected to the common electrodes, and an orthographic projection of the main electrode on the dual-gate array substrate has overlapping regions respectively with orthographic projections of corresponding ones, adjacent to the main electrodes, of the pixel electrodes on the dual-gate array substrate and at least covers the primary signal line.

In an embodiment of the present disclosure, a width of the secondary signal line is not greater than a width of the primary signal line.

In an embodiment of the present disclosure, the main electrodes of the common electrodes are disposed in an extension direction of the primary signal lines, the branching electrodes are disposed to be parallel to the main electrodes, a pattern of the common electrodes formed by any adjacent two of the main electrodes and the secondary electrodes between the two main electrodes corresponds to a corresponding one of the pixel units;

wherein any two adjacent main electrodes include a first main electrode and a second main electrode, an orthographic projection of a first main electrode on the array substrate has overlapping regions respectively with orthographic projections of the pixel electrodes, adjacent to the first main electrode, on the dual-gate array substrate, and at least covers the primary signal lines, and an orthographic projection of a second main electrode, adjacent to the first main electrode, on the dual-gate array substrate is located within a gap between two pixel electrodes, adjacent to the second main electrode, and covers the secondary signal line.

In an embodiment of the present disclosure, the orthographic projection of the second main electrode, adjacent to the first main electrode, coincides with the secondary signal line.

In an embodiment of the present disclosure, the main electrodes of the common electrodes are disposed in an extension direction of the primary signal lines, the branching electrodes are disposed in a direction across the primary signal lines, and a pattern of the common electrodes formed by any adjacent two of the main electrodes and the secondary electrodes between the two main electrodes corresponds to adjacent two of the pixel units;

wherein orthographic projections of two of the main electrodes on the array substrate have overlapping regions respectively with orthographic projections of the pixel electrodes, adjacent to the two of the main electrodes, on the dual-gate array substrate, and at least cover the main signal lines, and a pattern of the secondary electrodes at a boundary between adjacent two of the adjacent pixel units is continuous.

In an embodiment of the present disclosure, the branching electrodes are each provided with a corner structure at the boundary between the adjacent two of the pixel units.

With this configuration, uneven display caused by movement or pressure action during touch operation may be eliminated.

In an embodiment of the present disclosure, the secondary signal lines are made of metal or transparent oxide.

In an embodiment of the present disclosure, the secondary signal lines are made of tin indium oxide.

Embodiments of the present disclosure provide a dual-gate array substrate, comprising:

a plurality of gate lines arranged in a first direction, each of the gate lines being extended in a second direction that is perpendicular to the first direction;

a plurality of primary signal lines and secondary signal lines arranged alternately in the second direction and extended in the first direction;

a plurality of pixel units each being enclosed and defined by jointing adjacent two of the gate lines insulative with corresponding ones of the primary signal lines or the secondary signal lines, the pixel units each including pixel electrodes, the primary signal lines being connected to a drive unit and being connected respectively to ones of the pixel units that are adjacent thereto;

wherein the dual-gate array substrate further comprises common electrodes located in a different layer from the pixel units and comprising a plurality of main electrodes and a plurality of branching electrodes; and

wherein an orthographic projection of one of the main electrodes on the dual-gate array substrate at least covers a corresponding one of the primary signal lines and does not overlap orthographic projections of two ones, adjacent to the corresponding one of the primary signal lines, of the pixel electrodes on the dual-gate array substrate.

In an embodiment of the present disclosure, a line width of each of the secondary signal lines is not greater than a line width of each of the primary signal lines.

In an embodiment of the present disclosure, the main electrodes of the common electrodes are disposed in an extension direction of the primary signal lines, the branching electrodes are disposed to be parallel to the main electrodes, a pattern of the common electrodes formed by any adjacent two of the main electrodes and the secondary electrodes between the two of the main electrodes corresponds to a corresponding one of the pixel units, and the secondary signal lines are connected to the common electrodes;

wherein any adjacent two of the main electrodes include a first main electrode and a second main electrode, an orthographic projection of the first main electrode on the array substrate covers an orthographic projection of a corresponding one of the primary signal lines on the dual-gate array substrate, and does not overlap orthographic projections of the ones, adjacent to the corresponding one of the primary signal lines, of the pixel electrodes on the dual-gate array substrate; and an orthographic projection of the second main electrode, adjacent to the first main electrode, on the dual-gate array substrate covers an orthographic projection of a corresponding one of the secondary signal lines on the dual-gate array substrate and does not overlap orthographic projections of the ones, adjacent to the corresponding one of the secondary signal lines, on the dual-gate array substrate.

In an embodiment of the present disclosure, the orthographic projection of the second main electrode, adjacent to the first main electrode, on the dual-gate array substrate coincides with the orthographic projection of the corresponding one of the secondary signal lines on the dual-gate array substrate.

In an embodiment of the present disclosure, the main electrodes of the common electrodes are disposed in an extension direction of the primary signal lines respectively, the branching electrodes are disposed to be parallel to the main electrodes, a pattern of the common electrodes formed by any adjacent two of the main electrodes and the secondary electrodes between the two of the main electrodes corresponds to a corresponding one of the pixel units; and

wherein orthographic projections of the main electrodes on the array substrate cover orthographic projections of the primary signal lines on the dual-gate array substrate respectively, and do not overlap orthographic projections of the ones, adjacent to the primary signal lines, of the pixel electrodes on the dual-gate array substrate; and viewed in a direction orthogonal to the dual-gate array substrate, no main electrode is provided over the secondary signal lines.

In an embodiment of the present disclosure, the main electrodes of the common electrodes are disposed in an extension direction of the primary signal lines respectively, the branching electrodes are disposed in a direction across the primary signal lines, and a pattern of the common electrodes formed by any adjacent two of the main electrodes and the branching electrodes between the two main electrodes corresponds to adjacent two of the pixel units; and

wherein orthographic projections of adjacent two of the main electrodes on the dual-gate array substrate at least cover the primary signal lines and do not overlap orthographic projections of the ones, adjacent the primary signal lines, of the pixel electrodes on the dual-gate array substrate; and a pattern of the branching electrodes at a boundary between adjacent two of the adjacent pixel units is continuous.

In an embodiment of the present disclosure, the dual-gate array substrate further includes a photo spacer disposed at either side of each of the secondary signal lines and the photo spacer has two ends with different sizes; and

wherein between each pair of the primary signal line and the secondary signal line and within a space between adjacent two of the pixel units, the thin film transistor is disposed a side of the space close to the primary signal line and a metal pad is disposed a side of the space close to the corresponding secondary signal line.

In an embodiment of the present disclosure, the photo spacer has a frustoconical shape.

In an embodiment of the present disclosure, the dual-gate array substrate further includes a metal pad configured such that an end of the photo spacer with a greater size is disposed on a side surface of the metal pad facing away from the pixel electrode, wherein the metal pad and source and drain electrodes of the thin film transistor are different portions of a same metal film.

A display device includes a color film substrate, and further comprises the above dual-gate array substrate.

In an embodiment of the present disclosure, a black matrix is provided, at a position corresponding to the secondary signal lines in the dual-gate array substrate, in the color film substrate, wherein an orthographic projection of the black matrix on the dual-gate array substrate coincides with an orthographic projection of the secondary signal lines on the array substrate.

