FIELD OF THE INVENTION

The present invention relates to embedded memory devices, and more particularly, to embedded back-end-of-line (BEOL) memory devices having a top electrode pillar.

BACKGROUND OF THE INVENTION

Resistive random access memory (RRAM) is a type of non-volatile memory. RRAM devices store information based on a resistance across a dielectric element. The dielectric is typically insulating. However, an applied voltage to the RRAM device is used to form an electrically-conductive path or filament through the dielectric element.

Memory devices such as RRAM can be integrated with other device elements such as logic devices in embedded circuit designs. However, accessing the memory devices in a memory integration scheme can present some notable challenges.

For example, current back-end-of-line (BEOL) embedded memory integration schemes have wide top-level metal lines landing directly on the RRAM stack which causes etch and reliability issues. For instance, if the etch for the metal line is too deep, the metal line can wrap around the RRAM stack, causing shorts between the top and bottom electrodes.

Therefore, improved BEOL memory integration schemes would be desirable.

SUMMARY OF THE INVENTION

The present invention provides embedded back-end-of-line (BEOL) memory devices having a top electrode pillar. In one aspect of the invention, a method of forming an embedded memory device is provided. The method includes: depositing a first interlayer dielectric (ILD) on a substrate; forming at least one first interconnect in the first ILD over a logic region of the substrate, and at least one second interconnect in the first ILD over a memory region of the substrate; depositing a capping layer onto the first ILD over the at least one first interconnect and the at least one second interconnect; forming a memory film stack on the capping layer, the memory film stack including a bottom electrode layer disposed on the capping layer, a dielectric layer disposed on the bottom electrode layer, and a top electrode layer disposed on the dielectric layer; patterning the memory film stack into at least one memory device including a bottom electrode disposed on the capping layer over the at least one second interconnect, a dielectric element disposed on the bottom electrode, and a top electrode disposed on the dielectric element, wherein the at least one memory device has a width W1; patterning the top electrode to form a pillar-shaped top electrode having a width W2, wherein W2<W1; depositing a conformal encapsulation layer over the capping layer and the at least one memory device; depositing a second ILD over the conformal encapsulation layer; and forming at least one first metal line in the second ILD in contact with the at least one first interconnect, and at least one second metal line in the second ILD in contact with the pillar-shaped top electrode.

In another aspect of the invention, another method of forming an embedded memory device is provided. The method includes: depositing a ILD on a substrate; forming at least one first interconnect in the first ILD over a logic region of the substrate, and at least one second interconnect in the first ILD over a memory region of the substrate; depositing a capping layer onto the first ILD over the at least one first interconnect and the at least one second interconnect; forming a contact that extends through the capping layer; forming a memory film stack on the capping layer, the memory film stack including a bottom electrode layer disposed on the capping layer, a dielectric layer disposed on the bottom electrode layer, and a top electrode layer disposed on the dielectric layer; patterning the memory film stack into at least one memory device including a bottom electrode disposed on the capping layer over the at least one second interconnect, a dielectric element disposed on the bottom electrode, and a top electrode disposed on the dielectric element, wherein the at least one memory device has a width W1, and wherein the contact connects the at least one memory device to the at least one second interconnect; patterning the top electrode to form a pillar-shaped top electrode having a width W2, wherein W2<W1, and wherein the bottom electrode has a thickness T1and the pillar-shaped top electrode has a thickness T2, wherein T2>T1; depositing a conformal encapsulation layer over the capping layer and the at least one memory device; depositing a second ILD over the conformal encapsulation layer; and forming at least one first metal line in the second ILD in contact with the at least one first interconnect, and at least one second metal line in the second ILD in contact with the pillar-shaped top electrode.

In yet another aspect of the invention, a device is provided. The device includes: a first ILD disposed on a substrate; at least one first interconnect formed in the first ILD over a logic region of the substrate, and at least one second interconnect formed in the first ILD over a memory region of the substrate; a capping layer disposed on the first ILD over the at least one first interconnect and the at least one second interconnect; at least one memory device disposed on the capping layer including a bottom electrode disposed on the capping layer over the at least one second interconnect, a dielectric element disposed on the bottom electrode, and a pillar-shaped top electrode disposed on the dielectric element, wherein the bottom electrode and the dielectric element have a width W1and the pillar-shaped top electrode has a width W2, wherein W2<W1; a conformal encapsulation layer disposed over the capping layer and the at least one memory device; a second ILD disposed over the conformal encapsulation layer; and at least one first metal line formed in the second ILD in contact with the at least one first interconnect, and at least one second metal line formed in the second ILD in contact with the pillar-shaped top electrode.

A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings.

