FIELD

The present application relates to an integrated circuit (IC) chip and a method of forming the same. More particularly, the present application relates to an IC chip including a back-end-of-the-line (BEOL) metal-insulator-metal (MIM) capacitor and an integrally formed e-fuse element co-processed with an MIMcap electrode.

BACKGROUND

On-chip capacitors including metal-insulator-metal (MIM) capacitors are essential for many semiconductor chips. For example, MIM capacitors are frequently utilized as decoupling capacitors for mitigating power supply or switching noise caused by changes in current flowing in an integrated chip. MIM capacitors are often integrated into a back-end-of-the-line (BEOL) metallization stack, at a positon between an underlying first metallization layer and an overlying second metallization layer. When integrated, a MIM capacitor is commonly formed as a stacked structure including planar electrode plates.

Current BEOL e-fuses use Cu wire or a via as a fuse element, and due to limitations of lithographic semiconductor device processing, the Cu efuse can not be made any smaller than the minimum line width, thereby requiring higher power (larger devices) to program. As a result, there is possibility of inflicting potential severe damage during programing, thereby requiring surrounding fuse protection. This currently requires the building of e-fuses at lower metal levels, where the spacing has higher demand for signal/power wiring.

SUMMARY

An e-fuse element for an on-chip MIM capacitor, the e-fuse element formed integral with a MIM capacitor plate.

An e-fuse element for an on-chip MIM capacitor, the e-fuse element connecting to and/or integral with a MIMcap plate electrode and co-processed during fabricating of the MIM capacitor at the MIM capacitor level.

A method of fabricating an eFuse with an MIMcap process without any extra lithographic mask and processing steps.

In the present application, a MIM capacitor is formed at a BEOL metallization stack and the metallization stack co-processing steps form an e-fuse to as part of the MIM capacitor.

In one aspect of the present application, a semiconductor structure is provided. The semiconductor structure comprises: a metal-insulator-metal (MIM) capacitor (“MIMcap”) having a bottom electrode located on a topmost surface of a first dielectric material layer, a first capacitor dielectric located on the bottom electrode, a middle electrode located on the first capacitor dielectric, a second capacitor dielectric located on the middle electrode and a top electrode located on the second capacitor dielectric, a portion of the middle electrode in overlapped relation with a portion of the bottom electrode and a portion of the top electrode; a third dielectric material layer located over the MIM capacitor and the second dielectric material layer; a first upper interconnect structure extending through the third dielectric material layer, the second dielectric material layer and the first dielectric material layer to vertically contact a first lower interconnect structure embedded in a portion of a first dielectric material layer, wherein the first upper interconnect structure laterally contacts the middle electrode at a first end of the MIM capacitor; and a second upper interconnect structure extending through the third dielectric material layer, the second dielectric material layer and the first dielectric material layer to vertically contact a second lower interconnect structure embedded in another portion of the first dielectric material layer; and an integral portion of the middle electrode extending laterally beyond the first end of the MIM capacitor to define a fusing element, the fusing element having a first end portion laterally contacting the first upper interconnect structure and a second end portion laterally contacting second upper interconnect structure.

In another aspect of the present application, a semiconductor structure is provided. The structure includes a first metal-insulator-metal (MIM) capacitor (“first MIMcap”) having a bottom electrode located on a topmost surface of a first dielectric material layer, a first capacitor dielectric located on the bottom electrode, a middle electrode located on the first capacitor dielectric, a second capacitor dielectric located on the middle electrode and a top electrode located on the second capacitor dielectric, a portion of the middle electrode in overlapped relation with a portion of the bottom electrode and a portion of the top electrode; a third dielectric material layer located over the MIM capacitor and the second dielectric material layer; a first conductive via structure extending through the third dielectric material layer, the second dielectric material layer and the first dielectric material layer to vertically contact a first lower interconnect structure embedded in a portion of a first dielectric material layer, wherein the first conductive via structure laterally contacts the middle electrode at a first end of the first MIM capacitor; a parallel-connected second MIMcap having a bottom electrode located on a topmost surface of a first dielectric material layer, a first capacitor dielectric located on the bottom electrode, a middle electrode located on the first capacitor dielectric, the second capacitor dielectric located on the middle electrode and a top electrode located on the second capacitor dielectric, a portion of the middle electrode in overlapped relation with a portion of the bottom electrode and a portion of the top electrode of the second MIMcap, the third dielectric material layer located over the second MIM capacitor and the second dielectric material layer; a second conductive via structure extending through the third dielectric material layer, the second dielectric material layer and the first dielectric material layer to vertically contact a second lower interconnect structure embedded in another portion of the first dielectric material layer, wherein the second conductive via structure laterally contacts the middle electrode at a first end of the first MIM capacitor; and the middle electrode of the first MIMcap and parallel connected second MIMcap being an integral unitary structure; and an integral portion of the middle electrode of the first MIMcap and parallel connected second MIMcap comprising a fusing element, the fusing element having a first end portion laterally contacting the first conductive via structure and a second end portion laterally contacting second conductive via structure.

