SUMMARY

The present disclosure is directed to recovering from hard decoding errors by removing log likelihood values read from NAND memory cells. In one embodiment, hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors may be estimated and BER for the read channel may be estimated. Hard error regions may be found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder to decode the codeword bits is changed based on the hard error regions, the BER for the hard errors, and/or the BER for the read channel.

In another embodiment, hard errors are determined for an unsuccessful decoding of codeword bits read from the NAND memory cells via an LDPC decoder. The NAND memory cells are more likely to exhibit higher voltage thresholds upon being read back than the originally programmed voltage thresholds such that a BER of first hard errors for bits flipped from a ‘1’ to a ‘0’ are different than a number of second BER for bits flipped from a ‘0’ to a ‘1’. Hard error regions are found using an SLC reading of the NAND memory cells in response to determining the hard errors. An LLR mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions.

These and other features and aspects of various embodiments may be understood in view of the following detailed discussion and accompanying drawings.

