FIELD OF THE INVENTION

The disclosed embodiments relate generally to nonvolatile memory devices, and more particularly, to nonvolatile memory devices with a metal-insulator-metal (MIM) capacitor in a substrate and integration schemes.

BACKGROUND

A nonvolatile memory device retains stored data even if power is turned off. An example of a nonvolatile memory device includes electrically erasable programmable read only memory (EEPROM) and flash EEPROM. In typical flash memory architecture, a floating gate may be used to store charges. The floating gate may be arranged over an active region such as a p-well. A source region may be formed in the p-well adjacent to a first side of the floating gate and a drain region may be formed in the p-well adjacent to a second side of the floating gate opposite to the first side. A metal-insulator-metal capacitor may be used to bias the floating gate. The metal-insulator-metal capacitor is in a back-end-of line (BEOL) layer over the floating gate. The term “back-end-of line” may refer to a portion of a semiconductor processing that creates conductive lines carrying power and signals between devices such as transistors to a semiconductor chip interface.

A coupling ratio of the nonvolatile memory device with the metal-insulator-metal capacitor in the back-end-of-line layer over the floating gate is insufficient due to space constraints in the back-end-of-line layer. The issue is further aggravated for advanced technology nodes as feature sizes of the nonvolatile memory device shrinks. The low coupling ratio leads to higher program and erase voltages and a shorter device lifetime. Thus, there is a need to overcome the challenges mentioned above.

SUMMARY

In an aspect of the present disclosure, a nonvolatile memory device is provided. The nonvolatile memory device comprises a floating gate arranged over a first active region, whereby the first active region may be arranged in an active layer of a substrate. A metal-insulator-metal capacitor may be arranged laterally adjacent to the floating gate, whereby a portion of the metal-insulator-metal capacitor may be in the active layer. A contact pillar may connect a first electrode of the metal-insulator-metal capacitor to the floating gate.

In another aspect of the present disclosure, an array of nonvolatile memory devices is provided. The array of nonvolatile memory devices comprises a first active region and a second active region arranged in an active layer of a substrate. A first isolation region and a second isolation region adjacent to the first isolation region may be arranged between the first active region and the second active region. A first array of floating gates may be arranged over the first active region and a second array of floating gates may be arranged over the second active region. A metal-insulator-metal capacitor may be arranged laterally adjacent to the floating gates, whereby a lower portion of the metal-insulator-metal capacitor may be arranged in the first isolation region in the active layer and a first dielectric layer in the substrate. A contact pillar may connect a first electrode of the metal-insulator-metal capacitor to each floating gate.

In yet another aspect of the present disclosure, a method of fabricating a nonvolatile memory device is provided. The method comprises providing a floating gate arranged over a first active region, whereby the first active region may be arranged in an active layer of a substrate. A contact pillar may be provided over the floating gate. A metal-insulator-metal capacitor may be provided laterally adjacent to the floating gate, whereby a portion of the metal-insulator-metal capacitor may be arranged in the active layer and a first electrode of the metal-insulator-metal capacitor may be connected to the floating gate by the contact pillar.

Numerous advantages may be derived from the embodiments described below. The embodiments provide a nonvolatile memory device with a high coupling ratio. A second electrode of the metal-insulator-metal capacitor may be connected to an input terminal. The term “coupling ratio” may refer to the voltage transfer capability from the metal-insulator-metal capacitor to the floating gate. A lower portion of the metal-insulator-metal capacitor may be arranged in a first isolation region. An upper portion of the first isolation region may be surrounded by a second isolation region adjacent to the first active region leading to a compact nonvolatile memory device. The second isolation region may be a shallow trench isolation region. An extension portion of the metal-insulator-metal capacitor may be arranged over an inter metal dielectric (IMD) layer over the floating gate leading to a high capacitance value and a high coupling ratio. The metal-insulator-metal capacitor may extend across at least a length of an active region providing a high coupling ratio for the nonvolatile memory device. A lower portion of the metal-insulator-metal capacitor may be separated from a base layer of the substrate by a portion of the first dielectric layer. Thereby the metal-insulator-metal capacitor is electrically insulated from the base layer of the substrate, leading to a stable device operation.

