TECHNICAL FIELD

The present invention relates to a connection body, to a package and to a method of manufacturing a connection body.

BACKGROUND

A package, for instance for automotive applications, provides a physical containment for one or more electronic chips comprising one or more integrated circuit elements. Examples of integrated circuit elements of packages are a field effect transistor, an insulated-gate bipolar transistor (IGBT), a diode, and passive components (such as an inductance, a capacity, a resistor). Moreover, such packages may be used for producing a system-in-package.

For manufacturing a package, an electronic chip may be mounted on a chip carrier (such as a leadframe). Subsequently, a chip pad may be connected with the chip carrier by wire bonding. The at least one electronic chip may then be encapsulated by an appropriate encapsulant.

However, there is still potentially room to improve reliability of a chip package, in particular in terms of the mechanical integrity of the package. Also miniaturization of packages and a simple manufacturing method are desired. Last but not least, an efficient wiring architecture of a package is desirable.

SUMMARY

There may be a need for an efficient wiring architecture for an electronic chip which is compact and simple in manufacture.

According to an exemplary embodiment, a connection body is provided which comprises a base structure at least predominantly made of a semiconductor oxide material or glass, and an electrically conductive wiring structure on and/or in the base structure, wherein the electrically conductive wiring structure comprises at least one vertical wiring section with a first lateral dimension on and/or in the base structure and at least one lateral wiring section connected with the at least one vertical wiring section, wherein the at least one lateral wiring section has a second lateral dimension on and/or in the base structure, which is different to (in particular larger than) the first lateral dimension.

According to another exemplary embodiment, a package is provided which comprises an electronic chip having at least one pad (in particular exactly one pad or a plurality of pads), and a connection body comprising a base structure at least predominantly made of a semiconductor oxide material or glass and an electrically conductive wiring structure at least partially on and/or in the base structure, wherein the electrically conductive wiring structure of the connection body is connected to the at least one pad of the electronic chip.

According to another exemplary embodiment, a method of manufacturing a connection body is provided, wherein the method comprises providing a base structure at least predominantly made of a semiconductor oxide material or glass material, and forming an electrically conductive wiring structure on and/or in the base structure, wherein the electrically conductive wiring structure is formed with at least one vertical wiring section extending vertically through at least part of the connection body (in particular of the base structure) and with at least one lateral wiring section connected with the at least one vertical wiring section and extending laterally in the connection body (in particular in the base structure).

According to an exemplary embodiment, a connection body and a package are provided with a semiconductor oxide or glass based base structure with an electrically conductive wiring formed therein with an extension both in a lateral and in a vertical direction so that in particular at least one edge may be formed at an interface between a lateral wiring section and an adjacent vertical wiring section. By taking this measure, a cheap semiconductor oxide/glass base structure may be used for forming an electrically conductive wiring in an interior thereof. The latter may serve for contacting at least one electronic chip when the latter is mounted on the connection body. By taking this measure, the wiring connection of one or more electronic chips to be packaged may be formed in a very simple and compact way with very small effort and by carrying out a simple manufacturing process. Furthermore, the described packaging procedure of the electronic chip is highly appropriate for parallel processing in a batch manufacturing architecture, i.e. for forming multiple chip packages at the same time. Descriptively speaking, many processes of such a manufacturing procedure can be carried out on “wafer” level when the connection body is dimensioned so as to electrically connect (and optionally additionally also to mechanically carry) multiple electronic chips of different packages before singularization into individual packages.

In the following, further exemplary embodiments of the connection body, the package and the method will be explained.

In the context of the present application, the term “package” may particularly denote at least one electronic chip coupled with a wiring structure as at least one external electric contact. Such a package may further comprise a dielectric protection structure for protecting and insulating the chip (which may be accomplished in exemplary embodiments by the base structure), and optionally an electrically conductive carrier on which the chip may be mounted.

In the context of the present application, the term “electronic chip” may particularly denote a chip (more particularly a semiconductor chip) providing an electronic function. The electronic chip may be an active electronic component. In one embodiment, the electronic chip is configured as a controller chip, a processor chip, a memory chip, a sensor chip or a micro-electromechanical system (MEMS). In an alternative embodiment, it is also possible that the electronic chip is configured as a power semiconductor chip. Thus, the electronic chip (such as a semiconductor chip) may be used for power applications for instance in the automotive field and may for instance have at least one integrated insulated-gate bipolar transistor (IGBT) and/or at least one transistor of another type (such as a MOSFET, a JFET, etc.) and/or at least one integrated diode. Such integrated circuit elements may be made for instance in silicon technology or based on wide-bandgap semiconductors (such as silicon carbide, gallium nitride or gallium nitride on silicon). A semiconductor power chip may comprise one or more field effect transistors, diodes, inverter circuits, half-bridges, full-bridges, drivers, logic circuits, further devices, etc. The electronic chip may be a naked chip or may be already packaged or encapsulated. However, the electronic chip may also be a passive component such a capacitor or a resistor. A chip may also be denoted as die.

In the context of the present application, the term “carrier” may particularly denote an at least partially electrically conductive structure which serves simultaneously as a mounting base for one or more electronic chips and also contributes to the electric connection of the electronic chip(s) with an electronic environment of the package. In other words, the chip carrier may fulfil a mechanical support function and an electric connection function. A preferred embodiment of a carrier is a leadframe.

In the context of the present application, the term “glass” may particularly denote a non-crystalline amorphous solid comprising a significant amount of silicon dioxide (SiO2), i.e. silica. Silica may be the main component of glass. In particular, the term glass covers silicate glasses which are based on the chemical compound silica (silicon dioxide, or quartz). Of the many silica-based glasses that can be used, one example is a composition of approximately 75% silicon dioxide (SiO2), additionally sodium oxide (Na2O) and calcium oxide (CaO), and several minor additives. It is also possible that the glass is made of pure silica (SiO2), as in case of fused quartz. In particular, at least 80 weight percent, in particular at least 95 weight percent of the base structure of the connection body may be glass.

In the context of the present application, the term “semiconductor oxide” may particularly denote a chemical compound comprising a semiconductor material as first constituent and oxygen as further constituent. An example of a semiconductor oxide is silicon oxide (in particular silicon dioxide). Another example of a semiconductor oxide is germanium oxide (in particular germanium dioxide).

In the context of the present application, the term a base structure “at least predominantly made” of glass or semiconductor oxide may particularly denote that the main constituent or major component of the base structure may be glass material or semiconductor oxide material. In particular, the weight percentage of glass or semiconductor oxide of a base structure at least predominantly made of glass or semiconductor oxide may be at least 60 weight percent, in particular at least 70 weight percent, more particularly at least 90 weight percent. It is also possible that the base structure consists only of glass or semiconductor oxide.

In the context of the present application, the term “vertical wiring section” may particularly denote an electrically conductive section of the wiring structure extending along the thickness direction of the (in particular plate shaped) connection body. The connection body may have a dimension in its thickness direction of less than 50%, in particular of less than 20%, compared to its dimensions perpendicular to the thickness direction (i.e. compared to its dimensions in a plane corresponding to or parallel to two opposing main surfaces of the connection body.

In the context of the present application, the term “lateral wiring section” may particularly denote an electrically conductive section of the wiring structure extending perpendicular to the thickness direction of the (in particular plate shaped) connection body. A lateral or horizontal wiring structure may extend parallel to opposing main surfaces of the (in particular plate shaped) connection body.

A gist of an exemplary embodiment is the provision of a method for forming a semiconductor device or package. In such an embodiment, one or more electronic chips may be optionally arranged on a carrier such as a leadframe. Additionally, a wiring (or rewiring) structure may be formed in a base structure having glass or a semiconductor oxide material as main constituent (in particular a glass substrate, a semiconductor oxide substrate or a semiconductor oxide layer on a support body made of another material). In a further procedure, the base structure with the wiring structure formed therein (which may be denoted altogether as connection body) may be attached to the carrier (if present) such that the wiring structure electrically contacts the one or more electronic chips. In an embodiment in which no carrier is present, the one or more electronic chips may be directly mounted on the wiring structure of the connection body. The latter then also serves for carrying or holding the one or more electronic chips, in addition to its electric connection function.

In an embodiment, the base structure is made substantially of glass. In particular, at least 90 weight percent of the base structure, more particularly the entire base structure, may consist of glass. Thus, a simple glass body may be processed (in particular by etching) for forming wiring structures therein.

In another embodiment, the base structure may be made substantially of silicon dioxide (SiO2). In particular, at least 90 weight percent of the base structure, more particularly the entire base structure, may consist of silicon dioxide.

In yet another embodiment, it is also possible to form a base structure by covering a support body (in particular a silicon body) in a surface portion with a silicon dioxide surface layer (or a glass layer). This may be accomplished, for instance, by surface oxidation (for instance of silicon material), by material deposition, or by attachment of a previously separate base structure (for instance a thin glass plate) on the support body. The surface layer may then form the base structure in which the electrically conductive wiring structure is formed. For instance, the base structure may be substantially made of silicon dioxide which is present only in a surface region of a (in particular silicon) wafer. A main portion of the wafer may then constitute the support body and may hence serve as mechanical support, while the silicon oxide coverage constitutes the base structure and serves for forming the wiring structure therein.

For instance, a silicon wafer, as support body, being covered with silicon oxide, as base structure, may form part of a connection body.

In an embodiment, the electrically conductive wiring structure extends (in particular only) through a subportion of the thickness of the base structure without extending through the entire thickness of the base structure. In other words, a blind hole (in particular with complex shape having vertical as well as lateral sections) may be formed in the base structure and may be filled with electrically conductive material to thereby form the wiring structure. For example, such a connection body may be used as a substitute for bond wires, bond ribbons or clips used conventionally for contacting a chip pad with a chip carrier such as a leadframe. In the described embodiment, this connection task may be accomplished by a wiring structure in a base structure which wiring structure does not extend through the entire thickness of the base structure (compare for instanceFIG.4,FIG.5andFIG.53).

In another embodiment, the electrically conductive wiring structure extends through the entire base structure. In such an embodiment, it is for instance possible that the electrically conductive wiring constitutes a redistribution structure which translates, in terms of electrically conductive connection surfaces, between a small chip size and a larger size of a mounting base (for instance a printed circuit board) on which the connection body or package may be mounted. In such embodiments, the electronic chip may be mounted on one side of the connection body with one or more chip pads which can be connected to the opposing other side of the connection body by the wiring structure extending along the whole path between two opposing main surfaces of the base structure. At this opposing other side, a connection to a mounting base may be made.

In an embodiment, a lateral dimension of the electrically conductive wiring structure on one side of the base structure is different to a lateral dimension of the electrically conductive wiring structure remote to the one side of the base structure. More specifically, the electrically conductive wiring structure may spatially increase a dimension (such as a pitch) of the electrically conductive wiring structure on one side of the base structure to a larger dimension (such as a larger pitch) of the electrically conductive wiring structure on an opposing other side of the base structure. Thus, the electrically conductive wiring structure may serve as a redistribution layer. More specifically, the electrically conductive wiring structure may function as an electrically conductive transfer structure serving as an interface between small chip dimensions and larger dimensions of printed circuit board or the like.

In an embodiment, the electrically conductive wiring structure is configured so that at least one edge is formed in an interior of the base structure between one of the at least one vertical wiring section and a connected one of the at least one lateral wiring section. Such an edge may be an interior edge at a concave portion of the wiring structure, for instance in a corner of the wiring structure. However, such an edge may also be an exterior edge at a convex portion of the wiring structure. The combination of vertical and lateral wiring sections of the wiring structure being directly connected with one another in form of one or more edges allows providing wiring structures even for complex electric connection tasks. For instance, the formation of one or more such edges may be advantageous when forming redistribution layers or structures.

In an embodiment, the connection body is free of active components. Active components may denote electronic components able to control current by another electrical signal (for instance transistors, analog integrated circuits or digital integrated circuits). In contrast to this, components which are not able to control current by another electrical signal may be called passive devices (for instance a resistor or a capacitor). While simple passive devices may also be integrated in the interior of the connection body, the connection body itself is preferably free of integrated active components in the described embodiment. Such active components may be surface mounted on the connection body, and may be for example embodied as the one or more electronic chips.

In an embodiment, the electrically conductive wiring structure tapers towards an interior of the base structure. In other words, a lateral extension of the wiring structure in a surface region of the base structure may be larger than in an interior of the base structure.

In an embodiment, the base structure is made of an electrically insulating material. Therefore, electrically conductive paths supported by the connection body may be exclusively defined by the wiring structure. The surrounding base structure however may provide a reliable electric connection. Also for this reason it may be advantageous that the base structure is made of a homogeneous dielectric material.

In an embodiment, the electrically conductive wiring structure is made of a thermally conductive material, in particular a material which has a thermal conductivity of at least 50 W/mK. By configuring the electrically conductive wiring structure from a thermally highly conductive material (such as copper or aluminum), the material of the wiring structure may also contribute to the removal of heat generated during operation of the package and being caused, for instance, by the operation of the one or more electronic chips.

In an embodiment, the package comprises an at least partially electrically conductive carrier on which the electronic chip is mounted. For instance, such a chip carrier may comprise a leadframe and/or a ceramic sheet covered on both opposing main surfaces with a respective metallic layer (in particular a Direct Aluminium Bonding (DAB) substrate and/or a Direct Copper Bonding (DCB) substrate).

In a preferred embodiment, the carrier is however a leadframe. Such a leadframe may be a sheet-like metallic structure which can be patterned so as to form one or more mounting sections for mounting the one or more electronic chips of the package, and one or more lead sections for electric connection of the package to an electronic environment when the electronic chip(s) is/are mounted on the leadframe. In an embodiment, the leadframe may be a metal plate (in particular made of copper) which may be patterned, for instance by stamping or etching. Forming the chip carrier as a leadframe is a cost-efficient and mechanically as well as electrically highly advantageous configuration in which a low ohmic connection of the at least one electronic chip can be combined with a robust support capability of the leadframe. Furthermore, a leadframe may contribute to the thermal conductivity of the package and may remove heat generated during operation of the electronic chip(s) as a result of the high thermal conductivity of the metallic (in particular copper) material of the leadframe. A leadframe may comprise for instance aluminum and/or copper.

In an embodiment, the pad is electrically connected to the carrier by the wiring structure. Thus, the function of the wiring structure may substitute the conventional function of a bond wire, a bond ribbon or a clip. While bond wires or the like need to be assembled one after the other in a serial process and therefore involving a high consumption of time, wiring structures integrated in a base structure of glass or semiconductor oxide material may be connected in a batch process and/or on wafer level for multiple package at the same time. Thus, the parallel connection of multiple electronic chips of multiple packages with the carrier by the wiring structure enables a significantly simplified manufacturing of the packages.

In an embodiment, the wiring structure is composed of multiple connected sections with different shape in different layers. For instance, different sections may have a different ratio between thickness in the thickness direction of the base structure on the one hand and length and/or width in a direction perpendicular to the thickness direction of the base structure on the other hand. The difference dimensions and shapes of the different sections may be easily defined by correspondingly adjusting etch parameters of etching processes etching recesses in the base structure. These recesses may then be filled with electrically conductive material for forming the wiring structure. For instance, adjustable etching parameters may be the shape and size of an etching window in a hard mask, and the etching time (having an impact on the depth of the etching), an etching type (for instance defining a symmetric or asymmetric characteristics of the etching process), etc.

In an embodiment, the connection body is a plate. In particular, a length dimension and/or a width dimension of the connection body may be at least twice of, in particular at least five times of a thickness of the connection body. A multistage etching process for defining multiple connected recesses in a glass or semiconductor oxide based base structure is in particular appropriate for accurately forming various recesses in different depths and dimensions. This allows, in turn, properly defining the wiring structure with the opportunity to even define large ratios between lateral width and thickness. For instance, a ratio between a lateral width and a thickness of the wiring structure can be at least 5, in particular at least 10, more particularly at least 50. This may in particular allow forming a redistribution structure in a compact way.

In an embodiment, the connection body comprises a cavity in which the electronic chip and the pad are arranged so that a hollow space remains between the connection body and the electronic chip. In such an embodiment, the connection body may be directly connected with either only the chip or both the chip and a carrier (if present). The cavity may be dimensioned so as to properly accommodate the chip therein. A connection body with multiple cavities, each for accommodating at least one respective chip, may be advantageously used for a batch manufacturing process for producing multiple packages in parallel.

In an embodiment, the wiring structure delimits part of the cavity. This makes it possible to simultaneously accommodate the chip in the cavity and simultaneously electrically connect the chip pad with the wiring structure of the connection body.

In an embodiment, the electronic chip contains at least one, in particular multiple transistors (such as field-effect transistors, in particular metal oxide semiconductor field-effect transistors).

In an embodiment, the electronic chip comprises a transistor and the pad is a gate pad electrically connected to the wiring structure. In such an embodiment, the electronic chip may be a transistor chip fulfilling a transistor function. Corresponding applications may be from the field of power semiconductor technology. For instance, multiple of such electronic chips of the package may provide a half bridge function, a full bridge function, a converter function, etc.

In an embodiment, the method comprises forming a plurality of recesses having different depths and different lateral extensions in the base structure, and filling the recesses at least partially with electrically conductive material to thereby form the electrically conductive wiring structure. By taking this measure, substantially any desired arrangement of one or more vertical wiring sections and one or more lateral or horizontal wiring sections may be formed with high accuracy and in a simple way.

In an embodiment, the method comprises forming the plurality of recesses by etching the base structure. Glass or semiconductor oxide base structure may be efficiently etched in particular by wet etching.

In an embodiment, the etching comprises carrying out a plurality of etching stages for etching with different depths and different lateral extensions in the base structure. Different etching stages with different etching windows and different etching times may allow manufacturing connected recesses with different lateral and/or vertical dimensions.

In an embodiment, the etching comprises covering the base structure with a multilayer hard mask, exposing a first surface portion of the base structure by removing a first portion of the multilayer hard mask, thereafter etching the exposed first surface portion of the base structure to thereby form a first one of the recesses, exposing a second surface portion of the base structure by removing a second portion of the multilayer hard mask, and thereafter etching the exposed second surface portion of the base structure to thereby form a second one of the recesses. Highly advantageously, a multilayer hard mask may be formed, wherein an opening window of each hard mask layer may define a lateral extension of each individual one of the recesses. By using a stepped multilayer hard mask, a profile of multiple connected recesses in the base structure may be defined which can be translated, by etching, into a sequence of recesses of different vertical and lateral extensions. After filling these recesses, the wiring structure with both vertical and lateral sections can be obtained. It is possible that the described procedure is repeated multiple times.

Preferably, different layers of the multilayer hard mask may be made of different materials. By taking this measure, one or more stop layers may be implemented in the multilayer hard mask.

In an embodiment, the hard mask comprises an alternating sequence of at least two mask layers and at least two stop layers. Thus, for each recess, a set of one assigned mask layer and one assigned stop layer may be foreseen. The alternating procedure of patterning a respective mask layer and stopping the etching process on an assigned stopping layer allows manufacturing recesses of multiple depth and lateral dimensions in a simple and precise way.

In an embodiment, the filling comprises forming a seed layer in one or more of the recesses in the base structure (in particular by sputtering or electroless deposition), and thereafter depositing further electrically conductive material on the seed layer (in particular by plating or galvanic deposition). Seed layer formation may be accomplished by electroless deposition for preparing a subsequent plating or galvanic process. By the combination of a seed layer process with a subsequent galvanic deposition process, it may be possible to significantly increase the efficiency of the filling procedure.

In an embodiment, the method comprises forming the electrically conductive wiring structure in a front side of the base structure, and subsequently thinning the base structure from a back side. In particular, the method may comprise thinning the base structure until the electrically conductive wiring structure is exposed at the back side. Thus, back side thinning after front side plating may allow exposing the buried wiring structure from its back side so that only a thin portion of the base structure needs to be filled with electrically conductive material, and nevertheless an electrically conductive through hole contact may be formed.

In an embodiment, forming the electrically conductive wiring structure comprises connecting two partial base structure bodies with partial wiring structures with one another so that the wiring structure is composed partially by the combination of the connected two partial base structure bodies. In particular, it may be possible to form blind hole type recesses in surface portions of each of the partial base structures and to fill these recesses with electrically conductive material. The two partial base structure bodies may then be connected to one another so that their partial wiring structures are brought in direct physical contact with one another Thinning the obtained body from both sides may then allow obtaining a base structure with very small thickness and a metallic through connection composed of the connected partial wiring structures. Such a manufacturing procedure combines the simple handling of relatively thick base structure bodies with the formation of a precisely defined through connection in form of the wiring structure in a finally very thin base structure.

In an embodiment, the method comprises exposing a front side of the wiring structure by removing material of one of the connected base structure bodies, mounting an electronic chip on the exposed wiring structure, and exposing a back side of the wiring structure by removing material of the other one of the base structure bodies. In particular, the above-mentioned double-sided thinning may be accomplished in a way that after a front side thinning, chip mounting may be carried out before back side thinning.

In an embodiment, the method comprises, before exposing the back side, protecting the electronic chip by a protection structure. Thus, the—in many cases sensitive—electronic chip can be protected during back side thinning by the protection structure. For instance, the protection structure may be a lid or cap covering the electronic chip during back side thinning. It is also possible that the protection structure is a coating of the electronic chip on the front side.

In an embodiment, the method comprises, after exposing the back side, removing the protection structure. Thus, the protection structure may be a temporary protective structure which is removed before completing formation of the package. In other words, the protection structure does not form part of the readily manufactured package in the described embodiment.

In an embodiment, the method comprises electrically connecting the wiring structure with the electronic chip by soldering. Additionally or alternatively, the method comprises mounting the electronic chip on a carrier, in particular by soldering. Soldering is a simple and straightforward procedure of establishing the mentioned electrically conductive connection.

As substrate or wafer forming the basis of the electronic chip(s), a semiconductor substrate, preferably a silicon substrate, may be used. Alternatively, a silicon oxide or another insulator substrate may be provided. It is also possible to implement a germanium substrate or a III-V-semiconductor material. For instance, exemplary embodiments may be implemented in GaN or SiC technology.

Furthermore, exemplary embodiments may make use of standard semiconductor processing technologies such as appropriate etching technologies (including isotropic and anisotropic etching technologies, particularly plasma etching, dry etching, wet etching), patterning technologies (which may involve lithographic masks), deposition technologies (such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), sputtering, etc.).

The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings, in which like parts or elements are denoted by like reference numbers.

