CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application Nos. 10-2019-0139770 and 10-2020-0052247, filed on Nov. 4, 2019 and Apr. 29, 2020, respectively, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present disclosure relates to a semiconductor device and a method of fabricating the same, and in particular, to a semiconductor device including a field effect transistor and a method of fabricating the same.

Due to their small-size, multifunctional, and/or low-cost characteristics, semiconductor devices are considered important elements in the electronics industry. Semiconductor devices are classified into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices including both of memory and logic elements. As the electronics industry advances, there is an increasing demand for semiconductor devices with improved characteristics. For example, there is an increasing demand for semiconductor devices with high reliability, high performance, and/or multiple functions. To meet this demand, complexity and/or integration density of semiconductor devices are being increased.

SUMMARY

An embodiment of the inventive concept provides a semiconductor device, in which field effect transistors with improved electric characteristics are provided, and a method of fabricating the same.

According to an embodiment of the inventive concept, a method of fabricating a semiconductor device may include placing a standard cell. The standard cell may include a first lower interconnection pattern, a second lower interconnection pattern, a lower power pattern, a first upper interconnection pattern, a second upper interconnection pattern, an upper power pattern, a first via pattern between the first lower interconnection pattern and the first upper interconnection pattern, a second via pattern between the second lower interconnection pattern and the second upper interconnection pattern, and a third via pattern between the lower power pattern and the upper power pattern. A width of the second via pattern may be larger than a width of the first via pattern, and a first width of the third via pattern may be equal to a width of the second via pattern. The method may further include resizing the third via pattern in such a way that the third via pattern has a second width that is different from the width of the second via pattern, and applying different design rules to the second via pattern and the third via pattern, respectively, to perform a routing operation on the standard cell.

According to an embodiment of the inventive concept, a method of fabricating a semiconductor device may include placing an upper power pattern, placing a standard cell on the upper power pattern, placing a power via pattern between the upper power pattern and a lower power pattern of the standard cell, resizing the power via pattern to differentiate the power via pattern from another via pattern, and performing a routing operation on the standard cell.

According to an embodiment of the inventive concept, a semiconductor device may include a logic cell, which includes an active pattern and a gate electrode crossing the active pattern and extending in a first direction, on a substrate, a first metal layer on the logic cell, and a second metal layer on the first metal layer. The first metal layer may include a lower interconnection line, which is electrically connected to at least one of the active pattern and the gate electrode, and a lower power line, which is provided on a boundary of the logic cell and is extended in a second direction. The second metal layer may include an upper interconnection line, which is electrically connected to the lower interconnection line, an upper power line, which is electrically connected to the lower power line, an upper via between the lower interconnection line and the upper interconnection line, and an upper power via between the lower power line and the upper power line. A metal layer, which has the largest volume among the upper power via, may include a metallic material different from a metal layer, which has the largest volume among the upper via.

