BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to memory circuits. In particular, the present invention relates to high-density, ferroelectric random-access memory arrays including memory cells provided in a 3-dimensional configuration.

2. Discussion of the Related Art

An erase operation in a 3-dimensional non-volatile memory circuits (e.g., NAND-type flash memory circuits) is typically carried out on a block-by-block basis, which involves a long access time. Such memory circuits are not suitable for use in high speed (˜50 ns), high density storage class memory (SCM) applications.

Other alternative memory circuits, for example, include:(i) 3D XPoint memory circuits, jointly developed by Intel Corporation and Micron Corporation, while allowing bit-by-bit access that is suitable for SCM applications, use cross-point patterning (i.e., double exposures for patterning each material layer), which is prohibitively high in manufacturing cost. Also, such 3D XPoint memory circuits are based on a phase-change material (PCM), which results in high leakage currents and, hence, high power dissipation from sneak paths. Selector devices are needed to reduce the leakage currents from sneak paths, which increase the complexity of process and device integration.(ii) U.S. Pat. Nos. 10,249,370, 10,121,554, 10,121,553, and 9,892,800 disclose 3-dimensional vertical NOR-type memory string arrays, which require complicated X and Y patterning schemes. Due to NOR architecture, the power consumption is also high.

Ferroelectric memory circuits provide yet another alternative. U.S. Pat. No. 6,067,244 to T. Ma, entitled “Erroelectric Dynamic Random Access Memory, filed on Sep. 16, 1998, discloses a ferroelectric field-effect transistor (FeFET) that can serve as a memory circuit, as dipole moments in the FeFET can be aligned in either one of two configurations by an electric field. However, conventional ferroelectric materials, such as those based on lead zirconate titanate (PZT) and strontium bismuth tantalate (SBT), for example, do not provide high-density memory circuits. This is because the ferroelectric layer in an FeFET based on these materials must at least 70 nm thick.

FeFETs based on Hafnium oxide (HfO2) are, however, promising. U.S. patent application publication 2018/0366547A1 (“Liu”) discloses various examples of FeFETs. For example,FIGS. 2aand 2b, reproduced respectively fromFIG. 4AandFIG. 4Bin Liu's disclosure, illustrate the programmed states of exemplary FeFET 1.

As shown in bothFIGS. 2aand 2b, FeFET 1 is formed on a p−-type substrate10and includes n+-type source and drain regions101and102, respectively, channel region103, tunneling dielectric layer13, charge storage region12and gate electrode11. Charge region12includes ferroelectric layer120and paraelectric layer121. Paraelectric layer121has a “quantum well” energy band structure, which enables a charge-trapping capability suitable for a data storage application. Paraelectric layer121may have, for example, alternating layers of a base material and a dielectric material. The base material may be, for example, Hf1-xSixO2—x being a value between 0.02 and 0.65, while the dielectric material may be selected from the group consisting of hafnium oxide, zirconium oxide, titanium oxide, titanium nitride, tantalum nitride, aluminum oxide, tantalum oxide and any combination thereof. The alternating layers of base and dielectric materials may be formed using, for example, ALD processes.

Ferroelectric layer120may include an alkaline earth metal oxide or a transition metal oxide, such as hafnium oxide, zirconium oxide or hafnium zirconium oxide, with or without a 2-10% dopant selected from the group consisting of silicon, aluminum, yttrium, strontium, gadolinium, lanthanum and any combination thereof. One example of a ferroelectric material is Hf1-xSixO2, x ranging between 0.01 and 0.05. The composite material may also include hydrogen atoms in the manufacturing process. Liu discloses that the charge storage region12may be 1.0-30.0 nm thick, preferably 5.0-15.0 nm thick.

As shown inFIG. 2a, when a positive bias (e.g., Vt) is applied to gate electrode11, the electric dipoles in the ferroelectric layer12align with the electric field, such that electrons in channel region103tunnel through tunnel dielectric layer13into and are trapped in paraelectric layer121. The trapped charge causes positive charge carriers (i.e., holes) to accumulate in channel region103(“0” state, which provides a polarization switching voltage for the storage transistor). In this “0” state, FeFET 1 is non-conducting at the read voltage.

As shown inFIG. 2b, when a negative bias (e.g., −Vt) is applied to gate electrode11, the electric dipoles in charge storage region12allow holes in channel region103to tunnel to and be trapped in paraelectric layer121. The trapped charge cause electron accumulation at channel region103(“1” state, which provides a negative polarization switching voltage). In this “1” state, FeFET 1 conducting at the read voltage.

Liu also discloses that the ferroelectric layer120and paraelectric layer121need not be distinct. The ferroelectric layer120and paraelectric layer121may be provided as a single layer as a blend of the ferroelectric and paraelectric materials.

As disclosure in Liu, a hafnium oxide-based FeFET may be made with a ferroelectric layer that is less than 10 nm thick. Furthermore, such an FeFET may provide a 1-volt threshold-shift window. For example, the article, entitled “Low-Leakage-Current DRAM-Like Memory Using a One-Transistor Ferroelectric MOSFET With a Hf-Based Gate Dielectric” (“Cheng”), by C. Cheng and A. Chin, published inIEEE Electronic Device Letters, vol. 35. No. 1, 2014, pp. 138-140, disclose a high-endurance FeFET with a 30 nm thick zirconium-doped HfO2ferroelectric layer that can be programmed or erase in 5 ns.

FIG. 1ashows an architecture of an AND-type FeFET array that can be laid out in a conventional 4F2configuration.FIG. 1aalso provides a table that shows the voltage biases for the word line (WL(m), the source line (SL(m)) and the bit line (BL(m)) of a selected FeFET, as well as the voltage biases for the word line (WL(m+1), the source line (SL(m+1)) and the bit line (BL(m+1)) of a non-selected FeFET, during program, erase and read operations. In Cheng, for example, the programming voltage Vpmgand the read voltage Vreadfor such an FeFET may be −4.0 volts and −0.1 volts, respectively.

FIG. 1bshows an architecture of a NOR-type FeFET array.FIG. 1balso provides a table that shows the voltage biases for the word line (WL(m), the source line (SL(m)) and the bit line (BL(m)) of a selected FeFET, as well as the voltage biases for the word line (WL(m+1), the source line (SL(m+1)) and the bit line (BL(m+1)) of a non-selected FeFET, during program, erase and read operations.

SUMMARY

The present invention provides a 3-dimensional vertical memory string array that includes high-speed ferroelectric field-effect transistor (FET) cells that are low-cost, low-power, or high-density and suitable for SCM applications. The memory circuits of the present invention provide random-access capabilities.

According to one embodiment of the present invention, a memory string formed above a planar surface of substrate includes: (a) a vertical gate electrode (e.g., tungsten or a heavily doped semiconductor) extending lengthwise along a vertical direction relative to the planar surface, (b) a ferroelectric layer provided over at least a portion of the gate electrode along a horizontal direction substantially parallel the planar surface and extending lengthwise along the vertical direction; (c) a gate oxide layer provided over at least a portion of the ferroelectric layer along the horizontal direction and extending lengthwise along the vertical direction; (d) a channel layer provided over at least a portion of the gate oxide layer along the horizontal direction and extending lengthwise along the vertical direction; and conductive semiconductor regions embedded in and isolated from each other by an oxide layer arrayed along the horizontal direction, wherein the gate electrode, the ferroelectric layer, the channel layer, the gate oxide layer and each adjacent pair of semiconductor regions from a storage transistor of the memory string, and wherein the adjacent pair of semiconductor regions serve as source and drain regions of the storage transistor. In addition, a barrier layer (e.g., titanium nitride, tungsten nitride or tantalum nitride) may be provided between the gate electrode and the ferroelectric layer. The drain or source region may also be provided drain or source electrodes (e.g., tungsten or n+polysilicon).

The memory strings of the present invention may be organized into a memory array, and a staircase configuration provides electrical contacts to each of the source or drain electrodes. Storage transistors may be provided on opposite sides of each memory hole in which the gate, the ferroelectric layer, the gate oxide layer and the channel silicon layer are provided. One or more networks of global word line conductors each connecting the gate electrodes of a selected group of the memory strings may be provided above the memory array, below the memory array or both.

The ferroelectric layer comprises a zirconium-doped or silicon-doped HfO2ferroelectric material. The zirconium-doped hafnium silicon oxide may have a zirconium content of 40-60%, preferably 45-55%. The silicon-doped hafnium silicon oxide may have a silicon content of 2.0-5.0%, preferably 2.5-4.5%. The hafnium silicon oxide is prepared by depositing HfO2and SiO2or ZrO2using an ALD layer-by-layer lamination step.

In one embodiment the memory string further includes a charge-trapping layer that is between the gate oxide layer and the ferroelectric layer or between the ferroelectric layer and the barrier layer.

Various manufacturing processes, some of which are illustrated herein, may be used to fabricate a memory array of the memory strings of the present invention.

The present invention is better understood upon consideration of the detailed description below in conjunction with the accompanying drawings.

