BACKGROUND

1. Technical Field

The present invention relates to a drive circuit, a drive method, and a semiconductor system.

2. Related Art

In the related art, for a drive circuit of a semiconductor device such as a power semiconductor, a circuit including a circuit that detects an error such as an overcurrent is known (for example, see Patent Literatures 1 to 3).

[Patent Literature 1] Japanese Patent Application Publication No. H08-330929 (JP-H08-330929A)

[Patent Literature 2] Japanese Patent Application Publication No. 2010-62860 (JP-2010-62860A)

[Patent Literature 3] Japanese Patent Application Publication No. 2015-159471 (JP-2015-159471A)

The drive circuit has a low side control section that operates at a relatively low voltage, and a high side drive section that operates at a relatively high voltage. An error detection signal generated by the high side drive section is transmitted to the low side control section via a level shift circuit. In order to surely input the error detection signal to the low side control section, it is preferable that the high side drive section continue to output the error detection signal for a certain period. However, when the error detection signal is continuously output, power consumption in the level shift circuit increases.

In order to solve the above problem, a first aspect of the present invention provides a drive circuit of a semiconductor device. The drive circuit may include a control section that generates a control signal in accordance with an input signal. The drive circuit may include a first level shift section that raises a level of a signal from the control section. The drive circuit may include a high side drive section that controls the semiconductor device based on the control signal of which the level has been raised by the first level shift section. The drive circuit may include a second level shift section that lowers a level of a signal from the high side drive section for input to the control section. The high side drive section may have an error detection section that outputs an error detection signal when the semiconductor device is in an error status, and maintains the output of the error detection signal until a release signal is input. The control section may have an error handling section that outputs the release signal to the high side drive section via the first level shift section when the error detection signal is input via the second level shift section. The error detection section may stop the output of the error detection signal when the release signal is input.

The high side drive section may have a drive control section that drives the semiconductor device based on the control signal of which the level has been raised. The drive control section may control the semiconductor device to be in Off-state when the error detection section outputs the error detection signal.

The control section may have a control signal generation section that generates, in accordance with the input signal, the control signal which causes the semiconductor device to transition to On-state or Off-state. When the error detection signal is input, the error handling section may set a status of the control signal to be a status which causes the semiconductor device to transition to the Off-state, the control signal being generated as the release signal by the control signal generation section. When the control signal is in the status which causes the semiconductor device to transition to the Off-state, the error detection section may stop the output of the error detection signal.

The control signal generation section may generate the control signal which includes a set pulse signal having a pulse indicating a timing for causing the semiconductor device to transition to the On-state, and a reset pulse signal having a pulse indicating a timing for causing the semiconductor device to transition to the Off-state. The high side drive section may have a first latch section that receives the set pulse signal and the reset pulse signal, levels of the set pulse signal and the reset pulse signal having been raised by the first level shift section, and generates the control signal of which a logical value transitions in accordance with pulse timings of the set pulse signal and the reset pulse signal. The control signal output by the first latch section may be input to the error detection section.

The high side drive section may have a periodic pulse generation section that converts, for input to the second level shift section, the error detection signal output by the error detection section into an error detection pulse signal having a periodic pulse. The control section may have a second latch section that latches the error detection pulse signal for input to the error handling section.

The first level shift section may have a control signal shift circuit that raises a level of the control signal. The first level shift section may have a release signal shift circuit that raises a level of the release signal.

A second aspect of the present invention provides a semiconductor system including: a semiconductor device; and the drive circuit according to the first aspect, the drive circuit controlling the semiconductor device.

A third aspect of the present invention provides a drive method of driving a semiconductor device using a drive circuit including: a control section that generates a control signal in accordance with an input signal; a first level shift section that raises a level of a signal from the control section; a high side drive section that controls the semiconductor device based on the control signal of which the level has been raised by the first level shift section; and a second level shift section that lowers a level of a signal from the high side drive section for input to the control section. The drive method may include outputting an error detection signal when the semiconductor device is in an error status, and maintaining the output of the error detection signal until a release signal is input in the high side drive section as an error detection step. The drive method may include outputting the release signal to the high side drive section via the first level shift section when the error detection signal is input via the second level shift section in the control section as an error handling step. The drive method may include stopping the output of the error detection signal when the release signal is input to the error detection section as an error output stop step.

The summary clause does not necessarily describe all necessary features of the embodiments of the present invention. The present invention may also be a sub-combination of the features described above.

