FIELD OF THE INVENTION

The present invention relates to the field of integration and, more particularly, to electronic products, related semiconductor products, and their methods of manufacture.

The present invention more precisely relates to electronic components comprising electrodes such as capacitors.

TECHNICAL BACKGROUND

Electronic components such as capacitors may be integrated into semiconductor products in a variety of forms. For example, planar capacitors may be formed above semiconductor substrates by forming two planar electrodes separated by a dielectric layer. However planar capacitors provide low capacitance density, this implies that a high value capacitance will consume a significant area of silicon.

To overcome this issue, it has been proposed to form three-dimensional structures to increase the capacitance of a capacitor using the same surface area of the semiconductor substrates. Capacitance densities of the order of a Farad per m2have been achieved using three-dimensional capacitors. Fabrication of three-dimensional capacitors has been made possible through the introduction of manufacturing methods that form high aspect ratio structures such as Deep Reactive Ion Etching, better known under the acronym DRIE.

Initially, it has been proposed to form a matrix of deep holes in a silicon substrate. These holes could have openings of the order of 1 micrometer and a depth of up to 17 micrometers. The silicon in which the holes are formed is doped (either before the formation of holes or after in a deposition/diffusion process) so that the walls, the bottoms, and the top of the holes form a first electrode. A dielectric layer is deposited in a conformal manner and a second electrode is also deposited in a conformal manner so as to fill the holes and form a capacitor.

While this structure is particularly robust (in terms of mechanical robustness), it is also limited by the etching rates of the processes used to form the holes. This is caused by the reduced etching apertures and prevents the formation of deeper holes in an economical manner.

An alternative structure has been proposed in which bottom electrodes are formed in the shape of silicon pillars. In other words, the structure is a negative of the structure comprising holes.

The etching rate is consequently improved, but it has been observed that the mechanical robustness of this structure is poor as the pillars may bend prior to the deposition of the dielectric and of the upper electrode. Bent pillars may come into contact with each other and stick to each other. This generates process issues that can decrease capacitance density, increase the capacitor leakage current and even degrade the breakdown voltage by generating early failures.

Prior art document U.S. Pat. No. 8,283,750 discloses known three-dimensional capacitor structures using pillars with improved robustness so as to reduce sticking between pillars. There pillars may have three protrusions so that their cross-section is in the shape of a tripod.

The solutions of document U.S. Pat. No. 8,283,750 merely allow obtaining pillars having an aspect ratio of about 30 (the aspect ratio may be defined as the length of a pillar divided by the smallest cross-sectional dimension measured perpendicularly to its length direction). It has been observed that greater aspect ratios still lead to bended pillars and too much sticking.

Documents US 2011/244302 and WO 2007/125510 also disclose known pillar structures.

The present invention has been made in the light of the above problems.

SUMMARY OF THE INVENTION

The present invention provides an electronic product comprising a component having a first electrode comprising a first surface and a pillar extending from the first surface in a first direction, the pillar comprising three protrusions, the three protrusions forming angles of about 120 degrees with each other around a central line of the pillar where the three protrusions meet, and the three protrusions being bent in the same direction so that the pillar has a triskelion cross-section in a plane perpendicular to the first direction.

A triskelion is a shape comprising three legs or three branches (the protrusions of the invention) curved in the same direction (for example clockwise or counterclockwise) around a center (here the central line of the pillar where the three protrusions meet).

By way of example, triskelions are often used as Celtic symbols (with spiral legs).

The inventors of the present invention have observed that by bending the protrusions emerging from a pillar, the mechanical robustness of the pillar is improved and this prevents bending of the pillar.

The choice of the triskelion shape (with three bends oriented similarly) provides the following advantages: a compact structure is obtained, which allows maintaining the surface area of the first electrode, and this structure can be arranged in a matrix without loss of space between the structures, thus maintaining a high capacitance density.

According to a particular embodiment, the pillar has an aspect ratio greater than 60, or preferably greater than 100.

It has been observed that aspect ratios of 60 or 100 can be achieved using pillars having cross-sections in the shape of a triskelion, while the methods of the prior art lead to too much sticking at an aspect ratio of 50.

It should be noted that the aspect ratio of a pillar according to the present invention may be mainly limited by the cost of realizing deep structures (time/gaz), the uniformity of doping steps, the uniformity of subsequent dielectric depositions, the wafer warpage (after the filling of the deep trenches), and by the final die thickness (the final die thickness may be lower than 100 micrometers). It should be noted that an aspect ratio is, in the present description, the length of a pillar (measured in the first direction—or the depth of a trench delimiting a pillar) divided by the smallest cross-sectional dimension measured perpendicularly to its length direction (for example the width of a trench between two protrusions or two pillars).

According to a particular embodiment, the protrusions each comprise three segments each having the same length (or approximately the same length) and joined by angles of about 120 degrees.

It has been observed that this arrangement facilitates placing the pillar in a matrix of pillars.

According to a particular embodiment, the electronic product comprises a plurality of pillars, each central line of a pillar being arranged at a vertex of a planar equilateral triangular tessellation formed in a plane perpendicular to the first direction.

This arrangement of pillars is very advantageous as regards the surface area of the first electrode. This arrangement is possible because a triskelion arrangement has a substantially triangular shape.

It has been observed that the arrangement of the pillars in a matrix also participates in reducing wafer warpage or limits stress because the structure of each extends in three directions and comprises bends. This limits the amount of parallel linear trenches aligned in the same direction which may cause significant wafer warpage.

According to a particular embodiment, the pillars each have the same orientation.

The pillars are all extending in the first direction and the protrusions of each pillar are arranged so that this same orientation is obtained. This facilitates the arrangement in a matrix and increases the surface area of the electrodes (for example the first electrodes).

According to a particular embodiment, the smallest distance between two parallel segments of protrusions of adjacent pillars is approximately equal to the smallest distance between two parallel segments of protrusions of a same pillar.

In this embodiment, the protrusions of the pillars comprise segments.

This smallest distance (between two parallel segments of two adjacent pillars or between two parallel segments of a same pillar) may be the distance known to the skilled person as the critical dimension (for example the critical dimension of a DRIE step).

This embodiment is advantageous regarding the conformity of the subsequent deposition of materials. For example, if a capacitor is formed, a dielectric will be deposited in a conformal manner and a second electrode will also be deposited in a conformal manner. This ensures that there will be no large spaces between the pillars to be filled with a filling material.

According to a particular embodiment, the protrusions are formed of segments each having a width equal to said smallest distance (i.e. the smallest distance between two parallel segments of two adjacent pillars or between two parallel segments of a same pillar).

According to a particular embodiment, the cross section of the pillar is the same along the entire length of the pillar in the first direction.

According to a particular embodiment, the pillar has a length which is greater than 60 micrometers.

According to a particular embodiment, the first electrode is a first electrode of a capacitor of the electronic product.

In other words, a dielectric layer may be deposited on the first electrode, for example in a conformal manner, and a second electrode may be deposited on the dielectric layer.

The invention also provides a system comprising an electronic product as defined above.

The invention also provides a method for fabricating an electronic component as defined above.

By way of example, this method may comprise a DRIE step to form the pillar(s). Also, a photolithography step using a mask defining the triskelion-shape of the cross-section of the pillars may also be carried out in this method.

