TECHNICAL FIELD

The present invention relates to an image capturing apparatus and an image capturing method, in particular, to those that capture images using a high speed image sensor.

BACKGROUND ART

In the past, high speed video cameras that can capture images at high speeds have been known. For example, a video camera has accomplished high speed image capturing by converting an image size per one image to be processed at a high speed rate into ¼ of the standard image size and placing these four images in an image of the regular rate (see Patent Document “Japanese Patent Application Laid-Open Publication No. HEI 8-88833”). Another video camera has accomplished high speed image capturing using a circuit structure that processes data received from a sensor in parallel so as to increase a process amount per unit time (see Patent Document “Japanese Patent Application Laid-Open Publication No. HEI 8-251492”).

However, the high speed image capturing described in Patent Document “Japanese Patent Application Laid-Open Publication No. HEI 8-88833” or Patent Document “Japanese Patent Application Laid-Open Publication No. HEI 8-251492” was aimed to temporarily store a captured image in a storage device such as a VTR or a semiconductor memory, reproduce the captured image in slow motion, and analyze a very high speed motion and the device itself had a complicated structure and was expensive. Thus, it was difficult to apply high speed image capturing systems as described in Patent Document 1 or Patent Document 2 to portable image capturing devices that have been widespread as home-use devices, so-called camcorders (product names of devices in which a video camera and a recorder are integrated in one unit), digital cameras, and so forth from view points of portability and power consumption.

With reference toFIG. 1, an image capturing apparatus designed taking account of such points will be described. The structure shown inFIG. 1has the same structure as that of an existing camcorder. In other words, an image capturing apparatus100shown inFIG. 1includes an image sensor101, a pre-processing circuit102, a camera signal processing circuit103, a conversion processing section104, a compression and decompression circuit105, a memory control circuit106, a memory107, a display processing circuit108, a compression and decompression circuit109, a recording device control circuit110, a recording device111, a display section112, and a control section113.

The image sensor101can select a high speed image capturing mode in which the image sensor101reads a signal at a first screen rate (also referred to as frame rate) of 60 fps (fields/second) or more based on the NTSC specifications or a regular image capturing mode in which the image sensor101reads a signal at a regular second screen rate. The screen rate in the high speed image capturing mode is 240 fps that is four times higher than that of the regular rate. The image sensor101is equipped with a CDS (Correlated Double Sampling) and an A/D converter and the image sensor101outputs captured image data.

The pre-processing circuit102performs an optically correcting process such as a shading correction for captured image data that are output from the image sensor101and outputs a digital image signal. The camera signal processing circuit103performs a camera signal process such as a white balance adjustment process for the captured image data that are received from the pre-processing circuit102.

The conversion processing section104performs a display decimation and a size adjustment to convert an image signal received from the camera signal processing circuit103into an image signal having a screen rate and a screen size suitable for a display of the display section112. The display decimation is performed only when an image signal received from the camera signal processing circuit103is output to the display processing circuit108. The display decimation decimates the number of fields per unit time of the image signal captured by the image capturing apparatus100in the high speed image capturing mode to the number of fields per unit time defined in the display standard of the display device (60 fps in this case).

The compression and decompression circuit105performs a compression-encoding process for captured image data received from the conversion processing section104according to a still image encoding system, for example, JPEG (Joint Photographic Experts Group) or the like. In addition, the compression and decompression circuit105performs a decompression-decoding process for encoded data of a still image supplied from the memory control circuit106. The memory control circuit106controls writing and reading image data to and from the memory107. The memory107is a FIFO (First In First Out) type buffer memory that temporarily stores image data received from the memory control circuit106and, for example, an SDRAM (Synchronous Dynamic Random Access Memory) or the like is used for the memory107.

The display processing circuit108generates an image signal to be displayed on the display section112from an image signal received from the conversion processing section104or the compression and decompression circuit109, supplies the signal to the display section112, and causes it to display an image. The display section112is composed, for example, of an LCD (Liquid Crystal Display) and displays a camera-through image that is being captured or a reproduced image of data that have been recorded in the recording device111.

The compression and decompression circuit109performs a compression-encoding process according to a moving image encoding system, for example, MPEG (Moving Picture Experts Group) or the like for image data received from the conversion processing section104. In addition, the compression and decompression circuit109performs a decompression-decoding process for encoded data of a moving image supplied from the recording device111and outputs the resultant data to the display processing circuit108. The display section112displays a moving image received from the display processing circuit108.

The control section113is a microcomputer composed, for example, of a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and so forth and totally controls each section of the image capturing apparatus by executing programs stored in the ROM and so forth.

In the image capturing apparatus shown inFIG. 1, in the high speed image capturing mode, a captured image signal of 240 fps received from the image sensor101is supplied to the camera signal processing circuit103through the pre-processing circuit102. The conversion processing section104decimates an output image signal of the camera signal processing circuit103by ¼ so that an output signal of 60 fps is obtained. The decimated and size-converted image signal is supplied to the display processing circuit108. The display processing circuit108generates an image signal to be displayed on the display section112, supplies the resultant image signal to the display section112, and causes it to display an image.

When receiving a record request of a high speed captured image from the control section113according to the user's operation, the conversion processing section104sends an image signal of 240 fps to the compression and decompression circuit105. If necessary, the conversion processing section104reduces the size of the image signal received from the camera signal processing circuit103and sends the image signal to the compression and decompression circuit105.

The compression and decompression circuit105compression-encodes the image signal received from the conversion processing section104according to the JPEG format. The memory control circuit106temporarily stores encoded data received from the compression and decompression circuit105into the memory107. In such a manner, image data for a predetermined period are stored in the memory107.

When receiving a read request for encoded data stored in the memory107from the control section113, the memory control circuit106reads the encoded data stored in the memory107at 60 fps and sends the encoded data to the compression and decompression circuit105. The compression and decompression circuit105decompression-decodes the encoded data received from the memory control circuit106and sends the decoded data to the conversion processing section104. When receiving a record request for the recording device111from the control section113, the conversion processing section104sends the image signal received from the compression and decompression circuit105to the compression and decompression circuit109. The compression and decompression circuit109compresses the image signal received from the conversion processing section104according to the MPEG format and stores the compression-encoded signal to the recording device111through the recording device control circuit110. The conversion processing section104adjusts the size of the image signal of 60 fps received from the compression and decompression circuit105, sends the resultant image signal to the display processing circuit108, and causes display section112to display a reproduced image.

In the foregoing proposed image capturing apparatus shown inFIG. 1, in the high speed image capturing mode of the image sensor101, since the screen rate of the output captured signal is high, the pre-processing circuit102and the camera signal processing circuit103are required to operate at a high speed. If the system is accomplished by an LSI or the like, since the calculation scales of the pre-processing circuit102and the camera signal processing circuit103are large in the whole system, a high speed process or a parallel process is not advantageous from the view point of circuit area and power consumption. Moreover, in the structure shown inFIG. 1, since a captured image signal was temporarily stored in the memory107, there was a problem that after the high speed image capturing mode was stopped, it took a process time to decode data temporarily stored in the memory107and to re-encode the data according to the regular record format.

DISCLOSURE OF THE INVENTION

Therefore, an object of the present invention is to provide an image capturing apparatus and an image capturing method that do not need to cause a camera signal processing circuit to perform a process at a high speed screen rate and that are easy to operate, are produced at low cost, and thereby have excellent portability.

To solve the foregoing problems, the present invention is an image capturing apparatus, comprising:record medium control means for recording captured image data having a first screen rate obtained from a solid state image capturing device to a record medium and reading captured image data having a second screen rate which is lower than the first screen rate from the record medium;conversion means for converting the captured image data having the first screen rate obtained from the solid state image capturing device into the captured image data having the second screen rate;camera signal processing means for performing a camera signal process for the captured image data having the second screen rate obtained from the conversion means or the record medium control means; anddisplay processing means for generating an image signal to be displayed from an image signal obtained from the camera signal processing means.

The present invention is an image capturing apparatus, comprising:record medium control means for recording captured image data having a first screen rate obtained from a solid state image capturing device to a record medium and reading captured image data having a second screen rate which is lower than the first screen rate from the record medium;conversion means for converting the captured image data having the first screen rate obtained from the solid state image capturing device into the captured image data having the second screen rate;first camera signal processing means for performing a camera signal process for the captured image data having the second screen rate obtained from the conversion means;second camera signal processing means for performing a camera signal process for the captured image data having the second screen rate obtained from the record medium control means; anddisplay processing means for generating an image signal to be displayed from an image signal obtained from either the first and second camera signal processing means,wherein the first camera signal processing means is simply structured in comparison with the second camera signal processing means.

The present invention is an image capturing apparatus, comprising:first record medium control means for recording captured image data having a first screen rate obtained from a solid state image capturing device to a first record medium and reading captured image data having a second screen rate which is lower than the first screen rate from the record medium;conversion means for converting the captured image data having the first screen rate obtained from the solid state image capturing device into the captured image data having the second screen rate;first camera signal processing means for performing a camera signal process for the captured image data having the second screen rate obtained from the conversion means;second camera signal processing means for performing a camera signal process for the captured image data having the second screen rate obtained from the first record medium control means;second record medium control means for recording an output image signal of the second camera signal processing means to a second record medium and reading an image signal from the record medium at the second screen rate; anddisplay processing means for generating an image signal to be displayed from either an output image signal obtained from the first camera signal processing means or an output image signal of the second record medium control means,wherein the first camera signal processing means is simply structured in comparison with the second camera signal processing means.

The present invention is an image capturing method, comprising:a record medium control step for recording captured image data having a first screen rate obtained from a solid state image capturing device to a record medium and reading captured image data having a second screen rate which is lower than the first screen rate from the record medium;a conversion step for converting the captured image data having the first screen rate obtained from the solid state image capturing device into the captured image data having the second screen rate;a camera signal processing step for performing a camera signal process for the captured image data having the second screen rate obtained from the conversion step or the record medium control step; anda display processing step for generating an image signal to be displayed from an image signal obtained from the camera signal processing step.

The present invention is an image capturing method, comprising:a record medium control step for-recording captured image data having a first screen rate obtained from a solid state image capturing device to a record medium and reading captured image data having a second screen rate which is lower than the first screen rate from the record medium;a conversion step for converting the captured image data having the first screen rate obtained from the solid state image capturing device into the captured image data having the second screen rate;a first camera signal processing step for performing a camera signal process for the captured image data having the second screen rate obtained from the conversion step;a second camera signal processing step for performing a camera signal process for the captured image data having the second screen rate obtained from the record medium control step; anda display processing step for generating an image signal to be displayed from an image signal obtained from either the first and second camera signal processing step,wherein the first camera signal processing step is simply structured in comparison with the second camera signal processing step.

The present invention is an image capturing method, comprising:a first record medium control step for recording captured image data having a first screen rate obtained from a solid state image capturing device to a first record medium and reading captured image data having a second screen rate which is lower than the first screen rate from the record medium;a conversion step for converting the captured image data having the first screen rate obtained from the solid state image capturing device into the captured image data having the second screen rate;a first camera signal processing step for performing a camera signal process for the captured image data having the second screen rate obtained from the conversion step;a second camera signal processing step for performing a camera signal process for the captured image data having the second screen rate obtained from the first record medium control step;a second record medium control step for recording an output image signal of the second camera signal processing step to a second record medium and reading an image signal from the record medium at the second screen rate; anddisplay processing step for generating an image signal to be displayed from either an output image signal obtained from the first camera signal processing step or an output image signal of the second record medium control step,wherein the first camera signal processing step is simply structured in comparison with the second camera signal processing step.

In the image capturing apparatus according to the present invention, although a screen rate of an image capturing device is high, a camera signal processing circuit is needed to always satisfy only a screen rate according to the display performance of a display section. Thus, it is not necessary to perform a high frequency drive and a parallel process only for high speed image capturing and thereby power consumption and circuit scale can be reduced.

