This application claims priority to GB Patent Application No. 2003235.5 filed Mar. 5, 2020, the entire contents of each of which are hereby incorporated by reference.

BACKGROUND

The present technique relates to an apparatus and method for performing branch prediction.

An apparatus may comprise processing circuitry for executing a sequence of instructions, and often the processing circuitry is arranged in a pipelined arrangement, so that at any point in time a number of instructions can be in the process of being executed within the various stages of the pipeline. The instructions to be executed by the processing circuitry may be fetched from memory by fetch circuitry and then passed through the pipeline for execution by the processing circuitry. Some of the instructions fetched may be branch instructions, and execution of such a branch instruction may cause a discontiguous change in program flow if the branch is taken, whereas if the branch is not taken the next instruction to be executed will be the instruction immediately following the branch instruction in the memory address space.

Typically the fetch circuitry operates ahead of the processing circuitry with the aim of providing the processing pipeline with a steady stream of instructions for execution by the processing circuitry. Branch prediction circuitry can be provided in association with the fetch circuitry to predict whether, for a fetched branch instruction, the branch will be taken or not taken when that branch instruction is subsequently executed by the processing circuitry, with that prediction then being used to determine the subsequent instructions fetched by the fetch circuitry.

It is desirable for the predictions made to be as accurate as possible, as when the prediction is incorrect it will in due course be necessary to flush the incorrectly fetched instructions from the pipeline, which can have a significant performance impact.

SUMMARY

In one example arrangement, there is provided an apparatus comprising: processing circuitry to execute instructions; fetch circuitry to fetch the instructions for execution by the processing circuitry, the fetch circuitry being arranged, when encountering a branch instruction, to determine subsequent instructions to be fetched in dependence on an initial branch direction prediction for the branch instruction made by branch prediction circuitry; value prediction circuitry to maintain a predicted result value for one or more instructions; dispatch circuitry to maintain a record of pending instructions that have been fetched by the fetch circuitry and are awaiting execution by the processing circuitry, and to select pending instructions from the record for dispatch to the processing circuitry; wherein when a given instruction whose predicted result value is maintained by the value prediction circuitry has a dependent instruction whose outcome is dependent on a result value of the given instruction, and the dependent instruction is in the record of pending instructions, the dispatch circuitry is arranged to enable speculative execution of the dependent instruction by the processing circuitry using the predicted result value of the given instruction; and analysis circuitry arranged, when the dependent instruction is the branch instruction, to detect a mispredict condition when an additional branch direction prediction for the branch instruction determined using the predicted result value for the given instruction is considered more accurate than the initial branch direction prediction, and the additional branch direction prediction differs to the initial branch direction prediction, and on detection of the mispredict condition to issue a control signal to indicate that the branch instruction has been mispredicted.

In another example arrangement, there is provided a method of performing branch prediction comprising: employing processing circuitry to execute instructions; fetching the instructions for execution by the processing circuitry, and when encountering a branch instruction during the fetching, determining subsequent instructions to be fetched in dependence on an initial branch direction prediction for the branch instruction made by branch prediction circuitry; employing value prediction circuitry to maintain a predicted result value for one or more instructions; maintaining a record of pending instructions that have been fetched and are awaiting execution by the processing circuitry, and selecting pending instructions from the record for dispatch to the processing circuitry; when a given instruction whose predicted result value is maintained by the value prediction circuitry has a dependent instruction whose outcome is dependent on a result value of the given instruction, and the dependent instruction is in the record of pending instructions, enabling speculative execution of the dependent instruction by the processing circuitry using the predicted result value of the given instruction; when the dependent instruction is the branch instruction, detecting a mispredict condition when an additional branch direction prediction for the branch instruction determined using the predicted result value for the given instruction is considered more accurate than the initial branch direction prediction, and the additional branch direction prediction differs to the initial branch direction prediction; and on detection of the mispredict condition, issuing a control signal to indicate that the branch instruction has been mispredicted.

In a still further example arrangement, there is provided an apparatus comprising: processing means for executing instructions; fetch means for fetching the instructions for execution by the processing means, the fetch means, when encountering a branch instruction, for determining subsequent instructions to be fetched in dependence on an initial branch direction prediction for the branch instruction made by branch prediction means; value prediction means for maintaining a predicted result value for one or more instructions; dispatch means for maintaining a record of pending instructions that have been fetched by the fetch means and are awaiting execution by the processing means, and for selecting pending instructions from the record for dispatch to the processing circuitry; wherein when a given instruction whose predicted result value is maintained by the value prediction means has a dependent instruction whose outcome is dependent on a result value of the given instruction, and the dependent instruction is in the record of pending instructions, the dispatch means is arranged to enable speculative execution of the dependent instruction by the processing means using the predicted result value of the given instruction; and analysis means for detecting, when the dependent instruction is the branch instruction, a mispredict condition when an additional branch direction prediction for the branch instruction determined using the predicted result value for the given instruction is considered more accurate than the initial branch direction prediction, and the additional branch direction prediction differs to the initial branch direction prediction, and on detection of the mispredict condition for issuing a control signal to indicate that the branch instruction has been mispredicted.

