CROSS-REFERENCE TO RELATED APPLICATION

This application is a Section 371 of International Application No. PCT/CN2018/075271, filed Feb. 5, 2018, which was published in the Chinese language on Aug. 16, 2018 under International Publication No. WO 2018/145612 A1, which claims priority under 35 U.S.C. § 119 to Chinese Patent Application No. 201710067159.9, filed on Feb. 7, 2017, the disclosures of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Technical Field

The invention relates to the technical field of integrated circuits, in particular to a low-voltage and wide-output range charge pump circuit and a phase-locked loop.

2. Description of Related Art

As one of the most popular frequency synthesizer structures in modern wireless communication system applications, a phase locked loop (PLL) can realize signal modulation and demodulation, as well as clock recovery, and generate local oscillator signals for carrier recovery of a mixer and a wireless receiver. A charge pump phase-locked loop (CP-PLL) has become the most common phase-locked loop circuit due to the characteristics of high speed and low noise. A charge pump (CP) circuit plays a very important role in a charge pump phase-locked loop. The main function of the charge pump circuit is to convert UP and DN pulse digital signals from a phase frequency detector (PFD) into analog voltage signals through a low-pass filter (LPF), and the analog voltage signals control the oscillation frequency of a voltage control oscillator (VCO). Therefore, the charge pump circuit has a very important influence on the characteristics of the whole phase-locked loop.

In a traditional circuit structure realizing the match of the charging current and the discharging current of a charge pump circuit, an operational amplifier circuit is used to hold the voltage between different nodes, which not only increases the complexity of the circuit, but also brings certain hidden dangers to the overall stability of the circuit. Meanwhile, in order to realize a large output voltage swing, the structure of an operational amplifier needs to realize rail-to-rail input and output characteristics, which further increases the design difficulty of the operational amplifier. Moreover, an operational amplifier working at low voltages often has low operating frequencies and cannot be applied to high-frequency fields.

BRIEF SUMMARY OF THE INVENTION

In view of this, it is necessary to provide a charge pump circuit and a phase-locked loop which can realize the match of the charging current and the discharging current of a charge pump within a wide output voltage range without providing an additional operational amplifier and have simple circuit structure.

A charge pump circuit comprises a start module, a bias module, a current mirror module, a charging and discharging feedback control module and a charging and discharging matching module which are electrically connected in sequence; wherein

the start module is used for starting the bias module;

the bias module is used for generating constant bias current and outputting same to the current mirror module;

the current mirror module is used for receiving the bias current, and amplifying the bias current and outputting the amplified bias current in two paths;

the charging and discharging feedback control module is used for detecting the output voltage of a charge pump and controlling, according to the feedback of the output voltage, the charging current or the discharging current in the charging and discharging matching module, so as to suppress the mismatch between the charging current and the discharging current; and

the charging and discharging matching module is used for receiving an external charging control signal or an external discharging control signal, so as to charge or discharge the output load of the charge pump.

In one embodiment, the start module comprises transistors M1, M2, and M3, wherein the transistor M1and the transistor M3form a phase inverter, a source of the transistor M1and a source of the transistor M2are connected to a power end, and a drain of the transistor M1is connected to a gate of the transistor M2and then to a drain of the transistor M3; a gate of the transistor M1is connected to a gate of the transistor M3, and a source of the transistor M3is grounded; and the gate of the transistor M1and a drain of the transistor M2are connected to the bias module.

In one embodiment, the bias module comprises transistors M4, M5, M6, M7, M8, M9, and M10, wherein a source of the transistor M4, a source of the transistor M5, and a source of the transistor M10are all connected to the power end; a gate of the transistor M4is connected to a gate of the transistor M5; a drain of the transistor M4is connected to a gate of the transistor M4, the start module, a drain of the transistor M6, and a gate of the transistor M10; a drain of the transistor M5is connected to a drain of the transistor M7and a gate of the transistor M7; a gate of the transistor M6is connected to the gate of the transistor M7; a source of the transistor M6is connected to a drain of the transistor M8; a source of the transistor M7is connected to a drain of the transistor M9, a gate of the transistor M9, and the start module; a source of the transistor M8and a source of the transistor M9are both grounded; and a drain of the transistor M10is connected to a current mirror circuit.

In one embodiment, the bias module further comprises resistors R1, R2, and R3, wherein the source of the transistor M8is grounded via the resistor R1, and the resistors R2and R3are grounded in parallel and are pseudo resistors of the resistor R1.

In one embodiment, the current mirror module comprises transistors M11, M12, M13, M14, M15, M16, M17, M18, and M19, wherein a source of the transistor M11, a source of the transistor M12, a source of the transistor M15, a source of the transistor M16, and a source of the transistor M17are all grounded; a source of the transistor M13, a source of the transistor M14, a source of the transistor M18, and a source of the transistor M19are all connected to the power end; a drain of the transistor M11is connected to a gate of the transistor M11and the bias module; a gate of the transistor M11is connected to a gate of the transistor M12; a drain of the transistor M12is connected to a drain of the transistor M13and a gate of the transistor M13; the gate of the transistor M13is connected to a gate of the transistor M14; a drain of the transistor M14is connected to a drain of the transistor M15, a gate of the transistor M15, and a gate of the M17; the gate of the transistor M15is connected to a gate of the transistor M16; a drain of the transistor M16is connected to a drain of the transistor M18and a gate of the transistor M18; the gate of the transistor M18is connected to the gate of the transistor M19; and a drain of the transistor M17and a drain of the transistor M19are connected to the charging and discharging matching module.

In one embodiment, the charging and discharging matching module comprises a charging unit and a discharging unit, wherein the charging unit receives the bias current in one of the paths output from the current mirror module, and outputs the charging current according to the charging control signal to charge an output load of the charge pump; and the discharging unit receives the bias current in another of the paths output from the current mirror module, and outputs the discharging current according to the discharging control signal to discharge the output load of the charge pump.

In one embodiment, the charging unit comprises transistors M20, M21, M22, M23, and M24, wherein a source of the transistor M20, a drain and a source of the transistor M21, and a source of the transistor M22are all connected to the power end; a gate of the transistor M20is grounded, and a drain of the transistor M20is connected to a source of the transistor M23and the charging and discharging feedback control module; a gate of the transistor M21is connected to a gate of the transistor M23and a gate of the transistor M24; a gate of the transistor M22receives the charging control signal, and a drain of the transistor M22is connected to a source of the transistor M24; a drain of the transistor M23is connected to a gate of the transistor M23and the current mirror module; and a drain of the transistor M24is connected to the output load of the charge pump.

The discharging unit comprises transistors M25, M26, M27, M28, and M29, wherein a drain of the transistor M25is connected to a gate of the transistor M25and the current mirror module; a gate of the transistor M25is connected to a drain of the transistor M25, a gate of the transistor M26, and a gate of the transistor M28; a source of the transistor M25is connected to a drain of the transistor M27and the charging and discharging feedback control module; a drain of the transistor M26is connected to the output load of the charge pump, and a source of the transistor M26is connected to a drain of the transistor M29; a gate of the transistor M27is connected to the power end, and a source of the transistor M27, a source and a drain of the transistor M28, and a source of the transistor M29are all grounded; and a gate of the transistor M29receives the discharging control signal.

In one embodiment, the charging and discharging feedback control module comprises a charging feedback unit and a discharging feedback unit; the charging feedback unit is connected to the charging unit and the output load of the charge pump; the charging feedback unit is used for detecting the output voltage of the charge pump and controlling, according to the feedback of the output voltage, the discharging current output by the discharging unit, so as to suppress the mismatch between the charging current and the discharging current; the discharging feedback unit is connected to the discharging unit and the output load of the charge pump; and the discharging feedback unit is used for detecting the output voltage of the charge pump and controlling, according to the feedback of the output voltage, the charging current output by the charging unit, so as to suppress the mismatch between the charging current and the discharging current.

In one embodiment, the charging feedback unit comprises a transistor M30, and the discharging feedback unit comprises a transistor M31, wherein a source of the transistor M30is connected to the power end, a drain of the transistor M30is connected to the charging unit, and a gate of the transistor M30is connected to the output load of the charge pump; and a source of the transistor M31is grounded, a drain of the transistor M31is connected to the discharging unit, and a gate of the transistor M31is connected to the output load of the charge pump.

The above charge pump circuit comprises the start module, the bias module, the current mirror module, the charging and discharging feedback control module and the charging and discharging matching module which are electrically connected in sequence, According to the detected output voltage of the charge pump, the charging current or the discharging current in the charging and discharging matching module can be controlled by a charging feedback circuit; so as to suppress the mismatch between the charging current and the discharging current, thus maintaining the match of the charging current and the discharging current of the charge pump within a wide output voltage range. Meanwhile, the charge pump circuit in the embodiment of the invention has a simple structure and is suitable for a low-voltage working environment.

In addition, the invention provides a phase-locked loop which comprises the charge pump circuit.

