CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2020-0010018, filed on Jan. 28, 2020, which is incorporated herein by reference in its entirety.

BACKGROUND

Field of Invention

Various embodiments of the present disclosure relate to an electronic device, and more particularly, to a semiconductor memory device.

Description of Related Art

Generally, a memory device may have a two-dimensional structure in which strings are horizontally arranged on a semiconductor substrate, or a three-dimensional structure in which strings are vertically stacked on a semiconductor substrate. The three-dimensional memory device has been devised to overcome a limitation in the degree of integration of the two-dimensional memory device, and may include a plurality of memory cells which are vertically stacked on a semiconductor substrate.

SUMMARY

Various embodiments of the present disclosure are directed to a semiconductor memory device capable of programming a drain select transistor of a cell string.

An embodiment of the present disclosure may provide for a semiconductor memory apparatus including a cell string and a page buffer. The cell string may include a drain select transistor coupled with a bit line, and memory cells coupled with the drain select transistor. The page buffer may be coupled to the cell string through the bit line. The page buffer may include a latch and a first current path. The latch may store data of a value indicative of a result of a threshold voltage verification on the drain select transistor. The first current path may set a voltage of the bit line to a program inhibit voltage, based on the value of the data stored in the latch.

An embodiment of the present disclosure may provide for a semiconductor memory apparatus including a cell string, a latch, a bit line select transistor, a page buffer sensing transistor, a power supply transistor, and a voltage select circuit. The cell string may include a drain select transistor, and memory cells coupled with the drain select transistor. The latch may store data of a value indicative of a result of a threshold voltage verification on the drain select transistor. The bit line select transistor may be coupled to the drain select transistor. The page buffer sensing transistor may be coupled between the bit line select transistor and a first node. The power supply transistor may be coupled between a power supply and the first node. The voltage select circuit may supply a voltage of the power supply. The power supply transistor may be selectively turned on based on the value of the data stored in the latch so that the voltage of the power supply is supplied to the bit line as a program inhibit voltage.

An embodiment of the present disclosure may provide for a semiconductor memory apparatus including a cell string, a voltage supply circuit, a first control circuit and a second control circuit. The cell string includes a drain select transistor coupled to a bit line discharged before an initial period. The voltage supply circuit is configured to supply a first voltage during the initial period and a second voltage during a verify period. The first control circuit is configured to keep, when a threshold voltage of the drain select transistor is outside a range, the bit line discharged during the initial period. The second control circuit is configured to charge, when the threshold voltage is within the range, the bit line with the first voltage during the initial period and configured to charge the bit line with the second voltage during the verify period.

