PRIORITY DATA

The present application is a utility application of provisional U.S. patent application 62/905,850, filed on Sep. 25, 2019, entitled “Multi-Step Metal-Fill for Contact Via”, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.

For example, as the source/drain vias become smaller with each technology generation, electrical resistance attributed to the source/drain vias may increase. Such an increase in electrical resistance is undesirable since it may degrade device performance such as speed. Therefore, although conventional methods of forming source/drain vias have generally been adequate, they have not been satisfactory in all aspects.

