BACKGROUND

1. Technical Field

Embodiments of the present disclosure relate to semiconductor devices performing a write operation using an error correction code.

2. Related Art

Recently, a DDR2 scheme or a DDR3 scheme receiving and outputting four-bit data or eight-bit data during each clock cycle time has been used to improve an operation speed of semiconductor devices. If data transmission speeds of semiconductor devices become faster, the probability of errors occurring while the data are transmitted in the semiconductor devices increases. Accordingly, advanced design schemes have been proposed to improve the reliability of the data transmission.

Whenever data are transmitted in semiconductor devices, error codes which are capable of detecting occurrence of errors may be generated and transmitted with the data to improve the reliability of data transmission. The error codes may include an error detection code (EDC) which is capable of detecting errors and an error correction code (ECC) which is capable of correcting the errors by itself.

SUMMARY

In accordance with an embodiment of the present disclosure, a semiconductor device includes an error correction circuit and a write operation control circuit. The error correction circuit is configured to generate corrected data and an error flag from read data according to whether an error is included in the read data outputted when a read operation is performed. The write operation control circuit is configured to generate a write control signal for controlling a write operation based on the error flag. The write control signal is generated based on information about pads receiving pad data and information about a burst length when no error is included in the read data.

In accordance with another embodiment of the present disclosure, a semiconductor device includes a column decoding circuit, a mask control circuit, and a write control signal generation circuit. The column decoding circuit is configured to generate a pre-decoded signal from a write strobe pulse based on an error flag, a bit change signal, and a burst change signal. The mask control circuit is configured to generate a decoded signal from the pre-decoded signal based on the error flag and a data mask signal. The write control signal generation circuit is configured to generate a write control signal from the decoded signal during a time period when a write operation is performed.

