BACKGROUND

During manufacture, semiconductor chips (also commonly referred to as “dies”) are typically mounted on die pads of lead frames and are wire-bonded, clipped, or otherwise coupled to leads of the lead frame. Other devices may similarly be mounted on a lead frame pad. The assembly is later covered in a mold compound, such as epoxy, to protect the assembly from potentially damaging heat, physical trauma, moisture, and other deleterious factors. The finished assembly is called a semiconductor package or, more simply, a package. The leads are exposed to surfaces of the package and are used to electrically couple the packaged chip to devices outside of the chip.

However, other types of packages, commonly known as flip-chip packages, are configured differently than described above. Flip-chip packages include a die, metallic bumps (e.g., solder bumps), and a redistribution layer (RDL) that interfaces between the die and the metallic bumps so that signals are routed appropriately between the bumps and the active circuitry formed on the die. Examples of such flip-chip packages include chip scale packages (CSPs), such as wafer chip scale packages (WCSPs).

SUMMARY

In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.

