This application is the U.S. national phase of International Application No. PCT/GB2016/050978 filed 7 Apr. 2016, which designated the U.S. and claims priority to GB Patent Application No. 1509746.2 filed 5 Jun. 2015, the entire contents of each of which are hereby incorporated by reference.

This disclosure relates to data processing systems. More particularly, this disclosure relates to modal control of hardware to support the execution of program instructions.

It is known to provide data processing systems supporting multiple instruction sets. For example, processing systems as designed by ARM Limited of Cambridge, England may support both the ARM and Thumb instruction sets.

Viewed from one aspect the present disclosure provides apparatus for processing data comprising:

a processor to perform processing operations upon operands stored within a register file of said processor and as specified by program instructions of an instruction set, said processor operating in at least a first mode of operation having a first set of active processing circuitry ready to perform processing operations and a second mode of operation having a second set of active processing circuitry ready to perform processing operations, said second set of active processing circuitry different from said first set of active processing circuitry; wherein

a first proper subset of program instructions within said instruction set are processed by said processor operating in a selectable one of said first mode and said second mode; and

a second proper subset of program instructions within said instruction set are required to be processed by said processor operating in said second mode.

Viewed from another aspect the present disclosure provides apparatus for processing data comprising:

processing means for performing processing operations upon operands stored within a register file of said processor means and as specified by program instructions of an instruction set, said processing means operating in at least a first mode of operation having a first set of active processing means for performing processing operations and a second mode of operation having a second set of active processing means for performing processing operations, said second set of active processing means different from said first set of active processing means; wherein

a first proper subset of program instructions within said instruction set are processed by said processing means operating in a selectable one of said first mode and said second mode; and

a second proper subset of program instructions within said instruction set require to be processed by said processing means operating in said second mode.

Viewed from a further aspect the present disclosure provides a method of processing data comprising:

performing processing operations upon operands stored within a register file of a processor and as specified by program instructions of an instruction set using at least a first mode of operation having a first set of active processing circuitry for performing processing operations and a second mode of operation having a second set of active processing circuitry for performing processing operations, said second set of active processing circuitry different from said first set of active processing circuitry; wherein

a first proper subset of program instructions within said instruction set are processed using a selectable one of said first mode and said second mode; and

a second proper subset of program instructions within said instruction set require to be processed using said second mode.

