RELATED APPLICATIONS

This application is a National Phase of PCT Patent Application No. PCT/CN2019/117112 having International filing date of Nov. 11, 2019, which claims the benefit of priority of Chinese Patent Application No. 201911020554.7 filed on Oct. 25, 2019. The contents of the above applications are all incorporated by reference as if fully set forth herein in their entirety.

FIELD AND BACKGROUND OF THE INVENTION

The present disclosure relates to a technical field of display panels, and more particularly to an array substrate and manufacturing method thereof.

Flat panel display devices have advantages of having thin bodies, being power saving, and having no radiation, have been widely used. Existing flat panel display devices mainly include liquid crystal displays (LCDs) or organic light emitting diode displays (OLED). Array substrates are important components of flat panel display devices. Array substrates can be formed on glass substrates or plastic substrates. Array substrates are generally used as light-emitting devices or driving devices for LCDs or OLEDs, etc.

As resolutions of display panels are raised and sizes of display panels increase, a signal delay phenomenon becomes more serious. It is urgently desired to decrease wiring resistance. Copper (Cu) is second only to silver (Ag) in conductivity. Raw material of Cu is inexpensive. Cu is considered to be the most promising low-resistivity wiring material. In related art, Cu material is used as material of gate electrodes of thin film transistors (TFTs).

In advanced generation liquid crystal panels, using Cu material instead of conventional aluminum to serve as gate electrode metal lines has become a trend because Cu material have advantages such as low impedance and high electromigration resistance. As panel sizes are enlarged and resolutions are increased, using common Cu wire thickness of 3000 Å to solve problems such as circuit delay becomes harder and harder. Therefore, one direction for solving the problems is to increase thickness of Cu wires.

As thickness of Cu wires increases, because of step coverage problems, increase of thickness of Cu film layers in gate electrode structures cause thickness of gate electrode insulating layers to increase. In this way, ON-state current of array substrates is decreased, thereby increasing risks of insufficient panel charging rates.

Hence, it is desired to develop a novel array substrate manufacturing method to overcome deficiencies in the related art.

SUMMARY OF THE INVENTION

Technical problems are as follows.

An object of the present disclosure is to provide an array substrate that can solve a problem that thickness of a gate electrode insulating layer is increased due to increase of a thickness of a copper (Cu) film in a gate electrode structure.

Technical solutions are as follows.

In order to achieve the aforementioned object, the present disclosure provides an array substrate including: a substrate; a first gate electrode insulating layer disposed on the substrate, wherein the first gate electrode insulating layer has a recess therein; a gate electrode layer disposed in the recess of the first gate electrode insulating layer; a second gate electrode insulating layer covering the first gate electrode insulating layer and the gate electrode layer; and an active layer disposed on the second gate electrode insulating layer.

Further, in other embodiments, the array substrate further includes: a source or drain electrode layer disposed on the active layer; a planarization layer disposed on the source or drain electrode layer; and a pixel defined layer disposed on the planarization layer.

Further, in other embodiments, the gate electrode layer has a Cu material. A range of a thickness of the gate electrode layer is from 200 nm to 5000 nm.

Further, in other embodiments, each of the first gate electrode insulating layer and the second gate electrode insulating layer has at least one or at least two of a corresponding nitrogen oxide material, a corresponding silicon oxide material, and a corresponding silicon nitride material. A range of a thickness of the first gate electrode insulating layer is from 100 nm to 500 nm, and a range of a thickness of the second gate electrode insulating layer is from 100 nm to 500 nm.

Further, in other embodiments, the active layer has at least one or at least two of a zinc oxide material, an indium zinc oxide material, and an indium zinc gallium oxide material. A range of a thickness of the active layer is from 100 nm to 200 nm.

Further, in other embodiments, the planarization layer has a silicon oxide material or a silicon nitride material. A range of a thickness of the planarization layer is from 150 nm to 400 nm. The pixel electrode layer has an indium tin oxide material. A range of a thickness of the pixel electrode layer is from 30 nm to 100 nm.

Further, in other embodiments, the substrate has a polyimide material.

Further, in other embodiments, the source or drain electrode layer has an aluminum material, a molybdenum material, or a combination thereof. A range of a thickness of the source or drain electrode layer is from 20 nm to 600 nm.

In order to achieve the aforementioned object, the present disclosure further provides a method of manufacturing the array substrate including:

a step S1of providing a substrate; a step S2of depositing a gate electrode insulating material on the substrate to form a first gate electrode insulating film; a step S3of patterning the first gate electrode insulating film to form a first gate electrode insulating layer, wherein the first gate electrode insulating layer has a recess therein; a step S4of depositing a gate electrode material on the first gate electrode insulating layer, and forming a gate electrode film in the recess; a step S5of wet etching the gate electrode film to remove the gate electrode film on the first gate electrode insulating layer, and form a gate electrode layer in the recess; a step S6of depositing a gate electrode insulating material on the first gate electrode insulating layer and the gate electrode layer to form a second gate electrode insulating layer; and a step S7of forming an active layer on the second gate electrode insulating layer.

The gate electrode insulating layers are manufactured in two steps, thereby lowering a risk of worse step coverage caused by one-step manufacturing for related art.

The thickness of the second gate electrode insulating layer is related to electrical characteristics of the array substrate. By controlling a ratio of the thickness of the first gate electrode insulating layer and the thickness of the second gate electrode insulating layer, an ON-state current of the array substrate is ensured not to decrease, thereby lowering a risk of an insufficient panel charging rate.

Further, in other embodiments, in the step S2and the step S6, the gate electrode insulating material is deposited using a plasma enhanced chemical vapor deposition method.

Further, in other embodiments, before the step S6, the method further includes a step S100of processing the first gate electrode insulating layer using at least one or at least two of hydrogen, nitrogen, ammonia, and argon. Through the step S100, it is ensured that no fault occurs between the first gate electrode insulating layer and the second gate electrode insulating layer, and that optical characteristics of a pixel region do not worsen.

Further, in other embodiments, after the step S7, the method further includes: a step S8of forming a source or drain electrode layer on the active layer; a step S9of forming a planarization layer on the source or drain electrode layer; and a step S10of forming a pixel electrode layer on the planarization layer.

Advantageous effects are as follows.

Compared to the related art, the advantageous effects of the present disclosure are as follows. The present disclosure provides the array substrate and manufacturing method thereof. The gate electrode insulating layers are manufactured in two steps, thereby lowering the risk of the worse step coverage caused by the one-step manufacturing for the related art. The thickness of the second gate electrode insulating layer is related to the electrical characteristics of the array substrate. By controlling the ratio of the thickness of the first gate electrode insulating layer and the thickness of the second gate electrode insulating layer, the ON-state current of the array substrate is ensured not to decrease, thereby lowering the risk of the insufficient panel charging rate.

