FIELD

This Disclosure relates to integrated circuits (ICs) and packaged devices including at least one IC including plastic packages.

BACKGROUND

There are known to be parametric shifts, drifts and variations for packaged devices that include at least one IC that comprises stress sensitive circuitry due to package stress, and more specifically mold compound induced stress. As examples, for precision analog devices, which is one example type of stress sensitive circuitry, package stress can result in a higher non-linearity in case of precision analog to digital converters (ADCs), higher offset voltage or offset voltage drift in case of amplifiers, and lower accuracy and higher noise for reference circuits. Precision analog devices often include matching circuits, but not always, such as in the cases of references and bandgap circuits which may not be matching circuit-based. Although gradient cancelation techniques such as at test trim (implemented either at the IC/wafer level or at package level test) are known that can be used to minimize these performance problems, such performance problems still tend to show up as unit-to-unit between a population of packaged device units, variability such as across temperature, post-operating life or reliability stress, and a resulting degraded performance and corresponding lower performance specification for the packaged device.

One known packaged device arrangement comprises flipchip on leadframe (FCOL). For FCOL, the top side of an IC generally comprising a silicon substrate and having solder capped pillars on its bond pads is bonded to the leads or lead terminals of the leadframe for providing both the thermal and electrical connections directly from the substrate of the IC to the leadframe.

SUMMARY

This Summary is provided to introduce a brief selection of disclosed concepts in a simplified form that are further described below in the Detailed Description including the drawings provided. This Summary is not intended to limit the claimed subject matter's scope.

Disclosed aspects include an IC comprising a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is positioned with at least a majority of its area within an inner area of the substrate framed by the metal wall.

Disclosed aspects also include a packaged device including a disclosed IC. As used herein, the term ‘packaged devices’ include leadframe-based devices including at least one IC that are molded devices, with or without wirebonding such as a FCOL arrangement, where a disclosed packaged device can also optionally include bond wires. The metal wall prevents at least a portion of the mold compound (e.g., at least the filler particles in the mold compound) from entering an inner cavity that comprises the inner area which is framed by the metal wall.

