BACKGROUND

The present invention relates generally to a semiconductor structure and a method of forming the same. More particularly, the present invention relates to a semiconductor structure that includes a low-voltage flash memory integrated with a vertical field effect transistor (VFET).

Deep learning is a machine learning method based on artificial neural networks inspired by information processing in biological systems. In neuromorphic computing, electronic analog circuits are used to mimic neuro-biological architectures present in the nervous system.

SUMMARY

According to one embodiment of the present invention, a circuit is provided. The circuit may include a low-voltage flash memory integrated with a vertical field effect transistor and a non-volatile memory element. The low-voltage flash memory may be coupled to the non-volatile memory element by the vertical field effect transistor, one or more bit-lines, and one or more word-lines. The low-voltage flash memory may provide a lower significance conductance and the non-volatile memory element may provide a higher significance conductance. The low-voltage flash memory may include a source and a drain. The source may be separated from the drain by an epitaxial channel. The low-voltage flash memory may include a floating gate. The floating gate may be separated from the epitaxial channel by a first dielectric layer. The low-voltage flash memory may include a control gate. The control gate may be separated from the floating gate by a second dielectric layer. The low-voltage flash memory may be programmed by applying voltage pulses of opposite polarities to the control gate. The low-voltage flash memory may be programmed by switching off the vertical field effect transistor and applying a program voltage to the control gate of the low-voltage flash memory. The low-voltage flash may be read by turning on the vertical field effect transistor and applying a read voltage to the control gate of the low-voltage flash memory. The source, the drain, and the epitaxial channel may be doped with an n-type dopant. The non-volatile memory element may be a phase-change memory, resistive random access memory, magnetic random access memory, or a flash memory.

According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include a low-voltage flash memory integrated with a vertical field effect transistor and a non-volatile memory element. The low-voltage flash memory may be coupled to the non-volatile memory element by the vertical field effect transistor, one or more bit-lines, and one or more word-lines. The low-voltage flash memory may include a first source drain, a second source drain, a floating gate, and a control gate. The second source drain may be separated from the first source drain by an epitaxial channel. The floating gate may be separated from the epitaxial channel by a first dielectric layer. The control gate may be separated from the floating gate by a second dielectric layer. The floating gate may have a doping type that is opposite to a doping type of the epitaxial channel. The first source drain, the second source drain, and the epitaxial channel may be doped with an n-type dopant. The first dielectric may be made of high-k dielectric material. The low-voltage flash memory may be vertical and may be separated from the vertical field effect transistor by a shallow trench isolation. The non-volatile memory element may be a phase-change memory, resistive random access memory, magnetic random access memory, or a flash memory.

According to another embodiment of the present invention, a method is provided. The method may include forming a low-voltage flash memory integrated with a vertical field effect transistor and a non-volatile memory element. The method may include forming a shallow trench isolation between the low-voltage flash memory and the vertical field effect transistor. The low-voltage flash memory may be coupled to the non-volatile memory element by the vertical field effect transistor. Forming the low-voltage flash memory may include growing a first source drain on a substrate, epitaxially growing an epitaxial channel on the first source drain, epitaxially growing a second source drain on the epitaxial channel, forming a floating gate around the epitaxial channel, and forming a control gate around the floating gate, the control gate being separated from the floating gate by a first dielectric layer. The first dielectric layer may be made of a high-k dielectric material. The first source drain, the epitaxial channel, and the second source drain may be doped with an n-type dopant. The non-volatile memory element may be a phase-change memory, resistive random access memory, magnetic random access memory, or a flash memory. The floating gate may have a doping type that is opposite to a doping type of the epitaxial channel.

