REFERENCE TO RELATED APPLICATION

This Application claims priority to German Application No. 10 2019 103 514.7, filed on Feb. 12, 2019, the contents of which are hereby incorporated by reference in their entirety.

FIELD

The present disclosure relates to radar applications, in particular an efficient way to process radar signals obtained by at least one radar sensor, e.g., via at least one antenna. Processing radar signals in this regard in particular refers to radar signals received by a sensor or an antenna.

BACKGROUND

Several radar variants are used in cars for various applications. For example, radar can be used for blind spot detection (parking assistant, pedestrian protection, cross traffic), collision mitigation, lane change assist and adaptive cruise control. Numerous use case scenarios for radar appliances may be directed to different directions (e.g., back, side, front), varying angles (e.g., azimuth direction angle) and/or different distances (short, medium or long range). For example, an adaptive cruise control may utilize an azimuth direction angle amounting to ±18 degrees, the radar signal is emitted from the front of the car, which allows a detection range up to several hundred meters.

A radar source emits a signal and a sensor detects a returned signal. A frequency shift between the emitted signal and the detected signal (based on, e.g., a moving car emitting the radar signal) can be used to obtain information based on the reflection of the emitted signal. Front-end processing of the signal obtained by the sensor may comprise a Fast Fourier Transform (FFT), which may result in a signal spectrum, i.e. a signal distributed across a range of frequencies. The amplitude of the signal may indicate an amount of echo, wherein a peak may represent a target that needs to be detected and used for further processing, e.g., adjust the speed of the car based on another car traveling in front.

A radar processing device may provide different types of outputs, e.g., a command to a control circuit, an object or an object list to be post-processed by at least one control circuit, and/or at least one FFT peak to be post-processed by at least one control circuit. Utilizing FFT peaks enables high performance post processing.

It is in particular an issue that high speed processing conducted by a signal processing circuit (SPU) may cause power supply current jumps that may disturb the radar units, in particular during a transmission phase via the radar antenna(s).

SUMMARY

At least one problem to be solved, for example, is to overcome the disadvantage stated above and in particular to provide a solution to efficiently process signals in a radar system.

The examples suggested herein may, for example, be based on at least one of the following solutions. For example, combinations of the following features could be utilized in order to reach a desired result. The features of the method could be combined with any feature(s) of the device, apparatus or system or vice versa.

A method for processing a radar signal is disclosed. The method comprises adjusting a processing clock signal, wherein the processing clock signal determines an operation period of a signal processing circuit, wherein the processing clock signal is determined based on a time window. In the method the size of the time window is determined based on the maximum time available for processing a portion of the radar signal, and the end of the time window is determined such that it does not occur during an active transmission portion of the radar system.

The method allows conducting the signal processing at variable speed due to the adjusted processing clock signal. It is thus possible to provide time windows for processing subsequent to each other with no or only little gap between them. Without substantial gaps, there is no disturbing switching on/off between the time windows and therefore little to no disturbance conveyed over power supply lines.

In other words, the signal processing durations are continuously spread and ensure a seamless operation of the radar system by consuming a single DC supply current (instead of current jumps that would otherwise be caused by switching the SPU on and off).

In addition to mitigating the detrimental effect of load jumps, the solution presented herein may be used to efficiently distribute a power that is consumed during an acquisition period. For example, instead of using the SPU running at 100% processing power at 50% of the time, the SPU may be run at 50% processing power during the full time of the acquisition period. This would also avoid reaching high current consumption loads.

According to an embodiment, the start of the time window is determined such that it does not occur during an active transmission portion of the radar system

According to an embodiment, the processing clock signal is adjusted based on a clock signal via a fractional clock divider circuit.

The fractional clock divider circuit is also known as a frequency divider circuit, a clock divider circuit, a scaler circuit or a prescaler circuit. It provides an output frequency foutbased on an input frequency fin as follows: fout=fin/n, wherein n is an integer.

It is an option that this is implemented by a programmable fractional clock divider circuit, which is configured to meet the requirements as defined above. Such configuration may be done one or several times.

The configuration of the fractional clock divider can even be done during operation, i.e. in run time.

According to an embodiment, the portion of the radar signal comprises a transmission portion of the radar signal and/or a receiving portion of the radar signal, each of which, in one embodiment, comprises a ramp of frequencies.

The portion of the radar signal that is subject to the processing may, in one embodiment, be a transmission portion as described herein. The transmission portion may be associated with a radar chip (or any radar unit) that emits and receives radar signals, for example, radar signals of varying frequencies. During the time the radar signals are emitted and/or received by the radar unit, the power supply conveys electrical energy to the radar unit and to the signal processing circuit. If the signal processing circuit is switched on (enabled) or switched off (disabled) during the transmission portion of the radar signal, this will result in a load jump and thus disturb the transmission/reception of the radar signal by the radar unit and thus deteriorates the overall recognition of the radar system.

As suggested, such disturbance can be reduced or avoided if there is no such load jump during the transmission portion or the receiving portion of the radar signal.

According to an embodiment, adjusting the processing clock signal comprises reducing or increasing a cycle rate at which the signal processing circuit is run.

Hence, the speed at which the SPU is run can be adjusted by the fractional clock divider circuit.

According to an embodiment, adjusting the processing clock signal comprises at least one of the following: at the start of the time window, gradually increasing the frequency of the processing clock signal until the frequency of the processing clock signal is reached, and/or at the end of the time window, gradually decreasing the frequency of the processing clock signal until the frequency of the processing clock signal is reached.

Hence, this solution is directed, e.g., to ramping up and/or down the frequency at which the SPU is driven. This is, in one embodiment, useful for the start of the first time window (out of many adjacent time windows) and at the end of the time window (with no adjacent time window of operation for the SPU). Such measure efficiently reduces any voltage overshoot or undershoot towards the power supply and therefore mitigates any potential load jump.

Gradually increasing may be done by ramping up the frequencies towards a processing frequency, which could be the maximum frequency to drive the SPU. It might also be a frequency below the maximum frequency. The ramping up may be realized in discrete steps, which may have same or different lengths/heights. This also applies to ramping down, whereas the ramping up and the ramping down may utilize the same or different ramping patterns.

Also, a radar system is disclosed, and comprises a receiver that is configured to receive a radar signal via an antenna, and a processing circuit. The processing circuit is configured to adjust a processing clock signal. The processing clock signal determines an operation period of the processing circuit, and is determined based on a time window. The size of the time window is determined based on the maximum time available for processing a portion of the radar signal and the end of the time window is determined such that it does not occur during an active transmission portion of the radar system.

According to an embodiment, the processing circuit comprises a signal processing circuit.

Also, a vehicle is suggested comprising at least one radar system as described herein.

Further, a computer program product such as a non-transitory computer readable storage medium is provided, which is directly loadable into a memory of a digital processing device, comprising software code portions for performing the steps of the method as described herein.

Embodiments are shown and illustrated with reference to the drawings. The drawings serve to illustrate the basic principle, so that only aspects necessary for understanding the basic principle are illustrated. The drawings are not to scale. In the drawings the same reference characters denote like features.

