BACKGROUND

Processing systems receive data and commands from applications and input/output (I/O) devices at registers and other storage modules. As next generation processing systems are developed, an important design consideration is providing compatibility with older applications and I/O devices. For example, data and commands generated by an application could conflict with new functionality, thereby negatively impacting user experience. In addition, bug fix workarounds may need to set or clear register bits. Data can be manipulated at runtime using firmware or flash microcode to ensure backward compatibility. However, if data is manipulated using firmware, for each register write, the firmware applies an address test to determine if a potential modification of the data is needed and perform the modification if necessary. This requires multiple clock cycles, and the number of clock cycles needed increases with the number of addresses that must be checked. Thus, analyzing data while a program is running to reset or clear register bits in firmware or flash microcode is time intensive, and exacts a performance penalty that can potentially negatively impact the user experience.

