TECHNICAL FIELD

The present disclosure relates to a semiconductor device and a method for fabricating the semiconductor device, and more particularly, to a semiconductor device with alleviation features for reducing capacitive coupling between conductive features and the method for fabricating the semiconductor device with the alleviation features.

DISCUSSION OF THE BACKGROUND

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular telephones, digital cameras, and other electronic equipment. The dimensions of semiconductor devices are continuously being scaled down to meet the increasing demand of computing ability. However, a variety of issues arise during the scaling-down process, and such issues are continuously increasing. Therefore, challenges remain in achieving improved quality, yield, performance, and reliability and reduced complexity.

This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.

SUMMARY

One aspect of the present disclosure provides a semiconductor device including a substrate, a first conductive line positioned on the substrate and extend along a first direction, a first conductive line spacer positioned on a sidewall of the first conductive line, a bottom contact positioned adjacent to the first conductive line, a bottom contact spacer positioned on a sidewall of the bottom contact, an air gap positioned between the first conductive line spacer and the bottom contact spacer, and a second conductive line positioned above the bottom contact and extend along a second direction different from the first direction.

In some embodiments, a distance between the first conductive line spacer and the bottom contact spacer is less than one-fourth of a line width of the first conductive line.

In some embodiments, a sum of a thickness of the first conductive line spacer and a thickness of the bottom contact spacer is equal to or greater than one-half of a distance between the first conductive line and the bottom contact.

In some embodiments, the semiconductor device includes two impurity regions respectively correspondingly positioned below the first conductive line and the bottom contact. The two impurity regions are formed of silicon phosphide, phosphorus-doped silicon carbon, silicon carbide, silicon germanium, silicon-germanium-tin alloy, or silicon-germanium-boron alloy.

In some embodiments, the semiconductor device includes a word line structure positioned between the two impurity regions.

In some embodiments, each of the two impurity regions includes an upper portion positioned adjacent to the word line structure and a lower portion positioned below the upper portion and the upper portion has a tapering cross-sectional profile.

In some embodiments, the upper portion of each of the two impurity regions includes a top surface substantially coplanar with a top surface of the substrate and two tapering sidewalls connected to the top surface and an angle between one of the two tapering sidewalls and the top surface is between about 45 degree and about 60 degree.

In some embodiments, a thickness of the upper portion of each of the two impurity regions is equal to or less than one-fifth of a thickness of each of the two impurity regions.

In some embodiments, the word line structure includes a word line dielectric layer contacting the lower portion of the impurity region, a word line electrode positioned on the word line dielectric layer, and a word line capping layer positioned on the word line electrode.

In some embodiments, the word line dielectric layer has a thickness between about 10 angstroms and about 30 angstroms.

In some embodiments, the bottom contact includes a bottom contact barrier layer and a bottom contact conductive layer positioned on the bottom contact barrier layer. The bottom contact spacer is positioned on a sidewall of the bottom contact barrier layer and a sidewall of the bottom contact conductive layer.

In some embodiments, the bottom contact barrier layer is a stacked layer including a bottom layer formed of titanium and a top layer formed of titanium nitride.

In some embodiments, the bottom contact conductive layer is a stacked layer including a bottom layer formed of tungsten nitride and a top layer formed of tungsten.

In some embodiments, the semiconductor device includes a top contact positioned between the bottom contact and the second conductive line.

In some embodiments, the top contact includes a first conductive layer positioned on the bottom contact, a second conductive layer positioned on the first conductive layer, and a third conductive layer positioned on the second conductive layer.

In some embodiments, the first conductive layer is formed of doped polysilicon, the second conductive layer is formed of metal silicide and has a thickness between about 2 nm and about 20 nm, and the third conductive layer is formed of metal or metal nitride.

Another aspect of the present disclosure provides a semiconductor device including a substrate, a first conductive line positioned on the substrate and extend along a first direction, a first conductive line spacer positioned on a sidewall of the first conductive line, a bottom contact positioned adjacent to the first conductive line, a bottom contact spacer positioned on a sidewall of the bottom contact, and a porous insulating layer positioned between the first conductive line spacer and the bottom contact spacer. A porosity of the porous insulating layer is between about 25% and about 100%.

In some embodiments, the porous insulating layer is positioned on a sidewall of the first conductive line spacer and a sidewall of the bottom contact spacer.

Another aspect of the present disclosure provides a method for fabricating a semiconductor device including providing a substrate, concurrently forming a first conductive line and a bottom contact on the substrate, concurrently forming a first conductive line spacer on a sidewall of the first conductive line and a bottom contact spacer on a sidewall of the bottom contact, forming a first insulating layer over the substrate and concurrently forming an air gap between the first conductive line spacer and the bottom contact spacer.

In some embodiments, the method for fabricating the semiconductor device includes a step of forming two impurity regions in the substrate and below the first conductive line and the bottom contact. The two impurity regions are formed of silicon phosphide, phosphorus-doped silicon carbon, silicon carbide, silicon germanium, silicon-germanium-tin alloy, or silicon-germanium-boron alloy.

Due to the design of the semiconductor device of the present disclosure, the parasitic capacitance between conductive feature such as the first conductive line and the two bottom contacts may be reduced by the alleviation feature like the plurality of air gaps or the porous insulating layer. Therefore, the performance of the semiconductor device may be improved. In addition, the upper portions of the plurality of impurity regions having tapering cross-sectional profile may provide an extra process tolerance for formation of contact thereon. Hence, the yield of fabrication of the semiconductor device may be improved.

The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

