CROSS REFERENCE TO RELATED APPLICATIONS

This application is the National Stage of PCT/CN2018/072063 filed on Jan. 10, 2018, which claims priority under 35 U.S.C. § 119 of Chinese Application No. 201710525756.1 filed on Jun. 30, 2017, the disclosure of which is incorporated by reference.

TECHNICAL FIELD

Embodiments of the present disclosure relate to a display device, a power supply circuit and a power supply method.

BACKGROUND

When a current leakage failure or a short-circuit failure occurs in a display device, power-off protection is generally performed. The display device can be protected by the power-off protection so that the data being processed is not lost or the function is not damaged. However, the power-off protection may cause that the subsequent detection of the display device cannot be performed.

SUMMARY

According to one aspect of the present disclosure, at least one embodiment provides a power supply circuit, comprising: a control sub-circuit, configured to provide a first preset voltage and a second preset voltage and output the first preset voltage to a first power supply terminal; and a delay sub-circuit, configured to delay the second preset voltage and output the delayed second preset voltage to a second power supply terminal

In addition, according to an embodiment, the control sub-circuit is a power chip; the power chip comprises a first output terminal and a second output terminal, the first output terminal is configured to provide the first preset voltage, and the second output is configured to provide the second preset voltage, the first output terminal is used as the first power supply terminal; and the delay sub-circuit comprises an input terminal and an output terminal, the input terminal is connected to the second output terminal of the power chip, the output terminal of the delay sub-circuit is connected to the second power supply terminal to delay the second preset voltage provided by the power chip and output the delayed second preset voltage to the second power supply terminal, the first power supply terminal is connected to a first power receiving terminal of a display screen, and the second power supply terminal is connected to a second power receiving terminal of the display screen.

In addition, according to an embodiment, the delay sub-circuit comprises: a first switch transistor, a second switch transistor, and a voltage division and delay sub-circuit. A control terminal of the first switch transistor is connected to the input terminal of the delay sub-circuit, and a first terminal of the first switch transistor is grounded; a first terminal of the second switch transistor is connected to the input terminal of the delay sub-circuit, and a second terminal of the second switch transistor is connected to the output terminal of the delay sub-circuit; a first terminal of the voltage division and delay sub-circuit is connected to the input terminal of the delay sub-circuit, and a second terminal of the voltage division and delay sub-circuit is connected to the second terminal of the first switch transistor, a voltage division terminal of the voltage division and delay sub-circuit is connected to a control terminal of the second switch transistor, and a delay terminal of the voltage division and delay sub-circuit is connected to the output terminal of the delay sub-circuit after the delay terminal of the voltage division and delay sub-circuit is connected to the second terminal of the second switch transistor.

In addition, according to an embodiment, the first switch transistor is an NMOS transistor, and the second switch transistor is a PMOS transistor.

In addition, according to an embodiment, where the second preset voltage provided by the control sub-circuit is input to the input terminal of the delay sub-circuit, the first switch transistor is turned on under the driving of the second preset voltage; the voltage division and delay sub-circuit is configured to divide the second preset voltage provided by the power chip after the first switch transistor is turned on to generate a divided voltage signal and output the divided voltage signal through the voltage division terminal to the second switch transistor to drive the second switch transistor to be turned on; after the second switch is turned on, the second preset voltage is delayed to be output.

In addition, according to an embodiment, the voltage division and delay sub-circuit comprises: a first resistor and a second resistor. A first terminal of the first resistor is used as the second terminal of the voltage division and delay sub-circuit, and a second terminal of the first resistor is connected to the voltage division terminal of the voltage division and delay sub-circuit; a first terminal of the second resistor is used as the first terminal of the voltage division and delay sub-circuit, and a second terminal of the second resistor is connected to the voltage division terminal of the voltage division and delay sub-circuit.

In addition, according to an embodiment, the voltage division and delay sub-circuit further comprises: a first capacitor, a first terminal of the first capacitor is connected to the voltage division terminal of the voltage division and delay sub-circuit, and a second terminal of the first capacitor is used as the delay terminal of the voltage division and delay sub-circuit.

In addition, according to an embodiment, the voltage division and delay sub-circuit further comprises: a second capacitor, a first terminal of the second capacitor is connected to the first terminal of the second resistor, and a second terminal of the second capacitor is connected to the second terminal of the second resistor.

In addition, according to an embodiment, a preset delay time period of the delay sub-circuit is R1*C1*Ln ((ELVDD_IN−ELVDD_OUT)/ELVDD_IN), where R1is a resistance value of the first resistor, C1is a capacitance value of the second capacitor, ELVDD_IN is a voltage of the input terminal of the delay sub-circuit, ELVDD_OUT is a voltage of the output terminal of the delay sub-circuit, and Ln is a natural logarithm.

According to another aspect of the present disclosure, at least one embodiment provides a display device, comprising any of the above power supply circuits.

According to another aspect of the present disclosure, at least one embodiment provides a power supply method, comprising: outputting a first preset voltage provided by a control sub-circuit to a first power supply terminal; and delaying a second preset voltage provided by the control sub-circuit by a delay sub-circuit, and outputting the delayed second preset voltage to a second power supply terminal.

In addition, according to an embodiment, the control sub-circuit is a power chip; the first preset voltage is provided by a first output terminal of the power chip, and the first preset voltage provided by the power chip is output to the first power supply terminal; the second preset voltage is provided by a second output terminal of the power chip, the second preset voltage is delayed to be output, and the delayed second output voltage is output to the second power supply terminal.

In addition, according to an embodiment, the delay sub-circuit comprises a first switch transistor and a second switch transistor, and delaying the second preset voltage provided by the control sub-circuit by the delay sub-circuit comprises: acquiring the second preset voltage provided by the control sub-circuit, wherein the first switch transistor is turned on under driving of the second preset voltage; after the first switch transistor is turned on, the second preset voltage provided by the power chip is divided to generate a divided voltage signal, wherein the second switch transistor is turned on under driving of the divided voltage signal; and after the second switch transistor is turned on, the second preset voltage is delayed to be output.

