CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims the priority of Chinese patent application No. 201910097625.7, filed on Jan. 31, 2019, the entirety of which is incorporated herein by reference.

FIELD OF THE DISCLOSURE

The present disclosure generally relates to the field of semiconductor manufacturing and, more particularly, relates to semiconductor devices and fabrication methods.

BACKGROUND

Power semiconductor devices are widely used in switching power supplies, automotive electronics, industrial controls, wireless communications, motor controls and many other fields. Two essential indicators of the power semiconductor devices are high breakdown voltage and low on-resistance. Lateral diffused metal oxide semiconductor (LDMOS) device is a power MOS device; and mainly used in power integrated circuits.

The structure of an asymmetric LDMOS device often includes a first well region and a second well region formed in a semiconductor substrate. The conductivity type of the ions of the first well region and the conductivity type of the ions of the second well region are different. The asymmetric LDMOS device also includes a gate structure formed on the first well region and the second well region; and a doped source layer and a doped drain layer respectively formed in the substrate at both sides of the gate structure. The doped drain layer is formed in the first well region, and the source doped layer is formed in the second well region. The doped source layer and the doped drain layer are doped with source/drain ions. The conductivity type of the source/drain ions is the same as the conductivity type of the first well region. The portion of the second well region covered by the gate structure is a channel region of the LDMOS device. The first well region between the doped drain layer and the channel region is a drift region of the LDMOS device. The drift region is used to change the electric field distribution of the LDMOS device and increase the breakdown voltage of the LDMOS device. However, if the device structure is further shrunk, the effect for improving the breakdown voltage is not significant.

Thus, as the size of semiconductor device is continuously shrunk, a transistor structure of a lateral diffusion enhanced metal oxide semiconductor (LDEMOS) has been developed. A floating plug is formed in a dielectric layer on the gate structure and the doped drain layer of the LDEMOS. The floating plug is connected to a voltage to form a depletion layer in the semiconductor substrate under the floating plug to increase the breakdown voltage of the LDEMOS.

However, there is a need to further improve the performance of the LDEMOS device. The disclosed methods and semiconductor devices are directed to solve one or more problems set forth above and other problems in the art.

BRIEF SUMMARY OF THE DISCLOSURE

One aspect of the present disclosure includes a method for forming a semiconductor device. The method may include providing a semiconductor substrate; and forming a first well region and a second well region in the semiconductor substrate. The second well region may be formed in the first well region and a conductivity type of the first well region may be opposite to a conductivity type of the second well region. The method may also include forming a first gate structure on a surface of the second well region and a portion of a surface of the first well region and a second gate structure on a portion of the first well region. A first opening may be formed between the first gate structure and the second gate structure. Further, the method may include forming a sidewall spacer layer to cover sidewall and bottom surfaces of the first opening; forming a dielectric layer on the semiconductor substrate to cover the first gate structure, the second gate structure and the sidewall spacer layer; and forming a floating plug in the dielectric layer and on the sidewall spacer layer.

Another aspect of the present disclosure includes a semiconductor device. The semiconductor structure may include a semiconductor substrate; and a first well region and a second well region in the semiconductor substrate. The second well region may be in the first well region and a conductivity type of the first well region may be opposite to a conductivity of the second well region. The semiconductor device may also a first gate structure and a second gate structure on the semiconductor substrate. The first gate structure may coves a portion of a surface of the first well region and a portion of a surface of the second well region; and a first opening may be formed between the first gate structure and the second gate structure. Further, the semiconductor device may include a sidewall spacer layer in the first opening; a dielectric layer on the semiconductor substrate and covering the first gate structure, the second gate structure and the sidewall spacer layer; and a floating plug in the dielectric layer and on the sidewall spacer layer.

Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.

