TECHNICAL FIELD

The present disclosure generally relates to the technical field of integrated circuit design. In particular, the present disclosure addresses a multiple iteration clock tree synthesis process that includes a target macro clock latency computation.

BACKGROUND

An integrated circuit (IC) layout specifies portions of various components of an IC device. When the IC is to include cells, macros, and/or other types of clocked devices (“sinks”) that are to be clocked, the IC includes one or more clock networks for delivering a clock signal from a clock source to all of the components to be clocked by it. A clock network distributes a clock signal from its root (e.g., a clock source) to sinks (e.g., macros or flip flops) within an IC through a branching network of drivers (e.g., buffers or inverters).

Electronic design automation (EDA) software systems commonly perform clock-tree synthesis (CTS). Conventional approaches to CTS include building a clock tree by placing drivers at various regions of the clock network based on satisfaction of a set of clock tree design constraints that include timing constraints such as clock skew among others (e.g., clock slew and clock latency). Clock skew refers to a difference in clock arrival time between two clock sinks.

In some instances, clock skew may be intentionally added into a clock tree. For example, during CTS, a clock path delay for each clock sink is tuned in accordance with design constraints. Prior to tuning clock path delays, a pin insertion delay (PID) can be assigned to a clock path and provided as a constraint to CTS. PID is a virtual delay added to a clock path of the IC design that causes CTS to intentionally introduce skew when tuning clock path delays.

