CROSS-REFERENCE TO RELATED APPLICATION

The present disclosure claims priority to and the benefit of Korean Patent Application No. 10-2019-0161893, filed on Dec. 6, 2019, which is hereby incorporated by reference in its entirety.

BACKGROUND

Field of the Disclosure

The present disclosure relates to a thin film transistor array substrate for a digital X-ray detector device for minimizing leakage current of a PIN diode and the digital X-ray detector device including the same.

Description of the Background

Because X-ray is of a short wavelength, the X-ray may pass through an object easily. The transmittance of the X-ray depends on an inner density of the object. Therefore, an internal structure of the object may be observed by detecting an amount of the X-ray transmitted through the object.

One of X-ray based inspection methods used in a medical field is a film printing scheme. However, in the film printing scheme, to check a result, an image is shot, and then a film is printed. Thus, it takes a long time to check the result. Especially, in the film printing scheme, there are some difficulties in storing and preserving the printed film.

A digital X-ray detector (DXD) device using a thin film transistor has been developed and widely used in the medical field.

The DXD device detects the transmittance of the X-ray transmitted through the object and displays an internal state of the object on a display based on the transmittance.

Therefore, the digital X-ray detector device may display the internal structure of the object without using an additional film and printed paper. Further, the DXD device may check the results in real time immediately after X-ray photographing.

SUMMARY

A digital X-ray detector device detects current inside a digital X-ray detection panel to implement an image based on the current and includes a photo PIN (p type semiconductor-intrinsic type semiconductor-n type semiconductor) diode.

The digital X-ray detector device may minimize noise generated in an X-ray image to obtain an accurate and clear image desired by users.

As the noise may be generated based on leakage current, which occurs after a reverse voltage is applied to the top of the PIN diode, the leakage current generated by the PIN diode may be minimized.

Accordingly, the inventors of the present disclosure invented a thin film transistor array substrate for a digital X-ray detector device and the digital X-ray detector device capable of minimizing the leakage current generated by the PIN diode.

The present disclosure provides a thin film transistor array substrate for a digital X-ray detector device and the digital X-ray detector device capable of minimizing the leakage current of the PIN diode.

The present disclosure further provides a thin film transistor array substrate for a digital X-ray detector device and the digital X-ray detector device capable of minimizing a reduction in transmittance of light incident on the PIN diode.

The present disclosure is not limited to the above-mentioned objects, and the other objects and advantages of the present disclosure, which are not mentioned, may be understood by the following description, and more clearly understood by the aspects of the present disclosure. It is also readily understood that the objects and the advantages of the present disclosure may be implemented by features described in appended claims and a combination thereof.

According to an aspect of the present disclosure, there are provided a thin film transistor array substrate for a digital X-ray detector device and the digital X-ray detector device capable of minimizing the generation of the leakage current as well as minimizing the reduction of light transmittance of PIN diodes.

According to an aspect of the present disclosure, the thin film transistor array substrate for the digital X-ray detector device and the digital X-ray detector device include a base substrate, a driving thin film transistor disposed on the base substrate, and a PIN diode connected to the driving thin film transistor and including a lower electrode, a PIN layer, and an upper electrode and the PIN layer includes a p+ type semiconductor layer, a p− type semiconductor layer, an I (intrinsic) semiconductor layer, an n− type semiconductor layer, and an n+ type semiconductor layer.

In this case, the p+ type semiconductor layer and the p− type semiconductor layer each contain p type impurities, the p− type semiconductor layer has a lower concentration of p type impurities than that of the p+ type semiconductor layer, and the p type impurity may include at least one of Group 3 elements.

In addition, the n+ type semiconductor layer and the n− type semiconductor layer each contain n type impurities, the n− type semiconductor layer has a lower concentration of n type impurities than that of the n+ type semiconductor layer, and the n type impurity may include at least one of Group 5 elements.

In addition, according to another aspect of the present disclosure, the p+ type semiconductor layer may have the same thickness as the n+ type semiconductor layer and the p− type semiconductor layer may have the same thickness as the n− type semiconductor layer.

According to the present disclosure, multi-p type semiconductor layer including the p+ type semiconductor layer and the p− type semiconductor layer having different impurity concentrations is disposed above the intrinsic semiconductor layer of the PIN diode and multi-n type semiconductor layer including the n+ type semiconductor layer and the n− type semiconductor layer having different impurity concentrations is disposed below the intrinsic semiconductor layer to minimize ejection of holes by the p− type semiconductor layer and ejection of electrons by the n− type semiconductor layer, thereby minimizing occurrence of the leakage current of the PIN diode.

In addition, according to the present disclosure, a p− type semiconductor layer having a low concentration of impurities is disposed under a p+ type semiconductor layer having a high concentration of impurities and an n− type semiconductor layer having a low concentration of impurities is disposed on the n+ type semiconductor layer having a high concentration of impurities to minimize the reduction in the light transmittance of the PIN diode due to the high concentration of impurities.

Specific effects of the present disclosure, in addition to the above-mentioned effects, will be described together as well as describing specific matters to implement the present disclosure.

