TECHNICAL FIELD

This disclosure relates generally to queues, and specifically to systems, methods, and devices for queue availability monitoring.

BACKGROUND

A queue may store one or more entries such as a command and/or a request that may be processed by a processor. A processor may check the queue to determine if the queue has any entries that are available for processing.

The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute prior art.

SUMMARY

A method may include determining, with a queue availability module, that an entry is available in a queue, asserting a bit in a register based on determining that an entry is available in the queue, determining, with a processor, that the bit is asserted, and processing, with the processor, the entry in the queue based on determining that the bit is asserted. The method may further include storing the register in a tightly coupled memory associated with the processor. The method may further include storing the queue in the tightly coupled memory. The queue may be a first queue, the bit may be a first bit, and the method may further include determining, with the queue availability module, that an entry is available in a second queue, and asserting a second bit in the register based on determining that an entry is available in the second queue. The method may further include finding the first bit in the register using a find-first instruction. The method may further include determining, with the processor, that the second bit is asserted, and processing, with the processor, the entry in the second queue based on determining that the second bit is asserted. The queue may include one of a command queue, a direct memory access (DMA) queue, or a transfer queue. Processing the entry may include processing a command. Processing the entry may include managing a resource. The method may further include receiving a command from a host through a communication interface, parsing the command, and storing the command as the entry in the queue. Determining that an entry is available in the queue may include checking a phase tag of the entry.

A system may include a queue configured to hold one or more entries, a register comprising a bit to indicate an availability of one or more entries in the queue, a queue availability module configured to monitor the queue and assert the bit in the register based on determining that one or more entries are available in the queue, and a processor configured to check the register and process an entry in the queue based on determining that the bit in the register is asserted. The queue availability module may be coupled to the processor through a system bus, and the register may be stored on the processor side of the system bus. The register may be stored in a tightly coupled memory associated with the processor. The queue may be a first queue, the bit may be a first bit, the system may further include a second queue configured to hold one or more entries, the queue availability module may be further configured to monitor the second queue and assert a second bit in the register based on determining that one or more entries are available in the second queue, and the processor may be further configured to check the register and process an entry in the second queue based on determining that the second bit in the register is asserted. The processor may be further configured to check the register using a find-first instruction.

A method may include monitoring a queue with a queue availability module, updating, with the queue availability module, a register based on an available entry in the queue, checking, with a processor, the register, and processing, with the processor, the available entry based on a state of the register. The queue may be a first queue, updating the register may include asserting a first bit in the register, and the method may further include monitoring a second queue with the queue availability module, and updating, with the queue availability module, a second bit in the register based on an available entry in the second queue. The method may further include storing the register in a tightly coupled memory associated with the processor. The register may be checked with a find-first instruction.

