FIELD

This invention relates generally to information handling systems (IHSs), and more particularly, to IHSs that include Peripheral Component Interconnect Express (PCIe) slots.

BACKGROUND

As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.

Many information handling systems (IHSs), such as servers, desktop computers and mobile PCs, include Peripheral Component Interconnect Express (PCIe) interfaces and ports for connecting and communicating with PCIe-compatible devices. In some information handling systems, a number of PCIe slots may be included on the system motherboard, along with one or more processing devices (e.g., one or more central processing units (CPUs), GPUs, etc.), a platform controller hub (PCH) and other hardware components. Each PCIe slot included on the motherboard may be configured to receive a PCIe card comprising one or more PCIe devices. Examples of PCIe devices include, but are not limited to, video cards, sound cards, non-volatile memory cards, network interface cards (NICs), hardware RAID controllers, solid state drives (SSDs), graphics processing units (GPUs), etc.

In the PCIe bus architecture, PCIe devices are connected via a network of serial connections called “links” or “buses.” A PCIe link (or bus) is a point-to-point communication channel between two PCIe ports and includes one or more “lanes” (e.g., 1, 4, 8, 12, 16 or 32 lanes). Each lane is composed of two differential signal pairs, one for receiving data and the other for transmitting data. PCIe slots and PCIe cards can be configured with 1, 4, 8, 12, 16 or 32 lanes, and are generally designated in terms of lane width using the prefix “x”. For example, an “x16 slot” is a PCIe slot comprising 16 lanes, an “x8 slot” is a PCIe slot comprising 8 lanes, etc. Likewise, an “x8 card” is a PCIe card comprising 8 lanes, an “x4 card” is a PCIe card comprising 4 lanes, etc. In general, a PCIe card may fit into a PCIe slot of its physical size or larger. For example, an x8 PCIe card may fit within an x8, x16 or x32 PCIe slot, but will not fit within an x4, or x1 PCIe slot.

FIG. 1(Prior Art) is a block diagram illustrating an example hierarchy of PCIe devices that may be included within an information handling system (IHS). As shown inFIG. 1, PCIe devices are coupled in a tree topology, and may generally include a PCIe root complex, a PCIe switch, PCI-to-PCI bridge(s) and PCIe end devices. The PCIe root complex logic12can be implemented within a host processor10of the IHS, and may be used in some embodiments to provide a high speed PCIe connection to a first PCIe end device14(e.g., a PCIe-compatible GPU). The root complex logic12connects to the PCIe device tree through a logical port (known as the root port), which is connected to a PCIe switch18typically implemented, e.g., within a southbridge controller or PCH16of the IHS. A PCIe switch is a device that connects two or more PCIe links (or buses) and may contain several virtual PCI-to-PCI bridges. In the example shown inFIG. 1, PCIe switch18includes a first virtual PCI-to-PCI bridge1connecting PCIe bus0to PCIe bus1, a second virtual PCI-to-PCI bridge2connecting PCIe bus1to PCIe bus2, and a third virtual PCI-to-PCI bridge3connecting PCIe bus1to PCIe bus3.

Each PCIe link (or bus) may have a number of PCIe end devices and/or PCI-to-PCI bridges connected thereto. A PCIe end device is a PCIe device that terminates a PCIe link, i.e., it only has one connection to the PCIe tree topology. In the example shown inFIG. 1, three PCIe end devices (20,22, and24) are coupled to PCIe bus2, while only one PCIe end device (26) is coupled to PCIe bus3. A PCI-to-PCI bridge is a PCIe device that connects two PCIe links (or buses) together. InFIG. 1, PCI-to-PCI bridge28is included for connecting PCIe bus3to PCIe bus4, where two more PCIe end devices (30and32) are connected. In some cases, the PCIe end devices (20,22,24,26,30and32) and PCI-to-PCI bridge(s) (28) may be connected to the system motherboard via PCIe slots, or may be mounted directly onto the system motherboard.

Each time an information handling system (IHS) is powered on or rebooted, an IHS processing device (such as, e.g., the host processor10shown inFIG. 1and/or an embedded controller) executes boot firmware (e.g., BIOS or UEFI) to test and initialize IHS hardware components, perform a Power-On Self-Test (POST) to ensure the hardware configuration is valid and working properly, load an operating system (OS) from a computer readable storage device, and/or perform a variety of other actions known in the art. During POST, all PCIe devices (including PCIe root ports, switches, bridges and end devices) included within the system are detected and enumerated (i.e., assigned bus numbers), so that system software (such as, e.g., the operating system, device drivers, applications, etc.) can address and access the PCIe devices.

The PCIe Specification allows a maximum of 256 bus numbers (or bus resources) to be allocated to the PCIe devices included within an information handling system. While PCIe cards having only one PCI end device (e.g., a NIC, sound card, or USB controller) may consume just one bus number, other PCIe cards (e.g., SSDs, hardware-based RAID controllers, PCIe video cards, Thunderbolt™, PCI-to-PCI bridge devices, etc.) may require many more bus numbers. Also, PCIe cards that support hot-plugging devices (such as Thunderbolt™) require bus numbers to be reserved for devices that may be attached to the system later, after POST is complete and the operating system is running.

Before PCIe devices are detected and enumerated (i.e., assigned bus numbers), the system BIOS allocates various amounts PCIe bus resources to the host processor, PCIe devices and PCIe slots during POST. For example, the system BIOS may allocate a small number of PCIe bus resources to core devices within the host processor, and may allocate or distribute the remaining PCIe bus resources to the PCIe devices and PCIe slots included within the system. In order to do so, the system BIOS may check for the presence of PCI-to-PCI bridges in the PCIe device topology and allocate an optimal number of PCIe bus resources to each PCI-to-PCI bridge (Primary Bus Number/Secondary Bus Number/Subordinate Bus Number) included within the system. The remaining PCIe bus resources would then be distributed relatively evenly to all PCIe slots provided on the system motherboard. In a system comprising 7 PCIe slots, for example, the system BIOS may allocate approximately 35 bus resources to each PCIe slot (if, for example, all PCIe slots have the same lane width).

Although ideal in some cases, distributing PCIe bus resources evenly amongst the PCIe slots may not allow sufficient bus resources to be allocated to some PCIe cards. For example, a dual-port Thunderbolt3card requires a minimum of 65 bus resources, and therefore, cannot operate properly when only 35 bus resources are allocated to the PCIe slot to which it is connected. Other specialized PCIe cards having, e.g., multiple PCI-to-PCI bridge devices on a single card or a complex hardware design may also require more bus resources, and therefore, fail to operate properly when bus resources are allocated evenly among PCIe slots.

One conventional solution for supporting dual-port Thunderbolt3and other specialized PCIe cards is to provide a BIOS setup menu that enables users to control how PCIe bus resources are allocated among PCIe slots. In the conventional solution, the BIOS setup menu provided a number of user-selectable PCIe bus allocation options, including a “Default” option, an “Optimize for Thunderbolt” option, and a plurality of “Custom” options. If the “Default” option was selected, the system BIOS allocated bus resources relatively evenly among all PCIe slots. If the “Optimize for Thunderbolt” option was selected, the system BIOS allocated more than 65 bus resources to each PCIe slot configured to support Thunderbolt, and allocated the remaining bus resources evenly to the remaining PCIe slots. If a “Custom” option was selected, the system BIOS allocated a predetermined percentage of bus resources to one or more PCIe slots, while maintaining a minimum or moderate number of bus resources to the remaining PCIe slots.

By providing a BIOS setup menu with user-selectable PCIe bus allocation options, the conventional solution ensured that Thunderbolt3cards and other specialized PCIe cards had sufficient bus resources to operate properly, and provided flexibility to the user for various scenarios and usage of the PCIe slots. However, the conventional solution did not detect unused PCIe slots and reallocate PCIe bus resources if one or more of the PCIe slots were unused (i.e., if a PCIe card was not connected to one or more of the PCIe slots). As such, the conventional solution did not utilize bus resources optimally when there were unused PCIe slots on the system motherboard.

SUMMARY OF THE INVENTION

The following description of various embodiments of information handling systems and related methods is not to be construed in any way as limiting the subject matter of the appended claims.

According to one embodiment, a computer-implemented method is provided herein to allocate Peripheral Component Interconnect Express (PCIe) bus resources to PCIe slots according to various PCIe bus resource allocation option settings. In general, the computer-implemented method described herein may be executed by a host processor of an information handling system (IHS) having a plurality of Peripheral Component Interconnect Express (PCIe) slots, which are provided on a system motherboard. In some embodiments, the computer-implemented method may be performed each time the IHS is booted, for example, at the start of a Power-On Self-Test (POST).

In one embodiment, the computer-implemented method disclosed herein may include detecting a PCIe bus allocation option setting selected from a plurality of options provided in a boot firmware setup menu, wherein said plurality of options include at least an auto detect option; and determining whether or not the PCIe bus allocation option setting has changed since the IHS was last booted. If the PCIe bus allocation option setting has changed since the last boot, and the auto detect option is detected, the method may further include automatically detecting which of the plurality of PCIe slots are used and unused; releasing PCIe bus resources previously allocated to any PCIe slots determined to be unused; and reallocating the released PCIe bus resources to one or more of the PCIe slots determined to be used.

In some embodiments, said automatically detecting which of the plurality of PCIe slots are used and unused includes determining that a PCIe slot is used upon detecting a device present signal supplied from a pin on the PCIe slot; and determining that the PCIe slot is unused if no device present signal is detected from the pin on the PCIe slot.

In some embodiments, the method may allocate PCIe bus resources relatively evenly to the plurality of PCIe slots, if said automatically detecting determines that each of the plurality of PCIe slots on the system motherboard is used. If one or more of the plurality of PCIe slots are determined to be unused, however, the method may reallocate the released PCIe bus resources to one or more of the used PCIe slots based, at least in part, on at least one of: a number of the host processors included within the IHS, a number of the PCIe slots provided on the system motherboard and a lane width of the PCIe slots. In some embodiments, the method may further include detecting the system motherboard ID to determine the number of host processors included within the IHS, the number of PCIe slots provided on the system motherboard and the lane width of the PCIe slots prior to said reallocating.

If one or more of the plurality of PCIe slots is/are determined to be unused, one embodiment of the method may reallocate the released PCIe bus resources relatively evenly to only the used PCIe slots having a larger lane width. Another embodiment of the method may reallocate a larger amount of the released PCIe bus resources relatively evenly to the used PCIe slots having a larger lane width, while reallocating a smaller amount of the released PCIe bus resources to the used PCIe slots having a comparatively smaller lane width.

In some embodiments, the plurality of options provided in the boot firmware setup menu may further include one or more of: a default option, an optimize for Thunderbolt™ option, and one or more custom options. In some embodiments, the method may further include determining if Thunderbolt™ support is enabled for the IHS prior to said detecting a PCIe bus allocation option setting.

If Thunderbolt support is enabled, the method may further include automatically selecting the optimize for Thunderbolt option; rendering the default option, the auto detect option and the one or more custom options unavailable for user selection in the boot firmware setup menu; and allocating sufficient PCIe bus resources (e.g., at least 65 PCIe bus resources) to the PCIe slots that support Thunderbolt™. The remaining PCIe bus resources may be allocated to the other PCIe slots (i.e., the PCIe slots that do not support Thunderbolt™) based, at least in part, on at least one of: the number of the host processors installed in the system, the number of the PCIe slots provided on the system motherboard and the lane width of the PCIe slots.

If Thunderbolt™ support is disabled, the PCIe bus allocation option setting has changed since the last boot and the auto detect option is not detected, the method may allocate PCIe bus resources to the PCIe slots according to the detected PCIe bus allocation option setting, wherein said allocation is based, at least in part, on at least one of: the number of host processors included within the IHS, the number of PCIe slots provided on the system motherboard and the lane width of the PCIe slots.

According to another embodiment, an information handling system (IHS) is provided herein including a plurality of Peripheral Component Interconnect Express (PCIe) slots provided on a system motherboard, where each PCIe slot is configured to connect to a PCIe end device, and at least one host processor that is coupled to one or more of the PCIe slots. In general, the at least one host processor may be configured to execute: a first set of program instructions to detect a PCIe bus allocation option setting selected from a plurality of options provided in a boot firmware setup menu; a second set of program instructions to determine whether or not the PCIe bus allocation option setting has changed since the IHS was last booted; and a third set of program instructions to allocate PCIe bus resources to the plurality of PCIe slots according to the detected PCIe bus allocation option setting. The plurality of options provided in the boot firmware setup menu include at least an auto detect option, which when selected, enables the at least one host processor to automatically detect unused PCIe slots and reallocate PCIe bus resources to used PCIe slots.

If the PCIe bus allocation option setting has changed since the last boot and the auto detect option is detected, the third set of program instructions may be executed by the host processor to automatically detect which of the plurality of PCIe slots are used and unused; release PCIe bus resources previously allocated to any PCIe slots determined to be unused; and reallocate the released PCIe bus resources to one or more of the PCIe slots determined to be used.

In some embodiments, the IHS may further include a platform controller hub (PCH), which is coupled to the PCIe slots and to the at least one host processor. The PCH may include a plurality of general purpose input/output (GPIO) pins, which are coupled to present pins on the PCIe slots. In some embodiments, the third set of program instructions may determine that a particular PCIe slot is used, if a device present signal is detected via a GPIO pin of the PCH and a present pin of the particular PCIe slot, and may determine that the particular PCIe slot is unused, if no device present signal is detected.

If one or more of the PCIe slots is/are determined to be unused, the third set of program instructions may be executed by the host processor to reallocate the released PCIe bus resources to one or more of the used PCIe slots based, at least in part, on at least one of: the number of the host processors included within the IHS, the number of the PCIe slots provided on the system motherboard and the lane width of the PCIe slots. In some embodiments, the third set of program instructions may be executed by the host processor to reallocate the released PCIe bus resources relatively evenly to only the used PCIe slots having a larger lane width. In other embodiments, the third set of program instructions may be executed by the host processor to reallocate a larger amount of the released PCIe bus resources relatively evenly to the used PCIe slots having a larger lane width, and to reallocate a smaller amount of the released PCIe bus resources to the used PCIe slots having a comparatively smaller lane width.

In some embodiments, the plurality of options provided in the boot firmware setup menu may further include one or more of: a default option, an optimize for Thunderbolt™ option, and one or more custom options. In some embodiments, the at least one host processor may be configured to execute a fourth set of program instructions to determine if Thunderbolt™ support is enabled for the IHS prior to executing the first set of program instructions to detect the PCIe bus allocation option setting.

If Thunderbolt™ support is enabled, the at least one host processor may be configured to execute a fifth set of program instructions to automatically select the optimize for Thunderbolt™ option; render the default option, the auto detect option and the one or more custom options unavailable for user selection in the boot firmware setup menu; and allocate sufficient PCIe bus resources (e.g., at least 65 PCIe bus resources) to the PCIe slots that support Thunderbolt™. The remaining PCIe bus resources may be allocated to the remaining PCIe slots (i.e., the PCIe slots that do not support Thunderbolt™) based, at least in part, on at least one of: the number of the host processors installed in the system, the number of the PCIe slots provided on the system motherboard and the lane width of the PCIe slots.

If Thunderbolt™ support is disabled, the PCIe bus allocation option setting has changed since the last boot and the auto detect option is not detected, the at least one host processor may be configured to execute the third set of program instructions to allocate PCIe bus resources to the PCIe slots according to the detected PCIe bus allocation option setting, wherein said allocation is based, at least in part, on at least one of: the number of the host processors included within the IHS, the number of the PCIe slots provided on the system motherboard and the lane width of the PCIe slots.

