BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to memory control, and more particularly, to a method for performing access management of a memory device with aid of dedicated bit information, and an associated apparatus (e.g. a memory controller within the memory device, the memory device, and an electronic device comprising the memory device).

2. Description of the Prior Art

A memory device may comprise Flash memory for storing data, and the management of accessing the Flash memory is complicated. The memory device may comprise a RAM for purposes of buffering, management, etc. The storage capacity of the RAM is typically insufficient. The related art tries to correct the problem, but further problems are introduced. Thus, a novel method and associated architecture are needed for solving the problems without introducing any side effect or in a way that is less likely to introduce a side effect.

SUMMARY OF THE INVENTION

It is therefore an objective of the present invention to provide a method for performing access management of a memory device with aid of dedicated bit information, and to provide an associated apparatus (e.g. a memory controller within the memory device, the memory device, and an electronic device comprising the memory device), in order to solve the above-mentioned problems.

At least one embodiment of the present invention provides a method for performing access management of a memory device with aid of dedicated bit information, where the method is applicable to the memory device. The memory device may comprise a non-volatile (NV) memory, and the NV memory may comprise at least one NV memory element (e.g. one or more NV memory elements). The method may comprise: transmitting a compact hybrid table comprising multiple compressed tables to a host device, for being stored in the host device, to allow the host device to send one of multiple compact hybrid table entries of the compact hybrid table to the memory device to be reading reference, for enhancing reading performance (e.g. increasing reading speed) of the memory device, wherein the multiple compact hybrid table entries of the compact hybrid table have a same size; in response to the host device sending at least one packet for indicating at least one request, determining whether a reading request among the at least one request exists, wherein a read command packet carrying at least a starting logical address and a data length of the reading request among the at least one packet indicates the reading request; in response to existence of the reading request, obtaining reading reference information from the read command packet, wherein the reading reference information carried by the read command packet comprises first mapping information indicating a first mapping relationship and comprises the dedicated bit information, and the reading reference information represents a corresponding compact hybrid table entry of the multiple compact hybrid table entries of the compact hybrid table; determining at least one second mapping relationship according to the first mapping relationship and the dedicated bit information, for reading data of the data length that starts from the starting logical address; and reading the data from the NV memory for the host device at least according to the first mapping relationship and the at least one second mapping relationship.

In addition to the above method, the present invention also provides a memory device, and the memory device comprises a NV memory and a controller such as a memory controller. The NV memory is arranged to store information, wherein the NV memory may comprise at least one NV memory element (e.g. one or more NV memory elements). The controller is coupled to the NV memory, and the controller is arranged to control operations of the memory device. In addition, the controller comprises a processing circuit that is arranged to control the controller according to a plurality of host commands from a host device, to allow the host device to access the NV memory through the controller. For example, the controller transmits a compact hybrid table comprising multiple compressed tables to the host device, for being stored in the host device, to allow the host device to send one of multiple compact hybrid table entries of the compact hybrid table to the memory device to be reading reference, for enhancing reading performance (e.g. increasing reading speed) of the memory device, wherein the multiple compact hybrid table entries of the compact hybrid table have a same size; in response to the host device sending at least one packet for indicating at least one request, the controller determines whether a reading request among the at least one request exists, wherein a read command packet carrying at least a starting logical address and a data length of the reading request among the at least one packet indicates the reading request; in response to existence of the reading request, the controller obtains reading reference information from the read command packet, wherein the reading reference information carried by the read command packet comprises first mapping information indicating a first mapping relationship and comprises the dedicated bit information, and the reading reference information represents a corresponding compact hybrid table entry of the multiple compact hybrid table entries of the compact hybrid table; the controller determines at least one second mapping relationship according to the first mapping relationship and the dedicated bit information, for reading data of the data length that starts from the starting logical address; and the controller reads the data from the NV memory for the host device at least according to the first mapping relationship and the at least one second mapping relationship.

According to some embodiments, an associated electronic device is also provided. The electronic device may comprise the above memory device, and may further comprise: the host device, coupled to the memory device. The host device may comprise: at least one processor, arranged for controlling operations of the host device; and a power supply circuit, coupled to the at least one processor, arranged for providing power to the at least one processor and the memory device. In addition, the memory device can be configured to provide the host device with storage space.

In addition to the above method, the present invention also provides a controller of a memory device, such as a memory controller within the memory device, where the memory device comprises the controller and a NV memory. The NV memory may comprise at least one NV memory element (e.g. one or more NV memory elements). In addition, the controller comprises a processing circuit that is arranged to control the controller according to a plurality of host commands from a host device, to allow the host device to access the NV memory through the controller. For example, the controller transmits a compact hybrid table comprising multiple compressed tables to the host device, for being stored in the host device, to allow the host device to send one of multiple compact hybrid table entries of the compact hybrid table to the memory device to be reading reference, for enhancing reading performance (e.g. increasing reading speed) of the memory device, wherein the multiple compact hybrid table entries of the compact hybrid table have a same size; in response to the host device sending at least one packet for indicating at least one request, the controller determines whether a reading request among the at least one request exists, wherein a read command packet carrying at least a starting logical address and a data length of the reading request among the at least one packet indicates the reading request; in response to existence of the reading request, the controller obtains reading reference information from the read command packet, wherein the reading reference information carried by the read command packet comprises first mapping information indicating a first mapping relationship and comprises the dedicated bit information, and the reading reference information represents a corresponding compact hybrid table entry of the multiple compact hybrid table entries of the compact hybrid table; the controller determines at least one second mapping relationship according to the first mapping relationship and the dedicated bit information, for reading data of the data length that starts from the starting logical address; and the controller reads the data from the NV memory for the host device at least according to the first mapping relationship and the at least one second mapping relationship.

At least one embodiment of the present invention provides a method for performing access management of a memory device with aid of dedicated bit information, where the method is applicable to a host device. The memory device may comprise a non-volatile (NV) memory, and the NV memory may comprise at least one NV memory element (e.g. one or more NV memory elements). The method may comprise: receiving a compact hybrid table comprising multiple compressed tables from the memory device, and storing the compact hybrid table in the host device, for sending one of multiple compact hybrid table entries of the compact hybrid table to the memory device to be reading reference, for enhancing reading performance of the memory device, wherein the multiple compact hybrid table entries of the compact hybrid table have a same size; in response to at least one request from a user of the host device being received, determining whether a reading request among the at least one request exists; in response to existence of the reading request, sending a read command packet carrying at least a starting logical address and a data length of the reading request to the memory device, and providing reading reference information to the memory device through the read command packet, wherein the read command packet indicates the reading request, the reading reference information carried by the read command packet comprises first mapping information indicating a first mapping relationship and comprises the dedicated bit information, and the reading reference information represents a corresponding compact hybrid table entry of the multiple compact hybrid table entries of the compact hybrid table; utilizing a memory controller within the memory device to determine at least one second mapping relationship according to the first mapping relationship and the dedicated bit information, for reading data of the data length that starts from the starting logical address; and utilizing the memory controller to read the data from the NV memory for the host device at least according to the first mapping relationship and the at least one second mapping relationship.

In addition to the above method, the present invention also provides a host device, where the host device is applicable to performing access management of a memory device with aid of dedicated bit information. The memory device may comprise a non-volatile (NV) memory, and the NV memory comprising at least one NV memory element (e.g. one or more NV memory elements). The host device may comprise: at least one processor, arranged for controlling operations of the host device; at least one random access memory (RAM), coupled to the at least one processor, arrange for storing information within the host device; and a power supply circuit, coupled to the at least one processor, arranged for providing power to the at least one processor and the memory device. For example, the host device is configured to receive a compact hybrid table comprising multiple compressed tables from the memory device, and to store the compact hybrid table in the at least one RAM of the host device, for sending one of multiple compact hybrid table entries of the compact hybrid table to the memory device to be reading reference, for enhancing reading performance of the memory device, wherein the multiple compact hybrid table entries of the compact hybrid table have a same size; in response to at least one request from a user of the host device being received, the host device is configured to determine whether a reading request among the at least one request exists; in response to existence of the reading request, the host device is configured to send a read command packet carrying at least a starting logical address and a data length of the reading request to the memory device, and to provide reading reference information to the memory device through the read command packet, wherein the read command packet indicates the reading request, the reading reference information carried by the read command packet comprises first mapping information indicating a first mapping relationship and comprises the dedicated bit information, and the reading reference information represents a corresponding compact hybrid table entry of the multiple compact hybrid table entries of the compact hybrid table; the host device utilizes a memory controller within the memory device to determine at least one second mapping relationship according to the first mapping relationship and the dedicated bit information, for reading data of the data length that starts from the starting logical address; and the host device utilizes the memory controller to read the data from the NV memory for the host device at least according to the first mapping relationship and the at least one second mapping relationship.

According to some embodiments, the apparatus may comprise at least one portion (e.g. a portion or all) of the electronic device. For example, the apparatus may comprise the memory controller within the memory device. In another example, the apparatus may comprise the memory device. In some examples, the apparatus may comprise the electronic device or the host device within the electronic device. In addition, the memory controller can be configured to control operations of the memory device according to the method, and the NV memory (e.g. a Flash memory) comprising the at least one NV memory element (e.g. one or more Flash memory dies, or one or more Flash memory chip) can be configured to store data. Examples of the memory device may include, but are not limited to: a memory card, a solid state drive, etc. Examples of the host device may include, but are not limited to: a multifunctional mobile phone, a tablet, a personal computer such as a laptop computer and a desktop computer. Additionally, the memory device can be configured to store data for the host device. The memory device can be configured to read the stored data in response to a host command from the host device, and provide the host device with the data read from the NV memory. In order to enhance the performance of the memory device, the host device can be configured to obtain some internal information of the memory device. The host device can be configured to send back the internal information previously obtained from the memory device toward the memory device, to allow the memory device to use the internal information, where the memory device can utilize and share the RAM of the host device. According to some embodiments, the host device and the memory device can adopt one or more better packet formats to optimize communications between the host device and the memory device. For example, the one or more better packet formats can be configured to carry dedicated bit information to indicate more than one physical address, to reduce the number of packets between the host device and the memory device.

The present invention method and apparatus can guarantee that the memory device can operate properly in various situations. For example, the internal information sent from the host device may be incorrect, and the present invention method and apparatus can detect this situation and prevent malfunction, etc. of the memory device. In addition, the information may be altered, and the present invention method and apparatus can detect this situation and prevent some security issues. Additionally, the present invention method and apparatus can provide the one or more better packet formats to optimize communications between the host device and the memory device, to make the whole system be suitable for operating according to one or more newer specifications (e.g. Host Performance Booster (HPB) 2.0 supposed to be promoted together with Universal Flash Storage (UFS) 3.1) and to improve the random read speed of the memory device.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

