This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0045834, filed on Apr. 16, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

1. Technical Field

The present disclosure relates to a semiconductor device.

2. Description of the Related Art

Recently, with rapid spread of information media, functions of semiconductor devices have also been dramatically developed. In semiconductor products, low cost in manufacture and/or operation is beneficial for securement of competitiveness, and high integration of products is beneficial for miniaturization of products. For high integration, semiconductor devices are being scaled down.

On the other hand, as a pitch size decreases, it is beneficial to reduce capacitance between elements/signal lines and to secure electrical stability between contacts in semiconductor devices.

SUMMARY

Aspects of the present disclosure provide a semiconductor device capable of effectively controlling threshold voltages (Vt) of transistors in different regions, by differently forming thicknesses and heights of work function films of gate structures of transistors each disposed in different regions.

According to an exemplary embodiment of the present disclosure, there is provided a semiconductor device comprising a substrate including a first region and a second region, a first gate structure extending in a first direction on the first region of the substrate, the first gate structure including a first gate insulation film and a first work function film disposed on the first gate insulation film, and a second gate structure extending in the first direction on the second region of the substrate, the second gate structure including a second gate insulation film and a second work function film disposed on the second gate insulation film, wherein a first thickness of the first work function film in a second direction intersecting the first direction is different from a second thickness of the second work function film in the second direction, and wherein a first height of the first work function film in a third direction perpendicular to the first and second directions is different from a second height of the second work function film in the third direction.

According to an exemplary embodiment of the present disclosure, there is provided a semiconductor device comprising a substrate including a first region and a second region, a first gate structure extending in a first direction on the first region of the substrate, the first gate structure including a first work function film and a first filling conductive film disposed inside a first recess defined by the first work function film, and a second gate structure extending in the first direction on the second region of the substrate, the second gate structure including a second work function film and a second filling conductive film disposed inside a second recess defined by the second work function film, wherein a first width of the first filling conductive film disposed inside the first recess in a second direction intersecting the first direction is different from a second width of the second filling conductive film disposed inside the second recess in the second direction, and wherein a first height of the first work function film in a third direction perpendicular to the first and second directions is different from a second height of the second work function film in the third direction.

According to an exemplary embodiment of the present disclosure, there is provided a semiconductor device comprising a substrate including an NMOS region and a PMOS region, a first active pattern extending in a first direction on the NMOS region of the substrate, a first gate structure extending in a second direction intersecting the first direction on the first active pattern of the NMOS region, the first gate structure including a first gate insulation film, a first work function film conformally formed on the first gate insulation film, and a first filling conductive film disposed on the first work function film, a second active pattern extending in the first direction on the PMOS region of the substrate, a second gate structure extending in the second direction on the second active pattern of the PMOS region, the second gate structure including a second gate insulation film, a second work function film conformally formed on the second gate insulation film, and a second filling conductive film disposed on the second work function film, a first source/drain region disposed on at least one side of the first gate structure, and a second source/drain region disposed on at least one side of the second gate structure, wherein a first thickness of the first work function film in the first direction is smaller than a second thickness of the second work function film in the first direction, and wherein a first height of the first work function film in a third direction perpendicular to the first and second directions is smaller than a second height of the second work function film in the third direction.

However, aspects of the present disclosure are not restricted to the ones set forth herein. The above and other aspects of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

