FIELD

The embodiments of the present invention relate to a semiconductor storage device.

BACKGROUND

A 1T (Transistor)-1C (Capacitor) semiconductor storage device that uses a vertical transistor as a switching transistor is being developed in recent years. The vertical transistor uses, as a channel, a semiconductor pillar extending substantially perpendicularly to a main surface of a semiconductor substrate, and includes a gate electrode (a word line) that extends substantially in parallel to the main surface, around the semiconductor pillar.

In order to increase an on-current (a current driving capability) of this vertical transistor, it is considered to make the semiconductor pillar thick to increase the gate width of the vertical transistor. However, when the semiconductor pillar is made thick, the word line therearound becomes narrower, resulting in increase of the word line resistance. Alternatively, it is necessary to increase the width of the word line in order to keep the word line resistance low. Further, making the semiconductor pillar thick or increasing the width of the word line is disadvantageous to downsizing of a memory cell array.

Accordingly, the current driving capability of the vertical transistor and downsizing of the memory cell array have a trade-off relation.

