BACKGROUND

Graphics processing systems are configured to receive graphics data, e.g. from an application (e.g. a game application) running on a computer system, and to render an image from the graphics data to provide a rendering output. For example, an application may generate a 3D model of a scene and output geometry data representing the objects in the scene. In particular, the application may represent each object using one or more primitives (i.e. simple geometric shapes, such as, but not limited to rectangles, triangles, lines and points to which a texture can be applied) which are defined by the position of one or more vertices. In these cases, the geometry data output by the application may include information identifying each vertex (e.g. the coordinates of the vertex in world space) and information indicating the primitives formed by the vertices. The graphics processing system then converts the received geometry data into an image that may be displayed on a screen.

A graphics processing system may, for example, implement immediate mode rendering (IMR) or tile-based rendering (TBR). In IMR the entire scene is rendered as a whole. In contrast, in TBR a scene is rendered using a rendering space which is divided into subsections, which are referred to as tiles, wherein at least a portion of the rendering process may be performed independently for each tile. The tiles may have any suitable shape, but are typically rectangular (wherein the term “rectangular” includes square). An advantage of TBR is that fast, on-chip memory can be used during the rendering for colour, depth and stencil buffer operations, which allows a significant reduction in system memory bandwidth over IMR, without requiring on-chip memory that is large enough to store data for the entire scene at the same time.

TBR involves two key phases: a geometry processing phase; and a rasterization phase. During the geometry processing phase the geometry data (e.g. vertices defining primitives) received from an application (e.g. a game application) is transformed from world space coordinates into screen space coordinates. A per-tile list is then created of the transformed primitives (e.g. triangles) that, at least partially, fall within the bounds of the tile. During the rasterization phase each tile is rendered separately (i.e. the transformed primitives are mapped to pixels and the colour is identified for each pixel in the tile). This may comprise identifying which primitive(s) are visible at each pixel. The colour of each pixel may then be determined by the appearance of the visible primitive(s) at that pixel which may be defined by a texture applied at that pixel and/or the pixel shader program run on that pixel. A pixel shader program describes operations that are to be performed for given pixels. Rendering each tile separately enables the graphics processing system to only retrieve the transformed primitive data related to a particular tile when rendering that tile in the rasterization phase, which keeps bandwidth requirements for the memory (e.g. intermediate buffer) low. Once a colour value has been identified for each pixel in a tile the colour values for the tile are written out to memory (e.g. a frame buffer). Once the entire scene has been rendered (i.e. once colour values have been determined for the pixels of all of the tiles) the scene may be, for example, displayed on a screen.

FIG.1illustrates an example TBR graphics processing system100. The system100comprises memory1021,1022,1023,1024, geometry processing logic104and rasterization logic106. Two or more of the memories1021,1022,1023, and1024may be implemented in the same physical unit of memory.

The geometry processing logic104implements the geometry processing phase of TBR. The geometry processing logic104comprises transformation logic108, a primitive block generator110, and a tiling engine112. The transformation logic108receives geometry data (e.g. vertices, primitives and/or patches) from an application (e.g. a game application) and transforms the geometry data into the rendering space (e.g. screen space). The transformation logic108may also perform functions such as clipping and culling to remove geometry data (e.g. primitives or patches) that falls outside of a viewing frustum, and/or apply lighting/attribute processing as is known to those of skill in the art.

The primitive block generator110stores the transformed primitives (i.e. the transformed geometry data related thereto) in memory1022in primitive blocks. A primitive block is a data structure in which one or more primitives (e.g. the transformed geometry data related thereto) are stored together. Storing the primitives in primitive blocks may allow the transformed geometry data for a set of primitives to be stored more efficiently in memory1022. Specifically, the transformed geometry data for a primitive often comprises transformed vertex information for a plurality of vertices where the vertices are shared between (or are common to) multiple primitives. Accordingly, where multiple primitives in the same primitive block share a vertex the data related to that vertex only needs to be stored once in the primitive block.

The transformed primitives may be grouped into primitive blocks using any suitable method or technique. For example, in some cases the transformed primitives may be grouped into primitive blocks based on the order in which the transformed primitives arrive at the primitive block generator110. In these cases, each primitive block may have a maximum size (e.g. in terms of bits or bytes), a maximum number of primitives which can belong to a primitive block, and/or a maximum number of vertices that can belong to a primitive block and the primitive block generator110may be configured to add primitives to a current primitive block until one or more of the maximums is reached.

In other cases, the primitives may be grouped into primitives based on their location in the render space so that spatially similar primitives are in the same primitive block. For example, the rendering space may be divided into macro regions which may encompass multiple tiles (e.g. a 1024×1024 rendering space that is divided into one thousand twenty-four 32×32 tiles may have sixteen 256×256 macro regions) and the primitive block generator110may be configured to maintain a primitive block for each macro region. Then when the primitive block generator110receives a primitive it determines which macro region(s) the primitive, at least partially, falls within. If the primitive block generator110determines that the primitive falls, at least partially, within only one macro region, then the primitive block generator110may place the primitive (i.e. the transformed geometry data related to that primitive) in the primitive block for that macro region. If the primitive block generator110determines that the primitive falls within more than one macro region then the primitive block generator110may be configured to (i) select one of the macro regions the primitive falls within (e.g. the first one) and place the primitive (i.e. the transformed geometry data related thereto) in the primitive block for the selected macro region; or (ii) place the primitive (i.e. the transformed geometry data related thereto) in the primitive block for each of the macro regions the primitive falls, at least partially, within.

The primitive blocks along with information identifying the location of the primitive blocks in memory are provided to the tiling engine112. The tiling engine112generates, from the transformed geometry data, a list, for each tile, of the transformed primitives that fall, at least partially, within that tile. The list may be referred to as a display list or a transformed display list. In some cases, the transformed display lists may comprise pointers or links to the transformed geometry data (e.g. vertex data) related to the primitives that, at least partially, fall within the tile. For example,FIG.2shows an example display list202for a tile which comprises a primitive block entry204,206for each primitive block that comprises at least one primitive that falls, at least partially, within the bounds of that tile. Each primitive block entry204,206, comprises information208identifying the location of the primitive block in memory (e.g. an address of the primitive block in memory) and information210identifying which primitives of that primitive block fall, at least partially, within the bounds of the tile. As shown inFIG.2the information identifying which primitives of the primitive block fall, at least partially, within a tile may be in the form of a mask that comprises a bit for each primitive in the primitive block that indicates whether or not that primitive falls, at least partially, within the bounds of the tile.

Returning toFIG.1, the rasterization logic106implements the rasterization phase of TBR. Specifically, the rasterization logic106renders the primitives in a tile-by-tile manner by fetching the display list for a tile from memory1023and then fetching the transformed geometry data from memory1022for the primitives that fall within the tile as indicated by the display list for that tile; and rendering the primitives for that tile based on the transformed geometry data.

In some cases, the rasterization logic106may comprise a rasterizer114, hidden surface removal (HSR) logic116and texturing/shading logic118. In these cases, the rasterizer114fetches each of the display lists from memory1023and for each display list fetches the transformed geometry data from memory1022for the primitives that fall within a tile as specified by the corresponding display list, and converts each primitive into a set of primitive fragments. The term “fragment” is used herein to mean a sample of a primitive at a sampling point, which is to be processed to render pixels of an image. In some examples, there may be a one-to-one mapping of pixels to fragments. However, in other examples there may be more fragments than pixels, and this oversampling can allow for higher quality rendering of pixel values, e.g. by facilitating anti-aliasing and other filters that may be applied to multiple fragments for rendering each of the pixel values.

The primitive fragments for a particular tile are then provided to the HSR logic116which removes primitive fragments which are hidden (e.g. hidden by other primitive fragments) by performing depth testing on the primitive fragments. The remaining fragments (after hidden surface removal) are then passed to the texturing/shading logic118which performs texturing and/or shading on the primitive fragments to determine pixel values of a rendered image. The rendered pixel values for a tile are then stored in memory1024(e.g. frame buffer).

The rasterization logic106processes each of the tiles and when the whole image has been rendered and stored in the memory1024(e.g. frame buffer) the image can be output from the graphics processing system100and used in any suitable manner, for example, displayed on a display, stored in memory, or transmitted to another device, etc. The TBR graphics processing system100shown inFIG.1is a “deferred” rendering system in the sense that fragments are processed by the HSR logic116before being processed by the texturing/shading logic118. In other examples, the graphics processing system might not be a deferred rendering system in which case texturing/shading would be applied to fragments before HSR is applied to those fragments.

Although the geometry processing logic is shown in the figures as being separate to the rasterization logic, in some implementations the geometry processing logic and the rasterization logic may share some resources. For example, the graphics processing system could use a unified shading approach wherein the same physical execution units can be used to execute instructions for use in the geometry processing phase (e.g. to perform vertex processing) and to execute instructions for use in the rasterization phase (e.g. to perform fragment processing).

The embodiments described below are provided by way of example only and are not limiting of implementations which solve any or all of the disadvantages of known methods and systems for tiling primitives in a graphics processing system.

SUMMARY

This summary is provided to introduce a selection of concepts that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

Described herein are data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for that primitive block. Each primitive block may comprise valid tile information identifying which tiles of the tile group are valid for the primitive block. A tile is a valid tile for a primitive block if at least one primitive in the primitive block intersects that tile.

A first aspect provides a method of tiling primitives in a tile based graphics processing system in which a rendering space is divided into a plurality of tiles, the plurality of tiles being grouped into a plurality of tile groups each comprising at least two tiles, the method comprising, for a tile group: determining, for each tile of the tile group, which primitives of each of a plurality of primitive blocks intersect that tile, each primitive block comprising at least one primitive; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream, the control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block.

Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block, a tile may be a valid tile for a primitive block if at least one primitive in the primitive block intersects that tile.

The valid tile information may comprise a valid tile mask which comprises a bit for each tile in the tile group which indicates whether that tile is a valid tile for the primitive block.

The control stream may comprise at least one other type of entry, each of the at least one other type of entry may comprise valid tile information that indicates that none of the tiles of the tile group are valid tiles.

Each control data block may comprise information identifying which primitives of the corresponding primitive block intersect each tile.

At least one control data block may comprise at least one primitive mask which comprises a bit for each primitive in the corresponding primitive block that identifies whether or not that primitive intersects a set of one or more tiles of the tile group.

At least one control data block may comprise a primitive mask for each tile of the tile group that intersects at least one primitive in the corresponding primitive block, each primitive mask may comprise a bit for each primitive in the corresponding primitive block that identifies whether or not that primitive intersects the corresponding tile.

Each control data block may comprise information identifying an address of the corresponding primitive block in memory.

Each control data block may comprise a primitive block header that indicates: whether one or more of the tiles of the tile group intersect the same primitives of the corresponding primitive block and/or whether one or more of the tiles of the tile group intersect all of the primitives in the corresponding primitive block.

Each primitive block entry may comprise a data pointer that identifies the location in memory of the corresponding control data block; the control stream may comprise at least one control data base address entry which specifies at least a portion of a control data base address; and an address of a control data block in memory may be generated from a combination of the control data base address and the data pointer of the corresponding primitive block entry.

Each data pointer may comprise an offset into a portion of memory identified by the control data base address.

Each control data base address entry may specify a complete control data base address.

Each control data base address entry may specify only a portion of a complete control data base address.

The control stream may comprise a first control data base address entry that specifies a first portion of the control data base address and a second control data base address entry that specifies a second portion of the control data base address.

Each primitive block entry may comprise a primitive block header that comprises information that describes the corresponding primitive block and/or the corresponding control data block.

Storing the control stream in memory may comprises dividing the control stream entries into a plurality of control stream blocks; wherein a last entry in each control stream block, other than the last control stream block, may be a link entry which identifies a location of a next control stream block in memory.

The control stream may further comprise a termination entry which identifies an end of the control stream, the termination entry may be a last entry in the control stream.

Each primitive block entry may be 32-bits.

Each tile group may comprise an N×M block of tiles in the render space wherein N and M are integers greater than or equal to 1. N and M may be equal to 2.

A second aspect provides a tiling engine for use in a graphics processing system for tiling primitives into tiles in a tile group of a rendering space, the tiling engine comprising: tiling logic configured to determine, for each tile of the tile group, which primitives of each of a plurality of primitive blocks intersect that tile, each primitive block comprising at least one primitive; a control data block generator configured to store in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and a control stream generator configured to store in memory a control stream, the control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block.

A third aspect provides a method of decoding a control stream for a tile group comprising at least two tiles of a rendering space, the method comprising: receiving a control stream for the tile group, the control stream comprising one or more fixed length primitive block entries, each primitive block entry identifying a location in memory of a control data block for the corresponding primitive block; for at least one of the primitive block entries: (a) determining whether a current tile of the tile group is valid for the corresponding primitive block, a tile being a valid tile for a primitive block if at least one primitive in the primitive block intersects that tile; (b) in response to determining that the current tile is valid for the corresponding primitive block, retrieving the corresponding control data block from the identified location in memory; (c) identifying, from the retrieved control data block, an address of the primitive block in memory and the primitives of that primitive block relevant for rendering the current tile; and (d) outputting information identifying the address of the primitive block in memory and the primitives of that primitive block relevant for rendering the current tile.

Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block; and the method may further comprise for a group of entries of the control stream: selecting a portion of the valid tile information for each entry of the group of entries corresponding to the current tile; performing an operation on the selected portions to determine whether the current tile is valid for any of the primitive block entries in the group of entries; and only performing (a)-(d) for the primitive block entries in the group of entries if a result of the operation indicates that the current tile is valid for at least one of the primitive block entries in the group of entries.

The valid tile information for each entry may comprise a valid mask with a bit for each tile of the tile group that indicates whether that tile is valid for the entry; the selected portion of the valid tile information for each entry may be the bit of the valid tile mask that corresponds to the current tile; and the operation that is performed on the selected portions may be an OR operation.

A fourth aspect provides a control stream decoder for decoding a control stream for a tile group comprising at least two tiles of a rendering space, the control stream decoder comprising: a fetch module configured to fetch a control stream for the tile group from memory, the control stream comprising one or more fixed length primitive block entries, each primitive block entry identifying a location in memory of a control data block for the corresponding primitive block; a primitive block entry analyser which is configured to, for at least one of the one or more primitive block entries: determine whether a current tile of the tile group is valid for the corresponding primitive block, a tile being a valid tile for a primitive block if at least one primitive in the primitive block intersects that tile; in response to determining that the current tile is a valid tile for the corresponding primitive block, retrieve the corresponding control data bock from the identified location in memory; identify, from the retrieved control data block, an address of the primitive block in memory and the primitives of that primitive block relevant for rendering the current tile; and output information identifying the address of the primitive block in memory and the primitives of that primitive block relevant for rendering the current tile.

A fifth aspect provides a method of tiling primitives in a tile based graphics processing system in which a rendering space is divided into a plurality of tiles, the plurality of tiles being grouped into a plurality of tile groups each comprising at least two tiles, the method comprising, for a tile group: determining, for each tile of the tile group, which primitives of each of a plurality of primitive blocks intersect that tile, each primitive block comprising at least one primitive; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream, the control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry comprising (i) valid tile information identifying which tiles of the tile group are valid for the primitive block, and (ii) a data pointer identifying a location in memory of the control data block for that primitive block, a tile being a valid tile for a primitive block if at least one primitive in the primitive block intersects that tile.

A sixth aspect provides a tiling engine for use in a graphics processing system for tiling primitives into tiles in a tile group of a rendering space, the tiling engine comprising: tiling logic configured to determine, for each tile of the tile group, which primitives of each of a plurality of primitive blocks intersect that tile, each primitive block comprising at least one primitive; a control data generator configured to store in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and a control stream generator configured to store in memory a control stream, the control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry comprising (i) valid tile information identifying which tiles of the tile group are valid for the primitive block, and (ii) a data pointer identifying a location in memory of the control data block for that primitive block, a tile being a valid tile for a primitive block if at least one primitive in the primitive block intersects that tile.

A seventh aspect provides a method of decoding a control stream for a tile group comprising at least two tiles of a rendering space to generate a display list for a current tile in the tile group, the method comprises: receiving a control stream for the tile group, the control stream comprising one or more fixed length primitive block entries, each primitive block entry comprising (i) valid tile information identifying which tiles of the tile group are valid for the primitive block, and (ii) a data pointer identifying a location in memory of a control data block for that primitive block, a tile being a valid tile for a primitive block if at least one primitive in the primitive block intersects that tile; for at least one of the primitive block entries: determining, from the valid tile information whether the current tile is valid for the corresponding primitive block; in response to determining that the current tile is valid for the corresponding primitive block, identifying, from the data pointer, an address of the corresponding control data block in memory; retrieving the corresponding control data block from the identified address in memory; identifying, from the retrieved control data block, an address of the primitive block in memory and the primitives of that primitive block relevant for rendering the current tile; and outputting information identifying the address of the primitive block in memory and the primitives of that primitive block relevant for rendering the current tile.

An eighth aspect provides a control stream decoder for decoding a control stream for a tile group comprising at least two tiles of a rendering space to generate a display list for a current tile in the tile group, the control stream decoder comprising: fetch module configured to fetch a control stream for the tile group from memory, the control stream comprising one or more fixed length primitive block entries, each primitive block entry comprising (i) valid tile information identifying which tiles of the tile group are valid for the primitive block, and (ii) a data pointer identifying a location in memory of a control data block for that primitive block, a tile being a valid tile for a primitive block if at least one primitive in the primitive block intersects that tile; a primitive block entry analyser which is configured to, for at least one of the primitive block entries: determine, from the valid tile information whether the current tile is valid for the corresponding primitive block; in response to determining that the current tile is valid for the corresponding primitive block, identify, from the data pointer, an address of the corresponding control data block in memory; retrieve the corresponding control data block from the identified address in memory; identify, from the retrieved control data block, an address of the primitive block in memory and the primitives of that primitive block relevant for rendering the current tile; and output information identifying the address of the primitive block in memory and the primitives of that primitive block relevant for rendering the current tile.

The tiling engines, control stream decoders and graphics processing systems described herein may be embodied in hardware on an integrated circuit. There may be provided a method of manufacturing, at an integrated circuit manufacturing system, an integrated circuit embodying a tiling engine, a control stream decoder and/or a graphics processing system described herein. There may be provided an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the system to manufacture an integrated circuit embodying a tiling engine, a control stream decoder or a graphics processing system described herein. There may be provided a non-transitory computer readable storage medium having stored thereon a computer readable description of a tiling engine, a control stream decoder or a graphics processing system described herein that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the tiling engine, the control stream decoder or the graphics processing system.

There may be provided an integrated circuit manufacturing system comprising: a non-transitory computer readable storage medium having stored thereon a computer readable description of a tiling engine, a control stream decoder or a graphics processing system described herein; a layout processing system configured to process the computer readable description so as to generate a circuit layout description of an integrated circuit embodying the tiling engine, the control stream decoder or the graphics processing system; and an integrated circuit generation system configured to manufacture an integrated circuit embodying the tiling engine, the control stream decoder or the graphics processing system according to the circuit layout description.

There may be provided computer program code for performing a method as described herein. There may be provided non-transitory computer readable storage medium having stored thereon computer readable instructions that, when executed at a computer system, cause the computer system to perform the methods as described herein.

The above features may be combined as appropriate, as would be apparent to a skilled person, and may be combined with any of the aspects of the examples described herein.

