PRIORITY CLAIM

This application claims the priority benefit of French Application for Patent No. 1908778, filed on Jul. 31, 2019, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.

TECHNICAL FIELD

Implementations relate to the processes for fabricating integrated circuits and, in particular, to the operation for defining an effective channel length in the fabrication of metal-oxide-semiconductor field-effect transistors (MOSFETs).

BACKGROUND

The fabrication of metal-oxide-semiconductor field-effect transistors (MOSFETs) typically comprises a step of forming a gate region and a step of implanting lightly doped drain (LDD) regions.

Typically, the operation of forming the gate region for MOSFETs comprises an operation of forming a conductive polycrystalline silicon layer and an operation of lithographically etching the polycrystalline silicon layer using a mask. The lithographic etching of the gate regions is typically a critical step in the process, in particular in the alignment of the mask and the precision, selectivity and complexity of the etching chemistry, thus the cost of forming the gate regions is very high.

The operation of implanting the lightly doped drain regions typically comprises an implantation operation that is self-aligned with the gate region, where the gate region acts as a mask that defines the implanted regions.

As such, the effective channel length, i.e. the distance between the two lightly doped drain regions below the gate, is determined by the alignment of the implanted zones with the geometry of the gate region (taking into account in particular the diffusion of the dopants).

However, the effective channel length determines critical characteristics of MOSFETs such as threshold voltage, leakage current or the breakdown voltage of the transistors.

It would be desirable to be able to adjust the processes for fabricating integrated circuits so as to modify the characteristics of MOSFETs at lower cost.

SUMMARY

To this end, what is proposed according to one aspect is a process for fabricating metal-oxide-semiconductor field-effect transistors (MOSFETs), comprising a first step of implanting lightly doped regions on either side of the site for future gate regions and a second step of forming the gate regions with a physical gate length that is associated with a reference channel length. The first step is carried out before the second step, and the first step comprises an operation of forming an implantation mask defining the lightly doped regions and an effective channel length of each MOSFET, the operation of forming the implantation mask being configured to define an effective channel length of at least one MOSFET that is different from the respective reference channel length.

The lightly doped regions on either side of the gate region are commonly referred to as lightly doped drain regions regardless of the side of the gate region that actually accommodates the source region or the drain region.

Thus, the implantation mask is not dependent on the gate region and the effective channel length of each MOSFET is no longer dependent on the physical gate length of the transistor. As such, it is possible to vary the effective channel length without modifying the step of forming the gate regions, which is typically the most expensive step. Integrated circuits of the same design may then exhibit different configurations, for example one being fast and another exhibiting low consumption, or else be corrected or adjusted at lower cost. The cost decrease may also facilitate the fabrication of experimental products.

According to one implementation, the operation of forming the implantation mask is configured to define the effective channel length of at least one first MOSFET to be shorter than the respective reference channel length.

This makes it possible, in particular, to decrease the threshold voltage of the MOSFET, for example for producing fast transistors.

According to one implementation, the operation of forming the implantation mask is configured to define the effective channel length of at least one second MOSFET to be longer than the respective reference channel length.

This makes it possible, in particular, to decrease the leakage currents of the MOSFET, for example for producing an integrated circuit exhibiting low consumption.

According to one implementation, the operation of forming the implantation mask is configured to define the effective channel length of at least one third MOSFET to be zero or short enough that the third MOSFET is always on.

According to one implementation, the operation of forming the implantation mask is configured to define the effective channel length of at least one fourth MOSFET to be long enough that the fourth MOSFET is always off.

Of course, the terms “always on” and “always off” should be understood relative to the conditions of use for which the third and fourth transistor are intended.

These implementations are, for example, applicable to embodiments of decoys against reverse engineering.

Advantageously, when the fabrication of the MOSFETs further comprises an operation of forming dielectric spacer regions on the flanks of the gate regions, the operation of forming the implantation mask may be configured to define the effective channel length of said at least one fourth MOSFET to be delimited to below the spacer regions.

In other words, the ends of the channel region, the effective length of which is long enough to confer always-off behavior, are hidden below the spacer regions and below the gate region. Thus, the effective channel length is more difficult to measure and this forms an additional means against reverse engineering.

According to one implementation in which the fabrication of the MOSFETs further comprises an operation of forming at least one lateral isolating region in contact with the channel region of at least one fifth MOSFET, the operation of forming the implantation mask is configured to define the effective channel length of said at least one fifth MOSFET so as to compensate for a variation in its characteristics due to parasitic edge effects with the lateral isolating region.

Typically, the lateral isolating regions are produced using a shallow-trench-isolation (STI) or a local-oxidation-of-silicon (LOCOS) process.

Parasitic edge effects, usually referred to as hump effects, may deform the desired characteristics, which are for example determined by the reference channel length that is associated with the physical gate length. The process according to this implementation may thus compensate for such deformation.

According to one implementation, said MOSFETs are fabricated on a semiconductor wafer, and the operation of forming the implantation mask is configured to define the effective channel length of the MOSFETs so as to compensate for a variation in the characteristics of the MOSFETs that is correlated with the position of each MOSFET on the wafer.

The process according to this implementation thus makes it possible to compensate for unwanted scatter in the characteristics of the transistors, which is dependent on the position of the circuit on the wafer.

According to one implementation, the implantation mask is formed using resist and photolithography.

The steps of forming a resist mask are typically much less expensive than the operation of forming the gate regions, and this implementation allows the costs of the process to be limited.

According to one alternative, the implantation mask is a hardmask.

This alternative may be advantageous in particular in the case that the hard mask is also already present in the overall process for fabricating the integrated circuit.

According to another aspect, a semiconductor device, for example a silicon wafer or an integrated-circuit chip, is also proposed, which device comprises at least one first transistor and at least one second transistor, said at least one first transistor and said at least one second transistor each including a gate region with a gate length that is associated with a reference channel length, and a channel region with an effective channel length, wherein the gate lengths of said at least one first transistor and said at least one second transistor are all equal, and the effective channel lengths of said at least one first transistor and of said at least one second transistor are different.

For example, the effective channel lengths of said at least one first transistor and said at least one second transistor are distinctly configured:to be equal to the reference channel length; orto be short enough that the transistor is always on; orto be long enough that the transistor is always off; orto compensate for a variation in the characteristics of the transistor due to parasitic edge effects with a lateral isolating region in contact with the channel region of the transistor; orto compensate for a variation in the characteristics of the transistor that is correlated with the position of the transistor on a semiconductor wafer incorporating the semiconductor device.

