CROSS-REFERENCE TO RELATED APPLICATION

This patent application is a U.S. National Phase Application under 35 U.S.C. § 371 of International Application No. PCT/US2016/040832, filed Jul. 1, 2016, entitled “DEVICE, METHOD AND SYSTEM FOR PROVIDING RECESSED INTERCONNECT STRUCTURES OF A SUBSTRATE,” which designates the United States of America, the entire disclosure of which is hereby incorporated by reference in its entirety and for all purposes.

BACKGROUND

1. Technical Field

Embodiments discussed herein relate generally to microelectronic devices and more particularly, but not exclusively, to structures for providing interconnection of circuitry via a substrate.

2. Background Art

Mobile, tablet, and ultrabook technologies require microelectronic devices with increasingly reduced dimensions, also known as a small form factor. Packaged semiconductor devices and other integrated circuit (IC) devices often include a substrate and one or more IC dies, passive circuit elements and/or other circuit components that contribute to horizontal (x-y plane) dimensions and vertical (z-axis) height, limiting the degree to which package form factor can be reduced.

As various technologies approach the lower limits of their respective form factors, there is an increasing demand for solutions that provide for incremental improvements in the efficiency of space taken up by microelectronic devices.

