TECHNICAL FIELD

This disclosure generally relates to non-volatile memories and, more specifically, to wear leveling associated with non-volatile memories.

BACKGROUND

Non-volatile memory devices include memory cell arrays that may be configured as a memory component that stores data values for access by various other components of a system. Memory cells may include memory elements that may degrade over time, by retaining valid data for less time, as the cells experience an increased number of program and erase operations (PE cycles). Such memory cells may include physical storage locations grouped in physical sectors that are mapped to logical addresses and sectors that represent the memory space of the memory cell array. Wear leveling may be implemented to change a physical location of data and spread wear from PE cycles across several physical sectors. However, such wear leveling may also move less frequently cycled data to physical sectors that have already experienced numerous PE cycles. Accordingly, wear leveling techniques may inadvertently reduce the retention time of data that rarely experiences PE cycles.

