TECHNICAL FIELD

The present application relates to the technical field of semiconductors, and in particular to a semiconductor structure and a manufacturing method thereof.

BACKGROUND

The semiconductor structure may include memory cells. The memory cell usually includes a transistor and a capacitor electrically connected to the transistor. The capacitor stores data information, and the transistor controls the reading and writing of data information in the capacitor. The gate of the transistor is electrically connected to a word line (WL), and the on and off of the transistor is controlled by the voltage on the WL. One of a source and a drain of the transistor is electrically connected to a bit line (BL), and the other of the source and the drain is electrically connected to the capacitor. Data information is stored or outputted by using the BL.

As a size of the semiconductor structure becomes more miniaturized, gate-all-around (GAA) transistors are usually used. In the related art, the GAA transistor includes a first conductive layer, a channel region, and a second conductive layer that are stacked sequentially. One of the first conductive layer and the second conductive layer is a source, and the other is a drain. A dielectric layer surrounds the side surface of the channel region, and a gate is disposed on the dielectric layer. However, the foregoing transistor has a relatively large contact resistance with another structure (for example, a BL or a capacitor), the transistor requires a relatively large current, and the semiconductor structure has poor performance.

SUMMARY

A first aspect of the embodiments of the present application provides a manufacturing method of a semiconductor structure, including: providing a substrate; forming a plurality of laminated structures arranged at intervals on the substrate, where each of the laminated structures includes a first conductive layer, an insulating layer, and a second conductive layer that are stacked sequentially, and at least one of the first conductive layer and the second conductive layer is a semi-metal layer; forming a channel layer covering the laminated structures, and a dielectric layer covering the channel layer; and forming WLs extending along a first direction, where the WL includes a plurality of contact parts and a connecting part connecting adjacent contact parts, the contact part surrounds and is in contact with a side surface of the dielectric layer, and the contact part is opposite to at least a part of the insulating layer.

A second aspect of the embodiments of the present application provides a semiconductor structure, including: laminated structures, a channel layer covering side surfaces of the laminated structures, and a dielectric layer covering a side surface of the channel layer, and a gate annularly provided on the dielectric layer, where each of the laminated structures includes a first conductive layer, an insulating layer, and a second conductive layer that are stacked sequentially, one of the first conductive layer and the second conductive layer is a source, the other of the first conductive layer and the second conductive layer is a drain, and at least one of the source and the drain is a semi-metal layer.

