FIELD OF THE DISCLOSED TECHNIQUES

The presently disclosed techniques relates to circuit testing. Various implementations of the disclosed techniques may be particularly useful for reducing the routing congestion associated with test compression circuits.

BACKGROUND OF THE DISCLOSED TECHNIQUES

Test compression is widely recognized as instrumental in reducing the overall cost of scan-based semiconductor device testing. With aggressive technology scaling, test stimuli compression along with test response compaction plays a key role in handling test data volume growth. The development of test compression schemes reflects ever-changing needs of many applications and addresses insatiable consumer demands for greater performance at a lower cost.

The compression hardware architecture includes logic circuitry inserted on the scan path. The logic circuitry typically has two main blocks: an on-chip decompressor that feeds test stimuli, derived from a small number of scan input channels, to a large number of scan chains, and one or multiple on-chip compactors that compact test responses captured and shifted out of the scan chains to a small number of scan output channels. Unlike compactors that can be associated with only a subset of scan chains, a centralized decompressor often drives thousands or even tens of thousands of scan chains. This can lead to severe routing congestion in a large design. Designers need to consider layout constraints during the design of decompressors. K. Chakravadhanula et al. disclosed a two-dimensional layout-aware test compression technique in “Advancing Test Compression to the Physical Dimension,” Proc. International Test Conference, 2017, Paper 10.2. This technique, however, has limitations because the layout of scan chains is typically unavailable yet when designers insert compression logic circuitry into designs at the register-transfer level (RTL). Even at the gate-level, the detailed layout may not be known. It is thus desirable to search for a decompression technology that can be inherently layout friendly and also do not sacrifice test coverage or test data volume.

BRIEF SUMMARY OF THE DISCLOSED TECHNIQUES

Various aspects of the disclosed technology relate to segmented decompressor designs. In one aspect, there is a circuit, comprising: a register configured to be a linear finite state machine and comprising storage elements, injection devices, one or more input channels for injecting variables using the injection devices, and one or more feedback devices; a plurality of phase shifters, each of the plurality of phase shifters configured to receive signals from a unique segment of the register; scan chains, serial inputs of the scan chains configured to receive signals from outputs of the plurality of phase shifters, wherein the one or more input channels are coupled to the injection devices at injection points in the register, each of the injection points being assigned to one of the one or more input channels based on lifespan values for the injection points, the injection points being determined based on one or more predetermined requirements, a life span value for an injection point in a specific segment of the register being a number of clock cycles for which a variable injected at the injection point can provide encoding capacity to scan chains associated with the specific segment of the register before being shifted out of the specific segment of the register.

The register may be a ring generator. At least one segment of the register providing signals to a phase shifter in the plurality of phase shifters may contain two groups of bits, bits in each of the two groups of storage elements forming a shift register, the shift register having one or more of the injection points, one or more points for inserting the feedback devices, or both.

The injection devices and the feedback devices may be XOR gates. Each of the plurality of phase shifters may comprise XOR gates.

The one or more predetermined requirements may comprise: a requirement that a feedback device and an injection device should not be located at the same location between two neighboring storage elements of the register, a requirement that any two of the injection devices should be separated by at least two neighboring storage elements of the register, or both.

The injection points in each segment of the register may be assigned to different input channels if a number of the injection points in the each segment of the register is less than or equal to a number of the one or more input channels, or each of the one or more input channels may be assigned to at least one of the injection points in each segment of the register if the number of the injection points in the each segment of the register is greater than the number of the one or more input channels.

The assignment of the injection points to the one or more input channels may employ a diagonal search method on a two-dimensional map which groups the injection points in each of the segments of the register in one of columns or rows of the two-dimensional map, the injection points in each of the columns or rows being ordered according to the life span values of the injection points.

Each of the one or more input channels may be assigned to at least one of the injection points in each segment of the register, and sums of the life span values for the injection points may be equal for the one or more input channels.

In another aspect, there are one or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising: creating a circuit in a circuit design for testing a chip fabricated according to the circuit design.

Certain inventive aspects are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims.

Certain objects and advantages of various inventive aspects have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the disclosed techniques. Thus, for example, those skilled in the art will recognize that the disclosed techniques may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

