BACKGROUND

Some example embodiments disclosed herein relate to semiconductor memory devices, and more particularly, relate to non-volatile memory devices and program methods thereof.

Semiconductor memory devices are classified as volatile semiconductor memory devices and non-volatile semiconductor memory devices. Volatile semiconductor memory devices have fast read and write speeds but lose data stored therein when power is disconnected therefrom. In contrast, non-volatile semiconductor memory devices retain data stored therein even when power is disconnected therefrom. For this reason, non-volatile semiconductor memory devices are used to store information that it is desirable to retain regardless of whether a power is supplied thereto.

A flash memory device may be an example of a non-volatile semiconductor memory device. Flash memory devices are used for storing voice and image data of information devices. Examples of such information devices include one or more of a computer, a cellular phone, a smartphone, a personal digital assistant (PDA), a handheld personal computer (PC), a game console, a facsimile, a scanner, and a printer. Semiconductor memory devices with three-dimensionally stacked memory cells are being developed to improve the degree of integration of the semiconductor memory devices.

A three-dimensional semiconductor memory device may include a cell string that is implemented by stacking memory cells in a direction perpendicular to a substrate to improve the degree of integration. However, there is a demand for maintaining the reliability of the three-dimensional semiconductor memory device together with improving the degree of integration. In particular, channel holes of cell strings of the three-dimensional semiconductor memory device are different in size depending on locations thereof due to an etching process. It would be desirable to develop a method of programming memory cells in consideration of this geometrical characteristic in the three-dimensional semiconductor memory device.

SUMMARY

Some example embodiments provide a non-volatile memory device performing a program operation in consideration of a geometrical structure of a cell string and a program method thereof.

According to some example embodiments, a program method of a non-volatile memory device, the non-volatile memory device including a peripheral circuit region and a memory cell region vertically connected to the peripheral circuit region, the peripheral circuit region including at least one first metal pad, the memory cell region including a cell substrate, a cell string, and at least one second metal pad directly connected with the at least one first metal pad, respectively, and the cell string in which a plurality of memory cells are stacked in a direction perpendicular to a surface of a cell substrate. The method comprises performing a first program phase including programming a first memory cell among the plurality of memory cells, the first memory cell being connected to a first word line among a plurality of word lines of the cell string, the first program phase including applying a first pass voltage from the peripheral circuit region to other word lines among the plurality of word lines above or below the first word line with respect to the cell substrate, and performing a second program phase including programming a second memory cell among the plurality of memory cells after the first memory cell is completely programmed, the second memory cell being connected to a second word line among the plurality of word lines closer to the cell substrate than the first word line, the second program phase including applying a second pass voltage from the peripheral circuit region to a first word line group among the plurality of word lines below the second word line with respect to the cell substrate and applying a third pass voltage from the peripheral circuit region to a second word line group among the plurality of word lines above the second word line with respect to the cell substrate, the second pass voltage being lower than the third pass voltage.

According to some example embodiments, a program method of a non-volatile memory device, the non-volatile memory device including a peripheral circuit region and a memory cell region vertically connected to the peripheral circuit region, the peripheral circuit region including at least one first metal pad, the memory cell region including a cell substrate, a cell string, and at least one second metal pad directly connected with the at least one first metal pad, respectively, and the cell string in which a plurality of memory cells are stacked in a direction perpendicular to a surface of a cell substrate. The method comprises performing a program verify phase including applying a verify voltage from the peripheral circuit region to a selected word line among a plurality of word lines of the cell string and applying a read pass voltage from the peripheral circuit region to a plurality of unselected word lines among the plurality of word lines to verify whether a selected memory cell among the plurality of memory cells is programmed, the selected word line being programmed before a first word line among the plurality of word lines closer to the cell substrate or after a second word line among the plurality of word lines more distant from the cell substrate, performing a first recovery phase including applying a first recovery voltage from the peripheral circuit region to the selected word line and the plurality of unselected word lines and applying a precharge voltage from the peripheral circuit region to a common source line of the cell string, and performing a second recovery phase including discharging at least one of the plurality of unselected word lines to a ground voltage from the peripheral circuit region.

According to some example embodiments, a non-volatile memory device comprising a memory cell region including at least one first metal pad and a memory cell array including a cell string in which a plurality of memory cells are stacked in a direction perpendicular to a surface of a cell substrate, and a peripheral circuit region vertically connected to the memory cell region and including at least one second metal pad, an address decoder, a page buffer and a control logic circuit, wherein the at least one second metal pad is directly connected to the at least one first metal pad, respectively, the address decoder is configured to select a word line among a plurality of word lines included in the cell string for programming the plurality of memory cells, the page buffer is configured to control a bit line of the cell string, and the control logic circuit is configured to control the address decoder and the page buffer such that a word line among the plurality of word lines furthest from the cell substrate is first programmed in a program operation, and perform a recovery phase after a program verify operation, the recovery phase including applying a recovery voltage to a selected word line among the plurality of word lines and unselected word lines among the plurality of word lines, and the recovery phase including applying a precharge voltage to a common source line of the cell string.

