RELATED APPLICATION AND CLAIM OF PRIORITY

This application claims priority to Application No. EP19204152.3 filed Oct. 18, 2019 and titled “METHOD AND APPARATUS FOR INTEGRATING MACHINE LEARNING BASED TECHNIQUES TO IMPROVE COMPILATION OF FPGA BASED EMULATION AND PROTOTYPING SYSTEMS,” which is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to compilers used in the design of circuits or electrical components.

BACKGROUND

Designs for circuits or electrical components are programmed and compiled (e.g., for verification purposes). Program code for the designs can be written and compiled to create virtual circuits or electrical components. For example, code for designs may be compiled to simulate one or more field programmable gate arrays (FPGAs) that perform the operation of the designs. Test signals may then be sent through the virtual circuits or electrical components to test the designs.

SUMMARY

In one embodiment, a method includes generating a netlist for a circuit design and predicting, by applying a first machine learning model to the netlist, a first compile time for the circuit design. The method also includes predicting by applying a second machine learning model to the netlist, a first place and route strategy based on the first compile time. The method further includes adjusting a logic of the circuit design in accordance with the first place and route strategy.

The method includes may include predicting, by applying a third machine learning model to the adjusted logic, a second compile time for the circuit design and predicting, by applying a fourth machine learning model to the adjusted logic, a second place and route strategy based on the second compile time. The method may further include placing components of the circuit design in accordance with the second place and route strategy.

The method may include predicting, by applying a fifth machine learning model to the placed components, a third compile time for the circuit design and predicting, by applying a sixth machine learning model to the placed components, a third place and route strategy based on the third co[mile time. The method may also include routing the components in accordance with the third place and route strategy.

The method may include generating a bitstream in accordance with the routing of the components.

In some instances, the first and second machine learning models are part of a base model generated using base data and the base model was selected from a group that includes the base model, a tuned model generated using training data generated by compiling a plurality of circuit designs, and a hybrid model generated using the training data and the base data.

The method may include selecting the base model in response to a determination that a first distance between the netlist and the circuit design is less than a second distance between the netlist and the training data used to generate the tuned model and a third distance between the netlist and the training data and the base data used to generate the hybrid model.

The method may include determining the first distance by applying a first weight to a distance between a first feature in the netlist and a first feature in the base data to produce a first weighted distance, applying a second weight to a distance between a second feature in the netlist and a second feature in the base data to produce a second weighted distance, and summing the first weighted distance and the second weighted distance.

The method may include launching a separate compilation of the circuit design. Adjusting the logic of the circuit design in accordance with the first place and route strategy occurs in the separately launched compilation.

In another embodiment, a method includes storing a base model generated using base data, receiving training data generated by compiling a plurality of circuit designs, and generating, using the training data, a tuned model. The method also includes generating, using the training data and the base data, a hybrid model, receiving a selected cost function, and biasing the base model, the tuned model, and the hybrid model using the selected cost function.

In some instances, the cost function is selected from a plurality of cost functions that include a first cost function that biases towards reducing compilation time, a second cost function that biases towards reducing resource consumption during compilation, and a third cost function that biases towards both reducing compilation time and reducing resource consumption during compilation.

The method may include generating a netlist for a circuit design and predicting, by applying a first machine learning model to the netlist, a first compile time for the circuit design. The method may also include predicting, by applying a second machine learning model to the netlist, a first place and route strategy based on the first compile time. The method may further include adjusting a logic of the circuit design in accordance with the first place and route strategy.

The method may include predicting, by applying a third machine learning model to the adjusted logic, a second compile time for the circuit design and predicting, by applying a fourth machine learning model to the adjusted logic, a second place and route strategy based on the second compile time. The method may also include placing components of the circuit design in accordance with the second place and route strategy.

The method may include predicting, by applying a fifth machine learning model to the placed components, a third compile time for the circuit design and predicting, by applying a sixth machine learning model to the placed components, a third place and route strategy based on the third compile time. The method may also include routing the components in accordance with the third place and route strategy.

The method may include generating a bitstream in accordance with the routing of the components.

The method may include selecting the base model in response to a determination that a first distance between the netlist and the circuit design is less than a second distance between the netlist and the training data used to generate the tuned model and a third distance between the netlist and the training data and the base data used to generate the hybrid model.

In another embodiment, an apparatus includes a memory and a hardware processor communicatively coupled to the memory. The hardware processor receives an instruction to compile a circuit design and in response to the instruction, generates a netlist for the circuit design. The hardware processor also predicts, by applying a first machine learning model to the netlist, a first compile time for the circuit design. The hardware processor further predicts, by applying a second machine learning model to the netlist, a first place and route strategy based on the first compile time and adjusts a logic of the circuit design in accordance with the first place and route strategy.

The hardware processor may predict, by applying a third machine learning model to the adjusted logic, a second compile time for the circuit design and predict, by applying a fourth machine learning model to the adjusted logic, a second place and route strategy based on the second compile time. The hardware processor may also place components of the circuit design in accordance with the second place and route strategy.

The hardware processor may predict, by applying a fifth machine learning model to the placed components, a third compile time for the circuit design and predict, by applying a sixth machine learning model to the placed components, a third place and route strategy based on the third compile time. The hardware processor may also route the components in accordance with the third place and route strategy.

The hardware processor may generate a bitstream in accordance with the routing of the components.

In some instances, the first and second machine learning models are part of a base model generated using base data and the base model was selected from a group that includes the base model, a tuned model generated using training data generated by compiling a plurality of circuit designs, and a hybrid model generated using the training data and the base data.

