RELATED APPLICATION(S)

This application is related to the following commonly owned applications:

U.S. patent application Ser. No. 17/338,620, entitled, “Variable-Length Clock Stretcher with Correction for Glitches Due to Finite DLL Bandwidth,” filed concurrently herewith;

U.S. patent application Ser. No. 17/338,626, entitled, “Variable-Length Clock Stretcher with Correction for Digital DLL Glitches,” filed concurrently herewith; and

U.S. patent application Ser. No. 17/338,629, entitled, “Variable-Length Clock Stretcher with Passive Mode Jitter Reduction,” filed concurrently herewith.

The related application(s) are hereby incorporated by reference herein for all purposes.

BACKGROUND

Technical Field

The disclosed embodiments relate generally to systems and methods used in clocking electronics, and in particular to those for adaptively clocking circuits with a variable load.

Context

Unless otherwise indicated herein, elements described in this section are not prior art to the claims and are not admitted being prior art by inclusion in this section.

Central Processing Units (CPUs), processors for Artificial Intelligence (AI) applications, and other clocked digital electronics may be implemented as systems on a chip (SoCs), often requiring a large amount of power to operate. Based on the overall processing requirements, and possibly software being executed, the instantaneous load on the supply power can vary sharply, which may result in sharp changes in the supply voltage. A droop in the supply voltage may slow down electronic circuits, and a peak may increase their speed. Both droops and peaks may therefore impact the operation of a processor. Especially droops may result in timing violations when a digital circuit operates from a clock whose frequency is too high for the imminent supply voltage and, consequently, the digital circuit may fail functionally. Even a single clock pulse that is too short must be considered a glitch that can result in timing violations and a functional failure. In general, a processor has a maximum clock frequency that depends on the supply voltage available. Thus, a clock for a processor operating at its maximum clock frequency may need to be slowed down when the processor supply voltage decreases. One system that can do so is a clock stretcher, which can stretch the length of one or more successive clock pulses to temporarily slow down a clock.

However, conventional clock stretchers require a clean supply themselves. They often employ a delay line whose delay directly depends on the supply voltage. Conventional solutions embed the delay line with a phase detector in an analog delay-locked loop (DLL), a negative feedback loop that counters the influence of the supply voltage on the delay. To ensure stability, the DLL feedback loop is designed with a limited bandwidth, and the DLL cannot keep up with supply voltage changes that are too fast. Conventionally, the delay line must have a high resolution, which increases power consumption and die area, and limits the clock frequency range. DLL phase detector offset can introduce further inaccuracies. Unfortunately, modern semiconductor fabrication processes make it difficult to design a phase detector with a low offset. An analog DLL is very dependent on having a dedicated clean power supply. This can be overcome by using a digital DLL, but a digital DLL operates in discrete time steps, which may cause a shortened clock pulse at the time of a DLL adjustment. The shortened clock pulse may cause timing violations and functional failure.

When a clock stretcher is integrated with a powerful processor, or other electronic system with sharply variable load, a clean supply may be expensive or not be readily available. Embodiments of the invention address several of the problems that may occur due to polluted supply voltages and due to using a digital DLL.

SUMMARY

Central Processing Units (CPUs), processors for Artificial Intelligence (AI) applications, and other clocked systems may be implemented as large systems on a chip (SoCs), requiring large power to operate. Based on the overall processing requirement, and software being executed, the instantaneous load on the supply power can vary sharply, which may result in sudden changes in the supply voltage. A droop in the supply voltage may slow down electronic circuits, and result in timing violations and functional failures. In general, a processor has a maximum clock frequency that depends on the available supply voltage. Thus, a clock for a processor operating at or near its maximum clock frequency may need to be slowed down when the processor supply voltage decreases.

Embodiments of the invention provide a clock stretcher that is operable to receive an input clock signal whose frequency is fixed and to output a modified clock signal whose frequency is equal to or lower than the received frequency, based on one or more sensed conditions. The sensed condition may include the voltage of supplied power. The clock stretcher may include a sense unit for sensing the condition, a delay-locked loop (DLL) for deriving a series of delayed versions of the input clock signal, a combiner for selecting one or more of the delayed versions of the input clock signal, and a control unit that receives information from the sense unit and the DLL and controls the DLL and the combiner to generate the modified clock as required. Embodiments may operate from the supplied power without intervening voltage regulation.

In a first aspect of the invention, an embodiment provides a method to correct glitches due to phase detector offset in a delay-locked loop (DLL) in the clock stretcher. The input clock signal includes input clock pulses with a clock cycle time T. The method includes the following steps. It delays the input clock pulses in a delay line in the DLL. The delay line includes delay stages. The DLL locks a delay of N1 stages to clock cycle time T, and forwards the N1 equidistant phases of the delayed input clock pulses to the combiner. The combiner cyclically selects at least one of the N1 equidistant phases with the clock stretcher output to generate the modified clock. For successive clock pulses, the combiner successively selects phases, where the step size is determined by a hop code dependent on the sensed condition. The method retrieves an offset skip parameter value os, and uses os during a phase selection wraparound to correct for a phase detector offset glitch.

In a second aspect of the invention, and embodiment provides a clock stretcher. The clock stretcher comprises a DLL that has a delay line with delay stages, an end-of-chain (EOC) detector, a required length interface that provides required length N1, and a control unit. The control unit receives a hop code h and an offset skip value os. It outputs a combiner control signal that includes a cyclical selection of N1 delay line phase output signals. The selection is based on N1, h, and the offset skip value os.

The embodiment calculates the selection by adding h to a previous phase p. It wraps phase selection around at N1 minus os, or at N1. If it wraps around at N1, the embodiment adds os to the calculated selection.

Particular aspects of the technology disclosed are described in the claims, specification and drawings.

