BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a semiconductor structure and a method of forming the same, and in particular to a semiconductor structure including nanosheet or nanowire transistors having improved electrical performance and a method of forming the same.

Description of the Related Art

In recent years, advanced integrated circuit (IC) devices have become increasingly multifunctional and have been scaled down in size. Although the scaling down process generally increases production efficiency and lowers the associated costs, it has also increased the complexity of processing and manufacturing IC devices. For example, Fin Field-Effect Transistors (FinFETs) have been introduced to replace planar transistors. Among these FinFETs, gate-all-around (GAA) structures such as nanosheet or nanowire metal-oxide-semiconductor field-effect transistors (MOSFET) have been developed to possess excellent electrical characteristics, such as better power performance and area scaling compared to the current FinFET technologies.

Although existing semiconductor structures including nanosheet or nanowire transistors and methods for forming the same have been adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, in a semiconductor structure including nanosheet or nanowire transistors, each of the semiconductor stacks over the substrate includes the same number of channel layers over the substrate. However, it is disadvantageous that the semiconductor stack for forming a low-power device includes as many channel layers as the semiconductor stack for forming a high-power device does. Too many channel layers constructed in the semiconductor stack for forming the low-power device would lead to a considerable amount of leakage current while the device is in operation. Therefore, there are still some problems to be overcome in regards to semiconductor structures that include nanosheet or nanowire transistors in the semiconductor integrated circuits and technology.

BRIEF SUMMARY OF THE INVENTION

Some embodiments of the present disclosure provide semiconductor structures. An exemplary embodiment of a semiconductor structure includes a first semiconductor stack and a second semiconductor stack formed over the first region and the second region of a substrate, respectively. The first semiconductor stack and the second semiconductor stack extend in the first direction and are spaced apart from each other in the second direction. The second direction is different from the first direction. In some embodiments, each of the first semiconductor stack and the second semiconductor stack includes channel layers and a gate structure. In some embodiments, the channel layers are formed above the substrate and are spaced apart from each other in the third direction, wherein the third direction is vertical to the first direction and the second direction. In some embodiments, the gate structure includes gate dielectric layers formed around the respective channel layers, and a gate electrode layer formed on the gate dielectric layers to surround the channel layers. The number of channel layers in the first semiconductor stack is different from the number of channel layers in the second semiconductor stack.

Some embodiments of the present disclosure provide a method of forming a semiconductor structure. First, a structure is provided, including a fin structure over a substrate, and the fin structure includes a stack of alternating channel layers and sacrificial layers within the stack; a sacrificial gate structure over the fin structure; source/drain features on opposite sides of the sacrificial gate structure, and the source/drain features are adjacent to the channel layers in the fin structure; and an interlayer dielectric (ILD) layer over the substrate and covering the source/drain features and exposing the sacrificial gate structure. The method of forming the semiconductor structure also includes removing the sacrificial gate structure, and removing the sacrificial layers in the fin structure so that the channel layers in the fin structure are exposed. The method of forming the semiconductor structure further includes removing a portion of the exposed channel layers, and forming a gate structure around the remaining portions of the exposed channel layers.

Some embodiments of the present disclosure provide semiconductor structures. An exemplary embodiment of another semiconductor structure includes semiconductor stacks over a substrate, wherein each of the semiconductor stacks extends in the first direction, and adjacent semiconductor stacks are spaced apart from each other in the second direction. In some embodiments, one of the semiconductor stacks includes channel layers and a gate structure. The channel layers are formed above the substrate and are spaced apart from each other in the third direction, wherein the third direction is vertical to the first direction and the second direction. In some embodiments, the gate structure includes gate dielectric layers formed around the respective channel layers, and a gate electrode layer formed on the gate dielectric layers to surround the channel layers. Also, the first distance is defined as the distance in the third direction between the top surface of the gate structure of the semiconductor stack and the top surface of an uppermost channel layer in the semiconductor stack. The second distance is defined as the distance in the third direction between adjacent channel layers in the semiconductor stack. In some embodiments, the first distance is greater than 1.3 times the second distance. In some embodiments, the first distance is equal to or greater than 1.5 times the second distance. In some embodiments, the first distance is equal to or greater than 2.0 times the second distance.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

