FIELD OF THE INVENTION

The present invention relates in general to a CMOS IC and, more particularly, to a feed-forward current compensation scheme for a CMOS signal path.

BACKGROUND OF THE INVENTION

In a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) that handles high-speed serial data, it is efficient to employ CMOS logic-style circuit elements, such as inverters and logic gates, in the high-speed serial data signal path. The supply current for the CMOS logic-style circuitry varies rapidly in response to the logic transitions in the input data.

FIG. 1illustrates a conventional CMOS signal path50propagating high speed serial differential data through an IC. Voltage regulator52includes amplifier54receiving reference voltage VREFat its inverting input. The output of amplifier54is coupled to the gate of transistor56. The drain of transistor56is coupled to power supply conductor58operating at a positive potential VDD, and the source of transistor56is coupled to node60. The non-inverting input of amplifier54is coupled to node60, which operates as a power supply rail to maintain a regulated output voltage VREG. CMOS signal path50receives an input data signal DATA IN at terminal70and the complement of DATA IN at terminal72. DATA IN propagates through series-coupled of inverters or buffers80, which receive positive operating potential from VREGand ground operating potential from power supply conductor82. The complement of DATA IN propagates through series-coupled inverters or buffers84, which receive positive operating potential from VREGand ground operating potential from power supply conductor82. Effective load capacitance90is seen on output terminal92, and effective load capacitance94is seen on output terminal96. Capacitor98is coupled between node60and power supply conductor82.

Voltage regulator52supplying series inverters80and84struggles to cope with the large and instantaneous demands for charge from its load. The limited bandwidth of typical regulators and the limited size of the on-chip decoupling capacitor can cause the inability of the regulator to maintain a constant supply voltage with rapid variations in current demand, manifesting as variations in the regulated supply voltage, also known as ripple. The ripple in the supply rail adds to jitter in the output data signal at terminals92and96, since it modulates the propagation delay of CMOS logic circuits. Low jitter is important, particularly with higher data rates. It is desirable to reduce ripple in VREG, for high-speed serial data signal path50using CMOS logic circuitry, with the objective of reducing jitter in the output signal.

For a signal path having substantial load capacitance, or many stages, and/or operating at high data rates, the absolute supply current ISUPcan be quite large, and therefore the absolute peak-to-peak variation in short-term supply current consumption can also be substantial. Voltage regulator52generating VREGfor power supply rail60can be internal to the CMOS IC, particularly where the IC contains multiple functions operating at various different supply voltages, or in applications requiring dedicated supplies for noise isolation. If voltage regulator52is unable to respond instantaneously to the variation in its load current, the regulated voltage VREGdeviates from its nominal value. Short-term variation in the data signal content therefore results in ripple on the supply voltage.

A characteristic of a CMOS logic circuit is that its propagation delay varies with supply voltage. Consequently, if the instantaneous value of supply voltage is varying dependent on the data content, the propagation delay of the CMOS signal path is continuously varying, and this manifests as timing jitter at output terminals92and96of CMOS signal path50. For systems processing high speed serial data signals, jitter is exceedingly critical to performance. Therefore, ripple on the supply voltage of CMOS signal path50is undesirable.

