CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119 on Korean Patent Application No. 10-2020-0077046, filed on Jun. 24, 2020, which is herein incorporated by reference in its entirety.

BACKGROUND

1. Field

Various embodiments described herein relate to a semiconductor design technology and, more particularly, to a synchronous semiconductor memory device.

2. Description of the Related Art

Semiconductor memory devices have been continuously improved to increase the degree of integration and to increase the operation speed thereof. To increase the operation speed, synchronous memory devices that can operate in synchronization with an external clock have been introduced. First proposed is a single data rate (SDR) synchronous memory device that inputs and outputs one data item over a period of a clock through one data pin in synchronization with a rising edge of the clock external to the memory device. However, since the SDR synchronous memory device is also insufficient to accommodate a system requiring high-speed operation, a double data rate (DDR) synchronous memory device, which processes two data items in one clock period, has been proposed.

More recently developed semiconductor memory devices have been designed to input/output 2 bits of data between a rising edge and a falling edge of an externally applied system clock so as to input/output data at high speed in a low power environment. In other words, the semiconductor memory device is designed to be able to input/output four bits of data in one period of the system clock. To that end, a data clock having a frequency twice that of the system clock is used in the semiconductor memory device. That is, the semiconductor memory device may input/output 4 bits of data in one period of the system clock by using the system clock to receive addresses and commands from the outside and the data clock to input/output data.

SUMMARY

According to embodiments, there is provided a semiconductor memory device capable of controlling the latency of a read command and a write command depending on a first operation mode differentiated according to a ratio of data clock (WCK) to system clock (CK), and a second operation mode differentiated according to an individual bank mode and a bank group mode.

According to an embodiment, a semiconductor memory device may include: a memory cell array including a plurality of banks; a command/address buffer suitable for receiving a command/address based on a system clock; a data input/output circuit suitable for inputting/outputting data based on a data clock; a mode control circuit suitable for generating a plurality of mode selection signals indicating different latencies according to a burst length signal and operation information on a first operation mode differentiated based on a ratio of the data clock to the system clock, and a second operation mode differentiated based on a bank mode; and a latency setting circuit suitable for setting a latency according to an activated one of the mode selection signals, generating an internal write command by delaying a write command at least by the set latency according to the system clock during a write operation, and generating an internal read command by delaying a read command by the set latency according to the system clock during a read operation.

According to an embodiment, a latency setting circuit may include: a clock driving circuit suitable for delaying a write clock by a latency corresponding to an activated one of a plurality of mode selection signals for setting different latencies and generating a write trigger signal, during a write operation; and a write latency circuit suitable for delaying a write command and latching the write command according to the write trigger signal to output an internal write command.

According to an embodiment, a latency setting circuit may include: a control signal generating circuit suitable for generating first to third control signals based on first to third mode selection signals for setting different latencies; a write trigger circuit suitable for generating first to third write division clocks by dividing a write clock by certain multiples according to the first to third control signals, and outputting one of the first to third write division clocks as a write trigger signal according to the first to third mode selection signals, during a write operation interval; a read trigger circuit suitable for generating first to third read division clocks by dividing a read clock by certain multiples according to the first to third control signals, and outputting one of the first to third read division clocks as a read trigger signal according to the first to third mode selection signals, during a read operation interval; a write latency circuit suitable for latching a write command according to the write trigger signal and outputting an internal write command; and a read latency circuit suitable for latching a read command according to the read trigger signal and outputting an internal read command.

According to an embodiment, an operating method of a semiconductor memory device, may include: delaying a write or a read command by a delay amount with reference to a system clock; and performing an operation based on the delayed write or read command and a data clock, wherein the delay amount depends on a combination of a burst length, a ratio of the data clock to the system clock and a bank mode of the memory device.

According to embodiments described herein, the semiconductor memory device may operate at high speed in a low power environment by optimizing the latency of the read command and write command depending on various operation modes.

According to embodiments described herein, the semiconductor memory device may minimize the area and current consumption by reducing the number of flip-flops provided to control the latency of the read command and write command.

