TECHNICAL FIELD

Integrated assemblies (e.g., assemblies including integrated memory). Methods of forming integrated assemblies. Methods of forming charge-blocking material associated with integrated memory.

BACKGROUND

Memory provides data storage for electronic systems. Flash memory is one type of memory, and has numerous uses in modern computers and devices. For instance, modern personal computers may have BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid state drives to replace conventional hard drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and to provide the ability to remotely upgrade the devices for enhanced features.

NAND may be a basic architecture of flash memory, and may be configured to comprise vertically-stacked memory cells.

Before describing NAND specifically, it may be helpful to more generally describe the relationship of a memory array within an integrated arrangement.FIG. 1shows a block diagram of a prior art device1000which includes a memory array1002having a plurality of memory cells1003arranged in rows and columns along with access lines1004(e.g., wordlines to conduct signals WL0through WLm) and first data lines1006(e.g., bitlines to conduct signals BL0through BLn). Access lines1004and first data lines1006may be used to transfer information to and from the memory cells1003. A row decoder1007and a column decoder1008decode address signals A0through AX on address lines1009to determine which ones of the memory cells1003are to be accessed. A sense amplifier circuit1015operates to determine the values of information read from the memory cells1003. An I/O circuit1017transfers values of information between the memory array1002and input/output (I/O) lines1005. Signals DQ0through DQN on the I/O lines1005can represent values of information read from or to be written into the memory cells1003. Other devices can communicate with the device1000through the I/O lines1005, the address lines1009, or the control lines1020. A memory control unit1018is used to control memory operations which are to be performed on the memory cells1003, and utilizes signals on the control lines1020. The device1000can receive supply voltage signals Vcc and Vss on a first supply line1030and a second supply line1032, respectively. The device1000includes a select circuit1040and an input/output (I/O) circuit1017. The select circuit1040can respond, via the I/O circuit1017, to signals CSEL1through CSELn to select signals on the first data lines1006and the second data lines1013that can represent the values of information to be read from or to be programmed into the memory cells1003. The column decoder1008can selectively activate the CSEL1through CSELn signals based on the A0through AX address signals on the address lines1009. The select circuit1040can select the signals on the first data lines1006and the second data lines1013to provide communication between the memory array1002and the I/O circuit1017during read and programming operations.

The memory array1002ofFIG. 1may be a NAND memory array, andFIG. 2shows a schematic diagram of a three-dimensional NAND memory device200which may be utilized for the memory array1002ofFIG. 1. The device200comprises a plurality of strings of charge-storage devices. In a first direction (Z-Z′), each string of charge-storage devices may comprise, for example, thirty-two charge-storage devices stacked over one another with each charge-storage device corresponding to one of, for example, thirty-two tiers (e.g., Tier0-Tier31). The charge-storage devices of a respective string may share a common channel region, such as one formed in a respective pillar of semiconductor material (e.g., polysilicon) about which the string of charge-storage devices is formed. In a second direction (X-X′), each first group of, for example, sixteen first groups of the plurality of strings may comprise, for example, eight strings sharing a plurality (e.g., thirty-two) of access lines (i.e., “global control gate (CG) lines”, also known as wordlines, WLs). Each of the access lines may couple the charge-storage devices within a tier. The charge-storage devices coupled by the same access line (and thus corresponding to the same tier) may be logically grouped into, for example, two pages, such as P0/P32, P1/P33, P2/P34and so on, when each charge-storage device comprises a cell capable of storing two bits of information. In a third direction (Y-Y′), each second group of, for example, eight second groups of the plurality of strings, may comprise sixteen strings coupled by a corresponding one of eight data lines. The size of a memory block may comprise 1,024 pages and total about 16 MB (e.g., 16 WLs×32 tiers×2 bits=1,024 pages/block, block size=1,024 pages×16 KB/page=16 MB). The number of the strings, tiers, access lines, data lines, first groups, second groups and/or pages may be greater or smaller than those shown inFIG. 2.

FIG. 3shows a cross-sectional view of a memory block300of the 3D NAND memory device200ofFIG. 2in an X-X′ direction, including fifteen strings of charge-storage devices in one of the sixteen first groups of strings described with respect toFIG. 2. The plurality of strings of the memory block300may be grouped into a plurality of subsets310,320,330(e.g., tile columns), such as tile columnI, tile columnjand tile columnK, with each subset (e.g., tile column) comprising a “partial block” of the memory block300. A global drain-side select gate (SGD) line340may be coupled to the SGDs of the plurality of strings. For example, the global SGD line340may be coupled to a plurality (e.g., three) of sub-SGD lines342,344,346with each sub-SGD line corresponding to a respective subset (e.g., tile column), via a corresponding one of a plurality (e.g., three) of sub-SGD drivers332,334,336. Each of the sub-SGD drivers332,334,336may concurrently couple or cut off the SGDs of the strings of a corresponding partial block (e.g., tile column) independently of those of other partial blocks. A global source-side select gate (SGS) line360may be coupled to the SGSs of the plurality of strings. For example, the global SGS line360may be coupled to a plurality of sub-SGS lines362,364,366with each sub-SGS line corresponding to the respective subset (e.g., tile column), via a corresponding one of a plurality of sub-SGS drivers322,324,326. Each of the sub-SGS drivers322,324,326may concurrently couple or cut off the SGSs of the strings of a corresponding partial block (e.g., tile column) independently of those of other partial blocks. A global access line (e.g., a global CG line)350may couple the charge-storage devices corresponding to the respective tier of each of the plurality of strings. Each global CG line (e.g., the global CG line350) may be coupled to a plurality of sub-access lines (e.g., sub-CG lines)352,354,356via a corresponding one of a plurality of sub-string drivers312,314and316. Each of the sub-string drivers may concurrently couple or cut off the charge-storage devices corresponding to the respective partial block and/or tier independently of those of other partial blocks and/or other tiers. The charge-storage devices corresponding to the respective subset (e.g., partial block) and the respective tier may comprise a “partial tier” (e.g., a single “tile”) of charge-storage devices. The strings corresponding to the respective subset (e.g., partial block) may be coupled to a corresponding one of sub-sources372,374and376(e.g., “tile source”) with each sub-source being coupled to a respective power source.

The NAND memory device200is alternatively described with reference to a schematic illustration ofFIG. 4.

The memory array200includes wordlines2021to202N, and bitlines2281to228M.

The memory array200also includes NAND strings2061to206M. Each NAND string includes charge-storage transistors2081to208N. The charge-storage transistors may use floating gate material (e.g., polysilicon) to store charge, or may use charge-trapping material (such as, for example, silicon nitride, metallic nanodots, etc.) to store charge.

The charge-storage transistors208are located at intersections of wordlines202and strings206. The charge-storage transistors208represent non-volatile memory cells for storage of data. The charge-storage transistors208of each NAND string206are connected in series source-to-drain between a source-select device (e.g., source-side select gate, SGS)210and a drain-select device (e.g., drain-side select gate, SGD)212. Each source-select device210is located at an intersection of a string206and a source-select line214, while each drain-select device212is located at an intersection of a string206and a drain-select line215. The select devices210and212may be any suitable access devices, and are generically illustrated with boxes inFIG. 1.

A source of each source-select device210is connected to a common source line216. The drain of each source-select device210is connected to the source of the first charge-storage transistor208of the corresponding NAND string206. For example, the drain of source-select device2101is connected to the source of charge-storage transistor2081of the corresponding NAND string2061. The source-select devices210are connected to source-select line214.

The drain of each drain-select device212is connected to a bitline (i.e., digit line)228at a drain contact. For example, the drain of drain-select device2121is connected to the bitline2281. The source of each drain-select device212is connected to the drain of the last charge-storage transistor208of the corresponding NAND string206. For example, the source of drain-select device2121is connected to the drain of charge-storage transistor208Nof the corresponding NAND string2061.

The charge-storage transistors208include a source230, a drain232, a charge-storage region234, and a control gate236. The charge-storage transistors208have their control gates236coupled to a wordline202. A column of the charge-storage transistors208are those transistors within a NAND string206coupled to a given bitline228. A row of the charge-storage transistors208are those transistors commonly coupled to a given wordline202.

Memory may be fabricated in decks, and two or more decks may be stacked one atop another. Stress may occur along the stacked decks, leading to buckling or other problematic distortions of materials associated with the decks. It would be desirable to develop improved methods of fabricating stacked memory decks which alleviate the problematic stresses.

