FIELD

This Disclosure relates to integrated circuits having field-plated field effect transistors and other field-plated devices.

BACKGROUND

Some integrated circuits (ICs) contain field effect transistors (FETs) that have drift regions with a field relief oxide layer thereon that enables higher voltage operation. The drift regions deplete under high drain voltage conditions, allowing the FET to block the voltage applied between the drain and source while supporting conduction during the ON-state of the device. A higher voltage FET tends to be formed with the gate electrode extending over field oxide in order to act as a field plate for the drift region.

LOCal Oxidation of Silicon (LOCOS) is a semiconductor fabrication oxidation process that uses a patterned oxygen diffusion barrier layer, commonly a silicon nitride layer, over areas not meant to be oxidized, where a thermally grown silicon dioxide layer is formed within aperture regions of the oxygen diffusion barrier layer at a given thickness, with a thinner tapered silicon oxide region being formed along the edges of the oxygen diffusion barrier layer. Although the active areas widths bordered by LOCOS oxide can be varied, LOCOS provides a single given oxide thickness across the die and across the wafer.

SUMMARY

This Summary is provided to introduce a brief selection of disclosed concepts in a simplified form that are further described below in the Detailed Description including the drawings provided. This Summary is not intended to limit the claimed subject matter's scope.

Disclosed aspects include an IC with a semiconductor surface layer on a substrate including a first field-plated FET, a second field-plated FET, and functional circuitry configured together with the field-plated FETs for realizing at least one circuit function. The field-plated FETs include a gate structure including a gate electrode partially over a LOCOS field relief oxide and partially over a gate dielectric layer. The LOCOS field relief oxide thickness for the first field-plated FET is thicker than the LOCOS field relief oxide thickness for the second field-plated FET. There are sources and drains on respective sides of the gate structures in the semiconductor surface layer.

