BACKGROUND

Apparatuses consistent with embodiments relate to a memory device and a system on chip including the same, and more particularly, to a memory device for storing data through a shared latch and a plurality of latches connected to the shared latch, and a system on chip including the same.

As a mobile product such as a tablet PC or a mobile phone develops, a high performance of a computing system including a component device such as a memory device and an SoC may be required. The SoC includes a memory device for storing data therein. The memory device may include a plurality of latches arranged in columns and rows. The memory device may write data to the plurality of latches and read the written data. As the high performance and low power of the SoC may be required, high performance and low power may be required for the memory device included in the SoC.

SUMMARY

According to embodiments, a memory device includes a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows, each of the plurality of latches being configured to store at least one bit of data, a first flip flop configured to output first data, to first latches arranged in the first column, among the plurality of latches, based on a clock, and a second flip flop configured to output second data, to second latches arranged in the second column, among the plurality of latches, based on the clock. The first flip flop is further configured to, in a lock time section in which the first latches and the second latches maintain an output regardless of an input, block output of the first data to the first latches, and the second flip flop is further configured to, in the lock time section, block output of the second data to the second latches.

According to embodiments, a system on chip includes a control processing unit (CPU) configured to write first data to a plurality of latches through access to the plurality of latches, and a memory device configured to store the first data in correspondence to the access of the CPU. The memory device includes the plurality of latches arranged in a plurality of columns including a first column and in a plurality of rows, each of the plurality of latches being configured to store at least one bit of data, and a first blocking circuit configured to output at least some bits of the first data, to first latches arranged in the first column, among the plurality of latches, based on a clock, and block a signal that is applied to the first latches arranged in the first column, in a lock time section in which the first latches arranged in the first column do not output data.

According to embodiments, a memory device includes a plurality of latches arranged in a plurality of columns and a plurality of rows, each of the plurality of latches being configured to store at least one bit of data, and a bitwise enabler configured to mask one or more latches arranged in at least some of the plurality of columns, based on a plurality of bit enable signals. The one or more latches are configured to, when masked by the bitwise enabler, receive write data, without storing the write data.

