BACKGROUND

Current trends in microelectronic package architecture are increasingly focused on high-density interconnect fabrication in order to accommodate demands for package size miniaturization and heterogeneous integration. Such high-density architectures require increasingly smaller traces and via pads. In both single substrate and three dimensional (3D) microelectronic package architectures, vias provide inter-level connectivity. Vias are conductive pillars that extend through the dielectric material of a planar substrate to interconnect metallization layers. Current fabrication methods for forming vias in package substrates are limited in both scalability and range of suitable dielectric materials. To further scale via size in relation to target interconnect pitch, a breakthrough in package via fabrication is needed.

