RELATED APPLICATIONS

This application is a § 371 National Phase Application of International Application No. PCT/EP2017/079751, filed on Nov. 20, 2017, now International Publication No. WO 2019/096420 A1, published on May 23, 2019, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present invention relates to CMOS image sensors comprising a high number of pixels formed by pixel sensor cell having pinned photodiodes and CMOS integrated circuitry. Furthermore, the present invention relates to measures for readout noise reduction and increase of dynamic range of such CMOS image sensors.

TECHNICAL BACKGROUND

CMOS image sensors are widely applied in technical devices, such as mobile devices or digital cameras. While the development of the pinned photodiodes (buried photodiodes) dramatically increased noise performance of CMOS image sensors, the characteristics of conventional CMOS image sensors still have limitations with respect to sensitivity and dynamic range.

A conventional pixel sensor cell is exemplarily shown in document A. Boukhayma, A. Peizearat and C. Enz, “Noise Reduction Techniques and Scaling Effects towards Photon Counting CMOS Image Sensors”, Sensors 2016, 16, 514, http://www.mbpi.com/thermal/sensors. The conventional pixel sensor cell includes a pinned photodiode and generally four transistors which include a transfer transistor separating the pinned photodiode from a sense node, reset and row selection transistors and a source follower transistor that buffers the voltage level of the sense node.

The transfer transistor is used to control a potential barrier for charge carriers stored/generated in the pinned photodiode. When the gate voltage of the transfer transistor is low enough and the resulting potential in the channel of the transfer transistor is lower than the photo-generated voltage of the pinned photodiode, the integrated charge stored in the pinned photodiode is kept. When the gate voltage of the transfer transistor is set to a high voltage, a depletion in the channel of the transfer transistor is created so that the potential is higher than the charge potential of the pinned photodiode and also lower than a reset potential of the sense node. So, the electrons accumulated in the pinned photodiode during an integration phase flow towards the higher potential area of the sense node through the transfer transistor and the voltage level of the sense node drops from the reset potential depending on the transferred charge.

The voltage of the sense node is sensed by an adequate electronic circuit after resetting the sense node to the reset potential and after the charge of the photodiode has been allowed to flow onto the sense node. The sensed potentials are subtracted to obtain the signal level. This sensing method is called correlated double sampling and allows the reduction of noise that is correlated between the reset time and the transfer time.

While above architecture of the pixel sensor cell and the method of operation provide a good noise characteristic and a reasonable dynamic range, there is a further demand for CMOS image sensors with an even better sensitivity and a higher dynamic range.

Regarding an enhancement of the dynamic range, several techniques have been proposed in document K. Hara, H. Kubo, M. Kimura, F. Murao, and S. Komori, “A linear-logarithmic CMOS sensor with offset calibration using an injected charge signal” in ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, February 2005, pp. 354-603 Vol. 1, in document M. Loose, K. Meier, and J. Schemmel, “A self-calibrating single-chip CMOS camera with logarithmic response,” IEEE Journal of Solid-State Circuits, vol. 36, no. 4, pp. 586-596, April 2001 and in document J. S. et al., “A 1280 960 3.75 m pixel CMOS imager with triple exposure HDR,” in International Image Sensors Workshop, 2009, September 2009, pp. 1-4 which have the disadvantage of not being linear or not having a single synchronous integration time. Further methods are disclosed in A. K. Kalgi et al., “Four concepts for synchronous, PSN limited, true CDS, HDR imaging”, in International Image Sensors Workshop, 2015, September 2015, pp. 1-4. However, methods based on varying the integration time or using multiple different size photodiodes fail having photon-shot-noise limited operation and methods based on acquiring and combining multiple frames at different gains fail to operate in synchronous shutter mode.

From documents EP 2 890 117 A1, U.S. Pat. Nos. 7,408,210, 7,719,590, and US2017/0148832, further approaches are known which allow a linear response and a low readout noise for all lighting conditions and have the possibility to operate in a synchronous shutter mode. These approaches are based on multiple ranges of linear gain so that a high gain is provided for low light signals to ensure a low noise performance, and a low gain is provided for high dynamic signal to avoid saturation. Hence, this method requires a varying sense node capacitance which is embodied by an additional capacitance to be coupled with the sense node by means of a transistor. So, for low-light conditions, the extra capacitance can be disconnected from the sense node to ensure the lowest sense mode capacitance. For high dynamic signals, the extra capacitor can be connected with the sense node in order to increase dramatically the sense node capacitance resulting in a much lower conversion gain and a much larger saturation level. A disadvantage of these approaches is that the additional transistor increases the sense node capacitance and therefore increases the noise flow which affects the overall sensitivity.

SUMMARY OF THE INVENTION

This object has been achieved by the pixel sensor cell according to claim1, by the method of operating a pixel sensor cell and by the CMOS image sensor according to the further independent claims.

Further embodiments are indicated in the depending claims.

According to a first embodiment a pixel sensor cell for a CMOS sensor device is provided comprising:a photodiode for generating photoelectrons;a first transfer transistor coupling the photodiode with an intermediate node and configured to be controlled by a first control signal;a gain reducing capacitance applied on the intermediate node;a second transfer transistor coupling the intermediate node with a sense node and configured to be controlled by a second control signal;an output buffer coupled with the sense node and configured to amplify a potential on the sense node.

According to a further aspect, a method is provided for operating the above pixel sensor cell, comprising the steps of:accumulating photoelectrons in the photodiode during an integration time or allowing photoelectrons to accumulate in the photodiode during the integration time;in a first phase, coupling the intermediate node with the sense node by means of the second transfer transistor and providing a charge threshold for accumulated photoelectrons so that only excess photoelectrons (photoelectrons which contribute to a potential which allow an overflow over the charge threshold) are allowed to pass/flow to the intermediate node, wherein the potential generated by the excess photoelectrons is read out as an HDS sampling output signal;in a second phase, controlling the second transfer transistor to set a threshold of the second transfer transistor to a potential where the second transfer transistor forms an electrical isolation between the intermediate node and the sense node and which is substantially equal or higher than the potential of the intermediate node, coupling the intermediate node with the sense node and reading out the potential on the sense node as a LLS sampling output signal.

One idea of the above pixel sensor cell is to use a combination of a gain reducing capacitance and a first and second transfer transistors, particularly MOSFET transistors, to couple the preferably pinned photodiode with a sense node wherein the gain reducing capacitance may particularly be explicitly or intrinsically formed e.g. as a p+n junction and is separated from the sense node by the second transfer transistor. This allows the reduction of the noise by reducing the sense node capacitance by isolating it from the first transfer gate and the gain reducing capacitance.

Moreover, the saturation level of the pixel sensor cell is enhanced by providing an intermediate node with the gain reducing capacitance to be merged or isolated from the sense node by means of the second transfer transistor. Thereby, a high dynamic read-out can be performed by using the gain reducing capacitance. Further, a low-light sampling is also possible by having the integrated charge of the pinned photodiode directly flown into the sense node through the first and second transfer transistors. In difference to the state of the art high dynamic pixel sensor cells, the sense node is isolated from the first transfer transistor and further components by means of the second transfer transistor. In other words, the second transfer transistor decouples the sense node from the rest of the circuitry which results in an important reduction of the sense node capacitance and a lower read-out noise.

By closing (herein understood as making conductive) the second transistor, the sense node is merged with the gain reducing capacitor, which increases the sense node capacitance, reduces the pixel conversion gain and increases the saturation level.

The above method of operating a pixel sensor cell exploits the fact that the transfer transistors can be operated with analogue inputs defining potential levels for the photoelectrons path starting in the photodiode, the first transfer transistor, the gain reducing capacitance and the second transfer transistor to the sense node during the read-out steps. The potential levels for thresholds which can be applied to beneficially implement a multi-step read-out scheme which allows the definition of several phases to interpret a photosignal.

For the first read-out step, the first transfer gate is controlled to provide a charge threshold for photoelectrons generated in the pinned photodiode. The charge threshold defines a saturation level and corresponds to an amount of photoelectrons for a low-light signal read-out. The second transfer transistor is controlled to be conductive, thereby merging the sense node with the intermediate node coupled with the gain reducing capacitor. Under low-light condition, the generated photoelectrons remain in the photodiode since the photodiode charge remains below the saturation level of the first transfer transistor, i.e. below the charge threshold formed thereby. Under high-dynamic conditions, photoelectrons are generated in the photodiode above saturation level, so that the generated photoelectrons overflow the charge threshold formed by the first transfer transistor into the merged intermediate and sense nodes which have been reset to a higher potential and lowers the node potential. The sense node then can be read out to obtain a first sampling output.

In a second read-out step for reading out a low-light signal, the generated photoelectrons cannot pass the potential barrier of the first transfer transistor so that in a second read-out step, the photoelectron charge stored within the photodiode needs to be measured.

The second read-out step requires a preparation of the sense node for the read-out of the low-light signal. This includes that the sense node is firstly isolated from the intermediate node by controlling the second transfer transistor to be opened (herein understood as making non-conductive) and that the intermediate node potential is reset to a level between the potential of the photodiode and the reset level of the sense node which has been reset before. Then, the second transfer transistor is controlled to adapt its charge threshold (saturation level) to be equal or slightly higher than the intermediate node potential. In this configuration, the sense node is still isolated from the intermediate node so that a reference potential of the sense node can be read out as a second sampling output.

In a third read-out step, the first transfer transistor is controlled to lower the threshold to a voltage between the pin voltage of the photodiode and the present intermediate node potential. The photoelectrons are then transferred directly to the sense node and reduce its node potential. The third sampling output can then be read out and differentiated with the reset sampling output taken before.

This multi-step read-out scheme allows a read-out for two different dynamic ranges, firstly a high-dynamic range and secondly a low-light range. The read-out steps came along with different conversion gains so that a wide dynamic range can be achieved by maintaining a low noise read-out for the low-light signal.

Furthermore, a reset transistor may be provided which is configured to receive a reset signal and to selectively couple a supplied reset voltage to the intermediate node.

According to an embodiment, a control unit may be provided to control operation of the pixel sensor cell by timely providing the first and second control signal.

Furthermore, the output buffer may be formed with a selectable source follower.

Regarding the method, a cell output may be determined depending on the LLS sampling output signal and the HDS sampling output signal.

It may be provided that after the first phase a first reset potential is loaded on the sense node and a second reset potential VRST2which is in a range between a pin voltage Vpinof the photodiode11and the first reset potential.

After resetting the sense node and after the threshold of the second transfer transistor has been set to a potential where the second transfer transistor isolates the intermediate node and the sense node and which is substantially equal or higher than the potential of the intermediate node, a reference sampling output signal is read out, wherein the cell output is further determined depending on the reference sampling output signal.

Particularly, after reading out the potential on the sense node as an LLS sampling output signal, the second transfer transistor is controlled to electrically merge the intermediate node and the sense node, the intermediate and sense nodes are reset onto the first reset potential.

According to a further aspect, a CMOS image sensor including an array of multiple pixel sensor cells as described above is provided.

