CROSS REFERENCE TO RELATED APPLICATIONS

This application is a non-provisional utility application claiming priority to U.S. provisional application No. 62/389,050 filed Feb. 13, 2016, and to U.S. provisional patent No. 62/388,295 filed Jan. 20, 2016.

BACKGROUND OF THE INVENTION

This invention comprises a circuit for a sequential logic cell. Sequential logic cells are used in logic integrated circuits to temporarily store a data value. A sequential logic cell consist of the circuit that keeps a certain data signal, at least one output connection which provides the stored value to other parts of the IC circuits, one data input connection (D), which provides a new data value to be stored by the sequential element, one control input connection (CK) which determines if and when the new data on the data input (D) should be written into the sequential cell. In addition a sequential logic cell may contain additional input connections to change the data stored by the cell. Such additional signals include clear (CLR) and preset (PRESET) which sets the value stored by the cell regardless of the value on the data (D) input. The basic sequential logic cells are the latch and the static random access memory cells. Another common sequential logic cell is the flip-flop.

This invention is concerned with sequential logic cells used in complementary metal oxide semiconductor (CMOS) technology. This technology is the most common technology used in integrated circuits (ICs) today. It uses two types of metal oxide semiconductor field effect transistors (MOSFET), the n-type MOSFET and the p-type MOSFET, to form the logic circuitry of the IC. CMOS technology and MOSFET devices are well known to anyone familiar with integrated circuits, and these terms are used to describe a specific type of logic circuits and semiconductor devices, regardless of specific materials used to manufacture the devices and circuits.

Sequential logic cells are used very frequently in a logic IC and their electrical performance (speed, power), size, and reliability are very important factors for the overall performance and quality of an IC. This invention comprises a certain way to connect n-type MOSFETs and p-type MOSFETs to form the circuit for the sequential elements which improves the electrical performance of the sequential cell vs. prior art, and which improves certain reliability aspects of the sequential cell vs. prior art.

PRIOR ART

The invention will be described for a basic latch or SRAM sequential cell which consist of two cross-coupled inverter cells (INVs). In this circuit the ability to store a data value is accomplished by connecting the output of a first inverter circuit cell (INV) to the input of a second INV, and connecting the output of the second INV to the input of the first INV. In CMOS technology this circuit is realized by two INVs consisting of a p-type MOSFET and an n-type MOSFET connected in series between a high data signal, being the high electric potential, VDD, of the logic circuit, and a low data signal, being the low electric potential of the logic circuit. This basic circuit is shown inFIG. 1. This circuit can be in one of two states. In one state the output of the first INV is LOW (VSS) and the output of the second INV is HIGH, VDD. In the other state the output of the first INV is HIGH, VDD, and the output of the second INV is LOW, VSS.

In order to switch this circuit between the two states, additional MOSFETs, and input connections, must be added to the circuit. In prior art three main different ways to accomplish this have been applied; commonly referred to as the clock-inverter (clocked-INV) circuit (also referred to as the tri-state inverter circuit), the transmission-gated (TG) circuit, and the SRAM clocking circuit.FIG. 2shows the first prior art circuit (clocked-INV). In this circuit a first input connection (D) is provided, which provides the value of the new data to be stored, and a second input connection, CK, is provided, which controls whether the circuit should write in the new data, or keep the prior data. The circuit operates as follows: when the control signal, CK, has a first value (HIGH in the circuit inFIG. 2), the basic cross-coupled INV is connected as in the original circuit, and the circuit keeps its' current value. However, when the control signal, CK, has a second value, complementary (opposite) to the first value (LOW in the circuit inFIG. 2), the connection between the two INVs in the basic cross-coupled INV is broken, and, at the same time, the new data input connection, D, is connected into the circuit. Hence, the new data value, D, will be written into the circuit.

Two different versions of the second prior art circuit, which uses a TG to control the writing in of new data, are shown inFIGS. 3 and 4. As with the clocked-INV circuit, the control signal, CK, is used to write in a new data value, D, by both disconnecting the original cross-coupled INV circuit and connecting the new data value, D, into the circuit.

The SRAM prior art circuit is shown inFIG. 5. In this circuit the control signal, CK, does not disconnect the basic cross-coupled INV circuit. Instead, when a new value should be written in, the input data signal D, is connected to the output of one of the INVs in the original circuit, and the complementary of D (opposite value) is connected to the output of the other INV. Hence the switching to the new data value is accomplished by overwriting both values (output of both INVs) of the basic cross-coupled INV circuit.

In the clocked-INV and TG prior art circuits discussed above, the complementary signal, CKB, of the control signal, CK, is required to accomplish the writing in of data. This means that this signal, CKB, either must be generated by inverting the control signal, CK, in the logic cell, or it must be provided to the cell from the outside fully synchronously with the primary control signal, CK. In today's logic circuit design the former is by far the most common way to generate the complementary control signal inside the sequential logic cell.

The prior art SRAM circuit only the primary control signal is required, i.e., it is not necessary to provide or generate the complement of the control signal. However, the circuit requires both the primary data signal, D, and its' complement, Db. This clocking is used in practically all SRAM memory circuit today, and the complementary data signal, Db, is generated outside the cell itself. Since the SRAM circuit does not disconnect the basic cross-coupled INV circuit, it also requires that the new signal is strong enough to overwrite the prior value. In standard SRAM memory circuits this is accomplished by making the MOSFETs which are controlled by the control signal somewhat larger than the MOSFETs of the original cross-coupled INVs.

BRIEF DESCRIPTION OF THE INVENTION

This invention comprises a new way to connect a control, CK, and data, D, signal into the basic cross-coupled INV (and certain other basic sequential logic circuits), to control the writing in of a new data value, D, into the sequential logic cell. The primary advantages of this new connection over the prior art clock-INV and TG circuits is that it does not require the complement of the control signal; only the primary control signal, CK, is used. The main advantage over the prior art SRAM circuit is that the new circuit does disconnect the circuit of the original cross-coupled INV when the new data is written in. This means that it is easier to write in the new data, resulting in a lower power and/or faster switching. Another advantage is that this new circuit can be made harder against so called soft-errors.

A first basic variant of the new circuit is shown inFIG. 6. It connects two additional series connected p-type MOSFETs in parallel with the original p-type MOSFET in the basic cross-coupled INV circuit, and two parallel connected n-type MOSFETs in series with the original n-type MOSFETs in the basic cross-coupled INV circuits. The gates of these additional MOSFETs are connected to a control signal, CK, a data signal, D, and the complement of the data signal, Db, such that the basic cross-coupled INV pair is disconnected, and writing of data occurs, when the control signal, CK, is LOW (VSS), whereas, when the control signal CK, is HIGH (VDD), the circuit will keep its' value.

A second basic variant of the new circuit is shown inFIG. 7. Here two additional series connected n-type MOSFETs are connected in parallel with the original n-type MOSFET in the basic cross-coupled INV circuit, and two parallel connected p-type MOSFETs are connected in series with the original p-type MOSFETs in the basic cross-coupled INV circuits. The gates of these additional MOSFETs are connected to a control signal, CK, a data signal, D, and the complement of the data signal, Db, such that the basic cross-coupled INV pair is disconnected, and writing of data occurs, when the control signal, CK, is HIGH (VDD), whereas, when the control signal CK, is LOW, the circuit will keep its' value.

A person familiar with the field of the invention, will recognize that the control functions in the two basic variants in this invention can be implemented for other basic sequential circuits which uses a set of INVs connected in such a way that the data is kept by the circuit. The dual interlocked cell (DICE) is one such circuit. Instead of the two INVs in the basic cross-couple INV circuit, it uses four cross-coupled INVs. By including the control MOSFETs of either of the basic versions of this invention, a DICE circuit with same control of the writing of data into the basic DICE circuit can be constructed. Basic DICE circuits constructed using the first and second variants of this invention are shown inFIGS. 9 and 10respectively.

