BACKGROUND

The Institute of Electrical and Electronics Engineers (IEEE) Standards Association publishes an IEEE Standard for Ethernet, IEEE Std 802.3-2015, which will be familiar to those of ordinary skill in the art to which this application pertains. This Ethernet standard provides a common media access control specification for local area network (LAN) operations at selected speeds from 1 Mb/s to 100 Gb/s over coaxial cable, twinaxial cable, twisted wire pair cable, fiber optic cable, and electrical backplanes, with various channel signal constellations. Among the various signal specifications provided by the standard are CAUI-4 (100 Gbps Attachment Unit Interface using 4 lanes), 100GBASE-CR4, and 100GBASE-KR4, each of which couples to a Physical Coding Sublayer (PCS) and hence presumes the use of a data stream employing the channel coding, scrambling, block multiplexing, and alignment features provided in Clause 82 of the standard.

CAUI-4, which is set out in Annex 83D and Annex 83E of the standard, is used for chip-to-chip or chip-to-module connections and employs four lanes of differential, two-level signaling at a rate of 25.78125 GBd with either no forward error correction (FEC) protection or with RS(528,514) Reed-Solomon FEC coding as set out in Clause 91 of the standard. Ports and connectors that comply with the QSFP-28 specification may employ CAUI-4 for a 100 Gbps inbound data stream and for a 100 Gbps outbound data stream.

100GBASE-CR4, which is set out in Clause 92 of the standard, is a specification of a baseband medium intended for use in a multiconductor cable. It employs four lanes of differential, two-level pulse amplitude modulation signaling at a rate of 25.78125 GBd with RS(528,514) Reed-Solomon FEC coding as set out in Clause 91 of the standard.

100GBASE-KR4, which is set out in Clause 93 of the standard, is a specification of a baseband medium intended for use on an electrical backplane. It employs four lanes of differential, two-level pulse amplitude modulation signaling at a rate of 26.5625 GBd with RS(544,514) Reed-Solomon FEC coding as set out in Clause 91 of the standard. Both the RS(528,514) and RS(544,514) codes operate on 10 bit symbols, with the former being capable of correcting up to 7 symbols in any given data frame and the later being capable of correcting up to 15 symbols in any given data frame.

An update to the standard, IEEE 802.3cd, was approved in December 2018, and it allows for 100GBASE-CR4 to employ RS(544,514) Reed-Solomon FEC coding at the higher signaling rate of 26.5625 GBd using differential, two-level pulse amplitude modulation across four lanes in each direction. The update, IEEE 802.3cd, further sets forth (in Clause 135) 100GBASE-CR2, which unlike CR4, uses differential PAM4 signaling rather than 2-level signaling. As part of the process for adapting a 2-level signal to a 4-level signal, the update provides for the use of Gray coding and 1/(1+D) mod 4 precoding. The differential PAM4 signaling is performed over two lanes in each direction at a rate of 26.5625 GBd with RS(544,514) Reed-Solomon FEC coding.

The update similarly sets for 100GBASE-KR2, providing for differential PAM4 signaling on an electrical backplane using two lanes in each direction at a rate of 26.5625 GBd with RS(544,514) Reed-Solomon FEC coding. As with CR4, Gray coding and 1/(1+D) mod 4 precoding is used for adapting two-level signaling to PAM4.

For high bandwidth communications (≥100 Gbps) over distances greater than about 3 meters, the standard contemplates the use of fiberoptic cables. However, such cables tend to be undesirably expensive as compared with copper wire cables. Unfortunately, for high bandwidth communications over distances beyond 7 meters in conventional data centers, even cables using 100GBASE-CR2 tend to be undesirably bulky, inflexible, and heavy.

SUMMARY

Accordingly, there are disclosed herein novel cable designs and manufacturing methods for mass-manufacturing of long, 100 Gbps cables suitable for large communication centers. One illustrative cable embodiment includes: at least eight pairs of electrical conductors connected between a first connector and a second connector, each of said electrical conductors being 30 AWG or smaller in cross-section and about 10 meters or longer in length, each of the first and second connectors being adapted to fit into an Ethernet port of a corresponding host device to receive an electrical input signal to the cable conveying an outbound data stream from that host device and to provide an electrical output signal from the cable conveying an inbound data stream to that host device, each of the first and second connectors including a respective transceiver that performs clock and data recovery on the electrical input signal to extract and re-modulate the outbound data stream for transit via at least four of the pairs of electrical conductors as differential NRZ (non-return to zero) electrical transit signals each having a signaling rate of at least 25 GBd to convey a total of at least 100 GBd in each direction.

One illustrative cable manufacturing method that includes: connecting at least eight pairs of electrical conductors between a first transceiver and a second transceiver, respectively, to transport at least eight differential NRZ electrical transit signals each having a signaling rate of at least 25 GBd to convey a total of at least 100 GBd in each direction, each of the electrical conductors being 30 AWG or smaller in cross-section and about 10 meters or longer in length; packaging the first transceiver into a first connector configured to couple a first electrical input signal from a network interface port of a first host device to the first transceiver and a first electrical output signal from the first transceiver to the network interface port of the first host device; and packaging the second transceiver into a second connector configured to couple a second electrical input signal from a network interface port of a second host device to the second transceiver and a second electrical output signal from the second transceiver to the network interface port of the second host device, the first and second transceivers being configured to perform clock and data recovery on the first and second electrical input signal to extract and re-modulate the first and second outbound data streams as said differential NRZ electrical transit signals.

Each of the foregoing embodiments may be implemented individually or in combination, and may be implemented with one or more of the following features in any suitable combination: 1. the electrical input and electrical output signals for at least one of said transceivers each comprise two lanes of differential PAM4 signals. 2. the at least one of said transceivers uses bit multiplexing or demultiplexing to convert between each lane of differential PAM4 signals and two corresponding lanes of differential NRZ electrical transit signals. 3. the connector for the at least one of said transceivers is adapted to fit a SFP56-DD compliant Ethernet port. 4. the connector for the at least one of said transceivers is adapted to fit a DSFP compliant Ethernet port. 5. each of said transceivers uses bit multiplexing or demultiplexing to convert between each lane of differential PAM4 signals and two corresponding lanes of differential NRZ electrical transit signals. 6. the electrical transit signals are protected with a RS(544,514) Reed-Solomon forward error correction code. 7. the electrical input and electrical output signals for at least one of said transceivers each comprises four lanes of differential NRZ signals protected with a RS(528,514) Reed-Solomon forward error correction code. 8. the at least one of said transceivers uses error correction decoding and encoding to convert between the electrical transit signals and the electrical input and output signals. 9. the connector for the at least one of said transceivers is adapted to fit a QSFP-28 compliant Ethernet port.

