CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2020-0077968, filed on Jun. 25, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

BACKGROUND

1. Field of Invention

The present disclosure relates to an electronic device, and more particularly, to a storage device and a method of operating the same.

2. Description of Related Art

A storage device is a device that stores data under control of a host device, such as a computer or a smartphone. A storage device may include a memory device storing data and a memory controller controlling the memory device. The memory device may be classified as a volatile memory device or a non-volatile memory device.

The volatile memory device may be a device that stores data when power is supplied and loses the stored data when the power supply is cut off. The volatile memory device may include a static random access memory (SRAM), a dynamic random access memory (DRAM), and so on.

The non-volatile memory device is a device that does not lose data when power is cut off. The non-volatile memory device may include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory, and so on.

In the enterprise server market, due to increasing bandwidth demands and problems of power consumption, a solid state disk (SSD) including a NAND flash memory, instead of a hard disk drive, is often utilized as a storage device.

Initial SSD controllers utilized an internal memory as a data buffer. However, recent SSD controllers use a DRAM as the data buffer, due to the high speed demand. Most enterprise servers use a DRAM module, where an expensive error correction code (ECC) function is applied as a main memory of a system bus to provide data stability for the servers.

SUMMARY

An embodiment of the present disclosure provides a storage device having an improved operation speed, and a method of operating the same.

A volatile memory controller that controls a volatile memory device according to an embodiment of the present disclosure may include an error correction circuit configured to receive write transactions from an external host, wherein the write transactions store data in the volatile memory device and generate codewords used when performing error correction encoding on data corresponding to the write transactions and a data aggregator configured to generate a merged transaction in which write transactions that correspond to a burst length of the volatile memory device are merged and provide the merged transaction to the volatile memory device by performing a burst operation.

A storage device according to an embodiment of the present disclosure may include a nonvolatile memory device a main memory configured to temporarily store data related to controlling the nonvolatile memory device and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host, wherein the main memory aggregates and processes a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.

According to the present technology, a storage device having an improved operation speed, and a method of operating the same are provided.

