TECHNICAL FIELD

The following disclosure relates to a display device, and more specifically to a display device having two or more display regions.

BACKGROUND ART

In recent years, regarding a display device such as an organic EL display device and a liquid crystal display device, an increase in resolution and an increase in the size of a screen have advanced. Due to this, a panel load is large compared with that of a known configuration, increasing power consumption. Moreover, to improve display quality, an increase in luminance is advancing. In terms of this, too, power consumption increases. Further, with the advancement of an increase in resolution, drive time per line is reduced, and in order to implement the reduction in drive time, there is a need to improve the ability of a drive circuit (e.g., an LSI), which leads to an increase in power consumption. Regarding a display device, power consumption has increased as described above, and thus, an increase in the size of the drive circuit and an increase in the performance of peripheral parts are required. Such requirements are particularly remarkable in a display device used for virtual reality (VR) (e.g., a head mounted display). However, an increase in the size of the drive circuit and an increase in the performance of peripheral parts are big factors in cost increase.

In relation to this matter, Japanese Laid-Open Patent Publication No. 2003-344823 and Japanese Laid-Open Patent Publication No. 2009-276547 disclose display devices having a configuration in which switching elements whose on/off is controlled by a control signal are provided on data signal lines (source bus lines). In such a configuration, when a switching element is turned off, a data signal line on one side with respect to the position of the switching element (hereinafter, referred to as “first line”.) and a data signal line on the other side (hereinafter, referred to as “second line”) go into an electrically disconnected state. Here, assuming that a source driver is directly connected to the first line, when a data signal is written into a pixel circuit connected to the first line, the switching element is turned off. At this time, a wiring load on the data signal line is reduced compared with that of a configuration in which the switching elements are not provided on the data signal lines. By this, power consumption related to driving of the data signal lines is reduced.

PRIOR ART DOCUMENTS

Patent Documents

[Patent Document 1] Japanese Laid-Open Patent Publication No. 2003-344823

[Patent Document 2] Japanese Laid-Open Patent Publication No. 2009-276547

SUMMARY

Problems to be Solved by the Invention

Meanwhile, in recent years, for example, in order to achieve an improvement in display quality upon display of a moving image/an increase in frame rate has advanced. In addition, regarding a display device including a touch panel, in order to increase the accuracy of touch detection, there is a demand for the securing of a sufficiently long period for touch detection during a period during which drive operation for display is not performed. From the above-described facts, there is a problem about the reduction in drive time per scanning signal line over that of a known configuration. Neither of Japanese Laid-Open Patent Publication No. 2003-344823 and Japanese Laid-Open Patent Publication No. 2009-276547 mentions the reduction in drive time of the scanning signal lines.

An object of the following disclosure is therefore to implement a display device that can reduce drive time per scanning signal line compared to the known configuration while reducing power consumption.

Means for Solving The Problems

A display device according to some embodiments of the present disclosure is a display device that displays an image by writing a data signal into a plurality of pixel circuits arranged in a display panel, whereinthe display panel includes:a plurality of data signal lines configured to transmit the data signal;a plurality of scanning signal lines intersecting the plurality of data signal lines;the plurality of pixel circuits provided at intersecting portions of the plurality of data signal lines and the plurality of scanning signal lines, the plurality of pixel circuits forming a pixel matrix of a plurality of rows× a plurality of columns;a data signal line drive circuit configured to apply the data signal to the plurality of data signal lines;a scanning signal line drive circuit configured to apply a scanning signal to the plurality of scanning signal lines; anda first display region and a second display region in which the plurality of data signal lines are disposed,the first display region and the second display region are arranged side by side in a direction in which the plurality of data signal lines extend,each of the plurality of data signal lines includes a first data signal line disposed in the first display region and a second data signal line disposed in the second display region,the plurality of scanning signal lines include a plurality of first scanning signal lines disposed in the first display region and a plurality of second scanning signal lines disposed in the second display region,the data signal line drive circuit is provided at one edge of the second display region so that the data signal is applied to the second data signal line earlier than the first data signal line,the display panel further includes a first switching element provided for each of the plurality of data signal lines, the first switching element having a control terminal to which a first switching signal is provided, a first conductive terminal connected to the first data signal line, and a second conductive terminal connected to the second data signal line,when the scanning signal line drive circuit applies an on-level scanning signal to any of the plurality of first scanning signal lines, the first switching element is in an on state,when the scanning signal line drive circuit applies an on-level scanning signal to any of the plurality of second scanning signal lines, the first switching element is in an off state, andthe scanning signal line drive circuit sets a second writing period shorter than a first writing period, the second writing period being a period during which an on-level scanning signal is applied to each of the plurality of second scanning signal lines so that the data signal is written into pixel circuits included in the second display region, and the first writing period being a period during which an on-level scanning signal is applied to each of the plurality of first scanning signal lines so that the data signal is written into pixel circuits included in the first display region.

A display device according to some other embodiments of the present disclosure is a display device that displays an image by writing a data signal into a plurality of pixel circuits arranged in a display panel, whereinthe display panel includes:a plurality of data signal lines configured to transmit the data signal;a plurality of scanning signal lines intersecting the plurality of data signal lines;the plurality of pixel circuits provided at intersecting portions of the plurality of data signal lines and the plurality of scanning signal lines, the plurality of pixel circuits forming a pixel matrix of a plurality of rows× a plurality of columns;a data signal line drive circuit configured to apply the data signal to the plurality of data signal lines;a scanning signal line drive circuit configured to apply a scanning signal to the plurality of scanning signal lines; anda first display region and a second display region in which the plurality of data signal lines are disposed,the first display region and the second display region are arranged side by side in a direction in which the plurality of data signal lines extend,each of the plurality of data signal lines includes a first data signal line disposed in the first display region and a second data signal line disposed in the second display region,the plurality of scanning signal lines include a plurality of first scanning signal lines disposed in the first display region and a plurality of second scanning signal lines disposed in the second display region,the data signal line drive circuit is provided at one edge of the second display region so that the data signal is applied to the second data signal line earlier than the first data signal line,the display panel further includes a first switching element provided for each of the plurality of data signal lines, the first switching element having a control terminal to which a first switching signal is provided, a first conductive terminal connected to the first data signal line, and a second conductive terminal connected to the second data signal line,when the scanning signal line drive circuit applies an on-level scanning signal to any of the plurality of first scanning signal lines, the first switching element is in an on state,when the scanning signal line drive circuit applies an on-level scanning signal to any of the plurality of second scanning signal lines, the first switching element is in an off state,as display nodes, a first node in which drive frequency is a first frequency and a second node in which drive frequency is a second frequency higher than the first frequency are prepared,in the first node, a first writing period has a same length as a second writing period, the first writing period being a period during which an on-level scanning signal is applied to each of the plurality of first scanning signal lines so that the data signal is written into pixel circuits included in the first display region, and the second writing period being a period during which an on-level scanning signal is applied to each of the plurality of second scanning signal lines so that the data signal is written into pixel circuits included in the second display region, andin the second mode, the second writing period is shorter than the first writing period.

A display device according to some still other embodiments of the present disclosure is a display device chat displays an image by writing a data signal into a plurality of pixel circuits arranged in a display panel, whereinthe display panel includes:a plurality of data signal lines configured to transmit the data signal;a plurality of scanning signal lines intersecting the plurality of data signal lines;the plurality of pixel circuits provided at intersecting portions of the plurality of data signal lines and the plurality of scanning signal lines, the plurality of pixel circuits forming a pixel matrix of a plurality of rows× a plurality of columns;a data signal line drive circuit configured to apply the data signal to the plurality of data signal lines;a scanning signal line drive circuit configured to apply a scanning signal to the plurality of scanning signal lines; anda first display region and a second display region in which the plurality of data signal lines are disposed,the first display region and the second display region are arranged side by side m a direction in which the plurality of data signal lines extend,each of the plurality of data signal lines includes a first data signal line disposed in the first display region and a second data signal line disposed in the second display region,the plurality of scanning signal lines include a plurality of first scanning signal lines disposed in the first display region and a plurality of second scanning signal lines disposed in the second display region,the data signal line drive circuit is provided at one edge of the second display region so that the data signal is applied to the second data signal line earlier than the first data signal line,the display panel further includes a first switching element provided for each of the plurality of data signal lines, the first switching element having a control terminal to which a first switching signal is provided, a first conductive terminal connected to the first data signal line, and a second conductive terminal connected to the second data signal line,when the scanning signal line drive circuit applies an on-level scanning signal to any of the plurality of first scanning signal lines, the first switching element is in an on state,when the scanning signal line drive circuit applies an on-level scanning signal to any of the plurality of second scanning signal lines, the first switching element is in an off state,as display inodes, a first mode in which drive frequency is a first frequency and a second mode in which drive frequency is a second frequency higher than the first frequency are prepared,in the first mode, a first vertical scanning period has a same length as a second vertical scanning period, the first vertical scanning period being a period during which an on-level scanning signal is sequentially applied to the plurality of first scanning signal lines, and the second vertical scanning period being a period during which an on-level scanning signal is sequentially applied to the plurality of second scanning signal lines, andin the second mode, the second vertical scanning period is shorter than the first vertical scanning period.

Effects of the Invention

According to some embodiments of the present disclosure, in a display device, two display regions (a first display region and a second display region) are provided in a display panel. Further, in the display panel there is provided a first switching element that controls a state of electrical connection between a first data signal line disposed in the first display region and a second data signal line disposed in the second display region, and a first switching signal is provided to a control terminal of the first switching element. Thus, by changing the level of the first switching signal, on/off of the first switching element can be controlled. Here, since a data signal line drive circuit is provided at one edge of the second display region, when writing of a data signal into pixel circuits in the second display region is performed, the first data signal line and the second data signal line can be brought into an electrically disconnected state by turning off the first switching element. By this, wiring loads on data signal lines upon writing the data signal into the pixel circuits in the second display region are reduced over those of an original configuration, reducing power consumption compared with that of a known configuration. In addition, when the wiring loads on the data signal lines are reduced over those of the original configuration, a data signal writing period can be reduced to the extent that problems concerning display do not occur. That is, drive time per scanning signal line can be reduced over that of the known configuration. As described above, a display device is implemented that can reduce drive time per scanning signal line compared to the known configuration while reducing power consumption.

According to some other embodiments of the present disclosure, in a display device in which two switchable modes are prepared, drive time per scanning signal line can be reduced compared to the known configuration while reducing power consumption.

