CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority to Japanese Patent Application No. 2019-205455 filed on Nov. 13, 2019. The entire contents of this application are hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a multilayer ceramic capacitor.

2. Description of the Related Art

Electronic devices are used at a higher frequency than before, and multilayer ceramic capacitors used in electronic devices are required to withstand a high frequency range of several GHz or higher.

JP 2013-16770 A discloses a multilayer ceramic capacitor in which the coverage at a central portion of an internal electrode layer is 75% or more, and the coverage at a tapered portion is 80% or less of that of the central portion.

In a multilayer ceramic capacitor used at a high frequency range, the current tends to flow only in surfaces of internal electrode layers due to the skin effect.

When the current flow is restricted to the surfaces of the internal electrode layers, the current is likely to be affected by the conditions of the surfaces of the internal electrode layers or the conditions of boundary regions between the internal electrode layers and the ceramic layers. In such a case, equivalent series resistance per unit electrode layer (hereinafter, referred to as ESR per unit electrode layer) is disadvantageously increased.

The coverage control described in JP 2013-16770 A alone is insufficient to solve the problem. Other techniques to solve the problem have been needed but not yet provided.

SUMMARY OF THE INVENTION

Preferred embodiments of the present invention provide multilayer ceramic capacitors that are each capable of reducing ESR per unit electrode layer at a high frequency range.

A multilayer ceramic capacitor according to a preferred embodiment of the present invention includes a laminate including a plurality of ceramic layers and a plurality of internal electrode layers laminated together in a lamination direction, and includes, at a widthwise end of at least one of the internal electrode layers in a cross section of the laminate perpendicular or substantially perpendicular to the lamination direction, a ratio of a length X to a length Y of about 1.2 or more and about 3.0 or less, with the length X denoting a length of a straight boundary line between the internal electrode layer and the ceramic layer when a shape of the internal electrode layer is considered as a polygon, and the length Y denoting a length of an actual boundary line between the internal electrode layer and the ceramic layer.

Preferred embodiments of the present invention provide multilayer ceramic capacitors that are each capable of reducing ESR per unit electrode layer at a high frequency range.

The above and other elements, features, steps, characteristics and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments with reference to the attached drawings.

