BACKGROUND

Technical Field

The present disclosure relates to a semiconductor package and a manufacturing method thereof, and more particularly, to a fan-out semiconductor package and a manufacturing method thereof.

Description of Related Art

Fan-out semiconductor packaging is a packaging process in which contacts of a semiconductor die are redistributed over a larger area through a redistribution layer, and provides a solution for packaging semiconductor devices that require higher integration level and greater number of external contacts. However, during manufacturing process, fan-out semiconductor package is often subjected to a high level stress, and such stress may result in warpage issues.

SUMMARY

Accordingly, the present disclosure provides a semiconductor package and a manufacturing method thereof, which is less susceptible to the warpage problem.

According to some embodiments, a semiconductor package includes a semiconductor die, an encapsulant, a redistribution layer, a polymer pattern and a heat dissipation structure. The semiconductor die has a plurality of conductive pads at an active side of the semiconductor die. The encapsulant laterally encapsulates the semiconductor die. The redistribution layer is disposed at the active side of the semiconductor die, and spans over a front surface of the encapsulant. The redistribution layer is electrically connected with the plurality of conductive pads. The polymer pattern is disposed at a back surface of the encapsulant that is facing away from the front surface of the encapsulant. The semiconductor die is surrounded by the polymer pattern. The heat dissipation structure is in contact with a back side of the semiconductor die that is facing away from the active side of the semiconductor die, and extends onto the polymer pattern.

In some embodiments, a non-zero spacing is in between the polymer pattern and the semiconductor die.

In some embodiments, a sidewall of the polymer pattern is substantially coplanar with a sidewall of the semiconductor die.

In some embodiments, a peripheral portion of the semiconductor die is covered by the polymer pattern.

In some embodiments, the heat dissipation structure is in physical contact with the back side of the semiconductor die.

In some embodiments, the heat dissipation structure comprises a seed layer and a conductive layer. The seed layer is conformally formed over the polymer pattern and the back side of the semiconductor die. The conductive layer is formed over the seed layer.

In some embodiments, a portion of the conductive layer overlapped with the semiconductor die has a first thickness, another portion of the conductive layer covering the polymer pattern has a second thickness, and the first thickness is greater than the second thickness.

In some embodiments, the semiconductor package further comprises a heat spreader, disposed over the heat dissipation structure.

In some embodiments, the semiconductor die further has a plurality of conductive pillars respectively disposed between the redistribution layer and one of the plurality of conductive pads.

In some embodiments, the semiconductor die further has a plurality of solder joints respectively disposed between the redistribution layer and one of the plurality of conductive pillars.

In some embodiments, a surface of the redistribution layer at which the semiconductor die is attached has a recess, and the semiconductor die is located in the recess.

In some embodiments, the semiconductor package further comprises an underfill, laterally surrounding the plurality of conductive pillars and the plurality of solder joints.

In some embodiments, the semiconductor package further comprises a plurality of electrical connectors, disposed at a surface of the redistribution layer facing away from the semiconductor die, and electrically connected to the redistribution layer.

According to some embodiments, a manufacturing method of semiconductor package comprises: providing a semiconductor die, wherein the semiconductor die has a plurality of conductive pads at an active side of the semiconductor die; laterally encapsulating the semiconductor die with a encapsulant; forming a redistribution layer at the active side of the semiconductor die, wherein the redistribution layer covers the plurality of conductive pads and spans over a front surface of the encapsulant; forming a polymer pattern at a back surface of the encapsulant that is facing away from the front surface of the encapsulant, wherein the polymer pattern has an opening exposing a back side of the semiconductor die that is facing away from the active side of the semiconductor die; and forming a heat dissipation structure at the back side of the semiconductor die, wherein the heat dissipation structure is in contact with the semiconductor die, and extends over the polymer pattern.

In some embodiments, the step of forming the redistribution layer precedes the steps of forming the polymer pattern and the heat dissipation structure.

In some embodiments, the manufacturing method of semiconductor package further comprises: attaching the back side of the semiconductor die onto a first carrier before laterally encapsulating the semiconductor die with the encapsulant; attaching a second carrier to the redistribution layer and detaching the first carrier from the semiconductor die and the encapsulant after forming the redistribution layer and before forming the heat dissipation structure; and detaching the second carrier from the redistribution layer after forming the heat dissipation structure.

In some embodiments, the step of forming the redistribution layer follows the steps of forming the polymer pattern and the heat dissipation structure.

In some embodiments, the manufacturing method of semiconductor package further comprises: attaching the active side of the semiconductor die onto a first carrier before laterally encapsulating the semiconductor die with the encapsulant; attaching a second carrier to the heat dissipation structure and detaching the first carrier from the semiconductor die and the encapsulant after forming the heat dissipation structure and before forming the redistribution layer; and detaching the second carrier from the heat dissipation structure after forming the redistribution layer.

According to some embodiments, a manufacturing method of semiconductor package comprises: forming a redistribution layer over a carrier; attaching a semiconductor die onto the redistribution layer, wherein the semiconductor die has a plurality of conductive pillars at an active side of the semiconductor die, and the plurality of conductive pillars are attached and electrically connected with the redistribution layer; laterally encapsulating semiconductor die with an encapsulant; forming a polymer pattern on a back surface of the encapsulant that is facing away from the redistribution layer, wherein the polymer pattern has an opening exposing a back side of the semiconductor die that is facing away from the active side of the semiconductor die; forming a heat dissipation structure over the back side of the semiconductor die, wherein the heat dissipation structure is in contact with the semiconductor die, and extends over the polymer pattern; and detaching the carrier.

In some embodiments, the manufacturing method of semiconductor package further comprises: forming a recess at a surface of the redistribution layer before attaching the semiconductor die, wherein the attached semiconductor die is located in the recess; and forming an underfill laterally surrounding the plurality of conductive pillars after attaching the semiconductor die.

As above, the semiconductor package according to embodiments in the present disclosure includes at least one semiconductor die, which is laterally encapsulated by an encapsulant. A redistribution layer is disposed at an active side of the semiconductor die and a front surface of the encapsulant, whereas a polymer pattern is formed at a back surface of the encapsulant. As such, the encapsulant is located between the redistribution layer and the polymer pattern. A coefficient of thermal expansion (CTE) of the encapsulant may be greater than or less than the CTEs of the polymer pattern and the dielectric layers in the redistribution layer. Thereby, the stress caused by the CTE mismatch between the encapsulant and the dielectric layers can be at least partially cancelled by the stress caused by the CTE mismatch between the encapsulant and the polymer pattern. Accordingly, total stress in the semiconductor package can be reduced, and the semiconductor package may be less susceptible to warpage. Furthermore, the polymer pattern is formed over a portion of the encapsulant surrounding the semiconductor die, and can be regarded as having an opening overlapped with the semiconductor die. In this way, a heat dissipation structure covering the polymer pattern can be in physical contact with the semiconductor die. Therefore, heat generated by the semiconductor dies can be more effectively dissipated through the heat dissipation structure.

To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.

