CROSS-REFERENCE TO RELATED APPLICATION

The present application is a 371 of PCT/CN2019/119483 filed on Nov. 19, 2019, which claims priority to the Chinese Patent Application No. 201910020547.0, filed on Jan. 9, 2019, and entitled “THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR, DEVICE, CHIP AND DISPLAY APPARATUS”, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to the technical field of semiconductors, and in particular to a thin film transistor and manufacturing method thereof, and a display apparatus.

BACKGROUND

Thin film transistors serve as an indispensable semiconductor device in chips and display apparatuses. A thin film transistor includes an active layer and a source-drain layer as essential parts, and the source-drain layer includes a source and a drain that are spaced apart.

In the related art, when a source-drain layer of the thin film transistor is to be manufactured, generally, an electrode material layer will be formed first and then a patterning treatment will be performed on the electrode material layer, such that the source-drain layer is obtained.

SUMMARY

The present disclosure provides a thin film transistor and manufacturing method thereof, and a display apparatus. The technical solutions are as follows:

In one aspect, a thin film transistor is provided. The thin film transistor including: a base cushion layer, a base insulating layer, a source-drain layer and an active layer, wherein

the basic cushion layer has a recessed portion;

the base insulating layer is located on a side of the base cushion layer where the recessed portion is located; the base insulating layer has, on a side of the base insulating layer away from the base cushion layer, a first partition wall and a second partition wall that are spaced apart, and an orthographic projection region of a gap region between the first partition wall and the second partition wall onto the base cushion layer is located at a region where the recessed portion is located; and both orthographic projection regions of the first partition wall and the second partition wall onto the base cushion layer partially overlap with the region where the recessed portion is located; and

both the source-drain layer and the active layer are located on the side of the base insulating layer away from the base cushion layer, and arranged sequentially along a direction away from the base cushion layer.

Optionally, the base cushion layer includes: a first cushion block and a second cushion block that are spaced apart, and the recessed portion is located between the first cushion block and the second cushion block,

or, the base cushion layer includes: a substrate, as well as a first bump and a second bump that are spaced apart and located on one side of the substrate close to the base insulating layer, and the recessed portion is located between the first bump and the second bump.

Optionally, a material of the base cushion layer includes a conductive material, the base cushion layer being a first gate layer in the thin film transistor.

Optionally, the thin film transistor further includes: a second gate layer and a first gate insulating layer that are located on a side of the active layer away from the base cushion layer, and the first gate insulating layer is located between the active layer and the second gate layer.

Optionally, the thin film transistor further includes: a third gate layer and a second gate insulating layer that are located on the side of the base cushion layer away from the base insulating layer, and the second gate insulating layer is located between the base cushion layer and the third gate layer.

Optionally, the thin film transistor further includes: a second gate layer and a first gate insulating layer that are located on a side of the active layer away from the base cushion layer, as well as a third gate layer and a second gate insulating layer that are located on the side of the base cushion layer away from the base insulating layer; and

the first gate insulating layer is located between the active layer and the second gate layer, and the second gate insulating layer is located between the base cushion layer and the third gate layer.

Optionally, a recession depth of the recessed portion ranges from 5 nm to 50 μm; and a width of the recessed portion ranges from 5 nm to 50 μm in an arrangement direction of a source and a drain in the source-drain layer.

Optionally, a gap between the source and the drain in the source-drain layer ranges from 1 nm to 5 μm.

In another aspect, provided is a method of manufacturing a thin film transistor, which is used in manufacturing the aforesaid thin film transistor, including:

forming a base cushion layer having a recessed portion;

depositing a base insulating layer on a side of the base cushion layer where the recessed portion is located, wherein the base insulating layer has, on a side of the base insulating layer away from the base cushion layer, a first partition wall and a second partition wall that are spaced apart, and an orthographic projection region of a gap region between the first partition wall and the second partition wall onto the base cushion layer is within a region where the recessed portion is located; and both orthographic projection regions of the first partition wall and the second partition wall onto the base cushion layer partially overlap with the region where the recessed portion is located;

depositing a source-drain layer on the side of the base insulating layer away from the base cushion layer; and

forming an active layer on a side of the source-drain layer away from the base cushion layer.

Optionally, forming the active layer on the side of the source-drain layer away from the base cushion layer includes:

depositing the active layer on the side of the source-drain layer away from the base cushion layer.

Optionally, forming the base cushion layer having the recessed portion includes:

forming a base material layer; and

treating the base material layer with a photoetching technology to obtain the base cushion layer.

Optionally, a material of the base cushion layer includes a conductive material, the base cushion layer being a first gate layer in the thin film transistor.

Optionally, after forming the active layer on the side of the source-drain layer away from the base cushion layer, the method further includes:

forming a first gate insulating layer on a side of the active layer away from the base cushion layer; and

forming a second gate layer on a side of the first gate insulating layer away from the base cushion layer.

Optionally, before forming the base cushion layer having the recessed portion, the method further includes:

forming a third gate layer and a second gate insulating layer that are stacked, and

forming the base cushion layer having the recessed portion includes:

forming the base cushion layer on a side of the second gate insulating layer away from the third gate layer.

Optionally, the method further includes:

forming, before forming the base cushion layer having the recessed portion, a third gate layer and a second gate insulating layer that are stacked;

forming, after forming the active layer on the side of the source-drain layer away from the base cushion layer, a first gate insulating layer on a side of the active layer away from the base cushion layer; and

forming a second gate layer on a side of the first gate insulating layer away from the base cushion layer, and

forming the base cushion layer having the recessed portion includes:

forming the base cushion layer on a side of the second gate insulating layer away from the third gate layer.

In yet another aspect, provided is a display apparatus, including the aforesaid thin film transistor.

