CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2018-0148338, filed on Nov. 27, 2018 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.

BACKGROUND

The inventive concepts relate to a method of manufacturing a vertical memory device.

In order to connect channels to a substrate in a VNAND flash memory device, channel holes may be formed through a mold including insulation layers and sacrificial layers alternately stacked on the substrate to expose upper surfaces of the substrate. A selective epitaxial growth (SEG) process may be performed using the exposed upper surfaces of the substrate as a seed to form semiconductor patterns, and channels may be formed on the semiconductor patterns. However, the semiconductor patterns may have distributions of characteristics, e.g., height distributions, and particularly, in a COP structure in which circuit patterns may be formed under a memory cell array, the SEG process may be performed using a polysilicon layer as a seed on the circuit patterns, so that forming the semiconductor patterns uniformly may not be easy.

SUMMARY

Example embodiments provide a method of manufacturing a vertical memory device having improved characteristics.

According to some embodiments of the inventive concept, there is provided a method of manufacturing a vertical memory device. In the method, a first sacrificial layer including a nitride may be formed on a substrate. A mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer may be formed. The insulation layer and the second sacrificial layer may include a first oxide and a second oxide, respectively. A channel may be formed through the mold and the first sacrificial layer. An opening may be formed through the mold and the first sacrificial layer to expose an upper surface of the substrate. The first sacrificial layer may be removed through the opening to form a first gap. A channel connecting pattern may be formed to fill the first gap. The second sacrificial layer may be replaced with a gate electrode.

According to some embodiments of the inventive concept, there is provided a method of manufacturing a vertical memory device. In the method, a mold including an insulation layer and a first sacrificial layer alternately and repeatedly stacked may be formed on a substrate. The insulation layer may include silicon oxide, and the first sacrificial layer may include germanium oxide or silicon oxide doped with germanium. A channel may be formed through the mold. An opening may be formed through the mold to expose an upper surface of the substrate. The first sacrificial layer may be removed through the opening to form a first gap. A gate electrode may be formed in the first gap.

According to some embodiments of the inventive concept, there is provided a method of manufacturing a vertical memory device. In the method, a first sacrificial layer including a nitride may be formed on a substrate. A mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked may be formed on the first sacrificial layer. The insulation layer may include silicon oxide, and the second sacrificial layer may include germanium oxide or silicon oxide doped with germanium. A channel may be formed through the mold and the first sacrificial layer. An opening may be formed through the mold and the first sacrificial layer to expose an upper surface of the substrate. The first sacrificial layer may be removed through the opening to form a gap. A channel connecting pattern may be formed to fill the gap. The second sacrificial layer may be replaced with a gate electrode.

In a method of manufacturing a vertical memory device, when the first sacrificial layer for forming the channel connecting pattern is removed through the opening extending through the mold including the insulation layer and the second sacrificial layer, the first sacrificial layer may include a material having a high etching selectivity with respect to the insulation layer and the second sacrificial layer of the mold, and thus no etch stop pattern covering the sidewall of the opening may be formed. Accordingly, the channel connecting pattern may be formed by a reduced number of processes.

Particularly, when the gate electrode is formed by removing the second sacrificial layer, the second sacrificial layer may not include a nitride, and thus a C—N residue may not be generated during the removal of the second sacrificial layer, and the deterioration of the characteristics of the channel may be prevented.

