CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application Nos. 10-2020-0049865 filed on Apr. 24, 2020 and 10-2020-0110608 filed on Aug. 31, 2020, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties.

BACKGROUND

Embodiments of the inventive concept disclosed herein relate to a semiconductor memory, and more particularly, relate to an operation method of a nonvolatile memory device.

A semiconductor memory device is classified as a volatile memory device, in which stored data disappear when a power is turned off, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), or a nonvolatile memory device, in which stored data are retained even when a power is turned off, such as a flash memory device, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), or a ferroelectric RAM (FRAM).

A flash memory is being widely used as a high-capacity storage medium. The flash memory may erase memory blocks using an erase voltage. The reliability of data programmed in the memory cells of the flash memory may depend on an erase state of the flash memory. Accurate verifying of the erase state of the flash memory is desirable.

SUMMARY

Embodiments of the inventive concept provide an operation method of a nonvolatile memory device having improved reliability.

According to an embodiment of the present inventive concept, an operation method of a nonvolatile memory device which includes a memory block including a plurality of wordlines and a plurality of bitlines, includes performing an erase operation on the memory block using a 0-th erase voltage, performing a block verification operation on the memory block using a 0-th erase verification voltage, performing, in response to a result of the block verification operation being determined as a pass, a delta verification operation on the memory block using a first erase verification voltage different from the 0-th erase verification voltage, and outputting, in response to the result of the block verification operation or a result of the delta verification operation, information of whether the erase operation performed on the memory block is determined as a pass or a fail. The plurality of wordlines are grouped into a plurality of wordline groups. The delta verification operation includes generating a plurality of delta counting values respectively from the plurality of wordline groups using the first erase verification voltage, generating a delta value based on the plurality of delta counting values, and comparing the delta value and a first reference value.

According to an embodiment of the present inventive concept, an operation method of a nonvolatile memory device which includes a memory block including a plurality of wordlines and a plurality of bitlines, includes performing an erase operation on the memory block, performing a block verification operation on the memory block using a 0-th erase verification voltage, performing, in response to a result of the block verification operation being determined as a pass, a partial verification operation on the memory block using the 0-th erase verification voltage, performing, in response to a result of the partial verification operation being determined as a pass, a delta verification operation on the memory block using a first erase verification voltage different from the 0-th erase verification voltages, and outputting, in response to the result of the block verification operation, the result of the partial verification operation, or a result of the delta verification operation, information of whether the erase operation performed on the memory block is determined as a pass or a fail. The performing of the block verification operation includes generating a block counting value in a block unit using the 0-th erase verification voltage, and comparing the block counting value and a first reference value. The performing of the partial verification operation includes generating a plurality of partial counting values in a wordline group unit using the 0-th erase verification voltage and comparing each of the plurality of partial counting values and a second reference value. The performing of the delta verification operation includes generating a plurality of delta counting values in the wordline group unit using the first erase verification voltage, generating a delta value based on the plurality of delta counting values, and comparing the delta value and a third reference value.

According to an embodiment of the present inventive concept, an erase verification method of a nonvolatile memory device which includes a memory block erased in an erased operation and having a plurality of wordlines includes grouping the plurality of wordlines into a plurality of wordline groups, generating a plurality of delta counting values respectively from the plurality of wordline groups by using a first erase verification voltage, generating a delta value based on the plurality of delta counting values, comparing the delta value and a first reference value, and outputting, in response to the comparing of the delta value and the first reference value, information of whether an erase result of the erase operation performed on the memory block is determined as a pass or a fail.

According to an exemplary embodiment, an erase verification method of a nonvolatile memory device which includes a memory block including a plurality of wordlines includes performing a block verification operation on the memory block by using a 0-th erase verification voltage, performing a delta verification operation when a result of the block verification operation indicates a pass, outputting information about an erase result of the memory block based on the result of the block verification operation or a result of the delta verification operation, and the plurality of wordlines are classified into a plurality of wordline groups. The delta verification operation may include generating a plurality of first delta counting values respectively corresponding to the plurality of wordline groups based on a first sensing condition, generating a first delta value based on the plurality of first delta counting values, comparing the first delta value and a first reference value, and generating a plurality of second delta counting values respectively corresponding to the plurality of wordline groups based on a second sensing condition different from the first sensing condition, when the first delta value is smaller than the first reference value.

According to an exemplary embodiment, an erase verification method of a nonvolatile memory device which includes a memory block connected with a plurality of wordlines includes performing an erase operation on the memory block, performing a block verification operation on the memory block, performing a plurality of delta verification operations when a result of the block verification operation indicates a pass, and outputting information about an erase result of the memory block based on the result of the block verification operation or a result of the plurality of delta verification operations. The plurality of wordlines are classified into a plurality of wordline groups. Each of the plurality of delta verification operations indicates an operation in which a soft defect of each of the plurality of wordline groups is detected based on a difference between delta counting values respectively detected from the plurality of wordline groups based on a different erase verification voltage.

