TECHNICAL FIELD

This disclosure pertains to batteries for computing systems.

BACKGROUND

Volatile memory requires power to maintain stored data. If power is interrupted, e.g., system power is turned off, the data will be lost. Upon re-instituting powering, the system will need to reload all of the data back into the volatile memory. Reloading the data requires time and processing power, thereby increasing system latency.

SUMMARY

Various embodiments of the present disclosure provide systems and methods including an integrated circuit die substrate. A volatile memory electrically coupled to the integrated circuit die substrate. A first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element comprising a first field programmable gate array (FPGA), and the first integrated circuit die element disposed adjacent to the volatile memory. A battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state. A battery module disposed on a top portion of the first integrated circuit die element, the battery module operable to receive power from the battery charger, and the battery module operable to supply power to the volatile memory at least when the main power supply is in the off state.

In some embodiments, the systems and method further include a second integrated circuit die element stacked with and electrically coupled to the volatile memory.

In some embodiments, the volatile memory comprises a portion of the first integrated circuit die element.

In some embodiments, the second integrated circuit die element comprises a microprocessor.

In some embodiments, the second integrated circuit die element comprises a second FPGA and a corresponding reconfigurable dual function memory array.

In some embodiments, the systems and methods include a third integrated circuit die element stacked with and electrically coupled to the second integrated circuit die element, the third integrated circuit die element comprising any of a microprocessor, additional volatile memory, a second FPGA, or a reconfigurable dual function memory array.

In some embodiments, the systems and methods include a temperature sensor operable to monitor and sense a temperature of at least a portion of the system; and a control logic and microcontroller unit coupled to the temperature sensor, the control logic and microcontroller unit operable to disable, based on the sensed temperature, one or more connection circuits, thereby preventing power leakage from the volatile memory while allowing the volatile memory to continue to receive power from the battery module when the main power supply is in the off state.

Various embodiments of the present disclosure provide systems and methods include an integrated circuit die substrate. A volatile memory electrically coupled to the integrated circuit die substrate. A first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element disposed adjacent to the volatile memory. A battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state. A battery module disposed on the integrated circuit die substrate, the battery module operable to receive power from the battery charger, and the battery module operable to supply power to the volatile memory at least when the main power supply is in the off state.

In some embodiments, the systems and methods include a second integrated circuit die element stacked with and electrically coupled to the volatile memory.

In some embodiments, the volatile memory comprises a portion of the first integrated circuit die element.

In some embodiments, the second integrated circuit die element comprises a microprocessor.

In some embodiments, the second integrated circuit die element comprises a second FPGA and a corresponding reconfigurable dual function memory array.

In some embodiments, the systems and methods include a third integrated circuit die element stacked with and electrically coupled to the second integrated circuit die element, the third integrated circuit die element comprising any of a microprocessor, additional volatile memory, a second FPGA, or a reconfigurable dual function memory array.

In some embodiments, the systems and methods include a temperature sensor operable to monitor and sense a temperature of at least a portion of the system; and a control logic and microcontroller unit coupled to the temperature sensor, the control logic and microcontroller unit operable to disable, based on the sensed temperature, one or more connection circuits, thereby preventing power leakage from the volatile memory while allowing the volatile memory to continue to receive power from the battery module when the main power supply is in the off state.

Various embodiments of the present disclosure provide systems and methods configured to receive, by volatile memory, power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state, the volatile memory being electrically coupled to an integrated circuit die substrate. Receive, by a battery charger, power from the main power supply, the battery charger being disposed on a top portion of a first integrated circuit die element electrically coupled to the integrated circuit die substrate and comprising a first field programmable gate array (FPGA), and the first integrated circuit die element being disposed adjacent to the volatile memory. Receive, by a battery, power from the battery charger. Receive, by the volatile memory, power from the battery charger. Detect, by a control logic and microcontroller unit, a power output of the main power supply indicative of the main power supply being in the off state. Disable, in response to detecting the power output indicative of the main power supplying being in the off state, a first connection circuit between the main power supply and the volatile memory, thereby preventing power leakage from the volatile memory while allowing the volatile memory to continue to receive power from the battery.

In some embodiments, the volatile memory is electrically coupled to and stacked with a second integrated circuit die element.

In some embodiments, the volatile memory comprises a portion of the first integrated circuit die element.

In some embodiments, the second integrated circuit die element comprises a microprocessor.

In some embodiments, the second integrated circuit die element comprises a second FPGA and a corresponding reconfigurable dual function memory array.

In some embodiments, the second integrated circuit die element is electrically coupled to and stacked with a third integrated circuit die element, the third integrated circuit die element comprising any of a microprocessor, additional volatile memory, a second FPGA, or a reconfigurable dual function memory array.

These and other features of the systems, methods, and non-transitory computer readable media disclosed herein, as well as the methods of operation and functions of the related elements of structure and the combination of parts and economies of manufacture, will become more apparent upon consideration of the following description and the appended claims with reference to the accompanying drawings, all of which form a part of this specification, wherein like reference numerals designate corresponding parts in the various figures. It is to be expressly understood, however, that the drawings are for purposes of illustration and description only and are not intended as a definition of the limits of the invention.

