CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0112495 filed on Sep. 3, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

The present disclosure relates to a memory device, a controller for controlling the same, a memory system including the same, and a method of operating the same.

DISCUSSION OF RELATED ART

A dynamic random access memory (DRAM) is a type of random-access semiconductor memory that stores each bit in a memory cell consisting of a capacitor and a transistor. Since DRAM has high response speed and high operation speed, the DRAM may be used as a main memory of a system. A typical DRAM writes data or outputs written data under control of a host. Recently, a DRAM including an internal processor configured to perform a portion of an operation of a host or a central processing unit (CPU) has been developed. This paradigm is referred to as processing-in-memory (PIM).

SUMMARY

Example embodiments of the present disclosure provide a memory device operating in a dual operation mode, a memory system including the same, a controller controlling the same, and a method of operating the same.

Example embodiments of the present disclosure provide a memory device performing an internal operation under optimal environment conditions, a memory system including the same, a controller controlling the same, and a method of operating the same.

Example embodiments of the present disclosure provide a memory device implemented with a dual operation mode structure, a memory system including the same, a controller controlling the same, and a method of operating the same.

According to an example embodiment of the present disclosure, there is provided a memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.

According to an example embodiment of the present disclosure, there is provided a memory system including: a memory device configured to operate in one of a first operation mode and a second operation mode in response to a mode change command, wherein the memory device includes first banks and second banks; and a controller configured to control the memory device, wherein the controller includes a PIM mode generator configured to generate a mode change command for selecting one of the first and second operation modes, wherein the memory device includes: a plurality of pins for receiving a plurality of control signals from the controller; a PIM mode controller configured to activate one of the first and second banks in the first operation mode and to activate at least one of the first banks and at least one of the second banks in the second operation mode in response to the mode change command; and a processing unit configured to perform an operation on first data output from the activated first bank and second data output from the activated second bank.

According to an example embodiment of the present disclosure, a method of operating a memory device includes: receiving a mode change request from a controller; changing an operation mode of the memory device in response to the mode change request; receiving an internal operation request in the changed operation mode; and performing an operation on data output from at least two activated banks in response to the internal operation request.

According to an example embodiment of the present disclosure, there is provided a controller for controlling a memory device, the controller including: a clock generator configured to generate a clock and to output the clock to the memory device; a command address generator configured to generate a command address signal to operate the memory device; a command address transmitter configured to transmit the command address signal in response to the clock; and a PIM mode generator configured to generate a mode change command for selecting one of a first operation mode and a second operation mode, wherein among a plurality of banks of the memory device, one bank is activated in response to an operation command in the first operation mode, among the plurality of banks of the memory device, at least two banks are activated in response to an operation command in the second operation mode, and an operation mode and an internal operation environment of the memory device are dynamically changed in response to the mode change command.

According to an example embodiment of the present disclosure, there is provided a memory device including: a pin for receiving a mode change command from a controller; a PIM mode controller configured to activate one of first and second memory banks in a first operation mode when the mode change command identifies the first operation mode and to activate the first bank and the second bank in a second operation mode when the mode change command identifies the second operation mode; and a processing unit configured to perform an operation on first data output when the first bank is activated and second data output when the second bank is activated.

