CROSS REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit of Indian Patent Application No. 202041024347, entitled “MIMCAP ARCHITECTURE” and filed on Jun. 10, 2020, which is expressly incorporated by reference herein in its entirety.

BACKGROUND

Field

The present disclosure relates generally to a metal-insulator-metal (MIM) capacitor (MIMCAP) architecture, and more particularly, to a custom MIMCAP layout architecture for supporting high frequency and low voltage drop requirements.

Background

A standard cell device is an integrated circuit (IC) that implements digital logic. Such standard cell device may be reused multiple times within an application-specific IC (ASIC). An ASIC, such as a system-on-a-chip (SoC) device, may contain thousands to millions of standard cell devices. A typical IC includes a stack of sequentially formed layers. Each layer may be stacked or overlaid on a prior layer and patterned to form the shapes that define transistors (e.g., field effect transistors (FETs) and/or fin FETs (FinFETs)) and connect the transistors into circuits.

IC MIMCAPs may reduce voltage fluctuations and noise on the power supply through a provided decoupling capacitance. There is currently a need for cell MIMCAPs with a greater provided decoupling capacitance.

SUMMARY

In an aspect of the disclosure, a cell on an IC is provided. The cell includes a first set of metal x (Mx) layer interconnects coupled to a first voltage, and a second set of Mxlayer interconnects coupled to a second voltage different than the first voltage. The cell further includes a MIM capacitor structure below the Mxlayer. The MIM capacitor structure includes a capacitor top metal (CTM), a capacitor bottom metal (CBM), and an insulator between portions of the CTM and the CBM. The first set of Mxlayer interconnects is coupled to the CTM. The second set of Mxlayer interconnects is coupled to the CBM. The MIM capacitor structure is between the Mxlayer and a metal x-1 (Mx-1) layer. The MIM capacitor structure includes a plurality of openings. The MIM capacitor structure is continuous within the cell and extends to at least two edges of the cell.

In an aspect of the disclosure, an IC is provided. The IC includes a plurality of abutting cells. Each cell includes a first set of Mxlayer interconnects coupled to a first voltage, and a second set of Mxlayer interconnects coupled to a second voltage different than the first voltage. Each cell further includes a MIM capacitor structure below the Mxlayer. The MIM capacitor structure includes a CTM, a CBM, and an insulator between portions of the CTM and the CBM. The first set of Mxlayer interconnects is coupled to the CTM. The second set of Mxlayer interconnects is coupled to the CBM. The MIM capacitor structure is between the Mxlayer and an Mx-1layer. The MIM capacitor structure includes a plurality of openings. The MIM capacitor structure is continuous across the plurality of cells.

