REFERENCES

The following prior applications are herein incorporated by reference in their entirety for all purposes:

U.S. patent application Ser. No. 16/274,118, filed Jun. 12, 2019, naming Kiarash Gharibdoust, entitled “Low Latency Combined Clock Data Recovery Logic Network and Charge Pump Circuit”, hereinafter identified as [Gharibdoust].

BACKGROUND

It is common for communications receivers to extract a receive clock signal from the received data stream. Some communications protocols facilitate such Clock Data Recovery (CDR) operation by constraining the communications signaling so as to distinguish between clock-related and data-related signal components. Similarly, some communications receivers process the received signals beyond the minimum necessary to detect data, so as to provide the additional information to facilitate clock recovery. As one example, a so-called double-baud-rate receive sampler may measure received signal levels at twice the expected data reception rate (i.e. utilizing two distinct time samples per receive unit interval,) to allow independent detection of the received signal level corresponding to the data component, and the chronologically offset received signal transition related to the signal clock component.

However, the introduction of extraneous communications protocol transitions limits achievable data communication rate. Similarly, receive sampling at higher than transmitted data rate substantially increases receiver power utilization. Thus, a receive CDR system operating at baud rate (e.g. the receiver utilizing only a single time sample per receive unit interval) is desirable.

Data-dependent receive equalization is also well known in the art. Generally, these time-domain-oriented equalization methods focus on compensating for the effects of inter-symbol-interference or ISI on the received signal. Such ISI is caused by the residual electrical effects of a previously transmitted signal persisting in the communications transmission medium, so as to affect the amplitude or timing of the current symbol interval. As one example, a transmission line medium having one or more impedance anomalies may introduce signal reflections. Thus, a transmitted signal will propagate over the medium and be partially reflected by one or more such anomalies, with such reflections appearing at the receiver at a later time in superposition with signals propagating directly.

One method of data-dependent receive equalization is Decision Feedback Equalization or DFE. In DFE, the time-domain oriented equalization is performed by maintaining a history of previously-received data values at the receiver, which are processed by a transmission line model to predict the expected influence that each of the historical data values would have on the present receive signal. Such a transmission line model may be pre-calculated, derived by measurement, or generated heuristically, and may encompass the effects of one or more than one previous data interval. The predicted correction of the accumulated influence of these one or more previous data intervals is collectively called the DFE compensation. At low to moderate data rates, the DFE compensation may be calculated in time to be applied before the next data sample is detected, as example by being explicitly subtracted from the received data signal prior to receive sampling, or implicitly subtracted by modifying the reference level to which the received data signal is compared in the receive data sampler or comparator. However, at higher data rates the detection of previous data bits and computation of the DFE compensation may not be complete in time for the next data sample, requiring use of so-called “unrolled” DFE computations performed on speculative or potential data values rather than known previous data values. As one example, an unrolled DFE stage may predict two different compensation values depending on whether the determining data bit will resolve to a one or a zero, with the receive detector performing sampling or slicing operations based on each of those predictions, the multiple results being maintained until the DFE decision of the prior unit interval is resolved.

[Gharibdoust] describes a data communication receiver incorporating at least one stage of unrolled DFE, thus for each receive unit interval a single clock signal initiates two concurrent samples, one representing the received data result if the previous unit interval was a one, and the other representing the received data result if the previous unit interval was a zero. Because of the speculated influence of the previous unit interval data, the sampling thresholds at which the two concurrent measurements are made are offset in amplitude. For certain sequences of received data, it is possible for a received signal transition to pass through a first sampler's threshold voltage at the sampling time, while a second sampler obtains a stable “center of eye” data result. Said first sampler response may be processed to obtain an indication whether the actual received signal transition was earlier or later than would be predicted relative to the receive clock, providing a correction signal that may be used to adjust the receive clock phase.

BRIEF DESCRIPTION

Methods and systems are described which identify whether a receive clock signal is properly locked in frequency and phase to a receive signal stream, permitting error-free data detection to occur. Following conventional practices, the frequency and phase of a receive clock is adjusted based on “early” or “late” error indications obtained by observing transitions in a received signal stream, said adjustments accumulating until the transition timing of the receive clock is sufficiently accurate to maintain data detection. Due to inherent processing biases within the receive clock system and/or intentional clock rate variations generated by the transmitting device, there may be a variation between the number of “early” error indications and the number of “late” error indications observed, even when the receive clock phase is accurately adjusted. Integration or accumulation of error indications over two or more time intervals may be used to determine whether the receive clock is locked, in one embodiment by observing that the accumulated error indications are within a predetermined range, in a second embodiment by observing that the ratios of error indicators are within a predetermined range, and in another embodiment by observing that consecutive accumulated error indications are similar.

Methods and systems are described herein for generating early and late votes for a clock recovery system, each early or late vote associated with a detected transitional data pattern in a data stream, generating a first early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a first time interval, generating a second early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a second time interval, comparing the first and the second early-late vote ratios, and outputting a CDR-lock signal at least in part responsive to determining that the first and the second early-late vote ratios are within a predetermined threshold.

