CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 U.S.C. § 119(a) of European Application No. 19206163.8 filed Oct. 30, 2019 the contents of which are incorporated by reference herein in their entirety.

BACKGROUND OF THE DISCLOSURE

1. Field of the Disclosure

The present disclosure relates to semiconductor device. In particular this disclosure relates to a combined MOS controlled diode and MOS transistor semiconductor device and associated method of manufacture.

2. Description of the Related Art

In switching semiconductor devices such as MOSFETs power losses can arise in two main ways. Firstly, the inherent on-resistance, known as RDS(ON) dissipates power during operation of the MOSFET and the larger the transistor, the lower the RDS(ON) and therefore less power will be dissipated in the device. Secondly, as the MOSFET switches the intrinsic parasitic capacitance stores and then dissipates energy during each switching operation. These capacitive losses are proportional to the switching frequency of the MOSFET during operation and the value of the parasitic capacitance in the MOSFET. As the size of the MOSFET increases its intrinsic parasitic capacitance also increases such that increasing the MOSFET size also increases the switching loss.

As a result of these losses, there is therefore a trade-off between RDS(ON)and intrinsic parasitic capacitance. While a larger MOSFET will exhibit lower RDS(ON)and consequently lower conduction loss, the larger MOSFET increases parasitic capacitance and therefore increasing the switching loss. To overcome these losses, trench MOSFETs may have a low RDS(ON)at the expense of a large area between the gate, drain, and source, which results in larger parasitic capacitance.

One known way to lower the parasitic capacitance is the integration of a so-called MOS Controlled Diode (or MCD) on to the MOSFET die. The area taken up by the MCD to the MOSFET active area should ideally be equal, that is the ratio should be 1 or in percentage terms 100%. For a fixed current rating to integrate the MCD onto the same die as the MOSFET would require an increase in MOSFET die area is required to accommodate the MCD. Known systems use small ratio of about 20% because the cost of using increasing the active area is prohibitive in terms of device size.

SUMMARY

Various example embodiments are directed to issues such as those addressed above and/or others which may become apparent from the following disclosure concerning improving switching loss in MOSFET devices.

In certain example embodiments, aspects of the present disclosure involve improving the trade-off between RDS(ON)and intrinsic parasitic capacitance.

According to an embodiment there is provided a combined MOS controlled diode (MCD) and MOS transistor semiconductor device, comprising: an epitaxial semiconductor layer arranged on a semiconductor substrate; a matrix of trenches formed in the epitaxial layer, the matrix of trenches comprising a first plurality of spaced apart parallel trenches and a second plurality of spaced apart parallel trenches, wherein each of the first plurality of parallel trenches is orthogonal to each of the second plurality of parallel trenches; gate electrodes arranged in each of the first plurality of spaced apart parallel trenches; and source electrodes arranged in each of the second plurality of spaced apart parallel trenches.

The semiconductor device further comprises a first oxide layer formed in the first plurality of spaced apart parallel trenches and a second oxide layer formed in the second plurality of spaced apart parallel trenches.

The gate electrodes may be insulated from the epitaxial semiconductor layer by the first oxide layer and the source electrodes may be insulated from the epitaxial semiconductor layer by second oxide layer. The gate electrodes may be insulated from the source electrodes by the first oxide layer and the second oxide layer.

The gate electrodes may be continuous along the length of the each of the first plurality of spaced apart parallel trenches, and the source electrodes may be split along the length of each the second plurality of spaced apart parallel trenches.

The first plurality of spaced apart parallel trenches define a first cell pitch and the second plurality of spaced apart parallel trenches defines a second cell pitch. The first cell pitch is the pitch of the MOS controlled diode and the second cell pitch is the pitch of the MOS transistor.

According to embodiments there is also provided a method of manufacturing a combined MOS controlled diode (MCD) and MOS transistor semiconductor device, the method comprising: forming an epitaxial semiconductor layer on a semiconductor substrate; forming a matrix of trenches formed in the epitaxial layer, the matrix of trenches comprising a first plurality of spaced apart parallel trenches and a second plurality of spaced apart parallel trenches, wherein each of the first plurality of parallel trenches is orthogonal to each of the second plurality of parallel trenches; forming gate electrodes in each of the first plurality of spaced apart parallel trenches; and forming source electrodes in each of the second plurality of spaced apart parallel trenches.

The method may further comprise forming a first oxide layer in the first plurality of spaced apart parallel trenches and forming a second oxide layer in the second plurality of spaced apart parallel trenches.

The gate electrodes may be formed to be insulated from the epitaxial semiconductor layer by the first oxide layer and the source electrodes are formed to be insulated from the epitaxial semiconductor layer by second oxide layer.

The gate electrodes may be formed to be insulated from the source electrodes by the first oxide layer and the second oxide layer.

Forming the gate electrodes to be continuous along the length of the each of the first plurality of spaced apart parallel trenches, and forming the source electrodes to be split along the length of each the second plurality of spaced apart parallel trenches.

The first plurality of spaced apart parallel trenches to define a first cell pitch and forming the second plurality of spaced apart parallel trenches to define a second cell pitch. The first cell pitch is the pitch of the MOS controlled diode and the second cell pitch is the pitch of the MOS transistor.

