BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a driver circuit. In particular, the present invention relates to a display device having the driver circuit. Further, the present invention relates to an electronic device having the display device in a display portion.

2. Description of the Related Art

In recent years, with the increase of large display devices such as liquid crystal televisions, display devices such as liquid crystal display devices and light-emitting devices have been actively developed. In particular, a technique for forming a pixel circuit and a driver circuit including a shift register or the like (also referred to as an internal circuit) over the same insulating substrate by using transistors or the like having semiconductor layers has been actively developed, because the technique greatly contributes to reduction in power consumption and cost. The internal circuit formed over the insulating substrate is connected to an external circuit including a controller IC or the like provided outside the insulating substrate through an FPC or the like, and its operation is controlled.

As a driver circuit (also referred to as a driver), which is one of internal circuits, there is a scan line driver circuit or the like, for example. For example, a driver circuit is formed using a shift register including a plurality of flip-flop circuits, as disclosed in Reference 1.

REFERENCE

Reference 1: Japanese Published Patent Application No. 2006-024350

SUMMARY OF THE INVENTION

In a conventional driver circuit as disclosed in Reference 1, there is a problem in that malfunctions occur because timing of the switching operation of a transistor in a flip-flop circuit deviates from desired timing. As a cause of deviation in timing of the switching operation of a transistor, for example, when a gate terminal of a pull-up transistor in a flip-flop circuit of a shift register enters into a floating state in a non-selection period, noise or the like generated in the non-selection period adversely affects a potential of the gate terminal of the pull-up transistor.

In addition, deterioration of a transistor itself is one of causes of deviation in the timing of the switching operation. Due to the deterioration of the transistor, the threshold voltage of the transistor changes, so that malfunctions occur in the driver circuit. In the case of using a transistor having a semiconductor layer formed using an amorphous semiconductor as a transistor, malfunctions particularly occur easily because the transistor having the semiconductor layer formed using the amorphous semiconductor easily deteriorates.

In an embodiment of the present invention, it is an object to suppress malfunctions in a circuit including a shift register.

An embodiment of the present invention is a driver circuit which includes a shift register including a plurality of flip-flop circuits. At least one of the plurality of flip-flop circuits is a flip-flop circuit to which a first signal, a second signal, and a third signal are input and which outputs an output signal. The at least one of the plurality of flip-flop circuits includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor includes a gate terminal, a source terminal, and a drain terminal. A first potential corresponding to a potential of the first signal is applied to the gate terminal of the first transistor. The first potential or a second potential is applied to one of the source terminal and the drain terminal of the first transistor. The second transistor includes a gate terminal, a source terminal, and a drain terminal. A third potential corresponding to a potential of the second signal is applied to the gate terminal of the second transistor. One of the source terminal and the drain terminal of the second transistor is electrically connected to the other of the source terminal and the drain terminal of the first transistor. A fourth potential is applied to the other of the source terminal and the drain terminal of the second transistor. One of the third transistor and the fourth transistor controls whether to set a potential of the other of the source terminal and the drain terminal of the first transistor to the first potential or the fourth potential. The other of the third transistor and the fourth transistor controls whether to set the potential of the other of the source terminal and the drain terminal of the first transistor to the fourth potential. When the one of the third transistor and the fourth transistor is in an on state, the other of the third transistor and the fourth transistor is in an off state. When the other of the third transistor and the fourth transistor is in an on state, the one of the third transistor and the fourth transistor is in an off state. The fifth transistor includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the fifth transistor is electrically connected to the other of the source terminal and the drain terminal of the first transistor. A fifth potential corresponding to a potential of the third signal is applied to one of the source terminal and the drain terminal of the fifth transistor. A potential of the other of the source terminal and the drain terminal of the fifth transistor is a potential of the output signal. The fifth transistor is in an off state when the third transistor or the fourth transistor is in an on state.

An embodiment of the present invention is a driver circuit which includes a shift register including a plurality of flip-flop circuits. The flip-flop circuit is a flip-flop circuit to which a first control signal, a second control signal, a first clock signal, and a second clock signal are input and which outputs an output signal. The flip-flop circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The first transistor includes a gate terminal, a source terminal, and a drain terminal. A first potential corresponding to a potential of the first control signal is applied to the gate terminal of the first transistor. The first potential or a second potential is applied to one of the source terminal and the drain terminal of the first transistor. The second transistor includes a gate terminal, a source terminal, and a drain terminal. A third potential corresponding to a potential of the second control signal is applied to the gate terminal of the second transistor. One of the source terminal and the drain terminal of the second transistor is electrically connected to the other of the source terminal and the drain terminal of the first transistor. A fourth potential is applied to the other of the source terminal and the drain terminal of the second transistor. Each of the third transistor and the fourth transistor is a transistor including a gate terminal, a source terminal, and a drain terminal. One of the source terminal and the drain terminal of the third transistor is electrically connected to the other of the source terminal and the drain terminal of the first transistor. One of the source terminal and the drain terminal of the fourth transistor is electrically connected to the other of the source terminal and the drain terminal of the first transistor. The first potential or the fourth potential is applied to the other of the source terminal and the drain terminal of the one of the third transistor and the fourth transistor. One of the source terminal and the drain terminal of the other of the third transistor and the fourth transistor is electrically connected to the other of the source terminal and the drain terminal of the first transistor. The fourth potential is applied to the other of the source terminal and the drain terminal of the other of the third transistor and the fourth transistor. When the one of the third transistor and the fourth transistor is in an on state, the other of the third transistor and the fourth transistor is turned off. When the other of the third transistor and the fourth transistor is in an on state, the one of the third transistor and the fourth transistor is turned off. The fifth transistor includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the fifth transistor is electrically connected to the other of the source terminal and the drain terminal of the first transistor. A fifth potential corresponding to a potential of the first clock signal is applied to one of the source terminal and the drain terminal of the fifth transistor. A potential of the other of the source terminal and the drain terminal of the fifth transistor is a potential of the output signal. The fifth transistor is in an off state when the third transistor or the fourth transistor is in an on state. The sixth transistor includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the sixth transistor is electrically connected to the gate terminal of the other of the third transistor and the fourth transistor. One of the source terminal and the drain terminal of the sixth transistor is electrically connected to the other of the source terminal and the drain terminal of the fifth transistor. The fourth potential is applied to the other of the source terminal and the drain terminal of the sixth transistor. The seventh transistor includes a gate terminal, a source terminal, and a drain terminal. A sixth potential corresponding to a potential of the second clock signal is applied to the gate terminal of the seventh transistor. One of the source terminal and the drain terminal of the seventh transistor is electrically connected to the other of the source terminal and the drain terminal of the fifth transistor. The fourth potential is applied to the other of the source terminal and the drain terminal of the seventh transistor.

Note that in the above embodiment of the present invention, the flip-flop circuit can include a first capacitor, an eighth transistor, a second capacitor, and a ninth transistor. The first capacitor includes at least two terminals. The fifth potential is applied to one of the terminals of the first capacitor. The other of the terminals of the first capacitor is electrically connected to the gate terminal of the other of the third transistor and the fourth transistor. The eighth transistor includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the eighth transistor is electrically connected to the gate terminal of the fifth transistor. One of the source terminal and the drain terminal of the eighth transistor is electrically connected to the gate terminal of the other of the third transistor and the fourth transistor. The fourth potential is applied to the other of the source terminal and the drain terminal of the eighth transistor. The second capacitor includes at least two terminals. The sixth potential is applied to one of the terminals of the second capacitor. The other of the terminals of the second capacitor is electrically connected to the gate terminal of the one of the third transistor and the fourth transistor. The ninth transistor includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the ninth transistor is electrically connected to the gate terminal of the first transistor. One of the source terminal and the drain terminal of the ninth transistor is electrically connected to the gate terminal of the one of the third transistor and the fourth transistor. The fourth potential is applied to the other of the source terminal and the drain terminal of the ninth transistor.

In the above embodiment of the present invention, the flip-flop circuit can include a first capacitor and an eighth transistor. The first capacitor includes at least two terminals. The fifth potential is applied to one of the terminals of the first capacitor. The other of the terminals of the first capacitor is electrically connected to the gate terminal of the other of the third transistor and the fourth transistor. The eighth transistor includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the eighth transistor is electrically connected to the gate terminal of the fifth transistor. One of the source terminal and the drain terminal of the eighth transistor is electrically connected to the gate terminal of the other of the third transistor and the fourth transistor. The fourth potential is applied to the other of the source terminal and the drain terminal of the eighth transistor.

In the above embodiment of the present invention, the flip-flop circuit can include a tenth transistor. The tenth transistor includes a gate terminal, a source terminal, and a drain terminal. The first potential is applied to the gate terminal of the tenth transistor. One of the source terminal and the drain terminal of the tenth transistor is electrically connected to the gate terminal of the other of the third transistor and the fourth transistor. The fourth potential is applied to the other of the source terminal and the drain terminal of the tenth transistor.

In the above embodiment of the present invention, the flip-flop circuit can have a function of outputting a second output signal and can include an eleventh transistor, a twelfth transistor, and a thirteenth transistor. The eleventh transistor includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the eleventh transistor is electrically connected to the one of the source terminal and the drain terminal of the first transistor. The fifth potential is applied to one of the source terminal and the drain terminal of the eleventh transistor. A potential of the other of the source terminal and the drain terminal of the eleventh transistor is a potential of the second output signal. The twelfth transistor includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the twelfth transistor is electrically connected to the gate terminal of the other of the third transistor and the fourth transistor. One of the source terminal and the drain terminal of the twelfth transistor is electrically connected to the other of the source terminal and the drain terminal of the eleventh transistor. The fourth potential is applied to the other of the source terminal and the drain terminal of the twelfth transistor. The thirteenth transistor includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the thirteenth transistor is electrically connected to the gate terminal of the seventh transistor. One of the source terminal and the drain terminal of the thirteenth transistor is electrically connected to the other of the source terminal and the drain terminal of the eleventh transistor. The fourth potential is applied to the other of the source terminal and the drain terminal of the thirteenth transistor.

In the above embodiment of the present invention, the first control signal and the second control signal are digital signals, and the absolute value of a potential difference between a high state and a low state of each digital signal can be made larger than the absolute value of the threshold voltage of each transistor in the flip-flop circuit.

In the above embodiment of the present invention, the level of the fourth potential can be made equivalent to the level of a potential of a high state or a low state of the first control signal, the second control signal, the first clock signal, or the second clock signal.

In the above embodiment of the present invention, the phase of the first clock signal and the phase of the second clock signal are opposite to each other, and the absolute value of a potential difference between a high state and a low state of each of the first clock signal and the second clock signal can be made larger than the absolute value of the threshold voltage of each transistor in the flip-flop circuit.

In the above embodiment of the present invention, all the transistors in the flip-flop circuit can have the same conductivity type.

In the above embodiment of the present invention, each transistor in the flip-flop circuit can include a gate electrode, a gate insulating film provided so as to cover the gate electrode, a first semiconductor layer including a microcrystalline semiconductor layer and provided over the gate electrode with the gate insulating film interposed therebetween, a buffer layer provided over the first semiconductor layer, a pair of second semiconductor layers including an impurity element and provided over the buffer layer, a source electrode provided over one of the pair of second semiconductor layers, and a drain electrode provided over the other of the pair of second semiconductor layers.

An embodiment of the present invention is a display device which includes one of a scan line driver circuit and a signal line driver circuit having the above driver circuit, a plurality of scan lines, a plurality of signal lines, and a pixel portion. The pixel portion includes a plurality of pixels which are electrically connected to the scan line driver circuit through any one of the plurality of scan lines and are electrically connected to the signal line driver circuit through any one of the plurality of signal lines.

An embodiment of the present invention is an electronic device having the above display device in a display portion.

Note that in this specification, a transistor has at least three terminals: a gate terminal, a drain terminal, and a source terminal. A gate terminal refers to part of a gate electrode (including a conductive film, a wiring, and the like) or part of a portion which is electrically connected to the gate electrode. In addition, a source terminal refers to part of a source electrode (including a conductive layer, a wiring, and the like) or part of a portion which is electrically connected to the source electrode. Further, a drain terminal refers to part of a drain electrode (including a conductive layer, a wiring, and the like) or part of a portion which is electrically connected to the drain electrode. Furthermore, the transistor has a channel region between a drain region and a source region and can supply current through the drain region, the channel region, and the source region.

Further, in this specification, since a source terminal and a drain terminal of a transistor change depending on the structure, the operating condition, or the like of the transistor, it is difficult to define which is a source terminal or a drain terminal. Therefore, in this document, one of terminals selected optionally from a source terminal and a drain terminal is referred to one of the source terminal and the drain terminal, and the other of the terminals is referred to as the other of the source terminal and the drain terminal.

Note that when it is explicitly described that “B is formed on A” or “B is formed over A”, it does not necessarily mean that B is formed in direct contact with A. The description includes the case where A and B are not in direct contact with each other, i.e., the case where another object is interposed between A and B. Here, each of A and B corresponds to an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

Therefore, for example, when it is explicitly described that “a layer B is formed on (or over) a layer A”, it includes both the case where the layer B is formed in direct contact with the layer A, and the case where another layer (e.g., a layer C or a layer D) is formed in direct contact with the layer A and the layer B is formed in direct contact with the layer C or D. Note that another layer (e.g., a layer C or a layer D) may be a single layer or a plurality of layers.

Note that when it is explicitly described that “B is formed on A” or “B is formed over A”, it includes the case where B is formed obliquely above A.

Further, in this specification, terms with ordinal numbers, such as “first” and “second”, are used in order to avoid confusion among components, and the terms do not limit the components numerically.

According to an embodiment of the present invention, malfunctions in a circuit including a shift register can be suppressed.

