TECHNICAL FIELD

Embodiments of the present invention generally relate to a chip package assembly, and in particular, to a chip package assembly comprising at least one integrated circuit (IC) die disposed on a package substrate or interposer, and a plurality of extra-die heat transfer posts extending from an upper surface of the IC die.

BACKGROUND

Electronic devices, such as tablets, computers, copiers, digital cameras, smart phones, control systems and automated teller machines, among others, often employ electronic components which leverage chip package assemblies for increased functionality and higher component density. Conventional chip packaging schemes often utilize a package substrate, often in conjunction with a through-silicon-via (TSV) interposer, to enable a plurality of integrated circuit (IC) dies to be mounted to a single package substrate. The IC dies may include memory, logic or other IC devices.

In many chip package assemblies, providing adequate thermal management has become increasingly challenging. Failure to provide adequate cooling often results in diminished service life and even device failure. Thermal management is particularly problematic in applications where multiple dies are vertically stacked on a substrate in a single package assembly. In such applications, the IC dies that are located closer to the substrate often have poor heat transfer paths out of the package assembly. The lack of efficient paths to remove heat from these middle and lower positioned IC dies of the vertical IC stack often causes these dies to operate at temperatures very close to the thermal junction temperature limit. Thus, small fluctuations in ambient temperatures, such as by air conditioner failure, may quickly lead to the thermal junction temperature limit being exceeded, resulting in device failure or system shutdowns.

Therefore, a need exists for a chip package assembly having improved thermal management.

SUMMARY

A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, and a first plurality of electrically floating extra-die conductive posts. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC die is mounted to the first surface of the substrate. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die.

In another example, a chip package assembly is provided that includes a substrate, first and second integrated circuit (IC) dies, first and second pluralities of electrically floating extra-die conductive posts, and a cover. The substrate has a first surface and an opposing second surface. The first IC die has a first surface and an opposing second surface. The second surface of the first IC is mounted to the first surface of the substrate. Each of the first plurality of extra-die conductive posts have a first end contacting the first surface of the first IC die and extend to a second end. The second IC die also has a first surface and an opposing second surface. The second surface of the second IC is mounted above the first surface of the first IC die between the first plurality of extra-die conductive posts. Each of the second plurality of electrically floating extra-die conductive posts also have a first end contacting the first surface of the second IC die and extend to a second end. The cover has a surface facing the first surfaces of the first and second IC dies that is disposed adjacent the second ends of the first and second pluralities of extra-die conductive posts. The first and second pluralities of extra-die conductive posts provide a heat transfer path between the cover and the first surfaces of the first and second IC dies.

In another example, a method for fabricating chip package assembly is provided that includes mounting a first integrated circuit (IC) die to a substrate, the first IC die having a first plurality of electrically floating extra-die conductive posts extending from a side of the first IC die facing away from the substrate, and mounting a second IC die to the second IC die between the first plurality of extra-die conductive posts extending from the first IC die facing away from the substrate.

In another example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, a first plurality of electrically floating extra-die conductive posts, and a conductive member. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC is mounted to the first surface of the substrate. The first surface of the first IC die has a recess formed along at least one edge. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die. The conductive member is disposed in the recess.

In another example, a chip package assembly is provided that includes a substrate, first and second integrated circuit (IC) dies, first and second pluralities of electrically floating extra-die conductive posts, and a conductive member. The substrate has a first surface and an opposing second surface. The first IC die has a first surface and an opposing second surface. The second surface of the first IC is mounted to the first surface of the substrate. Each of the first plurality of extra-die conductive posts have a first end contacting the first surface of the first IC die and extend to a second end. The second IC die also has a first surface and an opposing second surface. The first surface of the second IC has a recess along at least one edge. The second surface of the second IC is mounted above the first surface of the first IC die between the first plurality of extra-die conductive posts. Each of the second plurality of electrically floating extra-die conductive posts also have a first end contacting the first surface of the second IC die and extend to a second end. The conductive member is disposed in the recess.

In another example, a method for fabricating chip package assembly is provided that includes mounting a first integrated circuit (IC) die to a substrate, the first IC die having a first plurality of electrically floating extra-die conductive posts extending from a side of the first IC die facing away from the substrate, mounting a second IC die to the second IC die between the first plurality of extra-die conductive posts extending from the first IC die facing away from the substrate, the first surface of the second IC having a recess along at least one edge, and disposing a conductive member disposed in the recess.

