FIELD

The present disclosure relates to correcting phase nonlinearities of Digital-to-Time Converters (DTC). In particular, the present disclosure relates to a method and a system for calibrating a phase nonlinearity of a DTC.

BACKGROUND

DTCs are used for generating fractional shifted frequencies or modulated signals from a constant reference frequency. They may be used, e.g., for carrier frequency shift and phase modulation in digital polar transmitters (DPTX), for frequency synthesis in receivers (RX), or for digital clock generation in clocking applications.

Some applications (e.g. digital clock generation) have relaxed specifications, i.e. they are tolerant against DTC phase nonlinearity. Especially applications for DPTX and RX require highly linear DTCs. As no attractive or competitive architecture for an ideally linear DTC is known, the DTC nonlinearity is calibrated on-chip and the digital DTC data is pre-distorted with the information from the DTC calibration.

Several calibration engines have been proposed and implemented. Their major drawback is the calibration of a specific DTC operation case (e.g. calibration of quasi-static DTC programming, or calibration of a particular code ramp).

However, the DTC nonlinearity changes for different operation types (e.g. different code ramps or modulation), so that one set of calibration data is not sufficient for all operation types.

Hence, there may be a desire for improved calibration of DTC nonlinearities.

