FIELD

An electronic circuit to divide the frequency of an input signal is provided.

BACKGROUND

Clock dividers are used to turn the frequency of an input signal into a reduced frequency of an output signal. The ratio between the frequency of the input signal and the output signal is the division factor. Clock dividers are widely used in phase-locked loops.

In phase-locked loops the generated clock needs to be divided down to be compared to the reference clock. It is known to break down the overall clock divider into several stages, where the first stage has highest speed and, therefore, is toughest to design.

The bottleneck of clock dividers is the maximum speed at which they are operable while providing stable divide ratios in view of process-voltage-and-temperature (PVT) variations in the presence of device aging or degradation.

FIG. 1is a simplified schematic drawing of an example100of a divide by 3 CMOS logic circuit according to the prior art. The circuit consists of four gated inverters110,120,130,140connected in series. The outputs of the second gated inverter120and the fourth gated inverted140are connected to the inputs152,154of a NAND gate150and its output156is connected to the input of the first gated inverter110. Each gated inverter has complementary control signal inputs. As an example, the first gated inverter110comprises a first and a second complementary input112,114. Each of these inputs is driven by an asymmetrical clock driver160. The asymmetrical clock driver160provides higher than 50 percentage duty cycle clocks so that each PMOS transistor and the NMOS transistor within the gated inverter is ON for more than 50 percentage of the clock period. This is to improve the maximum speed of operation. In any case the maximum speed is limited by the propagation delay through the NAND gate150. To speed up the NAND gate150one may increase its driving strength by increase its size, but this increases the load on nodes div3_stage4170and especially div3_stage2172which in turn becomes the speed bottle neck. The maximum achievable speed will be further reduced if a single divider circuit must be used for providing multiple divide ratios due to the complexity of the circuit which needs more combinatory logic and gated inverters.

SUMMARY

An electronic circuit is provided.

The electronic circuit may be a high speed CMOS logic circuit or may be suitable therefor.

The electronic circuit may be a clock divider.

The electronic circuit may comprise a ring oscillator. The ring oscillator may comprise a plurality of gated inverters. At least one of the gated inverters can be configured to receive an oscillating signal and a control signal at two complementary inputs. The electronic circuit may be configured to be partially gated such that a divide ratio may be selectable.

The ring oscillator may comprise at least three gated inverters. The at least three gated inverters can be arranged in a series connection. An output of each of the gated inverters can be applied to an input of a subsequent of the gated inverters of the ring oscillator.

The control signal may comprise a first signal and a second signal. The first signal and the second signal can be opposite to each other.

A duty-cycle of the control signal may be greater than 0.5.

At least one gated inverter may be partially gated such that it outputs a logic high or logic low depending on a logic state of an input signal. The output signal may be selectable by means of application of partial gating on either PMOS or NMOS.

The electronic circuit may comprise an interconnect.

The gated inverters may have bus holders.

The electronic circuit may be a tri-modulus clock divider.

Divide ratios of at least 1 over 3, 4, and 5 may be selectable.

In another aspect, a clock divider is provided. The clock divider may comprise a plurality of gated inverters subsequently coupled to each other. At least one of the gated inverters may be configured to receive an oscillating signal and a control signal. The clock divider may be configured such that a divide ratio is selectable based on the control signal.

According to yet another aspect an electronic circuit is provided. The electronic circuit may comprise a ring oscillator. The ring oscillator may comprise a plurality of gated inverters. At least one of the gated inverters may be configured to receive an oscillating signal and at least one auxiliary signal at an additional input. The electronic circuit may comprise a plurality of interconnects. The electronic circuit may provide a divide ratio which is selectable based on the at least one auxiliary signal.

