BACKGROUND

Integrated Circuits (ICs) contain internal buses that follow standard protocols for communication between internal logic blocks. Some examples include an Advanced Extensible Interface (AXI) bus protocol, an Advanced High-performance Bus (AHB) protocol, an Open Core Protocol (OCP), etc.

In some cases, an internal bus within an IC can hang (i.e., be non-responsive). In one example, the AXI bus requires each transaction to complete before performing a next transaction. If a clock becomes unstable or is lost for a period of time, the AXI bus can become unstable and hangs because it cannot complete the current transaction. In such a case, a hard reset is required. However, detection of problems on internal buses within an IC has been problematic.

