BACKGROUND

Field of Invention

The present invention relates to a semiconductor structure and semiconductor layout structure. More particularly, the present invention relates to a semiconductor structure and semiconductor layout structure with anti-fuse structures.

Description of Related Art

Fuse elements are commonly used in semiconductor devices, such as semiconductor memory or logic devices. Anti-fuses have electrical characteristics opposite to those of fuses and may be used for the repair of defective cells by swapping the defective cells with redundant cells.

In general, one anti-fuse needs to be controlled by one control gate adjacent thereof. Therefore, a unit cell is defined as 1T1C, which refers to one transistor (control gate) and one capacitance (anti-fuse). However, when the number of anti-fuse is increasing, the conventional of 1T1C structure will occupy a big area. In order to achieve a high density memory cell or redundancy, the unit cell should be as small as possible.

SUMMARY

In accordance with an aspect of the present disclosure, a semiconductor layout structure is provided. The semiconductor layout structure includes a substrate, a plurality of gate structures, and a plurality of conductive structures. The substrate includes a plurality of active regions extending along a first direction, in which the active regions are separated from each other by an isolation structure. The gate structures extend across the active regions along a second direction that is perpendicular to the first direction, in which each of the active regions includes a pair of source/drain portions at opposite sides of each of the gate structures. The conductive structures are embedded in a first portion of the isolation structure disposed between the adjacent active regions in the first direction, in which the conductive structures extend along the second direction and are separated from the source/drain portions by the isolation structure.

According to some embodiments of the present disclosure, the first portion of the isolation structure includes a lower isolation structure and an upper isolation structure. The lower isolation structure is interposed between the active regions. The upper isolation structure is disposed on the lower isolation structure and extends into the active regions on opposite sides of the first portion of the isolation structure along the first direction.

According to some embodiments of the present disclosure, the conductive structures have a portion of a sidewall covered by the upper isolation structure.

According to some embodiments of the present disclosure, the first portion of the isolation structure has a width that is greater than a width of the conductive structures in the first direction.

According to some embodiments of the present disclosure, the isolation structure further includes a second portion interposed between the active regions in the second direction.

According to some embodiments of the present disclosure, a first gate structure and a second gate structure are disposed on each of the active regions, and each of the active regions has a common source/drain portions shared by the first gate structure and the second gate structure.

According to some embodiments of the present disclosure, the semiconductor layout structure further includes a plurality of contact plugs respectively connected to the conductive structures, the source/drain portions, and the gate structures.

According to some embodiments of the present disclosure, the semiconductor layout structure further includes a plurality of connected lines extending along the first direction and connected to the gate structures via the contact plugs.

In accordance with another aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure includes a substrate, a first transistor and a second transistor, an isolation structure and an isolation structure. The substrate has a first active region and a second active region spaced from each other. The first transistor and the second transistor are respectively disposed in the first active region and the second active region. The isolation structure is interposed between the first transistor and the second transistor, in which the isolation structure has a protruding portion laterally extends into the first active region and the second active region. The conductive structure is embedded in the isolation structure, in which the conductive structure is separated from the first transistor and the second transistor by the protruding portion of the isolation structure.

According to some embodiments of the present disclosure, the conductive structure has a portion of a sidewall covered by the protruding portion of the isolation structure.

According to some embodiments of the present disclosure, the isolation structure has a width that is greater than a width of the conductive structure.

According to some embodiments of the present disclosure, each of the first transistor and the second transistor includes a gate structure on the substrate, and a pair of source/drain portions in the substrate.

According to some embodiments of the present disclosure, the source/drain portions have a bottom surface that is below a bottom surface of the conductive structure.

According to some embodiments of the present disclosure, the protruding portion of the isolation structure has a top surface that is level with a top surface of the source/drain portions.

According to some embodiments of the present disclosure, further includes a plurality of contact plugs respectively connected to the conductive structure, one of the source/drain portions away from the conductive structure, and the gate structure.

According to some embodiments of the present disclosure, the semiconductor structure further includes a connected line coupled to the gate structure.

It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed.

