BACKGROUND

A large number of computing applications have recently exploded onto the scene. Notable among them include the internet of things, wearables, and sensor networks. A common thread running across these applications is that they often have ultra-low-power requirements. These requirements are due to the fact that these applications are either energy-constrained (e.g., when they are battery powered) or power-constrained (e.g., applications with inductive coupling or power scavenging).

Considering that these applications tend to be embedded, one option to target these applications is to use an application-specific integrated circuit (ASIC). However, many of these applications are cost-sensitive. Also, many of these applications need to be tuned or updated in the field. As a result, an ultra-low-power (ULP) embedded microprocessor or microcontroller is often a better fit.

In addition, ULP processors have rapidly become the most abundant type of processor in production today. New and emerging power- and energy-constrained applications such as the internet-of-things (IoT), wearables, implantables, and sensor networks have already caused production of ULP processors to exceed that of personal computers and mobile processors. It is projected that these applications will continue to rely on simple single-core ultralow-power processors in the future, will be powered by batteries and energy harvesting, and will have even tighter peak power and energy constraints than the power- and energy-constrained ULP systems of today. Unsurprisingly, low-power microcontrollers and microprocessors are projected to continue being the most widely-used type of processor in the future.

Further, the ultra-low power and energy requirements of emerging applications, along with the increasing leakage energy dissipation that has accompanied complementary metal-oxide-semiconductor (CMOS) scaling, have fueled interest in aggressive power gating techniques. Conventional aggressive power gating techniques perform module-based power gating, i.e., power gating of register-transfer level (RTL) modules during periods of inactivity. An RTL module is encapsulated with a well-defined port list, making it relatively easy to determine when a module is inactive based on input signals in the port list.

While RTL modules form convenient boundaries for defining power domains, module-based domains may not be the best option for supporting aggressive power gating. Logic is grouped into a module based on common functionality, not necessarily based on correlated activity. In several cases, activity of logic in the same module can have uncorrelated activity (e.g., different registers in the register file may not be used by the same instruction or even the same application), while logic in different modules can often be correlated (e.g., when one module feeds data or control signals to another).

