CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2020-0111673, filed on Sep. 2, 2020, in the Korean Intellectual Property Office, and entitled: “Semiconductor Package and Method of Manufacturing the Semiconductor Package,” is incorporated by reference herein in its entirety.

BACKGROUND

1. Field

Example embodiments relate to a semiconductor package and a method of manufacturing the semiconductor package. More particularly, example embodiments relate to a multi-chip package including a plurality of stacked chips and a method of manufacturing the same.

2. Description of the Related Art

Mobile devices, e.g., smartphones and tablet personal computers (PCs), may store information using internal memory. A universal flash storage (UFS) package may be used as the internal memory.

SUMMARY

According to example embodiments, a semiconductor package includes a package substrate, a lower package structure arranged on the package substrate and including a mold substrate, a semiconductor chip provided in the mold substrate such that chip pads of the semiconductor chip are exposed from the mold substrate, a plurality of spacer chips provided in the mold substrate to be spaced apart from the semiconductor chip, and a redistribution wiring layer arranged on the mold substrate and having redistribution wirings electrically connected to the chip pads, first and second stack structures on the lower package structure to be spaced apart from each other, each of the first and second stack structures including a plurality of stacked memory chips, and a molding member on the package substrate to cover the lower package structure and the first and second stack structures. The mold substrate includes a first covering portion covering side surfaces of the semiconductor chip and the spacer chips and a second covering portion covering a lower surface of the semiconductor chip.

According to example embodiments, a semiconductor package includes a package substrate, a lower package structure adhered onto the package substrate by a first adhesive member, first and second stack structures on the lower package structure to be spaced apart from each other, each of the first and second stack structures including a plurality of stacked memory chips, and a molding member on the package substrate to cover the lower package structure and the first and second stack structures. The lower package structure includes a mold substrate, a semiconductor chip provided in the mold substrate such that chip pads of the semiconductor chip are exposed from the mold substrate, a plurality of spacer chips provided in the mold substrate to be spaced apart from the semiconductor chip, and a redistribution wiring layer arranged on the mold substrate and having redistribution wirings electrically connected to the chip pads. A thickness of the semiconductor chip is within a range of 40 μm to 60 μm, and a thickness of the first adhesive member is within a range of 15 μm to 25 μm.

According to example embodiments, a semiconductor package includes a package substrate, a lower package structure arranged on the package substrate and including a mold substrate, a semiconductor chip provided in the mold substrate such that chip pads of the semiconductor chip are exposed from the mold substrate, a plurality of spacer chips provided in the mold substrate to be spaced apart from the semiconductor chip, and a redistribution wiring layer arranged on the mold substrate and having redistribution wiring pads electrically connected to the chip pads, first and second stack structures on the lower package structure to be spaced apart from each other, each of the first and second stack structures including a plurality of stacked memory chips, first conductive connection members electrically connecting the redistribution wiring pads and substrate pads of the package substrate, second conductive connection members electrically connecting chip pads of the memory chips and substrate pads of the package substrate, and a molding member on the package substrate to cover the lower package structure and the first and second stack structures. The mold substrate includes a first covering portion covering side surfaces of the semiconductor chip and the spacer chips and a second covering portion covering a lower surface of the semiconductor chip.

