CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of the Korean Patent Applications No. 10-2019-0173305 filed on Dec. 23, 2019, which is hereby incorporated by reference as if fully set forth herein.

FIELD

The present invention relates to a memory controller for controlling a memory, and more particularly, to a memory controller having a structure capable of testing a memory in real-time using a built-in self-tester while the memory is in use, and an operation method thereof.

BACKGROUND

As the degree of integration of a memory increases, the time and cost required to test a memory increases.

Algorithms for detecting faults in a memory are largely divided into march test algorithms and a non-march test algorithms.

A march test algorithm can roughly detect faults (or errors) of a memory but has a short test time. A non-march test algorithm can accurately detect faults (or errors) of a memory but has a long test time.

A built-in self-tester (BIST) or a built-in tester is a device (or logic circuit) for performing a mechanism that permits an object to be tested by itself.

In the case of testing a semiconductor chip using an expensive external apparatus, the test cost increases. In the case of embedding a BIST or BIT into a semiconductor chip, the test cost decreases, but the BIST or BIT becomes redundant after the test. Also, since the BIST or BIT is embedded into the semiconductor chip, the size of the semiconductor chip increases.

SUMMARY

Accordingly, a technical object to be achieved by the present invention is to provide a memory controller capable of testing a memory in real time while the memory is in use by using a main controller configured to control the memory as a controller of a BIST, and an operation method thereof.

Also, another technical object to be achieved by the present invention is to provide a memory controller capable of allowing a user to directly input an operation command of the BIST.

A memory controller according to an embodiment of the present invention includes a built-in self-tester (BIST) configured to test a memory, a scheduler configured to change an execution order of memory commands to be transmitted to the memory, a main controller configured to control the memory, and a switch configured to connect one of an output of the scheduler and an output of the BIST to an input of the main controller in response to a control signal output from the BIST.

An operation method of a memory controller for controlling a memory according to an embodiment of the present invention includes a main controller performing a test operation on the memory using a test command output from a built-in self-tester (BIST) and the main controller controlling an operation of the memory using a first memory command output from a scheduler which changes an execution order of memory commands including the first memory command and a second memory command to be transmitted to the memory.

