FIELD OF THE INVENTION

The invention relates to Power over Data Lines (PoDL) systems, where DC power and data signals are provided over the same twisted wire pair, and, in particular, to techniques for equalizing the DC bias voltage across AC-coupling capacitors connected between the wires and the PHY.

BACKGROUND

FIG. 1is an example of one type of PoDL system where DC power and Ethernet differential data signals are provided over the same twisted wire pair. The Power Sourcing Equipment (PSE) is on the left side, and the Powered Device (PD) is on the right side.

A PHY10outputs differential data and receives differential data via a conventional Media Dependent Interface (MDI) connector12coupled to wires14and16of a twisted wire pair. The PHY10represents the physical layer in the OSI model and is a transceiver that typically includes signal conditioning and decoding circuitry for presenting bits to the next stage. The term PHY is a term of art and is defined by various IEEE standards, depending on the particular application. The PHY10is typically an integrated circuit. A digital processor (not shown) is coupled to the PHY10for processing the data. For purposes of this disclosure, the PHY10is a digital, differential data transceiver.

The PHY10is connected to the MDI connector12via AC-coupling capacitors C1and C2. The capacitors C1and C1prevent DC voltage being coupled to the PHY10inputs to avoid corrupting the differential data and also prevent the PSE power supply18being shorted out by the PHY10.

The PSE power supply18provides a suitable DC voltage across the wires14and16, such as 45 VDC.

DC-coupling inductors L1and L2provide a high impedance to the data signals and a low impedance to the DC voltage, so the power supply18impedance does not load the data signals.

The PD side may be identical to the PSE side except that the DC voltage is coupled to a PD load20via the DC-coupling inductors L3and L4. The AC-coupling capacitors C3and C4couple the differential data to the PHY22. An MDI24couples the wires14and16to the PD circuitry. The PD load20may be any powered device, such as a sensor, camera, etc.

PSE and PD controllers are not shown and perform a handshaking routine to ensure the PD is compatible with PoDL. If the PD is PoDL-compatible, the PSE controller closes a switch to supply the full DC voltage across the wires14and16.

Ceramic capacitors are commonly used in PoDL systems for AC-coupling due to their small size and other characteristics. It is well-known that the effective capacitance value of ceramic capacitors reduces as the DC voltage across the capacitor increases. Such a change in value is referred to as the DC bias characteristic of the capacitor or the capacitor's negative voltage coefficient. In some examples of ceramic capacitors used in PoDL systems, the nominal capacitance value (with 0V across it) is reduced by about 50% when the full PSE voltage of about 45 VDC is applied across it.

In the example ofFIG. 1, the capacitor C1sees approximately the full DC voltage of VPSE across it, while the capacitor C2sees about 0V across it. Therefore, the effective value of the capacitor C1is about half that of the capacitor C2. The same applies to the PD capacitors C3and C4.

As a result of this difference in effective capacitor values, the capacitors C1and C2produce non-symmetrical effects on the differential data signals and on common mode signals (e.g., noise signals). So the data paths are unbalanced. In an extreme instance, the differences could result in conversion of a common mode noise signal into a signal that the PHY10interprets as a data signal.

FIG. 2illustrates another example of a PoDL system, where a center-tapped transformer26is used to galvanically isolate the PHY10from the wires14and16. The PHY signals are magnetically coupled to the wire pair. The secondary windings28are coupled to the line-side, and the primary winding29is coupled across the terminals of the PHY10. AC-coupling capacitors C1and C2are also present to prevent the secondary windings28of the transformer26from shorting out the PSE power supply18. Since the center-tap of the transformer26is grounded, the DC bias across capacitor C1is approximately VPSE while the DC bias across the capacitor C2is approximately 0V. As a result, the capacitor C1capacitance is substantially less than the capacitor C2capacitance, leading to the same problems mentioned regardingFIG. 1.

What is needed is a technique whereby the AC-coupling capacitors in a PoDL system retain approximately equal effective values while blocking the DC voltage.

SUMMARY

Various PoDL circuits are described where the AC-coupling capacitors have approximately equal effective values at any DC bias voltage. The capacitors have the same nominal value at 0V bias.

In one embodiment of the inventive PoDL circuit, a first AC-coupling capacitor has one terminal coupled to the full PSE voltage of VPSE, and a second AC-coupling capacitor has one terminal coupled to approximately ground or other reference voltage, similar to the prior art. In the prior art, the other ends of both capacitors would be coupled to a low voltage, so there would be very different DC bias voltages across the two capacitors, causing their effective values to be very different. The present inventive technique uses a resistor divider to create the voltage VPSE/2. This voltage of VPSE/2 (instead of ground) is applied to the other ends of the capacitors, so both capacitors have VPSE/2 across them. Hence, even though the capacitance values have lowered due to the VPSE/2 bias, the capacitors' effective values remain equal. Therefore, the two data paths are balanced, resulting in more accurate data communication and higher efficiency.

In one example, the PoDL system uses a center-tapped transformer for isolation and to attenuate common mode noise. Instead of the center tap being coupled to ground, as in the prior art, the center tap is coupled to VPSE/2. In a related embodiment, the center tap is coupled to ground via an AC-coupling third capacitor to attenuate noise.

A common mode choke (CMC) may be added in series with the AC-coupling capacitors to further attenuate AC common mode noise.

In another embodiment, the same technique is employed in termination RC networks used to prevent reflections of any common mode noise on the twisted wire pair. The termination circuitry is generally designed to match the common mode impedance of the wire pair for maximum energy absorption and minimum reflectance while preserving the differential mode impedance presented by the transceiver. In the prior art, identical capacitor/resistors networks are used to terminate the wires in the PoDL system. In the prior art, both capacitors are coupled to ground, so one capacitor sees a high DC bias and the other capacitor sees a zero DC bias. This difference in DC bias voltages causes the termination networks to have different characteristics, possibly leading to the conversion of common mode noise signals to differential signals, corrupting the Ethernet data. By using the present invention, the voltage VPSE/2 is generated using a resistive divider, and the VPSE/2 voltage is applied to the common terminals of the termination capacitors instead of ground. Therefore, both termination capacitors see a DC bias voltage of VPSE/2, and their effective capacitances remain equal. Conversion of common mode noise signals is thus prevented due to the balanced termination networks.

