CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0014866, filed on Feb. 7, 2020, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

FIELD

The present disclosure relates to a semiconductor package, and in particular, to a semiconductor package including a connection structure formed by a print process.

DISCUSSION OF RELATED ART

A semiconductor package is configured to allow a semiconductor chip to be easily used as a part of an electronic product. Typically, the semiconductor package includes a substrate (e.g., a printed circuit board (PCB)) and a semiconductor chip mounted on the substrate. Various methods are used to electrically connect the semiconductor chip to the substrate. For example, a wire bonding method may be used to electrically connect the semiconductor chip to the substrate. The wire is formed of or includes a conductive material to electrically connect elements, which are connected thereto, to each other.

With recent advances in the electronics industry, there is an increasing demand for high-performance, high-speed and compact electronic components. To meet the demand, sizes of semiconductor packages are decreasing. Accordingly, various semiconductor packaging techniques are being used. For example, a semiconductor package device may be configured to include a plurality of semiconductor chips mounted on a package substrate, or to have a structure in which a package is stacked on another package.

SUMMARY

An embodiment of the inventive concept provides a semiconductor package configured to use an inner pad, which is provided between two pads disposed at an outer portion of a chip. An embodiment of the inventive concept provides a semiconductor package having a connection structure preventing a wire-to-wire short circuit. An embodiment of the inventive concept provides a semiconductor package with a reduced size.

According to an embodiment of the inventive concept, a semiconductor package may include a substrate including a first coupling terminal and a second coupling terminal, a first chip disposed on the substrate, the first chip including a first pad and a second pad, and a connection structure connecting the first coupling terminal to the first pad. A portion of the connection structure may be in contact with a first side surface of the first chip. The connection structure may include a connection conductor electrically connecting the first pad to the first coupling terminal.

According to an embodiment of the inventive concept, a semiconductor package may include a substrate, a first chip disposed on the substrate, a first semiconductor chip disposed on the first chip, and a second semiconductor chip disposed on the first semiconductor chip. The first chip may include a first pad, a second pad, and a third pad. The substrate may include a first coupling terminal electrically connected to the first pad, a second coupling terminal electrically connected to the second pad, and a third coupling terminal electrically connected to the third pad. The first coupling terminal and the first pad may be connected to each other by a connection structure. The connection structure may be formed by a printing process. The connection structure may include a connection conductor electrically connecting the first pad to the first coupling terminal.

According to an embodiment of the inventive concept, a semiconductor package may include a substrate, a first chip disposed on the substrate, a second chip disposed on the first chip, a first stack, which is horizontally spaced apart from the first chip and is electrically connected to the first chip, and a second stack, which is disposed on the first stack and is electrically connected to the second chip. The first stack may include a first semiconductor chip disposed on the substrate and a second semiconductor chip disposed on the first semiconductor chip. The first chip may include a first pad, a second pad, and a third pad. The second pad may be disposed between the first pad and the third pad. The substrate may include a first coupling terminal electrically connected to the first pad, a second coupling terminal electrically connected to the second pad, and a third coupling terminal electrically connected to the third pad. The first coupling terminal and the first pad may be connected to each other by a connection structure. A portion of the connection structure may be in contact with a first side surface of the first chip. The connection structure may include a connection conductor electrically connecting the first pad to the first coupling terminal.

