BACKGROUND

Embodiments of the present invention relate to power-driven synaptic network synthesis, and more specifically, to providing fault-tolerant power minimization in a multi-core neurosynaptic network.

BRIEF SUMMARY

According to one embodiment of the present invention, a method of and computer program product for power-driven neurosynaptic network synthesis are provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores connected by a plurality of routers. At least one faulty core of the plurality of neurosynaptic cores is located. A placement blockage is modeled at the location of the at least one faulty core. A placement of the neurosynaptic cores is determined by minimizing the wire length.

According to another embodiment of the present invention, a method of and computer program product for power-driven neurosynaptic network synthesis are provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores connected by a plurality of routers. At least one faulty router of the plurality of routers is located. A placement blockage is modeled. The placement blockage includes at least a core of the plurality of cores associated with the faulty router. A placement of the neurosynaptic cores is determined by minimizing the wire length.

