RELATED APPLICATION

The present application claims the benefit of Chinese Patent Application No. 201910615762.5, filed on Jul. 9, 2019, the entire disclosure of which is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to the field of display technologies, particularly to a display substrate, a manufacturing method thereof, a display panel, and a display device.

BACKGROUND

With the continuous development of display technology, display products are gradually developing toward high resolution, high color gamut, high image quality and long service life. An OLED (Organic Light Emitting Diode) display panel formed by an inkjet printing process has advantages of better performance and longer service life compared with an OLED display panel formed by an evaporation process, which is especially suitable for large-sized display products.

SUMMARY

An embodiment of the present disclosure provides a method for manufacturing a display substrate, comprising: forming a thin film transistor on a base substrate; forming a planarization layer covering the thin film transistor; forming a metal mask layer on the planarization layer; patterning the metal mask layer to form an etching hole in the metal mask layer, the etching hole exposing a portion of the planarization layer; etching the portion of the planarization layer exposed by the etching hole to form a first via hole penetrating the planarization layer, and removing the remaining metal mask layer on the planarization layer.

According to some embodiments of the present disclosure, the method for manufacturing a display substrate further comprises: prior to forming the planarization layer, forming, above the base substrate, a passivation layer covering the thin film transistor; and etching a portion of the passivation layer corresponding to the etching hole to form a second via hole penetrating the passivation layer, the second via hole communicating with the first via hole.

According to some embodiments of the present disclosure, a material of the metal mask layer comprises Cu or AlNd.

According to some embodiments of the present disclosure, processes of forming the first via hole and removing the remaining metal mask layer comprise: etching the portion of the planarization layer exposed by the etching hole using a first etching process to form the first via hole; removing the remaining metal mask layer on the planarization layer using a second etching process different from the first etching process.

According to some embodiments of the present disclosure, a process of forming the second via hole comprises: coating a photoresist on the planarization layer from which the remaining metal mask layer has been removed; patterning the photoresist to expose the first via hole; etching a portion of the passivation layer exposed by the first via hole using a third etching process to form the second via hole; and removing the photoresist on the planarization layer.

According to some embodiments of the present disclosure, the first etching process and the third etching process both comprise a dry etching process using a mixed gas of CF4and O2as an etching gas; the second etching process comprises a wet etching process using an acidic solution as an etching solution.

According to some embodiments of the present disclosure, a material of the metal mask layer comprises Au.

According to some embodiments of the present disclosure, processes of forming the first via hole and the second via hole, and removing the remaining metal mask layer comprise: etching the portion of the planarization layer exposed by the etching hole and a portion of the passivation layer corresponding to the etching hole using a fourth etching process to form the first via hole and the second via hole that communicate with each other; removing the remaining metal mask layer on the planarization layer using a fifth etching process different from the fourth etching process.

According to some embodiments of the present disclosure, the fourth etching process comprises a dry etching process using a mixed gas of CF4and O2as an etching gas; the fifth etching process comprises a wet etching process using a mixed solution of I2, KI and water as an etching solution.

According to some embodiments of the present disclosure, a gas flow ratio of CF4to O2in the mixed gas is 4:1 to 5:1.

According to some embodiments of the present disclosure, the metal mask layer has a thickness ranging from 3000 Å to 5000 Å.

According to some embodiments of the present disclosure, a thickness of the passivation layer is smaller than a thickness of the planarization layer.

According to some embodiments of the present disclosure, an orthographic projection of the etching hole on the base substrate at least partially overlaps an orthographic projection of a source or drain of the thin film transistor on the base substrate.

According to some embodiments of the present disclosure, a process of forming the thin film transistor on the base substrate comprises: forming a light shielding layer on the base substrate by a patterning process; forming a buffer layer covering the light shielding layer; forming an active layer on the buffer layer by a patterning process; forming a gate insulating layer and a gate successively on the active layer by a patterning process; forming an interlayer dielectric layer by a patterning process, the interlayer dielectric layer covering the buffer layer, the active layer, the gate insulating layer and the gate; forming a source and a drain on the interlayer dielectric layer by a patterning process, the source and the drain being connected to the active layer through via holes in the interlayer dielectric layer respectively.

Another embodiment of the present disclosure provides a display substrate manufactured by the method for manufacturing a display substrate descried in any one of the foregoing embodiments, the first via hole and the second via hole communicate with each other, and a size of a top opening of the first via hole is greater than a size of a top opening of the second via hole.

According to some embodiments of the present disclosure, a slope angle of the first via hole is smaller than a slope angle of the second via hole.

A further embodiment of the present disclosure provides a display panel comprising the display substrate described in the above embodiment.

Yet another embodiment of the present disclosure provides display device comprising the display panel described in the above embodiment.

