CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Patent Application No. 10-2019-0134103, filed on Oct. 25, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

The inventive concepts relate to an integrated circuit device and a method of manufacturing the same, and more particularly, to an integrated circuit device including a multi-layer wiring structure and a method of manufacturing the same.

With the rapid development of the electronics industry and in response to users' requests, electronic devices are reduced in size and/or provided with multiple functions. Thus, down scaling of integrated circuit devices is also making rapid progress, and the line widths and pitches of multi-layer wiring structures included in integrated circuit devices are decreasing. Accordingly, there is an increasing benefit to develop integrated circuit devices having multi-layer wiring structures in which a leakage of current is reduced or suppressed and/or parasitic capacitance is reduced, thus exhibiting improved electrical characteristics and/or reliability.

SUMMARY

The inventive concepts provide an integrated circuit device having improved electrical characteristics and/or reliability and a method of manufacturing the same by reducing or maximally reducing parasitic capacitance by forming an air gap around a wiring on which a via is located.

The inventive concepts also provide an integrated circuit device having improved electrical characteristics and/or reliability and a method of manufacturing the same by reducing or preventing a time dependent dielectric breakdown (TDDB) that may occur in an integrated circuit device by reducing or suppressing a current leakage in a multi-layer wiring structure.

Problems to be solved by the inventive concepts are not limited to the above-mentioned problems, and other problems not mentioned would be clearly understood by those skilled in the art from the disclosure below.

According to an aspect of the inventive concepts, there is provided an integrated circuit device including: lower wiring structures on a substrate, the lower wiring structures including an air gap arranged between the lower wiring structures; a capping layer covering an upper surface of the air gap; an etch stop layer conformally covering upper surfaces of the lower wiring structures and the capping layer and having a protrusion and recess structure; an insulating layer covering the etch stop layer; and an upper wiring structure penetrating the insulating layer and connected to the upper surface of the lower wiring structure not covered with the etch stop layer, wherein the upper wiring structure covers a portion of an upper surface of the capping layer, and a level of the upper surface of the capping layer is higher than a level of the upper surface of the lower wiring structures.

According to another aspect of the inventive concepts, there is provided an integrated circuit device including: lower wiring structures, which are spaced apart in a first direction on an upper surface of a substrate, extend in a second direction perpendicular to the first direction, and are flush with each other in a third direction perpendicular to the upper surface with air gaps between the lower wiring structures and having a first width or a second width which are different from each other in the first direction; capping layers covering an upper surface of the air gaps and having the first width or the second width; an insulating barrier layer surrounding a side surface and lower surface of the air gaps; an etch stop layer conformally covering upper surfaces of the lower wiring structures, a side surface of the insulating barrier layer, an upper surface of the insulating barrier layer, and an upper surface of the capping layers; an insulating layer covering the etch stop layer; and an upper wiring structure penetrating the insulating layer and connected to the upper surface of the lower wiring structure not covered with the etch stop layer, wherein the first width of the air gaps is less than a thickness of the capping layers in the third direction.

According to another aspect of the inventive concepts, there is provided an integrated circuit device including: a first lower wiring structure and a second lower wiring structure on a substrate; with an air gap therebetween; a capping layer covering an upper surface of the air gap; an insulating barrier layer surrounding a side surface of the air gap; an etch stop layer conformally covering an upper surface of the second lower wiring structure, a side surface of the insulating barrier layer, an upper surface of the insulating barrier layer, and an upper surface of the capping layer; an insulating layer covering the etch stop layer; and an upper wiring structure penetrating the insulating layer, connected to an upper surface of the first lower wiring structure, and having a protruding portion covering a portion of the upper surface of the capping layer, wherein a shortest distance between the first lower wiring structure and the second lower wiring structure closest thereto is less than a shortest distance between the protruding portion and the second lower wiring structure closest thereto.

