CROSS-REFERENCE TO RELATED APPLICATION APPLICATIONS

This application is the U.S. national phase of PCT Application No. PCT/CN2018/110639 filed on Oct. 17, 2018, which claims priority to Chinese Patent Application No. 201711083776.4 filed on Nov. 7, 2017, which are incorporated herein by reference in their entireties.

TECHNICAL FIELD

The present disclosure relates to the field of display technologies, and in particular to a pixel circuit, a method for driving the circuit and a display device.

BACKGROUND

One pixel compensation unit for a display device based on organic light emitting diodes (OLEDs) generally includes: a light sensing module used for converting a light signal emitted by a pixel unit into a corresponding electrical signal; a read-control module used for controlling transmission of the electrical signal to a reading line at a corresponding column during a reading period under control of a read control signal on a read-control line at a corresponding row; and a data voltage compensation module used for compensating a data voltage on a data line at a corresponding column according to the electrical signal. However, the above pixel compensation unit could not avoid influence of timing of gate and data lines on the light sensing module, and could not dynamically adjust integration time, which lead to an inaccurate compensation result.

SUMMARY

One embodiment of the present disclosure provides a pixel circuit including: a plurality of rows of gate lines; a plurality of rows of read-control lines; pixel unit circuits arranged in rows and columns; and a driving module. The pixel unit circuit includes a pixel compensation unit; the pixel compensation unit is coupled with the corresponding row of read-control line; the driving module includes a gate drive circuit coupled with the rows of gate lines, and a signal generation unit. The signal generation unit is coupled with the gate drive circuit and the pixel compensation unit, and is configured to generate a read-control signal and a gate drive-control signal, transmit the read-control signal to the corresponding row of read-control line and transmit the gate drive-control signal to the gate drive circuit. The gate drive circuit is configured to, based on the gate drive-control signal, generate a plurality of gate drive signals, thereby controlling the rows of gate lines to be turned off in a reading period.

In implementation, the pixel compensation unit includes a light sensing module configured to convert a light signal emitted by the pixel unit into a corresponding electrical signal; and the signal generation unit is configured to generate the read-control signal based on the electrical signal.

In implementation, the pixel compensation unit includes a read-control module; the pixel circuit further includes a plurality of columns of read lines; the read-control module is coupled with the corresponding column of read line; the electrical signal is a charge signal. The signal generation unit is specifically configured to determine a corresponding integration time based on quantity of electric charges indicated by the electrical signal and generate a corresponding read-control signal based on the integration time. The integration time is a time interval between a first moment and a second moment, the first moment is a moment at which the read-control module is controlled by the read control signal to begin transmitting the electrical signal to the corresponding column of read line, and the second moment is a moment at which the read-control module is controlled by the read control signal for the next time to begin transmitting the electrical signal to the corresponding column of read line after the reading period ends.

One embodiment of the present disclosure provides a method for driving the above pixel circuit, including: generating, by the signal generation unit, a read-control signal and a gate drive-control signal, and transmitting the read-control signal to the corresponding row of read-control line and transmitting the gate drive-control signal to the gate drive circuit; and generating, by the gate drive circuit based on the gate drive-control signal, a plurality of gate drive signals, thereby controlling the rows of gate lines to be turned off in a reading period.

In implementation, generating, by the signal generation unit, a read-control signal, specifically includes: generating, by the signal generation unit based on an electrical signal, the read-control signal; wherein the electrical signal is obtained by converting, by a light sensing module of the pixel compensation unit, a light signal emitted from the pixel unit.

In implementation, the pixel compensation unit includes a read-control module; the pixel circuit further includes a plurality of columns of read lines; the read-control module is coupled with the corresponding column of read line; the electrical signal is a charge signal. Generating, by the signal generation unit based on an electrical signal, the read-control signal, includes: determining, by the signal generation unit, a corresponding integration time based on quantity of electric charges indicated by the electrical signal and generating a corresponding read-control signal based on the integration time. The integration time is a time interval between a first moment and a second moment, the first moment is a moment at which the read-control module is controlled by the read control signal to begin transmitting the electrical signal to the corresponding column of read line, and the second moment is a moment at which the read-control module is controlled by the read control signal for the next time to begin transmitting the electrical signal to the corresponding column of read line after the reading period ends.

In implementation, the charge signal includes a first charge signal and a second charge signal, a first quantity of electric charges indicated by the first charge signal is greater than a second quantity of electric charges indicated by the second charge signal; a first integration time determined by the signal generation unit based on the first quantity of electric charges, is less than a second integration time determined by the signal generation unit based on the second quantity of electric charges.

In implementation, the pixel compensation unit includes a light sensing module and a read-control module; the pixel circuit further includes a plurality of columns of read lines; the read-control module is coupled with the corresponding column of read line. In one driving cycle, an n-th reading period is set between a period in which an n-th row of gate line is turned on and a period in which an (n+1)-th row of gate line is turned on; an N-th reading period is set in adjacent two driving cycles, where N is a quantity of rows of gate lines included in the pixel circuit, and N is a positive integer. Transmitting, by the signal generation unit, the read-control signal to the corresponding row of read-control line includes: outputting, by the signal generation unit, a corresponding read-control signal to an n-th row of read-control line, thereby enabling the read-control modules of all the pixel compensation units in the n-th row of the pixel circuit to be turned on in the n-th reading period and then turning on connection between the light sensing modules of the pixel compensation units in the n-th row and the corresponding columns of read lines; and outputting, by the signal generation unit, a corresponding read-control signal to an N-th row of read-control line, thereby enabling the read-control modules of all the pixel compensation units in the N-th row of the pixel circuit to be turned on in the N-th reading period and then turning on connection between the light sensing modules of the pixel compensation units in the N-th row and the corresponding columns of read lines. Generating, by the gate drive circuit based on the gate drive-control signal, a plurality of gate drive signals, thereby controlling the rows of gate lines to be turned off in a reading period, includes: generating, by the gate drive circuit based on the gate drive-control signal, a plurality of gate drive signals, thereby controlling all the gate lines in the pixel circuit to be turned off in the n-th reading period and the N-th reading period, where n is a positive integer and (n+1) is less than or equal to N.

In implementation, the pixel compensation unit includes a light sensing module and a read-control module; the pixel circuit further includes a plurality of columns of read lines; the read-control module is coupled with the corresponding column of read line. In one driving cycle, an n-th reading period is set between a period in which an n-th row of gate line is turned on and a period in which an (n+1)-th row of gate line is turned on; an (n+1)-reading period is set between the period in which the (n+1)-th row of gate line is turned on and a period in which an (n+2)-th row of gate line is turned on; an N-reading period is set in adjacent two driving cycles, where N is a quantity of rows of gate lines included in the pixel circuit, and N is a positive integer. Transmitting, by the signal generation unit, the read-control signal to the corresponding row of read-control line includes: outputting, by the signal generation unit, a corresponding read-control signal to an n-th row of read-control line, thereby enabling the read-control modules of all the pixel compensation units in the n-th row of the pixel circuit to be turned on in the n-th reading period and the (n+1)-th reading period, and then turning on connection between the light sensing modules of the pixel compensation units in the n-th row and the corresponding columns of read lines; and outputting, by the signal generation unit, a corresponding read-control signal to an N-th row of read-control line, thereby enabling the read-control modules of all the pixel compensation units in the N-th row of the pixel circuit to be turned on in the N-th reading period and the first reading period and then turning on connection between the light sensing modules of the pixel compensation units in the N-th row and the corresponding columns of read lines. Generating, by the gate drive circuit based on the gate drive-control signal, a plurality of gate drive signals, thereby controlling the rows of gate lines to be turned off in a reading period, includes: generating, by the gate drive circuit based on the gate drive-control signal, a plurality of gate drive signals, thereby controlling all the gate lines in the pixel circuit to be turned off in the n-th reading period and the N-th reading period, where n is a positive integer and (n+1) is less than or equal to N.

In implementation, the pixel compensation unit includes a light sensing module and a read-control module; the pixel circuit further includes a plurality of columns of read lines; the read-control module is coupled with the corresponding column of read line; a blank stage is set between two adjacent display stages; the blank stage includes M reading periods arranged sequentially, where M is a quantity of rows of read-control lines included in the pixel circuit, and M is a positive integer. Generating, by the gate drive circuit based on the gate drive-control signal, a plurality of gate drive signals, thereby controlling the rows of gate lines to be turned off in a reading period, includes: generating, by the gate drive circuit based on the gate drive-control signal, a plurality of gate drive signals, thereby controlling all the gate lines in the pixel circuit to be turned off in the blank stage. Transmitting, by the signal generation unit, the read-control signal to the corresponding row of read-control line includes: outputting, by the signal generation unit, a corresponding read-control signal to an a-th row of read-control line, thereby enabling the read-control modules of all the pixel compensation units in the a-th row of the pixel circuit to be turned on in the a-th reading period of the blank stage and then turning on connection between the light sensing modules of the pixel compensation units in the a-th row and the corresponding columns of read lines; where a is a positive integer which is less than or equal to M.

In implementation, the pixel compensation unit includes a light sensing module and a read-control module; the pixel circuit further includes a plurality of columns of read lines; the read-control module is coupled with the corresponding column of read line; a blank cycle is set between two adjacent display cycles. The blank cycle includes M reading periods arranged sequentially, M is a quantity of rows of read-control lines included in the pixel circuit, and M is a positive integer. Generating, by the gate drive circuit based on the gate drive-control signal, a plurality of gate drive signals, thereby controlling the rows of gate lines to be turned off in a reading period, includes: generating, by the gate drive circuit based on the gate drive-control signal, a plurality of gate drive signals, thereby controlling all the gate lines in the pixel circuit to be turned off in the blank cycle. Transmitting, by the signal generation unit, the read-control signal to the corresponding row of read-control line includes: outputting, by the signal generation unit, a corresponding read-control signal to a b-th row of read-control line, thereby enabling the read-control modules of all the pixel compensation units in the b-th row of the pixel circuit to be turned on in the b-th reading period of the blank cycle and then turning on connection between the light sensing modules of the pixel compensation units in the b-th row and the corresponding columns of read lines; where b is a positive integer which is less than or equal to M.

One embodiment of the present disclosure provides a display device including the pixel circuit.

