BACKGROUND

Game engines and simulation engines play an increasingly important role in graphics applications. One major task of such engines is to provide the most realistic and highest quality of graphics possible at a real-time performance comprising other features such as simulation capabilities. A software engine is typically provided as computer-executable code that is executed on a CPU. For example, the engine may typically run on a processor or microprocessor of a computing device, such as a CPU of a personal computer, a console, a mobile phone or a tablet. Hence, performance of the CPU may determine the performance of a software engine. The software engine may also access a graphics processing unit GPU. For example, the GPU can render lists of individual objects with a very high performance to graphics memory or video memory. A computer graphics scene may include a large number of objects with characteristics related to their 3D position and 3D orientation, behavior, material properties and the like. In order to achieve highly realistic scenes, the engine needs to consider the whole scene, which may often contain millions of objects that are to be rendered to the screen. For example, the engine may consider the behavior and interaction of light with individual objects and between the objects of the scene.

These engines offer an environment created specially to execute the functionalities that are specific to 3D video games and real-time simulations. Thus, engines enable functionality such as the management of an animated model, the collisions between objects, and the interaction between the player and the game. Many recent games, simulations and serious games use engines that go beyond visual and interaction aspects. For example, programmers can rely on a software physics engine to simulate physical laws within the virtual environment, a software audio engine to add music and complex acoustical effects, and a software artificial intelligence (AI) engine to program non-human players' behaviors. Properties expected for a 3D interface are very close to the ones for 3D video games. Thus, game engines may be used in any type of application that requires rendering of 3D graphics at a real-time performance, including applications in Virtual Reality (VR), Augmented Reality (AR), Mixed Reality (MR), or combinations thereof.

Specific developments in AI that are used in gaming and non-gaming applications have been enabled by an increase in computing power and availability of large data sets which may be used for machine learning. In one possible application of machine learning, known as supervised learning, a programmer gives a computer a set of sample data and a desired outcome, and the computer generates its own model on the basis of those data that it can apply to any future data. Other machine learning approaches include unsupervised learning and reinforcement learning. Within these broad approaches, many techniques can be applied including feature learning, anomaly detection, decision trees, artificial neural networks, Bayesian networks, and genetic algorithms.

Artificial intelligence functionality for gaming and non-gaming applications has been executed in computing devices by processing units such as CPUs and GPUs. However, as CPUs are all-purpose processors, performing artificial intelligence tasks has been inefficient. In contrast, some GPUs are good candidates for implementing AI applications, since they typically contain many more processing cores and can execute more software threads simultaneously. Thus, GPUs have expanded outside the graphics and video areas and into the domain of deep learning, where GPUs capabilities provide superior performance over CPUs.

Further research has led to the development of Intelligence Processing Units (IPUs), e.g., Google's Tensor Processing Unit (TPU), which are computing units dedicated to performing artificial intelligence tasks. IPUs have been mainly used in servers located in data centers, which may be effective in some circumstances, but the back-and-forth data transmissions required for updating applications and gathering feedback that constitute part of the machine learning data sets required for training is time-consuming and resource-wasteful. On top of this, IPUs solely implemented in servers do not provide a high level of privacy protection for users, as companies have to store user application data on their servers. Other techniques involve placing a dedicated AI processor on user devices, or combining the capabilities of local AI processing with server-based AI processing to achieve desired levels of security and performance. However, there still is a need for enhancing AI and graphics processing speeds.

Hence, improvements in the field of AI processors that can process large data sets required for machine learning while maintaining a high level of security and which can process the data at high speeds are required.

SUMMARY

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This summary is not intended to identify key features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

One or more problems are solved by embodiments of an electronic chip, a chip assembly, a computing device, and a method, as described herein.

A first aspect of the current disclosure includes a plurality of processing cores and at least one hardware interface coupled to the plurality of processing cores, wherein at least one processing core implements a first engine (e.g., one or more game engines and/or simulation engines) in hardware by dedicated electronic circuitry, wherein at least one of the processing cores implements one or more artificial intelligence engines in hardware by dedicated electronic circuitry, wherein the first engine is coupled to the artificial intelligence engine, and wherein the implementations are on-chip implementations. The hardware interface may be realized as a part of the at least one integrated circuit of the electronic chip. However, the hardware interface may also be realized as one or more further integrated circuits providing the functionality of interfacing the processing cores, including the hardwired first engine and hardwired artificial intelligence engine. The first engine and artificial intelligence engine may be directly coupled on a common processing unit to the chip may user a buffer or memory to exchange data between the game engine and/or simulation engine and artificial intelligence engine.

The verb “implement” as used throughout this application is directed at an implementation in hardware. Hence, a processing core may include a plurality of electronic circuits that are configured to realize functionality of a game and/or simulation engine and a plurality of electronic circuits that are configured to realize functionality of an artificial intelligence engine. The one or more processing cores are a dedicated electronic circuitry implementing or realizing the functionality of a game and/or simulation engine and artificial intelligence engine in hardware. Hence, the game and/or simulation engine may also be referred to as a hardware game and/or simulation engine or as a hardwired game and/or simulation engine or as an on-chip game and/or simulation engine, and likewise, the artificial intelligence engine also be referred to as a hardware artificial intelligence engine, a hardwired artificial intelligence engine, or as an on-chip artificial intelligence engine. Accordingly, the electronic chip may be referred to as an Engine on Chip (EOC) or Engine Processing Unit (EPU). The processing cores may implement the game and/or simulation engine and artificial intelligence engine as a plurality of hardwired electronic circuits implementing respective functionalities of a game and/or simulation engine and of an artificial intelligence engine, which may be arranged or assembled according to any suitable production process. Furthermore, a configured field programmable gate array (FPGA) could be used to implement the game and/or simulation engine, the artificial intelligence engine, or both, in hardware. The electronic chip may be provided as an integrated circuit that integrates all components and functionality of the hardwired game and/or simulation engine and hardwired artificial intelligence engine into a single chip or a plurality of chips.

The processing cores of the electronic chip may be regarded as functional units or modules of the electronic circuits of the electronic chip. For example, at least one of the one or more processing cores may be realized as an FPGA or any other form of an integrating circuit implementing a dedicated functionality. Accordingly, the electronic chip includes at least one integrated circuit realizing at least some of the one or more processing cores, wherein at least one of the processing cores implements the hardwired game and/or simulation engine, and wherein at least one of the processing cores implements the artificial intelligence engine.

The at least one hardware interface enables a direct interaction with the one or more processing cores. The hardware interface may be realized as a part of the at least one integrated circuit of the electronic chip. However, the hardware interface may also be realized as one or more further integrated circuits providing the functionality of interfacing the processing cores, including the hardwired game and/or simulation engine and artificial intelligence engine.

The hardwired game and/or simulation engine is configured to perform one or more tasks on input data thereby generating data sets. Preferably, the hardwired game and/or simulation engine may be implemented on a core that implements hardwired algorithms and code functions, which may be applied to data. This may enable faster graphics or simulation results in 2D, 3D or 4D (3D+time) even for stereo displays. The input data may be input by a user through suitable programming interfaces, captured by one or more external sensory mechanisms communicatively connected to the electronic chip via the at least one hardware interface, or any combination thereof. The sensory mechanisms may include, without limitations, optical sensors, inertial sensors, or combinations thereof. The input data may include one or more of an image data, 3D geometries, video data, audio data, textual data, haptic data, time data, position and orientation data, or any combination thereof.

In further embodiments, the electronic chip may include a memory configured to store data and to provide the data to one or more processing cores. For example, the game and/or simulation engine may store the preprocessed data in the memory and may issue a command to the on-chip artificial intelligence engine to read and further process the data. The artificial intelligence engine may use the memory or a different communication channel to communicate the results to the hardwired game and/or simulation engine. A register or a register set may be used to control properties of the memory, to indicate characteristics of the stored data and/or to control operation of the on-chip artificial intelligence engine. The input data may be stored in the memory, and may thereafter be retrieved by the hardwired game and/or simulation engine for performing one or more tasks thereon to generate data sets. In other embodiments, the data may be stored in an external main memory of the host system, which may be accessible via one or more ports of an on-chip memory controller.

In some embodiments, the one or more tasks performed by the hardwired game and/or simulation engine on the input data may be defined by and reflect the functionality of the game and/or simulation engine. The electronic chip may expose an interface for controlling the game and/or simulation engine according to its functionality. In some embodiments, the one or more tasks may be initiated via the interface of the on-chip game and/or simulation engine. The one or more tasks may be performed in real-time during the programming of a video game or other application, but may also be performed during application run-time (i.e., the actual real-time execution of the application by a user), whereby the game and/or simulation engine may process, in real time, data that may be used to generate data sets for the artificial intelligence engine. In yet another embodiment, the one or more tasks include one or more of determining how objects cast shadows over other objects, determining how objects are reflected in other objects, or determining how the light falling on one object illuminates other surrounding objects. In addition or as an alternative, the game and/or simulation engine may perform other and further tasks, including tasks directed at simulation and/or rendering of graphics scenes, such as a simulation of individual objects of the graphics scene, a determination of characteristics of objects of the graphics scene, rendering of one or more of the objects of the graphics scene, and the like. In addition or as an alternative, the game and/or simulation engine may perform one or more of viewport culling and coverage (z-) buffer culling to determine visibility of objects, voxelization of a scene as a preparation step for global illumination calculations, sparse voxel-based cone tracing for global illumination, muscle fiber mechanics and musculoskeletal skinning, finite element methods for biomechanical muscle modelling, fluid dynamics using SPH (smoothed-particle hydrodynamics) for realistic effects involving water volumes, volcanic lava volumes, and astrophysical effects, which may be related to surfaces of stars, real-time Eulerian water simulation, or realistic vegetation dynamics, and the like, in any combination. In another aspect of the current disclosure, the one or more tasks may include classifying input data into first and second data sets for processing by the artificial intelligence engine.

Performing the one or more tasks on the input data generates data sets that may be stored in the memory and retrieved by the artificial intelligence engine. The data sets may include at least a first data set including contextual data, and a second data set including target data. The term “context” or “contextual data”, as used in the current disclosure, refers to data related to the environment of a user employing a computing device including an EPU of the current disclosure. Thus, for example, contextual data may include 3D image data, 3D geometries, 3D entities, 3D sensory data, 3D dynamic objects, video data, audio data, textual data, time data, position and orientation data, lighting data, amongst others, of the environment surrounding a user. The term “target” or “target data”, as used in the current disclosure, refers to data related to current user or other entities (e.g., animals, objects, persons, places, etc.) that are prone to be identified through machine learning algorithms by the artificial intelligence engine. Thus, for example, target data may include 3D image data including target faces (e.g., a human or an animal face), 3D geometries, video data, audio data (e.g., the voice of a user of another person of interest), and textual data, amongst others.

Machine learning algorithms may include a training phase and an inference phase. The training of a machine learning algorithm, as well as the inference phase, may involve so-called “tensor operations”, or computational operations of multidimensional tensors. A multidimensional tensor refers to a multidimensional array of real numbers. Some tensor operations involved in a machine learning algorithm fall in a category called “tensor contraction”, which takes two tensors as input and applies operations such as multiplication and accumulation to the two tensors, resulting in an output tensor. Although these tensor contraction operations may be performed by general purpose CPUs or GPUs, certain characteristics of tensor contraction operations employed for machine learning, such as a consistent data flow, large number of multiplications, and specialized nature of non-multiplication operations, are not suitable to be performed in CPUs and GPUs. This may be especially the case for inference-requiring, autonomous applications that are interfaced to a user and require a real-time, fast processing. Thus, the on-chip, hardwired artificial intelligence engine of the current disclosure may be designed to be specifically tailored for performing such tensor contraction operations for machine learning. More specifically, the hardwired artificial intelligence engine of the current disclosure refers to a semiconductor, hardwired processing core that contains dedicated electronic circuitry for performing operations optimally for tensor operations and other operations specific to machine learning. For example, where a GPU may include hardware specific to quaternion operations, such operations, while related to linear algebra are not typically used in machine learning tensor operations. In contrast, permutations and noise generation are generally not implemented in GPUs, but are commonly used in machine learning.

According to an embodiment, the artificial intelligence engine is configured to perform machine learning algorithms on the data sets retrieved via the memory. The machine learning algorithms may be employed for training of the artificial intelligence engine, and for subsequent inference of new data. The machine learning algorithms may include, without limitations Naïve Bayes Classifiers Algorithms, Nearest Neighbours Algorithms, K Means Clustering Algorithms, Support Vectors Algorithms, Apriori Algorithms, Linear Regression Algorithms, Logistic Regression Algorithms, Neural Network Algorithms, Random Forest Algorithms, and Decision Trees Algorithms, amongst others, in any combination. Furthermore, the machine learning algorithms may combine one or more of a supervised learning, unsupervised learning, and reinforcement learning.

In a preferred embodiment, the artificial intelligence engine performs Neural Network (NN) algorithms on the data sets retrieved by the memory. Some kinds of NN that may be employed include, for example, Multi-Layer Perceptrons (MLP), Convolutional Neural Networks (CNN), and Recurrent Neural Networks (RNN).

The present disclosure thus provides a support for efficient, real-time, highly realistic rendering by implementing a game and/or simulation engine in hardware along with accelerated processing of tensor contraction operations used during machine learning and inferring for data recognition and other autonomous tasks. The electronic chip of the current disclosure may be suitable for use in applications requiring a high degree and speed of data processing and recognition, especially 3D applications that may be used for drones, autonomous driving, robotics, machine and computer vision, personal assistants, video games, etc. The electronic chip may be used to support a CPU of a host system, such as a console, mobile device, or head-mounted displays, by providing dedicated 3D graphics hardware and dedicated artificial intelligence training and inference hardware. However, since the hardware implements a game and/or simulation engine and an artificial intelligence engine, control of the hardware may be simplified since interfaces of the game and/or simulation engine and of the artificial intelligence engine may be used. Hence, an average graphics programmer that needs to write high-performance and highly realistic applications may use the hardwired game and/or simulation engine and artificial intelligence engine, which maintains a simple interface while providing the programmer with highly realistic real-time rendering and machine learning and inference options.

Moreover, employing contextual data in combination with target data of the current disclosure may enhance speed of recognition tasks performed by the artificial intelligence engine through machine learning algorithms, since the contextual data may provide an extra layer of information to the artificial intelligence engine. This extra layer of information may be used during training and inference of data to increase the probabilities of recognizing a specific target depending on the context where the target is located, which may enhance computing speeds and may reduce required computing power by any of the one or more processing cores. For example, if an individual target is found in a majority of situations in a specific place, using the contextual data, the artificial intelligence engine may reduce the probabilities of finding the individual target in another location, thus increasing the probabilities of finding the individual in the “usual” locations, reducing the computing power and the time required to perform the necessary processing. In addition, since the processing is done directly through the EPU including the coupled hardwired game and/or simulation engine and hardwired artificial intelligence engine, processing times may be accelerated because the coupled hardwired game and/or simulation engine and hardwired artificial intelligence engine process native data from the software game and/or simulation engine and software artificial intelligence engine without necessarily requiring data transmission and processing to CPUs or GPUs. In addition, coupling the game and/or simulation engine directly to the artificial intelligence engine, the data exchange speed and throughput can be greatly improved and optimized since data exchange can be carried out via short data links and no complex data exchange protocol needs to be implemented.

According to an embodiment, antennas may be configured to transmit and receive radio waves that enable mobile communication with the EPU. Antennas may be connected through wired or wireless means to compute centers. In other embodiments, the antennas are provided within the compute centers and/or areas services by compute centers. In some embodiments, in order to service host systems located outdoors, the antennas may include millimeter wave (mmW)-based antenna systems or a combination of mmW-based antennas and sub 6 GHz antenna systems. In other embodiments, the antennas may include other types of antennas, such as 4G antennas, or may be used as support antennas for the mmW/sub GHz antenna systems. In embodiments where antennas used for servicing host systems located indoors, the antennas may use wireless local area networking (WiFi), preferably, but not limited to, providing data at 16 GHz.

According to an embodiment, the on-chip game and/or simulation engine includes a dedicated on-chip artificial intelligence engine implemented by dedicated electronic circuitry on at least one common processing core, herein referred to as an engine core. The engine core may provide functionality in hardware of a game and/or simulation engine and of an artificial intelligence engine. Providing the game and/or simulation engine and artificial intelligence engine on a single, common hardware processing core may reduce processing times by enabling fast communication via short data links. Additionally, implementing an artificial intelligence engine dedicated to a single game and/or simulation engine may improve efficiency because the artificial intelligence engine may only need to process data sent by the game and/or simulation engine to which it is dedicated.

According to an embodiment, the game and/or simulation engine may be separated into individual, dedicated hardwired components comprising a 3D structures processor, a physics processor, a communications unit, and an optional rendering engine, each implemented in hardware by dedicated circuitry in a common engine core along with an artificial intelligence engine. The 3D structures processor may be configured to perform 3D data algorithms in order to determine a faithful approximation of a given surface's geometry and processing of images into suitable data structures (e.g., octrees, quadtrees, BSP trees, sparse voxel octrees, 3D arrays, and k-d trees). The physics processor may perform algorithms that provide an approximate simulation of certain physical systems, such as rigid body dynamics (including collision detection and crowd steering), soft body dynamics, mass particle dynamics, and fluid dynamics. The communications unit may include one or more dedicated transceivers to receive and send communication signals from and to antennas, Wi-Fi, or combinations thereof. Preferably, the one or more dedicated transceivers are millimeter-wave (mmW) transceivers. The rendering engine may perform rendering algorithms on data in order to synthesize images to generate photorealistic 3D models.

According to an embodiment, the common engine core comprises 3D structures processor, an artificial intelligence engine, a simulation engine, a communications unit, a position engine, and a rendering engine, each implemented in hardware by dedicated circuitry. A chip comprising the common engine core may act as a position-based game and/or simulation engine and artificial intelligence engine, providing an accurate position and orientation that may drive a plurality of applications. In some embodiments, the 3D structures processor requests the position and orientation of a respective client device implementing a chip comprising the common engine core to the position engine, in order to increase the accuracy of the position and orientation of the client device with respect to other elements around a user. In some embodiments, the position engine may, upon receiving a position and orientation request from the 3D structures processor, request and receive global satellite navigation system (GNSS) radio signals, which refers collectively to multiple satellite-based navigation systems like GPS, BDS, Glonass, Galileo, QZSS, and IRNSS, and thereby through techniques such as triangulation or trilateration, perform hardware-based algorithms to calculate position of respective client devices. In other embodiments, the position engine may further communicate to the communications unit and obtain further position data of respective client devices through cellular network positioning techniques using 4G antennas, mmW or cmW antennas (e.g., through 5G networks), or combinations thereof, by employing antenna triangulation methods such as TOA and AOA; may utilize indoor tracking techniques such as WiFi; or may utilize other tracking techniques known in the art. In other embodiments, the position engine may further obtain position-and-orientation-related sensory data from one or more sensory mechanisms connected to the chip via the hardware interface, such as one or more Inertia Measuring Unit (IMU), accelerometers, gyroscopes, cameras, eye-tracking sensors, and the like. In other embodiments, the position engine may further request and obtain position-and-orientation data of respective client devices from the 3D structures processor, whereby the 3D structure of entities around a user and the 3D structure of a user (e.g., the 3D structure of a 3D user avatar) can provide the position engine with further information to calculate the position and orientation of the respective client device. In other embodiments, the position engine can calculate the position and orientation of respective client devices by combining methods described above.

In some embodiments, the simulation engine comprises dedicated hardware circuitry configured to implement algorithms for simulating the behavior, functions and abstract or physical properties of real-world objects into virtual replicas in a virtual world, and to predict such characteristics. The simulation engine may obtain a plurality of data related to each real-world object through various methods, such as by inputting data sets through a virtual replica editor that may be part of a computer aided drawing (CAD) software or other similar system, by inputting sensory data of each of the real-world objects that can serve to enrich and/or complement the input data, or by using combinations thereof. For example, the real-world object data may be obtained by inputting a building information model (BIM), which provides a plurality of features related to the appearance and operations of a building. In another example, the real-world object data may be obtained by inputting the virtual model of a car providing a plurality of features related to the appearance and operations of the car. In another example, radar-imaging, such as synthetic-aperture radars, real-aperture radars, AVTIS radars, Light Detection and Ranging (LIDAR), inverse aperture radars, monopulse radars, and other types of imaging techniques may be used to map and model real world entities before integrating them into the virtual world.

The simulation engine may further obtain a client device position and orientation data from the position engine in order to simulate said position and orientation data into the virtual replica, or to further predict the position and orientation of the client device. By way of example, the simulation engine may be used in a chip implemented in a self-driving vehicle or drone in order to predict their immediate path. The prediction may be performed by obtaining the current position, orientation, speed and acceleration of the self-driving vehicle or drone and using these data to interpolate their immediate path.

In some embodiments, the communications unit includes hardware configured to receive wireless radio waves from antennas and to send the data back to the antennas, which may as well be used for enabling an accurate tracking of the host system. In some embodiments, mmW transceivers may be employed, which may be configured to receive mmW wave signals from antennas and to send the data back to antennas. In some embodiments, tracking may be performed employing several techniques known in the art, such as time of arrival (TOA), angle of arrival (AOA), or other tracking techniques known in the art (e.g., visual imaging, radar technology, etc.).

In another embodiment, the communications unit implements, in hardware, a distributed ledger-based communications pipeline between users of a host device including an electronic chip according to embodiments of the current disclosure. The distributed ledger-based communications pipeline may enable direct communication between users through a decentralized network by allowing storage of information in a secure and accurate manner using cryptography, employing cryptographic “keys” and cryptographic signatures. Once the information is stored, the data becomes an immutable database and is governed by rules of the network.

In yet another embodiment, a plurality of the processing cores implement a plurality of game and/or simulation engines and a plurality of artificial intelligence engines, wherein each of the plurality of game and/or simulation engines is associated with a single one or at least one of the plurality of artificial intelligence engines.

In an alternative embodiment, at least one of the processing cores implements a central processing unit. Hence, the at least one processing core may be an electronic circuitry that carries out instructions of a computer program by performing basic arithmetic, logical, control and input/output (I/O) operations. The functionality of the central processing unit may be the same or similar to that of existing CPUs. The central processing unit may allow an execution of software according to an instruction set architecture directly on the electronic chip. The software may be dedicated to processing of the game and/or simulation engine and artificial intelligence engine. However, it is to be understood that the central processing unit is not restrictive to processing of the game and/or simulation engine and artificial intelligence engine only but may, rather, execute any kind of software which may exploit the functionality of the electronic chip. The electronic circuitry may include at least one respective microcontroller, microprocessor or digital signal processor (DSP) on the single electronic chip in any combination. In order to enable operation of the central processing unit, the electronic chip may further comprise memory blocks, such as a selection of ROM, RAM, EEPROM and/or flash memory, timing sources including oscillators and phase-locked loops, peripherals including counter timers, real-time timers and power-on reset generators, external interfaces, such as USB, Firewire, Ethernet, SPI, and the like, analog interfaces including ADCs and DACs, voltage regulators and power management circuits on the electronic chip, in any combination. Some of these components may form part of the electronic circuitry realizing the at least one processing core implementing the central processing unit while others may be separate and dedicated components of the electronic chip that are realized by one or more electronic circuits implementing the desired functionality. The game and/or simulation engine and artificial intelligence engine may be directly coupled to the central processing unit and/or may utilize a buffer or memory to exchange data between the central processing unit and the game and/or simulation engine. The central processing unit may also include further interfaces to directly couple to the hardwired game and/or simulation engine and hardwired artificial intelligence engine. By coupling the game and/or simulation engine and artificial intelligence engine to the central processing unit using dedicated data links and/or buffers, the data exchange speed and throughput can be greatly improved and optimized since data exchange can be carried out via short data links and no complex data exchange protocols need to be implemented.

In a further embodiment, a plurality of the processing cores implement a plurality of central processing units, each central processing unit being configured to execute instructions of a different instruction set architecture. Hence, the electronic chip may execute software on the individual central processing units, which may be compiled for different systems, including but not limited to Intel's x86 architecture as commonly used in personal computer systems, and systems based on the ARM instruction set, which is typically used in mobile phones and tablets. Hence, the electronic chip may be used in a heterogeneous environment providing a unified access to a well-defined game and/or simulation engine interface for a broad range of software, without requiring an adaptation of the software to a particular instruction set architecture.

According to an embodiment, an instruction set architecture that may be suitable for use by software employed by the EPU includes an extendable instruction set computer (EISC) architecture, which may be designed specifically to perform high-level operations required by the on-chip game and/or simulation engine and on-chip artificial intelligence. In other embodiments, instruction set architectures such as the complex instruction set architecture (CISC), the reduced instruction set architecture (RISC), or other suitable instruction set architectures known in the art may be used by software employed by the EPU.

In another alternative embodiment, the game and/or simulation engine and artificial intelligence engine are configured to communicate data via the hardware interface with an external GPU. The game and/or simulation engine and artificial intelligence engine may receive data from an external entity, such as a CPU or GPU, via the at least one hardware interface. The game and/or simulation engine and artificial intelligence engine may send processed data via the hardware interface to the external entity or another external entity. Preferably, the hardware interface may be a bus interface or an external interface. The processed data may be supplied to the external GPU for further processing and/or rendering on a target display, or for providing complementary machine learning algorithm processing.

In yet another alternative embodiment, at least one of the processing cores implements a graphics processing unit (GPU) (in hardware). Hence, the GPU can be regarded as a hardwired graphics processing unit on the electronic chip. The at least one hardware interface may include a media interface, such as HDMI and the like, which may provide data rendered by the on-chip graphics processing unit to a display or screen. However, it is to be understood that the graphics processing unit may also interface, via the hardware interface, with a bus or other interconnect of a host system to provide the rendered data for display.

In yet another embodiment, the game and/or simulation engine and artificial intelligence engine are configured to generate data for the GPU. The game and/or simulation engine and artificial intelligence engine may pre-process input data that may be suitable for processing on the specialized hardware of the GPU, which may include SIMD processing or vector processing as is known in the art. The preprocessed data may be provided to the on-chip GPU, which may further process the data and/or generate a final rendering of the graphics scene based on the preprocessed data or for providing complementary machine learning algorithm processing. The graphics processing unit may also provide the results to the game and/or simulation engine and artificial intelligence engine for further processing. Hence, the game and/or simulation engine and artificial intelligence engine may prepare data or data sets and offload specific tasks to the GPU in order to exploit the GPU functionality or the specialized hardware of the GPU.

In some embodiments, the game and/or simulation engine and artificial intelligence engine may store the preprocessed data in the memory and may issue a command to the on-chip GPU to read and further process the data. The on-chip graphics processing unit may use the memory or a different communication channel to communicate the results to the hardwired game and/or simulation engine and/or artificial intelligence engine. A register or a register set may be used to control properties of the memory, to indicate characteristics of the stored data and/or to control operation of the on-chip GPU.

In yet another embodiment, the graphics processing unit is connected to a video memory and the game and/or simulation engine and artificial intelligence engine are configured to provide data to the GPU via the video memory. The on-chip GPU may be connected to a dedicated video memory, which may be used internally by the graphics processing unit to load, store or buffer data during processing of the graphics processing unit. The video memory may be located on an interposer as a stack of memory chips. The video memory may be further coupled, for example, via the at least one hardware interface, to the at least one processing core implementing the game and/or simulation engine or to the at least one processing core implement the artificial intelligence engine, thereby enabling the game and/or simulation engine and artificial intelligence engine to directly load and store data to the video memory. This may further improve speed and throughput of data exchange between the hardwired game and/or simulation engine, the artificial intelligence engine, and the on-chip GPU without departing from a standard design of the GPU, which may simplify the design and fabrication of the chip.

In another embodiment, the electronic chip may include a further video encoder and decoder and a display. The video encoder and decoder may perform various dedicated functionality directed at encoding and decoding of video sequences. The display may either be a display configured to display at least some of the output of the one or more processing cores (e.g., game and/or simulation engine, artificial intelligence engine, or the optional GPU) or may be configured to display a state of the chip, by, for example, using a plurality of status indicators. Furthermore, the display may also be configured as an interface to provide data to an external display.

According to an embodiment, the at least one hardware interface may be enabled to provide data for individual components of the chip, such as the game and/or simulation engine, artificial intelligence engine, the GPU, the CPU, the video encoder and decoder, and/or to output data generated by the individual components, such as data generated by the game and/or simulation engine, the artificial intelligence engine, the GPU or the CPU. The hardware interface may be configured to comply with one or more standards, such as USB, HDMI and the like.

According to a further aspect, a chip assembly is provided that comprises at least one chip according to embodiments of the present disclosure. The chip may preferably comprise one or more processing cores and at least one hardware interface coupled to at least one of the one or more processing cores, wherein at least one of the one or more processing cores implements a game and/or simulation engine and wherein at least one of the processing cores implements an artificial intelligence engine. The chip assembly may comprise a silicon interposer or carrier, board or substrate to mount the at least one chip and other components of the chip assembly.

As used throughout this disclosure, a chip can be regarded as a layer of transistors, which may further comprise a plurality of layers of metal interconnects on top of the layer of transistors. The layer of transistors may be difficult to produce, in particular for very small transistors. Furthermore, a first layer of the metal interconnect, which may include very fine metal wires, may also be hard to produce. A skilled person may understand that a majority of failures may occur in the production of these layers. The upper layers may have thicker wires and are, in comparison, easier to produce and seldom cause production failures. Hence, they may be used to connect major areas of the chip together.

A (silicon) interposer as used throughout this disclosure may be a generally very large chip with only upper layers of interconnects that may use thicker wires. Hence, the (silicon) interposer can be designed and produced cheaper with existing chip fabrication equipment. Although the wires may be relatively thick, a (silicon) interposer may include tens of thousands of wires.

A chip assembly as used throughout this disclosure may refer to a combination of a plurality of (sub-)chips on one silicon interposer. Hence, a chip assembly may be functionally equivalent to a single chip that may be very big. This is particularly advantageous if during production or fabrication, a single chip would become very big and therefore too costly to produce, for example due to higher defect rates. Accordingly, the design of the single chip could be subdivided into multiple separate (sub-)chips, which can be smaller. The smaller chips can be tested first and those that pass the test can then be connected together on a silicon interposer in the chip assembly. Furthermore, a whole range of designs can be made of different sizes, at little extra cost, by placing several equal small chips on an appropriately sized silicon interposer. Accordingly, the at least one chip of the chip assembly according to embodiments of the present disclosure may be subdivided into multiple separate smaller (sub-)chips that are connected together on the silicon interposer or carrier of the chip assembly.

A silicon interposer can be used to establish tens of thousands of connections between multiple chips on the chip assembly. It is to be understood that the silicon interposer may establish significantly more interconnects than provided by a carrier, board or substrate to mount the at least one chip. A silicon interposer may cover an entire area of all (sub-)chips that are interconnected by the silicon interposer.

In yet another embodiment, a chip assembly may be interconnected using micro-bridges comprising the interconnect layers. Micro-bridges may only cover edges of adjacent (sub-)chips providing the interconnections between these adjacent (sub-)chips.

In one embodiment, the chip assembly may further comprise at least one central processing unit, wherein the central processing unit is connected to the hardware interface of the chip. The central processing unit may be connected to the hardware interface via a bus or any other suitable interface or interconnect of the chip assembly.

In yet another embodiment, the chip assembly may further comprise at least one graphics processing unit, wherein the at least one graphics processing unit is connected to the hardware interface of the chip.

In yet another embodiment, the chip assembly further comprises a memory controller configured to exchange data with the game and/or simulation engine and the artificial intelligence engine of the chip.

Hence, the chip assembly may integrate the electronic chip implementing the hardwired game and/or simulation engine and artificial intelligence game and/or simulation engine and may further include one or more dedicated components, including a central processing unit, a graphics processing unit and/or a memory controller that may form part of the chip assembly but which may be off-chip with regard to the chip implementing the hardwired game and/or simulation engine and artificial intelligence engine. These components may be, however, distinct from components of a host system and components of the electronic chip implementing the hardwired game and/or simulation engine and artificial intelligence engine, such as on-chip central processing unit(s), on-chip GPU(s) and/or an on-chip memory controller. By using an off-chip implementation and integration of these components in the chip assembly, standard components for the central processing unit, the GPU and the memory controller may be used, which may simplify design, processing and fabrication of the chip assembly and reduce respective costs. The chip assembly and its components may be arranged on a carrier, board or substrate that may include an interconnect for the individual components of the chip assembly.

In one embodiment, the chip assembly may include a plurality of stacked integrated circuits, wherein an integrated circuit is stacked on top of another integrated circuit or on an interposer chip. The (vertically) stacked integrated circuits may be connected by Through Silicon Vias (TSV). TSVs are vertical electrical connections passing through a silicon wafer or die. Alternatively the (vertically) stacked integrated circuits may be connected using inductive coupling technology to enable near field wireless communication between the (vertically) stacked integrated circuits. The integrated circuits may realize or implement in hardware one or more of the electronic chip, including the one or more processing cores implementing the hardwired game and/or simulation engine, the artificial intelligence engine, the central processing unit, the graphics processing unit, the memory controller and further components and interfaces of the chip assembly, in any combination. A stacked design may be regarded as a variation of the interposer.

It should be noted that the use of the term silicon in “Silicon Interposer” or “Through Silicon Via” merely stems from the fact that silicon is a dominant material used as a wafer substrate in chip production. However, it is to be understood that embodiments of the present disclosure are not restricted to a particular material. Other materials suitable for application in embodiments of the present disclosure include Germanium, Gallium Arsenide, Indium Arsenide, and the like, in any combination. Accordingly, a respective interposer or through via may be used in corresponding embodiments.

In one embodiment, the chip assembly may be included in a package. Preferably, the chip assembly can be included in a graphics processor package or a game and/or simulation engine processor package. Preferably, the chip assembly may be included in a system in package (SiP) or a package on package. The package including the chip assembly may be easily integrated into a great variety of target environments in order to enable a high performance and realistic rendering of computer graphics along with highly efficient and accurate machine learning processing.

In a system in package (SiP), a number of integrated circuits may be enclosed in a single module (package). The SiP performs all or most of the functions of an electronic system, and may be used for mobile phones, digital media players, and the like. Dies containing the integrated circuits may be stacked vertically on a substrate, carrier or board. They may be internally connected by wires that may be bonded to the package. Alternatively, a flip chip technology may be applied, where solder bumps are used to join stacked chips together. SiP dies can be stacked vertically or tiled horizontally to produce a dense multi-chip package. SiP can connect the dies with standard off-chip wire bonds or solder bumps, or may at least partially use a technology similar to three-dimensional integrated circuits which connect stacked silicon dies with conductors running through the die. The SiP can include one or more of specialized processors, DRAM, flash memory, and other active components, which may be combined with passive components, such as resistors and capacitors that may be all mounted on the same board, carrier or substrate. The SiP represents a complete functional unit that can be built in a multi-chip package without further external components. This is advantageous in space-constrained environments, like mobile devices or head-mounted displays. The complexity of the printed circuit board and overall design may thus be greatly reduced.

According to an embodiment, a system according to the current disclosure may include a CPU coprocessor together with an engine coprocessor. The game and/or simulation engine coprocessor can be understood as a separate chip, optionally with its own package, which may be connected to the CPU via an interface bus, such as a PCI express bus, or any other bus interface or interconnect. The system including a CPU coprocessor together with an engine coprocessor may be used, for example, in a server, and may be configured to support edge-processing (i.e., processing performed by client devices, such as mobile phones or head-mounted displays). However, it may be understood that the system including a CPU together with an engine coprocessor may also be employed in a client device. The engine coprocessor may include one or more chips incorporating one or more hardwired game and/or simulation engines and one or more artificial intelligence engines. The engine coprocessor may further comprise a memory controller and a hardware interface to communicate with the CPU. The CPU may include one or more CPU cores, a memory controller, and a hardware interface. In other embodiments, the engine coprocessor may include an engine core implementing a 3D structures processor, an artificial intelligence engine, a physics processor, a communications unit, and a rendering engine, whereby implementations are in hardware by dedicated electronic circuitry. In other embodiments, no rendering engine is included in the engine core of the game and/or simulation engine coprocessor. The CPU may issue commands to the engine coprocessor which may then prepare data sets and commands that can be communicated back to the CPU. A higher performance can be reached by offloading CPU tasks to the game and/or simulation engine coprocessor. The dedicated memory controller on the engine coprocessor may allow the engine coprocessor to use its local memory to perform specific game and/or simulation engine and machine learning tasks. This may advantageously improve performance by increasing I/O speed and bandwidth.

According to yet another aspect, a computing device is provided, which includes at least one chip or chip assembly according to embodiments of the current disclosure, a host CPU and GPU, a power source, a memory, and I/O module, and sensing mechanisms. The chip or chip assembly may thus be used to support the host CPU and GPU by performing game and/or simulation engine tasks and machine learning algorithms as disclosed. The computing device may be a mobile device, a head-mounted display, a personal computer, a game console, a server computer, and the like.

According to an embodiment, a method for accelerated graphics processing and machine learning algorithm computations is provided. The method includes providing, on a computing device, at least one electronic chip including at least a hardware interface, and one or more processing cores including one or more game and/or simulation engines and one or more coupled artificial intelligence engines; providing a memory or memory controller communicatively connected to an external memory; obtaining input data, and transferring the data to the game and/or simulation engine via the memory; performing, by the game and/or simulation engine, one or more tasks on the sensory data in order to generate at least a first and a second data set, and transferring the data sets to the artificial intelligence engine via the memory; applying, by the artificial intelligence engine, machine learning algorithms on the data sets; checking whether there is more input data, in which case the method may loop back to obtaining the new input data, and, in negative case, the method may end.

According to yet another aspect, a computer-readable medium is provided, wherein the computer-readable medium stores instructions thereon that, when installed on and executed by a computing device, cause the computing device to perform a method according to embodiments of the present disclosure. Preferably, the method may include a fabrication of an electronic chip and/or an operation of the electronic chip according to embodiments of the present disclosure.

