CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional application claims the benefit of priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2019-0130075, filed on Oct. 18, 2019, in the Korean Intellectual Property Office, the entire disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Various example embodiments of the present inventive concepts relate to a semiconductor fabrication method, semiconductor device, and/or semiconductor fabrication system, and more particularly, to an overlay correction method and/or a semiconductor fabrication method including the same.

An overlay measurement process is used to detect the degree of distortion between lower and upper patterns on a semiconductor substrate. The overlay measurement process may be performed at many positions of the substrate, and thus a plurality of measurement values may be obtained. The overlay measurement process may yield a plurality of different overlay measurement values for many positions of the substrate.

SUMMARY

Various example embodiments of the present inventive concepts provide an overlay correction method that increases the uniformity of overlay correction values, and a semiconductor fabrication method including the same.

In at least one example embodiment, an overlay correction method may include: measuring, using processing circuitry, a lower pattern on a substrate to obtain a first central line of the lower pattern; forming, using the processing circuitry, a photoresist pattern on the lower pattern; measuring, using the processing circuitry, a first distance between a second central line of an upper flat surface of the lower pattern and a third central line of the photoresist pattern; calculating, using the processing circuitry, an after-development-inspection (ADI) overlay value based on the measured first distance; measuring, using the processing circuitry, a second distance between the second central line and the first central line; calculating, using the processing circuitry, an asymmetrical overlay value based on the measured second distance; forming, using the processing circuitry, an upper pattern on the substrate using the photoresist pattern; measuring, using the processing circuitry, a third distance between the first central line and a fourth central line of the upper pattern; calculating, using the processing circuitry, an after-cleaning-inspection (ACI) overlay value based on the measured third distance; calculating, using the processing circuitry, a first overlay skew value based on the ADI overlay value and the ACI overlay value; calculating, using the processing circuitry, a second overlay skew value based on the asymmetrical overlay value and the first overlay skew value; and adjusting, using the processing circuitry, a position of the photoresist pattern based on the second overlay skew value.

In at least one example embodiment, an overlay correction method may comprise: forming, using processing circuitry, an upper thin layer on a lower pattern of a substrate; forming, using the processing circuitry, a photoresist pattern on the upper thin layer; measuring, using the processing circuitry, a first distance between a central line of an upper flat surface of the lower pattern and a central line of the photoresist pattern; calculating, using the processing circuitry, an after-development-inspection (ADI) overlay value based on the measured first distance; measuring, using the processing circuitry, a second distance between a central line of the lower pattern and the central line of the upper flat surface; calculating, using the processing circuitry, an asymmetrical overlay value based on the second distance; etching, using the processing circuitry, the upper thin layer using the photoresist pattern as an etching mask to form an upper pattern on the substrate; measuring, using the processing circuitry, a third distance between the central line of the lower pattern and a central line of the upper pattern; calculating, using the processing circuitry, an after-cleaning-inspection (ACI) overlay value based on the measured third distance; calculating, using the processing circuitry, a first overlay skew value based on the ADI overlay value the ACI overlay value; updating, using the processing circuitry, the asymmetrical overlay value based on a weighting coefficient; calculating, using the processing circuitry, a second overlay skew value based on the asymmetrical overlay value and the first overlay skew value; and adjusting, using the processing circuitry, a position of the photoresist pattern based on the second overlay skew value.

In at least one example embodiment, a semiconductor fabrication method may comprise: forming, using processing circuitry, a lower pattern on a substrate; obtaining, using the processing circuitry, a first central line of the lower pattern using an electron microscope; forming, using the processing circuitry, an upper thin layer on the lower pattern; forming, using the processing circuitry, a photoresist pattern on the upper thin layer; measuring, using the processing circuitry, a first distance between a second central line of an upper flat surface of the lower pattern and a third central line of the photoresist pattern using an optical microscope; calculating, using the processing circuitry, an after-development-inspection (ADI) overlay value based on the measured first distance; calculating, using the processing circuitry, an asymmetrical overlay value that corresponds to a second distance between the second central line and the first central line; etching, using the processing circuitry, the upper thin layer using the photoresist pattern as an etching mask to form an upper pattern; measuring, using the processing circuitry, a third distance between the first central line and a fourth central line of the upper pattern using the electron microscope; calculating, using the processing circuitry, an after-cleaning-inspection (ACI) overlay value based on the measured third distance; calculating, using the processing circuitry, a first overlay skew value based on the ADI overlay value and the ACI overlay value; calculating, using the processing circuitry, a second overlay skew value based on the asymmetrical overlay value and the first overlay skew value; and adjusting, using the processing circuitry, a position of the photoresist pattern based on the second overlay skew value.

