RELATED APPLICATIONS

This application is the U.S. National Phase application under 35 U.S.C. § 371 of International Application No. PCT/EP2019/057582, filed on Mar. 26, 2019, which claims the benefit of European Application No. 18164308.1, filed Mar. 27, 2018. These applications are hereby incorporated by reference herein.

FIELD OF THE INVENTION

This invention relates to the field of signal processing, and more specifically to the field of signal processing across multiple, spatially separated stages within an ultrasound system.

BACKGROUND OF THE INVENTION

In the construction of an ultrasound probe, high voltage technologies are required to drive the acoustic transducer elements and amplify the received signals. However, these high voltage technologies are not suitable for the implementation of more complex functions, such as analog-to-digital conversion (ADC) and digital signal processing (DSP), simply due to the large feature size of the transistors in these technology nodes, which leads to prohibitively high area, and power, consumption and low speed. This issue drives system choices toward the high voltage integrated circuit containing a minimal functionality that is sufficient to transport the signal to a separate low voltage integrated circuit capable of performing the required signal processing in order to generate an ultrasound image. A low voltage integrated circuit implies small feature size transistors that can have state-of-art capabilities in terms of speed and power consumption, whilst maintaining their small size.

Typically, the high voltage integrated circuit is located within the ultrasonic probe itself, whereas, the low voltage integrated circuit is located in within a back end processing unit connected to the probe via a cable. Thus, the analog signals received by the high voltage integrated circuit must be propagated between the high and low voltage integrated circuits. Analog signal propagation is inherently difficult as the signal integrity must be maintained in order to properly interpret it at the receiving end. This is further complicated by the variable propagation distance along the cable, signal dissipation within the interconnecting cable lines and the presence of multiple interfering signals. In addition, new and emerging applications typically require an increasing number of ultrasound transducers in a 2D configuration, which in turn leads to an increase in the amount of acquired data channels that have to be propagated to the back end processing system.

Further, the limitations of analog beamforming, which is typically used at the front-end to reduce the amount of data that is transported in an analog way to the backend, must be considered. Analog beamforming introduces limitations on the achievable performance in terms of maximum dynamic range, spatial resolution and maximum frame-rate.

Finally all the data has to be transported in a robust way to the beam-former. For many non-multiplexed channels, this can be a difficult and costly process due to the many parallel cables required. Due to the high number of channels in an acoustic probe, it is beneficial to multiplex as many channels as possible on a single line; however, there are many difficulties associated with the multiplexing of multiple analogue signals.

There is therefore a need to provide a robust means of propagating the analog signals from one integrated circuit to another without requiring significant additional hardware.

SUMMARY OF THE INVENTION

The invention is defined by the claims.

According to examples in accordance with an aspect of the invention, there is provided a signal processing system, for transferring analog signals from a probe to a remote processing unit, comprising:

a first ASIC at the probe, adapted to receive an analog probe signal, wherein the first ASIC comprises:an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to:receive the analog probe signal; andoutput a binary bit-stream;

a second ASIC at the remote processing unit, adapted to receive the binary bit-stream.

The probe, for example an ultrasound probe, is adapted to receive an analog signal. The probe forms part of a signal processing system, the other part of which is the remote processing unit, which is typically separated from the probe by some variable distance. In some applications, the remote processing unit may be located within the same housing as the probe and may even occupy the same printed circuit board (PCB); whereas, in other applications, the remote processing unit may be separated from the probe by several meters of cable.

Maintaining the integrity of the analog signal is central to reliably interpreting the signals received by the probe using the remote processing unit. Accurate interpretation is particularly important for medical applications such as ultrasound. It is typically difficult to maintain signal integrity when propagating analog signals, particularly where those analog signals are weak, or where multiple analog signals are being propagated in parallel and are subject to interference. Further, it is costly to propagate analog signals over a substantial distance as this requires impedance matching, which in turn will be dependent on the type and length of the cable.

By performing asynchronous sigma-delta modulation on the analog signals, an analog signal is transformed into a digital time-domain signal, in which amplitude information is encoded in the time domain, thereby allowing the signal to be propagated to the remote processing unit with greater robustness and with less susceptibility to interference. In addition, it is possible to implement a massively parallel read-out of all individual transducers in a robust manner; whereas, the alternative of performing analog read-out and digitization in the first ASIC is far more difficult to realize.

According to examples in accordance with an aspect of the invention, there is provided a signal processing system (100), for transferring analog signals from a probe to a remote processing unit, comprising:

a first ASIC at the probe, adapted to receive an analog probe signal acquired from an imaging depth within a subject, wherein the first ASIC comprises:an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to:receive the analog probe signal; andoutput a binary bit-stream;

a second ASIC at the remote processing unit, adapted to receive the binary bit-stream, and wherein:

the asynchronous sigma-delta modulator comprises:a time gain function circuit adapted to alter a time gain function of the asynchronous sigma-delta modulator based on the imaging depth, wherein the time gain function is adapted to:control a feedback gain of the asynchronous sigma-delta modulator, thereby controlling a dynamic range of the asynchronous sigma-delta modulator.

Asynchronous sigma-delta modulators are typically capable of being programed to accommodate a large dynamic range of incoming signals. However, due to the nature of ultrasound signals, where longer signal acquisition windows lead to smaller signal amplitudes, it is often not possible to cover all of the incoming signal amplitudes with a fixed dynamic range.

By providing a time gain function circuit, having an adjustable time gain function, within a feedback loop of the asynchronous sigma-delta modulator, it is possible to control the dynamic range of the asynchronous sigma-delta modulator such that the instantaneous (at each control setting) dynamic range is adjusted for the amplitude of the expected incoming signal. Thus, the dynamic range of the asynchronous sigma-delta modulator may be adjusted over time by way of the time gain function circuit. Typically, the adjustment is performed over time due to the relationship with time and a given scan depth. However, the adjustment may also be done by the user, for example in a non-time synchronized way in order to optimize the current dynamic range to a desired viewing property such as lowering the detectable signal levels for imaging smaller depths.

In an embodiment, the signal processing system further comprises a data channel adapted to propagate the binary bit-stream from the first ASIC to the second ASIC.

The data channel may propagate the binary bit-stream across variable distances depending on the application. For example, in a typical ultrasound system, the remote processing unit may be located on the same PCB as the probe, meaning that the data channel would cover only a short distance. Alternatively, in the case of an ultrasound catheter, the data channel may be adapted to propagate the binary bit-stream across several meters in order to reach the remote processing unit.

In some embodiments, the first ASIC operates at a voltage greater than or equal to 1.8V, for example 2.5V, and wherein the second ASIC operates a voltage less than or equal to 1.8V, for example 1.1V.

In this way, it is possible to house components with a higher voltage requirement on the first ASIC and those with a lower voltage requirement on the second, thereby eliminating the need to sacrifice the efficiency of the various components by operating them all at the same voltage. In addition, this division between the first and second ASICs provides the capability for driving and biasing the ultrasound transducers with the high voltages, for example 75V, required for their operation.

In an arrangement, the asynchronous sigma-delta modulator comprises a low noise amplifier.

In this way it is possible to amplify low amplitude signals, such as deep ultrasound reflection signals acquired towards the end of the acquisition window, without significantly degrading the signal-to-noise ratio. By integrating the low noise amplifier into the asynchronous sigma-delta modulator it is possible to reduce the complexity and implementation cost of the signal processing system.

In a further arrangement, the asynchronous sigma-delta modulator further comprises a feedback capacitor connected with:an output of the low noise amplifier; andan input of the low noise amplifier.

Thus, the LNA may be configured as a charge, or current, integrator by way of the feedback capacitor. The feedback signal may be added at the LNA input in either current or charge form depending on the virtual ground provided by the LNA at that input node.

In an embodiment, the asynchronous sigma-delta modulator further comprises a low-pass filter.

In various embodiments, the asynchronous sigma-delta modulator further comprises an asynchronous binary quantizer.

In an arrangement, the asynchronous sigma-delta modulator comprises a feedback digital-to-analog converter.

In this way, through the characteristics of the low-pass filter and the hysteresis of the asynchronous quantizer, it is possible to control the phase shift of the signals within the asynchronous sigma-delta modulator loop such that the self-oscillations reach a frequency of greater than or equal to 10 times the Nyquist frequency of the input signal band, thereby reducing the number of spurious signals entering the signal band due to high amplitude input signals.

In some arrangements, the first ASIC further comprises an acoustic transducer element, wherein the acoustic transducer element is adapted to receive an incoming acoustic signal and output the acoustic signal. Alternatively, the acoustic transducer is a separate transducer element, such as a piezoelectric transducer, that is electrically connected to the first ASIC.

In an embodiment, the second ASIC comprises a demodulator.

In this way, the second ASIC may extract information, such as an amplitude of the acoustic signal received by the first ASIC, based on the binary bit-stream generated by the asynchronous sigma-delta modulator.

In a further embodiment, the demodulator is adapted to:receive the binary bit stream; andoutput a reconstructed analog signal; and

the second ASIC further comprises an analog-to-digital converter adapted to receive the reconstructed analog signal.

In various embodiments:

the probe is an ultrasonic probe; and

the remote processing unit is a back-end signal processing unit.

In this way, it is possible to reliably transfer the acoustic ultrasound signals received by the probe to the remote processing unit by transforming the signals into a binary bit-stream. This transfer may occur over various distances depending on the application. For example, in a conventional ultrasound system the probe and remote processing unit may be located within the same probe housing; whereas, in an ultrasound catheter the probe and remote processing unit may be separated by several meters of cable.

According to examples in accordance with an aspect of the invention, there is provided a method for transferring analog signals from a probe to a remote processing unit, the method comprising:

receiving an analog signal at a first ASIC at the probe;

performing asynchronous sigma-delta modulation on the analog signal, thereby generating a binary bit-stream; and

receiving the binary bit-stream from the data channel at the second ASIC at the remote processing unit.

According to examples in accordance with an aspect of the invention, there is provided a method for transferring analog signals from a probe to a remote processing unit, the method comprising:

receiving an analog signal from an imaging depth within a subject at a first ASIC at the probe;

performing asynchronous sigma-delta modulation on the analog signal, by way of an asynchronous sigma-delta modulator, thereby generating a binary bit-stream; and

receiving the binary bit-stream from the data channel at the second ASIC at the remote processing unit, and wherein:

performing asynchronous sigma-delta modulation on the analog signal comprises:altering a time gain function of the asynchronous sigma-delta modulator based on the imaging depth, wherein the time gain function is adapted to:control a feedback gain of the asynchronous sigma-delta modulator, thereby controlling a dynamic range of the asynchronous sigma-delta modulator.

In an embodiment, the analog signal comprises an ultrasound signal.

According to examples in accordance with an aspect of the invention, there is provided a computer program comprising computer program code means which is adapted, when said computer program is run on a computer, to implement the method described above.

According to examples in accordance with an aspect of the invention, there is provided an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator comprises:

a time gain function circuit adapted to alter a time gain function of the asynchronous sigma-delta modulator, wherein the time gain function is adapted to:control a feedback gain of the asynchronous sigma-delta modulator, thereby controlling a dynamic range of the asynchronous sigma-delta modulator.

In an embodiment, the time gain function circuit comprises a digital-to-analog converter having a switched current array, the switched current array comprising:

a plurality of current sources, wherein each current source provides a different current;

a plurality of switches, wherein each switch is connected to a current source and wherein:when the switch is in a closed position, the associated current source is activated; andwhen the switch is in an open position, the associated current source is deactivated; and

a control interface, adapted to control the position of the plurality of switches.

The feedback signal of an ASDM is typically implemented as a current controlled by the binary states of the output or by a source of electrical charge (e.g. a capacitor), discharged by the integration capacitor in the LNA feedback, while the discharge process is again controlled by the output binary state.

In this way, the time gain function may be controlled by the number of switches in each position. By implementing the current sources such that each current is different, it is possible to achieve a wide variety of dynamic ranges of the asynchronous sigma-delta modulator through the time gain function.

In a further embodiment, the control interface comprises a user interface adapted to receive a user input.

In a yet further embodiment, the user input comprises a designation for the positions of each of the plurality of switches.

In another, or further, embodiment, the user input comprises a desired dynamic range of the asynchronous sigma-delta modulator.

In this way, a user may be able to manually alter the dynamic range of the asynchronous sigma-delta modulator. This may occur directly, for example selecting which switches of the switched current array should be open or closed, or it may occur through an indirect selection of a user, for example selecting a desired function that in turn leads to the altering of the switch positions of the switched current array.

In an arrangement, the plurality of current sources each comprises a switched capacitor.

According to examples in accordance with an aspect of the invention, there is provided a system for controlling the dynamic range of an asynchronous sigma-delta modulator, the system comprising:

an asynchronous sigma-delta modulator as claimed in any preceding claim; and

an amplitude detector adapted to provide a control signal to the asynchronous sigma-delta modulator, wherein the control signal is adapted to alter the time gain function of the time gain function circuit.

In an embodiment, the asynchronous sigma-delta modulator comprises a controller adapted to automatically alter the time gain function of the time gain function circuit based on the control signal.

In this way, it is possible to fully automate the altering of the time gain function, and so the dynamic range, of the asynchronous sigma-delta modulator.

In an arrangement, the amplitude detector comprises a counter.

In an embodiment, the amplitude detector is adapted to receive an output of the asynchronous sigma-delta modulator.

In a further embodiment, the control signal is based on an amplitude of the output of the asynchronous sigma-delta modulator.

By detecting the amplitude of the output of the asynchronous sigma-delta modulator directly, it is possible to more accurately automate the adjusting of the dynamic range of the asynchronous sigma-delta modulator in response the incoming signals, thereby increasing the accuracy of the output signal. In addition, the asynchronous sigma-delta modulator feedback loop may also prevent overload from large input signals, or may be used in combination with gain boosting in order to enable the reception of small signals from a greater depth.

Alternatively, the amplitude detection may be performed on the signal before passing to the quantizer in the asynchronous sigma-delta modulator loop as the signal amplitude at this point will be proportional to the amplitude of the input signal.

In some embodiments, the system further comprises a low-pass filter connected in series with the asynchronous sigma-delta modulator and the amplitude detector.

In various arrangements, the system further comprises an ultrasonic transducer.

According to examples in accordance with an aspect of the invention, there is provided a method for controlling the dynamic range of an asynchronous sigma-delta modulator, the method comprising:

obtaining an analog signal;

performing asynchronous sigma-delta modulation on the analog signal, thereby generating a binary bit-stream;

altering a time gain function of a time gain function circuit within the asynchronous sigma-delta modulator based on a signal of the asynchronous sigma-delta modulator;

controlling a feedback gain of the asynchronous sigma-delta modulator based on the time gain function, thereby controlling the dynamic range of the asynchronous sigma-delta modulator.

In an embodiment, the controlling of the time gain function of the time gain function circuit comprises:

performing amplitude detection on the binary bit-stream, thereby generating output amplitude data;

generating a control signal based on the output amplitude data; and

altering the time gain function of the time gain function circuit based on the control signal.

According to examples in accordance with an aspect of the invention, there is provided a system for performing analog-to-digital conversion, the system comprising:

a probe having a first ASIC, wherein the first ASIC is adapted to:receive an analog signal; andoutput a binary bit-stream comprising asynchronous time-domain pulses;

a processing unit having a second ASIC, wherein the second ASIC comprises a time-to-digital converter adapted to:receive the binary bit-stream; andgenerate a digital output from the binary bit-stream based on time-to-digital conversion; and

a data channel adapted to propagate the binary bit-stream from the first ASIC to the second ASIC, wherein the first and second ASICs are spatially separated.

The probe, for example an ultrasound probe, is adapted to receive an analog signal. The probe forms part of a signal processing system, the other part of which is the processing unit, which is typically separated from the probe by some variable distance. In some applications, the remote processing unit may be located within the same housing as the probe and may even occupy the same PCB; whereas, in other applications, the remote processing unit may be separated from the probe by several meters of cable.

Maintaining the integrity of the analog signal is central to reliably interpreting the signals received by the probe using the processing unit. This is particularly important in cases of medical applications such as ultrasound. It is typically difficult to maintain signal integrity when propagating analog signals, particularly where those analog signals are weak, or where multiple analog signals are being propagated in parallel and are subject to interference. Further, it is costly to propagate analog signals over a substantial distance as this requires impedance matching, which in turn will be dependent on the type and length of the cable.

By processing the analog signals in order to generate digital time-domain signals, in which amplitude information may be encoded, it is possible for the signal to be propagated to the remote processing unit with greater robustness and with less susceptibility to interference. The digital time-domain signals may then be interpreted by the remote processing unit, using time-to-digital conversion, in order to generate digital data for interpreting the original analog signals, without the difficulty of analog signal propagation. By employing time-to-digital conversion at the remote processing unit to perform the decoding, it is possible to directly digitize the time-domain signals.

In an embodiment, the time-to-digital converter comprises a pipeline time-to-digital converter, the pipeline time-to-digital converter comprising:

a coarse time-to-digital converter, wherein the coarse time-to-digital converter is adapted to:receive the binary bit-stream; andoutput:a coarse digital output; anda coarse residue time; and

a fine time-to-digital converter block, adapted to receive the coarse residue time, wherein the fine time-to-digital converter block comprises:one or more fine time-to-digital converters connected in series, each adapted to:receive an incoming residue time from the previous fine, or coarse, time-to-digital converter in the series;output an outgoing residue time to the subsequent fine time-to-digital converter in the series; andoutput a fine digital output.

In an embodiment, the first ASIC comprises an asynchronous sigma-delta modulator.

In this way, it is possible to convert the analog signals into the binary bit stream without the need for a clock signal, thereby reducing the number of components required to transform the analog signals into digital time-domain signals.

In some embodiments, the asynchronous sigma-delta modulator comprises a low noise amplifier.

In this way it is possible to amplify low amplitude signals, such as deep ultrasound reflection signals acquired towards the end of the acquisition window, without significantly degrading the signal-to-noise ratio.

In an arrangement, the asynchronous sigma-delta modulator comprises a low-pass filter.

In various arrangements, the asynchronous sigma-delta modulator comprises an asynchronous quantizer.

In an embodiment, the asynchronous sigma-delta modulator comprises a digital-to-analog converter.

In this way, it is possible to control the phase shift of the signals within the asynchronous sigma-delta modulator loop such that the self-oscillations reach a frequency of greater than or equal to 10 times the Nyquist frequency of the input signal band, thereby reducing the number of spurious signals entering the signal band due to high amplitude input signals.

In an embodiment, the first ASIC operates at a voltage greater than or equal to 1.8V, for example 2.5V.

In an arrangement, the second ASIC operates a voltage less than or equal to 1.8V, for example 1.1V.

In this way, it is possible to house components with a higher voltage requirement on the first ASIC and those with a lower voltage requirement on the second, thereby eliminating the need to sacrifice the efficiency of the various components by operating them all at the same voltage.

In an embodiment, the data channel comprises a single line propagation channel.

According to examples in accordance with an aspect of the invention, there is provided a method for performing analog-to-digital conversion on analog signals across a probe and a remote processing unit, the method comprising:

obtaining an analog signal at a first ASIC at the probe;

processing the analog signal using the first ASIC, thereby generating a binary bit-stream based on the analog signal, wherein the binary bit-stream comprises asynchronous time-domain pulses;

propagating the binary bit-stream from the first ASIC to a second ASIC at the processing unit, wherein the second ASIC is spatially separated from the first;

performing time-to-digital conversion on the binary bit-stream by way of a time-to-digital converter housed on using the second ASIC, thereby generating a digital output.

In an embodiment, the processing of the analog signal using a first ASIC comprises performing asynchronous sigma-delta modulation on the analog signal.

In some embodiments, the propagating of the binary bit-stream from the first ASIC to the second ASIC comprises performing single line propagation.

In an arrangement, the analog signal comprises an ultrasound signal.

According to examples in accordance with an aspect of the invention, there is provided a computer program comprising computer program code means which is adapted, when said computer program is run on a computer, to implement the method described above.

According to examples in accordance with an aspect of the invention, there is provided a method for multiplexing a plurality of analog signals each from a separate channel, the method comprising:

obtaining the plurality of analog signals each analog signal being obtained from a separate channel, wherein each separate channel is associated with a channel identifier;

performing asynchronous sigma-delta modulation on each of the plurality of analog signals, thereby generating a plurality of quantized time domain signals based on the plurality of analog signals, wherein each quantized time domain signal comprises one or more edge timing events, an edge timing event relating to a signal edge within the quantized time domain signal; and

multiplexing, in an asynchronous manner, the plurality of quantized time domain signals based on the one or more edge timing events of each signal and the channel identifier, thereby generating a multiplexed signal in which edge timing events are associated with channel identifiers.

The propagation of many signals in parallel can be difficult and costly; however, the multiplexing of multiple analog signals is extremely difficult to achieve.

Thus, by processing the analog signals in order to generate digital time-domain signals, it is possible to multiplex the multiple signals with greater ease. Performing this processing in an asynchronous manner allows for the multiplexing to be performed without the need for a clock. In addition, the inclusion of channel identifiers with the edge timing events allows the multiplexed signal to be separated according to channel after propagation, allowing the multiplexed signal to be interpreted by a back end processing system.

By performing asynchronous sigma-delta modulation, each of the plurality of analog signals is transformed into a binary bit-stream in the time domain. By performing the sigma-delta modulation in an asynchronous manner, the need for a clock signal is removed, thereby reducing the number of components required to perform the multiplexing operation and the power dissipation of the circuit itself.

In an embodiment, the multiplexing of the plurality of quantized time domain signals comprises:

for each quantized time domain signal:identifying an edge timing event; andlabelling the edge timing event with a channel identifier based on the channel from which the associated analog signal was obtained; and

generating a multiplexed signal based on the plurality of quantized time domain signal, wherein the multiplexed signal includes the labelled edge timing events.

By labelling each edge timing event with a channel identifier, it is possible to extract the information from the multiplexed signal on a per channel basis. In this way, the multiplexed signal may carry both timing and channel signal data.

In some embodiments, the edge timing event comprises a rising signal edge.

In an arrangement, the edge timing event comprises a falling signal edge.

By identifying the rising and falling edges of the signals as an edge timing event, it is possible to convey a greater depth of information within the multiplexed signal, thereby allowing the multiplexed signal to be decoded at a later stage.

In an embodiment, the method further comprises decoding the multiplexed signal.

In a further embodiment, decoding the multiplexed signal comprises performing time-to-digital conversion on the multiplexed signal.

The decoding of the multiplexed signal allows for the multiplexed signal to be interpreted, for example, after being propagated to a separate processing location. In this way, it is possible to combine information from a plurality of different signal sources into a single signal, transmit said signal in a simple and robust manner and interpret it at a separate location.

In another embodiment, the decoding comprises timestamping each edge timing event of the multiplexed signal.

In yet another embodiment, the decoding comprises recording a time between receiving each edge timing event of the multiplexed signal.

By timestamping, and/or measuring the time between receiving, each edge timing event it is possible to determine the relative timings of each event. In this way, and taking into account the channel identifiers of each of the edge timing events, it is possible to more accurately interpret the original analog signals from the multiplexed signal.

In an arrangement, the decoding comprises reconstructing the plurality of analog signals in the digital domain.

According to examples in accordance with an aspect of the invention, there is provided a computer program comprising computer program code means which is adapted, when said computer program is run on a computer, to implement the method described above.

According to examples in accordance with an aspect of the invention, there is provided a system for multiplexing a plurality of analog signals, the system comprising:

an analog signal receiver comprising a plurality of channel each adapted to obtain an analog signal, and wherein each channel is associated with a channel identifier;

a signal processor comprising an asynchronous sigma-delta modulator and adapted to perform asynchronous sigma-delta modulation on each of the plurality of analog signals, thereby generating a plurality of quantized time domain signals based on the plurality of analog signals, wherein each quantized time domain signal comprises one or more edge timing events, an edge timing event relating to a signal edge within the quantized time domain signal; and a multiplexer adapted to multiplex, in an asynchronous manner, the plurality of time domain signals based on the one or more edge timing events of each signal and the channel identifier, thereby generating a multiplexed signal in which edge timing events are associated with channel identifiers.

In an embodiment, the analog signal receiver comprises an ultrasonic transducer.

In an arrangement, the system further comprises a time-to-digital converter.

According to examples in accordance with an aspect of the invention, there is provided a pipeline time-to-digital converter, the pipeline time-to-digital converter comprising:

a coarse time-to-digital converter, wherein the coarse time-to-digital converter is adapted to:receive an incoming signal; andoutput:a coarse digital output; anda coarse residue time; and

a fine time-to-digital converter block, adapted to receive the coarse residue time, wherein the fine time-to-digital converter block comprises:one or more fine time-to-digital converters connected in series, each adapted to:receive an incoming residue time from the previous fine, or coarse, time-to-digital converter in the series;output an outgoing residue time to the subsequent fine time-to-digital converter in the series; andoutput a fine digital output.

Typically, in time-to-digital converter designs, there exists a trade-off between resolution and dead time (the time between the end of a measurement and the commencement of a new one). It is possible to maximize both parameters; however, this comes at the cost of excessive power consumption, which, in systems such as an ultrasound system, is not feasible.

The coarse time-to-digital converter operates at a low frequency in order to maintain a low power consumption. The error in the measurement performed by the coarse time-to-digital converter then needs to be determined in order to achieve a high resolution. This error, referred to as time residue, is measured by the subsequent fine time-to-digital converter, which in turn produces an error that is measured by a further fine time-to-digital converter, and so on until the desired resolution is reached.

In addition, while the block of fine time-to-digital converters are processing the residue time of the initial coarse time-to-digital converter, the latter may begin another time measurement, thereby reducing the dead-time of the whole system.

In an embodiment, the coarse time-to-digital converter comprises a ring oscillator.

In a further embodiment, the ring oscillator comprises a plurality of inverters. In another, or further, embodiment the ring oscillator comprises a plurality of delay cells.

By employing a ring oscillator within the coarse time-to-digital converter, it is possible for the time-to-digital converter to generate its own clock signal, thereby eliminating the need to include a separate external clock for the system. In this way, the complexity and power demand of the coarse time-to-digital converter may be reduced.

The inclusion of delay cells within the ring oscillator may result in a higher resolution of the signal, with a potential time resolution of less than 1 ps, and a reduction in noise.

In an arrangement, the coarse time-to-digital converter comprises a time amplifier.

In a further arrangement, the time amplifier is adapted to generate a pulse train.

In a yet further embodiment, the pulse train amplifier is a D flip-flop pulse train time amplifier.

A time-to-digital converter operates at a given time resolution, accepting an input signal once per given time interval according to its operating resolution. If an input signal, for example a pulse, were to arrive at the input having a width lower than the operating resolution of the time-to-digital converter, the time-to-digital converter would be incapable of measuring the signal.

By including a time amplifier within the time-to-digital converter, it is possible to artificially widen the pulse width of an incoming signal by a given factor, thereby making it possible for the signal to be measured by the time-to-digital converter without requiring a significant increase in the hardware of the time-to-digital converter that would otherwise be required to significantly improve the resolution.

A pulse train amplifier allows for an accurate, linear gain that is simple to program to reach a desired extension in the input time range. It is possible to implement the pulse train amplifier using a D flip-flop architecture.It is possible to reduce the offset introduced to the pulse train generated by the pulse train amplifier, by implementing irregularly distributed delays between successive elements of the (gated) delay line, which forms part of the pulse train amplifier. The allocation ratio of the delays is technology dependent and may be vary across implementations.

In an embodiment, the coarse time-to-digital converter comprises a selector unit.

In a further embodiment, the selector unit comprises a D flip-flop.

In another, or further, embodiment, the selector unit comprises a 1-hot converter.

In yet another, or further, embodiment, the selector unit comprises a binary encoder.

In this way, the selector unit may be implemented in a relatively simple manner and may yield an encoded word representing the delay straight away.

In an arrangement, the series of one or more fine time-to-digital converter each comprises:

a 1.5-bit time-to-digital converter; and

a time amplifier.

The 1.5-bit time-to-digital converter allows for a simple implementation of the fine time-to-digital converter block. The type of time-to-digital converter used to implement the fine time-to-digital converters may vary depending upon the implementation of the pipelined time-to-digital converter.

According to examples in accordance with an aspect of the invention, there is provided a method for performing time-to-digital conversion, the method comprising:

obtaining an incoming signal;

performing a coarse time-to-digital conversion on the incoming signal, thereby generating:a coarse digital output; anda coarse residue time; and

performing a series of one or more fine time-to-digital conversions on an incoming residue time, thereby generating:an outgoing residue time; anda fine digital output;

wherein the incoming residue time comprises:the coarse residue time generated by the coarse time-to-digital converter; orthe outgoing residue time generated by a previous fine pipeline time-to-digital converter in the series of one or more fine time-to-digital converters.

In an embodiment, the incoming signal comprises a series of time domain pulses.

According to examples in accordance with an aspect of the invention, there is provided a computer program comprising computer program code means which is adapted, when said computer program is run on a computer, to implement the method described above.

