The contents of the following Japanese patent applications are incorporated herein by reference:NO. 2019-048290 filed on Mar. 15, 2019, andNO. PCT/JP2020/003773 filed on Jan. 31, 2020.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor device.

2. Related Art

Conventionally, in a semiconductor device including a gate trench and a dummy trench, a configuration for providing a runner for screening of the dummy trench is known (for example, see Patent documents 1 to 3).

PRIOR ART DOCUMENTS

Patent Documents

[Patent document 1] Japanese Patent Application Publication No. 2016-25124

[Patent document 2] Japanese Patent Application Publication No. 2015-207736

[Patent document 3] Japanese Patent Application Publication No. 2014-53552

[Patent document 4] Japanese Patent Application Publication No. 2018-174295

Technical Problem

If the runner for screening is provided in an active portion where a device such as a transistor formed, the area in which the device such as the transistor can be arranged becomes smaller.

General Disclosure

In order to solve the above described problem, one aspect of the present invention provides a semiconductor device including a semiconductor substrate. The semiconductor device may include an emitter electrode including at least two partial electrodes arranged with an interval in a top plan view of the semiconductor substrate. The semiconductor device may include an active-side gate runner and an active-side dummy runner. The active-side gate runner and the active-side dummy runner may be arranged to be sandwiched between two of the partial electrodes. The semiconductor substrate may include a gate trench portion connected to the active-side gate runner and having a longitudinal length in a first direction in the top plan view. The semiconductor substrate may include a dummy trench portion connected to the active-side dummy runner and having a longitudinal length in the first direction. The entirety of one of the active-side gate runner and the active-side dummy runner in the first direction may be covered by the other of the active-side gate runner and the active-side dummy runner.

The entirety of the active-side gate runner in the first direction may be covered by the active-side dummy runner arranged above the active-side gate runner.

The active-side dummy runner may be connected to the dummy trench portion at a portion that does not overlap the active-side gate runner.

The active-side gate runner may be a runner made of a semiconductor material, and the active-side dummy runner may be a runner made of a metal material.

The emitter electrode may have a bridge portion connecting two of the partial electrodes. The active-side dummy runner may be divided into at least two partial runners by the bridge portion. The semiconductor device may include an intersecting dummy runner made of a semiconductor material, which is provided intersecting with the bridge portion and connects two of the partial runners.

The intersecting dummy runner may be connected to the dummy trench portion.

The semiconductor substrate may have a transistor portion in which the gate trench portion and the dummy trench portion are provided and a diode portion in which the dummy trench portion is provided. The intersecting dummy runner may be connected to the dummy trench portion of the diode portion.

The dummy trench portion of the transistor portion may be connected to the active-side dummy runner.

The active-side gate runner may be provided intersecting with the bridge portion.

The semiconductor device may include an interlayer dielectric film. The interlayer dielectric film may be provided between the semiconductor substrate and the emitter electrode. The interlayer dielectric film may have a contact hole connecting the emitter electrode to the semiconductor substrate. The active-side dummy runner may be provided in a range that does not overlap with the contact hole in the top plan view of the semiconductor substrate.

The semiconductor device may include an outer circumferential gate runner. The outer circumferential gate runner may be arranged between the emitter electrode and an edge side of the semiconductor substrate in the top plan view. The outer circumferential gate runner may be connected to the active-side gate runner. The semiconductor device may include an outer circumferential dummy runner. The outer circumferential dummy runner may be arranged between the emitter electrode and the edge side of the semiconductor substrate in the top plan view. The outer circumferential dummy runner may be connected to the active-side dummy runner. The outer circumferential gate runner and the outer circumferential dummy runner may be arranged without overlapping with each other in the top plan view of the semiconductor substrate.

The semiconductor device may include a screening pad connected to the outer circumferential dummy runner.

The summary clause does not necessarily describe all necessary features of the embodiments of the present invention. The present invention may also be a sub-combination of the features described above.

