BACKGROUND

Static Random Access Memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. With the increasing demanding requirement to the speed of integrated circuits, the read speed and write speed of SRAM cells also become more important. With the increasingly down-scaling of the already very small SRAM cells, however, such request is difficult to achieve. For example, the sheet resistance of metal lines, which form the word-lines and bit-lines of SRAM cells, becomes increasingly higher, and hence the RC delay of the lines and bit-lines of SRAM cells is increased, preventing the improvement in the read speed and write speed.

When entering into nanometer era, split-word-line SRAM cells have become increasingly popular due to their lithography-friendly layout shapes of active regions, polysilicon lines, and metal layers, and also due to shorter bit-lines for speed improvement. However, in the nanometer era, SRAM cells are also larger, resulting in two problems. Firstly, each bit-line has to be connected to more rows of SRAM cells, which induces higher bit-line metal coupling capacitance, and hence the differential speed of the differential bit-lines (bit-line and bit-line-bar) is reduced. Secondly, each word-line also has to be connected to more columns of SRAM cells, resulting in longer word-lines and hence worsened resistance.

