BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to non-volatile NOR-type memory strings. In particular, the present invention relates to an architecture for the 3-dimensional memory array.

2. Discussion of the Related Art

In high density three-dimensional memory structures, such as those disclosed in the Non-provisional Application, it is desirable to keep memory cells separated from each other by at least a certain distance in order to avoid the effects of fringing fields resulting from charge in one memory cell from interfering with the charge storage in the other memory cell, while maintaining the desirable high density. In the prior art, such as illustrated byFIGS. 1aand 1b, a NOR-type memory array includes memory cells1and2which share a single bit line108. As shown inFIG. 1a, cells1and2are provided charge storage layers107and gate electrodes109(“local word lines”) on opposite sides of shared bit line108directly across from each other. The charge storage layers107of memory cells1and2are separated by less than the width of their shared bit line108. However, with decreasing feature sizes, memory cells1and2are in close enough proximity that each memory cell may disturb the other memory cell during program, erase, or read operations.

FIG. 1bshows a completed memory structure100having word lines that are aligned in the manner illustrated inFIG. 1a. As shown inFIG. 1b, three-dimensional memory structure100includes a regular array of memory cells, each illustrated by memory cell120. (Memory cell120shows in three dimensions each of cells1and2.) InFIG. 1b, memory cell120includes channel region112, which is provided between source region110, drain region or bit line108. In addition, memory cell120includes (i) charge-trapping material107provided between word line109and channel region112, and (ii) conductor layer113, provided adjacent and in contact with drain region or bit line108, for reducing resistivity in drain region or bit line108. The memory cells in each column of memory structure100are isolated from each other by dielectric layer114.

FIG. 1creproducesFIG. 9bof U.S. Patent Application Publication 2016/0086970 to Peng, in which word lines formed above a memory structure (“global word lines”) are provided in a staggered fashion to adjacent bit lines (i.e., the staggered local word lines serve different bit lines), but not relative to a single shared bit line. In other words, adjacent global word lines Such an arrangement does not decrease the distance between the nearest memory cells. These approaches also sacrifice memory array density.

SUMMARY

The present invention avoids the potential for disturbs between memory cells in close proximity without sacrificing memory cell density. According to one embodiment of the present invention, a staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. The memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.

The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings.

