TECHNICAL FIELD

The present invention relates generally to the field of voltage regulation in high-speed memory interface systems. More specifically, the present invention relates generally to reduction of power supply induced jitter in a high-speed memory interface system.

BACKGROUND

Emerging technologies like artificial intelligence, machine learning, and high-speed graphics need a high-speed memory interface to communicate with high bandwidth memory, such as dynamic random access memory (DRAM), for use in graphics cards, game consoles, and high-performance computing, such as graphics double data rate type six synchronous dynamic random access memory (GDDR6 DRAM), which has an operating speed of 24 Gbps. In a system-on-a-chip (SOC) interfacing with a GDDR6 DRAM, a write mode allows the SOC to transmit parallel data and an SOC clock to the DRAM, and the DRAM samples the parallel data signals using the SOC clock to obtain a set of data samples to be stored in the DRAM. In a read mode, the DRAM transmits parallel data back to the SOC, and the SOC reuses the SOC clock to sample the parallel data transmitted from the DRAM. In such a device, the DRAM may also transmit an Error Detection Code (EDC) signal, which the SOC uses to align the SOC clock with the parallel data received from the DRAM. The system may include a Phase Lock Loop (PLL) used to generate the clock for the system connected to a same power supply as the SOC and GDDR6 DRAM.

In some high-performance memory systems, like GDDR6, there can be accumulation jitter in the PLL due to a delay of up to 2.5 ns between the clock edge at which the DRAM transmits parallel data to the SOC and the clock edge at which SOC actually receives the sampled DRAM data. The accumulation jitter includes random noise dominated by device-induced noise and deterministic noise dominated by noise on the power supply. The deterministic noise may also include high levels of Simultaneous Switching Noise (SSN) on the power supply caused by the use of a parallel interface DRAM system (e.g., such as GDDR6), and dominates the accumulation jitter. The accumulation jitter results in a reduction of the clock read trimming margin for the SOC receiver, increasing the likelihood of a failed read operation in such high-speed systems.

To operate at full capacity, GDDR6 systems require minimization of the deterministic noise of the accumulation jitter, such as reducing power supply induced jitter (PSIJ) in the PLL, so that the PLL generates a clock with minimal delay. One conventional method of improving PSIJ includes providing the PLL with a dedicated power supply, however, the package coupling and inside chip coupling between supplies can cause the actual power supply reaching the PLL to be very noisy. Additional methods include using an on-chip regulator with high Power Supply Rejection (PSR) to filter out power supply noise before it reaches the PLL. Two such conventional on-chip regulators known in the art involve types of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) drivers: an N-type MOSFET (NMOS) power driver-based, on-chip regulator architecture100a, shown inFIG. 1A; and a P-type MOSFET (PMOS) power driver-based, on-chip regulator architecture100b, shown inFIG. 1B.

The conventional NMOS power driver-based regulator100a, shown inFIG. 1A, includes a comparator102aand an NMOS power driver104awhich provides the regulator output to a PLL106aand to an input of the comparator as negative feedback. This architecture offers the benefits of low output impedance, improved load current regulation, and good PSR. However, in such an architecture, the power supply voltage VDDQ is required to be greater than the sum of the regulated output voltage VREG and the NMOS power driver104athreshold voltage (Vth). In a GDDR6 system during a 5 nm T7G process, the power supply voltage VDDQ of GDDR6 can be as low as 1.21V, the regulated output voltage VREG can be as high as 0.88V, and the Vth can be as high as 0.5V; the power supply voltage VDDQ is insufficient to power the GDDR6 process, as 0.88V+0.5V=1.38V, which is greater than the low end of power supply voltage VDDQ at 1.21V. Thus, the NMOS power driver-based regulator100acannot be used for GDDR6 applications because of the architectures power supply requirements.

The conventional PMOS power driver-based regulator100b, depicted in background artFIG. 1B, includes a comparator102band a PMOS power driver104b. Similar to the NMOS power driver based solution, the PMOS power driver based solution provides the regulator output to both a PLL106band an input of the comparator as negative feedback. Unlike the NMOS-based architecture100adescribed with reference toFIG. 1A, the PMOS power driver-based regulator architecture100bdoes not suffer from the same power supply limitations and can operate for the power supply voltage VDDQ power supply less than regulated output voltage VREG plus PMOS power driver104bthreshold voltage (Vth). The PMOS architecture also provides good PSR for low frequency power supply noise. However, the PSR of this regulator architecture is limited by the bandwidth of the comparator102b. GDDR6 requires 200 MHz-300 MHz of bandwidth. Increasing the bandwidth of comparator102bcan compromise the stability of the negative feedback loop, resulting in limited bandwidth and poor PSR for high frequency power supply noise. Thus, the PMOS power driver-based regulator100bcannot be used for GDDR6 applications because the bandwidth limitations cannot effectively filter the high frequency power supply noise.

SUMMARY

Disclosed herein are systems and methods for voltage regulation designed to address the above-noted shortcomings of conventional voltage regulation of power supply input above-noted shortcomings of conventional voltage regulation of power supply input to a PLL for clock generation in high-speed memory systems, and may provide additional or alternative benefits as well. There is a desire for new methods and/or hardware components that provide good PSR to minimize PSIJ on the power supply of the PLL to enable the PLL to generate a clock with minimal accumulated deterministic jitter. The embodiments described herein provide for a voltage regulator architecture with high PSR capable of reducing the PSIJ of the PLL power supply across a large bandwidth of frequencies. The embodiments described herein further provide for a voltage regulator architecture capable of meeting the deterministic jitter target for maintaining the timing budget for a 24 Gbps GDDR6 PLL interface.

In an embodiment, a voltage regulator circuit comprises a first feedback circuit loop configured to receive a reference voltage and a voltage regulator output; detect a low frequency noise from a regulator power supply on the voltage regulator output using the reference voltage and the voltage regulator output; and apply the low frequency noise as a low frequency negative feedback to the voltage regulator output, thereby reducing the low frequency noise on the voltage regulator output. The circuit further comprises a second feedback circuit loop having a comparatively higher bandwidth than the first feedback circuit loop, and configured to: increase bandwidth of the voltage regulator circuit, and reduce a high frequency noise from the regulator power supply. The circuit further comprises a third feedback circuit loop configured to: detect a very high frequency noise from the regulator power supply on the voltage regulator output; apply the very high frequency noise as a very high frequency negative feedback to the voltage regulator output, thereby reducing the very high frequency noise on the voltage regulator output; and output a regulated output equal to the reference voltage and immune to the low frequency noise, the high frequency noise, and the very high frequency noise from the regulator power supply.

In another embodiment, a method for voltage regulation in a regulator circuit, the method comprising receiving, by a first feedback circuit loop, a reference voltage and a voltage regulator output; detecting, by the first feedback circuit loop, a low frequency noise from a regulator power supply on the voltage regulator output using the reference voltage and the voltage regulator output; applying, by the first feedback circuit loop, the low frequency noise as negative feedback to the voltage regulator output, thereby reducing the low frequency noise on the voltage regulator output; increasing, by a second feedback circuit loop, bandwidth of the circuit, the second feedback circuit loop having a comparatively higher bandwidth than the first feedback circuit loop, reducing, by the second feedback circuit loop, high frequency noise on the voltage regulator output; detecting, by a third feedback circuit loop, very high frequency noise from the regulator power supply on the voltage regulator output; applying, by the third feedback circuit loop, the very high frequency noise as negative feedback to the voltage regulator output, thereby reducing the very high frequency noise on the voltage regulator output; and outputting, by the third feedback circuit loop, a regulated output equal to the reference voltage and immune to the low frequency noise, the high frequency noise, and the very high frequency noise from the regulator power supply.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

