CROSS-REFERENCE TO RELATED APPLICATION

This U.S. nonprovisional patent application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2019-0090366, filed on Jul. 25, 2019 in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

BACKGROUND

1. Technical Field

The present disclosure relates to a semiconductor device. More particularly, the present disclosure relates to a semiconductor device including a field effect transistor.

2. Description of the Related Art

A semiconductor device includes an integrated circuit consisting of metal oxide semiconductor field effect transistors (MOSFETs). As the semiconductor device becomes highly integrated, the scale down of the MOSFETs is also being accelerated, and thus operating characteristics of the semiconductor device may deteriorate. Therefore, various efforts including studies have been made with a goal of manufacturing the semiconductor device having superior performances while overcoming limitations due to high integration of the semiconductor device.

SUMMARY

Some example embodiments of the inventive concepts described herein provide a semiconductor device including highly-integrated field effect transistors.

Objects of the inventive concepts described herein are not limited to those mentioned above, and other objects which have not been mentioned above will be clearly understood to those skilled in the art from the following description.

According to some example embodiments of the present disclosure, a semiconductor device may include a substrate, a device isolation layer, a gate structure, a first active contact pattern, a second active contact pattern, and a connection pattern. The substrate includes a first active region and a second active region. The device isolation layer is between the first active region and the second active region. The gate structure extends in a first direction and runs across the first active region and the second active region. The first active contact pattern is on the first active region on one side of the gate structure. The second active contact pattern is on the second active region on another side of the gate structure. The connection pattern is on the device isolation layer and connects the first active contact pattern and the second active contact pattern to each other. The connection pattern extends in a second direction and runs across the gate structure. Portions of the first active contact pattern and the second active contact pattern may extend in the first direction and may overlap the device isolation layer.

According to some example embodiments of the present disclosure, a semiconductor device may include a substrate, multiple first active patterns, multiple second active patterns, a gate structure, a first active contact pattern, a second active contact pattern, a third active contact pattern, a fourth active contact pattern, and a connection pattern. The substrate includes a first active region and a second active region. The first active patterns are on the first active region and extend in a first direction. The second active patterns are on the second active region and extend in the first direction. The gate structure runs across the first active patterns and the second active patterns and extends in a second direction intersecting the first direction. The first active contact pattern is on the first active patterns on one side of the gate structure. The first active contact pattern has a first length in the second direction. The second active contact pattern is on the first active patterns on another side of the gate structure. The second active contact pattern has a second length in the second direction. The second length is greater than the first length. The third active contact pattern is on the second active patterns on one side of the gate structure. The third active pattern has the second length. The fourth active contact pattern is on the second active patterns on another side of the gate structure. The fourth active contact pattern has the first length. The connection pattern extends in the first direction and runs across the gate structure between the first active region and the second active region. The connection pattern connects the second active contact pattern to the third active contact pattern.

Details of other example embodiments are included in the description and drawings.

