TECHNICAL FIELD

The present invention relates to semiconductor memories, and in particular, to an output circuit and a chip.

BACKGROUND

In both LPDDR4 (Low Power Double Data Rate SDRAM 4) and LPDDR4X applications, a high-speed interface standard of LVSTL (Low Voltage Swing Terminated Logic) is used, and different output pull-down driver capabilities and output high levels can be configured by a memory controller. However, because voltages of data output ports of the two are different, LPDDR4 and LPDDR4X cannot be applied to the same chip. This brings trouble to the application and design of the chip.

SUMMARY

The present invention provides an output circuit and a chip to at least resolve the foregoing technical problem in the prior art.

To achieve the foregoing objective, the present invention provides an output circuit, including: a first-stage circuit, a second-stage circuit, a third-stage circuit, and a fourth-stage circuit.

The first-stage circuit is configured to read serial data in a memory and divide the serial data into a plurality of first voltage signals each at a specified rate level.

The second-stage circuit is connected to the first-stage circuit, and is configured to: receive the plurality of first voltage signals output by the first-stage circuit, generate a plurality of second voltage signals, and allocate a transmission path to each of the generated second voltage signals.

The third-stage circuit is connected to the second-stage circuit, and is configured to: receive the plurality of second voltage signals output by the second-stage circuit, and allocate a transmission path to each of the second voltage signals according to a ZQ calibration signal.

The fourth-stage circuit is connected to the third-stage circuit, and includes a pull-up circuit and a pull-down circuit. The pull-up circuit and the pull-down circuit each include a plurality of parallel thin-gate low-threshold NMOS transistors, and the fourth-stage circuit is configured to receive a plurality of third voltage signals output by the third-stage circuit, and generate output voltage signals of the output circuit according to the third voltage signals.

In some embodiments, the pull-up circuit may include a plurality of parallel pull-up branches, each of the pull-up branches includes a first thin-gate low-threshold NMOS transistor with substantially the same structure, the drain of the first thin-gate low-threshold NMOS transistor is connected to a power supply voltage, and the gate of the first thin-gate low-threshold NMOS transistor is configured to receive a pull-up voltage signal output by the third-stage circuit; and the sources of the first thin-gate low-threshold NMOS transistors of the pull-up branches are connected as a data output terminal (DQ).

In some embodiments, the pull-down circuit may include a plurality of parallel pull-down branches, each of the pull-down branches includes a second thin-gate low-threshold NMOS transistor with substantially the same structure, the source of the second thin-gate low-threshold NMOS transistor is grounded, the drain of the second thin-gate low-threshold NMOS transistor is connected to the source of the first thin-gate low-threshold NMOS transistor, and the gate of the second thin-gate low-threshold NMOS transistor is configured to receive a pull-down voltage signal output by the third-stage circuit.

In some embodiments, the third-stage circuit may be further configured to output a plurality of pull-up ZQ calibration signals during ZQ calibration; and each of the pull-up branches may include a plurality of third thin-gate low-threshold NMOS transistors, and the third thin-gate low-threshold NMOS transistor in each pull-up branch may be connected in parallel to the first thin-gate low-threshold NMOS transistor; and the gate of the third thin-gate low-threshold NMOS transistor may be configured to receive the pull-up ZQ calibration signal, and the third thin-gate low-threshold NMOS transistor may be configured to adjust an equivalent resistance of the pull-up branch to RZQ (reference resistance) according to the pull-up ZQ calibration signal.

In some embodiments, the third-stage circuit may be further configured to output a plurality of pull-down ZQ calibration signals during ZQ calibration; and each of the pull-down branches may include a plurality of fourth thin-gate low-threshold NMOS transistors, and the fourth thin-gate low-threshold NMOS transistor in each pull-down branch may be connected in parallel to the second thin-gate low-threshold NMOS transistor; and the gate of the fourth thin-gate low-threshold NMOS transistor may be configured to receive the pull-down ZQ calibration signal, and the fourth thin-gate low-threshold NMOS transistor may be configured to adjust an equivalent resistance of the pull-down branch to RZQ according to the pull-down ZQ calibration signal.

In some embodiments, the plurality of third thin-gate low-threshold NMOS transistors and the plurality of fourth thin-gate low-threshold NMOS transistors may each have successively increasing equivalent width-to-length ratios.

In some embodiments, the pull-up circuit may further include a pull-up switch module, the pull-up switch module may include the same quantity of thick-gate high-threshold NMOS transistors as that of the first thin-gate low-threshold NMOS transistors, the drains of the thick-gate high-threshold NMOS transistors may be connected to the power supply voltage, the sources of the thick-gate high-threshold NMOS transistors may be respectively connected to the drains of the first thin-gate low-threshold NMOS transistors, and the gates of the thick-gate high-threshold NMOS transistors may be configured to receive a high-voltage threshold signal output by the third-stage circuit.

In some embodiments, each of the pull-up branches may further include at least one first low-voltage calibration MOS transistor. The first low-voltage calibration MOS transistor may be connected in parallel to the first thin-gate low-threshold NMOS transistor, the gate of the first low-voltage calibration MOS transistor may be connected to the third-stage circuit, and the first low-voltage calibration MOS transistor may be configured to be turned on at the time of receiving a low-voltage signal.

In some embodiments, each of the pull-down branches may further include at least one second low-voltage calibration MOS transistor. The second low-voltage calibration MOS transistor may be connected in parallel to the second thin-gate low-threshold NMOS transistor, the gate of the second low-voltage calibration MOS transistor may be connected to the third-stage circuit, and the second low-voltage calibration MOS transistor may be configured to be turned on at the time of receiving a low-voltage signal.

In some embodiments, a first fixed-value resistor may be connected in series between the data output terminal and a source connection terminal of the first thin-gate low-threshold NMOS transistor and the first low-voltage calibration MOS transistor, and a second fixed-value resistor may be connected in series between a source connection terminal of the plurality of third thin-gate low-threshold NMOS transistors and the data output terminal; and a third fixed-value resistor may be connected in series between the data output terminal and a source connection terminal of the second thin-gate low-threshold NMOS transistor and the second low-voltage calibration MOS transistor, and a fourth fixed-value resistor may be connected in series between a source connection terminal of the plurality of fourth thin-gate low-threshold NMOS transistors and the data output terminal.

In some embodiments, the first-stage circuit may include a first pull-up control module and a first pull-down control module that are of substantially the same structure, and both the first pull-up control module and the first pull-down control module may be configured to delay a read data signal, and divide and output the data signal into data signals of a plurality of rate levels.

In some embodiments, the second-stage circuit may include: a second pull-down control module. The second pull-down control module may be configured to: receive a data signal output by the first pull-down control module, and according to pull-down driver setting strength and an ODT (On Die Terminator) enable signal, select a path to output the data signal; a second pull-up control module, where the second pull-up control module is configured to: receive a data signal output by the first pull-up control module, and according to pull-up driver setting strength, select a path to output the data signal; and a pull-up switch control module. The pull-up switch control module may be configured to receive a switch enable signal and reuse the pull-up driver setting strength, so as to control each path in the second pull-up control module to be in one of an ON state and an OFF state.

In some embodiments, the third-stage circuit may include a third pull-up control module and a third pull-down control module that have substantially the same structure.

An input terminal of the third pull-up control module may be connected to the second pull-up control module and a ZQ calibration value, and an output terminal of the third pull-up control module may be connected to the gate of the first thin-gate low-threshold NMOS transistor; and the third pull-up control module may be configured to convert a received data signal and the ZQ calibration value into the pull-up voltage signal of the same rate and the pull-up ZQ calibration signal corresponding to the received data signal; and an input terminal of the third pull-down control module may be connected to the second pull-down control module and a ZQ calibration value, and an output terminal of the third pull-down control module may be connected to the gate of the second thin-gate low-threshold NMOS transistor; and the third pull-down control module may be configured to convert a received data signal and the ZQ calibration value into the pull-down voltage signal of the same rate and the pull-down ZQ calibration signal corresponding to the received data signal.

To achieve the foregoing objective, the present invention provides a chip, including the output circuit of the foregoing embodiments.

By using the foregoing technical solution, the present invention has the following advantages: The pull-up circuit is used to eliminate the limit on a minimum operating power supply voltage caused by an enable threshold voltage, so that two or more different high-speed data transmission standards become compatible. Thus the chip may operate in two environments with different output levels, thereby improving efficiency and reducing resource consumption.

The foregoing description is for the purpose of the specification only and is not intended to be restrictive in any way. In addition to the schematic aspects, implementations, and features described above, with reference to the accompanying drawings and the following detailed descriptions, further aspects, implementations, and features of the present invention will be readily understood.

