CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to French Patent Application No. 1903667, filed on Apr. 5, 2019, which application is hereby incorporated herein by reference.

TECHNICAL FIELD

Implementations and embodiments relate to integrated circuits of non-volatile memories, particularly writing to electrically erasable programmable read-only memory (EEPROM).

BACKGROUND

Integrated circuits of EEPROM memories typically comprise a memory plane for storing the stored data, decoders for accessing the data in the memory plane, and a peripheral portion.

The peripheral portion typically comprises a logic portion dimensioned for a power supply of, e.g., 5 V, conventionally comprising control means and a communication interface such as an I2C (“Inter-Integrated Circuits,” a standard well-known to the person skilled in the art) bus interface. The peripheral portion also comprises an analogue portion comprising high voltage or voltage ramp generators, amplifiers, and reference current generators.

SUMMARY

It is desirable to reduce the overall dimensions of the integrated circuit devices.

Techniques have been provided for reducing the size of the EEPROM memory plane.

However, for a given total memory capacity, the advantages of reducing the memory plane are partly dispelled by the overall dimensions of the peripheral portion. This phenomenon is worse for the lowest memory densities.

An efficiency parameter may be defined for the area of the memory plane “AE” where AE designates the ratio (area of the memory plane+decoders)/total area of the memory.

For example, for a memory of 128 kbit AE>50% in 0.18 μm technology, and AE<30% in 0.11 μm technology.

Accordingly, the shrinkage of the memory plane does not result in a significant gain in the complete product, particularly on low densities.

Moreover, many constraints prevent reducing the size of the components of the peripheral portion.

The peripheral portion comprises high voltage elements the dimensions of which are not practically capable of being reduced due to voltage stability constraints. The peripheral portion also comprises analogue components subjected to matching constraints (according to the usual term designating the design of elements whereof the characteristics exhibit little variation from one to another), which require large size components.

The elements meeting standards, e.g., communication interfaces such as an I2C interface, are provided with elements dedicated to their uses and do not, or only slightly benefit from manipulating their design in order to reduce their size.

However, it is desirable to reduce the overall dimensions of the peripheral portion of EEPROM memories in order to improve the efficiency parameter AE of the area of the memory plane.

EEPROM memories typically require an oscillator for activating a charge pump. This oscillator is preferably relatively fast. The oscillation frequency may be of medium precision, e.g., between 20 MHz and 30 MHz.

Also, EEPROM memories typically require a clock for timing write operations, and from which the write time is deduced, advantageously as accurately as possible. This clock may be slower (typically of the order of 1 MHz), but preferably accurate.

It is difficult in the context of EEPROM technologies, and within a constraint of minimum dimensions, to produce accurate oscillators, especially if they should to be fast.

Thus, EEPROM memories typically comprise a stable signal generator dedicated to the generation of a clock signal, while other generators are used for generating other oscillation signals, notably with high frequencies.

Embodiments are provided for generating stable frequencies based on a time reference already present on the circuit for other purposes, and not used for its initial purpose when it is used for stabilizing the frequencies.

Further embodiments provide that the area of the peripheral portion may be reduced, and the efficiency parameter AE of the area of the memory plane may be improved.

According one embodiment, a method of writing to an electrically erasable programmable read-only memory (EEPROM) is provided in this regard, comprising in a write cycle: operatively connecting a filter circuit belonging to a communication interface physically connected to a bus, with an oscillator circuit and generating via the oscillator circuit an oscillation signal and regulating the oscillation signal with the filter circuit, so as to generate a clock signal for timing the write cycle.

A write cycle designates the phase dedicated to writing data into the memory, generally comprising an erasure followed by programming one or more memory cells.

Preferably, the communication interface is of the I2C type, i.e., of the “inter-integrated circuits” type.

Thus according to this embodiment provision is made to use a filter circuit provided for a communication interface, for regulating an oscillation signal and thereby generating a sufficiently stable clock signal for timing the write cycle.

The method according to this embodiment thus makes it possible to meet the two constraints mentioned above, using only a single oscillator circuit.

According to one implementation, before operatively connecting the filter circuit with the oscillator circuit, the filter circuit is operatively disconnected from the communication interface.

During a write cycle, the exchanges on the bus via the communication interface are ignored, e.g., conventionally by forcing a reset of an output flip-flop intended for generating a circuit selection signal, preventing the selection of the circuit from a command transmitted to the communication interface of the I2C type, for the duration of the write cycle. However, spurious signals originating from outside may be transmitted on the bus, and operatively disconnecting the filter circuit from the communication interface prevents disruptions in the filter circuit originating from outside.

For example, before operatively connecting the filter circuit with the oscillator circuit, the filter circuit is operatively disconnected from the oscillator circuit and is operatively connected to the communication interface.

Conversely, this makes it possible for communications on the bus with the communication interface using the filter circuit not to be disrupted by the oscillation signal of the oscillator circuit.

According to one implementation, operatively connecting the filter circuit and the oscillator circuit comprises logic operations on a signal originating from the oscillator circuit and intended for the filter circuit with a mode selection signal, so as to deliver a signal to the filter circuit according to the signal originating from the oscillator circuit. Similarly, operatively connecting the filter circuit and the oscillator circuit comprises logic operations on a signal originating from the filter circuit and intended for the oscillator circuit with the mode selection signal, so as to deliver a signal to the oscillator circuit according to the signal originating from the filter circuit.

According to one implementation, operatively disconnecting the filter circuit and the communication interface comprises logic operations on a signal originating from the communication interface and intended for the filter circuit with a mode selection signal, the mode selection signal determining the result of the logic operations with a signal of constant arbitrary value, and logic operations on a signal originating from the filter circuit and intended for the communication interface with the mode selection signal, the mode selection signal determining the result of the logic operations with a signal of constant arbitrary value.

According to one implementation, the filter circuit has an adjustable time constant, and before regulating the oscillation signal with the filter circuit, the time constant is adjusted to a given value with a given precision.

Indeed, this makes it possible to improve the accuracy of the clock signal thus generated via regulation, the time constant of the filter circuit being able to undergo slight manufacturing process instabilities which are thus corrected by said adjustment, but being otherwise very stable with respect to temperature, power supply and ageing conditions

According to one alternative, the frequency of the oscillation signal is dynamically adjustable, and the regulation of the oscillation signal comprises a dynamic adjustment of the frequency of the oscillation signal relative to a time constant of the filter circuit.

This alternative may advantageously correspond to the use of an oscillator circuit capable of generating high frequencies for timing a charge pump, according to an implementation defined below.

Thus the frequency of the oscillation signal may be calibrated dynamically with respect to immediate variations, e.g., due to temperature, voltage and ageing conditions, being based on said time constant which is itself stable with respect to said conditions.

According to one implementation of this alternative, said regulation of the oscillation signal is performed at the start of each write cycle.

One calibration per write cycle is a period sufficient to compensate for the occurrence of variations in the frequency.

According to one implementation of this alternative, said dynamic adjustment of the frequency of the oscillation signal comprises counting the number of periods of the oscillation signal for the duration of the time constant, an adjustment of a level of the frequency of the oscillation signal, and a repetition of the counting and the adjustment until the number of counted periods closest to a preset targeted number is reached.

According to one implementation of this alternative, generating the clock signal further comprises a division of the frequency of the regulated oscillation signal.

According to one implementation of this alternative, the method further comprises in a write cycle, a generation of write high voltages comprising switchings of capacitive elements to supply voltages, the switchings being timed by the oscillation signal generated by the oscillator circuit.

According to another alternative, the generation of an oscillation signal comprises an accumulation of elementary delays, and the regulation of the oscillation signal comprises an insertion, in said accumulation, of an additional delay equal to a time constant of the filter circuit, the accumulation of elementary delays being negligible in duration with respect to the additional delay.

This alternative corresponds to the use of a conventional ring oscillator for generating the clock signal, but with the advantage of re-using the filter circuit of the communication interface when the latter is not used for this purpose.

According to another embodiment, an integrated circuit of an electrically erasable and programmable non-volatile memory is provided, comprising a state machine configured for controlling write operations in a write cycle timed by a clock signal, a communication interface comprising a filter circuit and physically connected to a bus, and means for generating the clock signal comprising an oscillator circuit and configured for, in a write cycle: operatively connecting the filter circuit with the oscillator circuit and generating an oscillation signal with the oscillator circuit and regulating the oscillation signal with the filter circuit, so as to generate the clock signal.

According to one embodiment, the means for generating the clock signal are configured for operatively disconnecting the filter circuit from the communication interface, before operatively connecting the filter circuit with the oscillator circuit.

According to one embodiment, the filter circuit is intended to be operatively disconnected from the oscillator circuit and to be operatively connected to the communication interface before being operatively connected with the oscillator circuit.

According to one embodiment, for operatively connecting the filter circuit and the oscillator circuit, the means for generating the clock signal comprise logic gates connected to an input of the filter circuit configured for, in the presence of a mode selection signal, generating on the input of the filter circuit a signal according to a signal originating from the oscillator circuit. And, the means for generating the clock signal also comprise logic gates connected to an output of the filter circuit configured for, in the presence of the mode selection signal, generating on an input of the oscillator circuit a signal according to a signal on the output of the filter circuit.

According to one embodiment, for operatively disconnecting the filter circuit and the communication interface, the means for generating the clock signal comprise logic gates connected respectively to an input of the filter circuit and to an output of the filter circuit, the logic gates being configured for generating a signal with a constant arbitrary value in the presence of a mode selection signal, equally signals intended for the filter circuit originating from the communication interface or signals at the output of the filter.

According to one embodiment, the filter circuit has an adjustable time constant, and the means for generating the clock signal are configured for adjusting the time constant to a given value with a given precision.

According to a first alternative, the oscillator circuit comprises an adjustment means capable of dynamically adjusting the frequency of the oscillation signal on command, and the means for generating the clock signal are configured for controlling a dynamic adjustment of the frequency of the oscillation signal relative to a time constant of the filter circuit, for regulating the oscillation signal.

According to one embodiment of the first alternative, the adjustment means of the oscillator circuit comprises a capacitive element with controllable capacitive value, or a power supply current generator with controllable current intensity.

According to one embodiment of the first alternative, the means for generating the clock signal are configured for regulating the oscillation signal at the start of each write cycle.

According to one embodiment of the first alternative, the adjustment means of the oscillator circuit comprises a counter configured for counting the number of periods of the oscillation signal for the duration of the time constant, and is configured for adjusting the frequency of the oscillation signal by an elementary level, and for repeating the counting and the adjustment until the number of counted periods closest to a preset targeted number is reached.

According to one embodiment of the first alternative, the means for generating the clock signal further comprise a frequency divider configured for dividing the frequency of the regulated oscillation signal.

According to one embodiment of the first alternative, the integrated circuit further comprises a charge pump circuit configured for generating write high voltages comprising switchings of capacitive elements over to power supply voltages, the switchings being timed by the oscillation signal generated by the oscillator circuit.

According to another alternative, the oscillator circuit comprises a ring oscillator configured for generating an accumulation of elementary delays on a signal, and the means for generating the clock signal are configured for connecting the filter circuit in a ring oscillator circuit, introducing an additional delay equal to a time constant of the filter circuit, the accumulation of elementary delays being negligible in duration with respect to the additional delay.

