BACKGROUND

The disclosure relates generally to semiconductor logic circuits. The disclosure relates particularly to exclusive or (XOR) and exclusive nor (XNOR) circuits including a single non-volatile memory cell.

Phase Change Memory (PCM) devices are non-volatile memory devices in which the state of the memory elements can be retained for days to decades without power consumption. Examples of volatile memory devices include Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM); where DRAM requires the memory element to be constantly refreshed while SRAM requires a constant supply of energy to maintain the state of the memory element.

With phase change memory, information is stored in materials that can be manipulated into different phases. Each of these phases exhibit different electrical properties which can be used for storing information. The amorphous and crystalline phases are typically two phases used for bit storage (0's and 1's) since they have detectable differences in electrical resistance. Specifically, the amorphous phase has a higher resistance than the crystalline phase.

Chalcogenides are a group of materials commonly utilized as phase change material. This group of materials contain a chalcogen (Periodic Table Group 16/VIA) and another element. Selenium (Se) and tellurium (Te) are the two most common semiconductors in the group used to produce a chalcogenide when creating a phase change memory cell. An example of this would be Ge2Sb2Te5(GST-225), SbTe, and In2Se3.

Phase change memory cell designs also attempt to minimize the area of each cell in order to maximize the density of the memory cell arrays, thereby reducing the overall die footprint of the associated circuits. Reducing the number of circuit components necessary for a logic device provides a means to reduce the overall logic circuit die footprint.

SUMMARY

The following presents a summary to provide a basic understanding of one or more embodiments of the disclosure. This summary is not intended to identify key or critical elements or delineate any scope of the particular embodiments or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, devices, systems, computer-implemented methods, apparatuses and/or computer program products enable computer logic circuits having fewer components and a reduced die footprint.

Aspects of the invention include a semiconductor device having a bottom electrode, a bottom heater over the bottom electrode, a bottom buffer layer over the bottom heater, a PCM region over the bottom buffer layer, a top buffer layer over the PCM region, a top heater over the top buffer layer, and a top electrode over the top heater.

Aspects of the invention disclose methods, systems and computer logic circuits associated with a semiconductor logic circuit including a non-volatile memory cell disposed in series between a first node and a second node, the first node configured to receive a first write pulse, the second node configured to receive a second write pulse, and the circuit configured to receive a read pulse across the first and second nodes. The method includes concurrently applying the first write pulse and the second write pulse to the non-volatile memory cell prior to a logical write operation, concurrently writing a first logical state of the first node and writing a second logical state of the second node, to the non-volatile memory, applying a read pulse across the first node and the second node, and interpreting the logical state of the circuit according to a response associated with the read pulse.

