CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority benefit under 35 U.S.C. § 119 of United Kingdom Patent Application No. 1811013.0, filed Jul. 4, 2018, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a gateway for use in a computer system to interface a host with a subsystem for acting as a work accelerator.

BACKGROUND

In the context of processing data for complex or high volume applications, a work accelerator may be a subsystem to which processing of certain data is offloaded from a host system. Such a work accelerator may have a specialised hardware for performing specific types of processing.

As an example, one area of computing in which such a specialised accelerator subsystem may be of use is found in machine intelligence. As will be familiar to those skilled in the art of machine intelligence, a machine intelligence algorithm is based around performing iterative updates to a “knowledge model”, which can be represented by a graph of multiple interconnected nodes. The implementation of each node involves the processing of data, and the interconnections of the graph correspond to data to be exchanged between the nodes. Typically, at least some of the processing of each node can be carried out independently of some or all others of the nodes in the graph, and therefore large graphs expose great opportunities for parallel processing. Therefore, a work accelerator specialised for machine intelligence applications may comprise a large degree of parallel processing.

One form of parallelism can be achieved by means of a processor comprising an arrangement of multiple tiles on the same chip (i.e. same die), each tile comprising its own separate respective processing unit and memory (including program memory and data memory). Thus separate portions of program code can be run in parallel on different ones of the tiles. The tiles are connected together via an on-chip interconnect which enables data to be exchanged between them. Such an accelerator may function as a subsystem for a host system to perform parallel processing of data sets provided to it.

In general, there may exist dependencies between the portions of a program running on different tiles. A technique is, therefore required to prevent a piece of code on one tile running ahead of data upon which it is dependent being made available by another piece of code on another tile. There are a number of possible schemes for achieving this, one of which is described here by way of example, ‘BSP’, bulk synchronous parallel. According to BSP, each tile performs a compute phase and an exchange phase in an alternating cycle.

During the compute phase each tile performs one or more computation tasks locally on tile, but does not communicate any results of its computations with any others of the tiles. In the exchange phase each tile is allowed to exchange one or more results of the computations from the preceding compute phase to and/or from one or more others of the tiles in the group, but does not yet proceed to the next compute phase. Further, according to the BSP principle, a barrier synchronization is placed at the juncture transitioning from the compute phase into the exchange phase, or transitioning from the exchange phase into the compute phase, or both. That is to say, either: (a) all tiles are required to complete their respective compute phases before any in the group is allowed to proceed to the next exchange phase, or (b) all tiles in the group are required to complete their respective exchange phases before any tile in the group is allowed to proceed to the next compute phase, or (c) both. In some scenarios a tile performing computation may be allowed to communicate with other system resources such as a network card or storage disk, as long as no communication with other tiles in the group is involved.

During an exchange phase, data exchange may not only take place internally (i.e. between tiles) within an accelerator, but in some circumstances may be required to take place between an accelerator and external storage, e.g. a host system. When a subsystem acts as a work accelerator, it is configured to process data sets provided to it (e.g. from a host system). The data sets should advantageously be retrieved such that they can be provided to the accelerator at the appropriate precompiled data exchange synchronisation point, which may represent a barrier synchronisation.

There is increasingly a requirement to enable accelerators to be connected in highly scalable systems. However, this should be done without excessive latencies for exchanging data, and mindful of the constraint when handling machine learning applications that there is not a high degree of determinism as to when data will be available, or what that data may be, for each piece of ‘ work’. In this context, work may be considered the processing of data, buy each accelerator, in each compute phase of the BSP system. When scaling subsystems by connecting them together—directly or indirectly—a problem may occur, which is how to ensure that the data is available for delivery to the accelerator when it is needed at the precompiled data exchange synchronisation point. This data may be retrieved from external storage—which may include different types of storage, e.g. host storage, or network access storage—prior to delivery to the accelerator at the precompiled data exchange synchronisation.

SUMMARY OF THE INVENTION

The present invention uses the concept of a gateway which can be used to provide data to the accelerators from external storage and thus interconnect them to scale a subsystem acting as a work accelerator. The external storage could be host storage, network access storage, storage at another gateway or storage at another accelerator. In some forms of the gateway, the gateway itself is an active processor of data and autonomously manages its data flows. The gateway acts as an intermediary between one or more accelerators operating in a BSP model and an external asynchronous environment. The gateway has a local memory for temporarily storing data for delivery to the accelerator from the external environment. This raises one challenge of how to ensure that the gateway has the appropriate data available in local memory for delivery to the accelerator at the precompiled data exchange synchronisation point.

According to one aspect of the invention there is provided a computer system comprising:a first accelerator for processing batches of data and generating result data;a gateway having an accelerator interface connected to the first accelerator and a gateway interface for connection to a second gateway for conveying data for processing by a second accelerator, wherein the first accelerator, the gateway and the second accelerator form a synchronisation zone in which a synchronisation barrier acts between a compute phase and an exchange phase in the synchronization zone,

wherein the accelerator interface is configured to receive messages from the first accelerator, each message comprising a batch of result data and a destination address indicating a storage location to receive the batch of result data, the accelerator interface further configured to check the destination address and to route the message to the gateway interface when the destination address indicates the storage location on the second accelerator.

In a BSP (or other sychnronisation system) the messages may be received in the exchange phase of the synchronization.

The computer system may comprise a second gateway connected to the gateway interface, the second accelerator connected to a second accelerator interface of the second gateway.

The gateway interface may comprise at least one fabric port having an address range which corresponds to addresses of storage locations on the second gateway and the second accelerator. A global address space ‘owned’ by a compiler at compile time of code to be executed by the gateways and accelerators is thus created, and can be extended as further gateways and accelerators are added.

The computer system may further comprise a third gateway connected to a second gateway interface of the second gateway, the third gateway being connected to a third accelerator through a third accelerator interface of the third gateway.

The first and second accelerators, and the first, second and third gateways may form part of the synchronisation zone.

The gateway interface may comprises multiple fabric port, each port for connection to a respective one of multiple gateways.

The gateway may be configured to augment or manipulate the result data prior to routing a message containing the manipulated or augmented result data to the destination address.

The gateway may be configured to manipulate or augment the data in the exchange phase of the synchronization.

The destination address may indicate a single storage location.

The destination address may be an implied broadcast address, and the accelerator interface may be configured to route the message to the gateway interface for transmission to the second accelerator and any further accelerators in the computer system.

The message may indicate multiple destination addresses, wherein the same batch of result data is routed to each of multiple different destination address in the computer system. Alternatively, the message may contain an indicator which is read at the accelerator interface or fabric port and mapped onto multiple or broadcast addresses using a mapping table, which is generated at compile time.

According to a second aspect, there is provided a method of operating a gateway to route data between accelerators and gateways in a scaled gateway fabric of a computer system. Thus, the invention may provide a method of exchanging data between first and second accelerators in a computer system, each accelerator configured to process batches of data and to generate result data, wherein the first accelerator is connected to a gateway via an accelerator interface of the gateway, wherein the gateway has a gateway interface for connection to a second gateway for conveying data for processing by the second accelerator, wherein the first accelerator, the gateway and the second accelerator form a synchronisation zone in which a synchronisation barrier acts between a compute phase and an exchange phase in the synchronisation zone, the method comprising:receiving messages from the first accelerator at the accelerator interface, each message comprising a batch of result data and a destination address indicating a storage location to receive the batch of result data;the accelerator interface checking the destination address and routing the message to the gateway interface when the destination address indicates the storage location on the second accelerator.

A third aspect provides a computer program recorded on non transitory or transitory medium which is compiled with a global address space for data storage at multiple accelerators cooperating on a single application and connected via gateways. Thus, the third aspect may provide a computer program stored on transitory or non-transitory media which comprises a set of computer readable instructions which when executed cause a gateway to implement the method as designed above.

