BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to an active gate drive circuit for a power MOSFET based on negative feedback mechanism.

2. Description of Related Art

The emergence of silicon carbide (SiC) and gallium nitride (GaN) semiconductor devices promises to revolutionize next-generation power electronics converters [1-4]. Compared with Si devices, SiC and GaN devices featured with high breakdown electric field, low on-state resistance, fast switching speed, and high junction temperature capability [5, 6]. These characteristics are beneficial for the efficiency, power density, and reliability of power electronics converters [7-9]. However, in a practical converter with phase-leg configuration, the switching transient of one device will impact its complementary device, generating the crosstalk phenomenon [4, 10].

The crosstalk phenomenon is characterized by large high-frequency spikes and oscillations on the interfered device's gate voltage. The fast switching generates high dv/dt and di/dt, which would pass through the Miller capacitance, inducing high-frequency spikes and oscillations on the gate voltage [11, 12]. Severe spikes and oscillations may lead to false triggers and additional switching losses, even lead to shooting thorough [9]. Moreover, overshoot and undershoot of the gate voltage are critical parameters that influence the switching-induced drift of gate threshold voltage [13-15]. Crosstalk is the critical element for the switching behavior of SiC and GaN devices [16-18].

As the interface between power circuits and logic control circuits, gate drives significantly affect devices' behavior, including the crosstalk phenomenon. However, the conventional gate drive with the fixed drive resistor must tradeoff between switching behaviors, such as switching speed, switching loss, switch stresses, and crosstalk suppression [19,20]. Introducing auxiliary passive components for crosstalk suppression also should tradeoff between switching behaviors to obtain superior performance [19]. Hence, introducing auxiliary active devices into the gate drive circuit, researchers propose various active gate drives to suppress SiC and GaN Devices crosstalk.

Literature [21] proposed two kinds of active gate drives, namely, Gate Impedance Regulation (GIR) and Gate Voltage Control (GVC). GIR predicts the variation trend of induced gate voltage and controls the auxiliary active device preemptively to reduce the gate impedance during the switching transients. Once its gate impedance becomes small during the switching transient, most displacement current will be bypassed by the gate loop, resulting in less current that would induce spurious gate voltage. Thus, crosstalk is mitigated. Similarly, GVC also predicts the variation trend of induced gate voltage. What is different is that GVC preemptively charges the gate-source capacitance before the switching transients to offset the induced voltage. In the follow-up research, literature [22] proposed the Intelligent Gate Drive (IGD). IGD has a gate assist circuit consisting of two auxiliary transistors with two diodes. By predicting the switching behavior, the assist circuits preemptively control the gate voltage and gate loop impedances. However, the complex auxiliary logic circuits are needed for detecting the induced gate voltage, or for predicting the variation trend of the induced gate voltage, to take preemptive action. However, from the end-users' point of view, additional complexity is added along with the reliability concern due to extra components. Thus, the acceptance and adoption of these advanced gate drive techniques are limited. The fixed operation cannot self-adaptive following the increase of dv/dt ratings to ensure real-time control and robustness against parameter uncertainty. Active Miller Clamp (AMC) [11, 12, 23] is a typical active gate drive to attenuate crosstalk and is widely used in commercial gate drive chips. The gate voltage is detected and the auxiliary clamp device is activated preemptively when the gate voltage drops below a threshold voltage, a value relative to the turn-off bias voltage. It is the detected gate voltage that is used to identify the existence of crosstalk. However, the detected gate voltage peaks are less than that across the internal gate-source terminals because of the relatively large internal gate resistance of the devices [21]. Moreover, due to the circuit propagation delay, the clamping bandwidth is not high enough for the crosstalk suppression [11, 21]. On the other hand, due to the high switching speed, the detected gate voltage is interfered with mainly by the common-source inductance between the drive loop and power loop, which is inevitable in practical situations [21]. AMC technique shows a significant crosstalk suppression with lower dv/dt ratings; However, some limitations and enlarged disturbance are visible at higher dv/dt, for example, higher than around 20 V/ns in the test bench used in the literature [11].

With a crosstalk suppression control that features a preemptive action, the existing active gate drive is mainly based on the feed forward architecture [24]. Besides the drive circuit, auxiliary logic circuits are needed for detecting the induced gate voltage or for predicting the variation trend of the induced gate voltage to take preemptive action. However, additional complexity is added along with the reliability concern due to extra components. Thus, the acceptance and adoption of these advanced gate drive techniques are limited. Furthermore, in the active gate drive based on the feed forward control architecture, the gate voltage follows the drive's output in an open-loop way. It operates fixedly, pre-set based on switching behavior prediction. The prediction is not always accurate, especially in a fast switching condition, due to detection deviation, propagation delay and parasitic inductances. The fixed operation cannot self-adaptive following the increase of dv/dt ratings to ensure real-time control and robustness against parameter uncertainty. The active gate drive based on the feedback control architecture naturally attracts the attention of researchers in this area.

The negative feedback control is initially implemented in the active gate drive for switching slew rate control [25] in the drive of Si power devices. The feedback control is implemented by high bandwidth analog circuits [26, 27] or digital approaches, such as field-programmable gate array with high-speed, high-resolution D/A and A/D conversion [28, 29]. High dv/dt and di/dt can result in crosstalk phenomenon with gate glitch, false-triggering, and other detrimental effects during switching transients. Unlike the design criterion of active gate drivers for Si power devices, crosstalk suppression for gate voltage stability is critical for SiC and GaN devices because of their low threshold voltage and considerable internal gate resistance. Several researchers have investigated the SiC or GaN based switching transition negative feedback control by either electrical approach [30] or optical approach [31, 32] but with relatively slow switching speed. Also, limited feedback control works focus on crosstalk suppression.

The implementation of negative feedback control in fast switching SiC and GaN devices for crosstalk suppression is challenging. Firstly, considering the switching time for SiC and GaN devices is as short as tens of nanoseconds, the propagation delay of the feedback control is a concern since it may be comparable, even longer than the switching time. Secondly, fast switching is always associated with parasitic ringing so that sensors that attempt to identify different switching subintervals easily interfere, resulting in improper operation. Generally, a high switching speed is desired due to the lower switching loss. However, coordinated optimization of gate voltage stability and switching speed is challenging.

This paper proposes a negative feedback active gate drive (NFAGD) employing one auxiliary P-channel MOSFET and one auxiliary capacitor together with the drive resistor for fast switching and crosstalk suppression base on the negative feedback control mechanism. The combined operation mechanism based on negative feedback control in the drive-semiconductor system is given to show the basic operation principle of the proposed gate drive. This paper then shows a design reference and experimental test results with commercial 1200V SiC MOSFETs to demonstrate the validity and effectiveness of the proposed methodology.

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SUMMARY OF THE INVENTION

The technical issue to be solved by the present invention is to provide a power MOSFET gate drive based on negative feedback mechanism, which can automatically suppress the induced gate voltage, or the so-called crosstalk, without sacrificing the switching speed and without increasing circuit complexity of a MOSFET.

The objective of the present invention is achieved by providing a MOSFET gate drive based on the negative feedback mechanism. The gate drive is used to connect the drive signal to enable or disable the switching action of the controlled MOSFET, comprising: an auxiliary MOSFET, being a P-channel MOSFET, and having its source connected to the gate of the controlled MOSFET for creating a negative feedback regulating mechanism, the auxiliary MOSFET having its drain connected to a drive voltage; the drive voltage is the output voltage of a push-pull drive circuit (usually realized by a conventional gate drive chip along with its power supplies) that has been filtered by a passive network which comprises a drive resistor R and an auxiliary capacitor C.

Moreover, the circuit further comprises:

(1) a first node, a second node, and a third node;

(2) a push-pull drive circuit, for providing a driving current to drive the controlled MOSFET, the drive signal being connected to the conventional gate drive chip or to a totem-pole circuit, forming the push-pull drive circuit, and the push-pull drive circuit and the third node being connected in series;

(3) a drive resistor R, having one end connected in series with the push-pull drive circuit, and having an opposite end connected to the first node, for limiting a charging/discharging current applied to an auxiliary capacitor C by the push-pull drive circuit;

(4) a voltage difference between the first node and a source of the controlled MOSFET being the drive voltage;

(5) an auxiliary capacitor C, having one end connected to the first node and having an opposite end connected to the source of the controlled MOSFET through the third node, so as to work with the drive resistor R to form the passive network for regulating a switching speed of the controlled MOSFET;

(6) the drain and the gate of the auxiliary MOSFET connect in series with the drive resistor R through the second node, the source of the auxiliary MOSFET is connected to the gate of the controlled MOSFET for creating the negative-feedback regulating mechanism.

Further, the push-pull drive circuit comprises: a conventional gate drive chip; an on-bias voltage VCCand an off-bias voltage VEE. The conventional gate drive chip having a positive supply terminal (the output side of isolation) connected to the positive pole of the on-bias voltage VCC, the conventional gate drive chip having a positive supply terminal (the output side of isolation) connected to the negative pole of the off-bias voltage VEE, the conventional gate drive chip having a drive output terminal connected to one end of the drive resistor R and having a drive input terminal connected to the drive signal; and a negative pole of the on-bias voltage VCCand a positive pole of the off-bias voltage VEEboth being connected to the third node. The conventional gate drive chip has a maximum permissible output current not smaller than (VCC−VEE)/Rg, where Rgis the internal gate resistance of the controlled MOSFET.

Further, the auxiliary MOSFET has a drain-source breakdown voltage not smaller than VCC−VEE, and has a maximum permissible continuous drain current not smaller than (VCC−VEE)/Rg.

The present invention has the following advantages. The negative feedback active gate drive (NFAGD) has a simple structure and easy to be realized using a conventional gate drive chip, a drive resistor, an auxiliary MOSFET and an auxiliary capacitor, without involving any additional logical circuits. Functionally, the negative feedback active gate drive (NFAGD) can automatically suppress the induced gate-source voltage and make the gate voltage of the MOSFET stable even during high-speed switching operation without sacrificing the switching speed of the MOSFET. In subsequent embodiments, compared to conventional passive suppression approaches, the negative feedback active gate drive (NFAGD) provides greater suppression of gate-source voltage spikes and oscillation. It can suppress the crosstalk without influencing the switching speed, thus enables coordinated optimization of gate voltage stability and switching behavior.

