BACKGROUND

Description of the Relevant Art

Advances in semiconductor fabrication techniques have been reducing transistor dimensions in order to increase both performance and functionality within the same amount of space. The supply voltages for the integrated circuits have been scaling down to reduce both power consumption and short channel effects. Therefore, an amount of inadvertent charge developed on these nodes that causes a current density to flow through metal wires and transistors (devices) that surpass safe thresholds also lowers substantially. Both planar transistors and non-planar transistors are fabricated for use in integrated circuits within semiconductor chips. A variety of choices exist for placing processing circuitry in system packaging to integrate the multiple types of integrated circuits. Some examples are a system-on-a-chip (SOC), multi-chip modules (MCMs) and a system-in-package (SiP). Mobile devices, desktop systems and servers use these packages.

Regardless of the choice for system packaging, during assembly of semiconductor chips, one or more die are placed onto a single substrate or onto a package, and these die are susceptible to an electrostatic discharge event. Despite many precautions taken to prevent objects in a manufacturing facility from developing opposing electrostatic charge, during the semiconductor chip assembly steps, it is possible for electrostatic charge of opposing polarity to develop on machinery. This machinery includes, but is not limited to, the holder of the die and the holder of the single substrate or the package on which the die is placed.

In view of the above, efficient methods and mechanisms for detecting and measuring electrostatic discharge during semiconductor assembly are desired.

