BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a semiconductor memory device capable of storing, for example, 2 bits or more of data.

2. Description of the Related Art

A nonvolatile semiconductor memory device capable of storing multivalued data, such as a NAND flash memory using EEPROM, has been proposed (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. 2000-195280).

In a nonvolatile semiconductor memory device of this type, when multivalued data is stored in a memory cell, a threshold voltage corresponding to each data is set in the memory cell. The number of threshold voltages increases as the number of bits in data stored in the memory cell increases. For example, to store 2 bits of 4-valued data, four threshold voltages are required. To store 3 bits of 8-valued data, eight threshold voltages are needed.

When data is written into a memory cell, it is verified whether the threshold voltage of the memory cell has reached a threshold voltage corresponding to the data to be written. To carry out a verify operation, the bit line to which the memory cell is connected is precharged to a specific potential. In this state, a verify voltage is supplied to the word line. If the threshold voltage of the memory cell has not reached the threshold voltage corresponding to the writing data, the memory cell turns on. As a result, the potential on the bit line is discharged via the memory cell and therefore goes low. In contrast, if the threshold voltage of the memory cell has reached the threshold voltage corresponding to the writing data, the memory cell remains off. As a result, the bit line remains high. The potential on the bit line is detected, thereby verifying the threshold voltage of the memory cell. The result of the verification has shown that the threshold voltage of the memory cell has not reached the threshold voltage corresponding to the data to be written into, writing is done again.

As described above, in a nonvolatile semiconductor memory device which stores multivalued data, when the number of bits of data to be stored is large, the number of threshold voltages set in the memory cell increases. In writing data, the verify operation has to be carried for on each threshold voltage. Consequently, it requires a long time to carry out the verify operation, which makes it difficult to speed up the data write operation.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present intention, there is provided a semiconductor memory device comprising: a memory cell array which is configured to have a plurality of memory cells arranged in a matrix, each of the plurality of memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3); and a control circuit which controls the potential of the word line and bit line according to input data and writes data into a memory cell and which writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.

According to a second aspect of the present intention, there is provided a semiconductor memory device comprising: a memory cell array which is configured to have a plurality of memory cells arranged in a matrix, each of the plurality of memory cells being connected to a word line and a bit line and being capable of storing 4 values; and a control circuit which controls the potentials of the word line and bit line according to input data and writes data into the memory cell and, wherein the control circuit, in a first write operation, changes the threshold voltage of the memory cell from a first threshold voltage to either the first threshold voltage or a second threshold voltage (the first threshold voltage<the second threshold voltage) and in a second write operation, changes the threshold voltage of the memory cell to either the first threshold voltage or a third threshold voltage (the first threshold voltage<the third threshold voltage) if the threshold voltage of the memory cell is the first threshold voltage, and to either a fourth threshold voltage (the second threshold voltage<=the fourth threshold voltage) or a fifth threshold voltage (the fourth threshold voltage<the fifth threshold voltage) if the threshold voltage of the memory cell is the second threshold voltage and which, in the first and second write operations, raises a program voltage in increments of ΔVpgm and carries out a write operation by repeating a program and verify operation, ΔVpgm in the first write operation being larger than ΔVpgm in the second write operation.

According to a third aspect of the present intention, there is provided a semiconductor memory device comprising: a memory cell array which is configured to have a plurality of memory cells arranged in a matrix, each of the plurality of memory cells being connected to a word line and a bit line and being capable of storing 4 values; and a control circuit which controls the potentials of the word line and bit line according to input data and writes data into the memory cell, wherein the control circuit, in a first write operation, changes the threshold voltage of the memory cell from a first threshold voltage to either the first threshold voltage or a second threshold voltage (the first threshold voltage<the second threshold voltage) and in a second write operation, changes the threshold voltage of the memory cell to either the first threshold voltage or a third threshold voltage (the first threshold voltage<the third threshold voltage) if the threshold voltage of the memory cell is the first threshold voltage, and to either a fourth threshold voltage (the second threshold voltage<=the fourth threshold voltage) or a fifth threshold voltage (the fourth threshold voltage<the fifth threshold voltage) if the threshold voltage of the memory cell is the second threshold voltage and which, in the second write operation, sets a maximum value to the number of verify operations of verifying whether the third threshold voltage has been reached by repeating a program and verify operation and, when the number of verify operations has reached the maximum value, skips the verify operation of verifying whether the third threshold voltage has been reached.

According to a fourth aspect of the present intention, there is provided a semiconductor memory device comprising: a memory cell which stores data using a first threshold voltage to an n-th threshold voltage (n is a natural number equal to or larger than 2); and a control circuit which writes any one of the first to n-th threshold voltages according to input data, wherein the control circuit, in a first write operation, writes k-valued threshold voltages of the n-th threshold voltage, (n−1)-th threshold voltage, . . . , (n−k+1)-th threshold voltage into the memory cell and, in a second write operation, writes k-valued threshold voltages of the (n−k)-th threshold voltage, (n−k−1)-th threshold voltage, . . . , (n−2k+1)-th threshold voltage into the memory cell and, in an n/k-th write operation, writes (k−1)-valued threshold voltages of the k-th threshold voltage, the (k−1)-th threshold voltage, . . . , second threshold voltage into the memory cell.

According to a fifth aspect of the present intention, there is provided a semiconductor memory device comprising: a memory which stores at least one data item; at least one data storage circuit which is connected to the memory cell and stores externally inputted data of a first logic level or a second logic level; and a control circuit which controls the operation of the data storage circuit, wherein the control circuit, when the logic level of the data stored in the data storage circuit is the first logic level, inverts the logic level to the second logic level and, when the logic of the data is the second logic level, inverts the logic level to the first logic level and further, when the logic level of the data stored in the data storage circuit is the first logic level, does writing on the memory cell to raise the threshold voltage and, when the logic level of the data is the second level, causes the threshold voltage of the memory cell to remain unchanged.

According to a sixth aspect of the present intention, there is provided a semiconductor memory device comprising: a memory cell array configured to have a plurality of memory cells arranged in a matrix, each of the plurality of memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3); and a control circuit which controls the potentials of the word line and bit line according to input data and writes data into a memory cell, wherein the control circuit writes data into the memory cell to an a1-valued (a1<=n) threshold voltage in a first write operation, to an a2-valued (a2<=n) threshold voltage in a second write operation, to an ak-valued (ak<=n) threshold voltage in a k-th write operation (k is a natural number equal to or larger than 2: k<=n) and which, in the first to k-th write operations, raises a program voltage in increments of ΔVpgm and carries out write operations by repeating a program and verify operation, ΔVpgm in the first to k-th write operations fulfilling the following expression: the first ΔVpgm>the second ΔVpgm> . . . >the k-th ΔVpgm.

According to a seventh aspect of the present intention, there is provided a semiconductor memory device comprising: a memory cell which stores data using a first to an n-th threshold voltage, each of the threshold voltages being defined so as to increase in the order of the first threshold voltage to the n-th threshold voltage (n is a natural number equal to or larger than 2) and rising as a result of a write operation; a control circuit which writes any one of the first to n-th threshold voltages into the memory cell according to input data, wherein the control circuit, in a first write operation, writes k1-valued threshold voltages of the n-th threshold voltage, (n−1)-th threshold voltage, . . . , (n−k1+1)-th threshold voltage into the memory cell and, in a second write operation, writes k2-valued threshold voltages of (n−k1)-th threshold voltage, (n−k1−1)-th threshold voltage, . . . , (n−k1−k2+1)-th threshold voltage into the memory cell and, in an i-th write operation, writes (ki−1)-valued threshold voltages of the ki-th threshold voltage, (ki−1)-th threshold voltage, . . . , second threshold voltage into the memory cell.

According to an eighth aspect of the present intention, there is provided a semiconductor memory device comprising: a memory cell array configured to have a plurality of memory cells arranged in a matrix, each of the plurality of memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3); a control circuit which controls the potentials of the word line and bit line according to input data and writes data into a memory cell and which, in a write operation, carries out a verify operation using a threshold voltage lower than a k-valued threshold voltage in verifying whether the threshold voltage of the memory cell has reached the k-valued threshold voltage and, if the threshold voltage of the memory cell has exceeded the threshold voltage lower than the k-valued threshold voltage, sets the data in the data storage circuit to the same data to be written to an i-valued threshold voltage (i<k) lower than the k-valued threshold voltage; and a data storage circuit which is connected to the bit line and stores at least one bit of data.

According to a ninth aspect of the present intention, there is provided a semiconductor memory device comprising: a memory cell which stores k bits of data (k is a natural number equal to or larger than 2); a first storage circuit which stores externally inputted data and the data read from the memory cell; a second storage circuit which stores the data stored in the first storage circuit; a third storage circuit which stores the data read from the memory cell; a fourth storage circuit which stores the data stored in the third storage circuit; and a control circuit which holds or change the data in the first to fourth storage circuits according to the data stored in the memory cell in a write operation and which writes 8-valued data simultaneously in a third page write operation.

According to a tenth aspect of the present intention, there is provided a semiconductor memory device comprising: a memory cell array in which a plurality of memory cells are arranged in a matrix, each of the plurality of memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3); and a control circuit which controls the potentials of the word line and bit line according to input data and reads data from the memory cell and which reads the data from the memory cell by precharging the bit line once and then changing the potential of the word line an i number of times.

