BACKGROUND

Fin field-effect transistor (“FinFET”) is a nonplanar, double-gate transistor built on a silicon-on-insulator (“SOI”) substrate. The FinFET is a variation on the traditional MOSFETs characterized by the presence of a thin silicon fin inversion channel on top of the substrate, allowing the gate to make two points of contact, namely the left and the right sides of the fin. More generally, FinFET refers to any fin-based mitigate transistor architecture regardless of the number of gates, the fin-shaped electrode allows multiple gates to operate on a single transistor. This type of multi-gate process extends Moore's law, allowing semiconductor manufacturers to create CPUs and memory modules that are smaller, faster, and more energy efficient. The FinFET devices have significantly faster switching times and higher current density than the mainstream CMOS technology.

In advanced nodes, standard cell libraries are developed with different cell heights, which corresponds to different number of fins in FinFET technology. Larger cell heights provide higher driving strength while at the cost of larger area, larger power consumption and larger pin capacitance. In comparison, cells with smaller heights are relatively small in area with weaker driving strength, and are more likely to suffer from routing congestion and pin accessibility issues. In advanced nodes, hybrid row-height systems are implemented to replace single row-height systems for increased area utilization.

In a hybrid row-height system, cells of different row-heights, corresponding to different number of fins for oxide diffusion, are implemented together. For example, a thinner row has one fin oxide diffusion, a taller row has two fins oxide diffusion. The hybrid row-height system cannot keep cell area shrinking ratio while maintaining the performance as node technology advances.

