FIELD OF INVENTION

The present application relates to the field of display technologies, and more particularly to driving circuit and a display panel.

BACKGROUND OF INVENTION

Current 8K (resolution 7680*4320) display panels with 1 gate and 1 data architecture (the same row of sub-pixels is connected to the same scan line and the same column of sub-pixels is connected to the same data line) are extremely sensitive to signal changes. Clock signal lines in the current 8K display panel are generally arranged vertically on both sides of a panel, and a low-frequency signal line A or a DC signal line is provided beside the clock signal lines on left and right sides. As shown inFIG. 1, a lateral coupling effect experienced by a clock signal line CK1and a clock signal line CK6is not completely consistent with intermediate clock signal line CK2to clock signal line CK5. Therefore, a load of the clock signal lines on both sides and a load of the clock signal lines in the middle may be different, which may result in defective horizontal lines of the display panel.

SUMMARY OF INVENTION

Embodiments of the present application provide a driving circuit and a display panel, to solve a technical problem of defective horizontal lines of a display panel caused by different loads of existing clock signal lines.

An embodiment of the present application provides a driving circuit comprising a signal generator; a driving circuit unit; a clock signal line group comprising a plurality of clock signal lines, wherein an input end of the clock signal line is electrically connected to the signal generator, and an output end of the clock signal line is electrically connected to the driving circuit unit, the clock signal lines are arranged side by side, and there is a first pitch between two adjacent clock signal lines; a non-high frequency signal line, wherein an input end of the non-high frequency signal line is electrically connected to the signal generator, and the non-high frequency signal line is provided on two sides of the clock signal line group; and a redundant clock signal line, wherein an input end of the redundant clock signal line is electrically connected to the signal generator; the redundant clock signal line is disposed between the clock signal line group and the non-high frequency signal line; a frequency and an amplitude of a signal received by the redundant clock signal line are the same as a frequency and an amplitude of a signal received by the clock signal line.

In the driving circuit according an embodiment of the present application, the redundant clock signal line has a second pitch with an adjacent clock signal line, and the second pitch is equal to the first pitch.

In the driving circuit according an embodiment of the present application, a thickness of the redundant clock signal line and a thickness of the clock signal line are equal.

In the driving circuit according to an embodiment of the present application, a thickness of the redundant clock signal line and a thickness of the clock signal line are equal.

In the driving circuit according to an embodiment of the present application, a width of the redundant clock signal line is less than or equal to a width of the clock signal line.

In the driving circuit according to an embodiment of the present application, material of the redundant clock signal line is the same as material of the clock signal line.

In the driving circuit according to an embodiment of the present application, the non-high frequency signal line has a third pitch with an adjacent redundant clock signal line, and the third pitch is equal to the second pitch.

In the driving circuit according to an embodiment of the present application, the non-high frequency signal line is a low-frequency signal line or a DC signal line.

In the driving circuit according to an embodiment of the present application, the non-high frequency signal line is a low-frequency signal line, and an output end of the low-frequency signal line is electrically connected to the driving circuit unit or a common electrode.

An embodiment of the present application further provides a display panel comprising a driving circuit disposed in a non-display area of the display panel. The driving circuit comprises a signal generator; a driving circuit unit; a clock signal line group comprising a plurality of clock signal lines, wherein an input end of the clock signal line is electrically connected to the signal generator, and an output end of the clock signal line is electrically connected to the driving circuit unit, the clock signal lines are arranged side by side, and there is a first pitch between two adjacent clock signal lines; a non-high frequency signal line, wherein an input end of the non-high frequency signal line is electrically connected to the signal generator, and the non-high frequency signal line is provided on two sides of the clock signal line group; and a redundant clock signal line, wherein an input end of the redundant clock signal line is electrically connected to the signal generator; the redundant clock signal line is disposed between the clock signal line group and the non-high frequency signal line; a frequency and an amplitude of a signal received by the redundant clock signal line are the same as a frequency and an amplitude of a signal received by the clock signal line.

In the display panel according to an embodiment of the present application, the redundant clock signal line has a second pitch with an adjacent clock signal line, and the second pitch is equal to the first pitch.

In the display panel according to an embodiment of the present application, a thickness of the redundant clock signal line and a thickness of the clock signal line are equal.

In the display panel according to an embodiment of the present application, a width of the redundant clock signal line is less than or equal to a width of the clock signal line.

In the display panel according to an embodiment of the present application, material of the redundant clock signal line is the same as material of the clock signal line.

In the display panel according to an embodiment of the present application, the non-high frequency signal line has a third pitch with an adjacent redundant clock signal line, and the third pitch is equal to the second pitch.

In the display panel according to an embodiment of the present application, the non-high frequency signal line is a low-frequency signal line or a DC signal line.

In the display panel according to an embodiment of the present application, the non-high frequency signal line is a low-frequency signal line, and an output end of the low-frequency signal line is electrically connected to the driving circuit unit or a common electrode.

It should be noted that a structure of the driving circuit of the display panel of an embodiment is the same as a structure of the driving circuit of the above embodiment.

Beneficial Effect

The driving circuit and the display panel of embodiments of the present application add a redundant clock signal line between the clock signal line group and the non-high frequency signal line. A frequency and an amplitude of a signal received by the redundant clock signal line are the same as a frequency and an amplitude of a signal received by the clock signal line, and do not enter the plane. Such an arrangement makes a lateral capacitive coupling of the clock signal lines in the clock signal line group the same. This achieves an effect of balancing a load of each clock signal line, and an image shows no horizontal line defects.

