FOREIGN PRIORITY

This application claims priority to European Patent Application No. 17197542.8 filed Oct. 20, 2017, the entire contents of which is incorporated herein by reference.

FIELD

The present disclosure relates to a monitoring system for identifying an operating state of a motor, and in particular whether the motor is operating normally or not.

BACKGROUND

Power drive units (PDU) may have multiple input channels such that, should one (or more) channel fail, the failed channel can be shut down, whilst the PDU continues to operate as normal, i.e. whilst providing the same output torque (the torque will remain the same, but the speed will decrease when one channel is shut down). However, when a channel has failed, it may be difficult to determine which channel has failed, because a mechanical connection between channels may cause normally functioning (i.e. non-failed channels) to be affected by the failed channel, causing them to exhibit outputs having a similar pattern to that of a failed channel.

SUMMARY

The present disclosure provides a monitoring system for identifying an operating state of a motor, the system comprising a speed sensor for determining a speed of a motor and providing a speed signal as a function of time in response thereto, and a processor configured to identify a symmetric and/or an asymmetric oscillation of the speed signal as a function of time.

A symmetric oscillation is an oscillation in the speed signal which has substantially the same positive and negative maximum amplitudes with respect to an average value of the speed signal. This may occur when the motor is in a failed or dysfunctional operating state (e.g. operating in a failed PDU channel) and the average value of the speed may be zero. An asymmetric oscillation is an oscillation in the speed signal which has substantially different positive and negative maximum amplitudes with respect to a local average value of the speed signal. This may be determined with respect to a local average value of the speed signal because the average speed signal may vary with time, e.g. when the motor is being ramped up or down in speed. For example, the average speed signal may be determined over a suitable time frame such as one or more oscillation cycles. Such asymmetric oscillations may occur when the motor is in a normally functioning operating state (e.g. in a normal PDU channel), but is mechanically coupled to a motor in a failed or dysfunctional state.

The speed sensor may directly detect the speed of the motor. Alternatively (or additionally), the speed sensor may detect the position of the motor, and determine the speed of the motor therefrom. The speed sensor may then provide the speed signal.

The processor may comprise any suitable means of the determining or identifying a symmetric and/or asymmetric oscillation of the speed signal. Techniques that are known in the art may be used.

The processor may comprise a first monitor, wherein the first monitor compares the speed signal to a first threshold speed, and is configured such that when the speed signal is greater than the first threshold speed, the first monitor counts up at a first count-up rate.

When the speed signal is less than or equal to the first threshold speed, the first monitor may count down at a first count-down rate.

Alternatively, the first monitor may use any other suitable means to count up and down. For example, the first monitor may use an integration algorithm. The integrator may activate when the speed signal is greater than the first threshold speed and decrease the value of the integral when the speed signal is less than or equal to the first threshold speed.

When the first monitor may output a “false” reading when a count of the first monitor is less than a first count threshold, and a “true” reading when the count of the first monitor is greater or equal to the first count threshold.

“True” and “False” may be Boolean outputs, which can be read (i.e. interpreted) and processed by suitable means, such as by a processor. The “True” and “False” readings would be understood to refer to any two labelled readings.

The processor may comprise a second monitor, wherein the second monitor compares the speed signal to a second threshold speed, and is configured such that when the speed signal is more negative than the second threshold speed, the second monitor counts up at a second count-up rate.

When the speed signal is more positive than or equal to the second threshold speed, the second monitor may count down at a second count-down rate.

Alternatively, the second monitor may use any other suitable means to count up and down. For example, the second monitor may use an integration algorithm. The integrator may activate when the speed signal is more negative than the second threshold speed and decrease the value of the integral when the speed signal is more positive than or equal to the second threshold.

The second monitor may output a “false” reading when a count of the second monitor is less than a second count threshold, and a “true” reading when the count of the second monitor is greater than or equal to the second count threshold

The count of a monitor refers to the cumulative number of counts (i.e. both up and down) from a start time.

The first count-down rate may be lower than the first count-up rate and/or the second count-down rate may be lower than the second count-up rate.

The first count-up rate may be the same as the second count-up rate and/or the first count-down rate may be the same as the second count-down rate.

The first threshold speed may have a first positive value with respect to an average speed of the signal and the second threshold speed may have a second value that is substantially the same as the first positive value but is negative with respect to the average speed of the signal.

The processor may be configured to determine if the speed signal varies as said symmetric oscillation or said asymmetric oscillation based on the outputs of the first and second monitors.

The processor may identify a symmetric oscillation of the speed signal when the readings of both the first and second monitors are simultaneously “true”.

The processor may achieve this by any suitable means such as, for example, by using an AND gate.

The processor may further comprise a counter, wherein the counter counts up when both the first and second monitors output a “true” reading, and identifies a symmetrical oscillation of the speed signal when the count of the counter exceeds a predetermined counter threshold. The counter may be a latched counter, which counts up and down, and the counter latches when the count is greater than a pre-defined number of counts.

The processor may additionally or alternatively detect or identify an asymmetric oscillation of the speed signal. It may do so by comparing the readings of the first and second monitors in any suitable way.

A motor assembly comprising a first motor and the monitoring system of any preceding claim, wherein the speed sensor is arranged for determining a speed of the first motor.

The motor system may include a second motor, a further speed sensor for determining a speed of the second motor and providing a speed signal as a function of time in response thereto, and a processor configured to identify a symmetric and/or an asymmetric oscillation of the speed signal as a function of time.

The motor system may further comprise a gearbox to which the first and second motors are coupled. The gearbox may be a differential gearbox, such as a summing differential gearbox.

The motor system may further comprise a shaft coupled to the first and second motors by the gearbox for enabling the first and/or second motor to drive the shaft.

The present disclosure also provides an actuator or power drive unit comprising the monitoring system or motor assembly as claimed in any preceding claim.

The motor(s) of the actuator may drive the shaft, which may be coupled to a load.

The present disclosure also provides an aerospace primary or secondary flight control system comprising the monitoring system, motor assembly or actuator described herein. For example, the control system may be a high lift system.

The present disclosure also provides a vehicle, such as an aircraft, comprising the monitoring system, motor assembly, actuator, or primary or secondary flight control system described herein.

However, the present disclosure is also applicable to non-aerospace applications that require detection of symmetrical and asymmetrical (i.e. non-symmetrical) failure modes. For example, other engineering sectors such as the automotive industry, or primary actuation in aerospace applications.

The present disclosure is also generally applicable in systems that use an electro-hydraulic servo drive control of the motor, e.g. in a closed loop control.

