TECHNICAL FIELD

Embodiments of the disclosure are in the field of integrated circuit structures and, in particular, self-aligned repeatedly stackable 3D vertical RRAM.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.

Embedded memory with non-volatile memory devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. A non-volatile memory device such as resistive random access memory (RRAM) device or magnetic tunnel junction (MTJ) memory device is coupled with selector element to form a memory cell. A large collection of memory cells forms a key component of non-volatile embedded memory. However, with scaling of memory devices, the technical challenges of assembling a vast number of memory cells presents formidable roadblocks to commercialization of this technology today.

