BACKGROUND

The present disclosure relates to bonding stack structures for particular semiconductor packaging applications.

DESCRIPTION OF THE RELATED ART

Some semiconductor chip packages use metallic bumps to allow for electrical connections to other devices. These bumps are formed over openings in a protective layer over a respective semiconductor chip.

SUMMARY

In accordance with some implementations, the present disclosure relates to a stack structure including a pad implemented on a substrate, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface. The stack structure also includes a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer.

In some embodiments, the stack structure further includes a metal structure implemented over the pad such that the metal structure is connected to the exposed upper surface of the upper metal layer through the plurality of openings of the passivation layer. In some implementations, the other layer of the pad is a metal layer such that the interface is between the polymer layer and the metal layer. In some embodiments, the metal layer is below the upper metal layer, and in some implementations, the upper metal layer is the metal layer forming the interface with the polymer layer.

In some embodiments, the polymer layer of the stack structure has a tensile film stress property, and in some implementations the polymer layer includes polyimide, benzocyclobutene (BCB), or polybenzoxazole (PBO). In some embodiments, the passivation layer of the stack structure includes a silicon nitride layer.

In some embodiments, the pattern defining the plurality of openings of the passivation layer, is configured to function as a strap or a net over the upper metal layer to thereby provide the compressive force on the upper metal layer. In some embodiments, the strap or the net of the pattern is substantially contiguous around the plurality of openings.

In some implementations, the substrate is a semiconductor substrate, and in some embodiments, the semiconductor substrate is a flip-chip substrate. In some embodiments, the pad of the stack structure is a bump pad and the metal structure is a metal bump. In some implementations, the semiconductor substrate is a base wafer layer having an integrated circuit (IC), and in some embodiments, the stack structure is configured to form a ring on the base wafer layer, the ring defining an inner area dimensioned to accommodate a device, the ring further configured to allow mounting of a cap wafer to substantially enclose the inner area.

The present disclosure also relates to a method for fabricating a stack structure. The method includes providing a substrate, forming a pad on the substrate such that the pad includes a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface, forming a passivation layer over the upper metal layer, and patterning the passivation layer to yield a plurality of openings to expose the upper surface of the upper metal layer, and to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface.

In some implementations, the method further comprises forming a metal structure over the pad such that the metal structure is connected to the exposed upper surface of the upper metal layer through the plurality of openings of the passivation layer.

According to some implementations, a chip is disclosed, having a substrate layer. The chip also includes a plurality of connection structures implemented on a surface of the substrate layer, each connection structure including a pad, where the pad includes a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface, the connection structure further including a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer, the connection structure further including a metal structure implemented over the pad such that the metal structure is connected to the exposed upper surface of the upper metal layer through the plurality of openings of the passivation layer.

In some embodiments, the chip is a flip-chip, and in some embodiments, the chip is a MEMS device. In some embodiments, the chip is an integrated passive device (IPD). In some implementations, the substrate layer includes a semiconductor die, while in some implementations, the semiconductor die includes an integrated circuit (IC), and in some implementations, the IC is configured to provide radio-frequency (RF) functionality.

In some embodiments, the substrate layer of the chip includes a semi-insulating layer, and in some embodiments, the semi-insulating layer includes a passive circuit. In some embodiments, the semi-insulating layer includes gallium arsenide (GaAs). In some embodiments, the substrate layer of the chip includes an insulator layer, and in some embodiments, the insulator layer includes glass or sapphire.

The present disclosure also relates to a method for fabricating a flip-chip. The method includes providing a semiconductor die having an integrated circuit (IC), and forming a plurality of connection structures on a surface of the die such that each connection structure includes a pad, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, where the upper metal layer has an upper surface. The method further includes forming a passivation layer over the upper metal layer, patterning the passivation layer to yield a plurality of openings to expose the upper surface of the upper metal layer and to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, and forming a metal structure over the pad such that the metal structure is connected to the exposed upper surface of the upper metal layer through the plurality of openings of the passivation layer.

Another aspect of the present disclosure includes a radio-frequency (RF) apparatus including a base wafer having an integrated circuit (IC) configured to provide RF functionality and a cap wafer implemented over the base wafer. The RF apparatus includes a ring structure implemented to join the cap wafer to the base wafer to yield a hermetic cavity, the ring structure including a pad, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface, the ring structure further including a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer, the ring structure further including a metal structure implemented over the pad such that the metal structure is connected to the exposed upper surface of the upper metal layer through the plurality of openings of the passivation layer.

In some embodiments, the cap wafer of the RF apparatus includes an IC, and in some embodiments, the IC of the cap wafer is at least partially connected electrically to the IC of the base wafer through the ring structure. In some implementations, the RF apparatus further includes a device implemented within the hermetic cavity.

In some embodiments, the device is built on, or a part of, the IC of the base wafer of the RF apparatus. In some embodiments, the device is a MEMS device, and in some embodiments, the device is mounted on the base wafer. In some embodiments, the device of the RF apparatus is a surface acoustic wave (SAW) device, a bulk acoustic wave (BAW) device, or a film bulk acoustic resonator (FBAR) device. In some embodiments, the device is an RF filter.

According to some implementations, the present disclosure relates to a method for fabricating a radio-frequency (RF) apparatus. The method includes providing a base wafer having an integrated circuit (IC) configured to provide RF functionality. The method also includes forming a ring structure on the base wafer such that the ring structure includes a pad, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface, the ring structure further including a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer, the ring structure further including a metal structure implemented over the pad such that the metal structure is connected to the exposed upper surface of the upper metal layer through the plurality of openings of the passivation layer, and mounting a cap wafer on the ring structure to yield a hermetic cavity.

In some implementations, the method includes mounting a device on the base wafer prior to the mounting of the cap wafer. In some embodiments, the mounting of the device includes mounting a surface acoustic wave (SAW) device, a bulk acoustic wave (BAW) device, or a film bulk acoustic resonator (FBAR) device on the base wafer.

The present disclosure further describes a radio-frequency (RF) module including a packaging substrate configured to receive a plurality of components, and an RF apparatus mounted on the packaging substrate, the RF apparatus including a stack structure having a pad, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface, the stack structure further including a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer, the stack structure further including a metal structure implemented over the pad such that the metal structure is connected to the exposed upper surface of the upper metal layer through the plurality of openings of the passivation layer.

In some embodiments, the RF apparatus of the RF module is a flip-chip. In some embodiments, the stack structure of the RF apparatus is a connection structure configured to facilitate mounting of the flip-chip. In some implementations, the RF apparatus is an apparatus having a hermetic cavity. In some implementations, the stack structure is a ring structure that interconnects a base wafer and a cap wafer to yield the hermetic cavity.

According to some implementations, the present disclosure relates to a wireless device including an antenna configured to transmit or receive a radio-frequency (RF) signal, and an RF apparatus configured to process the RF signal, the RF apparatus including a stack structure having a pad, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface, the stack structure further including a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer, the stack structure further including a metal structure implemented over the pad such that the metal structure is connected to the exposed upper surface of the upper metal layer through the plurality of openings of the passivation layer.

In some implementations, the RF apparatus of the wireless device is a flip-chip. In some implementations, the stack structure of the RF apparatus is a connection structure configured to facilitate mounting of the flip-chip. In some embodiments, the RF apparatus is an apparatus having a hermetic cavity. In some embodiments, the stack structure of the RF apparatus is a ring structure that interconnects a base wafer and a cap wafer to yield the hermetic cavity. In some embodiments, the RF apparatus of the wireless device has one or more other qualities of an RF apparatus, a stack structure or chip, as described in the present disclosure.

For purposes of summarizing the disclosure, certain aspects, advantages and novel features of the inventions have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.

