TECHNICAL FIELD

The present invention relates generally to a method, system, and computer program product for reducing the resistance and/or capacitance of a current path in vertical fin semiconductor devices. More particularly, the present invention relates to a method, system, and computer program product for forming self-aligned vias and air-gaps in semi conductor fabrication.

BACKGROUND

An integrated circuit (IC) is an electronic circuit formed using a semiconductor material, such as Silicon, as a substrate and by adding impurities to form solid-state semiconductor electronic devices (device, devices), such as transistors, diodes, capacitors, and resistors. Any reference to a “device” herein refers to a solid-state semiconductor electronic device unless expressly distinguished where used. Commonly known as a “chip” or a “package,” an integrated circuit is generally encased in hard plastic, forming a “package.” The components in modern day electronics generally appear to be rectangular black plastic packages with connector pins protruding from the plastic encasement. Often, many such packages are electrically coupled so that the chips therein form an electronic circuit to perform certain functions.

The software tools used for designing ICs produce, manipulate, or otherwise work with the circuit layout and circuit components on very small scales. Some of the components that such a tool may manipulate may only measure tens of nanometer across when formed in silicon. The designs produced and manipulated using these software tools are complex, often including hundreds of thousands of such components interconnected to form an intended electronic circuitry.

A layout includes shapes that the designer selects and positions to achieve a design objective. The objective is to have the shape—the target shape—appear on the wafer as designed. However, the shapes may not appear exactly as designed when manufactured on the wafer through photolithography. For example, a rectangular shape with sharp corners may appear as a rectangular shape with rounded corners on the wafer.

Once a design layout, also referred to simply as a layout, has been finalized for an IC, the design is converted into a set of masks or reticles. A set of masks or reticles is one or more masks or reticles. During manufacture, a semiconductor wafer is exposed to light or radiation through a mask to form microscopic components of the IC. This process is known as photolithography.

A manufacturing mask is a mask usable for successfully manufacturing or printing the contents of the mask onto wafer. During the photolithographic printing process, radiation is focused through the mask and at certain desired intensity of the radiation. This intensity of the radiation is commonly referred to as “dose”. The focus and the dosing of the radiation has to be precisely controlled to achieve the desired shape and electrical characteristics on the wafer. A cut mask is a mask usable to cut or form a pattern in one or more layers of materials during a fabrication process.

A device generally uses several layers of different materials to implement the device properties and function. A layer of material can be conductive, semi-conductive, insulating, resistive, capacitive, or have any number of other properties. Different layers of materials have to be formed using different methods, given the nature of the material, the shape, size or placement of the material, other materials adjacent to the material, and many other considerations.

An IC may use many layers of silicon to implement a circuit. In other words, components forming the circuit may be placed on different layers of silicon in a chip. Interconnects connecting the components on one layer to components on different layers go through the silicon layer. Such interconnects are also known as through silicon vias (TSVs).

The software tools used for designing ICs produce, manipulate, or otherwise work with the circuit layout and circuit components on very small scales. Some of the components that such a tool may manipulate may only measure a few nanometers across when formed in Silicon. The designs produced and manipulated using these software tools are complex, often including hundreds of thousands of such components interconnected to form an intended electronic circuitry.

The illustrative embodiments recognize that the present methods and techniques for fabricating vias are stretched to their limits due to the increased complexity of designs, increased density of components, reduced dimensions of the components, and the like. The existing process for fabricating vias is largely unsuitable for fabricating and interconnecting inline vias, line-end vias, and air-gaps, that each align with the lines in a given IC.

A line is a semiconductor structure formed to carry current to or from a semiconductor device, or in between semiconductor devices. A mandrel line and a non-mandrel line are two different types of lines. An inline via is a via that is fabricated on (or aligned with) a mandrel or non-mandrel line. A line-end via is a via that is fabricated at the end of a mandrel or non-mandrel line.

An air-gap is a hollow space, generally encapsulating vacuum, that is created within a structure formed in semiconductor material. An air-gap is used for reducing capacitance between adjacent structures, such as adjacent vias and/or lines. An air-gap can be formed by filling a shaped recess and pinching the material at the top of the fill.

Inline vias and line-end vias should align with lines, and air-gaps formed between such vias and/or lines should align with the vias and/or lines. Such self-aligned vias and air-gaps are presently difficult to fabricate and interconnect. Therefore, a method for fabricating forming self-aligned vias and air-gaps in semiconductor fabrication would be desirable.

SUMMARY

The illustrative embodiments provide a method, system, and computer program product. An embodiment includes a method that etches a first trench at a first location on a mandrel line in a set of mandrel lines, through a top mask layer and stopping at a middle mask layer. The embodiment etches a second trench at a second location on a non-mandrel line in a set of non-mandrel lines, through the top mask layer and stopping at the middle mask layer. The embodiment removes a spacer material from a structure resulting from etching the first trench and the second trench. The embodiment forms, using a removable material, a first via structure in the first trench and second via structure in the second trench. The embodiment forms an air-gap in a third trench created at a location of the spacer. The embodiment etches, to remove the first via structure and a first portion of a bottom mask layer under the first via structure, to form a fourth trench. The embodiment fills the fourth trench with a conductive metal to form a self-aligned line-end via on the mandrel line. Thus, the embodiment enables fabricating self-aligned vias on mandrel lines.

Another embodiment further etches, to remove the second via structure and a second portion of the bottom mask layer under the second via structure, to form a fifth trench. The embodiment fills the fifth trench with the conductive metal to form a self-aligned inline via on the non-mandrel line. Thus, the embodiment enables fabricating self-aligned vias on non-mandrel lines.

In another embodiment, the air-gap is aligned with the first via structure and the second via structure. Thus, the embodiment enables fabricating self-aligned air-gaps.

Another embodiment further fills the third trench with a low resistance material such that a hollow space is encapsulated within the low resistance material, the hollow space forming the air-gap. Thus, the embodiment enables fabricating an air-gap.

Another embodiment further stops, as a part of etching the third trench, the third trench at the bottom mask layer. Thus, the embodiment enables fabricating self-aligned vias and self-aligned air-gaps of one size.

Another embodiment further stops, as a part of etching the third trench, the third trench at the middle mask layer. Thus, the embodiment enables fabricating self-aligned vias and self-aligned air-gaps of another size.

In another embodiment, the second via structure and a third via structure are both inline vias, wherein the second via structure is aligned with the third via structure, and wherein the second via structure and the third via structure are both aligned with the non-mandrel line. Thus, the embodiment enables fabricating self-aligned vias on mandrel lines and non-mandrel lines, and self-aligned air-gaps.

In another embodiment, the first via structure and a third via structure are both line-end vias, wherein the first via structure is aligned with the third via structure, and wherein the first via structure and the third via structure are both aligned with the mandrel line. Thus, the embodiment enables fabricating self-aligned vias on mandrel lines and non-mandrel lines, and self-aligned air-gaps.

Another embodiment further separates two adjacent vias in the mandrel line with an intervening dielectric structure extending from the middle mask layer to the top mask layer. Thus, the embodiment enables separating self-aligned vias.

Another embodiment further fills the first trench and the second trench with the removable material up to the top mask layer. Thus, the embodiment enables another method of fabricating self-aligned vias.

Another embodiment further forms, in the structure, above the bottom mask layer, the first layer of a first material topped by the middle mask layer. The embodiment forms, above the middle mask layer, the second layer of a second material topped by the top mask layer. Thus, the embodiment enables another method of fabricating self-aligned vias.

Another embodiment further removes the top mask layer from above the spacer. The embodiment etches to create the third trench at the location of the spacer. Thus, the embodiment enables another method of fabricating self-aligned vias.

An embodiment includes a computer usable program product. The computer usable program product includes one or more computer-readable storage devices, and program instructions stored on at least one of the one or more storage devices.

An embodiment includes a computer system. The computer system includes one or more processors, one or more computer-readable memories, and one or more computer-readable storage devices, and program instructions stored on at least one of the one or more storage devices for execution by at least one of the one or more processors via at least one of the one or more memories.

