FIELD OF THE INVENTION

The present invention relates to the field of complementary metal oxide semiconductor (CMOS) image sensors. In particular the present invention relates to CMOS image sensors using charge domain binning to increase the sensitivity and to a method of readout of such a sensor.

BACKGROUND OF THE INVENTION

Binning is an advantageous approach for increasing the speed and reducing the power consumption of a readout of an array of pixels in an image sensor. When performing binning, the signals of a group of pixels are summed or averaged over the group of pixels and read out as a single signal. In particular, charge domain binning results in an increase in sensitivity and in a faster readout of an array of pixels. In such an approach, the charges of a group of pixels are added together, then converted into a corresponding voltage output. Typically, such group consists of 2×2 pixels, or 4×4, or 4×1, etc.

As an example of charge domain binning, WO2018/046688A1 discloses a plurality of shared pixel units, each of the pixel units comprising four sub-pixels connected in parallel, each having a photodiode and a transfer transistor. It is possible to read all of the sub-pixels of one pixel unit simultaneously, or to individually read out the sub-pixels. Reading the sub pixels simultaneously advantageously provides for a more sensitive pixel with more exposure surface area at the expense of lower pixel resolution.

It is a disadvantage of the charge domain binning method disclosed in WO2018/046688A1, that this method can only be applied to fairly simple and small (sub-)pixels. It cannot be applied to global shutter pixels and the overhead circuitry to realize the shared binning adds parasitic capacitance which reduces sensitivity and SNR.

SUMMARY OF THE INVENTION

It is an object of embodiments of the present invention to provide efficient charge domain binning in MOS pixels.

The above objective is accomplished by a device and a method in accordance with embodiments of the present invention.

In a first aspect, the present invention provides an array of pixels comprising at least two pixels in a common substrate. At least one of said pixels is configured or configurable to function as a pixel of a first type with a first, higher, charge collecting capability, for collecting charges generated by radiation impinging on the substrate. At least another one of said pixels is configurable to function (a) as a pixel of the first type and (b) as a pixel of a second type, with a second, reduced, charge collecting capability. The at least another one of said pixels is configurable to function as a pixel of both types, but obviously not as both types at the same time. At any moment in time, the at least another one of said pixels is configurable to function as a pixel of the first type, or as a pixel of the second type.

In accordance with embodiments of the present invention, a configuration in two modes is possible: a first mode wherein all pixels have the same charge collecting capability (all pixels are configured as pixels of the first type), which may be used for obtaining high resolution images, and a second mode where at least one pixel has a higher charge collecting capability (pixel of the first type), and at least one other pixel has a lower charge collecting capability (pixel of the second type), which may be used for charge binning.

In embodiments of the present invention, each of said at least two pixels comprises a photoreceptor charge collecting terminal in the common substrate. In particular embodiments, photoreceptor charge collecting terminal may form part of any of a photodiode, a pinned photodiode, a PIN photodiode, a Schottky photodiode, a photogate, a single-photon avalanche photodiode (SPAD), an avalanche photodiode (APD), or a photoresistor. The charge collecting terminal is for instance formed by an n-type volume in a p-type substrate in case of a photodiode in a p-type substrate and vice versa. Embodiments of the present invention also apply to pixels that have a photoresistor as photosensitive element, in which case the charge collecting terminal is formed by a highly doped volume. The other terminal is then formed by the common substrate.

In embodiments of the present invention, the at least two pixels are adapted for being configurable as a pixel of the first type (more collecting) or as a pixel of the second type (less collecting) under control of a voltage bias to be applied to the photoreceptor charge collecting terminal, wherein said voltage bias is either one of a predetermined voltage bias, or a programmable voltage bias, or a floating connection. In order to be not or less collecting, the non-collecting photoreceptor charge collecting terminals must be at an intermediate potential, which is, for an n-type collection volume in a p-type substrate, higher than the photoreceptor charge collecting terminal being forward biased towards the substrate, and lower than the bias of the photoreceptor charge collecting terminal.

The configuring of pixels to function as a pixel of the first type or as a pixel of the second type thus happens under pure electrical control. In particular embodiments, the electrical control of the configuration causes the widening of a depletion region of a pixel of the first type and/or the narrowing down of a depletion region of a pixel of the second type. The electrical control of pixels to function as a pixel of the first type (charge collecting) or of the second type (charge non-collecting) can be applied at will, individually per pixel, or per row or column if pixels are arranged in a grid.

The voltage bias may be applied directly or indirectly (e.g. via switches, charged capacitors, etc) to the photoreceptor charge collecting terminal.

An array of pixels in accordance with embodiments of the present invention may be a rectangular group of pixels, for instance 2×2, 3×3, 4×4, 1×3, 1×4, . . . . In practical implementations, an array of pixels will most often be much larger, e.g. 1080×1920 pixels, or 1440×2560 pixels, or larger.

An array of pixels in accordance with embodiments of the present may comprise at least one pixel configured as a pixel of the first type and a plurality of pixels configured as pixels of the second type, wherein said at least one pixel configured as a pixel of the first type is surrounded by a plurality of pixels configured as pixels of the second type. The at least one pixel configured as a pixel of the first type may for instance be surrounded by eight pixels configured as pixels of the second type.

An array of pixels in accordance with embodiments of the present invention, may comprise a plurality of pixels arranged in a 1- or 2-dimensional array, wherein each of said pixels configured as a pixel of the first type is surrounded by a plurality of pixels configured as pixels of the second type. In such implementations, no pixels at a border of the array are configured as pixels of the first type.

In particular embodiments of the present invention, each pixel of the array are configurable to function as a pixel of the first type and as a pixel of the second type. This provided most flexibility to the array. In alternative embodiments, some of the at least two pixels are fixedly configured to function as a pixel of the first type, and other pixels can be configured to function as a pixel of the first type or a pixel of the second type, depending on their control. In yet alternative embodiments of the present invention, also a combination is possible, in which some pixels are fixedly configured to function as a pixel of the first type, other pixels are fixedly configured to function as a pixel of the second type, and still other pixels are configurable to function as a pixel of the first type or as a pixel of the second type, depending on their control.

In an array in accordance with particular embodiments of the present invention, each of the at least two pixels, irrespective of being configured as a pixel of the first type or as a pixel of the second type, may be substantially equal.

In a second aspect, the present invention provides an image sensor comprising an array of pixels in accordance with embodiments of the first aspect of the present invention. In such image sensor according to embodiments of the second aspect of the present invention, pixels may be operated differently: some pixels may be operated to function as pixels of the first type—what would be called “normal” pixels, or charge collecting pixels —, and others may be operated to function as pixels of the second type, which are not (or less) charge collecting.

An image sensor according to embodiments of the present invention may be a complementary metal oxide semiconductor (CMOS) image sensor.

An image sensor according to embodiments of the present invention may be adapted for detecting backside radiation or frontside radiation.

In a third aspect, the present invention provides a method of operating an array of pixels in two different modes. The method comprisesin a first mode, configuring all pixels of the array to function as pixels of a first type with a first, higher, charge collecting capability, for collecting charges generated by radiation impinging on the substrate, andin a second mode, configuring at least one pixel of the array to function as a pixel of the first type, and configuring at least another one of the pixels to function as a pixel of a second type, with a second, reduced, charge collecting capability, so as to perform charge domain binning.

It is to be noted that no sequence is implied by the method described above: it only indicates that an array of pixels can be operated in two modes, which can be a first mode first, or in a second mode first.

A method in accordance with embodiments of the present invention comprises configuring a pixel to function as a pixel of the first type or as a pixel of the second type, by controlling a voltage bias, wherein the voltage bias is either one of a predetermined voltage bias, or a programmable voltage bias, or a floating connection.

A method in accordance with embodiments of the present invention may be performed on an array of pixels logically organized in row and columns, each pixel having a transfer transistor with a transfer gate, transfer gates of pixels in a same row being electrically connected to a transfer gate control wire, and pixels on a same column having a connection to a main supply via a column supply line. A row of pixels may be configured to function as pixels of the second type by biasing the transfer gate control wire for all pixels of that row such that the transfer transistors are made non-conductive. A column of pixels may be configured to function as pixels of the second type by leaving the supply line of the pixels on that column floating or biased at an intermediate bias between the main supply and a substrate bias. This way, a whole row and/or a whole column of pixels can be made not or less collecting. Where such rows and columns cross, the pixels are also not or less collecting.

Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims.

For purposes of summarizing the invention and the advantages achieved over the prior art, particular objects and advantages of the invention have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

The above and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.

