CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Chinese Application Serial No. 201910675677.8 filed Jul. 25, 2019, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

The present disclosure relates generally to information handling systems, and more particularly to configuring mapping granularity for storage devices in information handling systems.

As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.

Information handling systems often include storage devices such as, for example, Solid State Drive (SSD) storage devices that are used to store data. As would be appreciated by one of skill in the art, SSD storage devices store data in non-volatile memory devices such as NAND flash memory devices, and include an SSD controller that may utilize a Dual Data Rate (DDR) Dynamic Random Access Memory (DRAM) subsystem (typically DDR3 or DDR4) for the storage of management data used to manage those NAND flash memory devices. One of the management operations performed using management data stored on the DDR DRAM subsystem includes the mapping of logical storage locations associated with the SSD storage device to physical storage locations included in the NAND flash memory. As would be appreciated by one of skill in the art, such logical/physical storage location mappings may map Logical Allocation Addresses (LAAs) with Physical Allocation Addresses (PAAs), which allows the SSD controller receiving a data command (e.g., a write command) that is directed to an Logical Block Address (LBA) to identify the LAA associated with that LBA, and then determine the PAA that is mapped to that LAA and that identifies the physical location of the NAND flash memory in which that data is stored.

However, conventional mapping tables have a fixed mapping granularity that provides eight LBAs for each LAA that is mapped to a respective PAA, which can result in inefficiencies in the use of the mapping table that stores the logical/physical storage location mappings. For example, in the event data to be written to the SSD storage device is equal in size to eight LBAs, it may be written to a single PAA associated with the NAND flash memory devices, and a single LAA/PAA mapping entry may be provided in the mapping table that identifies the LAA that is associated with that PAA (and that is provided eight LBAs that are used to identify the logical storage location of that data.) However, in the event data to be written to the SSD storage device is greater in size than eight LBAs, it will be divided into data portions that are each equal in size to eight LBAs, and each of those data portion may be written to a respective PAA associated with the NAND flash memory devices, with multiple LAA/PAA mapping entries provided in the mapping table that each identify an LAA that is associated with each respective PAA (and that are each provided eight LBAs that define the logical storage location of a respective data portion.) As such, data that is equal in size to thirty-two LBAs will be divided into four eight-LBA sized data portions that are each written to a respective PAA associated with the NAND flash memory devices, and four mapping entries may be provided in the mapping table—one for each LAA that is associated with each of those respective PAAs (and each of which is provided eight LBAs that define the logical storage location of its respective eight-LBA sized data portion.) As such, for large data writes, the mapping table can grow very quickly, and has been found to occupy as much as 80% of the DDR DRAM subsystem in the SSD storage device.

Furthermore, such fixed mapping granularity also creates Read-Modify-Write (RMW) events. For example, when new data that is smaller in size than eight LBAs is used to modify existing data that is associated with a PAA in the NAND flash memory devices, all the existing data stored in association with that PAA must be read from the NAND flash memory devices, modified by writing the new data to the portion of that existing data that is being changed, and written back to the NAND flash memory devices. As would be appreciated by one of skill in the art, such RMW operations require additional SSD controller processing cycles that operate to reduce the performance of the SSD storage device, particularly relative to the situation where a modification to existing data in the NAND flash memory devices modifies all of that data (e.g., because the new data may simply be written directly to the NAND flash memory device that stores the existing data, rather than requiring the RMW operations discussed above.)

Accordingly, it would be desirable to provide a storage device mapping granularity system that addresses the issues discussed above.

SUMMARY

According to one embodiment, an Information Handling System (IHS) includes a processing system; and a memory system that is coupled to the processing system and that includes instructions that, when executed by the processing system, cause the processing system to provide a storage controller engine that is configured to: receive, from a host engine, a first storage device mapping granularity configuration command that identifies a first number of Logical Block Addresses (LBAs) to associate with a first plurality of Logical Allocation Addresses (LAAs); associate each of the first plurality of LAAs with the first number of LBAs identified in the first storage device mapping granularity configuration command; write, to a first Physical Allocation Address (PAA) that identifies a first physical location in a storage subsystem, first data that includes a first data size that is equal to a first combined LBA size of the first number of LBAs that were identified in the first storage device mapping granularity configuration command and associated with each of the first plurality of LAAs; and map, in a logical/physical storage location mapping database, the first PAA to a first LAA that is included in the first plurality of LLAs and that is associated the first number of LBAs identified in the first storage device mapping granularity configuration command.

