TECHNICAL FIELD

The present invention relates to a processor device.

BACKGROUND ART

In recent years, a processing device capable of performing a very large amount of processing, such as image processing, simply and at high speed is desired. As a means for performing such a large amount of processing at high speed, parallel processing is promising. However, the parallel processing requires a high degree of expertise in various fields, such as expertise in program construction, and transmission between processors due to data dependency. Thus, a patent document 1 proposes a technique wherein, in a multiprocessor device having a plurality of processors and a register memory, the plurality of processors repetitively processes the same instruction by performing processing of only a given quantity while changing addressing for the register memory, when the processing of the given quantity is finished, the command is switched to a next command, and processing of only a next given quantity is performed.

CITATION LIST

Patent Document

Patent document 1: WO 2016/024508

SUMMARY OF INVENTION

Problems to Be Solved by Invention

The processor device as disclosed in the above-described patent document 1 is desired to process at much higher-speed. As one of the large amount of processing as described above, inference processing and learning processing in deep learning is exemplified. Since actual state of the deep learning is a matrix product-sum operation, mounting many matrix operation units specialized in a product-sum operation on a processor device is assumed to improve processing performance thereof. However, in this situation, there is a problem that the processor device lacks universal applicability.

Thus, an object of the present invention is to provide a processor device capable of processing at higher-speed than conventional processor devices, as well as being applicable to various arithmetic processing.

Solution to Problem

To solve the above-described problem, a processor device according to one embodiment of the present invention includes an external memory, a plurality of processors, a plurality of register groups, a memory access unit, a control unit, and a scheduler. Each of the plurality of register groups includes a plurality of registers to store data to be processed. The memory access unit reads data to be processed from the external memory and writes the data to a first register group that the plurality of processors does not access among the plurality of register groups. The control unit sequentially makes each of the plurality of processors implement the same instruction, in parallel with changing an address of one register group that stores the data to be processed. The scheduler, based on specified scenario information, specifies an instruction to be implemented and a register group to be accessed for the plurality of processors, and specifies a register group to be written to among the plurality of register groups and data to be processed that is to be written for the memory access unit.

Alternatively, the above processor device can adopt a configuration wherein a bank that is comprised of one register group among the plurality of register groups and is defined for each of the plurality of processors is provided. In this configuration, each of the plurality of processors reads data from the register group that is defined as a bank and implements a given instruction.

In the above-described processor device, the plurality of processors may be configured to write data that is obtained as a result of implementing the instruction to the first register group from which data to be processed that is an original data thereof is read. In this case, the memory access unit may be configured to read the data that is written to the first register group by the plurality of processors, and write the data to the external memory.

Alternatively, in the above-described processor device, when the plurality of processors implements the same instruction by using the data stored in the first register group, the memory access unit may be configured to read data to be processed from the external memory according to an instruction to be implemented next by the plurality of processors and write the data to be processed to a second register group that is included in the plurality of register groups and includes a plurality of registers different from the first register group.

Further, in the above-described processor device, the scheduler may be configured to increase operation speed of each of the plurality of processors according to an instruction to be implemented by each of the plurality of processors.

Furthermore, the scheduler is inputted a leaning model comprised of a node and a link for inference processing and learning processing in deep learning. In this case, the scheduler may be configured to store input data to each node of the learning model in each register of the plurality of register groups, and the plurality of processors performs an arithmetic operation to be performed in each node.

Effect of Invention

The processor device according to one embodiment of the present invention can achieve parallel processing simply by implementing the same instruction by performing processing of only a specified quantity, in parallel with sliding the address of the register memory, and further can enhance a parallel degree of the processing by setting a bank where the plurality of processors is accessible.

