CROSS-REFERENCE TO RELATED APPLICATION

Priority is claimed on Japanese Patent Application No. 2019-183605, filed on Oct. 4, 2019, the contents of which are incorporated herein by reference.

BACKGROUND

Field of the Invention

The present invention relates to a semiconductor apparatus.

Background

In recent years, a HBM (High Bandwidth Memory) in which DRAM chips are laminated to enlarge a bandwidth and increase a speed has attracted attention (for example, refer to Japanese Unexamined Patent Application, First Publication No. 2018-32141 and Japanese Unexamined Patent Application, First Publication No. 2006-277870). A currently developed cutting-edge HBM2 is formed of laminated four chips and includes an input/output I/O of 1024 channels. In order to adapt to the speed of a CPU/GPU having a further increased speed, HBMs to be developed in the future are required to increase an input/output I/O number by one digit or two digits in some way and to achieve a further large-scale parallel processing (Parallelism).

SUMMARY

In order to realize a large-scale parallel processing having an increased input/output I/O number by one digit to two digits, it is necessary to narrow the number of TSV (Through Silicon Via) pitches from a current 100 μm pitch to a several 10 μm pitch, and finally to a 10 μm pitch. However, when a large number of TSVs stand at a pitch of 10 μm, the precise input and output of I/O data becomes difficult due to an impact of a noise associated with capacitive coupling between the TSVs. Such an electrical problem becomes more dominant as the pitch of the TSV becomes narrower.

An aspect of the present invention is intended to provide a semiconductor apparatus capable of preventing capacitive coupling between penetration electrodes (TSVs) formed in a narrow pitch.

A semiconductor apparatus according to a first aspect of the present invention includes: a plurality of semiconductor chips that are laminated; a plurality of penetration electrodes that penetrate in a lamination direction through the plurality of semiconductor chips and that electrically connect together the plurality of semiconductor chips; and a plurality of input/output elements that are configured to perform a signal input/output operation to the plurality of penetration electrodes, wherein the semiconductor chips are joined together via no bump, one of the plurality of input/output elements is connected to each of the plurality of penetration electrodes such that a functional element connected to each of the plurality of penetration electrodes performs an ON or OFF operation at a predetermined timing, and the input/output element connected to a first of two adjacent penetration electrodes among the plurality of penetration electrodes and the input/output element connected to a second of two adjacent penetration electrodes are configured to perform the signal input/output operation at a different timing from each other.

A second aspect of the present invention is the semiconductor apparatus according to the first aspect, wherein the plurality of input/output elements may be connected to an external electric power source that is configured to generate a clock signal, the input/output element connected to the first of two adjacent penetration electrodes may be configured to perform an input/output operation at a timing of rising of the generated clock signal, and the input/output element connected to the second of two adjacent penetration electrodes may be configured to perform an input/output operation at a timing of falling of the generated clock signal.

A third aspect of the present invention is the semiconductor apparatus according to the first aspect, wherein the plurality of input/output elements may be connected to an external electric power source that is configured to generate a clock signal, the input/output element connected to the first of two adjacent penetration electrodes may be configured to perform an input/output operation at a timing of rising or falling in an odd cycle of the generated clock signal, and the input/output element connected to the second of two adjacent penetration electrodes may be configured to perform an input/output operation at a timing of rising or falling in an even cycle of the generated clock signal.

A fourth aspect of the present invention is the semiconductor apparatus according to the first aspect, wherein the plurality of input/output elements may be connected to an external electric power source that is configured to generate a clock signal, and the input/output elements which are each connected to one of the penetration electrodes that are adjacent in one direction and the input/output elements which are each connected to one of the penetration electrodes that are adjacent in another direction may be configured to perform the signal input/output operation at a different timing from each other.

A fifth aspect of the present invention is the semiconductor apparatus according to the fourth aspect, wherein the input/output element connected to a first of two penetration electrodes that are adjacent in the one direction may be configured to perform an input/output operation at a timing of rising in an odd cycle of the generated clock signal, the input/output element connected to a second of two penetration electrodes that are adjacent in the one direction may be configured to perform an input/output operation at a timing of falling in the odd cycle of the generated clock signal, the input/output element connected to a first of two penetration electrodes that are adjacent in the other direction may be configured to perform an input/output operation at a timing of rising in an even cycle of the generated clock signal, and the input/output element connected to a second of two penetration electrodes that are adjacent in the other direction may be configured to perform an input/output operation at a timing of falling in the even cycle of the generated clock signal.

A sixth aspect of the present invention is the semiconductor apparatus according to any of the first to fifth aspects, wherein the plurality of penetration electrodes may be arranged to form a checker pattern.

A seventh aspect of the present invention may be the semiconductor apparatus according to any of the first to fifth aspects, wherein the plurality of penetration electrodes may be arranged to form a staggered grating pattern.

An eighth aspect of the present invention is the semiconductor apparatus according to any of the first to fifth aspects, wherein the plurality of penetration electrodes may be arranged to form a honeycomb pattern.

In the semiconductor apparatus according to the aspect of the present invention, functional elements on a different semiconductor chip are connected together via the plurality of penetration electrodes. The input/output element connected to the first of two adjacent penetration electrodes and the input/output element connected to the second of two adjacent penetration electrodes are configured to perform the input/output at a different timing from each other. Therefore, an input/output signal is not applied simultaneously to the two adjacent penetration electrodes. That is, when one changes from a H state to a L state or from the L state to the H state, another maintains the H state or the L state. Accordingly, in a case where the plurality of penetration electrodes are formed at a narrow pitch, the input/output signal applied to any of the penetration electrodes is not affected by a noise associated with capacitive coupling with another input/output signal, and the ON/OFF operation of the functional elements can be performed in a stable state.

