FIELD OF THE INVENTION

The present invention relates generally to data transfer among components in a computing system, and, more particularly, relates to real-time direct data transfer from one peripheral system to a main system memory, and from the main system memory to another peripheral system.

BACKGROUND OF THE INVENTION

In a typical computing system it is common to interface a central processing unit (CPU) to one or more peripheral components. The CPU includes memory in which application programs can be instantiated and executed, as well as input/output interfaces for interfacing with displays, keyboards, pointing devices, etc. The applications running on the CPU can use data provided by peripheral components, as well as generate data to be used by peripheral components. Communication and data transfer between peripheral components and the CPU occur over a bus via programmed I/O or direct memory access (DMA), using an application programming interface (API). When an application program running on the CPU needs data from a peripheral component, the program makes a call through the API, and the peripheral component responds in due course. This necessarily requires more clock cycles than would be required if the processor of the CPU could access the peripheral component's data in directly in the CPU's own physical memory. For many types of application programs, the CPU overhead and access latency that is inherent in retrieving data through API calls for every transfer is not a concern, or at least it is within an acceptable margin. However, for systems that are real-time dependent, reducing latency and freeing up processor time would be highly desirable. For example, in complex real-time simulation systems, there can be a large amount of data being produced by peripheral components, as well as data that other peripheral components need from the CPU immediately in order to carry out operations in accordance with user input in a real-time manner. In such applications, API calls for every transfer of data create an undesirable restriction in time and processing load on the CPU.

Therefore, a need exists to overcome the problems with the prior art as discussed above.

SUMMARY OF THE INVENTION

In accordance with some embodiments of the inventive disclosure, there is provided a method for cloning data in a real-time simulator system that includes defining, in a local memory of a first peripheral device, a range of memory locations of the local memory to be cloned. The method further includes receiving, at the first peripheral device, a plurality of signals produced by one or more physical components of a first peripheral system. The method also includes converting, by the first peripheral system, the plurality of signals produced by the physical components of a first peripheral system to a corresponding plurality of signal values and storing each one of the signal values in a respective assigned one of the range of memory locations of the local memory of the first peripheral device. The method can further include defining, in a memory of a main computing system, a dedicated memory space corresponding in size to the range of memory locations defined in the local memory of the first peripheral device, wherein each one of the plurality of signal values of the first peripheral system are mapped to respective memory location in the dedicated memory space in the memory of the main computing system. The method further includes writing, by a local processor on the first peripheral device, the signal values from the range of memory locations of the local memory of the first peripheral device directly to the dedicated memory space over a common bus of the main computing system.

In accordance with a further feature, writing to the dedicated memory space comprises writing to a dedicated memory space in a random access memory.

In accordance with a further feature, the common bus is a peripheral component interface bus.

In accordance with a further feature, writing directly to the dedicated memory space comprises writing to a processor cache of a processor of the computing system.

In accordance with a further feature, writing to the dedicated memory space in the physical memory is performed asynchronously and continuously by the local processor of the first peripheral device.

In accordance with a further feature, defining the range of memory locations of the local memory to be cloned is performed by a processor of the main computing system configuring the first peripheral device using an application programming interface.

In accordance with a further feature, the method further includes generating, by a processor of the main computing system, a plurality of output signal values for a second peripheral system that is, at least in part, based on the signal values in the first dedicated memory space. The method further includes the processor of the main computing system writing the plurality of output signal values for the second peripheral system in a second dedicated memory space of the main computing system. The method further includes a local processor of a second peripheral component directly accessing the second dedicated memory space to read from the second dedicated memory space. The method further includes the local processor of the second peripheral system writing output signal values of the plurality of output signal values read from the second dedicated memory space into corresponding memory locations in a local memory of the second peripheral component.

In accordance with a further feature, the method further includes providing each one of the output signal values in the local memory of the second peripheral component to a respective one of a plurality of D/A channels of the second peripheral component. The method further includes each one of the plurality of D/A channels generating an analog output based on the respective output signal value. The method further includes providing the analog output of each D/A channel to a respective hardware component of the second peripheral system.

In accordance with some embodiments of the inventive disclosure, there is also provided a method for cloning data between a peripheral domain and a user domain operated on a main system, the peripheral component being interfaced with the main system by a bus system, the method including configuring a peripheral component, through an application programming interface, by the main system, to directly write data in a plurality of local memory locations of the peripheral component to specified physical memory locations of the main system on an ongoing asynchronous basis. The method further includes generating data by the peripheral component at the local memory locations of the peripheral component. The method further includes the peripheral component generating a plurality of signal values from hardware elements, and wherein each of the plurality of signal values are written into an assigned respective memory location of the local memory location. The method further includes the peripheral component writing the signal data of the local memory locations to the specified physical memory locations of the main system over the bus system using a modular scatter gather engine. The method further includes a processor of the main system accessing the signal data in the specified physical memory locations using direct addressing to generate output signal values based on the signal data for a second peripheral system.

In accordance with a further feature, writing to the specified physical memory locations comprises writing to a random access memory.

In accordance with a further feature, the bus is a peripheral component interface bus.

In accordance with a further feature, writing directly to the specified memory locations comprises writing to a processor cache of a processor of the computing system.

In accordance with a further feature, writing to the specific physical memory location in the physical memory is performed asynchronously and continuously by a local processor of the first peripheral component.

In accordance with a further feature, the method further includes the processor of the main computing system writing the plurality of output signal values for the second peripheral system in a second dedicated memory space of the main computing system. The method further includes a local processor of a second peripheral component directly accessing the second dedicated memory space to read from the second dedicated memory space. The method further includes the local processor of the second peripheral system writing output signal values of the plurality of output signal values read from the second dedicated memory space into corresponding memory locations in a local memory of the second peripheral component.

In accordance with a further feature, the method further includes providing each one of the output signal values in the local memory of the second peripheral component to a respective one of a plurality of D/A channels of the second peripheral component. The method further includes each one of the plurality of D/A channels generating an analog output based on the respective output signal value. The method further includes providing the analog output of each D/A channel to a respective hardware component of the second peripheral system.

In accordance with some embodiments of the inventive disclosure, there is also provided a system that includes a main computing system having a processor, a physical memory, and a bus, the processor used to execute an application program. The physical memory has defined therein a first dedicated memory space and a second dedicated memory space. The system further includes a first peripheral component that is interfaced with the bus of the main computing system and having a local processor, a local memory, and a analog to digital (A/D) converter system that includes a plurality of A/D channels, each one of the plurality of A/D channels configured to receive a respective analog signal from a hardware element of a first peripheral system and produce a signal value that is provided to a respective memory location in the local memory, wherein the local processor is configured to directly write the signal values in the local memory to corresponding memory locations in the first dedicated memory space using direct memory access on an ongoing and asynchronous manner. The system further includes the processor of the main computing system being configured to read the signal values in the first dedicated memory space and generate a plurality of output signal values that are written into respective locations of the second dedicated memory space. The system further includes a second peripheral component that is interfaced with the bus of the main computing system and having a local processor, a local memory, and a digital to analog (D/A) converter system that includes a plurality of D/A channels, the local processor of the second peripheral component configured to directly read from the second dedicated memory space and write the plurality of output signal values into respective locations in the local memory of the second peripheral component, each one of the respective locations in the local memory being associated with a respective one of the plurality of D/A channels, and wherein each one of the plurality of D/A channels produces an analog output having a value proportional to the respective one of the output signal values in the respective one of the memory locations.

Although the invention is illustrated and described herein as embodied in a real-time computing system, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Additionally, well-known elements of exemplary embodiments of the invention will not be described in detail or will be omitted so as not to obscure the relevant details of the invention.

Other features that are considered as characteristic for the invention are set forth in the appended claims. As required, detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which can be embodied in various forms. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one of ordinary skill in the art to variously employ the present invention in virtually any appropriately detailed structure. Further, the terms and phrases used herein are not intended to be limiting; but rather, to provide an understandable description of the invention. While the specification concludes with claims defining the features of the invention that are regarded as novel, it is believed that the invention will be better understood from a consideration of the following description in conjunction with the drawing figures, in which like reference numerals are carried forward. The figures of the drawings are not drawn to scale.

Before the present invention is disclosed and described, it is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. The terms “a” or “an,” as used herein, are defined as one or more than one. The term “plurality,” as used herein, is defined as two or more than two. The term “another,” as used herein, is defined as at least a second or more. The terms “including” and/or “having,” as used herein, are defined as comprising (i.e., open language). The term “coupled,” as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically. The term “providing” is defined herein in its broadest sense, e.g., bringing/coming into physical existence, making available, and/or supplying to someone or something, in whole or in multiple parts at once or over a period of time.

“In the description of the embodiments of the present invention, unless otherwise specified, azimuth or positional relationships indicated by terms such as “up”, “down”, “left”, “right”, “inside”, “outside”, “front”, “back”, “head”, “tail” and so on, are azimuth or positional relationships based on the drawings, which are only to facilitate description of the embodiments of the present invention and simplify the description, but not to indicate or imply that the devices or components must have a specific azimuth, or be constructed or operated in the specific azimuth, which thus cannot be understood as a limitation to the embodiments of the present invention. Furthermore, terms such as “first”, “second”, “third” and so on are only used for descriptive purposes, and cannot be construed as indicating or implying relative importance.

In the description of the embodiments of the present invention, it should be noted that, unless otherwise clearly defined and limited, terms such as “installed”, “coupled”, “connected” should be broadly interpreted, for example, it may be fixedly connected, or may be detachably connected, or integrally connected; it may be mechanically connected, or may be electrically connected; it may be directly connected, or may be indirectly connected via an intermediate medium. As used herein, the terms “about” or “approximately” apply to all numeric values, whether or not explicitly indicated. These terms generally refer to a range of numbers that one of skill in the art would consider equivalent to the recited values (i.e., having the same function or result). In many instances these terms may include numbers that are rounded to the nearest significant figure. In this document, a “program,” “computer program,” or “software application” may include a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, a source code, an object code, a shared library/dynamic load library and/or other sequence of instructions designed for execution on a computer system. Those skilled in the art can understand the specific meanings of the above-mentioned terms in the embodiments of the present invention according to the specific circumstances.

