TECHNICAL FIELD

Embodiments of the present disclosure relates to systems and methods for applying a digital filter as a second tap of a decision feedback equalizer (DFE) in accordance with some embodiments.

BACKGROUND

Conventional high speed serial communication systems include various components that are used by the receiving device to receive, filter, recover, and correct errors and in the data signal from transmitter. Many serial receiver systems perform decision feedback equalization (DFE) on received data. Such serial receiver systems can include (i) an analog front end that provides some continuous time linear equalization (CLTE), (ii) a sampler, (iii) a DFE that uses the quantized received data to adaptively feedback a correction signal, and (iv) a timing recovery unit. The timing recovery unit can use edge samples of the signal to determine if the received timing is early or late (e.g., via phase detection). This information can be forwarded to a digital loop filter which outputs into a phase selector to generate a recovered clock signal. The recovered clock signal is then used to sample the input signal and process the received data.

As high-speed serial communications become faster, it becomes more important to recover the transmitted signal for proper signal processing. To aid in recovery of the transmitted signal at the receiver, decision feedback equalizers are used to correct a current symbol based on levels of previous symbols and to cancel out inter-symbol interference (ISI). Adding multiple tap values (decision points) increases the accuracy of the recovered signal but add additional cost in timing delay and hardware.

