CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims the benefit of priority to China Patent Application No. 202010764568.6, filed on Jul. 31, 2020 in People's Republic of China. The entire content of the above identified application is incorporated herein by reference.

Some references, which may include patents, patent applications and various publications, may be cited and discussed in the description of this disclosure. The citation and/or discussion of such references is provided merely to clarify the description of the present disclosure and is not an admission that any such reference is “prior art” to the disclosure described herein. All references cited and discussed in this specification are incorporated herein by reference in their entireties and to the same extent as if each reference was individually incorporated by reference.

FIELD OF THE DISCLOSURE

The present disclosure relates to an electronic package device and a carrier structure thereof, and more particularly to an electronic package device for transmitting high frequency signals and a carrier structure thereof.

BACKGROUND OF THE DISCLOSURE

In conventional package technologies, a die having a plurality of solder pads is usually disposed on a die paddle of a lead frame having a plurality of signal pins and a plurality of power pins, and then the solder pads of the die are respectively and electrically connected to the signal and power pins of the lead frame by performing a wire bonding process. Afterwards, a molding compound is used such that the die, a plurality of bonding wires, and the lead frame are packaged together to form an electronic package structure, such as a quad flat package (QFP) structure.

When the electronic package structure mounted on a printed circuit board cooperates with the printed circuit board, a current path is formed by the bonding wires for transmitting signals or supplying power, the signal and power pins, and a ground pad, so as to define a loop area. The loop area defined by the current path is in positive correlation with a parasitic inductance. That is to say, the larger the loop area defined by the current path is, the larger the parasitic inductance becomes. However, when the parasitic inductance becomes too large, signal impedance mismatch, power noise, and a decrease of power integrity may occur. Therefore, how the parasitic inductance and the power noise can be reduced whilst improving the power integrity is still one of the issues to be solved in the relevant industry.

SUMMARY OF THE DISCLOSURE

In response to the above-referenced technical inadequacies, the present disclosure provides an electronic package device and a carrier structure thereof, so as to improve power integrity during operation of the electronic package device.

In one aspect, a carrier structure is provided in the present disclosure, and the carrier structure includes a die attach paddle, a ground frame, a pin assembly, and a ground wing portion. The ground frame surrounds the die attach paddle. The pin assembly includes a plurality of pins that are spaced apart from one another. The pins extend radially outward and are arranged to surround the ground frame. The ground wing portion is connected to the ground frame and located in a space under the pin assembly. The ground wing portion includes an extending part and a joint part, the extending part extends away from the die attach paddle, and a top end of the extending part is located at a position above where a bottom surface of the die attach paddle is located.

In certain embodiments, a portion of the plurality of pins is disposed above and across the ground wing portion, and another portion of the plurality of pins does not overlap with the ground wing portion in a vertical direction.

In certain embodiments, each of the pins includes a main portion and a bent portion connected to the main portion. A shortest vertical distance between the main portion of one of the pins disposed above and across the ground wing portion and the extending part of the ground wing portion is less than a pitch between two adjacent ones of the pins.

In certain embodiments, the bent portion of one of the pins disposed above and across the ground wing portion and the extending part of the ground wing portion have a largest horizontal distance therebetween, and the largest horizontal distance is less than a pitch between two adjacent ones of the pins.

In certain embodiments, the carrier structure further includes another ground wing portion. The ground wing portion and the another ground wing portion are respectively located at two different sides of the ground frame. In another embodiment, the ground wing portion and the another ground wing portion are located at a same side of the ground frame and spaced apart from each other.

In certain embodiments, the ground wing portion extends outwardly from the ground frame and completely surrounds the ground frame.

In certain embodiments, the ground frame includes a frame body, at least one first connection element, and at least one second connection element. The at least one first connection element extends downward from the frame body to the die attach paddle, and the at least one second connection element extends upward from the frame body to the ground wing portion.

In certain embodiments, a largest height difference between the extending part and the bottom surface of the die attach paddle is greater than a shortest vertical distance between the extending part and one of the pins.

In another aspect, the present disclosure provides an electronic package device that includes a carrier structure, a chip, a plurality of first conductive wires, a plurality of second conductive wires, and a mold layer. The carrier structure includes a die attach paddle, a ground frame, a pin assembly, and a ground wing portion. The ground frame surrounds the die attach paddle. The pin assembly includes a plurality of pins that are spaced apart from one another. The pins extend radially outward and are arranged to surround the ground frame. The ground wing portion is connected to the ground frame and located in a space under the pin assembly. The ground wing portion includes an extending part and a joint part, the extending part extends away from the die attach paddle, and a top end of the extending part is located at a position above where a bottom surface of the die attach paddle is located. The chip is disposed on the die attach paddle of the carrier structure. The first conductive wires are connected to the chip and the ground frame, and the second conductive wires are connected to the chip and are respectively connected to the pins. The mold layer covers the chip, the first conductive wires, and the second conductive wires, in which the mold layer partially covers the carrier structure, and the joint part of the ground wing portion is not covered and exposed from the mold layer.

In certain embodiments, each of the pins includes a main portion and a bent portion connected to the main portion, and the mold layer covers the main portion of each of the pins and does not cover the bent portion.

In certain embodiments, the bottom surface of the die attach paddle is exposed at one of the surfaces of the mold layer.

Therefore, in the electronic package device and the carrier structure thereof provided by the present disclosure, by virtue of “the ground wing portion being connected to the ground frame and located under the pin assembly, in which the ground wing portion includes the extending part and the joint part,” and “a top end of the extending part is located at a position above where a bottom surface of the die attach paddle is located,” a loop area defined by a current path can be decreased, thereby improving the power integrity.

These and other aspects of the present disclosure will become apparent from the following description of the embodiment taken in conjunction with the following drawings and their captions, although variations and modifications therein may be affected without departing from the spirit and scope of the novel concepts of the disclosure.

