TECHNICAL FIELD

This disclosure relates to non-volatile memory storage systems in solid-state drives or other devices, including but not limited to flash drives or embedded/removable flash packages. More specifically, this disclosure relates to systems and methods for programming non-volatile memory structures.

BACKGROUND

Due to emerging technology and market forces, solid-state drives (SSDs) are steadily replacing previously conventional data storage systems that rely on the rotation of magnetic mediums for reading and writing data (e.g., hard disk drives). Rather than comprising any mechanical or moving parts, solid-state memory comprises integrated circuit assemblies or interconnected flash components to provide non-volatile storage in which stored data can be persistently retained even during a planned or unplanned interruption of power. As a result, a solid-state drive is inherently faster and more robust (i.e., less susceptible to data loss and corruption), as well as consumes less power and is more compact in comparison to disk-based storage. Accordingly, non-volatile memory is a powerful storage solution with respect to many types of computing, consumer electronic, and stand-alone external storage (e.g., USB drives) devices.

With respect to some flash memory types, each individual memory cell comprises a floating gate that is positioned above and isolated from a channel region of a semiconductor substrate, wherein the floating gate is positioned between the source and drain regions. Also, a control gate is provided over and isolated from the floating gate. Accordingly, the threshold voltage (Vth) of the resulting transistor is controlled by and dependent on the amount of charge retained on the floating gate. Specifically, in a switch-like manner, the minimum amount of voltage that must be applied to the control gate before the transistor is activated to permit conduction between its source and drain is determined by the level of charge retained on the floating gate. As a result, bit-value data can be programmed onto and erased from the memory cell by changing the level of charge on a floating gate in order to change the threshold voltage characteristic of the transistor.

As explained in detail below, the number of bits that can be stored in an individual memory cell is dependent upon the number of distinct voltage ranges that may be partitioned within the threshold voltage window of that memory cell. For example, to store one bit of data (referred to as a binary data), the possible threshold voltages (Vth) of the memory cell are divided into two ranges, wherein the ranges are assigned as logical data “1” and “0” respectively. A memory cell of this type of storage density may be referred to as a “single-level cell” or SLC.

By further partitioning the threshold voltage window of a memory cell into additional distinct voltage ranges, multiple levels of information may be stored. Such a memory cell may be referred to as a “multi-state cell.” For example, to store two bits of data, the threshold voltage window of a cell may be partitioned into four distinct voltage ranges (or states), wherein each range is assigned a certain bit value equal to, for example, “11,” “10,” “01,” and “00.” Accordingly, after an erase operation, the threshold voltage is negative and, therefore, may be defined as logic “11.” Therefore, the positive threshold voltages may be used for the states of “10,” “01, “00.” A memory cell of this storage density may be referred to as, for example, a “multi-level cell” or MLC. In another example, to store three bits of data, the voltage threshold window of a cell may be partitioned into eight distinct voltage ranges (or states), wherein each range is assigned a certain bit value that is equal to, for example, “111,” “110,” “100,” “010,” “011,” “000,” “001,” and “101.” A memory cell of this storage density may be referred to, for example, as a “tri-level” or “triple-level cell” (TLC). In a further example, to store four bits of data, the voltage threshold window of a cell may be partitioned into 16 distinct voltage ranges (or states), wherein each range is assigned a certain bit value that is equal to, for example, “1111,” “1110,” “1100,” “1000,” “0111,” “0011,” “0001,” “0000,” “0001,” “1001,” “1101,” “1011,” “0110,” “0100,” “0101,” and “1010.” A memory cell of this storage density may be referred to, for example, as a “quad-level cell” (QLC).

The specific relationship between the data that is programmed into a memory cell and the threshold voltage levels of the memory cell depends upon the data encoding scheme that is adopted for the memory cells.

Thus, a memory device that comprises multi-state data (by incorporating MLC and/or TLC-type and/or QLC-type cells) has an increased storage capacity using the same MOSFET structure and wafer size as an SLC-type cell and, as a result, provides a comparative cost per bit savings. However, as a consequence of the increased density and tightened tolerances between the partitioned voltage ranges of multi-state memory cells, programming operations occur at a slower speed relative to a single-state memory cell because the data is being programmed to multiple target threshold voltage ranges and requires a higher level of precision during programming. As such, the increased density of a multi-state memory cell decreases the actual margin of error between state changes and reduces the available voltage range capacity that is needed to endure the stress on the silicon oxide layer over the successive programming/erase cycles. As a result, the durability of a multi-state storage element is significantly lower in comparison to a single-state memory cell. Thus, it would be beneficial to derive and identify technologies and methodologies that, in one or more programming stages, refine or tighten the threshold voltage ranges of the programmable states of memory cells comprising such higher density memory structures In addition, it would be beneficial to be able to optimize one or more of the programming stages to further improve their efficiency, as well as other performance parameters.

SUMMARY

Various embodiments include a method for programming a non-volatile memory structure with four-page data, wherein the method comprises: in a first stage, selecting four programmable states of a segment of MLC NAND-type cells, programming at least a first of the four programmable states with two pages of a four-page data at a first step voltage level, between programming at least two neighboring programmable states of the four programmable states, increasing the first step voltage level to a second step voltage level for a single program pulse and by a pre-determined magnitude, and programming a latter of the at least two neighboring programmable states at the first step voltage level.

Other embodiments include a memory controller comprising a first port configured to couple to a non-volatile memory structure, wherein the memory structure comprises a memory array. The memory controller is configured to: in a first stage, select four programmable states of a segment of MLC NAND-type cells of the memory array, program at least a first of the four programmable states with two pages of a four-page data at a first step voltage level, between programming at least two neighboring programmable states of the four programmable states, increase the first step voltage level to a second step voltage level for a single program pulse and by a pre-determined magnitude, and program a latter of the at least two neighboring programmable states at the first step voltage level.

Additional embodiments include a non-volatile memory system that is comprised of a memory array, and a memory controller coupled to the memory array and, in a first stage, selecting four programmable states of a segment of MLC NAND-type cells, programming at least a first of the four programmable states with two pages of a four-page data at a first step voltage level, between programming at least two neighboring programmable states of the four programmable states, increasing the first step voltage level to a second step voltage level for a single program pulse and by a pre-determined magnitude, and programming a latter of the at least two neighboring programmable states at the first step voltage level.

