CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 109129393, filed on Aug. 27, 2020. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

TECHNICAL FIELD

The invention relates to a control circuit of a delay lock loop and a control method thereof, and more particularly, to a control circuit of a delay lock loop applied to a memory and a control method thereof.

BACKGROUND

Referring toFIG. 1, in the conventional technical field, when a clock enable signal CKE in a dynamic random access memory is pulled up from a low logic level to a high logic level, the dynamic random access memory may leave a power down mode, and a voltage value of a received operation voltage VINT will drop. When the voltage value of the operation voltage VINT drops, a variation of a clock cycle of a read data DQS provided by the dynamic random access memory will occur, and makes a clock signal CLK asynchronous with transition of the read data DQS. Consequently, if the read data DQS is captured at a time point TS, data reading errors may occur to reduce the reliability.

SUMMARY

The invention provides a control circuit of a delay lock loop and a control method thereof, which can improve the reliability of data reading in the application of memory.

The control circuit of the delay lock loop of the invention includes a power status detector, a voltage comparator, an enable signal generator and a control signal generator. The power status detector receives a clock enable signal, and detects a transition edge of the clock enable signal to generate a trigger signal corresponding to a variation of an operation power. The voltage comparator compares the operation power with a reference voltage to generate a comparison result. The enable signal generator is coupled to the power status detector and the voltage comparator, receives the trigger signal, sets an enable signal to an active state according to the trigger signal, and sets the enable signal to a non-active state according to the comparison result. The control signal generator receives the enable signal and a control clock, and outputs the control clock to generate a control signal when the enable signal is in the active state.

The control method of the delay lock loop of invention includes: detecting a transition edge of a clock enable signal to generate a trigger signal corresponding to a variation of an operation power; comparing the operation power with a reference voltage to generate a comparison result; setting an enable signal to an active state according to the trigger signal, and setting the enable signal to a non-active state according to the comparison result; and outputting a control clock to generate a control signal when the enable signal is in the active state. The control signal is configured to control a locking operation of the delay lock loop to be started or stopped.

Based on the above, with respect to the variation of the operation power, the invention stops the locking operation of the delay lock loop through the generated control signal during a time interval when the operating power supply is unstable, so as to maintain the reliability of data read from the memory.

