FIELD OF EMBODIMENTS OF THE DISCLOSURE

Embodiments of the present disclosure generally relate to methods and systems for serializing and/or deserializing in connection with high speed communications.

BACKGROUND OF THE DISCLOSURE

Certain conventional serializer and deserializer structures utilize a clocked tree approach, with clock speed doubled in each tree level. Accordingly, in a conventional serializer, a first tree level clocks data in a frame rate, and serializes it to 2 times the rate. The next level clocks in data at twice the frame clock, and serializes to 4 times the frame clock using double the clock level of the previous level, and so on, until a final rate is equal to a serializer/deserializer clock rate. Such an approach has various drawbacks. For example, it takes approximately 1 frame cycle (for relatively deep trees) to get a first bit out of the serializer onto the transmission medium, and it takes another frame cycle to get the bit from the transmission medium to the deserializer output. As another example, the serializer tree is limited to 2Nsize (where N is an integer). As one more example, an entire frame to be serialized has to be clocked in to the serializer at the same time.

SUMMARY OF THE DISCLOSURE

A need exists for improved serialization and deserialization.

With those needs in mind, certain embodiments of the present disclosure provide improved serialization and deserialization of data. In various embodiments, a serializer includes a recursive tree of serializer unit cells. Each serializer unit cell includes a multiplexer, a plurality of flip-flops coupled to the multiplexer, and a state machine. The state machine defines operation of the corresponding serializer unit cell. The recursive tree is organized with upper level serializer unit cells disposed more closely to a serializer output than are lower level serializer unit cells. The recursive tree is configured such that each serializer unit cell that is adjacent to and in an upper position relative to a corresponding lower level serializer unit cell directs the corresponding lower level serializer unit cell to output data, and the corresponding lower level serializer unit cell communicates to the corresponding serializer unit cell when the corresponding lower level serializer unit cell is done outputting data.

Certain embodiments of the present disclosure provide a deserializer that includes a recursive tree of deserializer unit cells. Each deserializer unit cell comprises a demultiplexer, a plurality of flip-flops coupled to the demultiplexer, and a state machine. The state machine defines operation of the corresponding deserializer unit cell. The recursive tree is organized with lower level deserializer unit cells disposed more closely to deserializer output registers of a serializer/deserializer link than are upper level deserializer unit cells. The recursive tree is configured such that each deserializer unit cell that is adjacent to and in an upper position relative to a corresponding lower level deserializer unit cell directs the corresponding lower level cell to deserialize data, and the corresponding lower level unit deserializer cell communicates to the corresponding upper level deserializer unit cell when the corresponding lower level unit cell is done deserializing data.

Certain embodiments of the present disclosure provide a serializer/deserializer system that includes a first serializer, a second serializer, a first deserializer, a second deserializer, and a serializer/deserializer link and associated analog electronics. The first serializer and second serializer each include a recursive tree of serializer unit cells, wherein each serializer unit cell includes a multiplexer, a plurality of flip-flops coupled to the multiplexer, and a state machine. The state machine defines operation of the corresponding serializer unit cell. The recursive tree is organized with upper level serializer unit cells disposed more closely to a serializer output than are lower level serializer unit cells. The recursive tree is configured such that each serializer unit cell that is adjacent to and in an upper position relative to a corresponding lower level serializer unit cell directs the corresponding lower level serializer unit cell to output data, and the corresponding lower level serializer unit cell communicates to the corresponding serializer unit cell when the corresponding lower level serializer unit cell is done outputting data. The second deserializer is coupled to the first serializer via the serializer/deserializer link and configured to receive serialized data from the first serializer via the serializer/deserializer link. The first deserializer is coupled to the second serializer via the serializer/deserializer link and configured to receive serialized data from the second serializer via the serializer/deserializer link. The first deserializer and the second deserializer each include a recursive tree of deserializer unit cells. Each deserializer unit cell includes a demultiplexer, a plurality of flip-flops coupled to the demultiplexer, and a state machine. The state machine defines operation of the corresponding deserializer unit cell. The recursive tree is organized with lower level deserializer unit cells disposed more closely to an output register of the serializer/deserializer link than are upper level deserializer unit cells. The recursive tree is configured such that each deserializer unit cell that is adjacent to and in an upper position relative to a corresponding lower level deserializer unit cell directs the corresponding lower level cell to deserialize data, and the corresponding lower level unit deserializer cell communicates to the corresponding deserializer unit cell when the corresponding lower level unit cell is done deserializing data. The first serializer is positioned on a first side of the serializer/deserializer link with the first deserializer, and the second serializer is positioned on a second side of the serializer/deserializer link with the second deserializer.

