BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to analog-to-digital converters (ADCs).

Description of the Related Art

Recently, the number of smart devices and the amount of data transfer are growing at an unprecedented rate. To provide users with a high-quality experience, wireless local area network (WLAN) plays a key role among wireless standards. Wifi 6 enhances spectrum efficiency, increases data rate, and serves more users simultaneously in public areas. To support 1024 Quadrature amplitude modulation (QAM) in a 160 MHz radio frequency (RF) signal bandwidth while retaining sufficient error vector magnitude (EVM), the ADC has to achieve in-band dynamic range (DR) of 63-70 dB over 80-MHz baseband bandwidth. Successive-approximation analog-to-digital converters (SAR ADCs) are used extensively in Wifi applications due to their low power and small footprint. For DR >60 dB, quantization noise and comparator noise become the dominant noise sources. Recently, noise-shaping (NS) SAR ADCs have become popular to increase signal-to-noise ratio (SNR), which considerably reduce these two noise sources.

A basic concept of SAR ADC is described in this paragraph. During an input sampling phase, an input voltage VIis sampled onto a weighted capacitor array (capacitive digital-to-analog converter, abbreviated to CDAC). During an analog-to-digital conversion phase, a successive-approximation scheme is performed. The CDAC is controlled to successively approximate its positive and negative output terminals. A comparator compares the positive and negative output terminals of the CDAC and, accordingly, successively adjusts a set of successive-approximation registers (e.g., a SAR logic). The values of the set of successive-approximation registers are fed back to the CDAC to control the successive-approximation between the positive and negative output terminals of the CDAC. According to a series of comparator outputs generated during the successive approximation, the capacitors within the CDAC are switched between several reference voltages to equalize the voltage levels at the positive and negative output terminals of the CDAC, and the digital representation of the input voltage VIis determined from the MSB (most significant bit) to the LSB (least significant bit) of the set of successive-approximation registers.

However, a residue voltage VR may still exist between the positive and negative output terminals of the CDAC after the successive approximation. A noise-shaping signal may be derived from the residue voltage VR for noise elimination. The comparator of the SAR ADC usually provides an additional differential input pair for subtraction of the noise-shaping signal. The additional differential input pair, however, may contribute extra thermal and kickback noise. Furthermore, the generation of the noise-shaping signal may involve an active residue amplification (using an op amp), which consumes a lot of power.

An efficient, low power, small area, high-speed, and wide bandwidth NS-SAR ADC is called for.

BRIEF SUMMARY OF THE INVENTION

A fully passive, time-interleaved (TI) noise-shaping successive-approximation analog-to-digital converter (NS-SAR ADC) is shown, which employs a passive (without an op amp) signal-residue summation technique and 2-way time-interleaving. The signal bandwidth is doubled while keeping the same dynamic range (DR) and figure-of-merit (FoM) versus a single-channel counterpart. A shared fine comparator reduces interleaving spurs.

A TI NS-SAR ADC in accordance with an exemplary embodiment of the present invention includes a first successive-approximation (SAR) channel, a second successive-approximation channel, a fine comparator, and a noise-shaping circuit. The first successive-approximation channel has a first set of successive-approximation registers (e.g. SAR logic), and a first coarse comparator operative to coarsely adjust the first set of successive-approximation registers. The second successive-approximation channel has a second set of successive-approximation registers (e.g. another SAR logic), and a second coarse comparator operative to coarsely adjust the second set of successive-approximation registers. The fine comparator is operative to finely adjust the first set of successive-approximation registers and the second set of successive-approximation registers alternately. The noise-shaping circuit samples residues of the first successive-approximation channel for the fine comparator to finely adjust the second set of successive-approximation registers, and samples residues of the second successive-approximation channel for the fine comparator to finely adjust the first set of successive-approximation registers.

In an exemplary embodiment, the noise-shaping circuit performs residue sampling using back-to-back capacitors, and integrates residues by charge sharing for signal-residue summation at the input side of the fine comparator.

In an exemplary embodiment, the first coarse comparator sets the first set of successive-approximation registers in a first phase, and the fine comparator sets the first set of successive-approximation registers in a second phase. The first phase is prior to the second phase.

In an exemplary embodiment, the second coarse comparator sets the second set of successive-approximation registers in the second phase, and the fine comparator sets the second set of successive-approximation registers in a third phase. The second phase is prior to the third phase.

In an exemplary embodiment, the first coarse comparator sets the first set of successive-approximation registers in the third phase, and the fine comparator sets the first set of successive-approximation registers in a fourth phase. The third phase is prior to the fourth phase.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

