CROSS-REFERENCE TO RELATED APPLICATION

This patent application is a U.S. National Phase Application under 35 U.S.C. § 371 of International Application No. PCT/US2017/069136, filed Dec. 30, 2017, entitled “GALVANIC CORROSION PROTECTION FOR SEMICONDUCTOR PACKAGES,” which designates the United States of America, the entire disclosure of which is hereby incorporated by reference in its entirety and for all purposes.

FIELD

Embodiments generally relate to semiconductor packages. More specifically, embodiments relate to techniques of reducing or eliminating galvanic corrosion that may occur during formation of a semiconductor package.

BACKGROUND INFORMATION

At least one technique of forming a semiconductor package (e.g., packages with cores, packages without cores, packages with embedded components, packages without embedded components, etc.) may involve providing a permanent or temporary package core, and subsequently fabricating one or more build-up layers, dielectric materials, and electrical connections (e.g., vias, contact pads, traces, etc.) over the package core. During package formation, one or more semiconductor components (e.g., semiconductor die, wireless transceivers, bridge dies, etc.) can be assembled on or embedded within one or more layers (e.g., build-up layers, etc) and coupled or connected to each other using interconnect layers. The interconnect layers may include: (i) one or more metal vias; (ii) one or more metal lines (e.g., metal traces, contact pads, etc.); and (iii) one or more interconnect structures (e.g., bumps, pillars, etc.). For example, contact pads of a first semiconductor die can be coupled to contact pads associated with one or more components on a second semiconductor die (e.g., die-side capacitors (DSCs), host fabric interfaces (HFIs), etc.) using an interconnect structure (e.g., a conductive metal bump, a conductive metal pillar, etc.). For this example, the contact pad(s) of the first die, the contact pad(s) of the second component, and the interconnect structure may experience galvanic corrosion because at least two or more of the contact pad(s) of the first die, the contact pad(s) of the second component, and the interconnect structure may be made from dissimilar metals.

Galvanic corrosion is an electrochemical process in which one metal corrodes preferentially when it is in electrical contact with another, different metal in the presence of an electrolyte. Galvanic corrosion may cause electrical connections between the semiconductor components and/or electrical couplings to fail or become faulty. Galvanic corrosion can be caused by a chemical potential difference between a first semiconductor component or electrical coupling (e.g., a Cu pad covered with a NiPdAu finish, etc.) and a second semiconductor component or electrical coupling (e.g., a Cu bump, etc.). This chemical potential difference can result from differences in sizes of the surface areas of the first and second components or electrical couplings. Additionally, galvanic corrosion can occur when electrical couplings (e.g., interconnect structures, etc.) are missing or over-etched during an etching process used to remove a seed layer. Galvanic corrosion can also be created or exacerbated by use of a strong oxidizer (e.g., hydrogen peroxide, etc.) during package formation.

For a non-limiting example that involves embedded semiconductor components, package formation may include a build layer comprising a power plane, a cavity formed in the build-up layer(s) to expose the power plane, and a conductive adhesive disposed on top of the power plane. For this example, after deposition of the conductive adhesive, a bridge die may be placed within the cavity, and another build-up layer may be fabricated over the bridge die and the previously created build-up layers such that the bridge die is embedded within the build-up layers. After the bridge die is embedded, one or more semiconductor dies may be assembled over the build-up layers. The semiconductor dies may then be encapsulated in a molding compound to form a semiconductor package.

One type of bridge die is an embedded multi-die interconnect bridge (EMIB) developed by Intel Corporation. INTEL and EMIB may be trademarks of Intel Corporation. The bridge die may include: (i) a bulk portion that is in contact with the power plane via the conductive adhesive; and (ii) one or more interconnect layers fabricated on top of the bulk portion. The interconnect layers may include metal vias for connecting the power plane and the bridge die. Furthermore, the interconnect layers may also include one or more metal lines (e.g., metal traces, contact pads, etc.) that enable electrical couplings between the bridge die and the one or more semiconductor dies that are assembled over the build-up layers.

The electrical couplings between the bridge die and the semiconductor dies are achieved by coupling contacts contact pads of the bridge die with contact pads of the semiconductor dies. For example, contact pads of the bridge die can be electrically coupled to contact pads associated with one or more components on the semiconductor die (e.g., die-side capacitors (DSCs), host fabric interfaces (HFIs), etc.). Contact pads of the bridge die can be made of metal, such as copper (Cu), and covered with a surface finish, such as a Nickel-Palladium-Gold (NiPdAu) finish.

In at least one semiconductor package that includes a bridge die (e.g., an EMIB, etc.), contact pads of the bridge die may be electrically and mechanically coupled to contact pads of semiconductor dies via an interconnect structure. Examples of such interconnect structures include, but are not limited to, Cu bumps, any type of low-lead or lead-free solder bumps, tin-copper bumps, Cu pillars, micro bumps, and combinations thereof, or the like.

One problem that may occur during coupling of the contact pads of the bridge die to the contact pads of semiconductor dies via an interconnect structure is galvanic corrosion, which is explained above.

