FIELD OF THE INVENTION

The present disclosure relates to semiconductor structures and, more particularly, to asymmetric source and drain structures and methods of manufacture.

BACKGROUND

Many advances have been achieved within integrated circuit transistors by forming the transistors to be asymmetric. For example, with asymmetric transistors, both series resistance in the source region and gate to drain capacitance are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate can be tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and to simultaneously minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).

However, as scaling of devices continue, e.g., as critical dimensions of devices shrink, it is becoming ever more difficult to manufacture asymmetric transistors while gaining benefits. For example, with known processes, devices show significant gate-induced drain leakage (GIDL) current at Vd=−4V. Id@Vg=Vs=Vb=0 is up to 10 nA for some devices. This prevents from working at Vd=4V to meet leakage specification 1 nA/4Fin.

SUMMARY

In an aspect of the disclosure, a structure comprises: at least one gate structure; a straight spacer adjacent to the at least one gate structure; and an L-shaped spacer on a side of the at least one gate structure opposing the straight spacer, the L-shaped spacer extending a first diffusion region further away from the at least one gate structure than the straight spacer extends a second diffusion region on a second side away from the at least one gate structure.

In an aspect of the disclosure, a structure comprising: a plurality of gate structures over a substrate; a first diffusion region between adjacent gate structures of the plurality of gate structures; a second diffusion region on opposing sides of the first diffusion region for each of the plurality of gate structures; L-shaped spacers on sidewalls of the adjacent gate structures, adjacent to the first diffusion region; and straight spacers on sidewalls of the adjacent gate structures, on opposing sides of the first diffusion region.

In an aspect of the disclosure, a structure comprising: a first epitaxial region at a first diffusion side only side of a gate structure, spaced away from the drain side by an L-shape spacer at first diffusion side only; and a second epitaxial region at a second diffusion side only side of the gate structure, spaced away from the second diffusion side by a straight spacer at the second diffusion side only.

