CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2020-0097658 filed on Aug. 4, 2020 in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Embodiments of the disclosure generally relate to a semiconductor device, and more particularly, to a semiconductor device capable of performing an auto-precharge operation.

2. Related Art

As semiconductor devices increasingly operate at higher speeds, the semiconductor devices adopt a scheme of performing an auto-precharge operation instead of a scheme of performing a precharge operation by receiving a separate precharge command after a write operation is performed. The auto-precharge operation is performed in such a way to be automatically performed without receiving a separate command after the write operation is performed.

SUMMARY

In an embodiment, a semiconductor device may include: an operation flag generation circuit configured to generate an operation flag at a time when a flag period elapses from a time when an internal setting signal is generated to perform a write operation accompanied by an auto-precharge operation; and an auto-precharge pulse generation circuit configured to generate an auto-precharge pulse by shifting the operation flag by a pulse generation period set by a period code based on divided clocks generated by dividing an internal clock.

In an embodiment, a semiconductor device may include: a shifting control signal generation circuit configured to generate a quotient code and a remainder code based on a pulse generation period; a pre-shifting circuit configured to generate a shifting operation flag by shifting an operation flag by a pre-shifting period set based on the remainder code, in synchronization with a first divided clock; and a shifting circuit configured to generate an auto-precharge pulse by shifting the shifting operation flag by a shifting period set based on the quotient code, in synchronization with a third divided clock.

