BACKGROUND

1. Technical Field

Various embodiments may generally relate to a semiconductor circuit, and more particularly, to a skew compensation circuit and a semiconductor apparatus including the same.

2. Related Art

As the operation speed is increased, semiconductor apparatuses need to more strictly obey fixed operation standards to ensure stable operation reliability.

However, it is difficult for the semiconductor apparatuses to obey specifications according to PVT (power, voltage, and temperature) variations as the degree of integration is increased.

Accordingly, there is a need for improvement in the operation reliability of semiconductor apparatuses by compensating skews of signals related to internal operations according to the PVT variations.

SUMMARY

Various embodiments are provided of a skew compensation circuit capable of compensating skews of signals related to internal operations in a semiconductor apparatus and a semiconductor apparatus including the same.

In an embodiment of the present disclosure, a skew compensation circuit may include: a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus; a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages; a variable delay circuit configured to generate a compensation signal by delaying an input signal for a delay time varied according to the skew compensation signal; and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.

In an embodiment of the present disclosure, a skew compensation circuit may include: a rectifier configured to generate a rectified voltage of which a variation in an external voltage is compensated for by rectifying the external voltage; a skew detection circuit configured to generate a first skew detection signal and a second skew detection signal using the rectified voltage by detecting threshold voltage characteristics of an NMOS transistor and a PMOS transistor; a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the first and second skew detection signals and a plurality of reference voltages; a variable delay circuit configured to generate a compensation signal by delaying an input signal for a delay time varied according to the skew compensation signal; and a reference voltage generation circuit configured to select partially divided voltages corresponding to a current temperature among a plurality of divided voltages generated using the rectified voltage and output the selected divided voltages as the plurality of reference voltages.

In an embodiment of the present disclosure, a semiconductor apparatus may include: a delay-locked loop circuit configured to generate a delay-locked clock signal using a replica circuit in which an internal delay time of the semiconductor apparatus is modeled; and a skew compensation circuit configured to generate a compensation signal by compensating a delay time offset of the delay-locked loop clock signal according to a detection result of a skew characteristic of a basic logic element constituting the semiconductor apparatus.

In an embodiment of the present disclosure, a semiconductor apparatus may include: an input buffer configured to generate an output signal by buffering an input signal and control a sink current amount according to a skew compensation signal; and a skew compensation circuit configured to generate the skew compensation signal according to a detection result of a skew characteristic of a basic logic element constituting the semiconductor apparatus.

These and other features, aspects, and embodiments are described below in the section entitled “DETAILED DESCRIPTION”.

