CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application Number 10-2019-0137846, filed on Oct. 31, 2019, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

BACKGROUND

Field of Invention

The present disclosure relates to an electronic device, and more particularly, to a memory controller and a method of operating the same.

Description of Related Art

A storage device is a device that stores data under the control of a host device such as a computer, a smart phone, or a smart pad. The storage device includes a device that stores data in a magnetic disk, such as a hard disk drive (HDD), a device that stores data in a semiconductor memory, such as a solid state drive (SSD) or a memory card. The semiconductor memory may include a non-volatile memory.

The storage device may include a memory device in which data is stored and a memory controller that stores data in the memory device. The memory device may be classified into a volatile memory and a non-volatile memory. Here, the non-volatile memory includes a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EPM), a flash memory, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), and the like.

SUMMARY

An embodiment of the present disclosure provides a memory controller and a method of operating the same, capable of selecting map data to be transmitted to a host by increasing or decreasing an activation count corresponding to an index to which a logical block address belongs in a host-aware performance booster (HPB) mode.

A memory controller according to an embodiment of the present disclosure includes an address counter configured to count a number of times a logical block address corresponding to a request is received based on the request received from a host, and output an activation signal indicating that an index to which the logical block address belongs is an activation index when an activation count corresponding to the index is equal to or greater than a preset reference value, the activation count being generated based on a counting result and a map data selector configured to select map data to be output to the host based on the activation signal, wherein the address counter decreases the activation count by a preset size when a size of the selected map data exceeds a storage capacity of the host allocated for storing map data.

A method of operating a memory controller according to an embodiment of the present disclosure may include receiving a request and a logical block address corresponding to the request from a host, counting a number of times the logical block address is received based on the request received from the host, and generating an activation count based on a counting result, outputting a first activation signal indicating that an index to which the logical block address belongs is an activation index when the activation count is equal to or greater than a preset reference value, selecting map data to be output to the host based on the first activation signal, detecting a deactivation index corresponding to an activation count that is less than the preset reference value when a size of the selected map data exceeds a storage capacity of the host allocated for storing map data, outputting a second activation signal based on the deactivation index and decreasing activation counts of indices when a size of map data selected based on the second activation signal exceeds the storage capacity of the host.

According to the present technology, when a host memory is in a saturation state, the activation count corresponding to the index to which the logical block address belongs may be decreased by a preset size, and the map data to be transmitted to the host again may be selected in a state in which the activation count is decreased.

