CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Patent Application No. 10-2019-0058311, filed on May 17, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

Inventive concepts relate to an integrated circuit device and/or a method of fabricating the same, and more particularly, to an integrated circuit device including a nonvolatile vertical memory device and/or a method of fabricating the same.

As information communication apparatuses become more multifunctional, there is a desire and/or a need for increased capacity and integration of integrated circuit devices including memory devices. With the reduction of the size of memory cells for higher integration, the operation circuits and wiring structures which are included in memory devices for operation and electrical connection of memory devices are becoming more complex. Accordingly, there is a desire and/or a need for an integrated circuit device including a memory device having improved electrical characteristics while improving the degree of integration.

SUMMARY

Inventive concepts provide an integrated circuit device and a method of fabricating the same, wherein in a vertical memory device, even when the number of word lines stacked is increased to obtain a higher degree of integration, and the number of contacts connected to the word lines and the number of interconnections are increased, the area the memory device occupies is reduced, and thus the area of a chip is reduced. This may enable a higher level of chip fabrication and/or a higher yield. Further, the degree of freedom of interconnection arrangement is improved, and even when the number of word lines stacked is increased, a simplified process may be performed without an increase in the difficulty of a process for contact formation.

According to some example embodiments of inventive concepts, there is provided an integrated circuit device comprising a substrate including a memory cell region and a connection region, a lower memory stack including a plurality of lower word lines on the memory cell region and the connection region of the substrate, the plurality of lower word lines extending in a horizontal direction parallel to a main surface of the substrate, the plurality of lower word lines overlapping each other in a vertical direction, an upper memory stack on the lower memory stack, the upper memory stack comprising a plurality of upper word lines overlapping each other in the vertical direction, at least one first lower interconnection layer on the connection region at a first vertical level between the lower memory stack and the upper memory stack, the at least one first lower interconnection layer extending in the horizontal direction, and configured to electrically connect to at least one lower word line selected from the plurality of lower word lines, a separate insulating film covering the at least one first lower interconnection layer such that an upper surface of the at least one first lower interconnection layer does not contact other conductors on the connection region, and at least one first upper interconnection layer on the connection region at a second vertical level higher than that of the upper memory stack, the at least one first upper interconnection layer extending, in the horizontal direction, the at least one first upper interconnection layer configured to be electrically connected to at least one upper word line selected from the plurality of upper word lines.

According to some example embodiments of inventive concepts, there is provided an integrated circuit device comprising a substrate including a memory cell region and a connection region, a peripheral circuit region spaced apart from the memory cell region and including a plurality of circuits, a lower memory stack including (i) a plurality of lower word lines on the memory cell region extending in a horizontal direction parallel to a main surface of the substrate, the plurality of lower word lines overlapping each other in a vertical direction, and (ii) a plurality of lower pad regions connected to the plurality of lower word lines and corresponding to a stepped lower connection portion on the connection region, an upper memory stack located above the lower memory stack on the memory cell region and including (i) a plurality of upper word lines extending in the horizontal direction and overlapping each other in the vertical direction, and (ii) a plurality of upper pad regions connected to the plurality of upper word lines and corresponding to a stepped upper connection portion on the connection region, a lower insulating film on the connection region, the lower insulating film covering the stepped lower connection portion, a plurality of lower contact plugs extending through the lower insulating film from the plurality of lower pad regions to a first vertical level, the first vertical level lower than the upper memory stack, and a plurality of first lower interconnection layers between the lower memory stack and the upper memory stack. At least one first lower interconnection layer selected from the plurality of first lower interconnection layers includes (i) a first local portion connected to at least one of the plurality of lower contact plugs and (ii) a second local portion connected to at least one of the plurality of circuits.

According to some example embodiments of inventive concepts, there is provided an integrated circuit device comprising a first substrate including a memory cell region and a connection region, a lower memory stack including (i) a plurality of lower word lines extending in a horizontal direction parallel to a main surface of the first substrate on the memory cell region, the plurality of lower word lines overlapping each other in a vertical direction, and (ii) a plurality of lower pad regions on the connection region, the plurality of lower pad regions connected to the plurality of lower word lines, and an upper memory stack on the lower memory stack, the upper memory stack including (i) a plurality of upper word lines on the memory cell region and overlapping each other in the vertical direction, and (ii) a plurality of upper pad regions connected to the plurality of upper word lines and located on the connection region. At least one first lower interconnection layer extends in the horizontal direction at a first vertical level between the lower memory stack and the upper memory stack on the connection region, at least one lower contact plug connects between at least one lower pad region selected from the plurality of lower pad regions and the at least one first lower interconnection layer, and a separate insulating film covers the at least one first lower interconnection layer such that an upper surface of the at least one first lower interconnection layer does not contact other conductors on the connection region.

According to some example embodiments of inventive concepts, there is provided a method of fabricating an integrated circuit device, the method comprising preparing a substrate, forming a lower memory stack including (i) a plurality of lower word lines extending in a horizontal direction parallel to a main surface of the substrate and overlapping each other in a vertical direction on the substrate, and (ii) a plurality of lower pad regions connected to the plurality of lower word lines, forming a plurality of lower contact plugs including a plurality of first lower contact plugs connected to a plurality of first lower pad regions selected from the plurality of lower pad regions, forming, on the substrate, a plurality of lower interconnection layers including a plurality of first lower interconnection layers extending in the horizontal direction at a first vertical level which is higher than the lower memory stack, the first lower interconnection layers connected to the plurality of first lower contact plugs, forming a separate insulating film on the plurality of lower interconnection layers, the separate insulating film covering the plurality of lower interconnection layers, forming an upper memory stack spaced apart from the lower memory stack in the vertical direction with the separate insulating film therebetween, the upper memory stack including (i) a plurality of upper word lines overlapping each other in the vertical direction, and (ii) a plurality of upper pad regions connected to the plurality of upper word lines, forming a plurality of upper contact plugs including a plurality of first upper contact plugs connected to the plurality of upper pad regions, and forming a plurality of upper interconnection layers extending in the horizontal direction at a second vertical level higher than the first vertical level, the plurality of upper interconnection layers connected to the plurality of lower contact plugs.

According to some example embodiments of inventive concepts, there is provided a method of fabricating an integrated circuit device, the method comprising: forming a lower memory stack on a substrate, the lower memory stack including (i) a plurality of lower word lines extending in a horizontal direction parallel to a main surface of the substrate and overlapping each other in a vertical direction, and (ii) a plurality of lower pad regions connected to the plurality of lower word lines, forming a plurality of lower contact plugs on the substrate, the plurality of lower contact plugs connected to the plurality of lower pad regions, forming, on the substrate, a plurality of lower interconnection layers extending in the horizontal direction at a first vertical level higher than the lower memory stack, and connected to the plurality of lower contact plugs, forming a separate insulating film covering the lower memory stack and the lower interconnection layers on the substrate, forming an upper memory stack including (i) a plurality of upper word lines on a bonding substrate, the plurality of upper word lines overlapping each other in the vertical direction, and (ii) a plurality of upper pad regions connected to the plurality of upper word lines, forming a plurality of upper contact plugs on the bonding substrate, the plurality of upper contact plugs connected to the plurality of upper pad regions, forming, on the bonding substrate, a plurality of upper interconnection layers extending in the horizontal direction at a second vertical level higher than the upper memory stack, and connected to the plurality of upper contact plugs, and bonding the separate insulating film and the bonding substrate to allow the lower memory stack and the upper memory stack to face each other with the bonding substrate therebetween.

