BACKGROUND

Description of the Related Art

A processor pipeline includes many different units which operate on instructions being executed. These units include a decode unit, scheduler queues, pickers, and execution units. The decode unit decodes fetched instructions into instruction operations. Instruction operations are also referred to as “ops” herein. Generally speaking, an op is an operation that the hardware included in the execution units is capable of executing. In various implementations, each instruction translates to one or more ops which, when executed, result in the performance of the operations defined for that instruction according to an instruction set architecture.

Pickers select ops out of the scheduler queues to be executed by the execution units. In various clock cycles, not enough ops are available to execute on all of the execution units. In other cycles, too many ops are ready that are not all able to be executed by the execution units. Accordingly, techniques for improving the utilization and/or throughput of execution units are desired.

