BACKGROUND

The improvement in integration density of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) in integrated circuits (IC) has come from shrinking the semiconductor process node, which entails reductions in operating voltage and current consumption of electronic circuits developed in the semiconductor process node. Accordingly, access speed of memory integrated circuits is expected to become faster. For example, some memories have a very small read window, which requires a low-offset sense amplifier for a successful read operation.

A mismatch or offset between components often exists in a sense amplifier circuit due to unavoidable process variations. According to an existing method, a sense amplifier undergoes an offset sampling or cancelling stage before an actual read operation to cancel out the mismatch of the sense amplifier circuit. In addition, the offset-compensation sense amplifiers cannot cancel the variations of reference cells, which are usually used in a read path design and suffer process variations.

