BACKGROUND

The present disclosure relates to managing parity data, and more specifically to managing parity data associated with commands to, and indications from, configuration registers associated with various data transfer protocols.

Data transfer protocols such as Peripheral Component Interconnect (PCI) or Open Coherent Accelerator Processor Interface (OpenCAPI) can specify a set of configuration registers. These configuration registers can provide a variety of functions including storing the ID of a device and/or the ID of the device vendor, and defining the range of addresses owned by the device within a memory space. Since this set of configuration registers is standard, many design houses market Intellectual Property (IP) which implements these configuration registers. Accordingly, this IP can be simply inserted into an integrated circuit (IC) or chip design which uses a data transfer protocol. This design practice can be popular, for example, when designing a chip design from an Field Programmable Gate Array (FPGA).

A problem with this solution is that since such IP is typically targeted for FPGA designs, IC design houses may not provide parity protection for the configuration registers in the IP. This can be done to reduce the IP cost and reduce the amount of logic, wiring and space taken up by the IP inside the FPGA. This in turn can reduce the overall FPGA project cost and can enable a faster time-to-market. Application-specific integrated circuit (ASIC) designs, particularly ones for enterprise applications, can require parity protection over configuration registers. As a result, when integrating configuration register IP, ASIC designs must implement their own parity protection.

A possible solution to this problem is to check parity over write data for a register update, update the register according to the write data and subsequently discard the accompanying parity. During a read operation, new parity can be generated from the read data when the register value is retrieved. Both the register value and generated parity can then be returned as part of the read indication. A problem with this solution is that, should a latch in a configuration register flip its value between the time it is updated by a write operation and the time it is read back, incorrect data, with parity corresponding to the incorrect data, will be read back without any indication that the latch flip occurred. This is because the parity for the read operation is generated based on the current register value at the time of the read operation which will have occurred after the latch flip.

SUMMARY

Embodiments can be directed towards a computer-implemented method for managing parity data associated with commands to, and indications from, a configuration register. The configuration register can include a first command first-in, first-out (FIFO) for receiving commands and a response FIFO for returning indications. The method includes tracking commands to the configuration register by storing the commands in a second command FIFO and dequeueing a command from the second command FIFO, in response to an indication from the configuration register of a command emerging from the response FIFO. The method also includes generating parity data from the data associated with a write operation and storing the generated parity data in a parity latch corresponding to the configuration register, in response to an indication that the dequeued command is a successfully completed write operation. The method also includes reading, in response to the indication, the generated parity data from a parity latch corresponding to the configuration register and providing the generated parity data for return with the indication that the dequeued command is a successfully completed write operation.

Embodiments can also be directed towards an apparatus for managing parity data associated with commands to, and indications from, a configuration register. The configuration register can have a first command FIFO for receiving commands and a response FIFO for returning indications. The apparatus can include a second command FIFO configured to track commands to the configuration register by storing the commands and a parity latch corresponding to the configuration register configured to store generated parity data. The apparatus can also include an engine control. The engine control can be configured to track commands to the configuration register by storing the commands in a second command FIFO and dequeue a command from the second command FIFO, in response to an indication from the configuration register of a command emerging from the response FIFO. The engine control can also be configured to generate parity data from the data associated with a write operation and store the generated parity data in a parity latch corresponding to the configuration register, in response to an indication that the dequeued command is a successfully completed write operation. The engine control can also be configured to read, in response to the indication, the generated parity data from a parity latch corresponding to the configuration register and provide the generated parity for return with the indication that the dequeued command is a successfully completed write operation.

Embodiments can also be directed towards a computer program product for managing parity data associated with commands to, and indications from, a configuration register. The configuration register can have a first command FIFO for receiving commands and a response FIFO for returning indications. The computer program product can include a computer-readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to track commands to the configuration register by storing the commands in a second command FIFO and dequeue a command from the second command FIFO, in response to an indication from the configuration register of a command emerging from the response FIFO. The program instructions are also executable to cause the computer to generate parity data from the data associated with a write operation and store the generated parity data in a parity latch corresponding to the configuration register, in response to an indication that the dequeued command is a successfully completed write operation. The program instructions are also executable to cause the computer to read, in response to the indication, the generated parity data from a parity latch corresponding to the configuration register and provide the generated parity for return with the indication that the dequeued command is a successfully completed write operation.

The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure.

