BACKGROUND

1. Field

This disclosure relates generally to clock trees for integrated circuits, and more specifically to hierarchical clock tree implementation.

2. Related Art

Hierarchical design is widely used in very large scale integration (VLSI) to design highly complex integrated circuits (ICs). Hierarchical design generally involves breaking a complex design into smaller physical blocks which may be easier to design individually, and then combining the blocks into a larger overall design. The blocks in hierarchical design are generally arranged in either a channel-based design or an abutted design. In a channel-based design, the blocks are separated by channels through which clock and other signals are distributed to the blocks. In abutted or channel-less design, the blocks are placed next to each other with no space between them.

Clock trees are used to distribute clock signals throughout integrated circuits. Clock trees are designed through a process that seeks to minimize latency, which is the delay from a root clock to a point of usage, and skew, which is the difference between the arrival time of a clock transition at different points on the integrated circuit. During the design process, many parameters of a clock tree are typically adjusted through multiple iterations to meet the timing requirements and constraints for the clock tree. When the goals for the timing requirements and constraints have been satisfied, the design is said to have achieved timing closure. VLSI design is performed on industry standard electronic design automation (EDA) tools which typically have automated workflows for many of the routine tasks performed by a designer. However, industry standard EDA tools do not have methodologies or workflows for efficient hierarchical clock implementation, especially for abutted designs.

SUMMARY

A method of constructing a hierarchical clock tree for an integrated circuit may include constructing a clock distribution network on a first level, pushing the clock distribution network to a second level, implementing partition clock trees in partitions on the second level, and calculating combined timing of the clock distribution network and the partition clock trees on the second level. Implementing the partition clock trees may include constructing the partition clock trees in the partitions on the second level, calculating trial timing for the partition clock trees, calculating target timing constraints for the partition clock trees based on timing of the clock distribution network and the trial timing for the partition clock trees, and adjusting the timing of one or more of the partition clock trees based on the target constraints. Calculating the combined timing of the clock distribution network and the partition clock trees on the second level may include merging the partition clock trees. The method may further include adjusting the timing of one or more of the partition clock trees on the second level. The timing of one or more of the partition clock trees on the second level may be adjusted through engineering change orders (ECO). The timing of one or more of the partition clock trees may be adjusted by adjusting one or more target constraints for the one or more of the partition clock trees on the second level. The method may further include determining that timing goals are not met by adjusting the timing of one or more of the partition clock trees, and/or adjusting the clock tree distribution network. The method may further include balancing the clock distribution network in parallel with balancing one or more of the partition clock trees. The method may further include pushing the clock distribution network to a third level, and implementing partition clock trees in partitions on the third level. The clock distribution network may be pushed into one or more of the partitions on the second level. The second level may include a block level. The second level may be lower than the first level.

A method of constructing a hierarchical clock tree for an integrated circuit may include constructing a clock distribution network at a first level, pushing the clock distribution network to partitions at a second level, calculating trial timing for the partitions at the second level, calculating combined timing of the clock distribution network and the trial timing for the partitions at the second level, calculating partition-level target constraints based on the combined timing of the clock distribution network and the trial timing for the partitions at the second level, and calculating revised timing at the partition level based on the target constraints. The method may further include merging the partitions at the partition level, calculating revised combined timing of the clock distribution network and the revised timing for the partitions at the second level, and checking if the revised combined timing meets design goals. The method may further include balancing the hierarchical clock tree by adjusting the revised timing for the partitions at the second level. The timing at the second level may be adjusted through engineering change orders (EGO). The timing at the second level may be adjusted by adjusting the target constraints at the second level. The timing may include latency. The timing may include skew. The partitions may include abutted blocks. The second level may include channel-based blocks. The partitions may include multiple instantiated modules (MIMs). A dependency between the clock distribution network and the partitions on the second level may be decoupled. The method may further include balancing the clock distribution network and the partitions at the second level in parallel.

A method of constructing a clock tree for an integrated circuit may include constructing a top-level clock distribution network, calculating distribution delays to endpoints of the clock distribution network, pushing the top-level clock distribution network down to a block level, constructing clock trees in blocks at the endpoints, calculating block-level insertion delays for the clock trees in blocks at the endpoints, combining the distribution delays with the block-level insertion delays to calculate clock tree insertion delays from a root of the top-level clock distribution network, calculating delay target constraints for the blocks based on the clock tree insertion delays from the root of the top-level clock distribution network, re-calculating block-level insertion delays based on the delay target constraints, merging the clock trees at the block level, and re-calculating the clock tree insertion delays from the root of the top-level clock distribution network. The method may further include checking if the re-calculated clock tree insertion delays from the root of the top-level clock distribution network meet design goals.

The method may further include determining that the insertion delays from the root of the top-level clock distribution network do not meet design goals, and changing clock cells on the clock tree using engineering change orders (EGO). The method may further include determining that the insertion delays from the root of the top-level clock distribution network do not meet design goals, and re-calculating the delay target constraints for the blocks. Pushing the top-level clock distribution network down to the block level may include creating ECO files for sub-blocks. Pushing the top-level clock distribution network down to the block level may include creating configuration files for sub-blocks. The method may further include determining that a sub-block floorplan changed to push the top-level clock distribution network down to a block level, and modifying the top-level clock distribution network structure at the block level to preserve the distribution delays to endpoints of the clock distribution network.

