CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-038055, filed on Mar. 5, 2020; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments of the present invention described herein relate generally to a semiconductor package.

BACKGROUND

As a semiconductor package, there is a surface mount type package that meets the demand for miniaturization. In the surface mount type package, each electrode of the package is mounted on a printed board or the like at the bottom face of the package, so the area necessary for mounting can be reduced.

However, the electrode to be surface-mounted in this way has a relatively large mounting surface, and gas bubbles may remain inside the solder that fixes the electrode at the mounting surface.

