BACKGROUND

1. Technical Field

The inventive concepts relates to an integrated circuit, and more particularly, to an integrated circuit including at least one standard cell and a standard cell library storing information about the at least one standard cell.

2. Description of the Related Art

Due to development of semiconductor process technology, transistor size has been reduced, and a large number of transistors are integrated into a semiconductor device. For example, a system-on-chip (SOC), which refers to an integrated circuit (IC) in which all components of a computer or other electronic systems are integrated into a single chip, is widely used in various applications, and as performance of the applications is improved, a semiconductor device including a larger number of components is desired.

SUMMARY

At leas one of the inventive concepts provides an integrated circuit including at least one standard cell, from which an asymmetric gate structure which can be downscaled may be implemented.

At least one of the inventive concepts provides a standard cell library storing information about the at least one standard cell.

According to an aspect of the inventive concepts, there is provided an integrated circuit including at least one cell. The at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first active region and the second active region; at least one first active fin disposed in the first active region and extending in a first direction; at least one second active fin extending in the first direction over the entire length of the second active region; and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

The at least one cell may be defined by a cell boundary having a first width in the first direction and a first height in the second direction, wherein the at least one second active fin vertically overlaps the cell boundary, and a first length of the at least one second active fin in the first direction is substantially the same as the first width of the cell boundary.

The active gate line may cross the at least one first active fin in the first active region, and the first active region may be a region where an NMOS transistor or a PMOS transistor is formed, and the second active region may be a region where a dummy transistor is formed.

The integrated circuit may further include: a first contact disposed on a portion of the active gate line that is vertically overlapping the dummy region; and a plurality of second contacts disposed on the at least one first active fin and at both sides of the active gate line.

The integrated circuit may further include a dummy gate line extending in the second direction in the second active region and spaced apart from the active gate line, and a line cut region disposed between the dummy gate line and the active gate line.

The dummy gate line and the active gate line may be disposed in a straight line, with the line cut region disposed therebetween.

The line cut region may be disposed in the dummy region and spaced apart from each of the first active region and the second active region.

The integrated circuit may further include a first contact disposed on a portion of the active gate line that is vertically overlapping the dummy region, wherein the first contact and the line cut region are spaced apart from each other.

A dummy gate line may not be disposed in a portion of the second active region disposed in a straight line with the active gate line.

According to another aspect of the inventive concepts, there is provided a standard cell library that includes information about a plurality of standard cells and is stored in a computer-readable storage medium, wherein at least one of the plurality of standard cells includes: a dummy region on a semiconductor substrate; a first active region and a second active region spaced apart from each other, with the dummy region disposed therebetween; a plurality of first active fins disposed in the first active region and extending in a first direction and disposed in parallel to one another in a second direction perpendicular to the first direction; an active gate line extending in the second direction over the first active fins, the active gate line extending to a portion of the dummy region; and a first contact disposed on a portion of the active gate line disposed in the dummy region, the first contact having a first width in the second direction.

The at least one of the plurality of standard cells may further include: a plurality of second active fins extending in the first direction over the entire length of the second active region and disposed in parallel to one another in the second direction; and a dummy gate line extending in the second direction over the second active fins, the dummy gate line extending to a portion of the dummy region.

The dummy gate line and the active gate line may be spaced apart from each other, with a line cut region disposed therebetween.

The line cut region may be disposed in the dummy region, wherein a first distance between the line cut region and the first contact in the second direction is about 0.5 times to about 5 times the first width.

The at least one of the plurality of standard cells may further include: a plurality of second contacts disposed on the first active fins and at both sides of the active gate line; and a plurality of third contacts disposed on the second active fins and at both sides of the dummy gate line.

The at least one of the plurality of standard cells may further include a plurality of second active fins extending in the first direction over an entire length of the second active region and disposed in parallel to one another in the second direction, wherein a dummy gate line is not disposed in a portion of the second active region disposed in a straight line with the active gate line.

According to another aspect of the inventive concepts, there is provided a standard cell library including information about a plurality of standard cells and stored in a computer-readable storage medium, wherein at least one of the plurality of standard cells includes: a dummy region on a semiconductor substrate; a first active region and a second active region spaced apart from each other, with the dummy region disposed therebetween; a plurality of first active fins disposed in the first active region and extending in a first direction and disposed in parallel to one another along a second direction perpendicular to the first direction; a plurality of second active fins extending in the first direction over the entire length of the second active region and disposed in parallel to one another in the second direction; and an active gate line extending in the second direction, wherein the active gate line extends over the first active fins, vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

The at least one of the plurality of standard cells may further include a dummy gate line disposed in the second active region and extending in the second direction and spaced apart from the active gate line, with a line cut region disposed therebetween.

The dummy gate line and the active gate line may be disposed in a straight line, with the line cut region disposed therebetween.

The at least one of the plurality of standard cells may further include: a first contact disposed on a portion of the active gate line vertically overlapping the dummy region; and a plurality of second contacts disposed on at least one of the first active fins and at both sides of the active gate line.

A dummy gate line may not be disposed on a portion of the second active region disposed in a straight line with the active gate line.

