TECHNICAL FIELD

This disclosure relates to field of input/output (“IO”) connectors, more specifically to small IO connectors.

DESCRIPTION OF RELATED ART

IO connectors are commonly used to support network and server applications. Known IO connectors include SFP, QSFP, CXP and XFP style connectors, just to name a few. A new IO connector style is available for use in PCIe standard and is known as an OCULINK connector in the standard. Similar to the QSFP style connector, the OCULINK connector is available 4× connector and thus is expected to be a popular choice for many applications as it provides sufficient bandwidth and front panel density to meet a wide range of applications. Unlike the QSFP style connector, however, the OCULINK connector has terminals on a 0.5 mm pitch and is substantially smaller than a QSFP style connector. An embodiment of the OCULINK connector is described in PCT Publication No. WO2014/113563, which is incorporated herein by reference in its entirety.

Currently OCULINK connectors can support 16 Gbps data rates (and with the 4× design, offers 64 Gbps of bandwidth in both directions) and thus existing OCULINK designs have a performance disadvantage compared to QSFP style connectors that can support 25 Gbps. Given the large difference in size, however, the tradeoff in performance is acceptable for a large number of applications. While the existing connector design is beneficial as is, certain individuals would appreciate improvements to such a connector system that would enable higher data rates.

SUMMARY

A plug connector assembly is disclosed. The plug connector assembly includes a mating portion and a mounting portion and a cover that encloses a connector and a circuit board. The connector includes a shell that wraps around a shell housing. The connector is mated to one end of a circuit board and wires can be terminated to the other end of the circuit board. The connector housing includes a first wafer and a second wafer that each support a row of terminals. The first and second wafer can each have a peg that press against the peg of the other wafer via a cutout in the circuit board so as define a spatial relationship between the first and second wafers. The terminals are connected to the circuit board via solder connection and the first and second wafer are configured to be positioned to be indirectly supported by the circuit board via a shim. The terminals are arranged on a 0.5 mm pitch and in certain embodiments the plug connector is configured to provide a 25 Gbps data rate.

