TECHNICAL FIELD

Embodiments relate generally to data buffering, and, more specifically, to buffering data units within a network device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. patent application Ser. No. 16/867,490, filed on May 5, 2020, entitled “Shared Buffer Memory Architecture,” by Mohammed Kamel Issa, the entire contents of which are hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND

The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section.

The process of temporarily storing data while the data awaits processing is commonly known as “buffering.” In computing devices, including both networking apparatuses and other devices, various components may need to temporarily store data while the data awaits processing. For example, a network switch may receive, from time to time, more data in a given period of time than can be processed by its packet processors. A traffic manager or other component within the switch may therefore regulate the flow of this data to the packet processors by buffering the data until the packet processors are ready to process the data.

Data temporarily stored in this manner is said to be stored in a buffer. A buffer may comprise one or more memory instances in which data may be stored. A memory instance is an independently addressable and accessible unit of memory, such as an on-chip block of memory (e.g. an array of memory cells) or off-chip memory chip. In an embodiment, static random-access memories (“SRAM”) may be preferred for speed and/or cost. However, in other embodiments any suitable type of memory may be utilized for a memory instance, including dynamic random-access memories, registers, flash-based memories, and so forth.

A memory instance may be classified based upon its access limitations, in terms of the number of operations that may be performed with respect to the memory instance in a given memory access period, such as a memory clock cycle, edge of a memory clock cycle, set of memory clock cycles, or any other suitable time slot. For instance, a memory instance may be single-ported, in that only one operation is supported in a time slot (either a read operation or a write operation). Or, a memory instance may be multi-ported, in that two, three, or even more operations are supported in a memory access period. In some embodiments, single-ported memories are preferred for cost efficiency, power demands, and/or other reasons. However, in other embodiments, dual-ported or other multi-ported memories may be preferred.

Each memory operation reads from or writes to a specified address in the memory instance. Each address corresponds to a different location within the memory, also referred to as an entry or buffer entry. Each entry is of a fixed size (e.g. a fixed number of bits or bytes), and this size is also known as the “width” of the memory instance. The number of entries within the memory instance is known as the “depth” of the memory instance.

It is generally desirable to optimize the components of a computing device, including the buffers, so that the device quickly determines where to send and/or store data for processing, and to expediently send and/or store that data to the appropriate destination once determined.

