CROSS REFERENCE TO RELATED APPLICATION

This application claims priority from and the benefit of Korean Patent Application No. 10-2019-0112761, filed on Sep. 11, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND

Field

Exemplary embodiments of the invention relate generally to a scan driver.

Discussion of the Background

Each pixel of a display device may emit light at a luminance corresponding to a data signal input through a data line. The display device may display a frame image with a combination of light emitting pixels.

A plurality of pixels may be connected to each data line. Therefore, a scan driver that provides a scan signal for selecting a pixel to which a data signal is to be supplied is required. The scan driver may be configured in a form of a shift register to sequentially provide a scan signal of a turn-on level in a scan line unit.

As occasion demands, for example, in order to obtain mobility information or threshold voltage information of a driving transistor of the pixel, a scan driver capable of selectively providing a scan signal of a turn-on level to only to a desired scan line is required.

When one scan line is selected for each frame to provide a scan signal to the selected scan line, in order to provide the scan signal to all scan lines, that is, in order to obtain characteristic information of all pixels in a display device (that is, in order to obtain mobility information or threshold voltage information of a driving transistor), a relatively long time may be taken.

The above information disclosed in this Background section is only for understanding of the background of the inventive concepts, and, therefore, it may contain information that does not constitute prior art.

SUMMARY

Exemplary embodiments of the present invention provide a scan driver capable of selecting plurality of scan lines in one frame and sequentially providing a scan signal to the selected scan lines.

Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts.

A scan driver according to an exemplary embodiment of the invention includes a plurality of scan stages. A first scan stage among the plurality of scan stages includes a first transistor having a gate electrode connected to a first Q node one electrode connected to a first scan clock line, and another electrode connected to a first scan line; a second transistor having a gate electrode and one electrode connected to a first scan carry line, and another electrode connected to the first Q node; a third transistor having a gate electrode connected to a first sensing carry line and one electrode connected to a second sensing carry line; a fourth transistor having a gate electrode connected to a first control line, and one electrode connected to another electrode of the third transistor; a fifth transistor having a gate electrode connected to another electrode of the fourth transistor, one electrode connected to a second control line, and another electrode connected to a first node; a first capacitor having one electrode connected to the one electrode of the fifth transistor, and another electrode connected to the gate electrode of the fifth transistor; and a sixth transistor having a gate electrode connected to a third control line, one electrode connected to the first node, and another electrode connected to the first Q node.

The first scan stage may further include a seventh transistor having a gate electrode connected to the first Q node, one electrode connected to the second control line, and another electrode connected to the first node.

A first control signal provided through the first control line may include a plurality of pulses during one frame, and a second sensing carry signal may be written to the first capacitor while both of a pulse of a first sensing carry signal provided through the first sensing carry line and a pulse of the second sensing carry signal provided through the second sensing carry line overlap one of the pulses of the first control signal.

The first scan stage may further include a second capacitor having one electrode connected to the gate electrode of the first transistor and another electrode connected to the other electrode of the first transistor; an eighth transistor having a gate electrode connected to the first Q node, one electrode connected to a first sensing clock line, and another electrode connected to a first sensing line; a third capacitor having one electrode connected to the gate electrode of the eighth transistor and another electrode connected to another electrode of the eighth transistor; and a ninth transistor having a gate electrode connected to the first Q node, one electrode connected to a first carry clock line, and another electrode connected to a first carry line.

The first scan stage may further include a tenth transistor having a gate electrode connected to a first reset carry line, one electrode connected to the first Q node, and another electrode connected to a first power line.

The first scan stage may further include an eleventh transistor having a gate electrode connected to a first QB node, one electrode connected to the first Q node, and another electrode connected to the first power line; and a twelfth transistor having a gate electrode connected to a second QB node, one electrode connected to the first Q node, and another electrode connected to the first power line.

The first scan stage may further include a thirteenth transistor having a gate electrode connected to the first QB node, one electrode connected to the first carry line, and another electrode connected to the first power line; a fourteenth transistor having a gate electrode connected to the second QB node, one electrode connected to the first carry line, and another electrode connected to the first power line; a fifteenth transistor having a gate electrode connected to the first QB node, one electrode connected to the first sensing line, and another electrode connected to a second power line; a sixteenth transistor having a gate electrode connected to the second QB node, one electrode connected to the first sensing line, and another electrode connected to the second power line; a seventeenth transistor having a gate electrode connected to the first QB node, one electrode connected to the first scan line, and another electrode connected to the second power line; and an eighteenth transistor having a gate electrode connected to the second QB node, one electrode connected to the first scan line, and another electrode connected to the second power line.

The first scan stage may further include a nineteenth transistor having a gate electrode connected to a fourth control line, one electrode connected to the gate electrode of the fifth transistor, and another electrode connected to the first power line.

The first scan stage may further include a twentieth transistor having a gate electrode connected to the fourth control line, one electrode connected to the first Q node, and another electrode connected to the first power line; a twenty-first transistor having a gate electrode connected to the first Q node, one electrode connected to the first power line, and another electrode connected to the first QB node; and a twenty-second transistor having a gate electrode connected to the first scan carry line, one electrode connected to the first power line, and another electrode connected to the first QB node.

The first scan stage may further include a twenty-third transistor having a gate electrode connected to the other electrode of the fourth transistor, and one electrode connected to the first power line; and a twenty-fourth transistor having a gate electrode connected to the third control line, one electrode connected to another electrode of the twenty-third transistor, and another electrode connected to the first QB node.

The first scan stage may further include a twenty-fifth transistor having a gate electrode and one electrode connected to a fifth control line; and a twenty-sixth transistor having a gate electrode connected to another electrode of the twenty-fifth transistor, one electrode connected to the fifth control line, and another electrode connected to the first QB node.

The first scan stage may further include a twenty-seventh transistor having a gate electrode connected to the first Q node, one electrode connected to the gate electrode of the twenty-sixth transistor, and another electrode connected to a third power line; and a twenty-eighth transistor having a gate electrode connected to a second Q node, one electrode connected to the gate electrode of the twenty-sixth transistor, and another electrode connected to the third power line.

The nineteenth transistor may further include a first sub-transistor having a gate electrode connected to the fourth control line, and one electrode connected to the other electrode of the fourth transistor; and a second sub-transistor having a gate electrode connected to the fourth control line, one electrode connected to another electrode of the first sub-transistor, and another electrode connected to the first power line. The first scan stage may further include a twenty-ninth transistor having a gate electrode connected to the other electrode of the fourth transistor, one electrode connected to the one electrode of the fourth transistor, and another electrode connected to the second control line.

A second scan stage among the plurality of scan stages may include a thirtieth transistor having a gate electrode connected to the second Q node, one electrode connected to a second scan line, and another electrode connected to a second scan clock line; a fourth capacitor connecting the gate electrode and the one electrode of the thirtieth transistor to each other; a thirty-first transistor having a gate electrode connected to the second Q node, one electrode connected to a second sensing line, and another electrode connected to a second sensing clock line; a fifth capacitor connecting the gate electrode and the one electrode of the thirty-first transistor to each other; and a thirty-second transistor having a gate electrode connected to the second Q node, one electrode connected to a second carry line, and another electrode connected to a second carry clock line.

The second scan stage may further include a thirty-third transistor having a gate electrode connected to the first QB node, one electrode connected to the first power line, and another electrode connected to the second Q node; and a thirty-fourth transistor having a gate electrode connected to the second QB node, one electrode connected to the first power line, and another electrode connected to the second Q node.

The second scan stage may further include a thirty-fifth transistor having a gate electrode, one electrode, and another electrode, the gate electrode and the other electrode being connected to a sixth control line; a thirty-sixth transistor having a gate electrode connected to the one electrode of the thirty-fifth transistor, one electrode connected to the second QB node, and another electrode connected to the sixth control line; a thirty-seventh transistor having a gate electrode connected to the first Q node, one electrode connected to the third power line, and another electrode connected to the gate electrode of the thirty-sixth transistor; and a thirty-eighth transistor having a gate electrode connected to the second Q node, one electrode connected to the third power line, and another electrode connected to the gate electrode of the thirty-sixth transistor.

The second scan stage may further include a thirty-ninth transistor having a gate electrode connected to the first QB node, one electrode connected to the first power line, and another electrode connected to the second carry line; a fortieth transistor having a gate electrode connected to the second QB node, one electrode connected to the first power line, and another electrode connected to the second carry line; a forty-first transistor having a gate electrode connected to the first QB node, one electrode connected to the second power line, and another electrode connected to the second sensing line; a forty-second transistor having a gate electrode connected to the second QB node, one electrode connected to the second power line, and another electrode connected to the second sensing line; a forty-third transistor having a gate electrode connected to the first QB node, one electrode connected to the second power line, and another electrode connected to the second scan line; and a forty-forth transistor having a gate electrode connected to the second QB node, one electrode connected to the second power line, and another electrode connected to the second scan line.

The second scan stage may further include a forty-fifth transistor having a gate electrode connected to the second sensing carry line, and one electrode connected to a third sensing carry line; a forty-sixth transistor having a gate electrode connected to the first control line, and one electrode connected to another electrode of the forty-fifth transistor; a forty-seventh transistor having a gate electrode connected to the third control line, one electrode connected to the second Q node, and another electrode connected to a second node; a forty-eighth transistor having a gate electrode connected to another electrode of the forty-sixth transistor, one electrode connected to the second node, and another electrode connected to the second control line; and a sixth capacitor having one electrode connected to the gate electrode of the forty-eighth transistor, and another electrode connected to the other electrode of the forty-eighth transistor.

The second scan stage may further include a forty-ninth transistor having one electrode connected to the second Q node, and a gate electrode and another electrode connected to a second scan carry line; and a fiftieth transistor having a gate electrode connected to the second Q node, one electrode connected to the second control line, and another electrode connected to the second node.

The second scan stage may further include a fifty-first transistor having a gate electrode connected to the other electrode of the forty-sixth transistor, and one electrode connected to the first power line; and a fifty-second transistor having a gate electrode connected to the third control line, one electrode connected to another electrode of the fifty-first transistor, and another electrode connected to the second QB node.

The second scan stage may further include a fifty-third transistor having a gate electrode connected to the second Q node, one electrode connected to the second QB node, and another electrode connected to the first power line; and a fifty-fourth transistor having a gate electrode connected to the first scan carry line, one electrode connected to the second QB node, and another electrode connected to the first power line.

The second scan stage may further include a fifty-fifth transistor having a gate electrode connected to the fourth control line, one electrode connected to the first power line, and another electrode connected to the second Q node; and a fifty-sixth transistor having a gate electrode connected to the first reset carry line, one electrode connected to the first power line, and another electrode connected to the second Q node.

The second scan stage may further include a fifty-seventh transistor having a gate electrode connected to the fourth control line, one electrode connected to the first power line, and another electrode connected to the gate electrode of the fifty-eighth transistor.

The fifty-seventh transistor may include a third sub-transistor having a gate electrode connected to the fourth control line, and one electrode connected to the other electrode of the forty-sixth transistor; and a fourth sub-transistor having a gate electrode connected to the fourth control line, one electrode connected to another electrode of the third sub-transistor, and another electrode connected to the first power line. The second scan stage may further include a fifty-eighth transistor having a gate electrode connected to the other electrode of the forty-sixth transistor, one electrode connected to the second control line, and another electrode connected to the one electrode of the forty-sixth transistor.

Another exemplary embodiment of the invention provides a scan driver including a plurality of scan stages. A first scan stage among the plurality of scan stages includes a first transistor having a gate electrode connected to a first Q node, one electrode connected to a first scan clock line, and another electrode connected to a first scan line; a second transistor having a gate electrode and one electrode connected to a first scan carry line, and another electrode connected to the first Q node; a third transistor having a gate electrode connected to a first sensing carry line, and one electrode connected to a first control line; a fourth transistor having a gate electrode connected to a second sensing carry line, and one electrode connected to another electrode of the third transistor; a fifth transistor having a gate electrode connected to another electrode of the fourth transistor, one electrode connected to a second control line, and another electrode connected to a first node; a first capacitor having one electrode connected to the one electrode of the fifth transistor, and another electrode connected to the gate electrode of the fifth transistor; and a sixth transistor having a gate electrode connected to a third control line, one electrode connected to the first node, and another electrode connected to the first Q node.

Another exemplary embodiment of the invention provides a scan driver including a plurality of scan stages. Odd-numbered stages among the scan stages are connected to a first sub-control line, and even-numbered stages among the scan stages are connected to a second sub-control line. A first scan stage among the plurality of scan stages includes a first transistor having a gate electrode connected to a first Q node, one electrode connected to a first scan clock line, and another electrode connected to a first scan line; a second transistor having a gate electrode and one electrode connected to a first scan carry line, and another electrode connected to the first Q node; a third transistor having a gate electrode and one electrode connected to a first sensing carry line; a fourth transistor having a gate electrode connected to the first sub-control line, and one electrode connected to another electrode of the third transistor; a fifth transistor having a gate electrode connected to another electrode of the fourth transistor, one electrode connected to a second control line, and another electrode connected to a first node; a first capacitor having one electrode connected to one electrode of the fifth transistor, and another electrode connected to the gate electrode of the fifth transistor; and a sixth transistor having a gate electrode connected to a third control line, one electrode connected to the first node, and another electrode connected to the first Q node.

A second scan stage among the plurality of scan stages may include a seventh transistor having a gate electrode connected to a second Q node, one electrode connected to a second scan clock line, and another electrode connected to a second scan line; an eighth transistor having a gate electrode and one electrode connected to a second scan carry line, and another electrode connected to the second Q node; a ninth transistor having a gate electrode and one electrode connected to a second sensing carry line; a tenth transistor having a gate electrode connected to the second sub-control line, and one electrode connected to another electrode of the ninth transistor; an eleventh transistor having a gate electrode connected to another electrode of the tenth transistor, one electrode connected to the second control line, and another electrode connected to a second node; a second capacitor having one electrode connected to the one electrode of the eleventh transistor, and another electrode connected to the gate electrode of the eleventh transistor; and a twelfth transistor having a gate electrode connected to the third control line, one electrode connected to the second node, and another electrode connected to the second Q node.

Another exemplary embodiment of the invention provides a scan driver including a plurality of scan stages. Odd-numbered stages among the scan stages are connected to a first sub-control line, and even-numbered stages among the scan stages are connected to a second sub-control line. A first scan stage among the plurality of scan stages include a first transistor having a gate electrode connected to a first Q node, one electrode connected to a first scan clock line, and another electrode connected to a first scan line; a second transistor having a gate electrode and one electrode connected to a first scan carry line, and another electrode connected to the first Q node; a third transistor having a gate electrode connected to a first sensing carry line, and one electrode connected to the first sub-control line; a fourth transistor having a gate electrode connected to the first sensing carry line, and one electrode connected to another electrode of the third transistor; a fifth transistor having a gate electrode connected to another electrode of the fourth transistor, one electrode connected to a second control line, and another electrode connected to a first node; a first capacitor having one electrode connected to the one electrode of the fifth transistor, and another electrode connected to the gate electrode of the fifth transistor; and a sixth transistor having a gate electrode connected to a third control line, one electrode connected to the first node, and another electrode connected to the first Q node.

According to the scan driver according to the inventive concepts, two or more stages may be selected by pulses of a selection signal (or a first control signal) in a display period within one frame, and in a sensing period within one frame, the two or more stages may sequentially provide scan signals (and sensing signals) to scan lines according to different clock signals (and sensing clock signals).

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

