CROSS-REFERENCE TO RELATED APPLICATION

This non-provisional application claims priority under 35 U.S.C. § 119(a) to Patent Application No. 201811530871.9 filed in China, P.R.C. on Dec. 14, 2018, the entire contents of which are hereby incorporated by reference.

BACKGROUND

Technical Field

The instant disclosure relates to ultrasonic transmission, in particular, to a wafer scale ultrasonic sensor assembly and method for manufacturing the same.

Related Art

Smart electronic devices like mobile phones, notebook computers, and tablets become important tools in our daily life. People are used to store important or personal information in the smart electronic devices. In order to prevent the information from getting lost or being stolen, smart electronic devices are equipped with fingerprint recognition functions to identify and recognize the users.

In a fingerprint recognition technology applied to smart electronic devices and known to the inventor(s), the ultrasonic element sends the ultrasonic signals to the finger and receives the ultrasonic signals reflected by the peaks and valleys of the fingerprint, so that the fingerprint can be recognized according to the amplitudes of the reflected ultrasonic signals. However, the ultrasonic signals of the ultrasonic element may be transmitted to an area not in contact with the finger, and the reflected ultrasonic signals received by the ultrasonic element are not definitely reflected by the finger. As a result, the fingerprint recognition accuracy of the fingerprint recognition technology known to the inventor is rather lower.

SUMMARY

In view of this, in one embodiment, a wafer scale ultrasonic sensor assembly is provided. The wafer scale ultrasonic sensor assembly comprises a wafer substrate, an ultrasonic element, a first protection layer, a first conductive wire, a second conductive wire, a second protection layer, a transmitting material, an application-specific integrated circuit chip (hereafter, ASIC), a conductive pillar, and a soldering portion.

The wafer substrate comprises a through groove penetrated through a first surface of the wafer substrate and a second surface of the wafer substrate, and the first surface is opposite to the second surface. The ultrasonic element is on the first surface of the wafer substrate, and the ultrasonic element has an upper surface and a lower surface. The lower surface of the ultrasonic element is exposed from the through groove. The first protection layer is on the first surface of the wafer substrate and surrounding the ultrasonic element. The first conductive wire and the second conductive wire are on the first protection layer and respectively connected to the upper surface of the ultrasonic element. The second protection layer covers the first conductive wire and the second conductive wire. The second protection layer has an opening, and the upper surface of the ultrasonic element corresponds to the opening. The transmitting material is in the opening and contacting the upper surface of the ultrasonic element. The ASIC comprises a connection surface and a bottom surface opposite to the connection surface. The connection surface is connected to the second surface of the wafer substrate. The via has a space between the connection surface of the ASIC and the lower surface of the ultrasonic element. The conductive pillar is in a via defined through the ASIC, the wafer substrate, and the first protection layer. The conductive pillar is connected to the first conductive wire or the second conductive wire. The soldering portion is on the bottom surface of the ASIC, and the soldering portion is connected to the conductive pillar.

In one or some embodiments, the connection surface of the ASIC and the second surface of the wafer substrate are connected with each other directly through anodizing.

In one or some embodiments, the ultrasonic element comprises a first piezoelectric layer, a first electrode, a second piezoelectric layer, and a second electrode. The first piezoelectric layer, the first electrode, the second piezoelectric layer, and the second electrode are stacked on the wafer substrate sequentially. The second piezoelectric layer and the second electrode do not cover the first electrode completely. The transmitting material contacts the second electrode. The first electrode is connected to the first conductive wire, and the second electrode is connected to the second conductive wire.

In one or some embodiments, the ultrasonic element comprises a first ultrasonic unit and a second ultrasonic unit. The first ultrasonic unit comprises a first piezoelectric layer and a first electrode. The first piezoelectric layer is on the wafer substrate. The first piezoelectric layer and the first protection layer have a first contact hole, so that the first piezoelectric layer communicates with the first protection layer through the first contact hole. The first electrode is enclosed by the first piezoelectric layer, and a portion of the first conductive wire is in the first contact hole and connected to the first electrode. The second ultrasonic unit is not overlapped with the first ultrasonic unit in a direction perpendicular to the first surface of the wafer substrate. The second ultrasonic unit comprises a second piezoelectric layer, a second circuit pattern layer, and a second electrode. The second piezoelectric layer is on the wafer substrate, and the first piezoelectric layer and the second piezoelectric layer are the same layer and separated from each other. The second circuit pattern layer is enclosed by the second piezoelectric layer, the second circuit pattern layer and the first electrode are the same layer and separated from each other, and the second electrode is on the second piezoelectric layer. The first protection layer has a second contact hole communicating with the opening. A portion of the second conductive wire is in the second contact hole and connected to the second electrode, and a portion of the transmitting material is in the second contact hole and contacting the second electrode.

In one or some embodiments, the ASIC further comprises a plurality of connection pads on the connection surface of the ASIC. Moreover, the via is defined through one of the connection pads connected to the conductive pillar.

In one or some embodiments, the transmitting material is polydimethylsiloxane.

A method for manufacturing wafer scale ultrasonic sensor assembly is also provided. The method comprises an ultrasonic element forming step, a first protection layer forming step, a wire connecting step, a second protection layer forming step, an opening forming step, a removing step, a connecting step, a via forming step, a via filling step, a soldering portion forming step, and a transmitting material filling step.

The ultrasonic element forming step comprises forming an ultrasonic element on a first surface of a wafer substrate, where the ultrasonic element comprises a first electrode and a second electrode not connected to the first electrode. The first protection layer forming step comprises forming a first protection layer on an upper surface of the ultrasonic element and the first surface of the wafer substrate, where the first protection layer has a first contact hole and a second contact hole, a portion of the first electrode is exposed from the first contact hole, and a portion of the second electrode is exposed from the second contact hole. The wire connecting step comprises forming a first conductive wire and a second conductive wire, where the first conductive wire and the second conductive wire are on the first protection layer, portions of the first conductive wire are in the first contact hole and connected to the first electrode of the ultrasonic element, and portions of the second conductive wire are in the second contact hole and connected to the second electrode of the ultrasonic element.

The second protection layer forming step comprises forming a second protection layer to cover the first conductive wire and the second conductive wire. The opening forming step comprises forming an opening on the second protection layer, where the opening at least exposes a portion of the second electrode. The removing step comprises removing a portion of the wafer substrate to form a through groove defined through the first surface and a second surface of the wafer substrate opposite to the first surface of the wafer substrate, so that a lower surface of the ultrasonic element is exposed from the through groove. The connecting step comprises connecting a connection surface of an ASIC and the second surface of the wafer substrate through anodizing, so that the through groove has a space between the connection surface and the lower surface of the ultrasonic element. The via forming step comprises forming a via defined through the ASIC, the wafer substrate, and the first protection layer. The via filling step comprises filling a conductive material in the via to form a conductive pillar, where the conductive pillar is connected to the first conductive wire or the second conductive wire. The soldering portion forming step comprises forming a soldering portion on a bottom surface of the ASIC, where a position of the soldering portion corresponds to a position of the conductive pillar, and the soldering portion is connected to the conductive pillar. The transmitting material filling step comprises filling a transmitting material in the opening, where the transmitting material contacts an upper surface of the ultrasonic element.

In one or some embodiments, after the opening forming step, the method further comprises a loading plate covering step. The loading plate covering step comprises covering a loading plate on the second protection layer and the opening to shield the opening. Moreover, after the soldering portion forming step, the method further comprises a loading plate removing step. The loading plate removing step comprises removing the loading plate to expose the opening.

In one or some embodiments, the ultrasonic element forming step comprises forming a first piezoelectric layer, a first electrode, a second piezoelectric layer, and a second electrode on the wafer substrate sequentially; and removing a portion of the first piezoelectric layer, a portion of the first electrode, a portion of the second piezoelectric layer, and a portion of the second electrode, where the second piezoelectric layer and the second electrode do not cover portions of the upper surface of the first electrode. The opening forming step, the opening is further defined through the first protection layer.

In some other embodiments, the ultrasonic element forming step comprises forming a first piezoelectric material layer and a first electrode material layer on the wafer substrate sequentially; patterning the first piezoelectric material layer and the first electrode material layer to form a first bottom piezoelectric layer, a second bottom piezoelectric layer, a first electrode, and a second circuit pattern layer, where the first bottom piezoelectric layer and the second bottom piezoelectric layer are separated from each other, the first electrode is stacked on the first bottom piezoelectric layer, and the second circuit pattern layer is stacked on the second bottom piezoelectric layer; forming a second piezoelectric material layer and a second electrode material layer on the first electrode and the second circuit pattern layer sequentially; and patterning the second piezoelectric material layer and the second electrode material layer to form a first piezoelectric layer, a second piezoelectric layer, and a second electrode, where the first piezoelectric layer and the second piezoelectric layer are separated from each other, the second electrode is formed on the second piezoelectric layer, wherein the first electrode is enclosed by the first piezoelectric layer, and the second circuit pattern layer is enclosed by the second piezoelectric layer. Furthermore, the first protection layer forming step further comprise forming a first protection material layer on the first piezoelectric layer, the second piezoelectric layer, and the second electrode; and forming the first contact hole and the second contact hole on the first protection material layer to convert the first protection material layer into the first protection layer, where the first protection layer comprises the first contact hole and the second contact hole, the first contact hole is defined through the first protection layer and the first piezoelectric layer, so that a portion of the first electrode is exposed from the first contact hole, and the second contact hole is defined through the first protection layer, so that a portion of the second electrode is exposed from the second contact hole.

Furthermore, in one or some embodiments, the ASIC further comprises a plurality of connection pad on the connection surface of the ASIC. Moreover, in one or some embodiments, in the via forming step, the via is defined through one of the connection pads.

In one or some embodiments, after the second protection layer forming step, the method further comprises a polishing step. The polishing step comprises polishing the wafer substrate in a direction from the second surface toward the first surface to reduce a thickness of the wafer substrate.

In one or some embodiments, the connecting step further comprises vacuuming the space.

As above, according to one or some embodiments of the instant disclosure, the first ultrasonic signals transmitted from the upper surface of the ultrasonic element travel through the transmitting material; while the second ultrasonic signals transmitted from the lower surface of the ultrasonic element travel through the space. Therefore, the transmission speed of the first ultrasonic signals is quite different from the transmission speed of the second ultrasonic signals. Furthermore, the ASIC is connected to the wafer substrate is electrically connected to the ultrasonic element. Hence, the structural strength of the wafer scale ultrasonic sensor assembly can be improved, and the ultrasonic signals can be recognized accurately and quickly.

