TECHNICAL FIELD

The disclosure relates to semiconductor integrated circuits, and more particularly to wiring layers and interconnects overlying semiconductor devices and their manufacturing processes.

BACKGROUND

As feature densities in semiconductor devices increase, the widths of the conductive lines, and the spacing between the conductive lines of back-end of line (BEOL) interconnect structures in the semiconductor devices also need to be scaled down. At 5 nm/7 nm nodes and beyond, the varying topography of deposited film caused by the density of underlying lines and devices makes conventional BEOL interconnect processing more difficult. Due to the varying topography, when filling insulating material into spacer openings formed by photolithographic operations, the amount of insulating material may vary. If too little insulating material is filled in the spacer openings, a short circuit may be caused in subsequent interconnect formation operations. If too much insulating material is filled in the spacers, then disconnects may be formed in subsequent interconnect formation operations.

