BACKGROUND

The semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs. As this progression takes place, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as fin-like field effect transistor (FinFET) device. A typical FinFET device is fabricated with a thin “fin” (or fin-like structure) extending from a substrate. The fin usually includes silicon and forms the body of the transistor device. The channel of the transistor is formed in this vertical fin. A gate is provided over (e.g., wrapping around) the fin. This type of gate allows greater control of the channel. Other advantages of FinFET devices include reduced short channel effect and higher current flow.

However, conventional FinFET devices may still have certain shortcomings. One shortcoming is that the manner in which the source/drain regions are defined for conventional FinFET fabrication has not been optimized. For example, the FinFET device may suffer from epi-selectivity loss in the formation of source/drain regions.

Therefore, while existing FinFET devices and the fabrication thereof have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.

