TECHNICAL FIELD

Embodiments of the present invention pertain to the field of electronic device manufacturing and methods for device patterning. In particular, embodiments pertain to the use of selective etching of aluminum oxide in patterning and gate contact applications.

BACKGROUND

Reducing the size of integrated circuits (ICs) results in improved performance, increased capacity and/or reduced cost. Each size reduction requires more sophisticated techniques to form the ICs. Photolithography is commonly used to pattern ICs on a substrate. An exemplary feature of an IC is a line of a material which may be a metal, semiconductor or insulator. Linewidth is the width of the line and the spacing is the distance between adjacent lines. Pitch is defined as the distance between a same point on two adjacent lines. The pitch is equal to the sum of the linewidth and the spacing. Due to factors such as optics and light or radiation wavelength, however, photolithography techniques are restricted by a minimum pitch, below which a particular photolithographic technique may not reliably form features. Thus, the minimum pitch of a photolithographic technique can limit feature size reduction of ICs.

Processes such as self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), and litho-etch-litho-etch (LELE) may be used for extending the capabilities of photolithographic techniques beyond the minimum pitch capabilities of existing lithographic equipment. Following the SADP, SAQP, or LELE process, multi-cut or block masks are placed over the lines and spaces generated by SADP, SAQP, or LELE processes to perform device patterning. As the feature size decreases, pitch and linewidth also decrease. Therefore the precision of mask edge placement control must be higher. For example, for a 7 nm node structure, the pitch is about 32 nm, and the cut or block mask's total edge placement errors (EPE) should be less than ¼ of the pitch, which is less than about 8 nm. Equipment capable of meeting such tight geometric requirements are extremely expensive, and additionally, such tight geometric requirements also contribute to low production yields.

Therefore, there is a need for improved methods for device patterning to reduce defects from pattern misalignment and increase production yields.

SUMMARY

One or more embodiments of the disclosure are directed to methods of forming a semiconductor device. A substrate with a gate with a first side and a second side and with a gate cap thereon is provided. The substrate has a spacer material adjacent the first side and the second side of the gate. The spacer material adjacent the first side of the gate is a first spacer and the spacer material adjacent the second side of the gate is a second spacer. A source material with a source cap is on an opposite side of the spacer material adjacent the first side of the gate. A drain material with a drain cap is on an opposite side of the spacer material adjacent the second side of the gate. A dielectric is on opposite sides of the source material from the first spacer and on opposite sides of the drain material from the second spacer. A mask is formed on a surface of the gate cap, spacer material, source cap, drain cap and dielectric. The mask has an opening exposing the surface of one or more of the gate cap, source cap or drain cap. One or more of the gate cap, source cap or drain cap is selectively etched through the opening in the mask to expose a top of one or more of the gate, source material or drain material forming a gap. At least one of the gate cap, source cap or drain cap comprises a material that is resistant to etching using the etch conditions for the selective etching.

Additional embodiments of the disclosure are directed to methods of forming a semiconductor device. A substrate with a gate with a first side and a second side and with a gate cap thereon is provided. The substrate has a spacer material adjacent the first side and the second side of the gate. The spacer material adjacent the first side of the gate is a first spacer and the spacer material adjacent the second side of the gate is a second spacer. A source material with a source cap is on an opposite side of the spacer material adjacent the first side of the gate. A drain material with a drain cap is on an opposite side of the spacer material adjacent the second side of the gate. A dielectric is on opposite sides of the source material from the first spacer and on opposite sides of the drain material from the second spacer. A mask is formed on a surface of the gate cap, spacer material, source cap, drain cap and dielectric. The mask has an opening exposing the surface of the gate cap and at least some of the surface of one or more of the source cap or drain cap. The gate cap is selectively etched through the opening in the mask to expose a top of one or more of the gate and leave substantially all of the source cap and drain cap.

Further embodiments of the disclosure are directed to methods of forming a semiconductor device. A substrate with a gate with a first side and a second side and with a gate cap thereon is provided. The substrate has a spacer material adjacent the first side and the second side of the gate. The spacer material adjacent the first side of the gate is a first spacer and the spacer material adjacent the second side of the gate is a second spacer. A source material with a source cap is on an opposite side of the spacer material adjacent the first side of the gate. A drain material with a drain cap is on an opposite side of the spacer material adjacent the second side of the gate. A dielectric is on opposite sides of the source material from the first spacer and on opposite sides of the drain material from the second spacer. A mask is formed on a surface of the gate cap, spacer material, source cap, drain cap and dielectric. The mask has an opening exposing the surface of one or more of the source cap or drain cap and at least some of the gate cap. One or more of the source cap or drain cap is selectively etched through the opening in the mask to expose a top of one or more of the source material or drain material and leave substantially all of the gate cap.

