FIELD

The embodiments discussed herein are related to an encoding circuit, a decoding circuit, an encoding method, a decoding method, and a transmitting device.

BACKGROUND

With increases in transmission capacities of optical transmitting devices, multilevel modulation, such as quadrature phase-shift keying (QPSK), 16 quadrature amplitude modulation (QAM), and 64 QAM, is used, for example. In the multilevel modulation, a symbol that is among symbols arranged in a constellation and corresponds to values of each bit string within a frame signal to be modulated is allocated to the bit string, and thus an optical signal with a phase and an intensity that are based on the symbol is generated.

A probabilistic shaping technique (hereinafter referred to as “PS”) generates a probability distribution for symbol allocation by converting values of bit strings so that, as a region within a constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger. This improves noise tolerance of signal light generated from a frame.

In the PS, a distribution matching (DM) process of increasing a mark rate of a bit string to a rate (of, for example, 80%) of greater than 50% is used, for example. Therefore, the probability of allocating a symbol is higher toward the center of the constellation only in a specific quadrant among first to fourth quadrants of the constellation. After that, a quadrant in which a symbol to be allocated is located is determined from the first to fourth quadrants.

To determine the quadrant, a parity bit of an error correction code, such as forward error correction (FEC), may be used (refer to, for example, F. Buchali, et al., “Rate Adaptation and Reach Increase by Probabilistically Shaped 64-QAM: An Experimental Demonstration,”, JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL., 34, NO. 7, Apr. 1, 2016). Since a mark rate of the error correction code is maintained at approximately 50%, the first to fourth quadrants are selected with almost the same probability, and a probability distribution in which symbols are biased toward the center of a constellation in all quadrants is generated.

Examples of a method of encoding the error correction code are bit-interleaved coded modulation (BICM) and multilevel coding (MLC) (refer to, for example, Japanese Laid-open Patent Publication No. 2008-187706, U. Wachsmann, et al., “Multilevel Codes: Theoretical Concepts and Practical Design Rules”, IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 45, NO. 5, July 1999, A. Bisplinghoff, et al., “Low-Power, Phase-Slip Tolerant, Multilevel Coding for M-QAM”, JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL., 35, NO. 4, Feb. 15, 2017, and Y. Koganel, et al., “Multilevel Coding with Spatially-Coupled Codes for beyond 400 Gbps Optical Transmission”, OFC, 2018, Tu3C.2). BICM is a method of collectively encoding bit strings in a way in which the bit strings are not distinguished based on levels (the most significant bit (MSB) and the least significant bit (LSB)). MLC is an encoding method of individually generating error correction codes in a way in which bit strings are classified based on levels.

SUMMARY

According to an aspect of the embodiments, an encoding circuit includes: an allocator configured to allocate, to a plurality of bit strings, symbols that are among a plurality of symbols within a constellation of multilevel modulation and correspond to values of the plurality of bit strings within a frame; a converter configured to convert values of each of bit strings among the plurality of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region among the plurality of symbols is larger; a switch configured to switch, in a cycle of the frame, between a first time period in which a first error correction code to correct an error of the plurality of bit strings is inserted in the plurality of bit strings and a second time period in which the first error correction code is not inserted in the plurality of bit strings; and a first insertor configured to generate the first error correction code from a second bit string among the plurality of bit strings in the second time period and inserts the first error correction code in two or more bit strings including the first bit string in the first time period in accordance with the switching by the switch. An apparatus includes

The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention.

