BACKGROUND

1. Field of the Invention

This invention relates in general to power amplifiers and, in particular, to power amplifier modules. More specifically, but without restriction to the particular embodiments hereinafter described in accordance with the best mode of practice, this invention relates to power amplifier modules for use in wireless communications and includes related systems, devices, and methods.

2. Description of Related Technology

Power amplifiers can be included in mobile devices to amplify a RF signal for transmission via an antenna. For example, in mobile devices having a time division multiple access (TDMA) architecture, such as those found in Global System for Mobile Communications (GSM), code division multiple access (CDMA), and wideband code division multiple access (W-CDMA) systems, a power amplifier can be used to amplify a RF signal having a relatively low power. It can be important to manage the amplification of a RF signal, as a desired transmit power level can depend on how far the user is away from a base station and/or the mobile environment. Power amplifiers can also be employed to aid in regulating the power level of the RF signal over time, so as to prevent signal interference from transmission during an assigned receive time slot.

The power consumption of a power amplifier and power added efficiency (PAE) associated therewith can be an important consideration. In view of the ever increasing demands associated with providing wireless communication for voice, data, and system control, there is a need for improved power amplifiers, power amplifiers modules, and devices, systems, and methods relating thereto. Furthermore, there is a need for power amplifiers having improved power efficiency.

Certain specific aspects of the present invention relate to the field of integrated circuit packaging, and more particularly to systems and methods of forming wire bond pads for packaging radio frequency (RF) integrated circuits (ICs).

Silicon or other semiconductor wafers are fabricated into integrated circuits as is known to one of ordinary skill in the art of IC fabrication. An IC is bonded and electrically connected to a carrier or substrate, which has layers of dielectric and metal traces, and packaged for use. A surface plating material is plated onto the top layer of copper traces to provide electrical connection points between the IC and the substrate, permitting the IC to interface with the outside world. Traditionally, nickel/gold (Ni/Au) has been a standard surface plating material for RFIC products and in certain situations, the RFIC is wire-bonded to the Ni/Au wire-bond pads plated on the surface of the substrate to form the electrical connections of the RFIC with its package. However, increases in gold prices have increased packaging costs associated with the Ni/Au surface plating.

Other particular aspects of the present invention relate to the field of integrated circuit layout and packaging, and more particularly to systems and methods of layout and packaging of radio frequency (RF) integrated circuits (IC s).

Still other aspects of this invention more particularly to bipolar transistors and products that include bipolar transistors. Bipolar transistors, such as heterojunction bipolar transistors (HBTs), are implemented in a wide variety of applications. Such bipolar transistors can be formed on semiconductor substrates, such as gallium arsenide (GaAs) substrates. One illustrative application for a bipolar transistor is in a power amplifier system. As technology evolves, specifications for power amplifier systems have become more demanding to meet.

As indicated above, one aspect of power amplifier performance is linearity. Measures of linearity performance can include channel power ratios, such as the adjacent channel power ratio (ACPR1) and the alternative channel power ratio (ACPR2), and/or channel leakage power ratios, such as an adjacent channel leakage power ratio (ACLR1) and an alternative channel leakage power ratio (ACLR2). ACPR2 and ACLR2 can be referred to as second channel linearity measures. ACPR2 and ACLR2 values can correspond at measurements at an offset of about 1.98 MHz from a frequency of interest.

Conventionally, most publications in the literature have focused on ACPR1 and ACLR1 linearity measures and little has been published about ACRP2 or ACLR2. Recent ACPR2 and ACLR2 system specifications from industry have been particularly difficult to meet, especially while meeting other system specifications related to RF gain. Accordingly, a need exists for improved linearity in systems that include bipolar transistors, such as power amplifier systems.

Yet still further aspects of the present disclosure relate to a dual mode digital control interface for power amplifiers.

A number of electronic devices, including wireless devices, may have one or more components that are controlled or set by a front-end component. For example, a power amplifier may be set or configured by a power amplifier controller. In some cases, the power amplifier controller may itself be controlled or configured by another interface component based on the state of the device.

Often, various components within a device will be created by different organizations. To facilitate interoperability between components, which may be designed by different organizations, standards are often adopted for different types of devices and components. As technology advances, standards may change or new standards may be adopted. In some cases, the newer standards are not compatible with the older standards.

And still yet other aspects of the present invention relate to heterojunction bipolar transistor (HBT) power amplifier bias circuits. Power amplifiers are typically active elements that can magnify an input signal to yield an output signal that is significantly larger than the input signal. Many types of power amplifiers exist and there are many ways to create power amplifiers. For example, some power amplifiers can be created using heterojunction bipolar transistors (HBT). Many HBT power amplifiers use a diode stack bias configuration. In some such configurations, the diode stack bias configuration exhibits sensitivity to the device beta, which can result in substantial quiescent current variation of the amplifier. Further, the variation of quiescent current may impact performance parameters and may degrade product yield.

Further aspects hereof relate to the understanding that in some semiconductor material systems it is possible to combine different device technologies on a single semiconductor die to form hybrid structures. For example, in certain material systems, it is possible to integrate a heterojunction bipolar transistor (HBT) with a field effect transistors (FET) on a single substrate, to fabricate what is referred to as a BiFET. Devices, such as RF power amplifiers, can be fabricated using BiFET technology to have increased design flexibility. As a result, a BiFET power amplifier including an HBT and a FET can be advantageously designed to operate at a lower reference voltage than a bipolar transistor power amplifier. Of particular interest to device manufacturers are high power BiFET amplifiers, which can be formed by integrating a FET into a gallium arsenide (GaAs) HBT process. However, previous attempts to integrate a FET into a GaAs HBT process have resulted only in an n-type FET device.

Therefore, it would be desirable to have a BiFET device structure that includes a p-type FET device, and that may include complementary n-type and p-type FET devices.

And yet still other aspects of the improved technology disclosed herein relate to terminating a harmonic component of a signal. In relatively high frequency applications, such as radio frequency (RF) applications, unwanted signal reflection and/or noise can occur. Such unwanted signal reflection and/or noise can occur at a fundamental frequency of the signal and/or other frequencies, such as harmonics of the fundamental frequency of the signal. To reduce the impact of signal reflection and/or noise, impedance matching can be implemented. One illustrative application in which it is advantageous to minimize unwanted signal reflection and/or noise is a power amplifier system.

Power added efficiency (PAE) is one metric for rating power amplifiers. In addition, linearity is another metric for rating power amplifiers. PAE and/or linearity can be metrics by which customers, such as original equipment manufacturers (OEMs), determine which power amplifiers to purchase. For instance, power amplifiers with a PAE below a certain level may not be purchased by a customer due to the impact of PAE on the customer's product. A lower PAE can, for example, reduce the battery life of an electronic device, such as a mobile phone. However, enhancing PAE can come at the cost of adversely impacting linearity. Similarly, improving linearity can cause a decrease in PAE. At the same time, customers want power amplifiers with high linearity and high PAE.

A load line at an output of a power amplifier can impact both PAE and linearity. Some conventional power amplifier systems have included a load line to match an impedance of the power amplifier output at a fundamental frequency of the power amplifier output signal and also to perform harmonic termination. However, it has proved difficult to match an impedance of the fundamental frequency of the power amplifier output while including harmonic termination in a way that optimizes both PAE and linearity. Accordingly, a need exists to improve both linearity and PAE of a power amplifier.

Now still further aspects of the present invention relate to transmission lines for high performance radio frequency applications.

Transmission lines can be implemented in a variety of contexts, such as on a packaging substrate or printed circuit board (PCB). Multi-layer laminate PCBs or package substrates are extensively used in radio frequency (RF) applications.

RF circuits, such as power amplifiers, low noise amplifiers (LNAs), mixers, voltage controlled oscillators (VCOs), filters, switches and whole transceivers have been implemented using semiconductor technologies. However, in RF modules (for example, an RF front-end module including power amplifiers, switches, and/or filters), single chip integration may not be practical due to different blocks being implemented in different semiconductor technologies. For instance, a power amplifier may be formed by a GaAs process, while related control and/or bias circuitry may be formed by a CMOS process.

Long transmission lines and/or other on chip passives can consume large chip area. Consequently, multi-chip module (MCM) and/or system in package (SiP) assembly technology can be used to achieve low cost, small size and/or high performance in RF modules. Laminate technology can be used for MCM assembly, in which transmission lines are implemented on a laminate substrate. Conductor loss in such transmission lines can have a significant impact on the performance of any of the elements in the MCM. Accordingly, laminate plating technology can impact RF performance significantly.

The cost of laminate technology can be driven by the choice materials for performance and/or assembly needs. RF SiPs that use gold (Au) wire bonding to connect RF circuit elements to transmission lines can use a variety of different finish platings such as lower loss, more expensive NiAu (for example, due to thicker Au) or higher loss, less expensive NiPdAu. Accordingly, a need exists for cost effective, high performance technology for RF transmission lines.

And yet further aspects related to apparatus and methods for tantalum nitride terminated through-wafer vias. In certain implementations, a tantalum nitride (TaN) termination layer is formed on a first or front side of a gallium arsenide (GaAs) wafer, and a gold conductive layer is formed over the TaN termination layer. Thereafter, a through-wafer via is etched into a second or back side of the GaAs wafer so as to extend through the GaAs wafer and a first or inner portion of the TaN termination layer to reach the gold conductive layer. In certain implementations, the through wafer via is plated with a nickel vanadium (NiV) barrier layer, a gold seed layer, and a copper layer. During through-wafer via formation, a second or outer portion of the TaN termination layer is maintained and configured to surround an interface between the gold conductive layer and the copper layer so as to inhibit diffusion of copper into the GaAs wafer.

TaN terminated through-wafer vias can provide improved metal adhesion and reduced copper migration relative to schemes employing silicon nitride termination and a sputtered barrier layer. Furthermore, in certain implementations using a TaN termination layer to terminate a through-wafer via can permit the location or position of the through wafer via to be moved without changing fabrication or lithographical masks associated with transistor structures formed on the front side of the GaAs wafer. Configuring the through-wafer vias to be movable without changing lithographical mask associated with transistors can increase design flexibility and/or reduce time and cost associated with incremental fixes or tape-outs of integrated circuits designs that include the through-wafer vias.

In addition to the above, still further aspects of the present disclosure relate to packaged semiconductor structures and, more particularly, to structures that provide radio frequency (RF) isolation and/or electromagnetic radiation.

Packaged semiconductor components can include integrated shielding technology within a package. To form a shield, which can be referred to as a “Faraday cage,” a top layer conductive layer can be electrically connected to a bottom conductive layer by vias. For instance, the bottom conductive layer can be a ground plane and the vias can connect the top conductive layer to ground. The vias can provide an electrical connection between the top and the bottom conductive layers and also function as part of the shield itself. However, the vias can consume a significant amount of area in the package. At the same time, the vias can affect a strength of the ground connection of the shield.

Further to the above, additional aspects of this invention are directed to semiconductor device packages and, more particularly, to electromagnetic and/or radio frequency interference shielding for semiconductor devices.

There exists a general need in radio frequency (RF) communication systems for RF devices to be isolated from electromagnetic (radio frequency) interference (EMI) generated by other RF devices in order to maintain proper device performance. Similarly, the RF devices generally need to be isolated from the electromagnetic interference received from, or transmitted to, the environment.

The traditional method of isolating RF devices from such electromagnetic interference is to cover the RF device with a grounded metal enclosure typically called a “can.” However, this solution is costly and lacks design flexibility. In addition, the metal can adds significant size to the device footprint on a printed circuit board, and also adds weight to the printed circuit board.

Implementing one or more of the features, attributes, or characteristics described in further detail in the various following sections hereof can achieve desirable linearity and PAE in a power amplifier system. Moreover, implementing in a power amplifier system one or more features described in the following disclosure can achieve desirable FOM and/or other metrics by which power amplifiers are rated. Although some features hereof are described in connection with a power amplifier module for illustrative purposes, it will be understood by those of skill in the art that the principles and advantages described herein can be applied to other portions of a power amplifier system, such as in a power amplifier die, a substrate for use with a power amplifier die, and a wireless communications device that includes a power amplifier, and in any and all other applications that would be apparent to those skilled in any analogous art.

SUMMARY

I. Introduction

Power amplifiers can boost the power of a radio frequency (RF) signal having a relatively low power. Thereafter, the boosted RF signal can be used for a variety of purposes, such as driving the antenna of a transmitter.

Power amplifiers can be used in a variety of RF wireless communications devices. As one example, power amplifiers can be included in mobile phones to amplify an RF signal for transmission. For instance, in mobile phones having a time division multiple access (TDMA) architecture, such as those found in Global System for Mobile Communications (GSM), code division multiple access (CDMA), and wideband code division multiple access (W-CDMA) systems, a power amplifier can be used to amplify an RF signal.

Power Added Efficiency (PAE) is one metric for rating power amplifiers. Linearity is another metric for rating power amplifiers. PAE and/or linearity can be metrics by which customers determine which power amplifiers to purchase. For instance, power amplifiers with a PAE below a certain level may not be purchased by a customer due to the impact of PAE on a customer product. A lower PAE can, for example, reduce the battery life of a mobile device, such as a mobile phone. Linearity can be measured, for example, by an Adjacent-Channel Power Ratio (ACPR) and/or an Alternative Channel Power Ratio (ACPR2). It can be difficult to achieve high PAE and high linearity at the same time. Yet customers typically desire high PAE and high linearity. Figure of Merit (FOM) is one metric that can reflect both PAE and linearity.

II. Wire Bond Pad Systems and Related Methods

Systems and methods are disclosed to reduce the cost of RFIC packaging by using a Nickel/Palladium/Gold (Ni/Pd/Au) surface plating material for RFIC products. To decrease the costs, the gold layer in the Ni/Pd/Au surface plating is thinner than the gold layer in Ni/Au surface plating. However, Ni/Pd/Au has a much higher radio frequency sheet resistance than Ni/Au due to thin palladium and gold layers and the ferromagnetic nature of nickel. This contributes to reduced effective current sheet thickness and increased current crowding on the RF signals, and can, in some embodiments, lead to greater RF losses for RF signals traveling through the Ni/Pd/Au plated surfaces than are found on RF signals traveling through the Ni/Au plated surfaces. These losses can impact product performance and yield.

Further systems and methods are disclosed to reduce the RF losses associated with the lower cost Ni/Pd/Au surface plating for RFICs. In some embodiments of design layouts, the RF line/trace surface, edge, and sidewalls in the wire-bonding area are open to the plating process and are therefore plated with the Ni/Pd/Au surface finish. Due to the skin effect and eddy current effect on the RF current traveling through the plated wire-bonding areas, a majority of the RF current is running on the trace edges and side walls of the plated wire-bonding areas. Because a majority of the RF current is running on the trace edges and side walls, plating the trace edges and sidewalls contributes more to RF losses. To reduce the RF losses, some embodiments reconfigure the solder mask to cover the trace edges and sidewalls in the wire-bonding area such that the trace edges and sidewalls are not plated with the Ni/Pd/Au surface finish. The copper trace edges and sidewalls free from the Ni/Pd/Au plating around the wire-bonding areas provide a low resistive path for the RF current around the Ni/Pd/Au wire bond pad and thus, reduce the RF signal loss associated with the Ni/Pd/Au surface plating of the RFIC substrate.

Certain embodiments relate to a method of fabricating a radio frequency integrated circuit (RFIC) module including providing a substrate having at least one copper trace, the copper trace having a wire bonding surface. The method further includes forming a solder mask opening for a wire bonding pad directly over the bonding surface of the copper trace, the wire bonding pad having at least one edge and at least one sidewall. The method further includes forming solder mask directly over the at least one edge and the at least one sidewall of the wire bonding pad, plating the copper trace with a nickel layer, plating the nickel layer with a palladium layer and plating the palladium layer with a gold layer to form a nickel/palladium/gold wire bonding pad. The nickel/palladium/gold wire bonding pad has the at least one edge and the at least one sidewall free from the nickel, palladium, and gold layers.

According to a number of embodiments, the disclosure relates to a wire bonding pad for a radio frequency integrated circuit (RFIC) module. The wire bonding pad includes a nickel layer plated over a wire bonding surface of a copper trace, the copper trace formed on an upper surface of a substrate of an RFIC module. The wire bonding pad further includes a palladium layer plated over the nickel layer and a gold layer plated over the palladium layer. The wire bonding pad having a wire bond area, at least one edge adjacent to the wire bond area, and at least one sidewall adjacent to the at least one edge, the at least one edge and the at least one sidewall free from the nickel layer, the palladium layer, and the gold layer.

In accordance with various embodiments, an apparatus for fabricating a radio frequency integrated circuit (RFIC) module includes means for providing a substrate having at least one copper trace, the copper trace having a wire bonding surface, and means for forming a solder mask opening for a wire bonding pad directly over the bonding surface of the copper trace, the wire bonding pad having at least one edge and at least one sidewall. The apparatus further includes means for forming solder mask directly over the at least one edge and the at least one sidewall of the wire bonding pad, means for plating the copper trace with a nickel layer, means for plating the nickel layer with a palladium layer, and means for plating the palladium layer with a gold layer to form a nickel/palladium/gold wire bonding pad. The nickel/palladium/gold wire bonding pad has the at least one edge and the at least one sidewall free from the nickel, palladium, and gold layers.

For purposes of summarizing the disclosure, certain aspects, advantages and novel features of the inventions have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.

III. Apparatus and Methods for Reducing Impact of High RF Loss Plating

Systems and methods are disclosed to reduce the cost of RFIC packaging by using a Nickel/Palladium/Gold (Ni/Pd/Au) surface plating material for RFIC products. To decrease the costs, the gold layer in the Ni/Pd/Au surface plating is thinner than the gold layer in Ni/Au surface plating. However, Ni/Pd/Au has a much higher radio frequency sheet resistance than Ni/Au due to thin palladium and gold layers and the ferromagnetic nature of nickel. This contributes to reduced effective current sheet thickness and increased current crowding on the RF signals, and can, in some embodiments, lead to greater RF losses for RF signals traveling through the Ni/Pd/Au plated surfaces than are found on RF signals traveling through the Ni/Au plated surfaces. These losses can impact product performance and yield.

Further systems and methods are disclosed to reduce the RF losses associated with the lower cost Ni/Pd/Au surface plating for RFICs. In some embodiments of design layouts, the RF line/trace surface, edge, and sidewalls in the wire-bonding area are open to the plating process and are therefore plated with the Ni/Pd/Au surface finish. Due to the skin effect and eddy current effect on the RF current traveling through the plated wire-bonding areas, a majority of the RF current is running on the trace edges and side walls of the plated wire-bonding areas. Because a majority of the RF current is running on the trace edges and side walls, plating the trace edges and sidewalls contributes more to RF losses. To reduce the RF losses, some embodiments reconfigure the solder mask to cover the trace edges and sidewalls in the wire-bonding area such that the trace edges and sidewalls are not plated with the Ni/Pd/Au surface finish. The copper trace edges and sidewalls free from the Ni/Pd/Au plating around the wire-bonding areas provide a low resistive path for the RF current around the Ni/Pd/Au wire bond pad and thus, reduce the RF signal loss associated with the Ni/Pd/Au surface plating of the RFIC substrate.

In addition, systems and methods are disclosed to reduce the RF losses associated with the high RF loss bonding pad of an on-die capacitor, resistor, inductor, or other passive device of the RFIC. In some embodiments, RFICs include an on-die capacitor, resistor, inductor, or other passive device. The capacitor or passive device is bonded to the copper trace carrying the RF current. When a high RF loss bonding pad, such as a Ni/Pd/Au bonding pad, for example, is used to connect the passive device to the circuit traces of the RFIC module, the high RF loss bonding pad creates RF signal losses when the RF current flows through it. Placing the on-die capacitor, resistor, inductor, or other passive device in an RF upper trace with respect to the RF signal output of the RFIC reduces the RF losses associated with the on-die passive device bonding pad.

In certain embodiments, an electronic circuit module configured to reduce signal losses is disclosed. The module includes an electronic circuit device having an output signal and a current associated therewith. The electronic circuit device includes a first lead, a second lead, and an integrated circuit die having an on-die passive component. The electronic circuit module further includes a substrate including a trace for conducting the current. The trace has a first bonding pad on an upper signal path electrically connected to the first lead and a second bonding pad on a down signal path electrically connected to the second lead. The electronic circuit device is configured such that the on-die passive component electrically connects to the first lead and the output signal electrically connects to the second lead. The current thereby being directed away from the first bonding pad. In an embodiment, the electronic circuit module is a radio frequency integrated circuit module and the signal losses are radio frequency signal losses. In another embodiment the electronic circuit device is a radio frequency electronic circuit device, the output signal is a radio frequency output signal, and the current is a radio frequency current.

According to a number of embodiments, an electronic circuit device is configured to reduce signal losses. The device includes an integrated circuit die having an on-die passive component, an output signal having an associated current, a first lead electrically connected to a first bonding pad located on an upper signal path of a trace on a substrate, and a second lead electrically connected to a second bonding pad located on a down signal path on the trace. The electronic circuit device is configured such that the on-die passive component electrically connects to the first lead and the output signal electrically connects to the second lead. The current thereby being directed away from the first bonding pad.

In accordance with various embodiments, a method for reducing signal losses in an electronic circuit module is disclosed. The method includes fabricating an electronic circuit device including an integrated circuit die having an on-die passive component, and generating an output signal from the electronic circuit device. The output signal has an associated current. The method further includes forming a first lead and a second lead on the electronic circuit device, forming a first bonding pad and a second bonding pad on a substrate, and forming a trace on the substrate to provide a conductive path to conduct the current between the first and the second bonding pads. The trace has an upper signal path associated with the first bonding pad and a down signal path associated with the second bonding pad. The method further includes electrically connecting the first lead to the first bonding pad, electrically connecting the second lead to the second bonding pad, and configuring the electronic circuit device so that the on-die passive component electrically connects to the first lead and the output signal electrically connects to the second lead. The current thereby being directed away from the first bonding pad.

In an embodiment, an apparatus for reducing signal losses in an electronic circuit module is disclosed. The apparatus includes means for fabricating an electronic circuit device including an integrated circuit die having an on-die passive component, and means for generating an output signal from the electronic circuit device. The output signal has an associated current. The apparatus further includes means for forming a first lead and a second lead on the electronic circuit device, means for forming a first bonding pad and a second bonding pad on a substrate, and means for forming a trace on the substrate to provide a conductive path to conduct the current between the first and the second bonding pads. The trace has an upper signal path associated with the first bonding pad and a lower signal path associated with the second bonding pad. The apparatus further includes means for electrically connecting the first lead to the first bonding pad, means for electrically connecting the second lead to the second bonding pad, and means for configuring the electronic circuit device such that the on-die passive component electrically connects to the first lead and the output signal electrically connects to the second lead. The current thereby being directed away from the first bonding pad.

For purposes of summarizing the disclosure, certain aspects, advantages and novel features of the inventions have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.

IV. Bipolar Transistors Having Collector with Grading

The innovations described in the claims each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of this invention, some prominent features will now be briefly discussed.

One aspect of this disclosure is a bipolar transistor that includes a collector, a base disposed over the collector, and an emitter. The collector has a doping concentration of at least about 3×1016cm−3in a first collector region abutting the base. The collector also has another collector region under the first collector region. The other collector region includes at least one grading in which doping concentration increases away from the first collector region.

In certain embodiments, the other collector region includes a first grading and a second grading in which doping concentration increases away from the base at a different rate than in the first grading. According to some of these embodiments, the bipolar transistor of can have a gain of at least about 29 dBm at a frequency within a frequency band centered around about 833 MHz. In accordance with a number of embodiments, the second grading of the bipolar transistor can be configured to increase BvCEX of the bipolar transistor compared to the same transistor without the second grading at the same current density. In various embodiments, a doping concentration in the first grading grades from about an order of magnitude less than the doping concentration of the first collector region to less than the doping concentration of the first collector region. According to some of these embodiments, a doping concentration in the second grading grades from about a maximum doping concentration in the first grading to a doping concentration that is at least about one order of magnitude less than the doping concentration of a sub-collector below the second grading. In some embodiments, the first grading spans a second collector region proximate the first collector region and having a thickness that is more than approximately twice the thickness of the first collector region. According to certain embodiments, the second grading spans a third collector region having a thickness that is greater than the thickness of the first collector region and less than the thickness of the second collector region. In various embodiments, the collector consists essentially of the first collector region, the second collector region, and the third collector region. According to some embodiments, the bipolar transistor also includes a sub-collector under the collector. In accordance with certain embodiments, the first grading borders the second grading and doping concentration is approximately the same on both sides of the border of the first grading and the second grading.

In certain embodiments, a thickness of the first collector region is selected from a range of about 1000 Å to 2000 Å. According to some of these embodiments, the doping concentration of the first collector region is selected from a range of about 3×1016cm−3to 9×1016cm−3.

According to a number of embodiments, the doping concentration in the first collector region is at least about 6×1016cm−3.

In accordance with some embodiments, the base has a thickness of less than about 1400 Å. In some of these embodiments, the base has a doping concentration selected from a range of about 3.5×1019cm−3to 7×1019cm−3.

In a number of embodiments, the bipolar transistor is a heterojunction bipolar transistor (HBT).

According to some embodiments, the bipolar transistor is a GaAs transistor.

Another aspect of this disclosure is a power amplifier module that includes a bipolar transistor. The bipolar transistor has a collector, a base, and an emitter. The collector has a doping concentration at a junction with the base such that the power amplifier has an alternative channel power ratio (ACPR2) of no greater than about 65 dBc. The collector also has at least a first grading in which doping concentration increases away from the base.

According to certain embodiments, the ACPR2 is no greater than about 65 dBc when the power amplifier operates within a frequency band centered around approximately 833 MHz.

In a number of embodiments, the collector also includes a second grading farther from the base than the first grading. The second grading is configured to increase BvCEX of the bipolar transistor compared to the same transistor without the second grading at the same current density, according to some embodiments.

According to a number of embodiments, the doping concentration in the collector at the junction with the base is at least about 3×1016cm−3.

In certain embodiments, the collector includes a first region abutting the base having a substantially flat doping concentration of at least about 3×1016cm−3and a thickness selected from a range of about 1000 Å to 2000 Å. According to some of these embodiments, the doping concentration in the first region of the collector is selected in the range from about 3×1016cm−3to 9×1016cm−3.

A further aspect of this disclosure is a power amplifier die that includes a bipolar transistor having a collector, a base abutting the collector, and an emitter. The collector has a doping concentration of at least about 3×1016cm−3at a junction with the base. The collector also has at least a first grading in which doping concentration increases away from the base.

Another aspect of this disclosure is a mobile device that includes an antenna, a battery, and a power amplifier. The power amplifier includes a heterojunction bipolar transistor having a collector, a base, and an emitter. The collector includes a first collector region abutting the base and having a first doping concentration of at least about 3×1016cm−3. The collector also includes a second collector region proximate the first collector region and having a first grading in which doping concentration increases away from the base. The collector also includes a third collector region proximate the second collector region and having a second grading in which doping concentration increases away from the base at a different rate than the first grading. The first doping concentration, the first grading, and the second grading are configured to improve linearity of the power amplifier.

Yet another aspect of this disclosure is a method of forming a bipolar transistor. The method includes forming a sub-collector; forming a collector region with at least one grading having a doping concentration that decreases away from the sub-collector; and forming a different collector region adjacent abutting a base of the bipolar transistor and having a doping concentration of at least about 3×1016cm−3at an interface with the base.

For purposes of summarizing the disclosure, certain aspects, advantages and novel features of the inventions have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.

V. Dual Mode Power Amplifier Control with Three-Mode Input/Output Interface

In accordance with some embodiments of this invention, this aspect of the present disclosure relates to a dual mode control interface that can be used to provide both a radio frequency front end (RFFE) serial interface and a general purpose input/output (GPIO) interface within a single digital control interface die. In certain embodiments, the dual mode control interface, or digital control interface, can communicate with a power amplifier. Further, the dual mode control interface can be used to set the mode of the power amplifier.

According to certain embodiments, the dual mode control interface includes a RFFE core configured to provide a RFFE serial interface. Further, the dual mode control interface includes a voltage input/output (VIO) pin configured to receive a VIO signal. This VIO signal determines whether an operating mode of the RFFE core is set to one of an active state and an inactive state. When the RFFE core is set to the inactive state, the dual mode control interface is configured to provide a general purpose input/output (GPIO) interface In addition, the dual mode control interface includes a combinational logic block configured to provide an enable signal and a mode signal to an enable level shifter and a mode level shifter, respectively. Moreover, the dual mode control interface includes a power on reset configured to select the enable signal and the mode signal to provide to the enable level shifter and the mode level shifter, respectively, based on the VIO signal.

For some implementations, the dual mode interface includes a clock/mode pin configured to provide a clock signal to the RFFE core when the RFFE core is set to an active state and a mode signal to the combinational logic block when the RFFE core is set to an inactive state. In addition, the dual mode interface includes a data/enable pin configured to provide a data signal to the RFFE core when the RFFE core is set to an active state and an enable signal to the combinational logic block when the RFFE core is set to an inactive state.

In some variations, the data/enable pin is further configured to provide an address signal to the RFFE core, the address signal associated with a register of the RFFE core.

According to some other related embodiments hereof, the dual mode interface includes a plurality of level shifters. Each level shifter of the plurality of level shifters may be configured to receive a register signal from the RFFE core. The register signal can be associated with a value stored in one of a plurality of registers associated with the RFFE core.

VI. Process-Compensated HBT Power Amplifier Bias Circuits and Related Methods

In some implementations relating to this aspect of the present invention, the present disclosure relates to a power amplifier (PA) configuration that takes advantage of a passive device on the amplifier die to effectively sense die-dependent parameter such as beta and compensate for the associated effects such as quiescent-current variation to improve performance and/or reduce the part-to-part variation of the product. In some embodiments thereof, such a PA configuration can include a silicon bias die and an HBT amplifier die. Traditionally, the silicon die would generate a reference current for the PA die which is substantially constant with respect to temperature of the PA die and essentially only varies by the tolerance of a discrete resistor.

In some implementation of the present invention, such a discrete reference resistor can be replaced by an integrated resistor on the HBT die. In some embodiments thereof, this integrated resistor can be formed with the HBT device base material, and can exhibit a sheet resistance characteristic which tracks with the process beta. Based on such resistance, a reference current can be configured to track with beta and cancel or reduce the “diode-stack” sensitivity to beta.

In other embodiments relating hereto, the foregoing base resistor (Rb) type can be configured to yield a high temperature coefficient which can be compensated by the bias generation circuitry within the silicon control die such that the voltage applied across the reference resistor increases with the ambient temperature. The resulting reference current sourced to the amplifier can be substantially constant over a selected range of ambient temperature and substantially track the HBT process beta.

VII. Devices and Methods for Structures Having HBTs and FETs

Embodiments of a semiconductor structure include a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET including a channel formed in the semiconductor material that forms the collector layer of the HBT.

In some embodiments of this aspect of the present invention, the semiconductor material that forms the collector layer of the HBT and the channel of the FET can include p-type gallium arsenide. In some embodiments, the semiconductor structure can further include an etch stop layer segment located over the collector layer of the HBT and the channel of the FET. In some embodiments, such an etch stop layer can include indium gallium arsenide (InGaAs) or indium gallium phosphide (InGaP), and can have a thickness range between 10 nanometers (nm) and 15 nm. Other thickness ranges can also be implemented. In some embodiments, such an etch stop layer can include any material with etch selectivity to, for example, the channel layer of the FET. Such a material can be implemented in an appropriate thickness or within an appropriate range of thicknesses so as to achieve similar results as the foregoing example materials InGaAs or InGaP.

In accordance with other embodiments hereof, the present disclosure relates to a semiconductor structure having a heterojunction bipolar transistor (HBT) that includes a collector layer located over a substrate and an emitter layer located over the substrate. The collector layer includes a first semiconductor material of a first conductivity type (P), and the emitter layer includes a second semiconductor material of a second conductivity type (N). The semiconductor structure further includes a first field effect transistor (FET) located over the substrate. The first FET includes a channel formed in the first semiconductor material that forms the collector layer of the HBT. The semiconductor structure further includes a second field effect transistor (FET) located over the substrate. The second FET includes a channel formed in the second semiconductor material that forms the emitter layer of the HBT.

In some embodiments hereof, the first semiconductor material that forms the collector layer of the HBT and the channel of the first FET can include p-type gallium arsenide, and the second semiconductor material that forms the emitter layer of the HBT and the channel of the second FET can include n-type gallium arsenide. In some embodiments, semiconductor structure can further include a first etch stop layer segment located over the collector layer of the HBT and the channel of the first FET, and a second etch stop layer segment located over the emitter layer of the HBT and the channel of the second FET. The first etch stop layer segment and the second etch stop layer segment can include indium gallium arsenide (InGaAs) or indium gallium phosphide (InGaP), and can have a thickness range between 10 nanometers (nm) and 15 nm. Other thickness ranges can also be implemented. In some embodiments, such etch stop layers can include any material with etch selectivity to, for example, the channel layers of the first and second FETs. Such a material can be implemented in an appropriate thickness or within an appropriate range of thicknesses so as to achieve similar results as the foregoing example materials InGaAs or InGaP.

In a number of implementations, the present disclosure relates to a method that includes forming a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate and an emitter layer located over the substrate. The collector layer includes a first semiconductor material of a first conductivity type (P), and the emitter layer includes a second semiconductor material of a second conductivity type (N). The method further includes forming a first field effect transistor (FET) over the substrate. The first FET includes a channel formed in the first semiconductor material that forms the collector layer of the HBT. The method further includes forming a second field effect transistor (FET) over the substrate. The second FET includes a channel formed in the second semiconductor material that forms the emitter layer of the HBT.

In some implementations, the first semiconductor material that forms the collector layer of the HBT and the channel of the first FET can include p-type gallium arsenide, and the second semiconductor material that forms the emitter layer of the HBT and the channel of the second FET can include n-type gallium arsenide. In some implementations, the method can further include forming a first etch stop layer segment over the collector layer of the HBT and the channel of the first FET, and forming a second etch stop layer segment over the emitter layer of the HBT and the channel of the second FET. The first etch stop layer segment and the second etch stop layer segment can include indium gallium arsenide (InGaAs) or indium gallium phosphide (InGaP), and can have a thickness range between 10 nanometers (nm) and 15 nm.

According to some implementations, the present disclosure relates to a method that includes forming a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate. The collector layer includes a semiconductor material. The method further includes forming a field effect transistor (FET) located over the substrate. The FET includes a channel formed in the semiconductor material that forms the collector layer of the HBT.

In some implementations, the semiconductor material that forms the collector layer of the HBT and the channel of the FET can include p-type gallium arsenide. In some implementations, the method can further include forming an etch stop layer segment located over the collector layer of the HBT and the channel of the FET. The etch stop layer can include indium gallium arsenide (InGaAs) or indium gallium phosphide (InGaP), and can have a thickness range between 10 nanometers (nm) and 15 nm.

According to some embodiments, the present disclosure relates to a die having an integrated circuit (IC). The die includes a circuit configured to process radiofrequency (RF) signal. The die further includes an assembly of a heterojunction bipolar transistor (HBT) and a field effect transistor (FET) configured to facilitate operation of the circuit. The HBT includes a collector layer including a semiconductor material located over a substrate. The FET includes a channel located over the substrate and formed in the semiconductor material that forms the collector layer of the HBT.

In some embodiments, the circuit configured to process RF signal can include a power amplifier circuit, a controller circuit for the power amplifier circuit, or a controller for a switching circuit. In some embodiments, the assembly can further include a second FET having a channel located over the substrate and formed in same semiconductor material as an emitter of the HBT. The first FET can include a pFET, and the second FET can include an nFET. In some embodiments, the substrate can include gallium arsenide (GaAs).

In a number of embodiments, the present disclosure relates to a packaged module for a radiofrequency (RF) device. The module includes a packaging substrate and an integrated circuit (IC) formed on a die and mounted on the packaging substrate. The IC includes an assembly of a heterojunction bipolar transistor (HBT) and a field effect transistor (FET) configured to facilitate operation of the IC. The HBT includes a collector layer including a semiconductor material located over a die substrate. The FET includes a channel located over the die substrate and formed in the semiconductor material that forms the collector layer of the HBT. The module further includes one or more connections configured to facilitate transfer of power to the IC and RF signals to and from the IC.

According to other related embodiments hereof, the assembly can further include a second FET having a channel located over the die substrate and formed in same semiconductor material as an emitter of the HBT. The first FET can include a pFET and the second FET can include an nFET.

In accordance with some other embodiments relating hereto, the present disclosure relates to a wireless device having an antenna and a radiofrequency integrated circuit (RFIC) configured to process RF signals received from the antenna and for transmission through the antenna. The wireless device further includes a power amplifier (PA) circuit configured to amplify the RF signals. The PA circuit includes an assembly of a heterojunction bipolar transistor (HBT) and a field effect transistor (FET). The HBT includes a collector layer including a semiconductor material located over a substrate. The FET includes a channel located over the substrate and formed in the semiconductor material that forms the collector layer of the HBT.

In still some other related embodiments hereof, the PA can be configured to operate as a high power BiFET amplifier capable of operating at a lower reference voltage than that of a bipolar transistor PA. In some embodiments, the substrate can include gallium arsenide (GaAs).

Other embodiments are also provided. Other systems, methods, features, and advantages of the invention will be or become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.

VIII. RF Power Amplifiers Having Semiconductor Resistors

In many situations, it is desirable to reduce the cost of radio-frequency (RF) devices such as power amplifiers (PAs). Removing process steps and/or using “free” devices that do not involve extra processing steps are examples of how such cost-reduction can be achieved. As described herein-below in further detail, semiconductor resistors can provide such advantageous cost reductions. As also described herein, other advantages can also be realized with semiconductor resistors. For example, depending on resistance values available, smaller resistor footprints can be provided, which in turn can help shrink die sizes. Such a reduction in die size can further reduce cost. In another example, some semiconductor resistors can be sensitive to conditions of the same semiconductor materials that also form the resistors.

In some implementations of this aspect of the present invention, some or all of thin-film (e.g., TaN) resistors associated with a semiconductor die and an IC thereon can be replaced with semiconductor resistors. In some implementations, such semiconductor resistors can be fabricated from one or more of the actual layers that form layer-stack devices such as heterojunction bipolar transistors (HBTs). Such resistors can be fabricated with no extra processing steps when the HBTs are made. Because a number of such resistors can be fabricated from different layers of a stack (e.g., emitter layer, base layer, and ion-implanted base layer of an HBT), flexibility in resistance values and die size reduction are possible.

In other implementations hereof, fabrication of a semiconductor resistor having one or more features as described herein can be achieved with no additional processing steps or very little modifications of process steps, when compared to fabrication of stack structure(s) on a given die. Although the various examples are described herein in the context of HBTs, it will be understood that similar resistor structures and fabrication methods can apply to other configurations. For example, additional layers can be formed for fabricating devices that include an HBT and one or more other transistor structures. Examples of such devices include, but are not limited to, U.S. Pat. No. 6,906,359 titled BIFET INCLUDING A FET HAVING INCREASED LINEARITY AND MANUFACTURABILITY and PCT Publication No. WO 2012/061632 titled DEVICES AND METHODOLOGIES RELATED TO STRUCTURES HAVING HBT AND FET.

According to other embodiments, one or more features of the present disclosure can be implemented in III-V semiconductor dies. In some embodiments, such III-V semiconductor dies can include GaAs-based dies. Transistors and/or other stack structures formed on such GaAs-based dies may or may not include an HBT.

As described herein, a number of advantageous features can be provided by semiconductor resistors. Other advantages can include, for example, a desirable feature where different temperature coefficient of resistance (TCR) values is provided by selecting a material associated with the resistor layer. In another example, size of the resistor can be optimized or configured in a desirable manner because of such a range of possible resistance values (e.g., sheet resistance of about 8 ohms/sq (e.g., sub-collector) to about 1,000 Ohms/sq (e.g., implanted base layer)). In yet another example, RF roll-off of resistor can be selected and/or tuned, depending on which resistor is selected (e.g., by modifying how the 3rd terminal on the device is biased).

IX. Signal Path Termination

One aspect of this disclosure is a power amplifier module including a power amplifier die, a load line, and a harmonic termination circuit. The power amplifier die includes one or more power amplifiers configured to amplify an input signal at a power amplifier input and to generate an amplified output signal at a power amplifier output. The power amplifier die also has a plurality of output pins. The load line is configured to match an impedance at the power amplifier output at a fundamental frequency of the amplified output signal. The load line is electrically coupled to a first group of one or more of the plurality of output pins of the power amplifier die external to the power amplifier die. The harmonic termination circuit is separate from the load line. The harmonic termination circuit is configured to terminate at a phase corresponding to a harmonic frequency of the amplified output signal. The harmonic termination circuit is electrically coupled to a second group of one or more other pins of the plurality of output pins of the power amplifier die external to the power amplifier die.

In certain implementations hereof, the harmonic termination circuit can include one or more interconnects coupled to the second group of one or more other pins of the power amplifier die external to the power amplifier die. According to some of these implementations, the one or more interconnects can include a wirebond. Alternatively or additionally, the load line can include one or more other interconnects coupled to the first group of one or more pins of the power amplifier die external to the power amplifier die. In accordance with various implementations, a different number of interconnects can be coupled to the first group of one or more pins of the power amplifier die than to the second group of one or more other pins of the power amplifier die.

According to a number of implementations, the first group of one or more pins of the power amplifier die can be electrically coupled to a first conductive trace on a substrate and the second group of one or more pins of the power amplifier die is electrically coupled to a second conductive trace on the substrate, in which the first conductive trace is included in a different signal path than the second conductive trace external to the power amplifier die. In some of these implementations, the harmonic termination circuit can include a wirebond having a first end and a second end, the first end coupled to the second first group of one or more pins of the power amplifier die; the second conductive trace on the substrate, the second conductive trace coupled to the second end of the wirebond; and a capacitor having a first end and a second end, the first end coupled to the second conductive trace and the second end coupled to a reference voltage.

The harmonic frequency of the amplified output signal can be, for example, a second harmonic frequency of the amplified output signal or a third harmonic frequency of the amplified output signal.

According to various implementations, the power amplifier module can also include another harmonic termination circuit separate from both the load line and the harmonic termination circuit, the other harmonic termination circuit configured terminate at a phase corresponding to another harmonic frequency of the amplified output signal. The harmonic termination circuit can be in parallel with the other harmonic termination circuit, according to certain implementations.

The power amplifier module can also include an input matching network configured to match an impedance at the power amplifier input and a separate harmonic termination circuit configured to terminate at a phase of a harmonic frequency of the input signal, according to certain implementations.

In some implementations, a portion of the harmonic termination circuit can be implemented within the power amplifier die.

Another aspect of this disclosure is a mobile device that includes a battery configured to power the mobile device, a power amplifier die, a load line, a harmonic termination circuit, and an antenna electrically coupled to the load line, the antenna configured to transmit an amplified RF signal. The power amplifier die includes a power amplifier configured to amplify a radio frequency (RF) input signal received at a power amplifier input node and to generate the amplified RF signal at a power amplifier output node. The load line is configured to match an impedance at the power amplifier output node at a fundamental frequency of the amplified RF signal. The harmonic termination circuit is separate from the load line. The harmonic termination circuit is configured to terminate at a phase corresponding to a harmonic frequency of the amplified RF signal. The harmonic termination circuit and the load line have different electrical connections to the power amplifier output node external to the power amplifier die.

Another aspect of this disclosure is an apparatus that includes a die and a substrate configured to receive the die. The die includes at least one active circuit element configured to drive an output signal to an output node. The substrate includes a first conductive trace and a second conductive trace. The first conductive trace and the second conductive trace are part of different signal paths on the substrate. The first conductive trace is included in a load line configured to match an impedance at output node of the die at a fundamental frequency of the output signal. The second conductive trace is included in a harmonic termination circuit separate from the load line. The harmonic termination circuit is configured to terminate at a phase corresponding to a harmonic frequency of the output signal.

In certain implementations, the substrate can include a third conductive trace, which is included in another harmonic termination circuit configured to terminate at a phase corresponding to a different harmonic frequency of the output signal.

According to some implementations, the apparatus can also include a wirebond configured to electrically couple the output node of the die to the second conductive trace, and the wirebond can be included in the harmonic termination circuit.

In accordance with a number of implementations, the apparatus can also include a capacitor mounted to the substrate, in which the capacitor is electrically coupled to the second conductive trace and the capacitor is included in the harmonic termination circuit.

Yet another aspect of this disclosure is a method of manufacturing a module. The method includes coupling power amplifier die to a packaging substrate, the power amplifier die including a power amplifier configured to receive an input signal and generate an amplified output signal; forming a first interconnect between the power amplifier die and a first conductive trace on the packaging substrate, the first interconnect being included in a first termination circuit configured to match an impedance of a fundamental frequency of the amplified output signal; and forming a second interconnect between the power amplifier die and a second conductive trace on the packaging substrate, the second interconnect being separate from the first interconnect, the first conductive trace being separate from the second conductive trace, and the second interconnect being included in a second termination circuit configured to terminate at a phase corresponding to a harmonic of the amplified output signal.

In some implementations, forming the first interconnect can include wirebonding a pad of the power amplifier die to the first conductive trace on the packaging substrate.

For purposes of summarizing the disclosure, certain aspects, advantages and novel features of the inventions have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.

X. Transmission Line for High Performance Radio Frequency Applications

One aspect of the disclosure is a radio frequency (RF) transmission line configured for use in a radio frequency (RF) circuit. The RF transmission line includes a bonding layer, a barrier layer, and diffusion barrier layer, and a conductive layer. The bonding layer has a bonding surface and is configured to receive an RF signal. The barrier layer is configured to prevent a contaminant from entering the bonding layer. The barrier layer is proximate the bonding layer. The diffusion barrier layer is configured to prevent contaminant from entering the bonding layer. The diffusion barrier layer is proximate the barrier layer. The diffusion barrier layer has a thickness that allows the received RF signal to penetrate the diffusion barrier layer to a conductive layer that is proximate to the diffusion barrier layer.

In some implementations, the bonding layer, the barrier layer, and the diffusion barrier layer can be embodied in a finish plating. The bonding layer can include gold according to certain implementations. In various implementations, the bonding surface can be configured for wire bonding. According to a number of implementations, the barrier layer can include palladium.

The diffusion barrier layer can include nickel according to certain implementations. In some implementations, the thickness of the diffusion barrier layer can be in the range from about 0.04 um to about 0.7 um. The thickness of the diffusion barrier layer can be no more than about 0.5 um according to a number of implementations. The thickness of the diffusion barrier layer can be no more than about 0.35 um according to various implementations. The thickness of the diffusion barrier layer can be no more than about 0.75 um according to a certain implementations. In some implementations, the thickness of the diffusion barrier layer can be less than the skin depth of nickel at a frequency of about 0.45 GHz.

In accordance with some implementations hereof, the thickness of the diffusion barrier can be less than the skin depth of the diffusion barrier layer at a frequency of about 0.45 GHz.

According to a number of implementations relating hereto, the conductive layer can include one or more of copper, aluminum, or silver. For instance, the conductive layer can include copper in certain implementations. In various implementations, substantially all of the received RF signal can propagate in the conductive layer.

The bonding layer can be gold, the barrier layer can be palladium, and the diffusion barrier layer can be nickel according to certain implementations. In some of these implementations, the thickness of the diffusion barrier layer is can be the range from about 0.04 um to about 0.7 um. According to a number of implementations, the thickness of the diffusion barrier layer can be no more than about 0.5 um. According to certain implementations, the thickness of the diffusion barrier layer can be no more than about 0.35 urn. According to some implementations, the thickness of the diffusion barrier layer can be no more than about 0.75 um.

Another aspect of this disclosure is a diffusion barrier layer configured for use in an RF transmission line. The diffusion barrier layer includes a material and has a thickness. The thickness of the diffusion barrier layer is sufficiently small such that an RF signal is allowed to penetrate the diffusion barrier layer.

In certain implementations of this aspect of the present invention, the material includes nickel. According to some of these implementations, the thickness of the diffusion barrier layer can be in the range from about 0.04 urn to about 0.7 urn. According to a number of implementations, the thickness of the diffusion barrier layer can be no more than about 0.5 urn. According to some implementations, the thickness of the diffusion barrier layer can be no more than about 0.35 urn. According to certain implementations, the thickness of the diffusion barrier layer can be no more than about 0.75 urn. In various implementations, the thickness of the diffusion barrier layer can be less than the skin depth of nickel at a frequency of about 0.45 GHz.

In accordance with a number of implementations relating hereto, the thickness of the diffusion barrier layer can be less than about the skin depth of the material at a frequency of about 0.45 GHz.

According to some implementations, substantially all of the RF signal that penetrates the diffusion barrier layer can travel in a conductive layer proximate the diffusion barrier layer.

In various implementations, the material and/or the thickness of the diffusion barrier layer can prevent contaminants from passing through the diffusion barrier layer.

Another aspect of this disclosure is a mobile device that includes a transmission line, an antenna, and a battery. The transmission line includes a bonding layer, a barrier layer, a diffusion barrier layer, and a conductive layer. The bonding layer has a bonding surface. The barrier layer is proximate the bonding layer. The diffusion barrier is layer proximate to the barrier layer. The conductive layer is proximate to the diffusion barrier layer. The barrier layer and the diffusion barrier layer are configured to prevent conductive material from the conductive layer from entering the bonding layer. The diffusion barrier layer has a thickness that is sufficiently small such that an RF signal is allowed to penetrate the diffusion barrier layer and propagate in the conductive layer. The antenna is coupled to the transmission line and configured to transmit an RF output signal. The transmission line is configured to extend an amount of time for the battery to discharge.

According to certain implementations, the mobile device can include a power amplifier having an output coupled to the transmission line. In some of these implementations, an output of the power amplifier can be coupled to the transmission line via a wire bond. In accordance with various implementations, the transmission line can be configured to transmit the RF signal from the power amplifier to an RF switch. The transmission line can be configured to transmit the RF signal from the power amplifier to a filter according to some implementations.

According to a number of implementations, the mobile device can include a filter having an output coupled to the transmission line. In some implementations, the transmission line can be configured to transmit the RF signal from the filter to an RF switch. In accordance with various implementations, the transmission line can be configured to transmit the RF signal from the filter to the antenna.

In accordance with some implementations, the mobile device can include an RF switch having an output coupled to the transmission line. In certain implementations, the transmission line is configured to transmit the RF signal from the RF switch to the antenna. In accordance with various implementations, the transmission line is configured to transmit the RF signal from the RF switch to a filter.

According to certain specific implementations hereof, the diffusion barrier layer can include nickel. In some of these implementations, the thickness of the diffusion barrier layer can be in the range from about 0.04 um to about 0.7 um. In a number of implementations, the thickness of the diffusion barrier layer can be no more than about 0.5 um. In some implementations, the thickness of the diffusion barrier layer can be no more than about 0.35 um. In certain implementations, the thickness of the diffusion barrier layer can be no more than about 0.75 um. In various implementations, the thickness of the diffusion barrier layer can be less than the skin depth of nickel at a frequency of about 0.45 GHz.

In a number of implementations, the thickness of the diffusion barrier layer can be less than the skin depth of the material at a frequency of about 0.45 GHz. In accordance with certain particular implementations, substantially all of the RF signal can travel in the conductive layer of the transmission line. According to some implementations, the bonding layer, the barrier layer, and the diffusion barrier layer can be embodied in a finish plating.

Another aspect of this disclosure is a laminate panel including a substrate. The substrate includes a transmission line configured for transmitting an RF signal. The transmission line has a bonding layer, a barrier layer, a diffusion barrier layer, and a conductive layer. The bonding layer has a bonding surface configured for bonding with a conductor separate from the conductive layer. The barrier layer is configured to prevent a contaminant from entering the bonding layer. The diffusion barrier layer includes a material and has a thickness such that contaminants are prevented from passing through the diffusion barrier layer and diffusing between the conductive layer and the bonding layer. The thickness of the diffusion barrier layer is sufficiently small such that the RF signal from the conductor is allowed to penetrate to the conductive layer.

According to certain implementations, the diffusion barrier layer can be nickel. In some of these implementations, the diffusion barrier layer can have a thickness that is less than the skin depth of nickel at a frequency of about 0.45 GHz.

In a number of implementations, the bonding layer can include gold, the barrier layer can include palladium, and the diffusion barrier layer can include nickel. In some of these implementations, the thickness of the diffusion barrier layer can be less than about 0.75 um.

Another aspect of this disclosure is a module that includes a substrate, a first RF component, and a second RF component. The substrate includes a conductor and a transmission line. The transmission line has a bonding layer, a barrier layer, a diffusion barrier layer, and a conductive layer. The bonding layer has a bonding surface configured for bonding with the conductor. The barrier layer and the diffusion barrier layer are configured to prevent a contaminant from entering the bonding layer. The thickness of the diffusion barrier layer is sufficiently small such that an RF signal from the conductor is allowed to penetrate to the conductive layer. The first RF component is coupled to the substrate and configured to generate the RF signal. The second RF component is coupled to the substrate and configured to receive the RF signal from the first component via the transmission line.

In certain implementations, the substrate is a laminate substrate. According to some of these implementations, the substrate can include a finish plating that includes the bonding layer, the barrier layer, and the diffusion barrier layer.

According to a number of implementations, the diffusion barrier layer can include nickel. In a number of implementations, the thickness of the diffusion barrier layer can be no more than about 0.7 um. In some implementations, the thickness can be no more than about 0.35 um. In certain implementations, the thickness of the diffusion barrier layer can be no more than about 0.75 um. In various implementations, the thickness of the diffusion barrier layer can be less than the skin depth of nickel at a frequency of about 0.45 GHz. In accordance with certain implementations, the conductive layer can include copper. In some implementations, the thickness of the diffusion barrier layer can be less than the skin depth of the material at a frequency of about 0.45 GHz.

In accordance with various implementations, the bonding layer can be configured for wire bonding and the conductor can be electrically coupled to the bonding layer via a wire bond.

According to certain implementations, substantially all of the RF signal can propagate from the first RF component to the second RF component in the conductive layer.

In various implementations, the first RF component can include a power amplifier. According to some of these implementations, the second RF component can include a filter and/or an RF switch.

According to some implementations, the first RF component can include an RF switch. According to some of these implementations, the second RF component can include a power amplifier and/or a filter.

In certain other implementations, the first RF component can include a filter. According to some of these implementations, the second RF component includes a power amplifier and/or an RF switch.

In accordance with a number of implementations, the barrier layer can be positioned between the bonding layer and the diffusion barrier layer.

Yet another aspect of this disclosure is an RF transmission line that includes a conductive layer and finish plating on the conductive layer. The finish plating includes a gold layer, a palladium layer proximate the gold layer, and a nickel layer proximate the palladium layer. The nickel layer has a thickness that allows an RF signal received at the gold layer to penetrate the nickel layer and propagate in the conductive layer. Still in other implementations, the gold layer can be configured for wire bonding.

In some further implementations, the thickness of the nickel layer can be in the range from about 0.04 um to about 0.7 um. According to a number of implementations, the thickness of the nickel layer can be no more than about 0.5 um. According to certain implementations, the thickness of the nickel layer can be no more than about 0.35 um. According to some implementations, the thickness of the nickel layer can be no more than about 0.75 um.

In accordance with certain additional implementations, the thickness of the nickel layer can be less than the skin depth of nickel at a frequency of about 0.45 GHz. The conductive layer can include one or more of copper, aluminum, or silver according to some implementations. For instance, the conductive layer can include copper.

According to a number of implementations, substantially all of the RF signal can propagate in the conductive layer.

For purposes of summarizing the disclosure, certain aspects, advantages and novel features of the inventions have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of these aspects of the present the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein-throughout without necessarily achieving other advantages as may be taught or suggested in the entirety of this disclosure.

XI. Tantalum Nitride Terminated Through-Wafer Vias

Apparatus and methods for tantalum nitride terminated through-wafer vias are described herein and taken in combination with one or more of the other aspects, features, or characteristics of the present disclosure. In certain implementations thereof, a tantalum nitride (TaN) termination layer is formed on a first or front side of a gallium arsenide (GaAs) wafer, and a gold conductive layer is formed over the TaN termination layer. Thereafter, a through-wafer via is etched into a second or back side of the GaAs wafer so as to extend through the GaAs wafer and a first or inner portion of the TaN termination layer to reach the gold conductive layer. In certain implementations taken in combination herewith, the through wafer via is plated with a nickel vanadium (NiV) barrier layer, a gold seed layer, and a copper layer. During through-wafer via formation, a second or outer portion of the TaN termination layer is maintained and configured to surround an interface between the gold conductive layer and the copper layer so as to inhibit diffusion of copper into the GaAs wafer.

TaN terminated through-wafer vias can provide improved metal adhesion and reduced copper migration relative to schemes employing silicon nitride termination and a sputtered barrier layer. Furthermore, in certain implementations using a TaN termination layer to terminate a through-wafer via can permit the location or position of the through wafer via to be moved without changing fabrication or lithographical masks associated with transistor structures formed on the front side of the GaAs wafer. Configuring the through-wafer vias to be movable without changing lithographical mask associated with transistors can increase design flexibility and/or reduce time and cost associated with incremental fixes or tape-outs of integrated circuits designs that include the through-wafer vias.

XII. Via Density and Placement in Radio Frequency Shielding Applications

One aspect of this disclosure is a method of determining a via placement. The method includes obtaining electromagnetic interference data for an initial placement of vias around a radio frequency (RF) component. The RF component is positioned between a first conductive layer and a second conductive layer. The vias are included in a connection between the first conductive layer and the second conductive layer. The vias and the first and second conductive layers form at least a portion of an RF isolation structure around the RF component. The method also includes determining an updated placement of vias based at least in part on the electromagnetic interference data for the initial placement.

In some embodiments hereof, determining the updated placement of vias can include identifying, based on the electromagnetic interference data for the initial placement, a selected defined area around the perimeter of the RF component associated with higher electromagnetic interference than other defined areas around the perimeter of the RF component in the initial placement; and increasing density of the vias in the updated placement in the selected defined area compared to the density of the vias in the selected defined area in the initial placement. Alternatively or additionally, the method can include identifying, based on the electromagnetic interference data for the initial placement, a defined area around the perimeter of the RF component associated with a permissible level of electromagnetic interference in the initial placement; and decreasing density of the vias in the updated placement in the defined area compared to the density of the vias in the initial placement. According to certain embodiments, the electromagnetic interference data for the initial placement of vias corresponds to an unshielded RF component.

The method hereof can be iterated any suitable number of times. For instance, the method can include obtaining electromagnetic interference data for the updated placement of vias around the RF component; and determining another updated placement of vias based at least in part on the electromagnetic interference data for the updated placement.

In accordance with some embodiments, electromagnetic interference data can be obtained for at least two different modes of operation of the RF component in the initial placement of vias.

Another aspect of the invention of this disclosure is a packaged module. The packaged module includes a substrate configured to receive at least one component. The packaged module also includes a radio frequency (RF) component coupled to a major surface of the substrate. The packaged module includes a first conductive layer disposed below the RF component, in which the first conductive layer configured at a ground potential. The packaged module includes a plurality of vias in the substrate that are disposed around the RF component. The plurality of vias have a higher density in a first region of the packaged module than a second region of the packaged module, in which the first region is associated with a higher electromagnetic interference than the second region. The packaged module includes a second conductive layer disposed above the RF component. The second conductive layer is electrically coupled to the plurality of vias such that the first conductive layer, the plurality of vias, and the second conductive layer form at least a portion of an RF isolation structure around the RF component.

In certain embodiments hereof, the first region is disposed along a periphery of the packaged module and the second region is disposed along the periphery of the packaged module. According to some of these embodiments, the first region and the second region have approximately the same width in a dimension substantially parallel to an outer edge of the packaged module. The plurality of vias can be aligned along the periphery of the packaged module. The first region can have the highest via density of any region along the periphery of the packaged module that has an area at least as great as the first region, according to certain embodiments. The first region can have approximately the same area as the second region in some embodiments.

According to a number of embodiments of this aspect of the present invention, the RF component can be configured to emit more radiation to the first region than to the second region. Alternatively or additionally, the packaged module is configured such that the first region is exposed to more radiation than to the second region. In certain embodiments, the first region can correspond to a hot spot of the packaged module and the second region can correspond to a low radiating area of the packaged module. Alternatively or additionally, the first region can be more sensitive to external electromagnetic interference than the second region.

In certain embodiments relating hereto, the packaged module can also include conductive features forming at least a portion of an electrical connection between the plurality of vias and the second conductive layer, the RF isolation structure including the conductive features. For example, the conductive features can include wirebonds or a metal can. According to some embodiments, the RF component can include a power amplifier.

Another aspect of this invention is a packaged module that includes a substrate, an RF device, first and second conductive layers, and a plurality of vias. The substrate is configured to receive at least one component. The RF device is coupled to a major surface of the substrate. The first conductive layer is disposed below the RF component and configured at a ground potential. The plurality of vias are disposed around the RF component. The plurality of vias have a higher density in a first region around the RF component than a second region around the RF component having approximately the same area as the first region. The first region is more sensitive to external radiation than the second region. The second conductive layer is disposed above the RF component. The second conductive layer is electrically coupled to plurality of vias such that the first conductive layer, the plurality of vias, and the second conductive layer form at least a portion of an RF isolation structure around the RF component.

Yet another aspect of this disclosure is a wireless device that includes an antenna, a packaged module and another module. The antenna is configured to facilitate transmitting and/or receiving a radio frequency (RF) signal. The packaged module is in communication with the antenna. The packaged module includes a substrate having a ground plane and a plurality of vias in the substrate disposed along a periphery of the packaged module. Vias of the plurality of vias are spaced closer together along the periphery of the packaged module in a hot spot than in a low radiating area. The packaged module includes an RF circuit coupled to a major surface of the substrate. The packaged module also includes a second conductive layer disposed over the RF circuit. The second conductive layer is electrically coupled to plurality of vias such that the ground plane, the plurality of vias, and the second conductive layer form at least a portion of an RF isolation structure around the RF circuit. The other module is in communication with the packaged module.

In some embodiments hereof, the hot spot can be associated with electromagnetic interference generated by the packaged module and the plurality of vias can be configured to isolate the other module from the electromagnetic interference associated with the hot spot. According to certain embodiments, the hot spot can be associated with electromagnetic interference generated by the other module and the plurality of vias can be configured to shield the packaged module from electromagnetic interference associated with the hot spot.

In accordance with a number of embodiments, the packaged module further includes conductive features forming at least a portion of an electrical connection between the plurality of vias and the second conductive layer, in which the RF isolation structure includes the conductive features. The conductive features can include wirebonds, for example.

For purposes of summarizing the disclosure, certain aspects, advantages and novel features of the inventions have been summarized herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of the invention. Thus, these aspects of the present the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein-throughout without necessarily achieving other advantages as may be taught or suggested herein above or below.

XIII. Semiconductor Packages with Integrated Interference Shielding

Features and embodiments of this aspect of the present invention are directed to a semiconductor device package, and methods of making the same, that uses wirebond process technologies to integrate an electromagnetic interference shield into the device package. In one embodiment, wirebond processes are used to form wirebond springs that are positioned around the device and coupled to conductive layers above and below the device, thereby forming an electromagnetic interference shield around the device. As discussed further below, the shape of and spring effect created by the wirebond springs enable a robust manufacturing process to create reliable electrical connections between a conductive layer at the top of the molded package and a ground plane in the substrate of the package. The use of these wirebond springs provides a flexible solution for integrated electromagnetic interference shielding that may be applied to any over-molded device.

One aspect hereof is directed to a packaged semiconductor module having an integrated electromagnetic interference shield. In one embodiment, the packaged semiconductor module includes a substrate having a ground plane, an electronic device mounted on a surface of the substrate, a plurality of wirebond springs disposed about the electronic device and electrically coupled to the ground plane, a mold compound covering the electronic device and at least partially covering the plurality of wirebond springs, and a conductive layer disposed on a top surface of the mold compound and electrically coupled to at least some of the plurality of wirebond springs, wherein the plurality of wirebond springs, the conductive layer and the ground plane together include the integrated electromagnetic interference shield.

In one example, the conductive layer includes silver-filled epoxy. The wirebond springs can be made from various conductive materials, such as gold wire or copper wire. Each of the plurality of wirebond springs may include a continuous loop of wire shaped to provide a spring effect that permits contact between the conductive layer and the wirebond spring to provide the electrical coupling between the conductive layer and the wirebond spring. In one example, the electronic device is an RF device.

According to another embodiment hereof, a wirebond spring formed of a continuous loop of wire includes a ball bond, a zone of inflection, a crest, a convex region extending between the zone of inflection and the crest, a sloping tail region, and a substantially flat region extending between the crest and the sloping tail region, wherein the zone of inflection is between the convex region and the ball bond. In one example, the crest is substantially vertically above the zone of inflection. As discussed above, the wirebond spring may be formed from a variety of conductive materials, including gold wire or copper wire. In one example, wirebond springs having this structure are used in the semiconductor module discussed above.

Another aspect hereof is directed to a semiconductor module package having an integrated electromagnetic interference shield. In one embodiment, the semiconductor module package includes a substrate, first and second metallized connection points disposed on a first surface of the substrate, and a wirebond spring including a continuous wire extending between the first metallized connection point and the second metallized connection point. The wirebond spring includes a ball bond electrically connected to the first metallized connection point, a zone of inflection, a crest, a convex region extending between the zone of inflection and the crest, a substantially flat region proximate the crest, and a sloping tail region extending between the substantially flat region and the second metallized connection point. In one example, the semiconductor module package further includes a ground plane disposed on the substrate and electrically coupled to at least one of the first and second metallized connection points. In another example, the semiconductor module package further includes an electronic device, and a plurality of additional wirebond springs substantially identical to the wirebond spring, wherein the plurality of wirebond springs are positioned on the substrate about a perimeter of the electronic device. In another example, the semiconductor module package further includes a mold compound covering the electronic device and at least partially covering the plurality of wirebond springs, and a conductive layer disposed on a surface of the mold compound and electrically connected to at least some of the plurality of wirebond springs, wherein the ground plane, the conductive layer and the at least some of the plurality of wirebond springs together form the integrated electromagnetic interference shield.

Another aspect of these features of the present invention is directed to a method of manufacturing a module having an integrated electromagnetic interference shield. According to one embodiment, the method includes connecting an electronic device to a substrate, providing metallizations on the substrate, forming a plurality of wirebond springs connected to the metallizations, performing a transfer molding process to encapsulate the electronic device in mold compound and to at least partially cover the plurality of wirebond springs with the mold compound, and disposing a conductive layer on a surface of the mold compound, the conductive layer electrically connected to at least some of the plurality of wirebond springs. In one example, the method further includes ablating the surface of the mold compound, prior to disposing the conductive layer on the surface of the mold compound, to expose regions of at least some of the plurality of wirebond springs. In another example, providing metallizations includes providing a ground plane and at least one wirebond contact area electrically connected to the ground plane. In another example, forming the plurality of wirebond springs includes depositing a wire ball on the metallizations, forming a wire loop by drawing wire from the wire ball to form the wire loop having a first end connected to the wire ball and a second end, and connecting the second end to the metallizations. In another example, disposing the conductive layer on the surface of the mold compound includes painting a layer of silver-filled epoxy on the surface of the mold compound.

According to another embodiment hereof, an electronic module includes a substrate, an electronic device disposed on the substrate, and integrated electromagnetic interference shield formed from a plurality of discrete structures disposed substantially about the electronic device, the structures having a minimum spacing defined by a fraction of the wavelength of a signal to be shielded by the integrated electromagnetic interference shield. In one example, the fraction of the wavelength is 1/20. In another example, the plurality of discrete structures includes a plurality of wirebond springs, as discussed below.

Still other aspects, embodiments, and advantages of these exemplary aspects and embodiments, are discussed in detail below. Moreover, it is to be understood that both the foregoing information and the following detailed description are merely illustrative examples of various aspects and embodiments, and are intended to provide an overview or framework for understanding the nature and character of the claimed aspects and embodiments. Any embodiment disclosed herein may be combined with any other embodiment in any manner consistent with the objects, aims, and needs disclosed herein, and references to “an embodiment,” “some embodiments,” “an alternate embodiment,” “various embodiments,” “one embodiment” or the like are not necessarily mutually exclusive and are intended to indicate that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment. The appearances of such terms herein are not necessarily all referring to the same embodiment. The accompanying drawing figures are included to provide illustration and a further understanding of the various aspects, features, and characteristics of the various embodiments, and are incorporated in and constitute a part of this specification. The drawing figures, together with the remainder of the specification, serve to explain principles and operations of the various described and claimed aspects and embodiments.

The various aspects, characteristics, and features of the improved power amplifiers, power amplifier modules, and related systems, devices, and methods described herein are attained in accordance with the present invention wherein for one particular embodiment thereof, there is provided a power amplifier module including a power amplifier having a GaAs bipolar transistor with a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3×1016cm−3at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base. In this embodiment the module would further include an RF transmission line driven by the power amplifier, the RF transmission line including a conductive layer and finish plating on the conductive layer, the finish plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness that is less than about the skin depth of nickel at 0.9 GHz.

In the above embodiment, the power amplifier module may advantageously include further an output matching network with a first termination circuit configured to match a fundamental frequency of an output of the power amplifier and a second termination circuit configured to terminate at a phase of a harmonic of the output of the power amplifier in which the first termination circuit includes at least a portion of the RF transmission line.

According to one particular aspect hereof, the power amplifier may be included on a power amplifier die having a tantalum nitride terminated through wafer via. In this embodiment, the power amplifier die may further advantageously include a gallium arsenide (GaAs) substrate, a gold layer disposed on a first side of the GaAs substrate, and a copper layer disposed on a second side of the GaAs substrate that is opposite the first side with the tantalum nitride terminated through wafer via configured to electrically connect the gold layer to the copper layer. For additional embodiments thereof, the power amplifier die may further include a tantalum nitride termination region configured to surround at least a portion of an interface between the copper layer and the gold layer so as to inhibit a diffusion of copper from the copper layer into the GaAs substrate.

In any of the above embodiments, the GaAs bipolar transistor may be advantageously implemented as a heterojunction bipolar transistor (HBT) included on a power amplifier die and the power amplifier die may further include a resistor formed from at least one HBT layer.

Any of the above embodiments may alternatively further include a wirebond in contact with the gold layer of the RF transmission line, at least one edge adjacent the wirebond and at least one sidewall adjacent the at least one edge being free from the nickel layer of the RF transmission line, the palladium layer of the RF transmission line, and the gold layer of the RF transmission line.

In certain preferred embodiments of the above, the power amplifier module may further advantageously further include in combination (1) a dual mode control interface having a front end core configured to provide a serial interface, (2) a voltage input/output (VIO) pin configured to receive a VIO signal, this VIO signal determining whether an operating mode of the front end core is set to one of an active state and an inactive state, the dual mode control interface configured to provide a general purpose input/output (GPIO) interface when the front end core is set to the inactive state, (4) a combinational logic block configured to provide an enable signal and a mode signal to an enable level shifter and a mode level shifter, respectively, and (5) a power on reset configured to select the enable signal and the mode signal to provide to the enable level shifter and the mode level shifter, respectively, based on the VIO signal.

To achieve further advantages associated with the above embodiments, the power amplifier module may further include an RF isolation structure that includes wirebonds disposed along a periphery of the power amplifier module.

In accordance with another principal aspect of this invention, there is also provided a power amplifier module that includes a power amplifier configured to receive an RF input signal and to generate an amplified RF output signal, the power amplifier including a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3×1016cm−3at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base; and that further include in combination therewith an output matching network including a first termination circuit configured to match an impedance of a fundamental frequency of the amplified RF output signal, and a second termination circuit separate from the first termination circuit, the second termination circuit configured to terminate at a phase corresponding to a harmonic frequency of the amplified RF output signal. In this embodiment, the power amplifier may drives an RF transmission line having a diffusion barrier layer, the diffusion barrier layer including nickel and having a thickness of less than about 0.5 μm. And therein, there may be provided a wirebond electrically connecting an output of the power amplifier to the RF transmission line where the wirebond is included in the first termination circuit. Alternatively, this embodiment may advantageously include further a dual mode control interface configured to provide both a radio frequency front end (RFFE) serial interface and a three-mode general purpose input/output (GPIO) interface on a single die. And in combination therewith when desired, the power amplifier module may further include an RF isolation structure that has wirebonds disposed along the periphery of the power amplifier module.

According to yet another principal aspect of this invention there is alternatively provided a power amplifier module having (1) a power amplifier configured to receive an RF input signal and to generate an amplified RF signal, (2) an RF transmission line configured to propagate the amplified RF signal, the RF transmission line including a gold layer configured to receive the amplified RF signal, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, and a conductive layer proximate the diffusion barrier layer, the diffusion barrier layer including nickel and having a thickness of less than about the skin depth of nickel at 0.45 GHz, (3) a first termination circuit configured to match an impedance of a fundamental frequency of the amplified RF signal, the first termination circuit including at least a portion of the RF transmission line, and (4) a second termination circuit separate from the first termination circuit, the second termination circuit configured to terminate at a phase corresponding to a harmonic frequency of the amplified RF signal, the power amplifier electrically coupled to first termination circuit by way of at least one wirebond and the power amplifier electrically coupled to the second termination circuit by way of a different number of wirebonds than the first termination circuit. In this alternate embodiment, the power amplifier may advantageously include a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3×1016cm−3at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base. Any version of the power amplifier module of this specific embodiment may advantageously further include a dual mode control interface configured to provide both a radio frequency front end (RFFE) serial interface and a general purpose input/output (GPIO) interface on a single die, and in combination therewith or alternative thereto, an RF isolation structure that includes wirebonds disposed along a periphery of the power amplifier module.

In still another preferred embodiment of the present invention as directed to RF modules, there is provided a power amplifier module including (1) a substrate configured to receive a plurality of components, the substrate having an RF transmission line thereon, the RF transmission line having a conductive layer and finish plating on the conductive layer, the finish plating having a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer having nickel and having a thickness that is less than the skin depth of nickel at a frequency of about 0.45 GHz, (2) a first die coupled to the substrate, the first die having a power amplifier with an output electrically connected to the gold layer of the RF transmission line, the first die further having a passive component having a property that depends on one or more conditions of the first die, and the present module further including (3) a second die coupled to the substrate, the second die having a bias generating circuit configured to generate a bias signal based at least in part on an indicator of the property of the passive component of the first die.

According to another aspect of this invention, the particular embodiment of the module described in the paragraph above may further include an output matching network with a first termination circuit configured to match a fundamental frequency of the output of the power amplifier and a second termination circuit configured to terminate at a phase of a harmonic of the output of the power amplifier, the first termination circuit including at least a portion of the RF transmission line. And in combination therewith or in the alternative thereto, the module may be configured so that the first die has a tantalum nitride terminated through wafer via and/or includes an HBT device and a resistor formed from at least one HBT layer. As an additional aspect of this embodiment, the power amplifier module hereof may further include when desired an RF isolation structure that has a plurality of vias in the substrate disposed around the power amplifier, and a desired number of wirebonds disposed along a periphery of the power amplifier module, the plurality of vias having a higher density in a first region of the power amplifier module than a second region of the power amplifier module where the first region being associated with a higher electromagnetic interference than the second region.

In accordance with yet still another preferred embodiment of this invention, there is advantageously provided for certain applications a power amplifier module that includes a substrate configured to receive a plurality of components and further configured according to the following. The substrate has a finish plating that includes a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer. The diffusion barrier layer advantageously includes nickel and has a thickness that is less than about the skin depth of nickel at 0.45 GHz. This embodiment would also include in combination with the above, a power amplifier die having a power amplifier and at least one tantalum nitride terminated through wafer via. Here the power amplifier is configured to receive an RF input signal and also configured to generate an amplified RF signal. Finally as a principal element hereof, this embodiment would further advantageously include in combination with all the prior elements hereof a termination circuit configured to terminate at a phase of a harmonic of the amplified RF signal where such termination circuit is provided with at least one wirebond configured to electrically couple an output of the power amplifier to the gold layer of the finish plating.

In the embodiment described in the paragraph just above this paragraph, the power amplifier die thereof may advantageously include an on-die passive component, a first lead electrically connected to the on-die passive component, and a second lead configured to receive the amplified RF signal. In that specific implementation, a first portion of the finish plating may be electrically connected to the first lead and a second portion of the finish plating may be electrically connected to the second lead to thereby direct current from the first portion of the finish plating when such is so desired. In any of these embodiments, the power amplifier die may include a heterojunction bipolar transistor and resistor that includes a heterojunction bipolar material layer when desired. And in the alternative or in combination therewith, the power amplifier may include a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter where the collector has a doping concentration of at least about 3×1016cm−3at a junction with the base and the collector also has at least a first grading in which doping concentration increases away from the base. In one particular embodiment of the above, the power amplifier module may further advantageously include when so desired (1) a dual mode control interface that has a front end core configured to provide a serial interface, (2) a voltage input/output (VIO) pin configured to receive a VIO signal where the VIO signal determines whether an operating mode of the front end core is set to an active state or an inactive state where therein the dual mode control interface is configured to provide a general purpose input/output (GPIO) interface when the front end core is set to the inactive state, (3) a combinational logic block configured to provide an enable signal and a mode signal to an enable level shifter and a mode level shifter, respectively, and (4) a power on reset configured to select the enable signal and the mode signal to provide to the enable level shifter and the mode level shifter, respectively, based on the VIO signal.

The present application hereby incorporates by reference the entire disclosures of U.S. Provisional Patent Application Nos. 61/659,848 entitled POWER AMPLIFIER MODULE filed Jun. 14, 2012; 61/659,701 entitled PROCESS-COMPENSATED HBT POWER AMPLIFIER BIAS CIRCUITS AND METHODS filed Jun. 14, 2012; and 61/659,834 entitled RF POWER AMPLIFIERS HAVING SEMICONDUCTOR RESISTORS filed Jun. 14, 2012.

The present application also hereby incorporates by reference the entire disclosures of U.S. patent application Ser. No. 13/040,127 entitled WIRE BOND PAD SYSTEM AND METHOD filed Mar. 3, 2011; Ser. No. 13/040,137 entitled APPARATUS AND METHODS FOR REDUCING IMPACT OF HIGH RF LOSS PLATING filed Mar. 3, 2011; Ser. No. 13/460,521 entitled BIPOLAR TRANSISTOR HAVING COLLECTOR WITH GRADING filed Apr. 30, 2012; Ser. No. 13/658,488 entitled DUAL MODE POWER AMPLIFIER CONTROL INTERFACE WITH A TWO-MODE GENERAL PURPOSE INPUT/OUTPUT INTERFACE filed Oct. 23, 2012; Ser. No. 13/658,522 entitled DUAL MODE POWER AMPLIFIER CONTROL INTERFACE WITH A THREE-MODE GENERAL PURPOSE INPUT/OUTPUT INTERFACE filed Oct. 23, 2012; Ser. No. 13/543,472 entitled SIGNAL PATH TERMINATION filed Jul. 8, 2011; Ser. No. 12/939,474 entitled BIPOLAR AND FET DEVICE STRUCTURE filed Nov. 4, 2010; Ser. No. 13/288,427 entitled DEVICES AND METHODOLOGIES RELATED TO STRUCTURES HAVING HBT AND FET filed Nov. 3, 2011; Ser. No. 13/464,775 entitled TRANSMISSION LINE FOR HIGH PERFORMANCE RADIO FREQUENCY APPLICATIONS filed May 4, 2012; Ser. No. 13/485,572 entitled VIA DENSITY AND PLACEMENT IN RADIO FREQUENCY SHIELDING APPLICATIONS filed May 31, 2012; Ser. No. 13/893,605 entitled SYSTEMS AND METHODS FOR PROVIDING ELECTROMAGNETIC INTERFERENCE SHIELDING FOR INTEGRATED CIRCUIT MODULES filed May 14, 2013; Ser. No. 13/893,614 entitled SYSTEMS AND METHODS FOR CONTROLLING ELECTROMAGNETIC INTERFERENCE FOR INTEGRATED CIRCUIT MODULES filed May 14, 2013; and Ser. No. 13/904,566 entitled SEMICONDUCTOR PACKAGE HAVING A METAL PAINT LAYER filed May 29, 2013.

In addition, the present application hereby incorporates by reference the entire disclosures of International Application Nos. PCT/US2008/071832 entitled WIREBOUND SPRING CONNECTORS AND METHOD OF MANUFACTURING FOR INTEGRATED EMI SHIELDING filed Jul. 31, 2008 and PCT/US2011/059208 entitled DEVICES AND METHODOLOGIES RELATED TO STRUCTURES HAVING HBT AND FET filed Nov. 3, 2011.

