CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2018-0162196 filed on Dec. 14, 2018, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field

Exemplary embodiments relate to a variable resistance semiconductor device which has an oxidation-resistant electrode.

2. Discussion of the Related Art

A variable resistance semiconductor device has attracted attention as an SCM (storage class memory) device because it has low production cost, is relatively simple to manufacture, has excellent yield and scalability, and has advantages of both a DRAM and a flash memory. Also, the variable resistance semiconductor device may be used in mobile devices due to its low power consumption and high degree of integration. However, the use of a variable resistance semiconductor device in a 3D cross-point structure, for example, includes a selector device to resolve the sneak current and interference between adjacent memory cells, and solutions are still in development with respect to sensing errors and sneak current so that the device can be widely used as a high integration and low power consumption applications.

SUMMARY

Various embodiments are directed to a variable resistance semiconductor device with an improved voltage sensing margin.

Also, various embodiments are directed to a variable resistance semiconductor device with a low switching failure rate.

Further, various embodiments are directed to a method for manufacturing the variable resistance semiconductor device.

In an embodiment, a variable resistance semiconductor device may include: a lower conductive wiring; a bottom electrode over the lower conductive wiring; a selection element pattern over the bottom electrode; a first intermediate electrode over the selection element pattern; a second intermediate electrode over the first intermediate electrode; a variable resistance element pattern over the second intermediate electrode; a top electrode over the variable resistance element pattern; and an upper conductive wiring over the top electrode. The first intermediate electrode may include a first material. The second intermediate electrode may include a second material which has a better oxidation resistance and a higher work function than the first material.

The first material may include at least one among titanium nitride (TiN), titanium carbon nitride (TiCN), titanium aluminum nitride (TiAlN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), carbon (C) and amorphous carbon (α-C). The second material may include ruthenium (Ru), cobalt (Co), palladium (Pd), nickel (Ni), rhenium (Re), iridium (Ir), platinum (Pt), aurum (Au), rhodium (Rh), lead (Pb), iridium oxide (IrO2), ruthenium oxide (RuO2), rhenium oxide (ReO2), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), ruthenium-hafnium (RuHf), ruthenium-tantalum (RuTa), ruthenium-titanium (RuTi), ruthenium-zirconium (RuZr), ruthenium-silicon (RuSi), iridium-hafnium (IrHf), iridium tantalum (IrTa), iridium-titanium (IrTi), iridium-zirconium (IrZr), iridium-silicon (IrSi).

The bottom electrode may include one among titanium nitride (TiN), titanium carbon nitride (TiCN), titanium aluminum nitride (TiAlN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), carbon (C) and amorphous carbon (α-C).

The selection element pattern may include one among an Ovonic threshold switching (OTS) material layer, a Schottky diode, a metal-insulator-metal (MIM), a PN junction diode, a metal-insulator transition (MIT) material layer, a mixed ionic electronic conduction (MIEC) material layer and a silicon doped with arsenic (As) ions.

The variable resistance element pattern may include one among a metal oxide such as hafnium oxide (HfO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), gadolinium oxide (Gd2O3), lanthanum oxide (La2O3) or ytterbium oxide (Yb2O3), silicon oxide (SiO2), a metal oxide containing at least two metals among hafnium (Hf), tantalum (Ta), titanium (Ti), zirconium (Zr), tungsten (W), aluminum (Al), gadolinium (Gd), lanthanum (La), ytterbium (Yb) and iridium (Ir), a chalcogenide-based alloy; or a conductive bridge RAM (CBRAM) material.

The variable resistance semiconductor device may further include a reservoir pattern interposed between the variable resistance element pattern and the top electrode. The reservoir pattern may include one among hafnium (Hf), tantalum (Ta), titanium (Ti), silicon (Si), titanium oxide (TiOx), tungsten (W), and combinations thereof.

The variable resistance semiconductor device may further include a resistive barrier layer interposed between the bottom electrode and the selection element pattern. The resistive barrier layer may include an oxide containing at least one among silicon (Si), hafnium (Hf), tantalum (Ta), titanium (Ti), zirconium (Zr) and aluminum (Al).

The variable resistance semiconductor device may further include a first spacer conformally formed on sidewalls of the top electrode and the variable resistance element pattern. The first spacer may include a dielectric material.

The variable resistance semiconductor device may further include a second spacer conformally formed on sidewalls of the bottom electrode, the selection element pattern, the first intermediate electrode, the second intermediate electrode and the first spacer. The second spacer may include a dielectric material.

In an embodiment, a variable resistance semiconductor device may include: a lower conductive wiring; a bottom electrode over the lower conductive wiring; a selection element pattern over the bottom electrode; a lower intermediate electrode over the selection element pattern; an upper intermediate electrode over the lower intermediate electrode; a variable resistance element pattern over the upper intermediate electrode; a top electrode over the variable resistance element pattern; and an upper conductive wiring over the top electrode. The lower intermediate electrode may include one of titanium nitride and amorphous carbon. The upper intermediate electrode may include one of ruthenium and ruthenium oxide.

The variable resistance semiconductor device may further include an adhesion layer between the lower intermediate electrode and the selection element pattern. The bottom electrode may include titanium nitride (TiN) or amorphous carbon (α-carbon).

The variable resistance semiconductor device may further include a reservoir pattern interposed between the variable resistance element pattern and the top electrode. The reservoir pattern may include one among hafnium (Hf), tantalum (Ta), titanium (Ti), silicon (Si), titanium oxide (TiOx), tungsten (W), and combinations thereof.

The variable resistance semiconductor device may further include a resistive barrier layer interposed between the bottom electrode and the selection element pattern. The resistive barrier layer may include an oxide containing at least one among silicon (Si), hafnium (Hf), tantalum (Ta), titanium (Ti), zirconium (Zr) and aluminum (Al).

The variable resistance semiconductor device may further include a first spacer conformally formed on sidewalls of the top electrode and the variable resistance element pattern. The first spacer may include a dielectric material.

The variable resistance semiconductor device may further include a second spacer conformally formed on sidewalls of the bottom electrode, the selection element pattern, the lower intermediate electrode, the upper intermediate electrode and the first spacer. The second spacer may include a dielectric material.

In an embodiment, a variable resistance semiconductor device may include: a lower conductive wiring; a bottom electrode over the lower conductive wiring; a selection element pattern over the bottom electrode; a lower intermediate electrode over the selection element pattern; an upper intermediate electrode over the lower intermediate electrode; a resistance element pattern over the upper intermediate electrode; a top electrode over the resistance element pattern; and an upper conductive wiring over the top electrode. The upper intermediate electrode may include a material which has a better oxidation resistance and a higher work function than the lower intermediate electrode.

The variable resistance semiconductor device may further include a reservoir pattern interposed between the resistance element pattern and the top electrode. The reservoir pattern may include one among hafnium (Hf), tantalum (Ta), titanium (Ti), silicon (Si), titanium oxide (TiOx), tungsten (W), and combinations thereof.

The variable resistance semiconductor device may further include a resistive barrier layer interposed between the bottom electrode and the selection element pattern. The resistive barrier layer may include an oxide containing at least one among silicon (Si), hafnium (Hf), tantalum (Ta), titanium (Ti), zirconium (Zr) and aluminum (Al).

The variable resistance semiconductor device may further include a first spacer conformally formed on sidewalls of the top electrode and the resistance element pattern; and a second spacer conformally formed on sidewalls of the bottom electrode, the selection element pattern, the lower intermediate electrode, the upper intermediate electrode and the first spacer. The first and second spacers may include silicon nitride.

The variable resistance semiconductor device according to the technical idea of the disclosure may have an improved voltage sensing margin and a low switching failure rate.

In an embodiment, a method of forming a variable resistance memory device, the method comprising: forming a lower conductive wiring; forming a bottom electrode over the lower conductive wiring; forming a selection element pattern over the bottom electrode; forming a lower intermediate electrode over the selection element pattern; forming an upper intermediate electrode over the lower intermediate electrode; forming a variable resistance element pattern over the upper intermediate electrode; forming a top electrode over the variable resistance element pattern; and forming an upper conductive wiring over the top electrode. The upper intermediate electrode has a better oxidation resistance and a higher work function than the lower intermediate electrode.

The method of forming a variable resistance memory device may further include forming a reservoir pattern between the variable resistance element pattern and the top electrode. The reservoir pattern may include one among hafnium (Hf), tantalum (Ta), titanium (Ti), silicon (Si), titanium oxide (TiOx), and tungsten (W).

The method of forming a variable resistance memory device may further include forming a resistive barrier layer between the bottom electrode and the selection element pattern. The resistive barrier layer may include an oxide containing at least one among silicon (Si), hafnium (Hf), tantalum (Ta), titanium (Ti), zirconium (Zr) and aluminum (Al).

The upper intermediate electrode comprises RuO2. The lower intermediate electrode comprises titanium nitride.

In an embodiment, a method of forming a variable resistance memory device, the method comprising: forming a selection element comprising a lower electrode, a selection element pattern and an intermediate electrode; and forming a resistance element comprising a variable resistance element pattern, a reservoir pattern and a top electrode. The intermediate electrode is comprised of a lower intermediate electrode and an upper intermediate electrode, and the upper intermediate electrode comprises ruthenium oxide (RuO2).

The lower intermediate electrode comprises a metal with a lower work function and a lower oxidation resistance compared to ruthenium oxide (RuO2). The lower intermediate electrode comprises titanium nitride.

