CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2019-0000372, filed on Jan. 2, 2019, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a semiconductor circuit, and more particularly, to a power control circuit, a semiconductor apparatus including the same and a power control method of the semiconductor apparatus.

2. Related Art

Recently, electronic devices, for example, portable electronic devices have been reduced in size and weight.

In particular, since the portable electronic device is operated by limited power, i.e. a battery, power consumption of the portable electronic device needs to be reduced.

The portable electronic device may operate in a power down mode to reduce the power consumption.

The power down mode may include a normal power down mode and a deep sleep mode (or deep power down mode).

The deep sleep mode needs to guarantee a longer power down interval than the normal power down mode.

The portable electronic device employs a power gating technique for preventing unnecessary power supply to function blocks in the power down mode.

The portable electronic device may necessarily include a semiconductor memory apparatus in order to perform the natural function thereof, to store data, and to perform an application program.

When the semiconductor memory apparatus includes volatile memory cells each composed of one transistor and one capacitor, data is stored in the capacitor.

Since a leakage current occurs due to the characteristic of the capacitor, the semiconductor memory apparatus performs a refresh operation of rewriting the data stored in the memory cell at each predetermined time, in order to retain the data stored in the memory cell for a long time.

Refresh operations may be classified as an auto refresh operation and a self refresh operation.

The auto refresh operation may be performed according to a command from a host, for example, a memory controller.

The self refresh operation may be performed by the semiconductor memory device itself. For example, the self refresh operation may be performed during the deep sleep mode.

SUMMARY

Various embodiments are directed to a power control circuit capable of reducing power consumption, a semiconductor apparatus including the same, and a power control method of a semiconductor apparatus.

In an embodiment, a power control circuit may include: a power control signal generation circuit configured to generate a voltage control signal according to a deep sleep command for operating a semiconductor apparatus in a deep sleep mode; a voltage divider circuit having a division ratio that is changed according to the voltage control signal, and configured to generate a divided voltage by dividing an internal voltage at the changed division ratio; a comparator configured to generate a detection signal by comparing a reference voltage to the divided voltage; an oscillator configured to generate an oscillation signal according to the detection signal; and a pump configured to generate the internal voltage according to the oscillation signal.

In an embodiment, a semiconductor apparatus may include: a memory region; a refresh control circuit configured to perform a refresh operation on the memory region using an internal voltage, according to a refresh command; and a power control circuit configured to adjust the level of the internal voltage to a second level during a deep sleep mode interval, the second level being lower than a first level which is set for operation intervals other than the deep sleep mode interval.

In an embodiment, a power control method of a semiconductor apparatus may include the steps of: generating an internal voltage at a first level when the semiconductor apparatus enters a normal power down mode; generating the internal voltage at a second level lower than the first level when the semiconductor apparatus enters a deep sleep mode; and raising the level of the internal voltage to the first level from the second level when the semiconductor apparatus exits from the deep sleep mode.

