CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit under 35 U.S.C. § 119(a) of European Application No. 18212913.0 filed Dec. 17, 2018 the contents of which are incorporated by reference herein in their entirety.

BACKGROUND OF THE DISCLOSURE

1. Field of the Disclosure

The present disclosure relates to a semiconductor chip scale package (CSP) and method of forming a semiconductor chip scale package. More specifically, the disclosure relates a semiconductor CSP marked with a colour-coded marking to form a machine and human readable identifier and a methods of forming a semiconductor CSP with such marking.

2. Description of the Related Art

Semiconductor devices are generally manufactured and packaged as individual devices such as diodes or transistors, or as integrated circuits ICs, each integrated circuit chip typically comprising thousands or several million interconnected electrical devices fabricated on a single compact semiconductor substrate or wafer.

The fabrication of semiconductor integrated circuits may involve two processing stages: the front-end-of-line (FEOL) processing stage and the back-end-of-line (BEOL) processing stage. The FEOL covers everything up to, but not including, the deposition of metal interconnect layers. At this stage, the patterning of the individual electronic devices that form part of the integrated circuit directly onto a semiconductor substrate or wafer takes place. A process known as front-end surface engineering also occurs, which comprises the growing of surface oxides to form elements such as gate dielectrics, the patterning of such gate devices and/or any essential electronic elements, for example, channels, source and drain regions, and the implantation or diffusion of dopants to produce the suitable charge carriers in the semiconductor material required to achieve the desired device characteristics.

The BEOL processing stage commences upon completion of the FEOL processing. At this stage, electrical contacts or pads, interconnect wires, vertical electrical connections that pass through a semiconductor wafer (vias) and dielectric structures are formed. Typically, more than ten metal layers can be added to a modern IC during the BEOL process. Also included in this stage is the cutting or singulating of the finished wafer into individual semiconductor die. Each of the separated dies are then packaged for structural support, package interconnect and ingress protection. For example, the separated individual dies may be mounted on a bespoke package substrate having pins or contact pads for interconnection with other system components. Internal to the bespoke package, the contact pads on the semiconductor die are electrically connected to the contact pads within the package to complete the circuit.

A chip scale package (CSP) is an example of an integrated circuit or a discrete package that employs FEOL and BEOL processes during fabrication. In accordance with industry standards, a CSP should have a package area or footprint that is no greater than 1.2 times that of the semiconductor die encapsulated within the package and the CSP must be in the form of a single-die, direct surface-mountable package. CSPs generally have no packaging comprising an insulation material used to encapsulate and protect the semiconductor dies. The back or top portion of the device is exposed for receiving pattern marking for chip identification purposes. A pattern mark may for example include a part number, a date of manufacture, a company logo, a place of manufacture, or any other information.

Small CSPs have a relatively small surface area on the back or top exposed portion, which may make pattern marking for chip identification problematic using existing marking technologies, because there is limited space for such marking.

Known pattern marking technologies include, for example, laser ablation, photolithography or photolithography with subsequent etching. In laser ablation, a beam of a laser is focused onto a semiconductor substrate thereby breaking down the chemical bonds within the area to which the beam is applied and selectively removing material on the surface of the substrate. In laser ablation, the laser intensity, pulse length, and wavelength, as well as the semiconductor material itself, influence the amount of surface material to be removed. During microfabrication, photolithography may also be used to transfer a desired pattern marking to a film or semiconductor substrate by applying light through a photomask to a light-sensitive chemical “photoresist” on the semiconductor substrate. Both marking process are limited either by the resolution of the laser for the ablation process or by the resolution of the inspection camera at customer side.

A pattern marking on a CSP smaller than chip package size code 0603 (i.e. an approximate package dimension of 0.6 mm×0.3 mm) is limited by the resolution of the pattern processes and tools used. Small pattern markings are generally expensive and difficult to create. For example, on a 0603 product, the back or top portion of the package typically only provides an exposed area sufficient to accommodate a single patterned character using laser ablation. The variability of a single patterned character or single digit is therefore limited to approximately 26 letters and 10 numbers.

Another issue that may arise relates to the optical recognition of product pattern markings in small CSPs using optical inspection tools. Small features used in such product markings may not be of a suitable resolution that would allow an optical inspection tool to correctly read and identify a CSP product.

Aspects and embodiments of the disclosure have been devised with the foregoing in mind.

SUMMARY

According to an aspect of the present disclosure, there is provided a semiconductor chip scale package comprising: a semiconductor die, the semiconductor die comprising: a first major surface opposing a second major surface; a plurality of side walls extending between the first major surface and second major surface; a plurality of electrical contacts arranged on the second major surface of the semiconductor die; and an insulating material disposed on the plurality of side walls and on the first major surface, said insulating material comprising a machine readable identifier by which a semiconductor chip scale packaging type is identifiable by an identification apparatus that reads said machine readable identifier, wherein said machine readable identifier comprises a colour component.

This disclosure relates to colour coded marking on at least the back/top/side of a CSP. Employing colour coding in this manner may place no limitations on the resolution of any optical recognition optics (e.g. an identification apparatus for identifying a type of CSP based upon the machine readable identifier) or to any resolution of optical patterning for marking creation. A machine readable marking to allow identification of CSP type may be possible even for cases where conventional marking types (e.g. characters, or other forms of marking) would not be suitable, because such marking types would be too small to be discernible.

A spectrum of wavelengths of visible light, giving a range of colours, may be achieved using the marking method of the present disclosure. This is employed to code/label/mark a semiconductor CSP in the manner described above and hereinafter. Observation of such a spectrum, by the identification apparatus, may require a less complex apparatus than is required in prior art identification methods, where more complex apparatus may be required to read patterns and/or characters that are of a small size.

The colour-coded marking of this disclosure may also be employed in combination with, for example, pattern markings, which may increase the variability. For example, the variability may be increased to (26 letters plus 10 numbers) multiplied by applicable colours.

Optionally, the machine readable identifier may comprise a metal oxide.

Optionally, the colour component may comprise a, or the, metal oxide.

Optionally, the machine readable identifier may comprise aluminium oxide.

Optionally, the machine readable identifier may comprise titanium dioxide.

Optionally, the insulating material comprises a layer of thickness, or a plurality of layers of combined thickness: 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, 125 nm, 130 nm, 135 nm, 140 nm, 145 nm, 150 nm, 155 nm, 160 nm, 165 nm, 170 nm, 175 nm, 180 nm, 185 nm, 190 nm, 195 nm, 200 nm, 205 nm, 210 nm, 215 nm, 220 nm, 225 nm, 230 nm, 235 nm, 240 nm, 245 nm, 250 nm, 255 nm, 260 nm, 265 nm, 270 nm, 275 nm, 280 nm, 285 nm, 290 nm, 295 nm, 300 nm, 305 nm, 310 nm, 315 nm, 320 nm, 325 nm, 330 nm, 335 nm, 340 nm, 345 nm, or 350 nm, wherein said thickness determines a colour of said colour component of said machine readable identifier. The thickness of a metal oxide layer, or thickness of multiple metal oxide layers, can provide different colours. That is, the colour of the insulating material may depend upon the thickness of the material that makes up the insulating material layer.

Optionally, the insulating material may be formed as a conformal layer on the semiconductor die by atomic layer deposition, or low temperature PECVD.

Optionally, the colour component may comprise an additive to said insulating material. Further optionally, the additive may comprise a dye, or paint.

Optionally, the colour component may comprise an additive disposed in a layer on an outer surface of the insulating material. Further optionally, the additive may comprise a dye, or paint.

Optionally, the colour component may comprise an additive disposed in a layer on an inner surface of the insulating material. Further optionally, the additive may comprise a dye, or paint.

Optionally, the colour component may be formed using surface structures formed in surfaces and/or side walls of the die. Further optionally, the surface structures may comprise optical lattices.

