CROSS-REFERENCE TO RELATED APPLICATIONS

This is the first application filed for the instantly disclosed technology.

FIELD OF THE INVENTION

The present invention generally relates to the field of communication systems and, in particular, to systems and methods for a low jitter phase-lock loop (PLL) based frequency synthesizer.

BACKGROUND

Phase-lock loops (PLL) are critical electronic circuits commonly employed in several communications systems such as radio, telecommunications, computers, and other electronic applications. As such PLL circuits are configured to provide, for example, local oscillator (LO) signals for transceiver circuits, clock signals for data-recovery circuits, etc. In general, the PLL circuit uses a feedback to maintain an output signal of the PLL circuit in a specific phase relationship with a reference input signal of the PLL circuit, as is well known in the art. When the output frequency of the PLL is equal to the frequency of the reference input signal, the PLL circuit is in a “locked” condition.

Apart from generating the output signals in specific phase relationship with the reference input signal, PLL circuits are also configured to synthesize frequency signals for various applications. In such applications, the PLL circuit acts as a frequency synthesizer and is configured to generate one or more of a plurality of new frequency signals based on harmonics of the reference input signal. Typically, the PLL based frequency synthesizer employs a programmable frequency divider in the PLL circuit feedback loop.

In general, the PLL based frequency synthesizer may be implemented as an “integer-N” synthesizer or “fractional-N” synthesizers, depending on the frequency division ratio N. In particular, with the integer-N synthesizer, the division ratio N is selected such that the output frequency of the integer-N synthesizer is only an integer multiple of the reference frequency. The integer-N synthesizer is advantageous in terms of having a simple design and having fewer spurs in the output spectrum.

On the other hand, a fractional-N synthesizer allows frequencies equal to fractional multiples of the reference frequency to be synthesized. That is, the division ratio N can be a fractional number. The fractional-N synthesizer has several benefits over integer-N synthesizers. Such benefits may include increased loop bandwidth, suppression of the phase noise associated with a voltage control oscillator (VCO) over a larger range. Also, with smaller division factor may result in reduced in-band phase noise.

However, it will be appreciated that the implementing fractional-N synthesizer presents certain challenges to the communication systems. One such challenge is that such the communication systems need to employ hardware, software, and firmware elements that are capable of operating at higher speeds to synthesize high frequency signals.

These challenges may be exacerbated by certain proposed enhancements to the existing communication systems as well as next-generation communication designs. Such enhancements and designs include the deployment of high speed delta-sigma modulator, etc. Such enhancements and designs potentially strain the receiver hardware and software processing resources that are currently implemented.

SUMMARY

The present disclosure generally provides a low jitter phase-lock loop (PLL) based frequency synthesizer. The low jitter PLL based frequency synthesizer may generate frequencies with 1 part per billion (PPB) frequency resolution. In certain embodiments, a low frequency (<=500 MHZ) first order DSM with 29 bits frequency control word resolution may be employed in the low jitter PLL based frequency synthesizer to meet the 1 PPB frequency resolution requirement with ultra-low power and area digital core.

Also, the low jitter PLL based frequency synthesizer may achieve a low phase interpolation integral non-linearity, which may be translated in a low spurious response of the low jitter PLL. In certain embodiments, an analog phase interpolation pre-distortion and input conditioning techniques may be applied to achieve the integral non-linearity of 0.75-1.5 ps. Also, analog modulation to phase modulation in the CML-to-CMOS first stage degenerated feedback inverter further reduces phase interpolation integral non-linearity. It is to be noted that integral non-linearity reduction leads to low phase errors during fractional operations at any fractional ratio of frequency, therefore improving the low jitter PLL spurious response.

Further, the low jitter PLL based frequency synthesizer may reduce Delta-Sigma modulator (DSM) noise during fractional operations while using low order DSM architectures which require low order PLL filtering. In certain embodiments, the low jitter PLL based frequency synthesizer may employ a parallel to serial converter serializing the 500 MHz parallel interface of 8×7 bits phase interpolation control words, coming out of the DSM, into a serial phase interpolation code sequence changing at 4 GHz rate, essentially creating equivalent DSM running at 4 GHz clock rate. Such a high rate of DSM clock noise which is far beyond PLL loop bandwidth corner, allows complete filtering of DSM noise. Hence fractional operations are affected mostly by the phase interpolation integral non-linearity, which has already been made as low as possible.

With this said, an object of the present disclosure is to provide a low jitter PLL based frequency synthesizer, comprising a first frequency divider configured to divide a reference frequency associated with an input signal Vinby an factor M, a phase frequency detector configured to generate an error voltage signal, a charge pump configured to generate an error current signal corresponding to the error voltage signal, a low-pass filter configured to filter the error current signal, a voltage control oscillator (VCO), communicatively coupled to the low-pass filter, configured to generate an output signal VVCO_frachaving a fractional frequency, wherein the fractional frequency is Cfractimes the reference frequency associated with the input signal Vin, Cfracbeing an integer or a fractional value, a phase interpolator communicatively coupled in a feedback path between the VCO and the phase frequency detector, wherein the phase interpolator comprises, a quadrature generator configured to generate a plurality of phase shifted signals from the output signal VVCO_frac, an input conditioner configured to perform wave shaping of the plurality of phase shifted signals, an input conditioner configured to perform wave shaping of the plurality of phase shifted signals, a phase rotator, wherein the phase rotator is configured to, receive a wave shaped plurality of phase shifted signals, provide positive or negative phase shifts to the wave shaped plurality of phase shifted signals in accordance with a control signal, generate a rotation frequency in accordance with the positive or negative phase shifts provided to the wave shaped plurality of phase shifted signals, provide an updated output signal VVCO_inthaving an integer frequency closest to the fractional frequency by removing the rotational frequency from the output signal VVCO_frachaving the fractional frequency, a current mode logic (CML) to complementary metal-oxide-semiconductor (CMOS) converter configured to receive CML differential voltage levels associated with the updated output signal VVCO_intand convert CML differential voltage levels to CMOS compatible voltage levels, a second frequency divider communicatively coupled in the feedback path between the phase interpolator and the phase frequency detector configured to divide the integer frequency associated with the updated output signal VVCO_intby a factor Na×Nb, wherein, Naand Nbare feedback division ratios associated with the second frequency divider and provides a difference signal Vdiffto the phase frequency detector.

In accordance with other aspects of the present disclosure, the PLL based frequency synthesizer, wherein the CML to CMOS converter comprises three AC coupled stages.

In accordance with other aspects of the present disclosure, the PLL based frequency synthesizer, wherein the first AC coupled stage is configured to convert the amplitude modulated CML differential voltage levels associated with the updated output signal VVCO_intto phase modulated CMOS differential voltage levels.

In accordance with other aspects of the present disclosure, the PLL based frequency synthesizer, wherein the first AC coupled stage further comprises a first capacitor, a second capacitor, a first inverter, a second inverter, a first resistive feedback and a second resistive feedback, wherein the first resistive feedback and the second resistive feedback are adjustable.

In accordance with other aspects of the present disclosure, the PLL based frequency synthesizer, wherein the second AC coupled stage is configured to perform correction of the duty cycle associated with the CML differential voltage levels associated with the updated output signal VVCO_int.

In accordance with other aspects of the present disclosure, the PLL based frequency synthesizer, wherein the AC coupled stage further comprises a third capacitor, a fourth capacitor, a third inverter, a fourth inverter, a third resistive feedback and a fourth resistive feedback, wherein the third resistive feedback and the fourth resistive feedback are adjustable.

In accordance with other aspects of the present disclosure, the PLL based frequency synthesizer, wherein the third AC coupled stage is configured to provide amplitude amplification to the output of the second stage of the CML to CMOS converter.

In accordance with other aspects of the present disclosure, the PLL based frequency synthesizer, wherein the quadrature generator is a divider by two based quadrature generator.

In accordance with other aspects of the present disclosure, the PLL based frequency synthesizer, wherein the quadrature generator is an all path quadrature generator.

In accordance with other aspects of the present disclosure, the PLL based frequency synthesizer, wherein the quadrature generator is a poly-phase filter based quadrature generator.

In accordance with other aspects of the present disclosure, the PLL based frequency synthesizer, wherein the quadrature generator is a RC ladder network based quadrature generator.

In accordance with other aspects of the present disclosure, the PLL based frequency synthesizer, wherein the quadrature generator is a LC ladder network based quadrature generator.

In accordance with other aspects of the present disclosure, the PLL based frequency synthesizer, wherein the input conditioner configured to change the wave shape the plurality of phase shifted signals to triangular waves.

In accordance with other aspects of the present disclosure, the PLL based frequency synthesizer, wherein the control signal is generated by a phase interpolator (PI) controller.

In accordance with other aspects of the present disclosure, the PLL based frequency synthesizer, wherein the PI controller further comprises a frequency-to-phase converter configured to receive a frequency control word (FCW) and convert a frequency associated with the associated with the FCW to a phase, a Delta-Sigma modulator (DSM) configured to generate a step signal in accordance with the FCW, a sub-step calculator configured to generate sub-step signals corresponding to the step signal, a parallel to serial converter configured to receive sub-step signals in parallel and convert the parallel sub-step signals into a serial signal representing the control signal.

In accordance with other aspects of the present disclosure, the PLL based frequency synthesizer, further comprising a third frequency divider.

In accordance with other aspects of the present disclosure, the PLL based frequency synthesizer, wherein the third frequency divider is configured to divide the fractional frequency by a first factor K1and a second factor K2, wherein the second factor K2is greater than the first factor K1.

In accordance with other aspects of the present disclosure, the PLL based frequency synthesizer, the DSM is further configured to operate on a clock frequency equals to the fractional frequency divided by the first factor K1.

In accordance with other aspects of the present disclosure, the PLL based frequency synthesizer, the parallel to serial converter is further configured to operate on a clock frequency equals to the fractional frequency divided by the first factor K2.

In accordance with other aspects of the present disclosure, the PLL based frequency synthesizer, wherein the rotation frequency is based on a difference between the fractional frequency and the integer frequency.

Another object of the present disclosure is to provide a method for synthesizing fractional frequency comprising dividing, by a first frequency divider, a reference frequency associated with an input signal Vinby an factor M, generating, by a phase frequency detector, an error voltage signal, generating, by a charge pump, an error current signal corresponding to the error voltage signal, filtering, by a low-pass filter, the error current signal, generating, by a voltage control oscillator (VCO), an output signal VVCO_frachaving a fractional frequency, wherein the fractional frequency is Cfractimes the reference frequency associated with the input signal Vin, Cfracbeing an integer or a fractional value, generating, by a quadrature generator, a plurality of phase shifted signals from the output signal VVCO_frac, performing, by an input conditioner, wave shaping of the plurality of phase shifted signals, receiving, by a phase rotator, wave shaped plurality of phase shifted signals, providing, by the phase rotator, positive or negative phase shifts to the wave shaped plurality of phase shifted signals in accordance with a control signal, generating, by the phase rotator, a rotation frequency in accordance with the positive or negative phase shifts provided to the wave shaped plurality of phase shifted signals, providing, by the phase rotator, an updated output signal VVCO_inthaving an integer frequency closest to the fractional frequency by removing the rotational frequency from the output signal VVCO_frachaving the fractional frequency, receiving, by a current mode logic (CML) to complementary metal-oxide-semiconductor (CMOS) converter, CML differential voltage levels associated with the updated output signal VVCO_int, converting, by the CML to CMOS converter, CML differential voltage levels to CMOS compatible voltage levels, dividing, by a second frequency divider, the integer frequency associated with the updated output signal VVCO_intby a factor Na×Nb, wherein, Naand Nbare feedback division ratios associated with the second frequency divider, providing, by the second frequency divider, a difference signal Vdiffto the phase frequency detector.

