FIELD

One or more aspects of embodiments according to the present disclosure relate to function-in-memory computation, and more particularly to a system and method for performing function-in-memory computation with a cache coherent protocol interface.

BACKGROUND

The background provided in this section is included only to set context. The content of this section is not admitted to be prior art. Function-in-memory computing may have advantages over other computing configurations, in that the total bandwidth for data paths between memory and a plurality of function-in-memory circuits may be significantly greater than the bandwidth of a data path between a memory and a central processing unit (CPU) or a graphics processing unit (GPU). Implementing function-in-memory computing may be challenging, however, in part because the execution of operations by the function-in-memory circuits may affect the latency of the operation of the memory.

Thus, there is a need for an improved system and method for performing function-in-memory computing.

SUMMARY

According to an embodiment of the present invention, there is provided a system for computing, the system including: a memory, the memory including one or more function-in-memory circuits; and a cache coherent protocol interface circuit having a first interface and a second interface, a function-in-memory circuit of the one or more function-in-memory circuits being configured to perform an operation on operands including a first operand retrieved from the memory, to form a result, the first interface of the cache coherent protocol interface circuit being connected to the memory, and the second interface of the cache coherent protocol interface circuit being configured as a cache coherent protocol interface on a bus interface.

In some embodiments: the function-in-memory circuits are arranged in a single instruction, multiple data configuration; or the function-in-memory circuits are arranged in a systolic configuration.

In some embodiments: the cache coherent protocol interface circuit is a Compute Express Link (CXL) interface circuit, and the bus interface is a Peripheral Component Interconnect express (PCIe) endpoint interface.

In some embodiments, a function-in-memory circuit of the one or more function-in-memory circuits is on a semiconductor chip with a dynamic random-access memory.

In some embodiments, the first interface is configured to operate according to a protocol selected from the group consisting of DDR2, DDR3, DDR4, and DDR5.

In some embodiments, a function-in-memory circuit of the one or more function-in-memory circuits includes: a plurality of registers, a plurality of multiplexers, and an arithmetic logic unit.

In some embodiments, a function-in-memory circuit of the one or more function-in-memory circuits is configured to perform an arithmetic operation selected from the group consisting of addition, subtraction, multiplication, and division.

In some embodiments, a function-in-memory circuit of the one or more function-in-memory circuits is configured to perform an arithmetic operation selected from the group consisting of floating-point addition, floating-point subtraction, floating-point multiplication, and floating-point division.

In some embodiments, a function-in-memory circuit of the one or more function-in-memory circuits is configured to perform a logical operation selected from the group consisting of bitwise AND, bitwise OR, bitwise exclusive OR, and bitwise ones complement.

In some embodiments, a function-in-memory circuit of the one or more function-in-memory circuits is configured, in a first state, to store the result in the memory, and, in a second state, to send the result to the cache coherent protocol interface circuit.

In some embodiments, the system further includes a host processing circuit connected to the second interface.

In some embodiments, the host processing circuit includes a PCIe root complex having a root port connected to the second interface.

According to an embodiment of the present invention, there is provided a system for computing, the system including: a memory; and a cache coherent protocol interface circuit having a first interface and a second interface, the cache coherent protocol interface circuit being configured to perform an arithmetic operation on data stored in the memory, the first interface of the cache coherent protocol interface circuit being connected to the memory, and the second interface being configured as a cache coherent protocol interface on a bus interface.

In some embodiments: the memory includes one or more function-in-memory circuits, and a function-in-memory circuit of the one or more function-in-memory circuits is configured to perform an operation on operands including a first operand retrieved from the memory, to form a result.

In some embodiments: the function-in-memory circuits are arranged in a single instruction, multiple data configuration; or the function-in-memory circuits are arranged in a systolic configuration.

In some embodiments: the cache coherent protocol interface circuit is a Compute Express Link (CXL) interface circuit, and the bus interface is a Peripheral Component Interconnect express (PCIe) endpoint interface.

In some embodiments, a function-in-memory circuit of the one or more function-in-memory circuits is on a semiconductor chip with a dynamic random-access memory.

In some embodiments, the first interface is configured to operate according to a protocol selected from the group consisting of DDR2, DDR3, DDR4, DDR5, GDDR, HBM, and LPDDR.

In some embodiments, a function-in-memory circuit of the one or more function-in-memory circuits is configured, in a first state, to store the result in the memory, and, in a second state, to send the result to the cache coherent protocol interface circuit.

According to an embodiment of the present invention, there is provided a method for computing, the method including: sending, by a host processing circuit, to a CXL interface circuit, one or more CXL packets; sending, by the CXL interface circuit, in response to receiving the CXL packets, to a function-in-memory circuit in a memory connected to the CXL interface circuit, an instruction; and performing, by the function-in-memory circuit, an operation, in accordance with the instruction, on operands including a first operand retrieved from the memory, to form a result.

