BACKGROUND

1. Field

The present invention relates to a semiconductor integrated circuit for power such as a high-voltage IC (hereinafter, referred to as “HVIC”), which can be used as a control IC of a power switching element.

2. Description of Related Art

Mainly in an inverter with low capacity, a power switching element of a bridge circuit for power conversion is driven and controlled by an HVIC. In accordance with an input signal from an input terminal, the HIVC outputs a drive signal from an output terminal so that a gate of the power switching element is turned into an on state or an off state, to thereby drive the power switching element. In the bridge circuit for power conversion, a high-voltage side power switching element (hereinafter, referred to as “high-voltage side switching element”) and a low-voltage side power switching element (hereinafter, referred to as “low-voltage side switching element”), which receive the signal from the HVIC, are operated to perform power conversion.

The HVIC includes a low-side circuit area and a high-side circuit area. The low-side circuit area has GND potential as reference potential. The high-side circuit area has VS potential higher than the GND potential as reference potential, and is operated with VB potential higher than the VS potential as power potential. The HVIC has a function of converting an input signal with the GND potential as a reference into a signal with the VS potential as a reference and outputting the converted signal. With this function, gate driving of the low-voltage side switching element and the high-voltage side switching element and the like can be performed.

The low-side circuit area and the high-side circuit area of the HVIC are required to be electrically isolated from each other. Among several isolation methods, a self-isolation method in which isolation is performed at a p-n junction formed by diffusion is the most inexpensive method. In this method, a deep n-type diffusion layer (high-side n well) is formed in an upper part of a p-type substrate, and a p-type diffusion layer (high-side p well) is formed in an upper part of the high-side n well. In this case, the p-type substrate, the high-side n well, and the high-side p well are fixed to the GND potential, the VB potential, and the VS potential, respectively.

At the time of operation of the HVIC, a relationship of the VB potential>the VS potential≥the GND potential is satisfied, and no current flows to junctions of a parasitic p-n-p transistor including the high-side p well, the high-side n well, and the p substrate. However, when a relationship of the VS potential>the VB potential>the GND potential is caused by noise and the like, the parasitic transistor is turned into an on state, and large current flows from the p-type diffusion layer to the p-type substrate. When the relationship of the VB potential>the VS potential≥the GND potential is satisfied again, however, no current flows. Thus, the noise has a negligible influence on the IC operation as long as the noise is instantaneous.

However, in a case where a deep n-type diffusion layer (low-side n well) fixed to different potential is present in the same p-type substrate as the one described above, when part of the current of the above-mentioned parasitic p-n-p transistor flows in, a parasitic p-n-p-n thyristor is turned into anon state. In this case, a latch-up phenomenon may be induced. Even when the relationship of the VB potential>the VS potential≥the GND potential is satisfied again, the current is liable to continue flowing. Thus, even when the noise is instantaneous, the noise has a significant influence on the IC operation. As a simple method for suppressing the parasitic p-n-p-n thyristor operation, the low-side n well and the high-side p well are arranged so as to be separated from each other. However, with this method, a chip area is increased.

As another method for suppressing the parasitic thyristor operation, the following method is described in Japanese Unexamined Patent Application Publication No. Hei 1-114077 (Patent Literature 1). That is, specific elements such as gate protection diodes are formed through use of polycrystal silicon on an oxide film, and these elements are formed at positions to which no parasitic current flows. Further, in Japanese Unexamined Patent Application Publication No. 2006-165026 (Patent Literature 2), it is described that parasitic p-n-p transistor current causing the thyristor operation is reduced by forming an n+buried layer directly under a high-side n well. Further, in Japanese Unexamined Patent Application Publication No. 2008-124205 (Patent Literature 3), it is described that a trench deeper than a low-side n well is formed between the low-side n well and a region to which noise current is to be injected so as to suppress injection of the noise current to the low-side n well. Further, in Japanese Unexamined Patent Application Publication No. 2010-109172 (Patent Literature 4), it is described that the parasitic thyristor operation is suppressed by always fixing cathode potential of a parasitic p-n-p-n thyristor (corresponding to the potential of the low-side n well) to potential higher than the GND potential.

With the methods described in Patent Literatures 1 to 3, the parasitic thyristor operation can be suppressed while suppressing the increase of a chip area. However, process cost is increased. Further, with the method described in Patent Literature 4, effects are not exerted in a case where the potential of the low-side n well swings to the GND potential even instantaneously at the time of noise application.

In view of the above-mentioned problems, the present invention has an object to provide a semiconductor integrated circuit, which can suppress operation of a parasitic thyristor with a smaller chip area while suppressing increase of process cost.

SUMMARY

An aspect of the present invention inheres in a semiconductor integrated circuit encompassing: a semiconductor substrate having a first conductivity type; a first well region having a second conductivity type, which is provided in an upper part of the semiconductor substrate in a high-potential side circuit area defined in the semiconductor substrate; a second well region having the first conductivity type, which is provided in an upper part of the first well region and has an impurity concentration higher than an impurity concentration of the semiconductor substrate; and a first semiconductor region having the second conductivity type, which is provided in a low-potential side circuit area, the low-potential side circuit area being separated from the high-potential side circuit area to be defined in the semiconductor substrate and being operated with potential as a reference, which is lower than reference potential of the high-potential side circuit area, wherein a whole semiconductor region having the second conductivity type, which includes the first semiconductor region, has an impurity concentration higher than an impurity concentration of the first well region.

Another aspect of the present invention inheres in a semiconductor integrated circuit encompassing: a semiconductor substrate having a first conductivity type; a first well region having a second conductivity type, which is provided in an upper part of the semiconductor substrate in a high-potential side circuit area defined in the semiconductor substrate; a second well region having the first conductivity type, which is provided in an upper part of the first well region and has an impurity concentration higher than an impurity concentration of the semiconductor substrate; a first semiconductor region having the second conductivity type, which has an impurity concentration higher than an impurity concentration of the first well region and is provided in a low-potential side circuit area, the low-potential side circuit area being separated from the high-potential side circuit area to be defined in the semiconductor substrate and being operated with potential as a reference, which is lower than reference potential of the high-potential side circuit area; and a third well region having the second conductivity type, which is provided to be separated from the first semiconductor region in the upper part of the semiconductor substrate in the low-potential side circuit area and has an impurity concentration equal to or lower than the impurity concentration of the first well region, wherein the first semiconductor region being arrange at a position relatively close to the high-potential side circuit area with respect to the third well region.

Further aspect of the present invention inheres in a semiconductor integrated circuit encompassing: a semiconductor substrate having a first conductivity type; a first well region having a second conductivity type, which is provided in an upper part of the semiconductor substrate in a high-potential side circuit area defined in the semiconductor substrate; a second well region having the first conductivity type, which is provided in an upper part of the first well region and has an impurity concentration higher than an impurity concentration of the semiconductor substrate; a first semiconductor region having the second conductivity type, which has an impurity concentration higher than an impurity concentration of the first well region and is provided in a low-potential side circuit area, the low-potential side circuit area being separated from the high-potential side circuit area to be defined in the semiconductor substrate and being operated with potential as a reference, which is lower than reference potential of the high-potential side circuit area; and a third well region having the second conductivity type, which is provided to be separated from the first semiconductor region in the upper part of the semiconductor substrate in the low-potential side circuit area and has an impurity concentration equal to or lower than the impurity concentration of the first well region, wherein an element, which is capable of being always applied with potential higher than substrate potential to be applied to the semiconductor substrate, is provided through use of the third well region, and an element, which is prevented from being always applied with the potential is provided through use of the first semiconductor region.

