TECHNICAL FIELD

Embodiments of the present invention relate to the field of picture processing such as still picture and/or video picture encoding and decoding.

BACKGROUND

Video coding (video encoding and decoding) is used in a wide range of digital video applications, for example broadcast digital TV, video transmission over internet and mobile networks, real-time conversational applications such as video chat, video conferencing, DVD and Blu-ray discs, video content acquisition and editing systems, and camcorders of security applications.

Since the development of the block-based hybrid video coding approach in the H.261 standard in 1990, new video coding techniques and tools were developed and formed the basis for new video coding standards. One of the goals of most of the video coding standards was to achieve a bitrate reduction compared to its predecessor without sacrificing picture quality. Further video coding standards comprise MPEG-1 video, MPEG-2 video, ITU-T H.262/MPEG-2, ITU-T H.263, ITU-T H.264/MPEG-4, Part 10, Advanced Video Coding (AVC), ITU-T H.265, High Efficiency Video Coding (HEVC), and extensions, e.g. scalability and/or three-dimensional (3D) extensions, of these standards.

SUMMARY

Embodiments of the invention are defined by the features of the independent claims and further advantageous implementations of the embodiments by the features of the dependent claims.

According to an embodiment, an apparatus is provided for decoding an image block including processing circuitry configured to: predict signs of a plurality of coefficients of a transformed image block based on a cost function including transformed difference between adjacent pixels neighboring the transformed image block and prediction of the adjacent pixels calculated based on a prediction signal of the image block; and reconstruct the signs of the plurality of coefficients according to the predicted signs.

In an exemplary implementation, the processing circuitry is further configured to: parse from a coded stream sign prediction error; reconstruct the signs including adding to the predicted signs the parsed sign prediction error.

For example, the cost function includes a sum of squared transformed differences between the adjacent pixels neighboring the transformed image block and the prediction of the adjacent pixels calculated based on a prediction signal of the image block.

Moreover, in one implementation, the processing circuitry is further configured to predict the signs of the plurality of coefficients of a transformed image block including: calculating the transformed difference between the adjacent pixels neighboring the transformed image block and the prediction of the adjacent pixels calculated based on a prediction signal of the image block; calculating cost function comprising a sum of squared transformed differences between said transformed difference and the transformed image block reconstructed according to each hypothesis of the signs out of a set of hypotheses; select as the predicted signs that hypothesis of the signs which minimize the cost given by the cost function.

For instance, in the transformed image block is reconstructed by adding the hypothesis of the signs to coefficients parsed from a coded stream.

In particular, the cost function F may be given by: F=Σn=0N-1(tn−qn)2+Σm=0M-1(vm−om)2, with tn=Trans1D(Tn), qn=Trans1D(Qn), vm=Trans1D(Vm), and om=Trans1D(Om) wherein Trans1D(.) is a one-dimensional orthogonal transform and Tn=[2Xn,-1−Xn,-2−Pn,0], Vm=[2Z−1,m−Z−2,m−P0,m], Qn=Rn,0and Om=R0,m, wherein P is prediction signal, and X and Z are neighboring pixels, N and M being height and width of the block in which the signs are predicted, respectively.

In an exemplary implementation, the adjacent pixels are located at a horizontal and a vertical boundary of the image block.

In some embodiments, the processing circuitry is further configured to decode the sign prediction error using Context-Adaptive Binary Arithmetic Coding, CABAC.

According to an embodiment, an apparatus is provided for encoding an image block including processing circuitry configured to: predict signs of a plurality of coefficients of a transformed image block based on a cost function including transformed difference between adjacent pixels neighboring the transformed image block and prediction of the adjacent pixels calculated based on a prediction signal of the image block; and encode the signs of the plurality of coefficients according to the predicted signs.

According to an embodiment, the apparatus for encoding an image block according to claim9, wherein the processing circuitry is further configured to encode the signs of the plurality of coefficients including: determining sign prediction error as a difference between the signs of the plurality of coefficients and the predicted signs of the plurality of coefficients; inserting into a coded stream including the coded image block the determined sign prediction error.

For instance, the cost function includes a sum of squared transformed differences between the adjacent pixels neighboring the transformed image block and the prediction of the adjacent pixels calculated based on a prediction signal of the image block.

In one exemplary implementation, the apparatus for decoding an image block according to any of claims9to11, wherein the processing circuitry is further configured to predict the signs of the plurality of coefficients of a transformed image block including: calculating the transformed difference between the adjacent pixels neighboring the transformed image block and the prediction of the adjacent pixels calculated based on a prediction signal of the image block; calculating cost function comprising a sum of squared transformed differences between said transformed difference and the transformed image block reconstructed according to each hypothesis of the signs out of a set of hypotheses; and select as the predicted signs that hypothesis of the signs which minimize the cost given by the cost function.

For example, the cost function F is given by: F=Σn=0N-1(tn−qn)2+Σm=0M-1(vm−om)2, with tn=Trans1D(Tn), qn=Trans1D(Qn), vm=Trans1D(Vm), and om=Trans1D(Om), wherein Trans1D(.) is a one-dimensional orthogonal transform and Tn=[2Xn,-1−Xn,-2−Pn,0], Vm=[2Z−1,m−Z−2,m−P0,m], Qn=Rn,0and Om=R0,m, wherein P is prediction signal, and X and Z are neighboring pixels, N and M being height and width of the block in which the signs are predicted, respectively.

Moreover, the adjacent pixels may be located at a horizontal and a vertical boundary of the image block.

The processing circuitry of the decoding apparatus is further configured to: encode the sign prediction error using Context-Adaptive Binary Arithmetic Coding, CABAC.

According to an embodiment, a method is provided for decoding an image block including the steps of: predicting signs of a plurality of coefficients of a transformed image block based on a cost function including transformed difference between adjacent pixels neighboring the transformed image block and prediction of the adjacent pixels calculated based on a prediction signal of the image block; and reconstructing the signs of the plurality of coefficients according to the predicted signs.

According to an embodiment, a method is provided for encoding an image block including the steps of: predicting signs of a plurality of coefficients of a transformed image block based on a cost function including transformed difference between adjacent pixels neighboring the transformed image block and prediction of the adjacent pixels calculated based on a prediction signal of the image block; and reconstructing the signs of the plurality of coefficients according to the predicted signs.

It is noted that the above embodiments, implementations and examples described with reference to the processing circuitries in an encoding or decoding apparatus, are also applicable to the above mentioned encoding and decoding methods, which may correspond to the steps performed by the respective processing circuitries.

According to an embodiment, a computer readable medium is provided storing program including instruction which, when executed on a processor, perform all steps of the methods referred to above.

Details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description, drawings, and claims.

