BACKGROUND

An integrated circuit includes various circuits with respective functions, such as a memory circuit having a plurality of memory bit cells to retain information. The memory circuit includes non-volatile devices or volatile devices. For example, the volatile devices include static-random-access memory (SRAM) devices. Three dimensional transistors with fin-type active regions are often desired for enhanced device performance. Those three-dimensional field effect transistors (FETs) formed on fin-type active regions are also referred to as FinFETs. Other three-dimensional field-effect transistors include gate-all-around FETs. These FETs are required to have narrow fin width for short channel control, which leads to smaller source/drain regions than those of planar FETs. This will reduce the alignment margins and cause issues for further shrunken device pitches and increasing packing density. Furthermore, when metal interconnect is continuously scaling down to less feature sizes for circuit routing density improvement, the existing interconnect structure schemes face various issues in tighter pitch metal layers. For example, there is metal filling problems due to metal lines or plugs require diffusion barrier metal layer for reliability consideration and the barrier layer further reduce the sizes of the metal lines and metal plugs. These barrier metal layers will impact the trench filling capability and therefore, result in metal resistance degradation or even worse, such as via opening or electro-migration (EM) concern. Other issues with the scaling down of the device sizes include increased routing resistance, increased parasitic capacitance, shorting, leakage, alignment margins, layout flexibility, and packing density. Therefore, there is a need for a structure and method for SRAM structures and method making the same to address these concerns with enhanced circuit performance and reliability, and increased packing density.

