BACKGROUND OF THE INVENTION

The invention relates generally to integrated circuit packages and, more particularly, to an apparatus and method of fabricating a package having a reduced stacking height thereof.

Integrated circuit (IC) packages are typically fabricated having a number of embedded silicon devices such as memory chips, microprocessors, translation circuitry, buffering, switching, and the like. In order to combine and increase functionality of an IC, it is often desirable to stack and interconnect various die types into a single device or package. Thus, embedded chip packages can be manufactured having a plurality of chips or electronic components in a stacked 3D arrangement. The plurality of chips or electronic components are electrically connected to an input/output system by way of metal interconnects routed through a plurality of laminate re-distribution layers.

Advancements in IC packaging requirements pose challenges to the existing embedded chip build-up process. That is, it is desired in many current embedded chip packages to have an increased number of re-distribution layers, with eight or more re-distribution layers being common. The advancements are driven by ever-increasing needs for achieving better performance, greater miniaturization, and higher reliability. New packaging technology also has to further provide for the possibilities of batch production for the purpose of large-scale manufacturing thereby allowing economy of scale. Thus, as ICs become increasingly smaller and yield better operating performance, packaging technology has correspondingly evolved from leaded packaging, to laminate-based ball grid array (BGA) packaging, to chip-scale packaging (CSP), to flipchip packages, and to embedded chip build-up packaging.

There are a variety of known methods for stacking die to form a stacked package. One method includes stacking on the wafer level. In this approach, the dies are kept in wafer format and are stacked on top of each other and bonded together at high temperatures. Typically the layer-layer connections are formed by thru silicon vias. However, this method limits the mixing of die types that can be intermixed in the IC package. Another method is by stacking on the individual die level. Typically this method includes mounting a single die to a lead frame chip carrier interconnect platform and additional dies are then glued and stacked on top of each other. The interconnect is then formed by wirebonding to the exposed pads of the stacked die and to an I/O of the lead frame. However, this arrangement also limits the use of die types to those having perimeter connections and pyramid die stacking.

Additionally, these stacking methods typically result in an unacceptably thick package height. In order to handle and process the die (in either wafer format or as individual die), each must be typically 250 microns or greater in thickness. Thus, when in final package form, an 8-layer structure, for example, may be 2 mm or more in thickness. Such a package may be cumbersome to work with, expensive to fabricate and process, and may be fragile to handle for subsequent processing and usage. Also, such limitations may limit the overall number of layers in the final package if there is a restrictive total package thickness for the final application, thus limiting the functionality and performance.

Accordingly there is a need for a method for embedded chip fabrication that allows for the application of multiple dies and die types in a stacked arrangement with a reduced overall stack height. There is a further need for embedded chip fabrication that allows for the application of multiple re-distribution layers and also provides a simple flexible stacking method.

It would therefore be desirable to have a system and method capable of processing and fabricating a stacked IC package having a reduced package thickness.

BRIEF DESCRIPTION OF THE INVENTION

The invention provides a system and method of processing and fabricating a stacked IC package having a reduced package thickness.

In accordance with one aspect of the invention, an electronic package includes an electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.

In accordance with another aspect of the invention, a method of fabricating an electronic package includes forming a first sub-assembly layer having a first silicon device therein, the first sub-assembly layer having a first surface, forming a first interface material in the first sub-assembly layer such that the first surface includes the first interface material, electrically connecting a node of the first silicon device to the first interface material, and forming a second sub-assembly layer having a second surface and a third surface. The method further includes forming a conductor in the second sub-assembly layer such that the second surface includes the conductor, forming a second interface material in the second sub-assembly layer such that the third surface includes the second interface material, electrically connecting the conductor to the second interface material, and compressing an anisotropic conductive paste (ACP) between the first sub-assembly layer and the second sub-assembly layer such that the first interface material is electrically connected with the conductor.

In accordance with yet another aspect of the invention, an electronic package includes a plurality of die package sub-layers, each sub-layer having a first surface and a second surface. Each sub-layer includes a device having one or more electrical nodes, a first contact pad electrically connected to one of the one or more electrical nodes, the first surface comprising the first contact pad, a second surface comprising a conductor, and an electrical feedthrough configured to pass an electrical signal from the conductor to the first contact pad. A paste including a plurality of solder balls that conduct electrical signals is positioned between the plurality of sub-layers such that the first contact pad of one sub-layer is electrically connected to the conductor of an adjacent sub-layer.

Various other features and advantages will be made apparent from the following detailed description and the drawings.

