CROSS REFERENCE TO THE RELATED APPLICATIONS

This application is the national phase entry of International Application No. PCT/CN2019/114226, filed on Oct. 30, 2019, which is based upon and claims priority to Chinese Patent Application No. 201910623458.5, filed on Jul. 11, 2019, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present invention belongs to the technical field of basic electronic circuits, and more particularly, relates to an in-memory computing circuit for a fully connected binary neural network, which uses digital logic to realize forward propagation calculation of the fully connected neural network.

BACKGROUND

Deep learning promises unique advantages in image recognition, natural language processing and other fields. Dedicated neural network chips, therefore, have become area of focused research.FIG. 1schematically shows the basic calculation process of a neural network, which includes performing a weighted summation of the activations of the previous layer, adding the bias, and obtaining an activation of the next layer through an activation function. This process can be organized into the form of matrix and vector multiplication, as shown in formula (1).

[A2⁢1A2⁢2]=f([W11W21W3⁢1W1⁢2W2⁢2W3⁢2]×⁢[A1⁢1A1⁢2A1⁢3]+⁢[b1b2])(1)

The activations and weights of traditional neural networks typically use high-precision floating-point numbers (32-bit or 16-bit). With the expansion of the network scale, a large number of multiply and accumulate (MAC) operations involved in the calculation process need large amounts of memory access, computational overhead and thus consume lots of power as well. This limits the application of neural networks in mobile devices. The binary neural network (BNN) proposed in recent years limits the activation and weight to 1 bit, whereby a large number of multiplication operations are simplified to exclusive or (XNOR) operations (as shown inFIG. 2), and accumulation operations are simplified to bit counting operations, that is, to count the number of 1s and the number of 0s in the XNOR result. The activation function is a sign function to determine whether the sum of the difference between the number of 1s and the number of 0s in the XNOR result and the bias is greater than 0. If the sum is greater than or equal to 0, output 1; otherwise, output 0. The basic calculation process is shown inFIG. 3.

The binary neural network significantly simplifies the computational overhead. Thus, memory access becomes a critical factor in system power consumption. As shown inFIG. 4, the accelerator based on the traditional Von Neumann architecture performs a multiply-accumulate operation, which needs to fetch 2 operands from the memory and put them in the registers, and then the arithmetic logic unit completes the XNOR logic. The operands involved in neural networks are often relatively long vectors, whereas the word length of general memory is relatively short (16-bit or 32-bit). This means that performing a vector-level MAC operation requires several memory accesses.

Since the memory access requires charging and discharging the bit line capacitance, and the memory and the arithmetic logic unit are physically connected via a long interconnected wire, frequent access to the memory and data movement will cause massive power consumption. The power needed is several orders of magnitude higher than that of the computation itself according to related research reports. Moreover, the word length of general memory also severely limits the computational throughput of neural networks. In order to solve the problem of power consumption waste and performance loss caused by “memory wall,” research on in-memory computing has become an area of concentration in academia and industry. As shown inFIG. 5, this architecture does not have explicit memory accesses and implements calculations in parallel on the bit lines of the memory or integrates computational logic and storage together, thus reducing the power consumption waste caused by data movement. Additionally, the multi-column parallel mode of this architecture also diminishes the number of memory accesses, thereby improving the system performance.

SUMMARY

In view of the above-mentioned shortcomings in the prior art, an objective of the present invention is to provide an in-memory computing circuit for a fully connected binary neural network. The improved circuit uses the XNOR operation executed in parallel on the Static Random-access Memory (SRAM) bit line to (i) realize in-memory computing of the fully connected binary neural network, (ii) realize read-write separation of the memory cell while reducing the significant power consumption caused by data movement, and (iii) solve the technical problems that the neural network accelerator based on the traditional Von Neumann architecture consumes massive power consumption due to frequent memory accesses and data movement.

To achieve the above-mentioned objective(s), the present invention adopts the following technical solutions:

An in-memory computing circuit for a fully connected binary neural network includes an SRAM for performing XNOR operations and a delay chain for performing accumulation and activation operations. The in-memory computing circuit specifically includes: an input latch circuit, a counting addressing module, an address selector, a decoding and word line drive circuit, a memory array, a pre-charge circuit, a writing bit line drive circuit, a replica bit line column cell, a timing control circuit, a sensitive amplifier and a not-and (NAND) gate array, an output latch circuit and a delay chain.

The memory array is an SRAM array with M+1 rows and N columns, and configured to store the weights of the current layer and the activations of the previous layer. The memory array includes (M+1)×N memory cells, wherein M and N are integers between 16-512, M is determined by the number of neurons in the current layer, and N is determined by the number of neurons in the previous layer. The following matrix-vector multiplication operation:

M×V=[W0,0W0,1…W0,N-1W1,0W1,1…W1,N-1⋮⋮⋱⋮WM-1,0WM-1,1…WM-1,N-1]×[A0A1⋮AN-1],

after being mapped to the memory array, is converted as follows:

[A0A1…AN-1W0,0W0,1…W0,N-1W1,0W1,1…W1,N-1⋮⋮⋱⋮WM-1,0WM-1,1…WM-1,N-1],

wherein the first row stores the activations of the previous layer, and the following rows store the corresponding weights of the current layer. The XNOR operation, accumulation operation, activation operation and other operations are performed on the activations of the first row and the weights of the following rows in sequence under clock control.

Compared with the traditional 6-transistor cell, additional 3 read branch transistors are used in the memory cell of the memory array. The latch unit composed of the first metal oxide semiconductor (MOS) transistor to the fourth MOS transistor includes the first complementary MOS (CMOS) inverter and the second CMOS inverter, wherein the output terminal of the second CMOS inverter is connected to the input terminal of the first CMOS inverter. The gate of the fifth MOS transistor and the gate of the sixth MOS transistor are connected in parallel and then connected to a writing word line enable signal. The drain of the fifth MOS transistor is connected to the low-level discharge writing word line. The source of the fifth MOS transistor is connected in parallel with the input terminal of the first CMOS inverter and the output terminal of the second CMOS inverter. The drain of the sixth MOS transistor is connected to the low-level discharge writing word line, the source of the sixth MOS transistor is connected to the input terminal of the second CMOS inverter. The drain of the seventh MOS transistor is connected to the low-level discharge reading word line, and the gate of the seventh MOS transistor is connected to the output terminal of the first CMOS inverter and the input terminal of the second CMOS inverter. The drain of the eighth MOS transistor is connected to the high-level discharge reading word line, and the gate of the eighth MOS transistor is connected to the input terminal of the first CMOS inverter and the output terminal of the second CMOS inverter. The source of the seventh MOS transistor and the source of the eighth MOS transistor are connected in parallel with the drain of the ninth MOS transistor, the gate of the ninth MOS transistor is connected to a reading word line enable signal, and the source of the ninth MOS transistor is grounded. In a holding state, the writing word line enable signal and the reading word line enable signal are both at a low level, and the latch unit composed of the first MOS transistor to the fourth MOS transistor maintains the data. In a writing state, the reading word line enable signal is at a low level, and the writing word line enable signal is at a high level. The fifth and sixth MOS transistors connected to the input and output terminals of the latch unit are turned on. Data on the low-level discharge writing word line and data on the high-level discharge writing word line are written into the latch unit through the fifth MOS transistor and the sixth MOS transistor. In a reading state, the writing word line enable signal is at a low level, and the reading word line enable signal is at a high level, and the ninth MOS transistor is turned on. If the stored data is 1, the eighth MOS transistor is turned on and the seventh MOS transistor is turned off, so that the pre-charged high-level discharge reading word line discharges through the reading branch formed by the eighth MOS transistor and the ninth MOS transistor, and the high-level discharge reading word line does not discharge. If the stored data is 0, the seventh MOS transistor is turned on and the eighth MOS transistor is turned off, so that the pre-charged low-level discharge reading word line discharges through the reading branch formed by the seventh MOS transistor and the ninth MOS transistor, and the high-level discharge reading word line does not discharge. The memory cell adopts a read-write separation mechanism. In the process of reading data, internal data acts on the gates of the seventh and eighth MOS transistors to ensure that multiple rows of reading word lines can be simultaneously turned on without destroying the internal data.

The delay chain includes two delay chains, one of the two delay chains is used as an adjustable chain and the other delay chain is used as a reference chain. The inputs of the two delay chains are all connected to a clock signal, the output of the adjustable chain is connected to a data terminal of a D flip-flop, and the output of the reference chain is connected to a clock terminal of the flip-flop. Each of the two chains is composed of N customized 6-transistor delay cells, and the 6-transistor delay cell is composed of two-stage inverters, wherein the first-stage inverter is composed of a P-Channel Metal Oxide Semiconductor (PMOS) transistor and three N-Channel Metal Oxide Semiconductor (NMOS) transistors; and the second-stage inverter is an ordinary inverter composed of a PMOS transistor and an NMOS transistor.

By adopting the above technical solutions, the invention has the following advantages.

(1) In the present invention, a large number of bitwise XNOR operations required in the binary neural network are accomplished on the SRAM bit line through logic simplification and transformation. Namely, partial calculation is completed while the memory is accessed to apportion the memory access power consumption through the calculation, thus reducing the memory access power consumption to a certain extent. Multi-column parallel computing also improves system throughput. Compared with the accelerators adopting a von Neumann architecture, the computing circuit of the present invention can significantly reduce overall network power consumption and improve energy efficiency.

(2) The accumulation and activation operations of the binary neural network are executed in time domain. Compared with the traditional digital accumulator and comparator (configured to realize the sign function), the computing circuit of the present invention has lower power consumption and simpler structure, and thus can be deployed near the SRAM to shorten the physical path from the memory to the accumulator, and further diminish the power consumption overhead caused by data movement.

(3) The 9-transistor memory cell in the present invention realizes the read-write separation, and the discharge of the reading branch is realized through two discharge behaviors of the bit line capacitance to facilitate limiting the discharge swing of the bit line capacitance via the sensitive amplifier, which saves energy consumption and has improved reading and writing noise margin. In this way, the system can work at a lower voltage, which is conducive to reducing power consumption and improving energy efficiency. This can ensure that multiple rows of reading word lines can be simultaneously turned on without destroying the data, which is suitable for applications where multiple rows of word lines are turned on simultaneously.

