CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Chinese Patent Application No. 202010130183.4, filed with the China National Intellectual Property Administration (CNIPA) on Feb. 28, 2020, the contents of which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

The present disclosure relates to the field of computer hardware, particularly to the cloud computing technology, and specifically to a caching device, an instruction cache, a system for processing an instruction, a method and apparatus for processing data and a medium.

BACKGROUND

A core in a multi-core processor acquires instruction processing from an external instruction storage device via an instruction cache (icache). The icache is connected to the external instruction storage device via a bus. The bus responds to a read operation issued by the icache with a random delay, and the icache can initiate a new read operation only after the bus responds to the current read operation. Within the delay time, the situation of that a instruction fetch of the core misses at the icache may occur, which require to cache a read operation not initiated yet.

In the existing technology, a FIFO (First Input First Output) storage device is generally used to cache a missing instruction identifier not initiated in the icache, and another FIFO is used to cache a missing instruction identifier responded but not written back by the bus. Currently, a register set is mainly used to synchronously cache a missing instruction identifier that is initiated, responded but not written back by the bus. When a next missing of instruction fetch occurs, whether a request for a corresponding instruction fetch needs to be initiated is ascertained by querying the missing instruction identifier cached in the register set. At the same time, another register set is used to record cores in which the missing of instruction fetch occurs. When written back via the bus, corresponding instructions may be written back into the cores accordingly.

In the process of implementing the present disclosure, the inventor finds that the existing technology has the following defects: in order to realize the function of fetching a missing instruction, many FIFOs and register sets need to be used, resulting in cumbersome control; in addition, repeated information is cached in the FIFOs and the register sets, thereby causing unnecessary resource waste.

SUMMARY

Embodiments of the present disclosure provide a caching device, a cache, system for processing an instruction, method for processing data, apparatus and medium. By designing a caching device that has a new structure, the hardware cost required for implementing the function fetching a missing instruction is reduced.

In a first aspect, some embodiments of the present disclosure provide a caching device, the caching device includes: a first queue, a second queue, a write port group, a read port, a first pop-up port, a second pop-up port and a press-in port;

the write port group is configured to write cache data into a set storage address in the first queue and/or the second queue;

the read port is configured to read all cache data from the first queue and/or the second queue at one time;

the press-in port is configured to press cache data into the first queue and/or the second queue;

the first pop-up port is configured to pop up cache data from the first queue;

the second pop-up port is configured to pop up cache data from the second queue.

An embodiment of the present disclosure has following advantages and beneficial effects: by setting the pop-up ports for the two queues, when missing of instructions occurs, the caching device may simultaneously store a missing instruction identifier that has not been initiated and a missing instruction identifier that has been responded to but not written back by the bus, thereby greatly saving the number of the caching devices. In addition, by setting the write port group and the read port, the core identifier of the processing core matching the instruction fetch missing identifier may be cached using the same structure, without using the register set to store the above information, thereby reducing the complex logic control.

Alternatively, the write port group comprises a write data port and a write address port;

the write data port is configured to receive written cache data; and

the write address port is configured to receive a storage address in the first queue and/or the second queue, the cache data written by the write data port being to be written to the address.

An embodiment of the present disclosure has following advantages and beneficial effects: by setting the write data port and the write address port, and then when requests for instruction fetch targeting at the same missing instruction are received from different processing cores of the multi-core processor, the information of the processing cores may be written to the same storage address, and thus, the limited storage space is multiplexed to the greatest extent, and the processing performance may be improved.

Alternatively, the write port group further comprises a write mask port,

the write mask port is configured to receive mask information of the cache data written by the write data port; and

the mask information is configured to indicate a data bit of the cache data written to the storage address, and a bit width of the write mask port is identical to a bit width of the write data port.

An embodiment of the present disclosure has following advantages and beneficial effects: by setting the write mask port, it may be accurately set that the corresponding cache data is written to a specific data bit in the storage address of the caching device, and then, that the identifier information of the processing core sending the request for instruction fetch targeting at the missing instruction is updated and stored, and thus, the limited storage space is multiplexed to the greatest extent, and the processing performance may be improved.

Alternatively, the caching device includes a first empty-full state flag bit group and a second empty-full state flag bit group,

the first empty-full state flag bit group is configured to indicate a storage state of cache data in the first queue, and

the second empty-full state flag bit group is configured to indicate a storage state of cache data in the second queue.

An embodiment of the present disclosure has following advantages and beneficial effects: by setting the first empty-full state flag bit group and the second empty-full state flag bit group, the functions of the caching device may be further enriched, and the storage state of each queue in the caching device may be learned in real time, and thus, processing operations matching different storage states may be performed.

In a second aspect, some embodiments of the present disclosure provide an instruction cache, the instruction cache includes a first caching device and a second caching device according to any one of the embodiments of the present disclosure.

An embodiment of the present disclosure has following advantages and beneficial effects: By setting the first caching device and the second caching device of the above new structure in the instruction cache, the performance of the instruction cache may be further optimized. In particular, in the instruction fetch scenario, the function of fetching a missing instruction that needs to be realized through the cooperation of many FIFOs and many register sets in the existing technology may be realized, thus omitting more complex control logics and simplifying the design of the instruction cache. In addition, that the multi-core processor sends repeated instruction fetch requests to the external instruction storage device, and thus, many unnecessary delays of the multi-core processor may be greatly reduced, thereby improving the performance of the multi-core processor.

In a third aspect, some embodiments of the present disclosure provide a system for processing an instruction, the system includes an instruction cache according to any one of the embodiments of the present disclosure, a multi-core processor and an external instruction storage device.

where the instruction cache is respectively connected to the external instruction storage device and a plurality of processing cores of the multi-core processor, and the instruction cache is connected to the external instruction storage device via a bus.

Alternatively, the multi-core processor is configured to provide, when missing of an instruction fetch occurs, a missing instruction identifier to the instruction cache;

the external instruction storage device is used to store instructions; and

the instruction cache is configured to send the missing instruction identifier to the external instruction storage device and acquire an instruction responded and written back by the external instruction storage device via the bus.

Alternatively, the first caching device is configured to cache, using a first queue, an instruction fetch missing identifier that has not been responded by the external instruction storage device when the instruction fetch missing occurs, and cache, using a second queue, an missing instruction fetch identifier that has been responded but has not written back by the external instruction storage device; and

the second caching device is configured to correspondingly store, using a first queue or a second queue and based on a storage address of the missing instruction fetch identifier in the first caching device, a core identifier of a processing core matching the missing instruction fetch identifier.

An embodiment of the present disclosure has following advantages and beneficial effects: by setting the first caching device and the second caching device of the new structure in the instruction cache, the function of fetching a missing instruction that needs to be realized through the cooperation of many FIFOs and many register sets in the existing technology may be realized in the system for processing an instruction, thus omitting more complex control logics and simplifying the design of the instruction cache. In addition, the situation that the multi-core processor sends repeated instruction fetch requests to the external instruction storage device may be avoided, and thus, many unnecessary delays of the multi-core processor may be greatly reduced, thereby improving the performance of the multi-core processor.

In a fourth aspect, some embodiments of the present disclosure provide a method for processing data, performed by the instruction cache in the system according to any one of the embodiments of the present disclosure. The method includes:

in response to detecting that an external instruction storage device is in an idle state, fetching a missing instruction identifier from a first queue of a first caching device, and popping up the missing instruction identifier via a first pop-up port, to provide to the external instruction storage device;

in response to detecting a write-back instruction fed back by the external instruction storage device targeting at a first target missing instruction identifier, fetching the first target missing instruction identifier from a second queue of the first caching device, and popping up the first target missing instruction identifier via a second pop-up port of the first caching device;

fetching first target cache data matching the first target missing instruction identifier from a second caching device, and popping up the first target cache data through a first pop-up port or a second pop-up port of the second caching device; and

identifying, based on the first target cache data, a first target core identifier of a first target processing core matching the first target missing instruction identifier, and sending the write-back instruction to the first target processing core.

An embodiment of the present disclosure has following advantages and beneficial effects: through the two queues set in the first caching device and the pop-up ports for the different queues, pop-up processing may be respectively performed on an instruction missing identifier that has not been initiated and an instruction missing identifier that has been responded to but has not been written back by the bus, thereby greatly saving the number of the caching devices used by the instruction cache. In addition, the core identifier of the processing core matching the instruction fetch missing identifier may be synchronously popped up through the pop-up ports in the second caching device, without using a register set to store the above information, thereby reducing the complex logic control.

Alternatively, the method further includes:

in response to detecting that missing of an instruction fetch targeting at a second target missing instruction identifier occurs in a second target processing core, reading all missing instruction identifiers stored in the first queue and the second queue from a read port of the first caching device;

in response to the first queue and the second queue of the first caching device not storing the second target missing instruction identifier, simultaneously storing the second target missing instruction identifier into the first queue and the second queue;

generating second target cache data based on the second target processing core and mapping relationships between preset processing cores and a corresponding data bits in cache data; and

pressing the second target cache data into a first queue or a second queue of the second caching device through a press-in port of the second caching device.

An embodiment of the present disclosure has following advantages and beneficial effects: by setting the first caching device in the instruction cache, when missing of an instruction occurs, the missing instruction identifier that has not been initiated and the instruction missing identifier that has been responded to but has not been written back by the bus may be simultaneously stored, thereby greatly saving the number of the caching devices. In addition, through the write port group and the read port in the second caching device, the core identifier of the processing core matching the instruction fetch missing identifier may be synchronously cached or read, without using the register set to store the above information, thereby reducing the complex logic control.

Alternatively, after the reading all missing instruction identifiers stored in the first queue and the second queue from the read port of the first caching device, the method further includes:

in response to the first queue or the second queue of the first caching device storing the second target missing instruction identifier, fetching a target storage address of the second target missing instruction identifier in the first caching device;

generating third target cache data and target mask information based on the second target processing core and the mapping relationships between the preset processing cores and the corresponding data bits in the cache data; and

writing the target storage address, the third target cache data and the target mask information through a write port group of the second caching device, to store, in the second caching device, a core identifier of the second target processing core matching the second target missing instruction identifier.

An embodiment of the present disclosure has following advantages and beneficial effects: through the write port group in the second caching device, it may be implemented that, when the instruction fetch requests of different processing cores in the multi-core processor targeting at an identical missing instruction are received, the information of the processing cores is written to the same storage address, and thus, the limited storage space is multiplexed to the greatest extent, and the processing performance may be improved. In addition, that the multi-core processor sends repeated instruction fetch requests to the external instruction storage device may be avoided, and thus, many unnecessary delays of the multi-core processor may be greatly reduced, thereby improving the performance of the multi-core processor.

Alternatively, the method further includes at least one of the following:

in response to there being no cache data in the first queue of the first caching device, setting an empty state flag bit in a first empty-full state flag bit group of the first caching device to a target level value;

in response to the first queue of the first caching device is full, setting a full state flag bit in the first empty-full state flag bit group of the first caching device to a target level value;

in response to there being no cache data in the second queue of the first caching device, setting an empty state flag bit in a second empty-full state flag bit group of the first caching device to a target level value; or

in response to the second queue of the first caching device is full, setting a full state flag bit in the second empty-full state flag bit group of the first caching device to a target level value.

Alternatively, the method further includes: in response to detecting the full state flag bit in the first empty-full state flag bit group or the second empty-full state flag bit group of the first caching device is the target level value, receiving no more instruction fetch requests from any one of processing cores in a multi-core processor.

In a fifth aspect, some embodiments of the present disclosure provide an apparatus for processing data, implemented by the instruction cache in the system according to any one of the embodiments of the present disclosure. The apparatus includes: a first pop-up processing module, configured to fetch, in response to detecting that an external instruction storage device is in an idle state, a missing instruction identifier from a first queue of a first caching device, and popping up the missing instruction identifier via a first pop-up port, to provide to the external instruction storage device;

a second pop-up processing module, configured to fetch, in response to detecting a write-back instruction fed back by the external instruction storage device targeting at a first target missing instruction identifier, the first target missing instruction identifier from a second queue of the first caching device, and popping up the first target missing instruction identifier via a second pop-up port of the first caching device;

a third pop-up processing module, configured to fetch first target cache data matching the first target missing instruction identifier from a second caching device, and popping up the first target cache data through a first pop-up port or a second pop-up port of the second caching device; and

a write-back instruction sending module, configured to identify based on the first target cache data, a first target core identifier of a first target processing core matching the first target missing instruction identifier, and sending the write-back instruction to the first target processing core.

An embodiment of the present disclosure has following advantages and beneficial effects: through the two queues set in the first caching device and the pop-up ports for the different queues, pop-up processing may be respectively performed on an instruction missing identifier that has not been initiated and an instruction missing identifier that has been responded to but has not been written back by the bus, thereby greatly saving the number of the caching devices used by the instruction cache. In addition, the core identifier of the processing core matching the instruction fetch missing identifier may be synchronously popped up through the pop-up ports in the second caching device, without using a register set to store the above information, thereby reducing the complex logic control.

In a sixth aspect, some embodiments of the present disclosure provide non-transitory computer readable storage medium, storing a computer instruction, wherein the computer instruction is used to cause a computer to perform the method according to any one of the embodiments of the present disclosure.

An embodiment of the present disclosure has following advantage and beneficial effects: through the two queues set in the first caching device and the pop-up ports for the different queues, pop-up processing may be respectively performed on an instruction missing identifier that has not been initiated and an instruction missing identifier that has been responded to but has not been written back by the bus, thereby greatly saving the number of the caching devices used by the instruction cache. In addition, the core identifier of the processing core matching the instruction fetch missing identifier may be synchronously popped up through the pop-up ports in the second caching device, without using a register set to store the above information, thereby reducing the complex logic control.

Other effects of the above-mentioned optional manners will be embodied in some aspects in combination with specific embodiments.

