FIELD

The present disclosure relates to a method for manufacturing a semiconductor device

BACKGROUND

To meet the requirements for reduction in size and improvement in performance of a semiconductor device, miniaturization of electrodes, wirings, and the like, which constitute the semiconductor device has been promoted. Particularly, in a field of a compound semiconductor, to utilize excellent high-frequency characteristics of materials, it is strongly desired to make a gate electrode thinner. However, if the gate electrode is made thinner, because an electric field concentrates in a narrow region, an adverse effect of miniaturization typified by a short channel effect, or the like, also occurs. As one means for solving this problem, an offset gate structure in which the gate electrode is placed closer to a source electrode side, and an interval from a drain electrode to which a voltage is applied is extended, is effective.

CITATION LIST

Patent Literature

[PTL 1] JP H11-126782 A

SUMMARY

Technical Problem

In related art, patterning of a resist for forming a recess and patterning of a resist for forming a gate electrode have been respectively and separately performed. However, because misalignment occurs between the first patterning and the second patterning, a position of the gate electrode within the recess varies. Therefore, characteristics fluctuate, and yield of products decreases. Further, because it is necessary to perform patterning twice, the number of processes increases, which increases manufacturing cost.

Further, a method in which a recess is formed using a resist at which two large and small openings are formed, and a gate electrode is formed in the recess via the large opening while the small opening is blocked with an insulating film has been also proposed (see, for example, PTL 1). However, when the insulating film is subjected to dry etching, a semiconductor immediately below the gate electrode is damaged. Therefore, there has been a problem that, because carriers decrease and defects and traps increase, reliability degrades.

The present invention has been made to solve the problem as described above, and an object of the present invention is to provide a method for manufacturing a semiconductor device which is capable of improving yield of products and reliability and reducing manufacturing cost.

Solution to Problem

A method for manufacturing a semiconductor device according to the present disclosure includes: applying a resist on a semiconductor substrate and forming a first opening and a second opening whose width is narrower than that of the first opening at the resist; wet-etching the semiconductor substrate using the resist as a mask to form one continuous recess below the first opening and the second opening; after forming the recess, cross-linking a shrink material with the resist to block the second opening without blocking the first opening; and after blocking the second opening, forming a gate electrode within the recess via the first opening.

Advantageous Effects of Invention

In the present disclosure, the semiconductor substrate is wet-etched to form one continuous recess below the first opening and the second opening. Then, the shrink material is cross-linked with the resist and the resist is subjected to pattern shrinking so that the second opening with a narrower width is completely blocked without the first opening whose width is wider being blocked. Then, the gate electrode is formed within the recess in a region where the first opening is formed. By this means, because the position of the gate electrode within the recess does not vary, yield of products is improved. Further, the number of processes of patterning of the resist is reduced, so that it is possible to reduce manufacturing cost. Further, because the semiconductor immediately below the gate electrode is not damaged, reliability is improved.

