CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2019-0122554, filed on Oct. 2, 2019, in the Korean Intellectual Property Office, and entitled: “Semiconductor Device,” is incorporated by reference herein in its entirety.

BACKGROUND

1. Field

Embodiments relate to a semiconductor device.

2. Description of the Related Art

Due to their small-sized, multifunctional, and/or low-cost characteristics, semiconductor devices are being esteemed as important elements in the electronic industry. The semiconductor devices are classified into a semiconductor memory device for storing data, a semiconductor logic device for processing data, and a hybrid semiconductor device including both of memory and logic elements. As the electronic industry advances, there is an increasing demand for semiconductor devices with improved characteristics. For example, there is an increasing demand for semiconductor devices with high reliability, high performance, and/or multiple functions. To meet this demand, complexity and/or integration density of semiconductor devices are being increased.

SUMMARY

Embodiments are directed to a semiconductor device, including a first channel pattern and a second channel pattern on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types from each other; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

Embodiments are also directed to a semiconductor device, including semiconductor patterns vertically stacked on a substrate; a gate electrode extended in a first direction to fill a space between the semiconductor patterns; a source/drain pattern disposed at a side of the gate electrode and connected to the semiconductor patterns; an interlayered insulating layer covering the gate electrode and the source/drain pattern; a contact plug including a first portion, which is buried in the source/drain pattern, and a second portion, which penetrate the interlayered insulating layer and is connected to the first portion; an interface layer between the first portion and the source/drain pattern; and a metal oxide between the second portion and the interlayered insulating layer.

Embodiments are also directed to a semiconductor device, including a substrate having a first active region and a second active region; a first channel pattern on the first active region, and a second channel pattern on the second active region, and each of the first channel pattern and the second channel pattern including vertically-stacked semiconductor patterns; a gate electrode extended in a first direction to cross the first and second channel patterns; a first source/drain pattern disposed at a side of the gate electrode and connected to the first channel pattern; a second source/drain pattern disposed at a side of the gate electrode and connected to the second channel pattern, and having a different conductivity type from the first source/drain pattern; an interlayer insulating layer covering the gate electrode, the first source/drain pattern, and the second source/drain pattern; a first contact plug including a first portion, which is buried in the first source/drain pattern, and a second portion, which penetrates the interlayer insulating layer and is connected to the first portion; a second contact plug including a third portion, which is buried in the second source/drain pattern, and a fourth portion, which penetrates the interlayer insulating layer and is connected to the third portion; a first interface layer interposed between the first portion and the first source/drain pattern; and a second interface layer interposed between the third portion and the second source/drain pattern, the first and second interface layers including different elements from each other.

Embodiments are also directed to a semiconductor device, including a first channel pattern and a second channel pattern on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types from each other; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom portion of the first interface layer.

Embodiments are also directed to a method of fabricating a semiconductor device, including forming a first channel pattern and a second channel pattern on a substrate, each of the first and second channel patterns including semiconductor patterns which are vertically stacked; forming a first source/drain pattern and a second source/drain pattern, which are respectively connected to the first channel pattern and the second channel pattern, the second source/drain pattern having a different conductivity type from the first source/drain pattern; forming a first recess region in a top surface of the first source/drain pattern and forming a second recess region in a top surface of the second source/drain pattern; forming an insulating layer to cover an inner side surface of the first recess region; forming a first interface layer to fill a portion of the second recess region and to cover an inner side surface of the second recess region; and forming a first contact plug to fill at least a portion of the first recess region and forming a second contact plug to fill a remaining portion of the second recess region.

