CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of Chinese Patent Application No. 201911335096.6 filed on Dec. 20, 2019 in the National Intellectual Property Administration of China, the whole disclosure of which is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to the field of display technology, and particularly to a display panel and a method for manufacturing the display panel.

BACKGROUND

Power consumption is one of important evaluation indicators of consumer products. The power consumption of OLED (Organic Light-Emitting Diode) display panels mainly includes power consumption caused by logic operations in integrated circuits and light-emitting power consumption of luminescent materials. The light-emitting power consumption of the luminescent material depends on a voltage difference across the luminescent material and a current flowing through electrodes on both sides of the luminescent material. When the maximum brightness of the OLED display panel is unchanged, the overall current on the display panel is approximately constant. Therefore, the light-emitting power consumption of the luminescent material is mainly determined by the voltage difference between the high-voltage level signal (VDD) and low-voltage level signal (VSS) across the luminescent material. At present, the low-voltage level signal is mainly transmitted through a cathode layer.

SUMMARY

According to an aspect of the present disclosure, a display panel is provided, comprising: a base substrate; a conductive layer on the base substrate, the conductive layer comprising a level signal wiring pattern; a cathode layer on a side of the conductive layer away from the base substrate; an anode layer on the side of the conductive layer away from the base substrate and on a side of the cathode layer facing the base substrate; a thin film transistor on a side of the anode layer facing the base substrate and on the side of the conductive layer away from the base substrate, the thin film transistor comprising a source electrode, a drain electrode, an active layer, and a gate electrode, wherein the level signal wiring pattern is electrically connected to the cathode layer.

According to some exemplary embodiments, the thin film transistor is a P-type thin film transistor.

According to some exemplary embodiments, the conductive layer further comprises a first group of hollow portions, an orthographic projection of the first group of hollow portions on the base substrate covers an orthographic projection of the gate electrode of the P-type thin film transistor on the base substrate.

According to some exemplary embodiments, the conductive layer further comprises a first group of hollow portions, an orthographic projection of the first group of hollow portions on the base substrate covers an orthographic projection of the P-type thin film transistor on the base substrate.

According to some exemplary embodiments, an area of the orthographic projection of the first group of hollow portions on the base substrate is larger than an area of the orthographic projection of the P-type thin film transistor on the base substrate.

According to some exemplary embodiments, the thin film transistor is an N-type thin film transistor.

According to some exemplary embodiments, an orthographic projection of the level signal wiring pattern on the base substrate covers an orthographic projection of the N-type thin film transistor on the base substrate.

According to some exemplary embodiments, the display panel further comprises a signal line on the side of the anode layer facing the base substrate, and on the side of the conductive layer away from the base substrate, the conductive layer further comprises a second group of hollow portions, and an orthographic projection of the second group of hollow portions on the base substrate at least partially overlaps with an orthographic projection of the signal line on the base substrate.

According to some exemplary embodiments, the signal line comprises a data line or a clock signal line.

According to some exemplary embodiments, the conductive layer further comprises a third group of hollow portions, an orthographic projection of the third group of hollow portions on the base substrate neither overlaps with the orthographic projection of the thin film transistor on the base substrate, nor overlaps with the orthographic projection of the signal line on the base substrate.

According to some exemplary embodiments, the level signal wiring pattern is a mesh pattern.

According to some exemplary embodiments, the display panel comprises a display area and a peripheral area, an electrical connection portion is provided in the peripheral area, and the level signal wiring pattern is electrically connected to the cathode layer through the electrical connection portion.

According to some exemplary embodiments, the electrical connection portion comprises: a first electrical connection layer, the first electrical connection layer being made of the same material and arranged in the same layer as the anode layer, the first electrical connection layer being electrically connected with the cathode layer; and a second electrical connection layer, the second electrical connection layer being made of the same material and arranged in the same layer as the source electrode and the drain electrode of the thin film transistor, the second electrical connection layer being electrically connected with the level signal wiring pattern; wherein the first electrical connection layer is electrically connected with the second electrical connection layer.

According to some exemplary embodiments, the display panel further comprises: a luminescent material layer between the anode layer and the cathode layer.

According to some exemplary embodiments, the display panel further comprises: an integrated circuit interface; a first connection bus that electrically connects the level signal wiring pattern to the integrated circuit interface; and a second connection bus that electrically connects the cathode layer to the integrated circuit interface.

According to some exemplary embodiments, the first connection bus is made of the same material and arranged in the same layer as the conductive layer, and the second connection bus is made of the same material and arranged in the same layer as the cathode layer.

According to some exemplary embodiments, an orthographic projection of the level signal wiring pattern on the base substrate at least partially overlaps with an orthographic projection of the cathode layer on the base substrate.

According to another aspect of the present disclosure, there is provided an method for manufacturing a display panel, comprising: providing a base substrate; forming a conductive layer on the base substrate, the conductive layer comprising a level signal wiring pattern; forming a thin film transistor on a side of the conductive layer away from the base substrate; forming an anode layer on a side of the thin film transistor away from the base substrate; and forming a cathode layer on a side of the conductive layer away from the base substrate, wherein the cathode layer is electrically connected to the level signal wiring pattern.

