CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a national stage of International Application No. PCT/US2017/053649, filed Sep. 27, 2017.

FIELD OF INVENTION

The field of invention relates generally to computer processor architecture, and, more specifically, to instructions for vector multiplication of unsigned words with rounding.

BACKGROUND

A (e.g., hardware) processor, or set of processors, executes instructions from an instruction set, e.g., the instruction set architecture (ISA). The instruction set is the part of the computer architecture related to programming, and generally includes the native data types, instructions, register architecture, addressing modes, memory architecture, and interrupt and exception handling.

Certain functions may include operations on vectors containing multiple fixed-sized data elements. Certain operations on a plurality of vectors may multiply each fixed-sized element from one vector with a corresponding fixed-sized element of another vector to produce a product for each pair of elements. As used herein, the term “corresponding” refers to vector elements that occupy a same relative position within their associated vectors. To generate precise products, each of the products of such pair of corresponding fixed-sized vector elements is double-sized, requiring at least twice as many bits as the fixed size. The memory and register resources required to hold the double-sized products, especially when vectors are involved, can be costly.

