FIELD OF THE DISCLOSURE

The present application relates to display technologies, and more particularly to a display device and a power management chip for the same.

DESCRIPTION OF RELATED ARTS

With development of display technologies, display devices such as active matrix organic light-emitting diode (AMOLED) display devices have become more and more mature, and more and more applications have been applied in the field of displays.

For the AMOLED display devices, demands are highly increasing on OLED driving ability as display panel size is larger and larger and pixel density (e.g., pixels per inch, PPI) increases. An analog power voltage (AVDD), a driving voltage (ELVDD) and a low-level power voltage (ELVSS) that are integrated in a driver IC cannot satisfy the existing needs. It often needs a power management IC (PMIC) with a more powerful driving ability to provide the AVDD, ELVDD and ELVSS by the additional power management IC, in which the AVDD is used for the driver IC to generate a gamma voltage and a switching voltage of a thin-film transistor (TFT), and the ELVDD and ELVSS are driving voltages for OLED luminescence.

FIG. 1is a schematic diagram showing an existing power management chip10. An existing driving chip communicates with the power management chip10via a single wire (S-wire) interface. The existing power management chip10includes a rising-edge trigger12, a counter14and a digital-to-analog converter (DAC)16. The rising-edge trigger12receives pulses outputted by the driving chip and detects rising edges of the pulses. The counter14is electrically connected to the rising-edge trigger12for calculating the number of the rising edges of the pulses. The DAC16is electrically connected to the counter14for converting the number obtained by the counter14to a target voltage and outputting the same. In the existing arts, the driving chip outputs a different number of pulses to the power management chip10, the power management chip10identifies input signals using the rising-edge trigger12, the counter14calculates the number of cycles of the outputted pulses, and finally the DAC16converts it to a corresponding voltage and outputs the same.

FIG. 2is a timing diagram of AVDD, ELVDD and ELVSS voltages generated by the power management chip10controlled by the driving chip in the existing arts. The three voltages AVDD, ELVDD and ELVSS are controlled separately and sequentially. In the existing arts, when the power management chip10detects the outputted pulses by the driving chip through the S-wire interface, only the rising edges of the pulses are detected. This delays the time able to supply power by the power management chip10, thereby making poweron time of the display device become longer. At client ends, it needs to notice that the time of imputing a signal cannot be earlier than the time when the power is ready. Otherwise, exception is generated. Moreover, since the poweron time of the display device become longer, the starting-up time and the time needed to wake up from hibernation also become longer in machine applications, thereby affecting a user experience.

Technical Problems

The objective of the present application is to provide a display device and a power management chip for the same, for reducing the poweron time of the power management chip.

Technical Solutions

To achieve above object, in an aspect, the present application provides a power management chip for a display device, the power management chip configured to provide supply voltage required for driving the display device, the power management chip including:

a rising-edge trigger, receiving a pulse signal and detecting rising edges of the pulse signal;

a first counter, electrically connected to the rising-edge trigger, configured to calculate a number of the rising edges of the pulse signal;

a falling-edge trigger, receiving the pulse signal and detecting falling edges of the pulse signal;

a second counter, electrically connected to the falling-edge trigger, configured to calculate a number of the falling edges of the pulse signal;

an adder, electrically connected to the first counter and the second counter, configured to sum up the number of the rising edges of the pulse signal calculated by the first counter and the number of the falling edges of the pulse signal calculated by the second counter; and

a digital-to-analog converter, electrically connected to the adder, configured to convert to a target voltage based on the sum obtained by the adder,

wherein the pulse signal detected by the rising-edge trigger is identical to the pulse signal detected by the falling-edge trigger, and the target voltage is an analog voltage value.

In an embodiment of the present application, the rising-edge trigger and the falling-edge trigger receive the pulse signal via a single wire (S-wire) interface.

In an embodiment of the present application, the rising-edge trigger includes a D flip-flop and the falling-edge trigger includes any of a RS mater-slave flip-flop and a JK flip-flop.

In another aspect, the present application provides a power management chip for a display device, the power management chip configured to provide supply voltage required for driving the display device, the power management chip including:

a rising-edge trigger, receiving a pulse signal and detecting rising edges of the pulse signal;

a first counter, electrically connected to the rising-edge trigger, configured to calculate a number of the rising edges of the pulse signal;

a falling-edge trigger, receiving the pulse signal and detecting falling edges of the pulse signal;

a second counter, electrically connected to the falling-edge trigger, configured to calculate a number of the falling edges of the pulse signal;

an adder, electrically connected to the first counter and the second counter, configured to sum up the number of the rising edges of the pulse signal calculated by the first counter and the number of the falling edges of the pulse signal calculated by the second counter; and

a digital-to-analog converter, electrically connected to the adder, configured to convert to a target voltage based on the sum obtained by the adder.

In an embodiment of the present application, the rising-edge trigger and the falling-edge trigger receive the pulse signal via a single wire (S-wire) interface.

In an embodiment of the present application, the pulse signal detected by the rising-edge trigger is identical to the pulse signal detected by the falling-edge trigger.

In an embodiment of the present application, the target voltage is an analog voltage value.

In an embodiment of the present application, the rising-edge trigger includes a D flip-flop and the falling-edge trigger includes any of a RS mater-slave flip-flop and a JK flip-flop.

In still another aspect, the present application provides a display device, including a power management chip, a driving chip and a display panel, the power management chip generating a target voltage based on a pulse signal outputted by the driving chip for providing supply voltage required for driving the display panel, the power management chip including:

a rising-edge trigger, receiving the pulse signal from the driving chip and detecting rising edges of the pulse signal;

a first counter, electrically connected to the rising-edge trigger, configured to calculate a number of the rising edges of the pulse signal;

a falling-edge trigger, receiving the pulse signal from the driving chip and detecting falling edges of the pulse signal;

a second counter, electrically connected to the falling-edge trigger, configured to calculate a number of the falling edges of the pulse signal;

an adder, electrically connected to the first counter and the second counter, configured to sum up the number of the rising edges of the pulse signal calculated by the first counter and the number of the falling edges of the pulse signal calculated by the second counter; and

a digital-to-analog converter, electrically connected to the adder, configured to convert to a target voltage based on the sum obtained by the adder for driving the display panel.

In an embodiment of the present application, the rising-edge trigger and the falling-edge trigger receive the pulse signal, which is outputted by the driving chip, via a single wire (S-wire) interface.

In an embodiment of the present application, the pulse signal detected by the rising-edge trigger and the pulse signal detected by the falling-edge trigger are a same pulse signal from the driving chip.

In an embodiment of the present application, the target voltage is an analog voltage value for providing the supply voltage required for driving the display panel.

In an embodiment of the present application, the rising-edge trigger includes a D flip-flop and the falling-edge trigger includes any of a RS mater-slave flip-flop and a JK flip-flop.

BENEFICIAL EFFECTS

In the display device and the power management chip for the same in accordance with the present application, the power management chip utilizes the rising-edge trigger and the failing-edge trigger to simultaneously detect the number of the rising edges and the falling edges of the pulses outputted by the driving chip, utilizes the adder to sum up the number of the rising edges and the number of the falling edges, and then the DAC converts it to the target voltage that is needed. By this way, the poweron time of the power management chip can be reduced, the possibility of an exception of poweron timing and signal timing is avoided, the time needed to wake up from hibernation is reduced, and end consumer satisfaction is improved.

