BACKGROUND

Technical Field

The technology disclosed relates to built-in self-test (BIST) of integrated circuits. In particular, it relates to testing of processor chips that include one or more modules comprising a datapath with a memory and an ALU.

Context

The subject matter discussed in this section should not be assumed to be prior art merely as a result of its mention in this section. Similarly, a problem mentioned in this section or associated with the subject matter provided as background should not be assumed to have been previously recognized in the prior art. The subject matter in this section merely represents different approaches, which in and of themselves can also correspond to implementations of the claimed technology.

Integrated circuits that combine multiple processors on a single die, such as used for artificial intelligence or graphics processing, are made in the most advanced semiconductor processes. Such processes always provide new challenges to IC designers, including for testing their correct functionality prior to shipping finished product to customers. Traditionally, a digital IC is tested using automatic test pattern generation (ATPG), which distributes the ATPG test vectors over the IC in scan chains that transport the test vectors from an external tester to scan flipflops in the logic, and that transport test results back from the scan flipflops to the external test machine. Test vectors and test results may be compressed for more efficient interfacing. Tests focus on detecting stuck-at faults, and a coverage (i.e., reachability and observability) percentage in the high nineties has been considered adequate. Additionally, an integrated circuit may include circuits for built-in self-test (BIST) dedicated to specific blocks. Those includes memories (memory BIST, or MBIST), other standardized circuits, and some logic (logic BIST, or LBIST). BIST significantly reduces the dependence on an external tester and the cost of testing the IC, which is proportional to the time a tester takes for testing the IC. It can also be used after production, so that an IC in a life-critical application can test itself every time it is powered up.

Logic BIST generates and applies a relatively large number of pseudo-random test vectors to the scan chains, compresses the results obtained at-speed, and compares the compressed results with precompiled compressed results to detect any differences (i.e., errors). However, LBIST has challenges. The pseudo-random test vectors can create paths that are not used in normal operation (false paths), and may detect failures on the false paths. This wastes good ICs. LBIST may also generate extra heat because of heightened activity during test that would not be experienced in normal operation. The extra heat can cause timing violations, and thus functional faults. The heightened activity may also cause crosstalk issues that are not experienced during normal operation. Yet another problem is that LBIST cannot control don't-care bits. Whereas typically with ATPG the test coverage grows roughly linearly with the number of test vectors (until it nears an asymptote), for LBIST the test coverage grows only roughly logarithmically, and the asymptote may be lower than achieved with ATPG.

The fastest digital circuits cannot take the burden of slowdown by flipflops for scan testing with ATPG or LBIST vectors, and they may not be coverable with scan tests. For those cases, functional tests may be developed that directly test for the correct functionality of a circuit or block. Functional tests are used in moderation, as their development consumes much engineering time, and production test may take much tester time.

Processor chips are conventionally tested with ATPG for the logic and MBIST for the memory. The arithmetic logic unit (ALU) performs a number of different operations (on sets of two input numbers). The number of internal states the ALU can have can be exceedingly high, and ATPG scan testing has been considered the only practical solution to achieve good coverage.

However, the logic related to the insertion of MBIST vectors and the extraction of MBIST results creates problems for scan testing (ATPG or LBIST), including interface logic that is not observable, or shadow logic that isn't used in normal operation. Additionally, large processor chips made in advanced semiconductor processes show more failures than is expected on the basis of the scan test coverage for both stuck-at faults and speed-dependent mechanisms that should be found with at-speed tests. Defects that are the suspects for this discrepancy may include (1) bridging (short-circuits), (2) opens (missing connection), (3) defects in re-convergent logic for stuck-at vectors, (4) high-resistive shorts known as non-logic bridging, (5) resistive opens, and (6) coupling faults for at-speed vectors. One approach to capture these defects is functional testing, with the drawbacks mentioned above. Another, called “n-detect”, is detecting a defect in n different ways as if it were a stuck-at fault. However, applying n-detect on ATPG increases the cost of testing by n times.

SUMMARY

In a first aspect, implementations of the disclosed technology provide a configurable unit that includes a memory, an ALU coupled with the memory, a test controller, a test control register, and a signature register. The signature register may be coupled with an ALU output to receive ALU output data, compress the ALU output data, and store the compressed result as a test signature. The test controller manages a series of steps. The steps include overriding an ALU control signal with a replacement ALU control signal (from the test control register). The test controller generates a test pattern and forwards the test pattern to an input of a first circuit, other than a scan chain input. The first circuit output data is forwarded to the ALU, which executes an ALU operation on the first circuit output data, based on the replacement ALU control signal. A test result is obtained from the ALU output, compressed, and stored in the signature register.

The first circuit may be (or include) the memory. The test controller forwards the test pattern to the memory and writes it a first address. It obtains first circuit output data by reading from the first address. The test pattern may be included in a series of test patterns for detecting a memory error. The test pattern may include a pseudo-random number, focused at testing logic in the datapath, including testing the ALU.

In a second aspect, implementations of the disclosed technology provide a method to test a datapath in a configurable unit. The datapath includes a memory and an ALU. The method includes the following steps. It provides a memory test vector from a series of memory test vectors to the memory, and writes the memory test vector to a first address in the memory. It reads memory output data from the first address, and forwards this data to the ALU. The method replaces a signal on an ALU control input with a replacement ALU control signal, and the ALU performs an operation on the data read from the memory, based on the replacement ALU control signal. A test result is obtained from the ALU data output, and compressed to obtain a test signature. The test signature is stored in a signature register.

Particular aspects of the technology disclosed are described in the claims, detailed description, and drawings.

