INTRODUCTION

Disclosed herein are memory integrated circuits (ICs) and associated embedded full-scan methodologies. Embedded memory scanning applications, which sometimes include automatic test pattern generation, are often used to simplify combinatorial logic testing of memory instances and other integrated circuits. A memory compiler of the type commonly used for memory design and validation typically employs an architecture specifying required circuit elements and test signals. Compiler inputs may include one or more bitcell arrays, multiplexing arrangements, built-in self-test (BIST) modes, and possibly other user-selectable modes or logic features. A given memory instance created with the assistance of a memory compiler may be used in a myriad of applications. Since a given memory application may or may not require all of the available logic features of a given memory instance, users are typically permitted to de-select or disable unused logic features.

Scan cell chains are implemented in embedded memory scanning applications to fully test and validate the performance of constituent logic against an expected or modeled performance. In a typical embedded D/Q scan cell chain for a memory register, for instance, scanning inputs may be individually fed into corresponding flip-flops or latches. A separate scan chain may be used for testing write-enable (WEN) functions, with the D/Q and WEN scan chains possibly being combined in other configurations. When a bit-write mask is disabled, the available WEN inputs are tied-off to a low/O logic state. This action ties off associated logical signal propagation paths or “logic cones” of the WEN scan chain while leaving intact the associated logic cones of the associated memory circuit.

SUMMARY

Memory circuits and associated methods are disclosed herein. According to an exemplary embodiment, the memory circuit includes input and output phase circuits. The input phase circuit includes first set of multiplexers (“input MUXes”) each configured to receive a pair of input bits, and in response to a scan enable signal (SE), to selectively pass one of the pair of input bits. The input MUXes include a first MUX arranged to receive, as the pair of input bits, a first data bit D[0] and a serial input bit SI[0]. Additional input MUXes are arranged to receive, as the pair of input bits, either a respective pair of data (D) bits, or a write-enable (WEN) bit and a single D bit.

The input phase includes scan latches each arranged to receive one of the pair of input bits from a respective input MUX, and to provide an upstream/scan output bit (QU) in response to an edge of a digital clock signal. As used herein, the subscript “U” indicates “upstream” relative to a signal flow direction through the memory circuit.

The output phase includes a plurality of logical OR gates each arranged to receive the scan output bit (QU) from a different corresponding pair of the scan latches, and to perform a logical OR operation thereon to thereby generate an OR output bit. The output phase also includes a second set of multiplexers (“output MUXes”) each arranged to pass either a corresponding bit from a bit array or the OR output bit from a corresponding one of the OR gates, and a plurality of sense latches. Each downstream sense latch is arranged to receive the corresponding scan output bit from one of the input MUXes and provide a downstream output bit (QD), with the subscript “D” referring herein to “downstream” relative to the signal flow direction through the memory circuit.

In this particular embodiment, each downstream output bit that is output by the sense latches is fed into two or more of the input MUXes as either one of the pair of D bits or as the single D bit, thus allowing the WEN bit to toggle when solving the particular control issues addressed herein.

An input phase circuit is also disclosed herein for use in a memory circuit, the latter having (n/2) sense latches logically coupled to (n) scan latches of the input phase circuit by a respective OR gate and output MUX. That is, each output MUX receives an OR output bit from the respective OR gate and a bit value from a bit array.

The input phase circuit according to an exemplary embodiment includes a set of (n) input MUXes, with (n) being an even integer value. Each input MUX is configured to receive a pair of input bits and, in response to a scan enable signal (SE), to selectively pass one of the pair of input bits to a respective one of the scan latches. The input MUXes include a first MUX arranged to receive a first data bit D[0] and a serial input bit SI[0] from a control circuit, and (n−1) additional MUXes each arranged to receive either a respective pair of data (D) bits, or a write-enable (WEN) bit and a single D bit.

In this embodiment, an output bit from a plurality of the sense latches is fed into two or more of the input MUXes as either one of the pair of D bits or as the single D bit. During a scan capture operation in which a bit-write-mask function is disabled, such an arrangement enables the WEN bit, which is tied-low when the bit-write-mask function is disabled, to be selectively toggled between high and low logic values.

A method for performing an embedded scan chain operation is also disclosed. According to a representative embodiment of the method, the method includes generating a plurality of multiplexed bits by multiplexing a pair of input bits through each multiplexer of a first set of multiplexers (“input MUXes”) in response to a scan enable (SE) signal. The input MUXes include a first input MUX arranged to receive a first data bit D[0] and a serial input bit SI[0], and a plurality of second input MUXes each arranged to receive either a respective pair of data bits or a write-enable (WEN) bit and a single data bit (D[0]-D[n/2−1]).

The method may include generating a plurality of latched bits, including latching the multiplexed bits in response to an edge of a clock signal (CLK), and processing different corresponding pairs of the latched bits through an OR gate to thereby generate a plurality of logic bits. The method may also include latching the logic bits to thereby generate a plurality of additional latched bits, and feeding each additional latched bit into two or more of the input MUXes as one of the pair of data bits or the single data bit to thereby enable the WEN bit to control the additional latched bit during a scan operation in which a bit-write-mask operation is disabled. The WEN bit, which is tied-low when the bit-write-mask function is disabled, is thus selectively toggled between high and low logic values.

The above features and advantages and other features and advantages of the present disclosure are readily apparent from the following detailed description of the best modes for carrying out the invention when taken in connection with the accompanying drawings.

