CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2019-0167561 filed in the Korean Intellectual Property Office on Dec. 16, 2019, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a semiconductor memory device, and particularly, to a three-dimensional semiconductor memory device.

2. Related Art

In order to meet demands for excellent performance and low price that consumers demand, the degree of integration in a semiconductor device must increase. Since the degree of integration of a two-dimensional or planar semiconductor memory device is mainly determined by the area occupied by a unit memory cell, the degree of integration is greatly influenced by the level of a fine pattern forming technique. However, since highly expensive equipment is required for the formation of a fine pattern, the degree of integration of a two-dimensional semiconductor memory device is still limited, although it is increasing. To overcome such limitations, alternatives include a three-dimensional semiconductor memory device including memory cells that are three-dimensionally arranged has been proposed.

In a three-dimensional semiconductor memory device, the degree of integration may be increased by increasing the stack number of row lines. However, since the number of wiring lines coupled to the row lines increases in proportion to the number of row lines, a large number of metal layers are required.

SUMMARY

Various embodiments are directed to a semiconductor memory device capable of contributing to a reduction in the number of metal layers.

In an embodiment, a semiconductor memory device may include: a cell region defined with a plurality of vertical channels which pass through a plurality of electrode layers and a plurality of interlayer dielectric layers alternately stacked on a source plate; a step region disposed adjacent to the cell region in a first direction parallel to a top surface of the source plate, and defined with a plurality of contacts which are coupled to the plurality of electrode layers extending in different lengths; a first opening passing through the plurality of electrode layers and the plurality of interlayer dielectric layers, in a vertical direction in the step region; a second opening passing through the plurality of electrode layers and the plurality of interlayer dielectric layers, in the vertical direction in the cell region; a plurality of under wiring lines disposed under the source plate, and coupled with a peripheral circuit which is defined on a substrate below the source plate; a plurality of top wiring lines disposed over the plurality of electrode layers and the plurality of interlayer dielectric layers, and coupled with the plurality of contacts; and a plurality of vertical vias coupling the plurality of under wiring lines and the plurality of top wiring lines. The vertical vias may include a plurality of first vertical vias which pass through the first opening and a plurality of second vertical vias which pass through the second opening.

In an embodiment, a semiconductor memory device may include: a cell region having a plurality of vertical channels which pass through a plurality of electrode layers and a plurality of interlayer dielectric layers alternately stacked on a source plate; a step region adjacent to the cell region in a first direction that is parallel to a top surface of the source plate, and having a plurality of contacts which are coupled to the plurality of electrode layers extending in different lengths into the step region; a first opening passing through the plurality of electrode layers and the plurality of interlayer dielectric layers, in a vertical direction in the step region; a second opening and a third opening passing through the plurality of electrode layers and the plurality of interlayer dielectric layers, in the vertical direction in the cell region, and arranged in the first direction; a plurality of under wiring lines disposed under the source plate, and coupled with a peripheral circuit which is defined on a substrate below the source plate; a plurality of top wiring lines disposed over the plurality of electrode layers and the plurality of interlayer dielectric layers, and coupled with the plurality of contacts; and a plurality of vertical vias coupling the plurality of under wiring lines and the plurality of top wiring lines. The plurality of vertical vias may include a plurality of first vertical vias which pass through the first opening, a plurality of second vertical vias which pass through the second opening, and a plurality of third vertical vias which pass through the third opening.

In an embodiment, a semiconductor memory device may include: a plurality of pass transistors defined in a substrate which is defined with a cell region, a step region extending in a first direction from the cell region and a peripheral region extending in the first direction from the step region; a plurality of electrode layers and a plurality of interlayer dielectric layers alternately stacked on a source plate over the plurality of pass transistors; vertical channels passing through the plurality of electrode layers and the plurality of interlayer dielectric layers, in the cell region; a plurality of under wiring lines disposed between the plurality of pass transistors and the source plate, and coupled to the plurality of pass transistors; a plurality of top wiring lines disposed over the electrode layers and the plurality of interlayer dielectric layers, and coupled to the plurality of electrodes layers through plurality of contacts which are coupled to the plurality of electrode layers, respectively, in the step region; and a plurality of vertical vias coupling the plurality of top wiring lines and the plurality of under wiring lines. The plurality of vertical vias may include first vertical vias that pass through a first opening defined in the electrode layers and the interlayer dielectric layers in the step region, and second vertical vias that pass through a second opening defined in the plurality of electrode layers and the plurality of interlayer dielectric layers in the cell region.

