BACKGROUND

Current methods of measuring phase noise are costly and complex. High speed probes for phase-locked loop (PLL) jitter measurement, for example, are expensive and the probes suffer from contact issues at high temperatures. On the other hand, a phase noise built-in self test (BIST) circuit may be able to detect the on-chip PLL jitter performance information and convert it to a low frequency digital signal.

Current methods to measure phase-locked loop (PLL) in-band phase noise utilize 2nd-order delta sigma (ΔΣ) time-to-digital converters (TDC). One feature of ΔΣ converters or modulators is that they can shape the quantization noise to higher frequencies that reflect the low frequency input noise. Current TDC structures utilize cascade type continuous time 2ndorder ΔΣ modulators. However, high order continuous time ΔΣ modulators suffer from stability issues. In order to avoid stability issues, current TDC structures increase the clock rate up to 340 MHz, for example, for the PLL and built-in self test (BIST). However, a high frequency input clock is not suitable for general PLL applications. Therefore, current methods for measuring PLL in-band phase noise are not entirely satisfactory.

The information disclosed in this Background section is intended only to provide context for various embodiments of the invention described below and, therefore, this Background section may include information that is not necessarily prior art information (i.e., information that is already known to a person of ordinary skill in the art). Thus, work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

