FIELD

The present disclosure relates generally to the field of semiconductor devices, and particularly to a three-dimensional memory device including discrete charge storage elements and methods of manufacturing the same.

BACKGROUND

Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36.

SUMMARY

According to an aspect of the present disclosure, a method of forming a three-dimensional memory device is provided, which comprises: forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layer; forming a memory opening through the alternating stack; forming annular lateral recesses at levels of the insulating layers by laterally recessing sidewalls of the insulating layers relative to sidewalls of the spacer material layers around the memory opening; forming a vertical stack of discrete metal portions in the annular lateral recesses; forming a semiconductor material layer on the vertical stack of the metal portions; forming a vertical stack of metal-semiconductor alloy portions by reacting the vertical stack of metal portions with portions of the semiconductor material layer located at levels of the insulating layers; removing the vertical stack of metal-semiconductor alloy portions selective to unreacted portions of the semiconductor material layer, wherein unreacted portions of the semiconductor material layer remain at levels of the spacer material layers and comprise a vertical stack of discrete semiconductor material portions; and forming a tunneling dielectric layer and a vertical semiconductor channel in the memory opening.

According to another aspect of the present disclosure, a three-dimensional memory device is provided, which comprises: an alternating stack of insulating layers and electrically conductive layers located over a substrate; a memory opening vertically extending through the alternating stack, wherein the memory opening has laterally-protruding portions that extend outward at each level of the insulating layers; and a memory opening fill structure located in the memory opening and comprising, from outside to inside, a blocking dielectric layer, charge storage structures comprising a vertical stack of discrete semiconductor material portions and at least one silicon nitride material portion in contact with the vertical stack, a tunneling dielectric layer in contact with the charge storage structures, and a vertical semiconductor channel.

According to yet another aspect of the present disclosure, a three-dimensional memory device is provided, which comprises: an alternating stack of insulating layers and electrically conductive layers located over a substrate; a memory opening vertically extending through the alternating stack, wherein the memory opening has laterally-protruding portions that extend outward at levels of the insulating layers; and a memory opening fill structure located in the memory opening and comprising, from outside to inside, a blocking dielectric layer, a vertical stack of discrete charge storage material portions, a tunneling dielectric layer, and a vertical semiconductor channel, wherein each charge storage material portion comprises a tubular portion located at a level of a respective one of the electrically material layers, an upper flange portion laterally extending outward from an upper end of an outer sidewall of the tubular portion, and a lower flange portion laterally extending outward from a lower end of the outer sidewall of the tubular portion.

According to still another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided, which comprises: forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layer; forming a memory opening through the alternating stack; forming annular lateral recesses at levels of the insulating layers by laterally recessing sidewalls of the insulating layers relative to sidewalls of the spacer material layers around the memory opening; forming a vertical stack of discrete metal portions in the annular lateral recesses; forming a semiconductor material layer on the vertical stack of the metal portions; removing the vertical stack of discrete metal portions and portions of the semiconductor material layer that are adjacent to the vertical stack of discrete metal portions, wherein remaining portions of the semiconductor material layer comprise a vertical stack of semiconductor material portions, and each of the semiconductor material portions comprises a tubular portion, an upper flange portion laterally extending outward from an upper end of an outer sidewall of the tubular portion, and a lower flange portion laterally extending outward from a lower end of the outer sidewall of the tubular portion; and forming a tunneling dielectric layer and a vertical semiconductor channel in the memory opening.

According to another aspect of the present disclosure, a three-dimensional memory device is provided, which comprises: an alternating stack of insulating layers and electrically conductive layers located over a substrate; a memory opening vertically extending through the alternating stack, wherein the memory opening has laterally-protruding portions that extend outward at levels of the insulating layers; and a memory opening fill structure located in the memory opening and comprising, from outside to inside, a blocking dielectric layer, a vertical stack of charge storage material portions, a tunneling dielectric layer, and a vertical semiconductor channel, and a vertical stack of discrete annular insulating material portions located at the levels of the insulating layers between the blocking dielectric layer and the tunneling dielectric layer.

