CROSS-REFERENCE TO RELATED APPLICATION

This U.S. nonprovisional application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2019-0124864 filed on Oct. 8, 2019, in the Korean Intellectual Property Office, the disclosures of which are hereby incorporated by reference in their entirety.

BACKGROUND

The inventive concepts relate to semiconductor devices and/or methods of fabricating the same, and more particularly, to semiconductor memory devices with improved electrical characteristics and/or methods of fabricating the same.

Semiconductor devices have been highly integrated for satisfying high performance and low manufacturing costs of semiconductor devices which are required by customers. Because integration of semiconductor devices is an important factor in determining product prices, high integrated semiconductor devices are increasingly demanded. Integration of typical two-dimensional or planar semiconductor devices is primarily determined by the area occupied by a unit memory cell, and thus it is greatly influenced by the level of technology for forming fine patterns. However, the extremely expensive processing equipment needed for fine patterning may set a practical limitation on increasing the integration of the two-dimensional or planar semiconductor devices. Therefore, there have been proposed three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells.

SUMMARY

Some example embodiments of the inventive concepts provide three-dimensional semiconductor memory devices with improved electrical characteristics and increased reliability.

Some example embodiments of the inventive concepts provide methods of fabricating a three-dimensional semiconductor memory device with improved electrical characteristics and increased reliability.

According to an example embodiment of the inventive concepts, a method of fabricating a semiconductor memory device includes forming a mold structure by alternately stacking a plurality of first insulating layers and a plurality of second insulating layers on a substrate, patterning the mold structure to form a first trench that exposes a first inner sidewall of the mold structure, growing a vertical semiconductor layer in the first trench such that the vertical semiconductor layer covers the first inner sidewall, using the substrate as a seed, patterning the mold structure to form a second trench that exposes a second inner sidewall of the mold structure, forming a plurality of recesses by selectively removing the second insulating layers from the mold structure through the second trench, and horizontally growing a plurality of horizontal semiconductor layers in corresponding recesses, using the vertical semiconductor layer as a seed.

According to an example embodiment of the inventive concepts, a semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate, each of the plurality of layers including a bit line extending in a first direction and a semiconductor pattern extending in a second direction from the bit line, the second direction intersecting the first direction, a gate electrode penetrating the stack structure and vertically extending along semiconductor pattern included in each of the plurality of layers, and a data storage element electrically connected to the semiconductor pattern. The data storage element may include a first electrode electrically connected to the semiconductor pattern, a second electrode on the first electrode, and a dielectric layer between the first electrode and the second electrode. The semiconductor pattern may have a lattice defect that obliquely extends from a bottom surface of the semiconductor pattern toward a top surface of the semiconductor pattern.

According to an example embodiment of the inventive concepts, a semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate, each of the plurality of layers including an insulating layer, a bit line extending in a first direction on the insulating layer, and a semiconductor pattern extending in a second direction from the bit line, the second direction intersecting the first direction, a gate electrode penetrating the stack structure and vertically extending along the semiconductor pattern included in each of the plurality of layers, and a data storage element electrically connected to the semiconductor pattern. The data storage element may include a first electrode electrically connected to the semiconductor pattern, a second electrode on the first electrode, and a dielectric layer between the first electrode and the second electrode. The semiconductor pattern may have a lattice defect therein. The lattice defect may be at an angle of 50° to 60° with respect to a top surface of the insulating layer below the semiconductor pattern.

