FIELD OF THE INVENTION

The present invention relates generally to the field of communications, and more particularly to high speed electronic signaling within and between integrated circuit devices.

BACKGROUND

The performance of many digital systems is limited by the interconnection bandwidth within and between integrated circuit devices (ICs). High performance communication channels between ICs suffer from many effects that degrade signals. Primary among them is inter-symbol interference (ISI) from high frequency signal attenuation and reflections due to impedance discontinuities.

ISI becomes more pronounced at higher signaling rates, ultimately degrading signal quality to the point at which distinctions between originally transmitted signal levels may be lost. Some receivers cancel ISI using a decision-feedback equalizer (DFE). DFEs multiply each of N recently received symbols by respective tap coefficients, the resulting products representing the ISI attributable to the corresponding symbol. The sum of these products is subtracted from the received signal prior to sampling. The ISI associated with the prior data is thereby reduced or eliminated.

In very high-speed systems it can be difficult to resolve the most recent data bit or bits in time to calculate their impact on the incoming symbol. Some receivers therefore ignore the impact of such symbols on the incoming signal, and consequently fail to correct for the ISI attributed to those symbols. Other receivers employ partial response DFEs (PrDFEs) that obtain multiple samples of the incoming data using multiple correction coefficients, one for each of the possible values of the most recently received symbol or symbols. The correct sample is then selected after the most recently received symbol or symbols are resolved.

PrDFEs are effective, but require a separate subtraction and sampling path for each possible value of the most recently received symbol or, in the case of multiple symbols (multi-symbol PrDFE), a separate computational path for each possible combination of the multiple symbol values. This results in e.g. 2Mpaths in a binary PrDFE system that considers M prior symbols. The additional paths occupy area, require power, and slow signal rates by increasing the input capacitance of the receiver. There is therefore a need for power and area-efficient receivers capable of filtering incoming signals to cancel ISI from the most recently received symbol or symbols.

