CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims priority to Chinese Patent Application No. 201811636763.X, filed on Dec. 29, 2018, entitled “Method and apparatus for analyzing semiconductor wafer”, which is incorporated by reference herein for all purposes.

FIELD

The invention relates to the field of defect analysis, in particular to defect analysis of semiconductor wafers and monitoring and early warning thereof.

BACKGROUND

Defect monitoring and defect analysis have always been indispensable parts of the semiconductor process. Especially in the process of large integrated circuit wafer production, monitoring the defect problem generated in the process at each process node is a necessary means to control the improvement of yield. In other words, how to accurately screen defective semiconductor wafers from a large number of semiconductor wafers is a prerequisite for ensuring subsequent defect analysis and control to improve yield.

At present, the industry mainly relies on the defect number threshold alarm for online defect monitoring. With the gradual development of the semiconductor manufacturing process, the absolute number of defects has been well controlled. Therefore, relying solely on the defect number threshold alarm cannot effectively screens out the defective semiconductor wafers.

Furthermore, due to its specific machine structures or special process operations, different processes may cause special or regular distribution of defects. For example, in a defect detecting process of a dry etching process, since the machine structure has inherent defects, inevitably accumulate polymer deposited during the long-term dry etching process on certain fixed parts above the cavity. If these polymers are dropped on the wafer being worked on, the wafers that are being worked on will be incompletely dried, some of the patterns cannot be etched successfully, and a special distributed defect wafer is formed. Due to the different number of drops, the number of defects will vary to different extents. Large differences in the number of defects make it difficult to monitor the above defects.

For such special distribution defects, the advanced approach in current industry is to generate surface defect maps for semiconductor wafers and to intelligently identify images by similar or simulated face recognition. This method mainly identifies the similar defect maps by grasping and comparing the feature points. This kind of intelligent picture recognition method has a higher recognition rate for a serious or very typical special distributed defect wafer map, it is not possible to accurately identify types that have a small interception or a large variation in the area of the defect.

In view of this, there is a need for a method and apparatus for analyzing semiconductor wafers, which are capable of intelligently classifying and identifying different numbers of defects exhibiting various distributions on different semiconductor wafers, and performing alarm interception or unified classification analysis the defects to finally achieve the long-term effective monitoring and analysis of surface defects of semiconductor wafers.

SUMMARY

A brief summary on one or more aspects is given below to provide the basic understanding for these aspects. This summary is not an exhaustive overview of all the contemplated aspects and is neither intended to indicate critical or decisive elements of all aspects nor to attempt to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a preface for a more detailed description presented later.

As described above, in order to solve the problem that the prior art cannot effectively monitor and analyze various defects of different numbers and different distribution situations, the invention provides a method of analyzing a semiconductor wafer for analyzing a defect distribution pattern on a semiconductor wafer to be tested, the method comprising:

obtaining a defect distribution map of the semiconductor wafer to be tested, the defect distribution map indicating a defect distribution within a surface of the semiconductor wafer to be tested;

establishing a three-dimensional model to be tested according to the defect distribution map, wherein an XY plane of the three-dimensional model to be tested corresponds to the surface of the semiconductor wafer to be tested, and a Z-axis of the three-dimensional model to be tested corresponds to the number of defects in each grid unit in the XY plane; and

calculating a similarity between the three-dimensional model to be tested and at least one three-dimensional reference model to determine a defect distribution pattern of the semiconductor wafer to be tested, wherein each three-dimensional reference model indicates a pattern of defect distribution.

In the above embodiments, the method further comprises: adjusting the three-dimensional model to be tested to obtain an adjusted three-dimensional model to be tested; and

calculating the similarity further includes calculating a similarity between the adjusted three-dimensional model to be tested and the at least one three-dimensional reference model to determine the defect distribution pattern of the semiconductor wafer to be tested.

In the above embodiments, the adjusting the three-dimensional model to be tested further comprises: normalizing the number of defects in each grid unit in the XY plane to obtain the Z-axis adjusted three-dimensional model to be tested.

In the above embodiments, the adjusting the three-dimensional model to be tested further comprises: Fourier transforming the number of defects in each grid unit in the XY plane to obtain the Z-axis adjusted three-dimensional model to be tested.

In the above embodiments, the adjusting the three-dimensional model to be tested further comprises:

in response to the number of grid units of the XY plane of the three-dimensional model to be tested being inconsistent with the number of grid units of the XY plane of the at least one three-dimensional reference model, re-gridding the XY plane of the three-dimensional model to be tested according to the number of grid units of the XY plane of the at least one three-dimensional reference model to obtain the XY plane adjusted three-dimensional model to be tested.

In the above embodiments, the adjusting the three-dimensional model to be tested further comprises: rotating the three-dimensional model to be tested multiple times around the Z-axis;

the computing further comprises, for each of the at least one three-dimensional reference model, calculating the similarity between the three-dimensional reference model and the three-dimensional model to be tested after each rotation, wherein the highest similarity is the similarity between the three-dimensional model to be tested and the three-dimensional reference model.

In the above embodiments, the at least one three-dimensional reference model comprises a plurality of three-dimensional reference models; the method further comprises:

calculating a similarity between each of the three-dimensional reference models and the three-dimensional model to be tested; and

the defect distribution pattern of the semiconductor wafer to be tested is determined to be a defect distribution pattern indicated by the three-dimensional reference model corresponding to the highest similarity in response to the highest similarity among the obtained plurality of similarities being higher than a preset threshold.

In the above embodiments, the method further comprises: establishing the at least one three-dimensional reference model.

In the above embodiments, the establishing further comprises:

obtaining distribution maps of a plurality of semiconductor wafer samples;

establishing a plurality of three-dimensional sample models based on defect distribution maps of the plurality of semiconductor wafer samples;

classifying the plurality of three-dimensional sample models into at least one category according to a degree of similarity between the plurality of three-dimensional sample models, and the three-dimensional sample models included in a same category indicate a same defect distribution pattern; and

selecting any one three-dimensional sample model in the same category as the three-dimensional reference model for that category.

In the above embodiments, when it is determined that the defect distribution of the semiconductor wafer to be tested is a defect distribution pattern indicated by the at least one three-dimensional reference model, the method further comprises:

marking the semiconductor wafer to be tested, and/or further analyzing the cause of the defect of the semiconductor wafer to be tested.

The invention also provides an apparatus for analyzing a semiconductor wafer for performing a method of analyzing a semiconductor wafer for analyzing a defect distribution pattern on a semiconductor wafer to be tested, the apparatus comprising a processor and a memory having a database stored therein, wherein

at least one three-dimensional reference model is stored in the database, and each three-dimensional reference model indicates a pattern of defect distribution;

the processor is configured to: obtain a defect distribution map of the semiconductor wafer to be tested, the defect distribution map indicating a defect distribution within a surface of the semiconductor wafer to be tested;

establish a three-dimensional model to be tested according to the defect distribution map, wherein an XY plane of the three-dimensional model to be tested corresponds to the surface of the semiconductor wafer to be tested, and a Z-axis of the three-dimensional model to be tested corresponds to the number of defects in each grid unit in the XY plane; and

calculate a similarity between the three-dimensional model to be tested and the at least one three-dimensional reference model to determine a defect distribution pattern of the semiconductor wafer to be tested.

In the above embodiments, the processor is further configured to: adjust the three-dimensional model to be tested to obtain an adjusted three-dimensional model to be tested; and

calculate a similarity between the adjusted three-dimensional model to be tested and the at least one three-dimensional reference model to determine a defect distribution pattern of the semiconductor wafer to be tested.

In the above embodiments, the processor is further configured to: normalize the number of defects in each grid unit in the XY plane to obtain the Z-axis adjusted three-dimensional model to be tested.

In the above embodiments, the processor is further configured to: Fourier transforming the number of defects in each grid unit in the XY plane to obtain the Z-axis adjusted three-dimensional model to be tested.

In the above embodiments, the processor is further configured to:

in response to the number of grid units of the XY plane of the three-dimensional model to be tested being inconsistent with the number of grid units of the XY plane of the at least one three-dimensional reference model, re-grid the XY plane of the three-dimensional model to be tested according to the number of grid units of the XY plane of the at least one three-dimensional reference model to obtain the XY plane adjusted three-dimensional model to be tested.

In the above embodiments, the processor is further configured to: rotate the three-dimensional model to be tested multiple times around the Z-axis;

for each of the at least one three-dimensional reference model, calculate the similarity between the three-dimensional reference model and the three-dimensional model to be tested after each rotation, wherein the highest similarity is the similarity between the three-dimensional model to be tested and the three-dimensional reference model.

In the above embodiments, the at least one three-dimensional reference model stored in the database comprises a plurality of three-dimensional reference models;

the processor is configured to: calculate a similarity between each of the three-dimensional reference models and the three-dimensional model to be tested; and

the defect distribution pattern of the semiconductor wafer to be tested is determined to be a defect distribution pattern indicated by the three-dimensional reference model corresponding to a highest similarity in response to the highest similarity among the obtained plurality of similarities being higher than a preset threshold.

In the above embodiments, the processor is further configured to:

establish the at least one three-dimensional reference model and store the established at least one three-dimensional reference model to the database.

In the above embodiments, the processor is further configured to:

obtain distribution maps of a plurality of semiconductor wafer samples;

establish a plurality of three-dimensional sample models based on defect distribution maps of the plurality of semiconductor wafer samples;

classify the plurality of three-dimensional sample models into at least one category according to a degree of similarity between the plurality of three-dimensional sample models, wherein the three-dimensional sample models included in a same category indicate a same defect distribution pattern; and

select any one three-dimensional sample model in the same category as the three-dimensional reference model for that category.

In the above embodiments, the processor is further configured to:

mark the semiconductor wafer to be tested, and/or further analyzing the cause of the defect of the semiconductor wafer to be tested when it is determined that the defect distribution of the semiconductor wafer to be tested is a defect distribution pattern indicated by the at least one three-dimensional reference model.

As described above, according to the method and apparatus for analyzing a semiconductor wafer of the present invention, it is possible to intelligently identify different numbers of defects on different semiconductor wafers and exhibiting various distributions by three-dimensional modeling the defect map of the semiconductor wafer, and makes alarm interception or unified classification analysis possible in subsequent steps. Through the method and device provided by the invention, long-term effective monitoring and analysis of surface defects of the semiconductor wafer can be realized.

