BACKGROUND

Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and fabrication methods thereof.

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A 3D memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

SUMMARY

Embodiments of 3D memory devices and methods for forming the same are disclosed herein.

In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a slit structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the slit structure. The 3D memory device further includes an insulating structure extending vertically from the second side of the substrate to the first doped region. The 3D memory device further includes a plurality of second doped regions in the substrate and separated by the insulating structure.

In another example, a 3D memory device includes a first semiconductor structure including a peripheral circuit, a second semiconductor structure, and a joining interface between the first semiconductor structure and the second semiconductor structure. The second semiconductor structure includes a memory stack including interleaved conductive layers and dielectric layers. The second semiconductor structure also includes a plurality of channel structures each extending vertically through the memory stack and electrically connected to the peripheral circuit. The second semiconductor structure also includes a plurality of slit structures each extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The second semiconductor structure further includes a semiconductor layer including a plurality of first doped regions each in contact with a respective one of the plurality of slit structures, and a plurality of second doped regions in contact with the plurality of first doped regions. The second semiconductor structure further includes a plurality of insulating structures each extending vertically from a backside of the semiconductor layer to a respective one of the plurality of first doped regions to separate the plurality of second doped regions into the blocks.

In still another example, a method for forming a 3D memory device is disclosed. A doped area is formed from a first side of a substrate in the substrate. A plurality of channel structures each extending vertically through a memory stack at the first side of a substrate are formed. A first doped region is formed in the substrate and in contact with the doped area. A slit structure extending vertically through the memory stack to the first doped region, and extending laterally to separate the plurality of channel structures into a plurality of blocks is formed. An insulating structure extending vertically from the second side of the substrate to the first doped region is formed to separate the doped area into a plurality of second doped regions.

