TECHNICAL FIELD

The present disclosure relates generally to a semiconductor assembly and, more particularly, to a semiconductor assembly with three-dimensional integrated circuits (3D ICs) and a method of manufacturing the same.

DISCUSSION OF THE BACKGROUND

As integrated circuit (IC) technologies continue to advance, ongoing efforts seek to increase performance or reduce costs. One approach explored to realize such benefits is implementation of stacked three-dimensional integrated circuits (3D ICs). Such 3D IC technology is driven by strong demand for high-speed, high-density, small and multifunctional electronic devices. Some areas where 3D ICs are a suitable consideration include stacking of two or more chips fabricated using different processes or stacking of chips that are fabricated using the same process to reduce the footprint of the IC apparatus.

Through-silicon via (TSV) interconnection is an effective approach for 3D integration due to its shortest interconnection distance and fastest speed. Typically, TSVs are formed by etching vias through the chip and filling the vias with metal after chip circuits and wiring are nearly complete. TSV etching requires etching vias completely through a stack of back end of line (BEOL) layers to the silicon chip.

The 3D ICs provide advantages of integration density, greater speed and greater bandwidth, because of the decreased length of interconnects between the stacked devices. However, there are many challenges related to 3D ICs.

This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this Discussion of the Background section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.

SUMMARY

One aspect of the present disclosure provides a semiconductor assembly. The semiconductor assembly comprises a first device, a second device, a passivation layer and an interconnect structure. The first device comprises a first top metal layer. The second device is bonded to the first device and comprises a second bottom metal layer. The passivation layer is disposed on the second device. The interconnect structure electrically couples the first device to the second device, wherein the interconnect structure comprises a head member, a first leg and a second leg. The head member is disposed on the passivation layer. The first leg penetrates through the passivation layer and the second device, wherein the first leg connects the head member to the first top metal layer. The second leg penetrates through the passivation layer and extends into the second device to connect the head member to the second bottom metal layer. The first leg and the second leg comprise a top portion and a bottom portion. The top portion is disposed in the passivation layer and has a first critical dimension. The bottom portion is connected to the top portion and has a second critical dimension, wherein the second critical dimension is greater than the first critical dimension.

In some embodiments, the first device and the second device are memory devices.

In some embodiments, the first leg electrically connects the first top metal layer of the first device to the head member and the second leg electrically connects the second bottom metal layer of the second device to the head member.

In some embodiments, the semiconductor assembly further comprises a bonding layer interposed between the first device and the second device.

In some embodiments, the first device and the second device are arranged in a front-to-front configuration.

In some embodiments, the head member is surrounded by a protection layer.

In some embodiments, the head member is above the first leg and the second leg.

In some embodiments, the semiconductor assembly further comprises a liner layer, wherein the first leg and the second leg are surrounded by the liner layer.

Another aspect of the present disclosure provides a semiconductor assembly. The semiconductor assembly comprises a first device, a second device, a passivation layer and an interconnect structure. The first device comprises a first top metal layer. The second device is bonded to the first device and comprises a second bottom metal layer. The passivation layer is disposed on the second device. The interconnect structure electrically couples the first device to the second device, wherein the interconnect structure comprises a head member, a first leg and a second leg. The head member is disposed on the passivation layer. The first leg penetrates through the passivation layer and the second device, wherein the first leg connects the head member to the first top metal layer. The second leg penetrates through the passivation layer and extends into the second device to connect the head member to the second bottom metal layer. The first leg and the second leg comprise a top portion, an intermediate portion and a bottom portion. The top portion penetrates through the passivation layer and has a first critical dimension that gradually decreases at positions of increasing distance from the head member. The intermediate portion extends from the top portion and penetrates through a second substrate of the second device, wherein the intermediate portion has a second critical dimension that gradually increases at positions of increasing distance from the head member. The bottom portion extends from the intermediate portion.

In some embodiments, the bottom portion has a substantially uniform critical dimension.

In some embodiments, the top portion and the intermediate portion have identical maximum critical dimension.

In some embodiments, the semiconductor assembly further comprises a liner layer, wherein the first leg and the second leg are surrounded by the liner layer.

In some embodiments, the head member is surrounded by a protection layer.

In some embodiments, the semiconductor assembly further comprises a bonding layer interposed between the first device and the second device.

Another aspect of the present disclosure provides a method for fabricating a semiconductor assembly. The method comprises providing a first device and a second device, wherein the first device comprises a first top metal layer and the second device comprises a second bottom metal layer disposed on a second substrate; bonding the second device to the first device via a bonding layer; forming a passivation layer on the second device; forming a first trench penetrating through the passivation layer, the second device and the bonding layer to expose the first top metal layer; forming a second trench penetrating through the passivation layer and a portion of the second device to expose the second bottom metal layer; forming a liner layer within the first trench and the second trench; and depositing a first conductive material to fill the first trench and the second trench, wherein surfaces of the passivation layer exposed by the first trench and the second trench are discontinuous with surfaces of the second substrate exposed by the first trench and the second trench.

In some embodiments, the forming of the first trench and the second trench comprise: forming a plurality of first openings penetrating through the passivation layer; forming a plurality of second openings penetrating through the second substrate, wherein the second openings connected to the first openings; forming a third opening connected to one of the second openings to expose the first top metal layer; and forming a fourth opening connected to the other second opening to expose the second bottom metal layer.

In some embodiments, the first openings have a first width that gradually decreases at positions of decreasing distance from the first device.

In some embodiments, the second openings have a second width that gradually increases at positions of decreasing distance from the first device.

In some embodiments, the method further comprises: performing a polishing process to remove the first conductive material above a top surface of the passivation layer.

In some embodiments, the method further comprises: forming a protection layer on the passivation layer; forming a contact hole that exposes a portion of the passivation layer and the first conductive material in the first trench and in the second trench and; and depositing a second conductive material in the contact hole.

In the present disclosure, the waist portions prevent the first trench and the second trench from forming a funnel-shaped profile so that the liner layer on a sidewall surface within the trench will not be overly consumed in a subsequent liner etching process. A liner layer can be robustly formed in the first trench and the second trench without a crack or hole appearing in the liner layer. As a result, the first leg and the second leg can be completely isolated from the second device. The copper-containing material in the first conductive material will not diffuse through the liner to the silicon-containing second device. In addition, current leakage or shorting problems can be prevented by isolation provided by the liner.

The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and technical advantages of the disclosure will be described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

