BACKGROUND

Once memory cells in a data storage device, e.g., a memory system, are programmed, data can be read from the memory cells by sensing a programmed state of each memory cell by comparing a cell threshold voltage to one or more read voltages. However, the cell threshold voltage may change due to one or more factors, such as read disturbance or data retention, which may make the sensed programming states different from the written programmed states and cause failed bits in a reading output of the data.

SUMMARY

The present disclosure describes systems and techniques for determining read voltages for memory systems, e.g., non-volatile memory (NVM) systems, with machine learning (ML), which can reduce fail bit counts (FBCs) in reading outputs of memory data.

One aspect of the present disclosure features a memory system including a memory and a memory controller coupled to the memory and configured to: obtain a first reading output of target memory data in the memory by using a first read voltage corresponding to a first set of parameters associated with the target memory data; in response to determining that the first reading output fails to pass an Error-Correcting Code (ECC) test, obtain a second reading output of the target memory data by using a second read voltage corresponding to a second set of parameters associated with the target memory data, the second read voltage being generated using at least one machine learning (ML) algorithm based on the second set of parameters, the second set of parameters including the first set of parameters; and in response to determining that the second reading output passes the ECC test, output the second reading output as a target reading output of the target memory data.

In some embodiments, the memory controller is configured to generate the first read voltage using stored read voltage data based on the first set of parameters. The stored read voltage data can be stored in the memory.

In some embodiments, the stored read voltage data is generated based on supervised ML training using a plurality of inputs associated with the memory and corresponding optimal read voltages, each of the optimal read voltages corresponding to a minimum failed bit count of a reading output for a respective page in the memory with a respective input of the inputs, each of the inputs including respective values of a plurality of parameters, the plurality of parameters including the first set of parameters.

In some embodiments, each of the plurality of parameters has a respective influence level on a memory cell characteristic of the memory, and value intervals of the plurality of parameters in the inputs are determined based on the respective influence levels of the plurality of parameters. The supervised ML training can be performed during manufacturing the memory system.

In some embodiments, the stored read voltage data includes a transfer function generated based on the supervised ML training, the transfer function representing a relationship between an input of the plurality of parameters and an optimal read voltage. The transfer function can include a lookup table, a hash function, or a k mean.

In some embodiments, the memory controller is configured to update the stored read voltage data with the second read voltage in response to determining that the second reading output passes the ECC test. The memory controller can be configured to: update the stored read voltage data in response to determining that threshold voltages of states of memory cells in the target memory data are within corresponding predetermined ranges.

In some embodiments, the memory controller is configured not to update the stored read voltage data with the second read voltage in response to determining that the second reading output passes the ECC test and that at least one threshold voltage of a state of memory cells in the target memory data is outside of a corresponding predetermined range.

In some embodiments, the memory controller is configured to: in response to determining that the second reading output fails to pass the ECC test, adjust the second set of parameters and generate a new second read voltage using the at least one ML algorithm based on the adjusted second set of parameters. The memory controller can be configured to adjust the second set of parameters by adding one or more new parameters associated with the target memory data.

In some embodiments, the memory controller is configured to: determine whether the first reading output passes the ECC test by determining whether a failed bit count (FBC) of the first reading output is beyond a first predetermined threshold.

In some embodiments, the memory controller is configured to: in response to determining that the failed bit count of the first reading output is no more than the first predetermined threshold, determine whether the failed bit count of the first reading output is beyond a second predetermined threshold that is smaller than the first predetermined threshold.

In some embodiments, the memory controller is configured to: in response to determining that the failed bit count of the first reading output is no more than the second predetermined threshold, output the first reading output as the target reading output of the target memory data.

In some embodiments, the memory controller is configured to: in response to determining that the failed bit count of the first reading output is beyond the second predetermined threshold and no more than the first predetermined threshold, generate a third read voltage using the at least one ML algorithm. The memory controller can be configured to update the stored read voltage data with the third read voltage. In some embodiments, the memory controller is configured to: update the stored read voltage data with the third read voltage in response to determining that threshold voltages of states of memory cells in the target memory data are within corresponding predetermined ranges.

In some embodiments, the first set of parameters includes at least one of address information, a number of P/E cycles, a reading temperature, a read disturbance level, or a retention time.

In some embodiments, the second set of parameters includes at least one of a failed bit count in the first reading output, a number of “1” values obtained for each read voltage, a number change of “1” values between a previous read voltage and a current read voltage, a read time, a syndrome of low-density parity-check (LDPC) code, or a number of iteration of LDPC code.

In some embodiments, the at least one ML algorithm includes at least one of a linear regression, a support vector regression, or a deep learning algorithm including a convolutional neural network (CNN) algorithm or a Recurrent Neural Network (RNN) algorithm.

In some embodiments, the memory controller is configured to: in response to determining that the first reading output passes the ECC test, output the first reading output as the target reading output of the target memory data.

In some embodiments, the memory controller is configured to: receive a read quest from a host device, the read request including information of the target memory data; and output the target reading output of the target memory data to the host device.

Another aspect of the present disclosure features a memory system including a memory and a memory controller coupled to the memory and configured to: determine a first read voltage using stored read voltage data based on a first set of parameters associated with memory data to be read from the memory; obtain a first reading output by reading the memory data using the first read voltage; determine whether the first reading output passes an Error Correction Code (ECC) test; in response to determining that the first reading output fails to pass the ECC test, generate a second read voltage using at least one machine learning (ML) algorithm based on a second set of parameters associated with the memory data, the second set of parameters including the first set of parameters and at least one additional parameter; obtain a second reading output by reading the memory data using the second read voltage; determine whether the second reading output passes the ECC test; and in response to determining that the second reading output passes the ECC test, output the second reading output as the memory data read from the memory.

In some embodiments, the memory controller is configured to: in response to determining that the second reading output passes the ECC test, update the stored read voltage data with the second read voltage.

A further aspect of the present disclosure features a memory controller coupled to a memory, the memory controller including: at least one processor; an Error Correction Code (ECC) circuit; a machine learning (ML) circuit; and at least non-transitory medium storing instructions executable by the processor. The memory controller is configured to: determine, by the ML circuit, a first read voltage using stored read voltage data based on a first set of parameters associated with memory data to be read from the memory; obtain, by the processor, a first reading output by reading the memory data using the first read voltage; determine, by the ECC circuit, whether the first reading output passes an ECC test; in response to determining that the first reading output does not pass the ECC test, generate, by the ML circuit, a second read voltage using at least one machine learning (ML) algorithm based on a second set of parameters associated with the memory data, the second set of parameters including the first set of parameters and at least one additional parameter; obtain, by the processor, a second reading output by reading the memory data using the second read voltage; determine, by the ECC circuit, whether the second reading output passes the ECC test; and in response to determining that the second reading output passes the ECC test, output, by the processor, the second reading output as the memory data read from the memory.

In some embodiments, the stored read voltage data is stored in the memory, and the memory controller includes a memory interface, and the ML circuit is configured to communicate with the memory through the memory interface.

In some embodiments, the memory controller includes an open NAND flash interface (ONFI) or a toggle interface.

Implementations of the above techniques include methods, systems, computer program products and computer-readable media. In one example, a method can be performed by a memory controller coupled to a non-volatile memory and the method can include the above-described actions performed by the memory controller, e.g., the actions for determining read voltages for the non-volatile memory with machine learning. In another example, one such computer program product is suitably embodied in a non-transitory machine-readable medium that stores instructions executable by one or more processors. The instructions are configured to cause the one or more processors to perform the above-described actions. One such computer-readable medium stores instructions that, when executed by one or more processors, are configured to cause the one or more processors to perform the above-described actions.

The details of one or more disclosed implementations are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings and the claims.

