FIELD OF INVENTION

The present invention relates to the field of display, and in particular, to an array substrate, a manufacturing method thereof, and a display module.

DESCRIPTION OF PRIOR ART

Array substrates fabricated using low temperature poly-silicon (LTPS) have high carrier mobility and are therefore the first choice for driving back-plates of flexible display panels. However, in a thin film transistor device structure of the array substrate, a patterned active layer is used as an active layer, and such a structure has its shortcomings that stress concentration occurs at edges of a channel of the active layer under the action of bending stress. This has a negative influence on electrical properties of the thin film transistor device, which in turn affects the normal display of the display panel.

Therefore, there is an urgent need for an array substrate, a method of fabricating the same, and a display module to solve the above problems.

SUMMARY OF INVENTION

The present invention provides an array substrate, a manufacturing method thereof, and a display module, so as to solve the negative influences of stress concentration at edges of the channel of an active layer when the existing array substrate is subjected to the bending stress, causing poor electrical conductivity of a thin film transistor device.

To solve the above problems, the technical solution provided by the present invention is as follows:

The present invention provides an array substrate including a substrate and a thin film transistor disposed on the substrate, wherein an active layer of the thin film transistor includes: a first region including source and drain doped regions doped with a first ion and a channel region which is not ion-doped, disposed between the source and drain doped regions; and a second region at least surrounding a side of the channel region not in contact with the source and drain doped regions, the second region being doped with a second ion, and the first region and the second region forming a PN junction.

According to an embodiment of the present invention, the first region and the second region have different conductivities.

According to an embodiment of the present invention, the first ion and the second ion are derived from different elements.

According to an embodiment of the present invention, the first region and the second region have a same thickness.

According to an embodiment of the present invention, the thin film transistor further includes a gate insulating layer disposed on the active layer and a gate layer disposed on the gate insulating layer, and wherein a pattern of the gate layer covers a pattern of the channel region from a top view.

According to an embodiment of the present invention, the second region is connected to a metal line having a constant voltage.

According to an embodiment of the present invention, the second region surrounds the first region.

According to another embodiment of the present invention, a method of fabricating an array substrate is provided, including:

Step S10, providing a substrate, and forming a polysilicon layer on the substrate, the polysilicon layer including a first region and a second region;

Step S20, performing implantation of a second ion on the second region;

Step S30, sequentially forming a gate insulating layer and a gate layer on the polysilicon layer which has been subjected to ion-implantation once, the gate layer covering the channel region;

Step S40, performing implantation of a first ion on the second region and the channel region of the first region, wherein areas in the first region which have been subjected to ion-implantation twice are formed into source and drain doped regions; and

Step S50, electrically connecting a metal wire having a constant voltage to the second region to form an active layer,

wherein the first region includes the source and drain doped regions and the channel region between the source and drain doped regions, the second region at least surrounds a side of the channel region not in contact with the source and drain doped regions, and the first region and the second region form a PN junction.

According to an embodiment of the present invention, the first ions and the second ions are derived from different elements.

According to an embodiment of the present invention, a concentration of the second ion during the implantation of the second ion is greater than a concentration of the first ion during the implantation of the first ion.

According to an embodiment of the present invention, the step S20includes: forming a photoresist layer on the polysilicon layer, exposing and developing the photoresist layer to obtain a pattern of the second region, performing the implantation of the second ion on the second region, and stripping the patterned photoresist.

According to an embodiment of the present invention, the method of fabricating an array substrate further includes forming an insulating layer and a gate layer on the active layer, wherein a pattern of the gate layer covers a pattern of the channel region from a top view.

According to an embodiment of the present invention, the second region surrounds the first region.

According to another embodiment of the present invention, a display module is provided, including an array substrate and a polarizer and a cover plate disposed over the array substrate, the array substrate including a substrate and a thin film transistor disposed on the substrate, wherein an active layer of the thin film transistor includes: a first region including source and drain doped regions doped with a first ion and a channel region which is not ion-doped, disposed between the source and drain doped regions; and a second region at least surrounding a side of the channel region not in contact with the source and drain doped regions, the second region being doped with a second ion, and the first region and the second region forming into a PN junction.

According to an embodiment of the present invention, the first region and the second region have different conductivities.

According to an embodiment of the present invention, the first ion and the second ion are derived from different elements.

According to an embodiment of the present invention, the first region and the second region have a same thickness.

According to an embodiment of the present invention, the thin film transistor further includes a gate insulating layer disposed on the active layer and a gate layer disposed on the gate insulating layer, and wherein a pattern of the gate covers a pattern of the channel region from a top view.

According to an embodiment of the present invention, the second region surrounds the first region.

According to an embodiment of the present invention, the second region is connected to a metal line having a constant voltage.

The present invention improves the bending resistance of a thin film transistor by providing a second region surrounding at least a side of a channel region not in contact with source and drain doped regions to reduce bending stress received by the channel region.

