BACKGROUND

In NAND flash memory, memory cells can store one or more bits as voltage values. For example, a single level cell stores one bit and the measured voltage value can be compared to a single voltage threshold to determine a logical value of the bit (e.g., a “0” or a “1”). A multi-level cell (MLC) can store two bits and the measured voltage value can be compared to three voltage thresholds to determine the logical value of each bit. Generally, the logical value stored in a memory cell is determined by a voltage range between each of the three voltage thresholds (e.g., 1-2V, 2-3V, 3-4V, etc.) in which the cell's threshold voltage lies. As more bits per memory cell are stored, the threshold voltage ranges become smaller, resulting in increased error rates in determining the memory cell's value.

Error-correction codes (ECCs) are typically used for various types of data storage devices including NAND flash memories. ECCs are also frequently used during the process of data transmission. ECC refers to codes that add redundant data, or parity data, to a message, such that the message can be recovered by a receiver even when a number of errors were introduced, either during the process of transmission, or storage. In general, the ECC can correct the errors up to the capability of the code being used. ECC decoding can include hard decoding, such as Bose-Chaudhuri-Hocquenghem (BCH) decoding, where the logical value stored in a memory cell is determined by the voltage range in which the cell's threshold voltage lies. ECC decoding can also include soft decoding, such as Low-density parity-check code (LDPC) decoding, where the logical value stored in a memory cell is represented as a probability distribution.

The accuracy of read threshold voltage is critical for storage devices, including solid state drives using NAND flash memory technology, because a better read threshold voltage results in a lower raw bit error rate (RBER), which determines SSD system performance such as input/output operations per second (IOPs) and throughput. However, during the life time of a storage device, the optimal read threshold voltage for a memory cell can change depending on a large number of variable factors. Theoretically, if all the factors affecting the change to a read threshold voltage are known, the optimal read threshold can be determined from offline memory characterization. For example, a look-up table can be generated, where the table associates optimal read thresholds with possible combinations of the variable factors under different realizations of these factors. However, such a table is practically challenging to implement in part because it would need a huge number of realizations and likely does not result in optimal voltage read thresholds because not all possible combinations and realizations can be determined offline.

BRIEF SUMMARY

Techniques related to improving a performance related to generating a voltage read range are described. The techniques involve a computer system for reading data from storage and implement methods on such a computer system. In an example, the computer system includes a processor and a memory communicatively coupled with the processor. The memory is configured to store client data, a voltage read range generator, and computer-readable instructions. The voltage read range generator receives a first set of parameters that represent a first probability distribution within a first voltage read range and a second set of parameters that represent a second probability distribution within a second voltage read range. The computer-readable instructions upon execution by the processor configure the computer system to perform operations. The operations include generating a voltage read threshold based on inputs to an objective function and the first voltage read range and second voltage read range.

In one example, a methods for improving a performance related to reading data stored in memory cells is disclosed. The method includes selecting a first voltage read range and a second voltage read range from multiple voltage read ranges that are associated with a number of bits storable in a memory cell. The method includes receiving a first set of parameters that represent a first probability distribution of first candidate voltage read thresholds within the first voltage read range. The method includes receiving a second set of parameters that represent a second probability distribution of second candidate voltage read thresholds within the second voltage read range. The method includes generating, based on an input to an objective function, a voltage read threshold. The method includes reading data stored in the memory cell based on the voltage read threshold.

This illustrative example is mentioned not to limit or define the disclosure, but to provide an example to aid understanding thereof. Additional embodiments and examples are discussed in the Detailed Description, and further description is provided there.

