TECHNICAL FIELD

The present disclosure relates to the technical field of testing of memory chips and, more specifically, to a method, a device, and a terminal for testing a memory chip.

BACKGROUND

With more advanced fabrication technologies of memory chips, the physical sizes of semiconductor devices are getting smaller and smaller. Although it is possible to integrate more storage capacities on a single memory chip, the electromagnetic interference may occur among memory cells. As a result, a read/write operation performed on a certain memory area may interference adjacent memory areas, and undesired currents may flow into or out from the neighboring memory cells. When such a read/write operation is repeated for a large number of times, the information stored on the adjacent memory cells may change, for example, from “0” to “1” or from “1” to “0”. This phenomenon is called bit flipping, and may be leveraged to commit attacks on the memory chip, i.e., which is commonly referred as bit-flipping attack or rowhammer attack.

Since bit-flipping attacks on a single line may involve hundreds of thousands of on and off operations, such attacks are generally associated with great randomness and high complexity. For this reason, it is difficult for existing test methods to simulate the attack process, and the testing may be difficult, inaccurate, and may take a long time. On the other hand, since the existing test methods may not be able to carry out a continuous wide-range test at one time, it is difficult to detect the status of the entire memory chip when it is attacked. Therefore, it is very difficult to verify the physical condition and specification of the memory chip.

It is to be noted that the above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.

SUMMARY OF THE DISCLOSURE

The present disclosure provides a method, a device, and a terminal for testing a memory chip, which provide beneficial options for overcoming or mitigating one or more problems described in the Background section.

One aspect of the present disclosure is directed to a method for testing a memory chip. The method may comprise setting an attack mode and random attack parameters, generating a random attack command according to the attack mode and random attack parameters, attacking the memory chip according to the random attack command, and testing the attacked memory chip and generating a test result.

In one embodiment of the present disclosure, the method may comprise choosing a capacity of the memory chip, choosing at least an attack range according to the capacity, wherein the at least attack range may comprise at least one of a range of row addresses and a range of column addresses, and setting an attack count.

In one embodiment of the present disclosure, the method may comprise randomly choosing an odd number of test lines within the attack range to form at least a test line set, choosing at least an aggressor in each test line set, and attacking the at least aggressor in each test line set according to the random attack command.

In one embodiment of the present disclosure, the at least aggressor may comprise at least a middle line in each test line set, the test lines may comprise word lines, bit lines, or a combination thereof, and the at least test line set may comprise at least a word line set, or at least a bit line set, or a combination thereof.

In one embodiment of the present disclosure, the method may comprise checking data on the at least aggressor and data on victims thereof. If the data on the at least aggressor differ the data on the victims thereof, the attack on the memory chip is completed.

In one embodiment of the present disclosure, the victims of the at least aggressor comprise adjacent test lines of the at least aggressor, or test lines spaced apart from the at least aggressor by at least one test line.

In one embodiment of the present disclosure, the method may comprise recording the attack count into the test result when the attack on the memory chip is completed.

One aspect of the present disclosure may comprise a device for testing a memory chip, comprising an attack configuration module configured to set an attack mode and random attack parameters, an attack command generation module configured to generate a random attack command according to the attack mode and random attack parameters, a random attack module configured to attack the memory chip according to the random attack command, and an attack testing module configured to test the attacked memory chip and generate a test result.

In one embodiment of the present disclosure, the attack configuration module may comprise a chip capacity configuration unit configured to choose a capacity of the memory chip, and an attack range configuration unit configured to choose at least an attack range according to the capacity, wherein the at least attack range may comprise at least one of a range of row addresses and a range of column addresses, and an attack count configuration unit, configured to set an attack count.

In one embodiment of the present disclosure, the random attack module may comprise a word line grouping unit configured to randomly choose an odd number of word lines to form a word line set and choose at least a middle word line in each word line set, and a word line attack unit configured to attack the at least middle word line in each word line set according to the random attack command. The random attack module may also comprise a bit line grouping unit configured to randomly choose an odd number of bit lines to form a bit line set and choose at least a middle bit line in each bit line set, and a bit line attack unit configured to attack the at least middle bit line in each bit line set according to the random attack command.

In one embodiment of the present disclosure, the attack testing module may be configured to check data on at least an aggressor and data on victims thereof. If the data on the at least aggressor differ the data on the victims thereof, the attack on the memory chip is completed.

In one embodiment of the present disclosure, the victims of the at least aggressor may comprise adjacent word lines of the at least aggressor and word lines spaced apart from the at least aggressor by at least one word line, and the at least aggressor may comprise at least a middle word line in each word line set.

In one embodiment of the present disclosure, the victims of the at least aggressor may comprise adjacent bit lines of the at least aggressor and bit lines spaced apart from the at least aggressor by at least one bit line, and the at least aggressor may comprise at least a middle bit line in each bit line set.

In one embodiment of the present disclosure, the attack count configuration unit may be configured to recoding the attack count into the test result when the attack on the memory chip is completed

One aspect of the present disclosure may be directed to a terminal for testing a memory chip that has experienced a random attack. The terminal may comprise the device as defined above, a processor, and a computer-readable storage unit comprising executable instructions, when executed, causing the processor to execute the method as described above.

The method, device, and terminal of the present disclosure offer the following advantages. Various types of attacks may be simulated and thus can perform a suitable test on the memory chip for the certain types of the actual attacks. Since the attacks can be randomized to any memory cell of the memory chip, testing of the whole memory chip is made possible.

The preceding summary is for illustration only and is not limiting in any sense. Besides the above illustrative aspects, embodiments, and features, other aspects, embodiments, and features will become apparent from the following detailed description in conjunction with the accompanying drawings.

