BACKGROUND

Field

The present invention relates to integrated circuit memory, including nonvolatile flash memory, and methods for operating the same.

Description of Related Art

In high density memory, such as 3D memory, the channel of memory cell transistors can have different resistivities before and after stress. For example, thin film polysilicon used in the vertical channel structures of 3D NAND memory can suffer changes in resistivity over time. The different resistances that arise because of this characteristic can cause the threshold voltages to shift by, for example, 10 to 30 milliVolts, which in turn can reduce the operating windows for the memory.

It is desirable to provide technologies than can improve the operating window for memory in these conditions.

SUMMARY

A memory is described comprising a memory array having a plurality of blocks, wherein blocks in the plurality of blocks are arranged to be activated for memory operations in response to corresponding groups of word lines. Control circuits are part of or coupled to the memory, and comprise logic to execute a read setup operation, including no-current read setup operations.

Generally, a device is described comprising a plurality of memory cells, and a plurality of bit lines, and sense amplifier circuits. Control circuits for the memory array comprise logic to execute a read setup operation, which can maintain more consistent resistivities or operating threshold voltages during the operation of the memory array. The read setup operation comprises applying a read setup bias to selected memory cells in the memory array, and disabling current flow through the selected memory cells to the sense amplifier circuits during the read setup bias.

Examples are described in which the memory cells are disposed in a plurality of NAND strings, each NAND string in the plurality of NAND strings having a string select gate controllable to connect the NAND string to, or disconnect the NAND string from, a corresponding bit line in the plurality of bit lines. An example read setup operation disables said current flow by controlling the string select gate to disconnect the NAND string from the corresponding bit line.

Examples are described in which the memory array includes a plurality of NAND strings, each NAND string in the plurality of NAND strings having a source side select gate controllable to connect the NAND string to, or disconnect the NAND string from, a source side reference line. An example read setup operation disables said current flow by controlling the source side select gate to disconnect the NAND string from the source side reference line.

In other examples, the memory cells are disposed in a NOR architectures, having local bit lines with block select gates controllable to connect a column of memory cells in the block to, or disconnect the column of memory cells from, a corresponding bit line in the plurality of bit lines.

Examples are described in which the memory array includes bit line select gates controllable to connect and disconnect the sense amplifier circuits from bit lines in the memory array. An example read setup operation disables said current flow by controlling the bit line select gates to disconnect the bit lines coupled to the selected memory cells from the sense amplifier circuits.

The read setup operation needs to be executed periodically. In this way, it can achieve the purpose of maintaining a more consistent distribution of electrons near the inversion layer in the memory cell channels when the memory cells are activated for read operations separated in time. A read setup operation described herein includes applying a read setup bias that includes a gate-to-channel voltage, while blocking, or turning off, cell current between the memory cells and a sense amplifier circuit. The cell current can be blocked by disconnecting the memory cells from the sensing amplifier unit, using for example a MOSFET switch in the current path. Therefore, the power loss caused by the cell current can be greatly reduced.

In the case of memory arrays comprising NAND strings, there can be a plurality of switches usable to disconnect the memory cell current from the sense amplifier circuits. NAND strings can include upper select switches (also called string select gates SSGs), which are used to connect and disconnect the corresponding NAND strings from global bit lines. Also, NAND strings can include lower select switches (also called ground select gates GSGs), which are used to connect and disconnect the corresponding NAND strings from source bias lines such as common source lines or ground. The biasing arrangement for the read setup operation can disconnect the current flow from the memory cells to the sense amplifier circuit by turning off the upper select switches, turning off the lower select switches, or turning off both the upper and lower select switches.

Also, in some embodiments, a bit line select switch is disposed between a global bit line and the sense amplifier circuit. The biasing arrangement for the read setup operation can disconnect the current flow from the memory cells to the sense amplifier circuit by turning off the bit line select switch.

The read setup operation can comprise simultaneously applying a no-current read setup bias to a plurality of memory cells disconnected from the sense amplifier circuit, of a selected block of the plurality of blocks. Logic to traverse the blocks in the plurality of blocks is described, to apply the read setup operation to the plurality of blocks. The blocks in the plurality of blocks can include, respectively, a plurality of sub-blocks, wherein sub-blocks in the plurality of sub-blocks are arranged to be activated for connection to the set of global bit lines for memory operations in response to corresponding sub-block string select lines, and a sub-block comprises a plurality of NAND strings. The read setup operation can include traversing the sub-blocks in the selected block, to simultaneously apply the read setup bias to respective pluralities of memory cells of individual sub-blocks of the selected block, including embodiments in which more than one NAND string connected to a single global bit line receives the setup bias simultaneously. For the purposes of this description, “simultaneously” means that the biasing arrangements overlap in time, at least partially, so that all simultaneous biasing arrangements consume current to increase combined current consumption for the memory array.

Embodiments can include maintaining a block status table identifying stale blocks, and the read setup operation can be applied to stale blocks identified in the block status table. Alternatively, the blocks in the array can be traversed sequentially, or in a systematic order, as a background operation or otherwise independent of read commands addressing the blocks, to maintain readiness of the memory cells for subsequent read operations.

A method of operating a memory is described, including blocking current flow between memory cells and sense amplifier circuits during read setup operations.

The method can be deployed in a memory in which each block in the plurality of blocks of memory cells has a plurality of sub-blocks, each sub-block including a distinct subset of the set of NAND strings of the block, the distinct subset of NAND strings in each sub-block being operatively connected to a respective sub-block string select line by which gate voltages are applied to the string select gates of the NAND strings in the distinct subset of the sub-block. The read setup bias operations can be applied to more than one sub-block in a single block simultaneously.

Other aspects and advantages of the present invention can be seen on review of the drawings, the detailed description and the claims, which follow.

