CROSS-REFERENCE TO RELATED APPLICATIONS

This application is the U.S. National Phase of International Application No. PCT/JP2018/039111, filed Oct. 19, 2018. That application claims priority to JP2017-202437, filed Oct. 19, 2017. Both of those application are incorporated by reference in their entireties.

TECHNICAL FIELD

The present invention relates to a memristor having an oxide, and a neural network using the same.

BACKGROUND ART

A memristor is a device that exhibits change in resistance value when current flows therethrough under predetermined conditions, and that is capable of maintaining that state. There is known a structure of a memristor where a memristor layer is disposed between a first electrode and a second electrode. For example, Japanese Translation of PCT Application No. 2015-502031 and Japanese Translation of PCT Application No. 2016-510501 disclose a Ti oxide as a typical memristor layer. The Ti oxide is single crystalline or polycrystalline. Japanese Translation of PCT Application No. 2015-502031 discloses, besides this, oxides having elements of Zr, Hf, V, Nb, Ta, Mo, W, Cr, Fe, Ni, Co, Sc, Y, or Lu, as a memristor layer. Japanese Translation of PCT Application No. 2016-510501 discloses, besides this, a Ta oxide or Nb oxide as a memristor layer. Such memristors can be used as memory devices in variable resistance memory (ReRAM) through integration, and also can be used as synapse devices that connect neuron circuits to each other in a neural network that mimics the structure of a brain (see Japanese Translation of PCT Application No. 2015-502031 and Japanese Translation of PCT Application No. 2016-510501).

BRIEF SUMMARY

A memristor that uses a Ti oxide memristor layer requires a high-temperature (e.g., temperatures of 200° C. to 300° C. or higher) process in manufacturing. Also, although much is unclear regarding the structures and manufacturing processes of memristors disclosed in Patent Document 1 and Patent Document 2 that use memristor layers of oxides having elements other than Ti, a process of 300° C. is used in an example described in Patent Document 1, and it is conceivable that a temperature around the same level as that of Ti oxides is required, as in this example.

Additionally, in a neural network, the number of synapse devices where memristors are applied is extremely great, and highly integrating these using a substrate that has a size as large as possible is preferable.

However, in a case of highly integrating using a substrate that is large in size, manufacturing by a process as low in temperature as possible instead of a high-temperature process is preferable from the perspective of manufacturing facilities, and it is preferable not to include metals of which resources might be depleted, to keep from becoming extremely expensive.

The present invention has been made in light of such situations, and it is an object thereof to provide a memristor that can be manufactured at lower temperatures and does not include metals of which resources might be depleted, and also to provide a neural network where high integration of synapse devices can be realized by using the same.

In order to achieve the above object, a memristor according to an embodiment of the present invention includes a first electrode, a second electrode, and a memristor layer of an oxide having elements of Ga, Sn, and oxygen, disposed between the first electrode and the second electrode. When voltage is applied to the first electrode with respect to the second electrode, the voltage being positive or negative, a current flows; when voltage of a data-set voltage value is applied, a state is transitioned from a high-resistance state to a low-resistance state; and when voltage of a data-reset voltage value that is of an opposite sign to that of the data-set voltage value is applied, the state is transitioned from a low-resistance state to a high-resistance state.

The oxide preferably is an amorphous oxide.

The first electrode and/or the second electrode preferably is/are formed by deposition of aluminum.

A neural network according to an embodiment of the present invention includes a plurality of neuron circuits and a plurality of synapse devices, the synapse devices including the memristor.

Alternatively, a neural network according to an embodiment of the present invention includes a plurality of neuron circuits and a plurality of synapse devices, the neuron circuits including the memristor.

Preferably, the plurality of synapse devices are arrayed in a matrix form, with a plurality of the synapse devices thereof laid out in a first direction having one of the first electrodes and the second electrodes thereof connected in common, and a plurality of the synapse devices laid out in a second direction having the other of the first electrodes and the second electrodes thereof connected in common, and each of the plurality of neuron circuits is connected to one of the first electrodes and the second electrodes connected in common, and is connected to the other of the first electrodes and the second electrodes connected in common.

Preferably, the neuron circuits have a thin-film transistor. The thin-film transistor includes a drain electrode, a source electrode, a gate electrode, and a channel layer. When voltage is applied across the drain electrode and the source electrode and across the gate electrode and the source electrode, a current corresponding to these voltages flows in the channel layer between the drain electrode and the source electrode. The channel layer uses the same layer as the memristor layer.

The memristor according to the present invention can be manufactured at lower temperatures and can be made not to include metals of which resources might be depleted. Also, in the neural network according to the present invention, high integration of synapse devices and so forth can be realized by using the memristor.

