CROSS-REFERENCE TO RELATED APPLICATION

This U.S. nonprovisional patent application claims the benefit of priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0116067, filed on Sep. 10, 2020 in the Korean Intellectual Property Office, the contents of which are herein incorporated by reference in their entirety.

BACKGROUND

1. Technical Field

The inventive concept(s) described herein relate to a memory controller, a memory device, and a storage device.

2. Description of the Related Art

By configuring a storage device so that a plurality of NAND dies operate in parallel, consistency of write performance may be enhanced. For example, a plurality of blocks included in NAND dies different from each other may be grouped and controlled by super block management.

In order to program a specific block of a NAND die, an erase of the specific block needs to precede programming. While the NAND die performs the erase operation, the programming required for the NAND die may not be performed. If all the plurality of NAND dies controlled in this manner by the super block management have blocks being erased, none of the plurality of NAND dies may execute programming requested by a host. That is, a throughput (a host write throughput) may be 0 in a section in which all the plurality of NAND dies have blocks being erased.

SUMMARY

According to aspects of the present disclosure, a memory controller and a memory device are capable of improving erasing of a plurality of NAND dies controlled by a super block management and thereby enhancing the consistency of write performance. According to another aspect of the present disclosure, a storage device that includes the memory controller and the memory device is capable of improving erasing of the plurality of NAND dies controlled by the super block management and thereby enhancing the consistency of write performance.

However, aspects of the inventive concept(s) described herein are not restricted to those set forth herein. Other aspects of the inventive concept(s) described herein will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure as provided below.

According to an aspect of the present disclosure, a memory controller includes an interface and a control module. The interface is provided for communicating with a memory device which includes a first die and a second die. The first die includes a first block and a second block, and the second die includes a third block and a fourth block. The control module manages the memory device in units of a first super block and a second super block. The first super block includes the first block and the third block, and the second super block including the second block and the fourth block. The control module causes a program of the first super block and an erase of the second super block to complete before starting the program of the second super block. The erase of the second super block is performed in multiple steps. Completion of the program of the first super block and the erase of the second super block includes performing a first step erase of the second block after programming a first portion of the first block, programming a second portion of the first block after the first step erase of the second block, and performing a second step erase of the second block after programming the second portion of the first block.

According to another aspect of the present disclosure, a memory controller includes an interface and a control module. The interface interfaces with a memory device including a plurality of dies that each include a plurality of blocks. The control module groups the plurality of blocks included in different dies and manages the plurality of blocks as super blocks. The control module performs scheduling to alternately perform a program of a part of an Nth super block, wherein N is a natural number, and a phased erase of an N+1st super block. The control module causes the program on the Nth super block and the erase on the N+1st super block to complete before the program on the N+1st super block starts.

According to another aspect of the present disclosure, a memory device includes a first die and a second die. The first die includes a first block and a second block. The second die includes a third block and a fourth block. The memory device is controlled in units of a first super block and a second super block, the first super block includes the first block and the third block, and the second super block includes the second block and the fourth block. Before starting a program of the second super block, a program of the first super block and an erase of the second super block are completed, and the erase of the second super block is divided into multiple steps. Completion of the program of the first super block and the erase of the second super block includes performing a first step erase of the second block after programming a first portion of the first block, programming a second portion of the first block after the first step erase of the second block, and performing a second step erase of the second block after programming the second portion of the first block.

According to an aspect of the present disclosure, a storage device includes a memory device and a controller. The memory device includes a first die and a second die. The first die includes a first block and a second block, and the second die includes a third block and a fourth block. The controller manages the memory device by a first super block or a second super block. The first super block includes the first block and the third block, and the second super block includes the second block and the fourth block. The controller completes a program on the first super block and an erase on the second super block before starting the program of the second super block, and divides performance of the erase on the second super block into multiple steps. The program of the first super block and the erase of the second super block include performing a first step erase of a second block after programming a first portion of the first block, programming a second portion of the first block after the first step erase of the second block, and performing a second step erase of the second block after programming a second portion of the first block.

According to an aspect of the present disclosure, a memory controller includes an interface and a control module. The interface is provided for communicating with a memory device which includes a first die and a second die. The first die includes a first block and a second block, and the second die includes a third block and a fourth block. The control module manages the memory device in units of a first super block and a second super block. The first super block includes the first block and the third block, and the second super block includes the second block and the fourth block. The control module causes a program of the first super block and an erase of the second super block to complete, before starting the program of the second super block, and the control module controls so that an erase section of the second block of the first die and an erase section of the fourth block of the second die only partially overlap to erase the second super block.

According to another aspect of the present disclosure, a memory controller includes an interface and a control module. The interface is provided for communicating with a memory device which includes a first die and a second die. The first die includes a first block and a second block, and the second die includes a third block and a fourth block. The control module manages the memory device in units of a first super block and a second super block. The first super block includes the first block and the third block, and the second super block includes the second block and the fourth block. The control module completes an erase of the second super block before starting a program of the second super block. The erase of the second super block includes starting the erase of the second block of the first die, reducing a total token from an initial number by a predetermined consumed token, when the erase of the second block of the first die starts, increasing the number of total tokens with an erase progress time, and starting the erase of the fourth block of the second die, when the number of total tokens reaches the number of threshold tokens.

According to an aspect of the present disclosure, a memory device includes a first die and a second die. The first die includes a first block and a second block. The second die includes a third block and a fourth block. The memory device is controlled in units of a first super block and a second super block. The first super block includes the first block and the third block, and the second super block includes the second block and the fourth block. Before starting a program of the second super block, a program of the first super block and an erase of the second super block are completed, and the second super block is erased by controlling so that an erase section of the second block of the first die and an erase section of the fourth block of the second die only partially overlap.

According to an aspect of the present disclosure, a storage device includes a memory device and a controller. The memory device includes a first die and a second die. The first die includes a first block and a second block, and the second die includes a third block and a fourth block. The controller manages the memory device by a first super block or a second super block. The first super block includes the first block and the third block, and the second super block includes the second block and the fourth block. The controller completes a program on the first super block and an erase on the second super block, before starting the program of the second super block, and the controller controls so that an erase section of the second block of the first die and an erase section of the fourth block of the second die only partially overlap to erase the second super block.

Specific matters of other embodiments are included in the detailed description and drawings.

