CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a U.S. National Phase of International Patent Application No. PCT/JP2019/010003, filed on Mar. 12, 2019, which claims the benefit and priority of Japanese Patent Application No. 2018-070349 filed on Mar. 30, 2018. The contents of the above applications are incorporated herein by reference in their entirety.

TECHNICAL FIELD

The present invention relates to an integrated circuit device including a resistance variable memory element.

BACKGROUND ART

A resistance variable memory storing data in accordance with a high or low in the resistance of an element has been known. Examples of the resistance variable memory include a resistive random access memory (ReRAM) including a resistance variable memory element of which electrical resistance is changed in accordance with a change in electric-field induced colossal resistance, a phase change memory, and a magnetic random access memory (MRAM) including a magnetic tunnel junction element in which a tunnel magnetoresistance effect is used as a resistance variable memory element.

An integrated circuit device including the resistance variable memory element such as the MRAM described above is combined with a circuit element of a semiconductor such as a MOSFET by a CMOS process, in order to perform the write and read of data with respect to the element. In such an integrated circuit device, the resistance variable memory element is formed on a metal wiring layer of a semiconductor substrate on which the circuit element of the semiconductor is formed (for example, refer to International Publication WO 2016/159017).

CITATION LIST

Patent Literature

Patent Literature 1: WO 2016/159017

SUMMARY OF INVENTION

Technical Problem

In the integrated circuit device in which a battery is used as a power supply, in particular, in a mobile product, a ubiquitous product, or the like, a reduction in the current consumption is a highest-priority issue. In addition, an operation speed of the integrated circuit device is required to be as high as that of a high-end product, in accordance with multi-functionalization for the same application. The resistance variable memory element is a nonvolatile memory, and thus, has attracted attention as a memory element having low power consumption and a high operation speed, compared to a DRAM or the like that is required to be refreshed, and has been researched/developed in various places.

However, individual studies have been conducted with respect to the resistance variable memory element, and the operation speed or the size reduction thereof so far, but no study has been conducted with respect to an operation efficiency of the whole integrated circuit device. The problem of power consumption or the problem of a data processing speed is in a stage of being studied in detail. In addition, it is desirable to dispose the resistance variable memory element in a multi-layer state by focusing on high integration, and to increase the operation efficiency in the integrated circuit device in which the resistance variable memory element is in a multi-layer state. Note that, the operation efficiency is used as a broad index including not only an individual performance index for evaluating the power consumption, the operation speed, or the like of the element itself, but also the power consumption or the operation speed of the whole integrated circuit device, signal quality, consistency with a peripheral circuit, and the like.

An object of the invention is to provide an integrated circuit device in which a resistance variable memory element is disposed in a multi-layer state, in consideration of an operation efficiency.

Solution to Problem

A write operation speed of the resistance variable memory element is not determined only by the operation speed of an element single body, but it is necessary to consider the influence of a wiring delay. The present inventors have found that the wiring delay is inseparably connected with a wiring length, that is, the multi-layer disposition of the resistance variable memory element, and the operation efficiency is highly affected by a multi-layer disposition configuration of the resistance variable memory element. In addition, the power consumption is inseparably connected with not only low current consumption of the memory cell single body including the resistance variable memory element, but also a dynamic distribution ratio of a current amount to be supplied to each module mounted on the integrated circuit device, in the whole integrated circuit device. The present inventors have found that in the amount of current consumption, the operation efficiency is highly affected by a current distribution with respect to each layer of the resistance variable memory element that is disposed in a multi-layer state. The invention is based on such findings.

An integrated circuit device of the invention, includes: a first resistance variable memory element provided on a semiconductor substrate; a second resistance variable memory element provided on the semiconductor substrate; and a semiconductor circuit for controlling write and read of the first resistance variable memory element and the second resistance variable memory element, which is provided on the semiconductor substrate, in which the second resistance variable memory element has a write current that is smaller than a write current of the first resistance variable memory element, and the second resistance variable memory element is disposed farther from the semiconductor substrate than the first resistance variable memory element.

An integrated circuit device of the invention, includes: a first resistance variable memory element provided on a semiconductor substrate; a second resistance variable memory element provided on the semiconductor substrate; and a semiconductor circuit for controlling write and read of the first resistance variable memory element and the second resistance variable memory element, which is provided on the semiconductor substrate, in which the first resistance variable memory element has a write time that is shorter than a write time of the second resistance variable memory element, and the second resistance variable memory element is disposed farther from the semiconductor substrate than the first resistance variable memory element.

Advantageous Effects of Invention

According to the invention, it is possible to improve an operation efficiency of an integrated circuit device in which an MTJ element is disposed in a multi-layer state.

