CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of China application serial no. 202010122857.6, filed on Feb. 27, 2020. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a data processing circuit, and in particular, to a data transferring apparatus and a method for transferring data with overlap.

2. Description of Related Art

In a graphics processing unit (GPU), an artificial intelligence (AI) chip, or other data processing circuits (apparatuses), block level transfer (BLT) is a common memory operation. The BLT indicates that in a virtual address space, all data in a consecutive memory area (a source block) is transferred to another consecutive memory area (a destination block).

FIG. 1is a schematic diagram describing a source block10and a destination block20that do not overlap with each other in a virtual address space. When implementing the BLT, a data processing circuit usually splits the source block10and the destination block20into a large quantity of tiles with a fixed size. As shown inFIG. 1, the source block10is split into a large quantity of tiles (dashed line blocks), and the quantity of the tiles of the destination block20is the same as the quantity of the tiles of the source block10. Transfer of data is completed based on the tiles. If there is no address space overlap between the source block10and the destination block20, the tiles of the source block10may be transferred to the destination block20in parallel, and such data transfer in parallel does not cause any disaster of “write after read (WAR)”. When copying the data, an execution order of the tiles does not affect a final result. In other words, the execution order of the tiles may be out-of-order.

FIG. 2is a schematic diagram describing the source block10and the destination block20that overlap with each other in the virtual address space. When executing a BLT task on the source block10shown inFIG. 2, if performing data transfer on the tiles of the source block10in parallel, the disaster of data WAR may occur.

For a situation in which the source block10and the destination block20overlap with each other shown inFIG. 2, even if only one tile (that is, a dashed line block shown inFIG. 2) is transferred each time, to prevent original data of the source block10from being damaged before the original data is read, the data transfer also needs to be performed based on an order of the tiles. By usingFIG. 2as an example, if “transferring from a tile at an address A1 in the source block10to a tile at an address C2 in the destination block20” is first performed, the original data of the tile C2 of the source block10is lost. Subsequently, when “transferring from a tile at an address C2 in the source block10to a tile at an address E3 in the destination block20” is performed, data of the tile C2 has actually become data of A1. Consequently, a final result is wrong. However, if “transferring from a tile at an address C2 in the source block10to a tile at an address E3 in the destination block20” is first performed, and then “transferring from a tile at the address A1 in the source block10to a tile at the address C2 in the destination block20” is performed, correctness of the data can be ensured. Therefore, for the example inFIG. 2, a correct order for transferring data is from bottom to top and row by row. A transferring order of tiles in a row does not affect a final result.

However, the data processing circuit (apparatus) usually includes a plurality of hardware processing units (hereinafter referred to as a tile processing unit), to process data transfer of the tiles. If only one tile processing unit is opened (tile transfer is performed in a correct order), mistakes may not occur. However, in this case, other tile processing units are in an idle state, and valuable hardware resources are wasted.

When BLT is performed, in a case that the source block10and the destination block20overlap with each other, a well-known data processing circuit (apparatus) does not process the tiles in parallel. The well-known data processing circuit (apparatus) enables a tile processing unit to complete data transfer of all the tiles tile by tile. Anyway, BLT execution efficiency of the well-known data processing circuit (apparatus) is excessively low because some hardware resources are in an idle state. In addition, the data transfer manner cannot fully use a high bandwidth of a video memory.

It should be noted that contents in paragraphs of Description of Related Art are used to help to understand the invention. Some contents (or all contents) disclosed in the paragraphs of Description of Related Art do not need to be a technology well known by a person of ordinary skill in the art. The contents disclosed in the paragraphs of Description of Related Art do not mean that the contents have been acknowledged by a person of ordinary skill in the art before the invention is filed.

SUMMARY OF THE INVENTION

The invention provides a data transferring apparatus and a method for transferring data with overlap, to perform data transfer on a plurality of tiles in parallel by using a plurality of tile processing circuits.

The data transferring apparatus in the invention is configured to transfer data with overlap. The data transferring apparatus includes a command splitter circuit and a plurality of tile processing circuits. The command splitter circuit is configured to receive a BLT command. The command splitter circuit may split the BLT command into a plurality of tile transfer tasks, and split the tile transfer tasks into a plurality of batches. The command splitter circuit may issue the tile transfer tasks in a current batch of the batches to the tile processing circuits. The tile processing circuits may execute the tile transfer tasks in the current batch, to read data of a plurality of first corresponding tiles among a plurality of source tiles of a source block to the tile processing circuits (as a plurality of pieces of cache tile data). Only after all the tile transfer tasks in the current batch have been executed by the tile processing circuits, the command splitter circuit issues the tile transfer tasks in a next batch of the batches to the tile processing circuits.

The method for transferring data with overlap in the invention includes: receiving, by a command splitter circuit, a BLT command; splitting, by the command splitter circuit, the BLT command into a plurality of tile transfer tasks, and splitting the tile transfer tasks into a plurality of batches; issuing the tile transfer tasks in a current batch of the batches; executing, by a plurality of tile processing circuits, the tile transfer tasks in the current batch, to read data of a plurality of first corresponding tiles among a plurality of source tiles of a source block to the tile processing circuits (as a plurality of pieces of cache tile data); and only after all the tile transfer tasks in the current batch have been executed by the tile processing circuits, issuing, by the command splitter circuit, the tile transfer tasks in a next batch of the batches to the tile processing circuits.

Based on the above, the command splitter circuit in the embodiments of the invention may split the BLT command into a plurality of tile transfer tasks, and split the tile transfer tasks into a plurality of batches. After the command splitter circuit issues the tile transfer tasks in a batch (the current batch) to the plurality of tile processing circuits, the command splitter circuit pauses issuing the tile transfer tasks. Only after all the data of corresponding tiles of the tile transfer tasks in the current batch has been read to the tile processing circuits, the command splitter circuit issues the tile transfer tasks in another batch (a next batch) to the tile processing circuits. Therefore, the command splitter circuit may perform data transfer on a plurality of tiles in parallel by using the plurality of tile processing circuits.

To make the features and advantages of the invention more comprehensible, detailed descriptions are provided below with reference to the accompanying drawings by using the embodiments.

