This application claims priority from Japanese Patent Application No. 2019-089274 filed on May 9, 2019. The content of this application is incorporated herein by reference in its entirety.

BACKGROUND OF THE DISCLOSURE

1. Field of the Disclosure

The present disclosure relates to a power amplifier circuit and a bias control circuit.

2. Description of the Related Art

In a power amplifier circuit, two or more power amplifiers may be connected in stages. The power amplifier in the final stage has a transistor, the size of which is larger than the size of a transistor in the power amplifiers in the previous stages, and therefore generates more heat. Therefore, when the power of a high-frequency output signal increases, the power amplifier in the final stage generates more heat, decreases a gain, and approaches a saturation state. As a result, the gain of the entire power amplifier circuit decreases.

U.S. Patent Application Publication No. 2017/0141734 describes a power amplifier circuit which increases a current flowing through a bias circuit in a preceding stage in response to a current flowing in a bias circuit in a subsequent stage. In the power amplifier circuit described in U.S. Patent Application Publication No. 2017/0141734, the current flowing through the bias circuit in the preceding stage increases in response to the increase in the current flowing through the bias circuit in the subsequent stage. As a result, the gain of the power amplifier in the preceding stage increases. The increase in the gain of the power amplifier in the preceding stage can compensate for a decrease in the gain of the power amplifier in the subsequent stage. Therefore, a decrease in the gain of the entire power amplifier circuit can be reduced.

In the power amplifier circuit described in U.S. Patent Application Publication No. 2017/0141734, a transistor246for detecting a current of a bias circuit230is disposed between the bias circuit230in a subsequent stage and a power supply potential Vbatt. Accordingly, the power supply potential Vbatt needs to be high in consideration of a potential drop in the transistor246. That is, it is difficult for the power amplifier circuit described in U.S. Patent Application Publication No. 2017/0141734 to operate at a low power supply potential.

In recent years, envelope tracking control that is the control of varying a collector bias (collector potential) of a power amplifier in response to an envelope of a high-frequency signal may be performed to reduce power consumption. As described above, in the power amplifier circuit described in U.S. Patent Application Publication No. 2017/0141734, the power supply potential Vbatt is inputted to the transistor246for detecting the current of the bias circuit230. Therefore, it is difficult for the power amplifier circuit described in U.S. Patent Application Publication No. 2017/0141734 to vary the current flowing through the transistor246in accordance with a variation in the collector potential of the power amplifier.

BRIEF SUMMARY OF THE DISCLOSURE

The present disclosure has been made in view of the above circumstances, and an object of the present disclosure is to enable the operation at a low power supply potential.

A power amplifier circuit according to an aspect of the present disclosure includes: a plurality of power amplifiers connected in a plurality of stages to amplify a high-frequency input signal and to output an amplified high-frequency output signal; a plurality of bias circuits each of which outputs a bias current to a corresponding one of the plurality of power amplifiers; and a bias control circuit configured to output a bias control current based on a second reference potential that varies in response to power of the high-frequency output signal and that is a potential of a portion in one bias circuit of the plurality of bias circuits, the bias control current being output to one or more bias circuits in a stage preceding the one bias circuit for increasing a bias current output from the one or more bias circuits in the stage preceding the one bias circuit.

A bias control circuit according to an aspect of the present disclosure is a bias control circuit configured to control a bias current of a power amplifier circuit including a plurality of power amplifiers connected in a plurality of stages to amplify a high-frequency input signal and to output an amplified high-frequency output signal and a plurality of bias circuits each of which outputs a bias current to a corresponding one of the plurality of power amplifiers. The bias control circuit is configured to output a bias control current based on a second reference potential that varies in response to power of the high-frequency output signal and that is a potential of a portion in one bias circuit of the plurality of bias circuits, the bias control current being output to one or more bias circuits in a stage preceding the one bias circuit for increasing a bias current output from the one or more bias circuits in the stage preceding the one bias circuit.

Other features, elements, characteristics and advantages of the present disclosure will become more apparent from the following detailed description of preferred embodiments of the present disclosure with reference to the attached drawings.

