BACKGROUND

The present invention generally relates to semiconductor integrated circuits and methods of fabrication thereof, and more specifically, to interconnect structures and methods to form back end of line metallization interconnect structures.

Integrated circuit processing can be generally divided into front end of the line (FEOL), middle of the line (MOL) and back end of the line (BEOL) processes. The FEOL and MOL processing will generally form many layers of logical and functional devices. By way of example, the typical FEOL processes include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MOL is mainly gate, and source/drain contacts formation. Layers of interconnections are formed above these logical and functional layers during the BEOL processing to complete the integrated circuit structure. As such, BEOL processing generally involves the formation of insulators and conductive wiring.

SUMMARY

Embodiments of the present invention are generally directed to integrated circuits including interconnect structures formed with alternative metals and methods for fabricating the same. A non-limiting example of an interconnect structure according to aspects of the invention includes a top via including a first alternative conductive metal other than copper or tungsten and a metal line including a second alternative conductive metal. A conductive etch stop layer is intermediate the top via and the metal line. The top via is fully aligned to the metal line.

A non-limiting example method for forming an interconnect structure according to aspects of the invention includes forming a metal stack on a substrate, wherein the metal stack includes an alternative metal other than copper or tungsten. A line pattern is formed from a mandrel on the metal stack. Spacers are formed on sidewalls of the mandrel line pattern, wherein gaps remain between adjacent sidewall spacers. The gaps between the adjacent sidewall spacers are filled with a non-mandrel material to form a non-mandrel line pattern. Via openings are formed in the mandrel line pattern and the non-mandrel line pattern and filled with a fill material. The sidewall spacers are selectively removed to expose portions of the metal stack between the mandrel and non-mandrel line patterns. The exposed portions of the metal stack are selectively etched to a depth corresponding to a desired via height. The mandrel and the non-mandrel line patterns are selectively removed. The metal stack is etched to the substrate to form the interconnect structure including a plurality of metal lines with fully aligned top vias under the fill material. The fill material is then removed.

A non-limiting example subtractive etching method to form a fully aligned top via and metal line interconnect structure according to aspects of the invention includes providing a metal stack on a substrate, the metal stack including a conductive liner layer, a first alternative metal on the conductive liner layer, a conductive etch stop layer on the first alternative metal layer, and a second alternative metal layer on the conductive etch stop layer, wherein the second alternative metal layer has a height equal to a desired top via height and first alternative metal layer has a height equal to a desired metal line height. A mandrel layer is deposited and patterned on the metal stack to form a plurality of mandrel lines. A sidewall spacer is deposited onto the mandrel lines, wherein gaps remain between adjacent sidewall spacers. The gaps are filled with a non-mandrel material to form non-mandrel lines. The mandrel and non-mandrel lines are patterned to form via openings to the second alternative metal layer in the metal stack. The via openings are filled with a fill material having an etch selectivity relative to the mandrel, non-mandrel, metal stack, and sidewall spacers. The sidewall spacers are selectively removed to expose portions of the second alternative metal layer of the metal stack. The exposed portions of the second alternative metal layer are etched to the conductive etch stop layer. The mandrel lines, the non-mandrel lines, and exposed portions of the etch stop layer are selectively removed. Exposed portions of the first alternative metal layer and the liner layer are etched to the substrate; and the fill material is removed to form the fully aligned top via and metal line interconnect structure.

Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.

