CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2019-0019706, filed on Feb. 20, 2019, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a semiconductor system, and more particularly, to a semiconductor system capable of scrambling addresses.

2. Related Art

Generally, a semiconductor memory device may include a plurality of memory cells divided into a plurality of groups. Memory cells may be controlled by the group. A memory cell group may be referred to as a memory cell array or a MAT. A control block may be arranged at a boundary between memory cell arrays. The memory cell arrays may be controlled separately by the control block.

A difference between signal transmission characteristics may be generated between a memory cell adjacent to the control block (hereinafter, referred to as an adjacent cell) and a memory cell remote from the control block (hereinafter, referred to as a far cell). Particularly, in a cross point array using a phase changeable material as a switching element and a storage medium, an error may be frequently generated in the adjacent cell.

Meanwhile, an error-bit test of a semiconductor integrated circuit device may be performed on a semiconductor chip unit, a bank unit, or a MAT unit. The error-bit test may be simultaneously performed on the semiconductor chips, the banks, and the MATs. When the adjacent cell is tested, an error ratio in the adjacent cell may be remarkably increased as compared to other regions. Although the errors in the adjacent cell region may not to a worrisome level in view of the bank and the MAT, the instantaneous increase of the error ratio may cause low yield of the semiconductor chip, the bank, and the MAT.

SUMMARY

In accordance with an embodiment of the present disclosure, a semiconductor system includes a module controller and a plurality of semiconductor chips configured to receive logical addresses from the module controller. The semiconductor system also includes a plurality of scramble circuits, with a scramble circuit provided for each of the plurality of semiconductor chips, configured to receive the logical addresses and to output corresponding physical addresses for the plurality of semiconductor chips. Each scramble circuit of the plurality of scramble circuits is configured to receive the same logical address and to output a corresponding physical address different from the physical addresses output by the other scramble circuits of the plurality of scramble circuits.

In accordance with another embodiment of the present disclosure, a semiconductor system includes a module substrate and a plurality of semiconductor chips mounted on the module substrate. The semiconductor system also includes a module controller configured to provide each of the semiconductor chips with logical addresses and address bit test commands. The semiconductor system further includes scramble circuits, with a scramble circuit provided for each of the semiconductor chips, the scramble circuits configured to convert the logical addresses into physical addresses based on the address bit test commands. The scramble circuits are configured to generate a different physical addresses for each semiconductor chip given the same logical address.

