CROSS REFERENCE TO RELATED APPLICATIONS

This disclosure claims the priority of Chinese Patent application with No. 202010740611.5, filed on Jul. 28, 2020 and entitled “Array Substrate Drive Circuit, Display Module and Display Device”, which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

This disclosure relates to the technical field of electronic circuits, and in particular to an array substrate drive circuit, a display module and a display device.

BACKGROUND

The Gate Driver on Array (GOA) technology, as a representative of the new technology, is to integrate a gate switch circuit on a display substrate to remove a gate drive integrated circuit part.

Liquid Crystal Display (LCD) based on GOA technology has the advantages of simple manufacturing process and low cost, and has gradually become a mainstream display device. In the production process, the LCD needs to be equipped with a test circuit for Array Test (ATT). Due to the process of the GOA circuit in the production process and other reasons, short circuits between adjacent metal conductive layers are prone to occur. The ATT in the related technology cannot detect this type of short-circuit, resulting in a loss of product capacity and a low pass rate.

SUMMARY

The main object of this disclosure is to provide an array substrate drive circuit, a display module and a display device, aiming to reduce the defect rate of the display panel.

In order to achieve the above object, this disclosure provides an array substrate drive circuit, which includes:

a signal driver configured for receiving a test signal, and generating a drive signal for driving a pixel array according to the test signal; and

a signal isolator configured for dividing the drive signal into an even-numbered row drive signal and an odd-numbered row drive signal for driving the pixel array according to a preset control signal to drive the pixel array in rows.

In an embodiment, the signal isolator includes even-numbered row isolation circuits and odd-numbered row isolation circuits;

controlled terminals of the even-numbered row isolation circuits are connected to even-numbered row output terminals of the signal driver in a one-to-one correspondence, output terminals of the even-numbered row isolation circuits are connected to even-numbered rows of the pixel array in a one-to-one correspondence, and input terminals of the even-numbered row isolation circuits are connected to each other; and

controlled terminals of the odd-numbered row isolation circuits are connected to odd-numbered row output terminals of the signal driver in a one-to-one correspondence, output terminals of the odd-numbered row isolation circuits are connected to odd-numbered rows of the pixel array in a one-to-one correspondence, and input terminals of the odd-numbered row isolation circuits are connected to each other.

In an embodiment, the preset control signal includes a first control signal and a second control signal;

each odd-numbered row isolation circuit includes a first transistor; a gate of the first transistor is connected to a drain of the first transistor, the gate of the first transistor is connected to a corresponding odd-numbered row output terminal of the signal driver, and a source of the first transistor is connected to a corresponding odd-numbered row of the pixel array; the gate of the first transistor is further configured for receiving the first control signal.

In an embodiment, each even-numbered row isolation circuit includes a second transistor; a gate of the second transistor is connected to a drain of the second transistor, the gate of the second transistor is connected to a corresponding even-numbered row output terminal of the signal driver, and a source of the second transistor is connected to a corresponding even-numbered row of the pixel array; the gate of the second transistor is further configured for receiving the second control signal.

In an embodiment, the first transistor and the second transistor are both thin film transistors.

In an embodiment, the signal driver includes drive circuits, output terminals of odd-numbered row drive circuits are connected to the controlled terminals of the odd-numbered row isolation circuits in a one-to-one correspondence, and output terminals of even-numbered row drive circuits are connected to the controlled terminals of the even-numbered row isolation circuits in a one-to-one correspondence.

In an embodiment, the drive circuit is a gate driven on array drive circuit, and the drive circuit includes voltage phase-related CK signal, LC signal and frame start signal Vst, where the CK signal includes CK1, CK2, CK3and CK4, and the LC signal includes LC1and LC2.

In an embodiment, the gate driven on array drive circuit comprises 4 thin film transistors and 1 capacitor C.

In an embodiment, the signal isolator is configured for receiving a first control signal and a second control signal;

in response to receiving the first control signal by the signal isolator, outputting an odd-numbered row drive signal satisfying a first preset duty ratio; and

in response to receiving the second control signal by the signal isolator, outputting an even-numbered row drive signal satisfying a second preset duty ratio.

In an embodiment, the array substrate drive circuit further includes a control chip;

where the control chip is configured for generating the first control signal or the second control signal in turn according to a preset cycle, and outputting the generated first control signal or the generated second control signal to the signal isolator.

In order to achieve the above object, this disclosure further provides a display module, which includes:

a control chip, including a test signal output terminal, a first control signal output terminal and a second control signal output terminal;

a display panel, including a display area and a non-display area, where the display area includes a pixel array; and

the array substrate drive circuit according to any one of the above mentioned embodiments, where the array substrate drive circuit is provided in the non-display area of the display panel.

In order to achieve the above object, this disclosure further provides a display device including the display module as described above.

According to the technical solution of this disclosure, a signal driver and a signal isolator are provided to form an array substrate drive circuit. The signal driver generates a drive signal for driving a pixel array according to a test signal, and the signal isolator divides the drive signal into an even-numbered row drive signal and an odd-numbered row drive signal for driving the pixel array according to a preset control signal. The even-numbered row drive signal and the odd-numbered row drive signal respectively drive the pixel array in rows. Since adjacent metal conductive layers will not output drive signals at the same time, even if the adjacent metal conductive layers are short-circuited, it can be detected during the test, thus improving the yield of the display panel.

