BACKGROUND

The present disclosure relates to a semiconductor device.

A semiconductor device, which is installed in autonomous driving vehicles, is required to be highly reliable. On the other hand, a semiconductor device may perform unintentional operations due to cosmic rays or physical deterioration. This means that a failure may occur in the semiconductor device. Since it is not possible to prevent all failures that occur in the semiconductor device, it is required to detect that a failure has occurred.

One technique for detecting a failure that occurs in a semiconductor device is a technique called lock-step. In this technique, two circuit blocks which can realize the same function are used, and each circuit block is operated at a specific timing. After the processing of the two circuit blocks is completed, the processing results of the two circuit blocks are compared.

There are disclosed techniques listed below.

[Patent Document 1] Japanese Unexamined Patent Application Publication No. 2020-4108

Patent Document 1 discloses a semiconductor device for performing a SoftWare Lock-Step (SWLS). The semiconductor device disclosed in Patent Document 1 includes a CPU 10, a CPU 20, a CPU 230, and a memory 260. During the SWLS operation, each of the CPU 10 and the CPU 20 reads program and data for the SWLS stored in the memory 260. Each of the CPU 10 and the CPU 20 executes the program for the SWLS to write the execution results in the memory 260. The CPU 230 reads the execution result of the CPU 10 and the execution result of the CPU 20 from the memory 260, and compares them.

SUMMARY

The semiconductor device for performing the SWLS disclosed in Patent Document 1 can cause the CPU 10 and the CPU 20 to perform different processing, respectively. Therefore, when the SWLS operation and the non-SWLS operation are mixed, the semiconductor device performing the SWLS has an advantage that the hardware resources (CPU 10 and CPU 20) can be effectively utilized.

However, during the SWLS operation, each of the CPU 10 and the CPU 20 reads the program and the data for the SWLS from the memory 260, and writes the execution result in the memory 260. Further, the CPU 230 reads the execution result of the CPU 10 and the execution result of the CPU 20 from the memory 260. That is, there is a problem that the bus bandwidth required for accessing the memory 260 increases during the SWLS operation.

Other objects and new features will be apparent from the description of this specification and the accompanying drawings.

A semiconductor device according to one embodiment performs a SoftWare Lock-Step (SWLS). The semiconductor device includes a first circuit group including a first Intellectual Property (IP) to be operated in a first address space, a first bus, and a first memory coupled to the first IP via the first bus, a second circuit group including a second IP to be operated in a second address space, a second bus, and a second memory coupled to the second IP via the second bus, a third bus connectable to a third memory, and a transfer control circuit coupled to the first to third buses, and including a comparator. When the SWLS is performed, the transfer control circuit transfers a program for the SWLS from the third memory to the first and second memories. The first IP executes the program for the SWLS stored in the first memory to store a first execution result in the first memory. The second IP executes the program for the SWLS stored in the second memory to store a second execution result in the second memory. The transfer control circuit reads the first and second execution results from the first and second memories, and compares the first execution result with the second execution result using the comparator. The second circuit group converts an access address from the second IP to the second memory such that an address assigned to the second memory in the second address space is a same as an address assigned to the first memory in the first address space.

According to one embodiment, it is possible to reduce the bus bandwidth required for accessing the memory during the SWLS operation.

