CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application No. 10-2020-0089201, filed on Jul. 17, 2020, the contents of which are hereby incorporated by reference in its entirety.

BACKGROUND

1. Field of Disclosure

The present disclosure relates to a dual-domain sub-sampling phase-locked loop.

2. Description of the Related Art

A phase-locked loop (PLL) is a circuit that generates a reference clock required for a wired transmission and reception and a digital circuit. The phase-locked loop PLL samples an external input reference clock having extremely low jitter and low speed to a phase of high speed clock of an oscillator, and thus, a clean and high speed clock of which speed is n-times greater than that of the reference clock is generated in an IC chip.

In particular, different from a conventional phase-locked loop, a sub-sampling phase-locked loop (SSPLL) does not use a frequency divider, and thus, a noise of a charge pump is not amplified by n-times. That is, the sub-sampling phase-locked loop SSPLL has an advantage in terms of noise.

In recent years, as the analog characteristics are degraded and become sensitive to the process-voltage-temperature (PVT) variation according to the scaling of the semiconductor process, a digital-based sub-sampling phase-locked loop has been spotlighted. As the digital-based sub-sampling phase-locked loop, there are a digital SSPLL using a bang-bang phase detector (PD) and a sub-sampling phase-locked loop SSPLL using an n-bit analog-to-digital converter (ADC).

However, since the jitter of the clock is large in the digital SSPLL using the bang-bang PD due to a high quantization noise, the digital SSPLL is not appropriate to provide the high speed clock. In addition, the SSPLL using the n-bit analog-to-digital converter has the disadvantage that requires a high performance analog-to-digital converter consuming a large amount of power.

Thus, a dual-domain sub-sampling phase locked-loop that enables the high quantization noise to be reduced and the power consumption to be decreased is provided.

SUMMARY

The present disclosure provides a dual-domain sub-sampling phase-locked loop capable of reducing a jitter in high-speed clock output through a phase-locked loop and reducing the number of circuits of the phase-locked loop.

Embodiments of the inventive concept provide a sub-sampling phase-locked loop including a first phase output unit sub-sampling an output clock of a digitally-controlled oscillator and outputting a sign bit corresponding to a voltage-domain phase and a second phase output unit outputting a gain bit corresponding to a time-domain phase based on a pulse width set according to the output clock and a threshold time set according to a reference clock.

Embodiments of the inventive concept provide a method of operating a sub-sampling phase-locked loop. The method includes allowing a first phase output unit to sub-sample an output clock of a digitally-controlled oscillator and to output a sign bit corresponding to a voltage-domain phase, allowing a second phase output unit to output a gain bit corresponding to a time-domain phase based on a threshold time set according to the reference clock and a pulse width set according to the output clock, and allowing a digital loop filter to calculate a digital loop filter value for controlling a phase of the output clock based on the sign bit and the gain bit.

According to the above, the dual-domain sub-sampling phase-locked loop is capable of outputting the voltage-domain phase and the time-domain phase, and thus, a jitter with respect to the output clock of the digitally-controlled oscillator is effectively reduced.

