TECHNICAL FIELD

Embodiments of the disclosure relate generally to integrated circuit (IC) structure. More specifically, various embodiments of the disclosure provide an IC structure with an avalanche junction to a doped semiconductor over a semiconductor well.

BACKGROUND

Integrated circuits (ICs) may include elements for protecting the device hardware against electrostatic discharge (ESD) voltages that can cause electrical shorts, dielectric breakdown, and/or other failure modes. In an ideal setting, ESD elements have no effect on the device operation until an ESD event is seen by a pin on an IC where the ESD event acts as a trigger voltage, which turns on the ESD devices and discharges current through the ESD element to power, or ground supply rails. ESD elements may be designed to adjust their trigger voltages to allow input voltages that are higher than the power supply voltage without causing excess leakage through the ESD devices at elevated voltages. As ICs continue to become smaller and their scale decreases, lower trigger voltages may be needed for compliance with manufacturing specifications for the device. However, conventional approaches for reducing the trigger voltage can have the undesired effect of raising the holding voltage of the ESD element, i.e., the voltage level to which the device returns after the ESD element ceases operating. Conventional configurations for ESD elements and/or other structures have been unable to provide lower trigger voltages while keeping holding voltages the same or reducing them as well.

SUMMARY

Aspects of the present disclosure provide an integrated circuit (IC) structure, including: a doped well in a semiconductor substrate, the doped well having a first doping type; a base region within the doped well, and having the first doping type; an emitter region within the doped well and having a second doping type opposite the first doping type; a first insulator within the doped well, horizontally between the base region and the emitter region; a collector region within the doped well and having the second doping type; a second insulator within the doped well, horizontally between the collector region and the emitter region; an insulative material within the doped well, the insulative material having a first end horizontally adjacent the collector region and a second end opposite the first end; and a doped semiconductor region within the doped well adjacent the second end of the insulative material, wherein the doped semiconductor region is of the first doping type, such that an avalanche junction is defined between the collector region and the doped semiconductor region across the doped well.

Further aspects of the present disclosure provide an integrated circuit (IC) structure, including: a first doped well in a semiconductor substrate, and having a first doping type; a base region within the first doped well, and having the first doping type; a second doped well having a first end adjacent the first doped well, and a second end opposite the first end, the second doped well having a second doping type opposite the first doping type; a first insulator within the first doped well, horizontally between the base region and the second doped well; a third doped well adjacent the second end of the second doped well, the third doped well having the first doping type; an emitter region within the third doped well, the emitter region having the second doping type; a second insulator within the third doped well, horizontally between the emitter region and the second doped well; a collector region within the third doped well and having the second doping type; a third insulator within the third doped well, horizontally between the emitter region and the second doped well; an insulative material within the third doped well, the insulative material having a first end horizontally adjacent the collector region and a second end opposite the first end; and a doped semiconductor region within the third doped well adjacent the second end of the insulative material, wherein the doped semiconductor region is of the first doping type, such that an avalanche junction is defined between the collector region and the doped semiconductor region across the doped well.

Yet another aspect of the present disclosure provides an integrated circuit (IC) structure, including: a first doped well in a semiconductor substrate, and having a first doping type; a second doped well within the first doped well, the second doped well having a second doping type opposite the first doping type, wherein an upper surface of the second doped well is coplanar with an upper surface of the first doped well; a third doped well within the first doped well, and having the first doping type, wherein an upper surface of the third doped well is coplanar with the upper surface of the second doped well; a base region within the third doped well, and having the first doping type; a collector terminal within the third doped well and laterally separated from the base region by a first insulator, the collector terminal including a first pair of oppositely-doped semiconductor regions separated by a first insulative material within the third doped well, such that a first avalanche junction is defined between the first pair of oppositely-doped semiconductor regions; and an emitter terminal within the third doped well and laterally separated from the collector terminal by a second insulator, the emitter terminal including a second pair of oppositely-doped semiconductor regions separated by a second insulative material within the third doped well, such that a second avalanche junction is defined between the second pair of oppositely-doped semiconductor regions.

