FIELD OF THE DISCLOSURE

The disclosure relates generally to display devices, and more particularly to bezel-free display tiles comprising an edge-wrapped conductor and methods for manufacturing the same.

BACKGROUND

Displays comprised of a plurality of individual display tiles are used to manufacture large displays, which are sometimes referred to as tiled displays. For example, video walls comprised of multiple display tiles are known for their high-impact engagement and stunning visuals, and are utilized in a variety of settings, including retail environments, control rooms, airports, television studios, auditoriums and stadiums. As will be apparent fromFIG. 1, in current displays, the edge portions of the display tiles and the display device itself are utilized for electrical leads and various other electronic components associated with the operation of the display panel, such as driver circuits that can include thin film transistor arrays for an active matrix display. Examples of these displays include liquid crystal displays (LCD) and organic light emitting diode (OLED) displays. This has resulted in flat display panel manufacturers encasing the edge portions within and/or behind a bezel, which conceals the foregoing electronic components.

FIG. 1shows a prior art display tile50, which comprises a first substrate52having a first surface55and an outer perimeter56. The display tile50includes rows60of pixel elements, each row60of pixel elements58connected by a row electrode62and a plurality of columns70of pixel elements58, each column70of pixel elements58connected by a column electrode72. The display tile further includes at least one row driver65that activates the rows60of pixel elements58and at least one column driver75that activates the columns70of pixel elements58. In the prior art display tile50, the row drivers65and the column drivers75are located on the first surface55on the same side of the pixel elements, requiring a bezel (not shown) to cover the row drivers65and the column drivers75.

For aesthetic reasons, flat panel display makers are trying to maximize the image viewing area and provide a more aesthetically pleasing appearance by minimizing the size of the bezel surrounding the image on the display. However, there are practical limits to this minimization, and current bezel sizes are on the order of 3 millimeters to 10 millimeters in width.

There have been efforts in the industry to achieve tiled displays comprised of display tiles with no bezel and seamless zero millimeter bezel (referred to herein as “zero bezel” or “bezel-free”). Bezel-free display tiles allow for vast configurations of tiled displays without the need for irritating black gaps. To achieve a bezel-free display tile, it can be advantageous to have the pixel elements in close proximity to the edges of the display tiles. These pixel elements can be located on the front side of the display tile substrate and the control electronics on the back side. As a result, there is a need to electrically interconnect the front and back sides of the display tile substrate.

One way to achieve such interconnects in a display tile substrate made from glass is with metallized through glass vias (“TGVs”). Such TGVs can be used to manufacture a zero bezel microLED display, however, TGVs are fairly expensive to make, at least using current methods which involve laser damage of each hole (a serial process) followed by etch. The holes then need to be further processed for metallization.

Implementation of TGVs presents challenges with overall manufacturing process sequence. If the front of the tile substrate is to have a thin film transistor (TFT) array, a question arises as to when the glass vias are made and metallized. Since TFT array fabrication is traditionally done on a pristine glass surface, etching and metallization may best be done after TFT fabrication. As a result, the array must be protected from etch and also be compatible with the metallization technique.

There is a continuing need to provide efficient and effective interconnects on display tiles. It would be desirable to provide bezel-free display tiles that could be placed in an array to achieve a large display that maintains pixel pitch across tile boundaries of adjacent display tiles without metallized vias.

SUMMARY

A first aspect of the disclosure pertains to a display tile comprising a first substrate comprising a first surface, a second surface opposite the first surface and an edge surface between the first surface and the second surface, the edge surface defining an outer perimeter; the first surface comprising an array of pixel elements arranged in a plurality of rows of pixel elements and a plurality of columns of pixel elements, each row of pixel elements connected by a row electrode and each column of pixel elements connected by a column electrode; a row driver that activates the rows of pixel elements and a column driver that activates the columns of pixel elements, the row and the column drivers located opposite the first surface; a plurality of row electrode connectors, each row electrode connector wrapped around the edge surface and electrically connecting a row electrode, a row of pixel elements and the row driver; and a plurality of column electrode connectors, each column electrode connector wrapped around the edge surface and electrically connecting a column electrode, a columns of pixel elements and the column driver.

A second aspect of the disclosure pertains to a method of manufacturing a display tile, the method comprising placing at least one driver on a first substrate having pixel elements on a first surface of the first substrate, the driver placed on a second surface opposite the first surface and that can activate the pixel elements; and placing a connector on an edge surface and extending to the first surface and the second surface, the edge surface defining an outer perimeter.

A third aspect of the disclosure pertains to a method of manufacturing a display, comprising placing display tiles described herein in close proximity to each other at respective edge surfaces of the display tiles.

A fourth aspect of the disclosure pertains to a method of manufacturing a plurality of display tiles comprising stacking a plurality of substrates to provide a stack, each of the plurality of substrates having a first surface, a second surface opposite the first surface and an edge surface between the first surface and the second surface, the edge surface defining an outer perimeter; arranging the stack at an angle with respect to a horizontal surface to expose the edge surface; depositing conductive material on the edge surface, the first surface and the second surface to form a plurality of row electrode connectors and a plurality of column electrode connectors; electrically connecting an array of pixel elements arranged in a plurality of rows of pixel elements and a plurality of columns of pixel elements so that there are individual rows of pixel elements on the first surface of each of the plurality of substrates, the individual rows of pixel elements connected with individual row electrodes and individual row electrode connectors; electrically connecting individual columns of pixel elements on the first surface of each of the plurality of substrates with individual column electrodes and individual column electrode connectors; and placing at least one driver on a second surface opposite the first surface of each of the plurality of substrates, wherein the driver can activate the pixel elements.

