BACKGROUND OF THE INVENTION

Field of the Invention

The present disclosure relates to a semiconductor device drive circuit.

Description of the Background Art

An error signal occurs in accordance with a variation of secondary side reference potential VS in a semiconductor device drive circuit associated with a level shift from a primary side circuit to a secondary side circuit in some cases. The variation of the secondary side reference potential VS is also represented as dV/dt hereinafter. International Publication No. 2017/159058 discloses a method of adjusting impedance of a level shift circuit at a time of dV/dt to suppress the occurrence of the error signal.

SUMMARY

According to the method disclosed in International Publication No. 2017/159058, the impedance itself of the level shift circuit is adjusted at the time of dV/dt. A dV/dt detection circuit receives an output signal from the level shift circuit, detects a dV/dt period, and outputs the dV/dt period to an impedance adjusting part. The dV/dt detection circuit receives a feedback caused by a drive of the impedance adjusting part, thus there is a problem that the dV/dt detection circuit cannot stably detect the dV/dt period, and the output of the level shift circuit becomes unstable.

An object of a technique of the present disclosure is to provide a semiconductor device drive circuit stably preventing an erroneous operation at a time of dV/dt.

A semiconductor device drive circuit according to the present disclosure includes a pulse generation circuit, an on-side level shift circuit, an off-side level shift circuit, an on-side pulse transmission circuit, an off-side pulse transmission circuit, a dV/dt detection circuit, a logic filter circuit, and a latch circuit. The pulse generation circuit outputs an on-pulse signal synchronized with a leading edge of an input signal and an off-pulse signal synchronized with a falling edge. The on-side level shift circuit outputs a level shift on-pulse signal in which a level of reference potential of the on-pulse signal is shifted from primary side reference potential to secondary side reference potential. The off-side level shift circuit outputs a level shift off-pulse signal in which a level of reference potential of the off-pulse signal is shifted from primary side reference potential to secondary side reference potential. The on-side pulse transmission circuit outputs an on-pulse transmission signal based on the level shift on-pulse signal. The off-side pulse transmission circuit outputs an off-pulse transmission signal based on the level shift off-pulse signal. The dV/dt detection circuit detects a dV/dt period which is a variation period of the secondary side reference potential based on the level shift on-pulse signal and the level shift off-pulse signal. The logic filter circuit is provided in a latter stage of the on-side pulse transmission circuit and the off-side pulse transmission circuit, and does not change an output when both the on-pulse transmission signal and the off-pulse transmission signal are input. The latch circuit outputs a signal synchronized with an output of the logic filter circuit. The on-side pulse transmission circuit includes an on-side impedance adjusting part. The on-side impedance adjusting part reduces a signal level of the on-pulse transmission signal during the dV/dt period. The off-side pulse transmission circuit includes an off-side impedance adjusting part. The off-side impedance adjusting part reduces a signal level of the off-pulse transmission signal during the dV/dt period.

The semiconductor device drive circuit according to the present disclosure reduces the signal level of the on-pulse transmission signal and the off-pulse transmission signal during the dV/dt period, thereby preventing erroneously drive of a semiconductor device. The on-pulse transmission signal and the off-pulse transmission signal are not input to the dV/dt detection circuit, thus the dV/dt period can be stably detected. Accordingly, an erroneous operation at the time of dV/dt can be stably prevented.

These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

