TECHNICAL FIELD

Examples of the present disclosure generally relate to a multi-port memory system (e.g., a system that can perform multiple reads and writes in parallel) that uses a single port memory (e.g., a memory element that can perform only a read or only a write at any given time).

BACKGROUND

Many applications require a memory to perform read and writes in parallel (e.g., multi-port memory systems). These systems typically include dual-ported memories (i.e., memories that perform at least one read and write in parallel) to implement large delay buffers and dynamic coefficient storage. In an application specific integrated circuit (ASIC), a dual-ported memory consumes more area and power per bit than single port memory (i.e., memories that can perform only a single read or a single write at any given time). Also, multiple independent small memories are inefficient in area when compared with a single large memory. Thus, there are large area and power advantages of replacing a multi-port memory (e.g., a two-port memory that can perform a read and write in parallel) with single port memories. Doing so can result in a 40% reduction in area for memory macros.

SUMMARY

One embodiment describes a multi-port memory system that includes a single port memory capable of performing only one read or one write at a time where an address space of the single port memory is half or less than the address space of the multi-port memory system, a divider configured to divide received read and write addresses, a first register coupled to a write data port of the single port memory and configured to store a received write data word when the single port memory is performing a read operation, and a second register coupled to a read data port of the single port memory and configured to store a first data word of a plurality of data words read from the single port memory during the read operation. Further, to a perspective of an external entity, the multi-port memory system performs at least one of (i) at least one read and at least one write operation in parallel or (ii) multiple reads or multiple writes in parallel using the single port memory.

Another embodiment described herein is a method that includes writing, during a first cycle, a first plurality of data words into the single port memory using a write data port, reading, during a second cycle, a second plurality of data words from a first memory address of the single port memory using a read data port, storing, during the second cycle, a first one of the second plurality of data words in a first register coupled to the read data port, outputting, during the second cycle, a second one of second plurality of data words as read data, storing, during the second cycle, a first received word in a second register coupled to a write data port of the single port memory, writing, during a third cycle, the first received word and a second received word into a second memory address of the single port memory using the write data port, and outputting, during the third cycle, the second one of the second plurality of data words as read data.

Another embodiment described herein is a multi-port memory system that includes a single port memory capable of performing only one read or one write at a time where a depth of the multi-port memory system is greater than the depth of the single port memory and a width of the multi-port memory system is less than a width of the single port memory, a first register coupled to a write data port of the single port memory and configured to store a received write data word when the single port memory is performing a read operation, and a second register coupled to a read data port of the single port memory and configured to store a first data word of a plurality of data words read from the single port memory during the read operation. Further, an access pattern corresponding to the multi-port system is sequential such that memory addresses used to perform read and write operations increment according to a fixed amount.

