TECHNICAL FIELD

The disclosure relates to a semiconductor integrated circuit, more particularly to a semiconductor device having metal layers formed by a dual damascene process.

BACKGROUND

As the semiconductor industry introduces new generations of integrated circuits (ICs) having higher performance and greater functionality, the density of the elements that form the ICs is increased, while the dimensions and spacing between components or elements of the ICs are reduced. The structure of metal wiring layers also becomes complex and minimized. To fabricate the metal wiring layers, a damascene process has been used together with a low-k (low dielectric constant being, e.g., 3.5 or lower) material.

