BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to an imaging device, an imaging system, and a semiconductor chip.

Description of the Related Art

Conventionally, imaging devices having an analog-to-digital conversion unit have been used. An imaging device disclosed in Japanese Patent Application Laid-Open No. 2009-124514 includes an analog-to-digital conversion unit having a comparator that compares a signal of a photoelectric conversion unit with a reference voltage signal and a source ground circuit connected to the comparator. The imaging device disclosed in Japanese Patent Application Laid-Open No. 2009-124514 further has a current compensation circuit that compensates current fluctuations in the comparator and intends to avoid image quality deterioration due to the power source fluctuations.

In recent years, an imaging device in which a plurality of semiconductor chips are stacked has been proposed. In an imaging device with the stacked structure, since a constraint for the chip area is relatively small, it is possible to increase the number of pixels and analog-to-digital conversion units. In Japanese Patent Application Laid-Open No. 2009-124514, however, there is no suggestion for the configuration and arrangement of the analog-to-digital conversion units in the imaging device with the stacked structure.

The present invention intends to provide a technique for the configuration and arrangement of the analog-to-digital conversion units in an imaging device with stacked structure.

SUMMARY OF THE INVENTION

An imaging device in the disclosure of the present specification includes: a first semiconductor chip in which a plurality of pixels that generate pixel signals are formed; and a second semiconductor chip stacked on the first semiconductor chip and including a plurality of analog-to-digital conversion units that convert analog signals output from the pixels into digital signals. The plurality of analog-to-digital conversion units include comparators, respectively, and each of the comparators compares each of the analog signals with a reference signal, and each of the comparators includes a differential amplifier circuit including an output node that outputs a first signal based on a difference between each of the analog signals and the reference signal, a source ground circuit that includes an input transistor including a gate configured to receive the first signal from the output node of the differential amplifier circuit and a load transistor cascade-connected to the input transistor and outputs a second signal from a connection node of the input transistor and the load transistor, and a current compensation circuit that includes a current control transistor including a gate configured to receive the second signal from the connection node and a current source transistor cascade-connected to the current control transistor and causes a second current to flow that changes complementarily with respect to a change of a first current flowing in the source ground circuit.

An imaging device in another disclosure of the present specification is an imaging device including analog-to-digital conversion units that convert, into digital signals, analog signals output via signal lines from a plurality of pixels that generate pixel signals. Each of the analog-to-digital conversion units includes a comparator that compares each of the analog signals with a reference signal, and the comparator includes a differential amplifier circuit that outputs a first signal based on a difference between each of the analog signals and the reference signal, a source ground circuit that includes a first transistor of a first polarity connected to a first power source, in which the first signal is input to the first transistor, and a second transistor of a second polarity connected to a second power source and outputs a second signal inverted from the first signal from a connection node of the first transistor and the second transistor, and a current compensation circuit that includes a third transistor of the first polarity connected to the first power source, a fourth transistor of the second polarity connected to the second power source, and a fifth transistor of the first polarity provided between the third transistor and the fourth transistor, wherein the second signal is input to the fifth transistor, and the fifth transistor causes a second current to flow that changes complementarily with respect to a change of a first current flowing in the source ground circuit. At least any one of a first group of elements in which the first transistor and the third transistor are arranged adjacent to each other and a second group of elements in which the second transistor and the fourth transistor are arranged adjacent to each other is formed.

A semiconductor chip in another disclosure of the present specification is a semiconductor chip to be stacked including: a connection portion used for connecting to another semiconductor chip in which a plurality of pixels each including a photoelectric conversion unit are formed; and analog-to-digital conversion units that convert analog signals output from the pixels via signal lines into digital signals. Each of the analog-to-digital conversion units includes a comparator that compares each of the analog signals with a reference signal, and the comparator includes a differential amplifier circuit including an output node that outputs a first signal based on a difference between each of the analog signals and the reference signal, a source ground circuit that includes an input transistor including a gate configured to receive the first signal from the output node of the differential amplifier circuit and a load transistor cascade-connected to the input transistor and outputs a second signal from a connection node of the input transistor and the load transistor, and a current compensation circuit that includes a current control transistor including a gate configured to receive the second signal from the connection node and a current source transistor cascade-connected to the current control transistor, in which the current control transistor causes a second current to flow that changes complementarily with respect to a change of a first current flowing in the source ground circuit.

Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.

