TECHNICAL FIELD

The present application relates to the technical field of semiconductors, and in particular, to a manufacturing method of a memory.

BACKGROUND

With gradual development of storage device technologies, a dynamic random access memory (DRAM) is widely used in various electronic devices due to its high density and fast reading/writing speed. A DRAM usually includes a plurality of memory cells. Each memory cell includes a transistor and a capacitor. A gate of the transistor is electrically connected to a word line, a source of the transistor is electrically connected to a bit line, and a drain of the transistor is electrically connected to the capacitor. A word line voltage on the word line can control on or off of the transistor, such that data information stored in the capacitor can be read through the bit line or data information can be written to the capacitor.

During manufacturing of a memory, a void or a seam is easily formed within a bit line contact, resulting in performance degradation of the memory.

SUMMARY

Embodiments of the present application provide a manufacturing method of a memory, where the manufacturing method includes: providing a substrate, where the substrate includes a core region and a peripheral region located outside the core region, a plurality of active regions are arranged at intervals in the core region, and a first barrier layer is further provided in the core region; laminating and forming a first conductive layer and a first mask layer on the substrate in sequence; etching the first mask layer, the first conductive layer, and the first barrier layer which are in the core region, to form a first etched hole penetrating through the first mask layer, the first conductive layer, and the first barrier layer, where the first etched hole is opposite to the active region; etching the substrate along the first etched hole, to form a bit line contact hole, where the bit line contact hole exposes the active region; removing the first mask layer and the first conductive layer which are in the core region and located around the bit line contact hole, and retaining the first barrier layer located around the bit line contact hole; and forming a bit line contact in the bit line contact hole, where the bit line contact is electrically connected to the active region, and a surface of the bit line contact away from the substrate is flush with a surface of the first barrier layer away from the substrate.

