CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application Nos. 10-2019-0094008, 10-2019-0097258, and 10-2020-0007423, filed on Aug. 1, 2019, Aug. 9, 2019, and Jan. 20, 2020, respectively, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present disclosure relates to a semiconductor device, and more particular, to a semiconductor device including a field effect transistor.

Due to their small-sized, multifunctional, and/or low-cost characteristics, semiconductor devices are being esteemed as important elements in the electronic industry. The semiconductor devices are classified into a semiconductor memory device for storing data, a semiconductor logic device for processing data, and a hybrid semiconductor device including both of memory and logic elements. As the electronic industry advances, there is an increasing demand for semiconductor devices with improved characteristics. For example, there is an increasing demand for semiconductor devices with high reliability, high performance, and/or multiple functions. To meet this demand, complexity and/or integration density of semiconductor devices are being increased.

SUMMARY

An embodiment of the inventive concept provides a semiconductor device with improved performance or reliability characteristics.

According to an exemplary embodiment of the present inventive concept, a semiconductor device includes a first gate electrode disposed on a substrate and extending in a first horizontal direction with respect to an upper surface of the substrate, a first gate contact and a dummy gate contact, which are spaced apart from each other in the first horizontal direction and are in contact with a top surface of the first gate electrode, a first interconnect line extending in a second horizontal direction, different from the first horizontal direction, with respect to the upper surface of the substrate and overlapping the first gate contact in a vertical direction with respect to the upper surface of the substrate, and a voltage generator configured to generate a first voltage and apply the first voltage to the first gate electrode via the first interconnect line and the first gate contact. The first gate electrode receives the first voltage via the first interconnect line and the first gate contact from the voltage generator. The dummy gate contact receives the first voltage via the first gate electrode.

According to an exemplary embodiment of the present inventive concept, a semiconductor device includes a plurality of gate electrodes on a substrate, each of the plurality of gate electrodes extending in a first horizontal direction with respect to an upper surface of the substrate and the plurality of gate electrodes being spaced apart from each other in a second horizontal direction, with respect to the upper surface of the substrate, different from the first horizontal direction, a plurality of gate contacts, each of the plurality of gate contacts being disposed on a respective one of the plurality of gate electrodes and electrically connected thereto, a plurality of interconnect lines, each of the plurality of interconnect lines extending in the second horizontal direction and overlapping, in a vertical direction with respect to the upper surface of the substrate, at least one gate contact of the plurality of gate contacts, and the plurality of interconnect lines being spaced apart from each other in the first horizontal direction, a voltage generator configured to generate a first voltage and apply the first voltage to the plurality of gate electrodes via the plurality of gate contacts and the plurality of interconnect lines, and a dummy gate contact disposed on a corresponding one gate electrode of the plurality of gate electrodes and spaced apart, in the first horizontal direction, from a gate contact disposed on the corresponding one gate electrode. The first voltage is applied to the dummy gate contact through the corresponding one gate electrode.

According to an exemplary embodiment of the present inventive concept, a semiconductor device includes a substrate including a first active region and a second active region, which are spaced apart from each other in a first horizontal direction with respect to an upper surface of the substrate, a plurality of active fins, which protrude from the substrate in a vertical direction with respect to the upper surface of the substrate and extend in a second horizontal direction, with respect to the upper surface, crossing the first horizontal direction, first to third gate electrodes, which cross the plurality of active fins in the first horizontal direction, are parallel to each other in the second horizontal direction, and are line-shape patterns, a first gate contact disposed on the second gate electrode and overlapping, in the vertical direction, a region between the first active region and the second active region, and a first dummy gate contact overlapping the second gate electrode in the vertical direction and spaced apart from the first gate contact in the first horizontal direction, the first dummy gate contact overlapping in the vertical direction or is adjacent, in the first horizontal direction, to one of the first active region and the second active region and at least two or three active fins of the plurality of active fins being disposed in each of the first active region and the second active region, a first interconnect line extending in the second horizontal direction and overlapping first gate contact in the vertical direction, and a voltage generator configured to generate a first voltage and apply the first voltage to the second gate electrode through the first gate contact and the first interconnect line. The first voltage is applied to the first dummy gate contact through the second gate electrode.

