BACKGROUND OF INVENTION

1. Field of the Invention

The invention relates generally to integrated transceiver chips, and more specifically to wafer-level testing of transmitter to receiver links of multiple integrated transceiver chips.

2. Description of the Related Art

In recent memory, integrated photonics transceivers have become widely developed and thus deployed in high volume for use in various optical communication systems. As is known in the art, a transceiver chip may comprise a transmitter (Tx) adapted for electrical-to-optical (EO) conversion, and a receiver (Rx) adapted for optical-to-electrical (OE) conversion, for example. As an example, a transmitter, which may be realized using a Mach-Zehnder Interferometer (MZI) modulator having 1×2 couplers, requires two optical edge couplers for proper functionality, an input edge coupler (adapted to connect to a laser light source for receiving laser light) and an output edge coupler (adapted to couple the laser light out). A receiver, for example, may be realized using a single-input P-I-N-based photodetector (PD), which may require one input optical edge coupler (adapted to receive encoded laser light). Edge couplers, for example, are often utilized to achieve broadband low-loss optical input/output (I/O) in transceiver products. Moreover, transceiver chips may be provided with electrical pads disposed along the chip surface, such as along an edge of the chip, to provide electrical connections between on-chip components (e.g., Rx, Tx, etc.) and external components (e.g., drivers, transimpedance amplifiers, PCBs, etc.).

In order to ensure sufficient and/or proper functionality of a given transceiver chip, all of the components disposed on the transceiver chip must undergo a screening test before the chip is packaged into a module product, for example. Accordingly, only the transceiver chips having on-chip components that have passed the screening test will be selected for packaging, such that to substantially guarantee the product yield (and thus minimize the failure rate). The on-chip components to be tested in this case are the modulators (i.e., the Tx) and the PDs (i.e., the Rx). As an example, the screening test assesses the EO performance of the modulator, which requires coupling optical light into and out of the chip, for example, while the assessment of the OE performance of the PD requires coupling optical light into the chip. Conventionally, transceiver chips must be diced (cut) from a wafer, which comprises a plurality of transceiver chips, packaged with a laser light source through edge coupling (e.g., via lens or fiber array coupling), and then tested. Upon assessment of each of the transceiver chips, the packaged chips that show good/sufficient performance will be approved for packaging into a product. Clearly, this approach to screening is costly and time-consuming.

Recently, approaches to solving the above problems have been developed that utilize on-chip grating couplers to test the functionality of the transmitters and receivers on a wafer level, which thus negate the need for dicing the wafer into individual transceiver chips. Using such approaches, laser light can be vertically coupled into and out of each transceiver chip on the wafer through the on-chip grating couplers. As such, the above-described screening test can be performed across all the transceiver chips in a wafer one after another, which can be automated (via a computer, for example) at a single automatic testing station, for example. Using the wafer-level test results, operational/sufficient chips and nonoperational/insufficient chips may be marked and thus singled out on a wafer map modeling on the wafer, as an example. Once the wafer is diced into individual transceiver chips, only the known sufficient chips will be sent for packaging and product implementation, as an example. Thus, the use of grating couplers allows the chip screening and sorting processes to run more efficiently and cost-effectively and may also benefit the yield and quality control.

However, some of the approaches described above of on-wafer testing of integrated photonics components (e.g., Tx and Rx) require the use of additional edge couplers (aside from those already on the transceivers) and additional grating couplers disposed outside the actual transceiver chips, which thus occupies space on the wafer itself. These additional edge couplers and grating couplers are diced away and thus disposed of after the screening tests are completed, which is wasteful and thus reduces the number of transceiver chips that could be provided on the wafer. In addition, the screening tests of the transceiver chips are geared toward testing the Tx and Rx components individually, rather than as a link, for example.

Therefore, there is a need to solve the problems described above by providing a system and method for easily, efficiently, and cost-effectively testing transmitter to receiver links of integrated transceiver chips on a wafer level.

The aspects or the problems and the associated solutions presented in this section could be or could have been pursued; they are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches presented in this section qualify as prior art merely by virtue of their presence in this section of the application.

BRIEF INVENTION SUMMARY

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key aspects or essential aspects of the claimed subject matter. Moreover, this Summary is not intended for use as an aid in determining the scope of the claimed subject matter.

In an aspect, an integrated transceiver chip is provided. The integrated transceiver chip may comprise: a plurality of bidirectional ports, each bidirectional port of the plurality of bidirectional ports being aligned to an edge of the integrated transceiver chip; a plurality of grating couplers; a receiver having a first and a second input ports, the first input port being optically connected to a first grating coupler of the plurality of grating couplers, and the second input port being optically connected to a first bidirectional port of the plurality of bidirectional ports; and a transmitter having a first and a second input and a first and a second output ports, the first input port being optically connected to a second bidirectional port of the plurality of bidirectional ports and the second input port being optically connected to a second grating coupler of the plurality of grating couplers, and the first output port being optically connected to a third bidirectional port of the plurality of bidirectional ports and the second output port being optically connected to a third grating coupler of the plurality of grating couplers; wherein the receiver is adapted to receive a first optical signal being launched into one of the first grating coupler and the first bidirectional port, and the transmitter is adapted to receive a second optical signal being launched into one of the second bidirectional port and the second grating coupler, the transmitter being further adapted to cause a transmitting of the second optical signal to one of the third grating coupler and the third bidirectional port. Thus, an advantage is that on-chip transmitter and receiver components may be effectively and efficiently tested using grating couplers on the wafer level, thus reducing time consumption associated with individually testing each and every component. Another advantage of the disclosed transceiver chip is the ability to customize and rearrange the layout of the transceiver chip, such that to accommodate specific optical applications, for example, while maintaining the ability to test the Tx and Rx components on a wafer level. An additional advantage is that, because of the increased efficiency in the testing process of transceiver chips on the wafer level, cost efficiency may be increased.

In another aspect, an assembly for wafer-level testing of transmitters and receivers of integrated transceiver chips disposed on a wafer is provided. The assembly may comprise at least one coupled pair of a first and a second integrated transceiver chips, the at least one coupled pair of a first and a second integrated transceiver chips comprising: a plurality of first bidirectional ports each aligned to an edge of the first integrated transceiver chip, and a plurality of second bidirectional ports each aligned to an edge of the second integrated transceiver chip; wherein at least one first bidirectional port of the plurality of first bidirectional ports and at least one second bidirectional port of the plurality of second bidirectional ports are aligned and optically connected; a plurality of first grating couplers disposed on the first integrated transceiver chip, and a plurality of second grating couplers disposed on the second integrated transceiver chip; and a first transmitter and a first receiver disposed on the first integrated transceiver chip, and a second transmitter and a second receiver disposed on the second integrated transceiver chip; wherein one of the plurality of first grating couplers is optically connected to the first transmitter, the first transmitter being optically connected to one of the at least one first bidirectional ports aligned and optically connected to one of the at least one second bidirectional ports, the one of the at least one second bidirectional ports being optically connected to the second receiver, such that an optical link is established between the first transmitter of the first integrated transceiver chip and the second receiver of the second integrated transceiver chip. Thus, an advantage is that chip space utilization may be maximized and thus optimized on the wafer, which may increase overall product output. Another advantage is that manufacturing costs for the wafer may be reduced as a result of using solely on-chip components for conducting tests of the transceiver chip. Another advantage is that on-chip transmitter and receiver components may be effectively and efficiently tested using links on the wafer level, thus reducing time consumption associated with individually testing each and every component. An additional advantage is that, because of the increased efficiency in the testing process of transceiver chips on the wafer level, cost efficiency may be increased.

In another aspect, a method of enabling wafer-level testing of a pair of a first and a second integrated transceiver chips disposed on a wafer is provided, the pair of a first and a second integrated transceiver chips each comprising a transmitter and a receiver. The method may comprise establishing a transmitter-to-receiver link between the first and the second integrated transceiver chips, the transmitter-to-receiver link being established by: providing a plurality of bidirectional ports on each of the first and the second integrated transceiver chips, wherein at least a first and a second bidirectional ports of each of the first and the second integrated transceiver chips, respectively, are aligned and optically connected; providing a plurality of grating couplers on each of the first and the second integrated transceiver chips, wherein a first grating coupler is optically connected to a first transmitter of the first integrated transceiver chip, and a second grating coupler is optically connected to a second transmitter of the second transceiver chip; optically connecting the first transmitter to the first bidirectional port; and optically connecting a second receiver of the second integrated transceiver chip to the second bidirectional port, such that to establish a transmitter-to-receiver link between the first transmitter and the second receiver, the transmitter-to-receiver link enabling wafer-level testing of the first and the second transceiver chips. Thus, an advantage of the disclosed method is that costs associated with purchasing and implementing external optical testing components may be greatly reduced. Another advantage is that on-chip transmitter and receiver components may be effectively and efficiently tested using links on the wafer level, thus reducing time consumption associated with individually testing each and every component. An additional advantage of the disclosed method is that wafer-level testing may be efficiently conducted for pairs of transceivers having only one pair of directly connected edge couplers. An additional advantage is that, because of the increased efficiency in the testing process of transceiver chips on the wafer level, cost efficiency may be increased.

The above aspects or examples and advantages, as well as other aspects or examples and advantages, will become apparent from the ensuing description and accompanying drawings.

