BACKGROUND

I. Technical Field

The present disclosure relates to microprocessor implementations that execute instructions in pipelined fashion.

II. Background

A microprocessor implementation may execute instructions in pipelined, or staged, fashion to optimize resource utilization and to compensate for execution time complexity that would otherwise limit throughput. This customary approach may be used to optimize throughput at the cost of unnecessary execution latency for some instructions, particularly simpler operations requiring fewer resources. Variable-latency instructions are often included in such pipelined implementations. The exact execution latency of such variable-latency instructions may span a wide range of possibilities, but the results data are necessary to begin execution of subsequent (i.e. dependent) instructions. The requirement to wait for the results data can leave execution resources underutilized, an effect that can be mitigated, particularly when a given variable-latency instruction's actual execution latency can be anticipated.

Some implementations may compensate for variable-latency execution by scheduling independent instructions for execution, either out-of-order from the same code flow, or by supporting multiple independent code flows. Some implementations may include other resources and optimizations to minimize variable-length instruction latency, or to reduce the latency variance to a narrower range of possibilities.

SUMMARY

Consistent with embodiments of this disclosure, there is provided a system for predicting latency of at least one variable-latency instruction. The system includes a microprocessor including at least one pipeline, the at least one pipeline having an instruction stream. The microprocessor in the system is configured to issue at least one dependent instruction, execute at least one pipeline to serve at least one variable-latency instruction, and generate a result of the at least one variable-latency instruction, and serve the at least one dependent instruction by using the result of the at least one variable-latency instruction.

Consistent with embodiments of this disclosure, there is also provided a method, performed by a microprocessor including at least one instruction stream pipeline, for predicting latency of at least one variable-latency instructions. The method includes issuing at least one dependent instruction, executing the at least one instruction stream pipeline to serve at least one variable-latency instruction, generating a result of the at least one variable-latency instruction, and serving the at least one dependent instruction by using the result of the at least one variable-latency instruction.

The foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the claims.

