CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 16/546,002 filed Aug. 20, 2019, which claims the priority benefit of French Application for Patent No. 1857840, filed on Aug. 31, 2018, the contents of which are hereby incorporated by reference in their entireties to the maximum extent allowable by law.

TECHNICAL FIELD

Embodiments relate to integrated circuits, in particular to integrated antifuse devices and more particularly to the protection of integrated circuits from reverse engineering, for example to the protection of memory-storage integrated circuits from attacks by probing.

BACKGROUND

Integrated circuits, in particular those provided with memories containing sensitive information, have to be protected to the greatest possible extent from reverse-engineering operations, in particular from those intended to uncover stored data.

The stored data may, for example, be binary information, and be stored on antifuse devices including two terminals, which may be in a broken-down (or on) state, to represent a first binary value, or in a non-broken-down (or off) state, to represent a second binary value of the data.

A possible attack may be carried out after thinning the integrated circuit so as to get as close as possible to the antifuse devices in order to measure the resistance between the two terminals of the antifuse device and, in this way, to learn their states.

There are solutions allowing an operation of thinning the integrated circuit to be detected, and the stored data to be made unreadable in the event of a thinning operation having taken place.

Although these solutions are effective, they may, in some cases, be complex to implement or bypassed.

There is a need to produce an antifuse device structure which is technologically simple and which, when it is used in particular in a memory cell, allows facilitated reading.

SUMMARY

According to one embodiment, what is proposed is a new antifuse device structure which may in particular be used for data storage and which is complex to analyze in the context of a reverse-engineering operation, most particularly in the context of a memory module having a matrix architecture.

According to one aspect, what is proposed is an integrated circuit including at least one memory cell comprising an antifuse device including a state transistor having a control gate and a second gate that is configured to be floating so as to confer a non-broken-down state on the antifuse device or to be electrically coupled to the control gate so as to confer a broken-down state on the antifuse device.

Incorporating an antifuse device into a double-gate state transistor structure (a structure having a control gate and a floating gate) is technologically straightforward since this embodiment uses existing double-gate state transistor structures and simply requires that the dielectric layer between the two gates be broken down or not broken down.

Furthermore, combining an antifuse device with a MOS transistor advantageously allows the state of the antifuse device to be read by biasing the transistor, and hence the formation of a contact on the second gate to be avoided. Thus, it is not possible for an attacker to measure the electrical resistance between the two gates for the purpose of learning the state of the antifuse device.

The state transistor may include at least a first polysilicon region and a second polysilicon region separated by a layer of dielectric material, the second gate including the first polysilicon region and the control gate including the second polysilicon region, the broken-down state of the antifuse device resulting in an electrical connection between the first polysilicon region and the second polysilicon region through the layer of dielectric material.

The integrated circuit may comprise an electrically conductive connecting element including a first end that is electrically coupled to the second gate and a second, free end that is located outside the integrated circuit.

The integrated circuit may include a sealing ring including metal tracks and vias extending around the entire periphery of the integrated circuit, the connecting element including a crossing part which crosses said sealing ring, the second end being located outside the sealing ring.

This sealing ring advantageously allows the integrated circuit to be protected in particular during a cutting step.

According to one embodiment, the integrated circuit includes a semiconductor well, the bottom of which is delimited by a buried semiconductor region and including an insulated vertical electrode extending from the upper face of the well down to a region close to the bottom of the well, a heavily n-doped region providing electrical continuity between the vertical electrode and the buried semiconductor layer, said vertical electrode comprising said first polysilicon region and forms the second gate, the state transistor being a vertical transistor.

The memory cells may advantageously be interconnected according to a matrix architecture, each memory cell including an access transistor which is coupled between the MOS transistor and a read line which is common to all of the cells.

For a memory cell to be read, it is then necessary for the access transistor of said memory cell to be on and the other access transistors of the line to be kept in an off state so as to avoid parasitic currents propagating over the read line and falsifying the result.

An attacker will therefore have to use a distinct probe for each access transistor of the line, which makes the read operation very complex or even impossible when the matrix includes a substantial number of columns, for example more than 10 or so columns.

A plurality of memory cells may share one and the same first polysilicon region.

According to one aspect, what is proposed is a semiconductor wafer including first zones including integrated circuits such as defined above, which first zones are separated from one another by second zones including cutting lines, wherein the second end of the connecting element of at least one integrated circuit is located in a second zone such that the integrated circuit and the second end are located on either side of the corresponding cutting line.

It is thus possible to program the memory cells before the step of cutting through the integrated circuit, via the connecting element. During the cutting operation, the connecting element is severed, leaving the first polysilicon region unconnected to a fixed potential.

According to one aspect, what is proposed is a method for programming at least one memory cell including an antifuse device such as defined above, comprising an operation of forming an electrical connection between the control gate and the second gate so as to have said broken-down state, or an operation of placing the second gate in the floating state so as to have said non-broken-down state.

The operation of programming said at least one memory cell may include an operation of setting the potential of the second gate to a first reference potential via a connecting element, the application or otherwise of a second reference potential so as to place said antifuse device in a broken-down or non-broken-down state, respectively, and an operation of cutting through said connecting element in such a way that its second end is free.

According to one aspect, what is proposed is a method for reading at least one memory cell of an integrated circuit such as defined above, wherein the control gate of the state transistor is biased and the drain current of the state transistor is read, a drain current that is below a threshold being read indicating a non-broken-down state of the antifuse device and a drain current that is above said threshold being read indicating a broken-down state of the antifuse device.

According to another aspect, what is proposed is a chip card incorporating an integrated circuit such as defined above.

