The present application claims priority to the Chinese patent application No. 201710582688.2, filed on Jul. 17, 2017, the entire disclosure of which is incorporated herein by reference as part of the present application.

TECHNICAL FIELD

Embodiments of the present disclosure relate to a shift register unit, a scan driving circuit, an array substrate, a display device, and a driving method.

BACKGROUND

Compared with traditional technologies, the Gate driver On Array (GOA) technology can not only save a circuit board carrying the gate driver and realize a symmetrical design on both sides of a display panel, for example, but also can save wiring areas of a chip bonding area and a fan-out area on the edge of the display panel and is beneficial to realize a narrow border. Also, because the GOA technology can omit the chip bonding process in a row direction, it is also greatly helpful to improve the overall productivity and yield.

SUMMARY

At least one embodiment of the present disclosure provides a shift register unit, which includes an input terminal, an output terminal, an input circuit, a replacement circuit, an output circuit, and a pull-down circuit. The input circuit is respectively connected to the input terminal and a first node, and is configured to set the first node to an active level when the input terminal is at an active level; the replacement circuit is respectively connected to the input terminal and a second node, and is configured to set the second node to an inactive level when the input terminal is at an active level; the output circuit is respectively connected to the first node and the output terminal, and is configured to set the output terminal to an active level by using a clock signal when the first node is at an active level; and the pull-down circuit is respectively connected to the first node, the output terminal, and the second node, and is configured to set the first node to an inactive level and the output terminal to an inactive level when the second node is at an active level.

For example, in the shift register unit provided by an embodiment of the present disclosure, the replacement circuit includes a first transistor, a gate electrode of the first transistor is connected to the input terminal, a first electrode of the first transistor is connected to the second node, and a second electrode of the first transistor is connected for the inactive level of the second node.

For example, the shift register unit provided by an embodiment of the present disclosure further includes a pull-down control circuit; the pull-down control circuit is respectively connected to the first node and the second node, and is configured to set the second node to the inactive level when the first node is at the active level, and use the clock signal to set the second node to the active level when the first node is at an inactive level.

For example, the shift register unit provided by an embodiment of the present disclosure further includes a reset terminal and a reset circuit; the reset circuit is respectively connected to the reset terminal, and the first node and the output terminal, and is configured to set the first node to the inactive level and the output terminal to the inactive level when the reset terminal is at an active level.

For example, in the shift register unit provided by an embodiment of the present disclosure, the input circuit includes a second transistor, a gate electrode of the second transistor is connected to the input terminal, a first electrode of the second transistor is connected to the input terminal or connected for the active level of the first node, and a second electrode of the second transistor is connected to the first node.

For example, in the shift register unit provided by an embodiment of the present disclosure, the output circuit includes a third transistor and a first capacitor; a gate electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to a first clock signal line, and a second electrode of the third transistor is connected to the output terminal; and a first terminal of the first capacitor is connected to the first node, and a second terminal of the first capacitor is connected to the output terminal.

For example, in the shift register unit provided by an embodiment of the present disclosure, the reset circuit includes a fourth transistor and a fifth transistor, a gate electrode of the fourth transistor is connected to the reset terminal, a first electrode of the fourth transistor is connected to the first node, and a second electrode of the fourth transistor is connected for the inactive level of the first node; and a gate electrode of the fifth transistor is connected to the reset terminal, a first electrode of the fifth transistor is connected to the output terminal, and a second electrode of the fifth transistor is connected for the inactive level of the output terminal.

For example, in the shift register unit provided by an embodiment of the present disclosure, the pull-down circuit includes a sixth transistor and a seventh transistor, a gate electrode of the sixth transistor is connected to the second node, a first electrode of the sixth transistor is connected to the first node, and a second electrode of the sixth transistor is connected for the inactive level of the first node; and a gate electrode of the seventh transistor is connected to the second node, a first electrode of the seventh transistor is connected to the output terminal, and a second electrode of the seventh transistor is connected for the inactive level of the output terminal.

For example, in the shift register unit provided by an embodiment of the present disclosure, the pull-down control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor, a gate electrode of the eighth transistor is connected to the first node, a first electrode of the eighth transistor is connected to the second node, and a second electrode of the eighth transistor is connected for the inactive level of the second node; a gate electrode of the ninth transistor is connected to a third node, a first electrode of the ninth transistor is connected to a second clock signal line, and a second electrode of the ninth transistor is connected to the second node; a gate electrode of the tenth transistor is connected to the first node, a first electrode of the tenth transistor is connected to the third node, and a second electrode of the tenth transistor is connected for a gate turn-off voltage; and a gate electrode of the eleventh transistor is connected to the second clock signal line, a first electrode of the eleventh transistor is connected to the second clock signal line, and a second electrode of the eleventh transistor is connected to the third node.

For example, in the shift register unit provided by an embodiment of the present disclosure, the input circuit includes a second transistor, the output circuit includes a third transistor and a first capacitor, the reset circuit includes a fourth transistor and a fifth transistor, the pull-down circuit includes a sixth transistor and a seventh transistor, and the pull-down control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor, a gate electrode of the second transistor is connected to the input terminal, a first electrode of the second transistor is connected to the input terminal or connected for the active level of the first node, and a second electrode of the second transistor is connected to the first node; a gate electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to a first clock signal line, and a second electrode of the third transistor is connected to the output terminal; a first terminal of the first capacitor is connected to the first node, and a second terminal of the first capacitor is connected to the output terminal; a gate electrode of the fourth transistor is connected to the reset terminal, a first electrode of the fourth transistor is connected to the first node, and a second electrode of the fourth transistor is connected for the inactive level of the first node; a gate electrode of the fifth transistor is connected to the reset terminal, a first electrode of the fifth transistor is connected to the output terminal, and a second electrode of the fifth transistor is connected for the inactive level of the output terminal; a gate electrode of the sixth transistor is connected to the second node, a first electrode of the sixth transistor is connected to the first node, and a second electrode of the sixth transistor is connected for the inactive level of the first node; a gate electrode of the seventh transistor is connected to the second node, a first electrode of the seventh transistor is connected to the output terminal, and a second electrode of the seventh transistor is connected for the inactive level of the output terminal; a gate electrode of the eighth transistor is connected to the first node, a first electrode of the eighth transistor is connected to the second node, and a second electrode of the eighth transistor is connected for the inactive level of the second node; a gate electrode of the ninth transistor is connected to a third node, a first electrode of the ninth transistor is connected to a second clock signal line, and a second electrode of the ninth transistor is connected to the second node; a gate electrode of the tenth transistor is connected to the first node, a first electrode of the tenth transistor is connected to the third node, and a second electrode of the tenth transistor is connected for a gate turn-off voltage; a gate electrode of the eleventh transistor is connected to the second clock signal line, a first electrode of the eleventh transistor is connected to the second clock signal line, and a second electrode of the eleventh transistor is connected to the third node; and the first clock signal line and the second clock signal line are respectively configured to transmitting one and other one of a positive phase clock signal and an inverted clock signal.

For example, the shift register unit provided by an embodiment of the present disclosure further includes an output noise reduction circuit; the output noise reduction circuit is respectively connected to the second clock signal line and the output terminal, and is configured to set the output terminal to an inactive level when the second clock signal line is at an active level.

For example, in the shift register unit provided by an embodiment of the present disclosure, the output noise reduction circuit includes the twelfth transistor, a gate electrode of the twelfth transistor is connected to the second clock signal line, a first electrode of the twelfth transistor is connected to the output terminal, and a second electrode of the twelfth transistor is connected for the inactive level of the output terminal.

For example, the shift register unit provided by an embodiment of the present disclosure further includes a pull-up control circuit, wherein the pull-up control circuit is respectively connected to the second clock signal line, the input terminal and the first node, and is configured to charge the first node or reduce noise of the first node.

For example, in the shift register unit provided by an embodiment of the present disclosure, the pull-up control circuit includes a thirteenth transistor, a gate electrode of the thirteenth transistor is connected to the second clock signal line, a first electrode of the thirteenth transistor is connected to the input terminal, and a second electrode of the thirteenth transistor is connected to the first node.

At least one embodiment of the present disclosure further provides a scan driving circuit, which includes a plurality of cascaded shift register units as provided by the embodiments of the present disclosure.

For example, in the scan driving circuit provided by an embodiment of the present disclosure, an input terminal of a shift register unit in each of remaining stages except for a first stage is connected to an output terminal of a shift register unit in a previous stage.

At least one embodiment of the present disclosure further provides an array substrate, which includes the scan driving circuit as provided by the embodiments of the present disclosure.

At least one embodiment of the present disclosure further provides a display device, which includes the array substrate as provided by the embodiments of the present disclosure.

At least one embodiment of the present disclosure further provides a driving method of the shift register unit, which includes that: in an input phase, by the input circuit, setting the first node to the active level when the input terminal is at the active level, and by the replacement circuit, setting the second node to the inactive level when the input terminal is at the active level; in an output phase, by the output circuit, setting the output terminal to the active level by using a clock signal when the first node is at the active level; and in a reset phase, by the pull-down circuit, setting the first node to the inactive level and the output terminal to the inactive level when the second node is at the active level.

