CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority to and benefits of Korean Patent Application No. 10-2020-0034543 under 35 U.S.C. § 119 filed on Mar. 20, 2020 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

BACKGROUND

1. Technical Field

Embodiments relate to a display device.

2. Description of the Related Art

A display device is a device displaying an image for providing visual information to a user. The display device may include pixels, and each of the pixels may include a light emitting element generating light and a pixel circuit providing a driving current to the light emitting element. The pixel circuit may include stacked conductive layers.

In the process of forming the conductive layers to form the pixel circuit, the conductive layers may be misaligned due to misalignment of a mask. In this case, capacitances between the conductive layers of pixel rows may not be uniform, therefore, kickback voltages of the pixel rows may not be uniform. Accordingly, stains may be recognized in the display device, and display quality of the display device may be reduced.

It is to be understood that this background of the technology section is, in part, intended to provide useful background for understanding the technology. However, this background of the technology section may also include ideas, concepts, or recognitions that were not part of what was known or appreciated by those skilled in the pertinent art prior to a corresponding effective filing date of the subject matter disclosed herein.

SUMMARY

Embodiments provide a display device having improved display quality.

A display device according to an embodiment may include a first transistor including a gate electrode disposed on a substrate; a second transistor including a lower gate electrode disposed on the substrate; an upper gate electrode disposed on the lower gate electrode; and a first end portion electrically connected to an end portion of the first transistor; a lower gate signal line extending in a first direction, a portion of the lower gate signal line forming the lower gate electrode; an upper gate signal line disposed on the lower gate signal line and extending in the first direction, a portion of the upper gate signal line forming the upper gate electrode; and a first connection pattern disposed on the upper gate signal line, electrically connecting the gate electrode and a second end portion of the second transistor, and intersecting the lower gate signal line and the upper gate signal line. An entirety of the upper gate signal line may overlap a part of the lower gate signal line in an overlapping area in which the lower gate signal line or the upper gate signal line may overlap the first connection pattern.

In an embodiment, a width of the upper gate signal line in a second direction may be less than a width of the lower gate signal line in the overlapping area in the second direction.

In an embodiment, a difference between the width of the lower gate signal line and the width of the upper gate signal line in the second direction may be greater than about 1 μm.

In an embodiment, the first connection pattern may extend in the overlapping area in the second direction.

In an embodiment, the widths of the first lower gate signal line both inside and outside of the overlapping area in the second direction may be substantially equal, and the widths of the first upper gate signal line both inside and outside of the overlapping area in the second direction may be substantially equal.

In an embodiment, the lower gate signal line may protrude in the second direction in the overlapping area in a plan view.

In an embodiment, the upper gate signal line may be recessed in the second direction in the overlapping area in a plan view.

In an embodiment, the first transistor may include a first active layer disposed between the substrate and the gate electrode; and the second transistor may include a second active layer disposed between the lower gate electrode and the upper gate electrode. A first end portion of the second active layer may be electrically connected to an end portion of the first active layer.

In an embodiment, the first active layer of the first transistor may include polycrystalline silicon, and the second active layer of the second transistor may include an oxide semiconductor.

In an embodiment, the first connection pattern may electrically connect the gate electrode and a second end portion of the second active layer of the second transistor.

In an embodiment, the display device may further include a second connection pattern electrically connecting the end portion of the first active layer and the first end portion of the second active layer, wherein the first connection pattern and the second connection pattern may be disposed on a same layer.

A display device according to an embodiment may include a first transistor including a gate electrode disposed on a substrate; a second transistor including a lower gate electrode disposed on the substrate; an upper gate electrode disposed on the lower gate electrode; and a first end portion electrically connected to an end portion of the first transistor; a lower gate signal line extending in a first direction, a portion of the lower gate signal line forming the lower gate electrode; an upper gate signal line disposed on the lower gate signal line and extending in the first direction, a portion of the upper gate signal line forming the upper gate electrode; and a first connection pattern disposed on the upper gate signal line, electrically connecting the gate electrode and a second end portion of the second transistor, and intersecting the lower gate signal line and the upper gate signal line. An entirety of the lower gate signal line may overlap a part of the upper gate signal line in an overlapping area in which the lower gate signal line or the upper gate signal line may overlap the first connection pattern.

In an embodiment, a width of the upper gate signal line in a second direction may be greater than a width of the lower gate signal line in the overlapping area in the second direction.

In an embodiment, a difference between the width of the upper gate signal line and the width of the lower gate signal line in the second direction may be greater than about 1 μm.

In an embodiment, the first connection pattern may extend in the overlapping area in the second direction.

In an embodiment, the widths of the first lower gate signal line both inside and outside of the overlapping area in the second direction may be substantially equal, and the widths of the first upper gate signal line both inside and outside of the overlapping area in the second direction may be substantially equal.

In an embodiment, the lower gate signal line may be recessed in the second direction in the overlapping area in a plan view.

In an embodiment, the upper gate signal line may protrude in the second direction in the overlapping area in a plan view.

In an embodiment, the first transistor may include a first active layer disposed between the substrate and the gate electrode, and the second transistor may include a second active layer disposed between the lower gate electrode and the upper gate electrode, a first end portion of the second active layer being electrically connected to an end portion of the first active layer.

In an embodiment, the first active layer of the first transistor may include polycrystalline silicon, and the second active layer of the second transistor may include an oxide semiconductor.

In an embodiment, the first connection pattern may electrically connect the gate electrode and a second end portion of the second active layer of the second transistor.

In an embodiment, the display device may further include a second connection pattern electrically connecting the end portion of the first active layer and the first end portion of the second active layer, wherein the first connection pattern and the second connection pattern may be disposed on a same layer.

In the display device according to the embodiments, an entirety of the upper gate signal line may overlap a part of the lower gate signal line, or an entirety of the lower gate signal line may overlap a part of the upper gate signal line in the overlapping area in which the lower gate signal line or the upper gate signal line may overlap the first connection pattern, so that a capacitance between the lower gate signal line and the first connection pattern and a capacitance between the upper gate signal line and the first connection pattern may be constantly maintained. Accordingly, a kickback voltage of the first connection pattern due to a gate signal applied to the lower gate signal line and the upper gate signal line may be constant. Further, stains may not occur in the display device, therefore, display quality of the display device may be improved.

