CROSS REFERENCE TO RELATED APPLICATIONS

This application is the National Stage of PCT/CN2019/079171 filed on Mar. 22, 2019, the disclosure of which is incorporated by reference.

TECHNICAL FIELD

Embodiments of the present disclosure relate to a shift register unit, a driving circuit, a display device, and a driving method.

BACKGROUND

In the field of display technology, in order to improve the quality of the display image and the user experience, the realization of high PPI (Pixels Per Inch) and narrow bezel has gradually become a research direction. In recent years, with the continuous improvement of the manufacturing process of amorphous silicon thin film transistors or oxide thin film transistors, a driving circuit can be directly integrated on an array substrate of the thin film transistor to form a GOA (Gate driver On Array) to drive the display panel. The GOA technology helps to realize the narrow bezel design of the display panel and can reduce the production cost of the display panel.

SUMMARY

At least an embodiment of the present disclosure provides a shift register unit, comprising a first input circuit, a second input circuit, an output circuit, a first control circuit, and a second control circuit. The first input circuit is electrically connected to a first node, and is configured to transmit an input signal to the first node under control of a first clock signal; the second input circuit is electrically connected to the first node and a second node, and is configured to control a level of the second node under control of a level of the first node or the first clock signal; the first control circuit is electrically connected to the second node and a third node, and is configured to control a level of the third node under control of the level of the second node and a second clock signal; the output circuit is electrically connected to the third node and an output terminal, and is configured to output an output signal to the output terminal under control of the level of the third node; and the second control circuit is electrically connected to the first node and the third node, and is configured to control the level of the third node under control of the level of the first node.

For example, the shift register unit provided by an embodiment of the present disclosure further comprises an output reset circuit, the output reset circuit is electrically connected to the first node and the output terminal, and is configured to reset the output terminal under control of the level of the first node.

For example, the shift register unit provided by an embodiment of the present disclosure further comprises a third control circuit, the third control circuit is electrically connected to the first node, and is configured to adjust, by coupling, the level of the first node under control of the level of the first node.

For example, in the shift register unit provided by an embodiment of the present disclosure, the first input circuit comprises a first transistor, a gate electrode of the first transistor is configured to receive the first clock signal, a first electrode of the first transistor is configured to receive the input signal, and a second electrode of the first transistor is electrically connected to the first node.

For example, in the shift register unit provided by an embodiment of the present disclosure, the second input circuit comprises a second transistor and a third transistor, a gate electrode of the second transistor is electrically connected to the first node, a first electrode of the second transistor is configured to receive the first clock signal, and a second electrode of the second transistor is electrically connected to the second node; and a gate electrode of the third transistor is configured to receive the first clock signal, a first electrode of the third transistor is configured to receive a first low voltage, and a second electrode of the third transistor is electrically connected to the second node.

For example, in the shift register unit provided by an embodiment of the present disclosure, the first control circuit comprises a fourth transistor, a fifth transistor, and a first capacitor; a gate electrode of the fourth transistor is electrically connected to the second node, a first electrode of the fourth transistor is configured to receive the second clock signal, and a second electrode of the fourth transistor is electrically connected to a fourth node; a gate electrode of the fifth transistor is configured to receive the second clock signal, a first electrode of the fifth transistor is electrically connected to the fourth node, a second electrode of the fifth transistor is electrically connected to the third node; and a first electrode of the first capacitor is electrically connected to the second node, and a second electrode of the first capacitor is electrically connected to the fourth node.

For example, in the shift register unit provided by an embodiment of the present disclosure, the second control circuit comprises a sixth transistor, a gate electrode of the sixth transistor is electrically connected to the first node, a first electrode of the sixth transistor is configured to receive a first high voltage, and a second electrode of the sixth transistor is electrically connected to the third node.

For example, in the shift register unit provided by an embodiment of the present disclosure, the output circuit comprises a seventh transistor and a second capacitor, a gate electrode of the seventh transistor is electrically connected to the third node, a first electrode of the seventh transistor is configured to receive a second high voltage, and a second electrode of the seventh transistor is electrically connected to the output terminal; and a first electrode of the second capacitor is electrically connected to the third node, and a second electrode of the second capacitor is electrically connected to the first electrode of the seventh transistor.

For example, in the shift register unit provided by an embodiment of the present disclosure, the output reset circuit comprises an eighth transistor, a gate electrode of the eighth transistor is electrically connected to the first node, a first electrode of the eighth transistor is configured to receive a second low voltage, and a second electrode of the eighth transistor is electrically connected to the output terminal.

For example, in the shift register unit provided by an embodiment of the present disclosure, the third control circuit comprises a ninth transistor and a third capacitor, a gate electrode of the ninth transistor is electrically connected to the first node, a first electrode of the ninth transistor is configured to receive the second clock signal, a second electrode of the ninth transistor is electrically connected to a first electrode of the third capacitor, and a second electrode of the third capacitor is electrically connected to the first node.

At least an embodiment of the present disclosure further provides a driving circuit, comprising a plurality of cascaded shift register units each of which is provided by any one of the embodiments of the present disclosure, except a first-stage of the shift register units, any one of the shift register units of other stages is connected with the output terminal of a shift register unit of a preceding stage before the any one of the shift register units of other stages.

For example, the driving circuit provided by an embodiment of the present disclosure further comprises a first clock signal line and a second clock signal line, a (2n−1)th-stage of the shift register units is electrically connected to the first clock signal line to receive the first clock signal, and the (2n−1)th-stage of the shift register units is electrically connected to the second clock signal line to receive the second clock signal; a (2n)th-stage of the shift register units is electrically connected to the second clock signal line to receive the first clock signal, and the (2n)th-stage of the shift register units is electrically connected to the first clock signal line to receive the second clock signal; and n is an integer greater than zero.

At least an embodiment of the present disclosure further provides a display device, comprising the driving circuit provided by any one of the embodiments of the present disclosure.

For example, the display device provided by an embodiment of the present disclosure further comprises a plurality of pixel units arranged in an array, each of the plurality of pixel units comprises a pixel circuit, the pixel circuit comprises a data writing sub-circuit, a driving sub-circuit, and a light-emitting control sub-circuit; an output terminal of an (n)th-stage of the shift register units in the driving circuit is electrically connected to a control terminal of the light-emitting control sub-circuit of the pixel circuit in an (n)th row of the pixel units; and n is an integer greater than zero.

At least an embodiment of the present disclosure further provides a driving method of the shift register unit, comprising a preliminary stage, a pull-up stage, a high-potential maintenance stage, a pull-down stage, and a low-potential maintenance stage, in the preliminary stage, causing the second clock signal to be changed from a low level to a high level, causing the input signal to be changed from a low level to a high level, and causing the level of the first node to be pulled up; in the pull-up stage, causing the second clock signal to be changed from a high level to a low level, causing the level of the third node to be pulled down, and causing a level of the output signal to be pulled up; in the high-potential maintenance stage, causing the second clock signal to be changed from a low level to a high level, causing the level of the first node to be maintained at a high level, causing the level of the output signal to be maintained at a high level, and adjusting a pulse width of the output signal by adjusting a pulse width of the input signal; in the pull-down stage, causing the first clock signal to be changed from a high level to a low level, causing the level of the first node to be pulled down, causing the level of the third node to be pulled up, and causing the level of the output signal to be pulled down; and in the low-potential maintenance stage, causing the level of the first node to be maintained at a low level, causing the level of the third node to be maintained at a high level, and causing the level of the output signal to be maintained at a low level.

For example, in the driving method provided by an embodiment of the present disclosure, adjusting the pulse width of the output signal by adjusting the pulse width of the input signal comprises: in a case where the pulse width of the output signal needs to be increased, causing the high level of the input signal to be maintained to a time point, in a next period of the first clock signal, when the first clock signal is at a high level, thereby causing the pulse width of the output signal to be delayed by one period of the first clock signal.

For example, in the driving method provided by an embodiment of the present disclosure, a duty cycle of the first clock signal and a duty cycle of the second clock signal are both greater than 50%.

