FIELD

Embodiments of the present disclosure relate to transistor structures and methods for forming these transistor structures.

BACKGROUND

Compared with conventional power devices made of silicon, Group III-Nitride (III-N) semiconductors possess excellent electronic properties that enable the fabrication of modern power electronic devices and structures for use in a variety of applications. The limited critical electric field and relatively high resistance of silicon make currently available commercial power devices, circuits and systems constrained with respect to operating frequencies. On the other hand, the higher critical electric field and higher electron density and mobility of III-N materials allow high-current, high-voltage, high-power and/or high-frequency performance of improved power transistors. These attributes are desirable in advanced transportation systems, high-efficiency electricity generation and conversion systems, and energy delivery networks. Such systems rely on efficient power converters to modify electric voltages, and use power transistors capable of blocking large voltages and/or carrying large currents. For example, power transistors with blocking voltages of more than 500V are used in hybrid vehicles to convert DC power from the batteries to AC power. Some other exemplary applications of power transistors include power supplies, automotive electronics, automated factory equipment, motor controls, traction motor drives, high voltage direct current (HVDC) electronics, lamp ballasts, telecommunication circuits and display drives.

Conventional III-nitride semiconductor transistors have planar structures. Due to the polarization property of III-nitride semiconductors, two-dimensional-electron-gas (2DEG) is formed at the AlGaN/GaN heterojunction interface.

It would be beneficial if there were a transistor structure that included a stress layer outside the gate recess region to allow modulation of the characteristics of the transistor.

SUMMARY

A new transistor structure is disclosed. This new structure has a dielectric stress layer in a three-dimensional structure outside of the gate recess region for modulation or the characteristics of the transistor. Additionally, trenches are created in the region between the source electrode and the drain electrode in such a manner so as to create ridges that traverse the gate recess region.

According to one embodiment, a semiconductor structure for use in a III-Nitride (III-N) semiconductor device is disclosed. The semiconductor structure comprises a semiconductor layer comprising a first III-N material for providing electrical conduction; a barrier layer comprising a second III-N material; a source electrode and a drain electrode disposed in ohmic recesses in contact with the barrier layer; a trench region defined between the source electrode and the drain electrode, wherein trenches are etched into portions of the barrier layer between the source electrode and the drain electrode, wherein ridges are created between the trenches, wherein the ridges comprise the semiconductor layer and the barrier layer and extend from an area near the source electrode to an area near the drain electrode and traverse the trench region; a gate recess region defined in the trench region, wherein the gate recess region is narrower than the trench region such that the trenches are disposed on both sides of the gate recess region; a dielectric layer, wherein the dielectric layer fills at least a portion of the trenches and covers the barrier layer outside the gate recess region, and wherein a thickness of the dielectric layer in the gate recess region is less than in other areas; and a gate electrode disposed in the gate recess region, wherein the gate electrode is formed over the ridges. In certain embodiments, the dielectric layer has compressive or tensile stress. In some embodiments, the dielectric layer comprises a plurality of sublayers, wherein at least one of the sublayers has compressive or tensile stress. In some embodiments, a magnitude of the compressive or tensile stress is greater than 10 MPascal. In certain embodiments, the dielectric layer is selected from SixNy, SiO2, SiOxNy, Al2O3, and AlN. In some embodiments, the dielectric layer fills an entirety of the trenches between the ridges outside of the gate recess region. In some embodiments, the dielectric layer is absent in the gate recess region. In some embodiments, the gate electrode fills the gate recess region and an upper portion of the gate electrode is wider than the gate recess region. In some further embodiments, the upper portion of the gate electrode is narrower than the trench region. In certain embodiments, a gate dielectric material is disposed beneath the gate electrode. In some embodiments, a depth of the trenches is greater than a thickness of the barrier layer such that the trench extends into the semiconductor layer. In other embodiments, a depth of the trenches is less than a thickness of the barrier layer such that the trench does not extend into the semiconductor layer.

According to another embodiment, a method of manufacturing a semiconductor structure is disclosed. The method comprises providing a wafer having a substrate, a semiconductor layer disposed on the substrate and a barrier layer disposed on the semiconductor layer; etching the barrier layer to form trenches, wherein ridges are created between adjacent trenches, the ridges traversing a gate region of the semiconductor structure; depositing a dielectric layer over the wafer after the etching; removing at least a portion of the dielectric layer in the gate region to form a gate recess region; forming a gate electrode in the gate recess region after removing at least a portion of the dielectric layer; creating ohmic recesses on both sides of the gate region; and forming a source electrode and a drain electrode in the ohmic recesses. In certain embodiments, the dielectric layer has compressive or tensile stress.

According to another embodiment, a semiconductor structure for use in a III-Nitride (III-N) semiconductor device is disclosed. The semiconductor structure comprises a semiconductor layer comprising a first III-N material for providing electrical conduction; a barrier layer comprising a second III-N material; a source electrode and a drain electrode disposed in ohmic recesses in contact with the barrier layer; a trench region defined between the source electrode and the drain electrode, wherein trenches are etched into portions of the barrier layer between the source electrode and the drain electrode, wherein ridges are created between the trenches, wherein the ridges comprise the semiconductor layer and the barrier layer and extend from an area near the source electrode to an area near the drain electrode and traverse the trench region; a plate recess region defined in the trench region, wherein the plate recess region is narrower than the trench region such that the trenches are disposed on both sides of the plate recess region; a dielectric layer, wherein the dielectric layer fills at least a portion of the trenches and covers the barrier layer outside the plate recess region, and wherein a thickness of the dielectric layer in the plate recess region is less than in other areas; a field plate disposed in the plate recess region, wherein the field plate is formed over the ridges; and a gate electrode disposed in a recess in the barrier layer between the field plate and the source electrode. In certain embodiments, the dielectric layer has compressive or tensile stress. In some embodiments, the dielectric layer comprises a plurality of sublayers, wherein at least one of the sublayers has compressive or tensile stress. In some embodiments, a magnitude of the compressive or tensile stress is greater than 10 MPascal. In certain embodiments, a gate dielectric material is disposed beneath the gate electrode. In certain embodiments, a dielectric material is disposed beneath the field plate.

