CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit under 35 USC 119(a) of Korean Patent Application No. 10-2020-0104613 filed on Aug. 20, 2020 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.

BACKGROUND

1. Field

The following description relates to a semiconductor device having a vertical DMOS structure.

2. Description of Related Art

The process of manufacturing several semiconductor devices on a single semiconductor substrate at once may require a considerable cost. This cost may be incurred because dozens of masks may be used for manufacturing each device, and dozens of lithography and etching processes may also be involved. A key to producing cheaper semiconductor devices or chips may be to reduce the number of these processes. Bipolar-CMOS-DMOS (BCD) technology corresponds to this, among the processes of manufacturing several semiconductor devices on a single semiconductor substrate at once.

In recent years, with the development of BCD technology, a Double-Diffused Metal-Oxide-Semiconductor (DMOS) transistor and a Complementary Metal-Oxide-Semiconductor (CMOS) transistor, which are high voltage power MOS transistor devices, may be configured together on a single IC chip. When a DMOS transistor and a CMOS transistor are combined and integrated into a single IC chip, it may be possible to provide design diversity, improved performance, and reliability, and also may be possible to reduce overall system manufacturing costs.

Typically, in semiconductor devices using BCD technology, DMOS devices may still be manufactured using a lateral type structure. However, when the DMOS device is manufactured in a lateral type, there may be a problem in that the degree of integration may be disadvantageous due to lateral diffusion of the semiconductor device. Also, there may be a limit in increasing the channel density because current may flow in the horizontal direction.

SUMMARY

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In one general aspect, a semiconductor device includes a substrate, a buried doped layer formed on the substrate, a trench gate formed on the buried doped layer, a source region formed adjacent the trench gate, an interlayer dielectric layer formed on the trench gate and the source region, a source contact plug formed to extend and connect to the source region, and a drain contact plug, extending and connecting to the buried doped layer, formed deeper than the source contact plug.

The drain contact plug may be deeper than a bottom surface of the trench gate.

The drain contact plug may be formed to extend from the interlayer dielectric layer to the buried doped layer.

A width of the drain contact plug may be greater than a width of the trench gate.

A width of the drain contact plug may be greater than a width of the source contact plug.

The device further may further include a drift region formed on the buried doped layer, a body region formed in the drift region, a body contact region formed in the body region, a source metal wiring connected to the source contact plug, and a drain metal wiring connected to the drain contact plug. The drain contact plug may be formed to extend through the body region and the drift region, and extend to the buried doped layer.

The drain contact plug may be formed in a drain contact hole.

The device may further include a middle trench filled with a gap-fill dielectric material to surround the drain contact plug, and directly contact the buried doped layer.

The device may further include a shallow trench having a depth shallower than a depth of the middle trench, and a deep trench having a depth deeper than the depth of the middle trench. The shallow trench may be filled with a gap-fill dielectric material, and the deep trench may be filled with the interlayer dielectric layer.

The deep trench may be formed deeper than the buried doped layer, and an air gap may be formed in the deep trench.

The buried doped layer may be used as a drain region. The semiconductor device may be a vertical DMOS device, and a movement path of electrons may be formed in a vertical direction to the surface of the substrate.

The trench gate may surround the drain contact plug.

The source contact plug may include a plurality of source contact plugs, and in a plan view, the plurality of source contact plugs may surround the drain contact plug, and the drain contact plug may be located at the center of the plurality of source contact plugs.

The device may further include a Complementary Metal-Oxide-Semiconductor (CMOS) device, an extended drain MOS (EDMOS) device, and a bipolar junction transistor (BJT) device on the substrate.

In another general aspect, a method of manufacturing a semiconductor device includes forming a trench gate formed in a substrate, forming a source region adjacent the trench gate, forming an interlayer dielectric layer on the trench gate and the source region, forming a drain contact plug by etching the interlayer dielectric layer and the substrate, forming a source contact plug connected to the source region by etching the interlayer dielectric layer, wherein the drain contact plug is formed deeper than the source contact plug.

The method may further include forming a middle trench in the substrate, and forming a gap-fill dielectric material in the middle trench. The drain contact plug may be formed in the gap-fill dielectric material.

The forming of the drain contact plug may include forming a drain contact mask pattern on the interlayer dielectric layer, etching the interlayer dielectric layer by using the drain contact mask pattern, forming a drain contact hole by etching a gap-fill dielectric material in the middle trench, and filling the drain contact hole with a metal material.

The method may further include forming a buried doped layer on the substrate. The drain contact plug may be formed to extend from the interlayer dielectric layer to the buried doped layer.

The method may further include forming a drift region on the buried doped layer, forming a body region in the drift region, forming a body contact region in the body region, and forming a source metal wiring connected to the source contact plug and a drain metal wiring connected to the drain contact plug.

The method may further include forming a shallow trench in the substrate, and forming a deep trench in the substrate. A depth of a bottom surface of the drain contact plug may be located between a bottom surface of the shallow trench and a bottom surface of the deep trench.

The deep trench may be filled with the interlayer dielectric layer, and an air gap may be formed in the deep trench.

The method may further include forming a Complementary Metal-Oxide-Semiconductor (CMOS) device, an extended drain MOS (EDMOS) device, and a bipolar junction transistor (BJT) device on the substrate.

The drain contact plug may extend through the body region and the drift region and extend to the buried doped layer.

In another general aspect, a semiconductor device includes a buried doped layer formed on a substrate, a drift region and a trench gate formed on the buried doped layer, a body region formed in the drift region, and a drain contact plug formed to extend through the body region and the drift region and extend to the buried doped layer.

The device may further include a source region and a body contact region formed in the body region, an interlayer dielectric layer formed on the trench gate, a source contact plug connected to the source region. A length of the drain contact plug may be formed to be longer than a length of the source contact plug.

The device may further include a source metal wiring formed on the interlayer dielectric layer and connected to the source contact plug, and a drain metal wiring formed on the interlayer dielectric layer and connected to the drain contact plug.

The drain contact plug may be formed starting from the interlayer dielectric layer and extended to the buried doped layer.

In another general aspect, a semiconductor device includes a buried doped layer formed between a substrate and an interlayer dielectric layer, source contact plugs each formed to extend and connect to a source region, a drain contact plug formed, deeper than the source contact plugs, between adjacent ones to the source contact plugs to extend and connect to the buried doped layer, and trench gates each opposingly formed about the drain contact plug. One of the trench gates is formed between the drain contact plug and one of the source contact plugs and another of the trench gates is formed between the drain contact plug and another of the source contact plugs.

The device may further include an interlayer dielectric layer formed on the trench gates and the source region. The source region may be formed adjacent the one of the trench gates.

The device may further include a drift region formed on the buried doped layer, a body region formed in the drift region, and a body contact region formed in the body region. The drain contact plug may be formed to extend to the buried doped layer through the body region and the drift region.

Other features and aspects will be apparent from the following detailed description, the drawings, and the claims.

