TECHNICAL FIELD

The present application relates to semiconductor devices and circuits, and more particularly, to analog, digital and mixed signal integrated circuits (ICs) that employ Super Complementary Metal-Oxide-Semiconductor (SCMOS™) devices and thereby exhibit improved device performance due to improvements in power consumption, operating speed, circuit area and device density.

BACKGROUND

Since the introduction of integrated circuits (ICs), engineers have been trying to increase the density of circuits on ICs, which reduces the cost of manufacturing of said ICs. One approach has been to put more components/functionality onto a chip. A second approach has been to build more chips on a larger wafer to reduce IC costs. For example, silicon wafer sizes have grown from averaging 3 inches in diameter in the 1960s to 12 inches today.

Various attempts were tried in the past to improve IC functionality, performance, and cost figures. Early IC implementations used bipolar junction transistors (BJTs), which have layers of various diffusion regions stacked vertically, and isolated transistor pockets containing the three switching terminals (base, emitter and collector), among other resistive (R) and capacitive (C) circuit elements. However, for the last decade of IC implementations, it was V-I signal and PHY parameter scaling that was used to house more components on a chip.

CMOS technology came after and surpassed BJT technology, which was relatively bulky, provided poor transistor yield, and exhibited high DC power usage. Device complexity has grown to over billions of circuit elements with Complementary MOS (CMOS) constructs. For more than 30 years a reduction in cost and increase in performance of CMOS technology has been achieved by shrinking the physical dimensions of CMOS transistors. These dimensions have shrunken to a size that is only a few molecular layers thick in critical device parameters. However, further shrinking of CMOS is running against limits imposed by the laws of physics. In addition to trying to manufacture tens of billions of these CMOS circuit elements with “molecular” dimensions, these dramatically smaller circuits operate with very low signal (voltage) levels, making their signal integrity susceptible to noise and causing speed degradation, and or power/heat run-off.

SUMMARY

In various embodiments, Schottky-CMOS (also referred to herein as “Super CMOS” and SCMOS™) technology is employed to build circuit blocks using Schottky Barrier diodes (SBDs), such as low threshold Schottky Barrier Diodes (LtSBD™s), thereby addressing the above deficiencies and problems associated with an increasing demand for higher semiconductor efficiency and upcoming physical limits on CMOS transistor dimensions.

In some embodiments, an integrated circuit implements a NAND gate system.

The integrated circuit includes a first input coupled to a cathode of a first p-type Schottky diode and x additional inputs coupled to x respective cathodes of x additional p-type Schottky diodes. The integrated circuit additionally includes a first n-type transistor including a gate node that is coupled to an anode of the first Schottky diode and x respective anodes of the x additional Schottky diodes. The integrated circuit additionally includes a p-type transistor including a gate node that is coupled to the anode of the first Schottky diode and x respective anodes of the x additional Schottky diodes. The integrated circuit additionally includes a second n-type transistor including a gate node that is coupled to the cathode of the first p-type Schottky diode and x additional n-type transistors including x respective gate nodes that are coupled to the x respective cathodes of the x additional p-type Schottky diodes. An output is coupled to a non-gate node of the first n-type transistor and a non-gate node of the p-type transistor.

In some embodiments, an integrated circuit implements a NOR gate system. The integrated circuit includes a first input coupled to an anode of a first n-type Schottky diode and x additional inputs coupled to x respective anodes of x additional n-type Schottky diodes. The integrated circuit additionally includes a first p-type transistor including a gate node that is coupled to a cathode of the first n-type Schottky diode and a cathode of x additional n-type Schottky diodes. The integrated circuit additionally includes an n-type transistor including a gate node that is coupled to the cathode of the first n-type Schottky diode and the cathodes of the x additional n-type Schottky diodes. The integrated circuit additionally includes a second p-type transistor including a gate node that is coupled to the anode of the first n-type Schottky diode and x additional p-type transistors including x respective gate nodes that are coupled to the x respective anodes of the x additional n-type Schottky diodes. An output is coupled to a non-gate node of the first p-type transistor and a non-gate node of the n-type transistor.

In some embodiments, an integrated circuit implements an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.

Various advantages of the disclosed technology will be apparent in light of the descriptions below.

