The contents of the following Japanese patent applications are incorporated herein by reference:NO. 2017-202228 filed in JP on Oct. 18, 2017, andNO. PCT/JP2018/038353 filed on Oct. 15, 2018.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor device.

2. Related Art

Conventionally, semiconductor devices such as insulated gate bipolar transistors (IGBTs) are known (see Patent Documents 1 and 2, for example).Patent Document 1: Japanese Patent Application Publication No. 2017-103400Patent Document 2: Japanese Patent Application Publication No. 2015-207736

It is preferable to prevent decrease in withstand capability in semiconductor devices.

SUMMARY

An aspect of the present invention provides a semiconductor device including a semiconductor substrate. The semiconductor device may include an active section provided in the semiconductor substrate and in which current flows between upper and lower surfaces of the semiconductor substrate. The semiconductor device may include a transistor section provided in the active section. The semiconductor device may include a gate metal layer electrically connected to the transistor section to supply a gate voltage to the transistor section. The semiconductor device may include a gate pad arranged on the upper surface of the semiconductor substrate and electrically connected to the gate metal layer. The semiconductor device may include a temperature-sensing unit provided on the upper surface of the semiconductor substrate and above the active section. The semiconductor device may include a temperature-measurement pad arranged on the upper surface of the semiconductor substrate and in a peripheral region between the active section and an outermost perimeter of the semiconductor substrate. The semiconductor device may include a temperature-sensing wire having a longitudinal portion extending in a predetermined longitudinal direction on the upper surface of the semiconductor substrate, and connecting the temperature-sensing unit and the temperature-measurement pad. On the upper surface of the semiconductor substrate, the gate pad may be arranged in a region other than an extending region that is an extension of the longitudinal portion of the temperature-sensing wire to the outermost perimeter of the semiconductor substrate in the longitudinal direction.

The gate pad may be arranged in the peripheral region. The semiconductor device may include an inner electrode formed of metal and provided more inside than the gate metal layer. The semiconductor device may include one or more voltage-supplying pads arranged in the peripheral region and electrically connected to the inner electrode. The gate pad and all the voltage-supplying pads may be arranged in a same one of two divided regions into which the peripheral region is halved by the longitudinal portion of the temperature-sensing wire and the extension of the longitudinal portion.

The temperature-measurement pad may be arranged in other one of the two divided regions than the divided region in which the gate pad and the voltage-supplying pads are arranged. The semiconductor device may include a diode section provided in the active section and arrayed alternately with the transistor section in a predetermined array direction on the upper surface of the semiconductor substrate. The semiconductor device may include a dummy gate metal layer electrically connected to the diode section to supply a dummy gate voltage to the diode section.

The gate metal layer may be provided to surround the active section in top view of the semiconductor substrate. The dummy gate metal layer may be provided inside the gate metal layer to surround the active section in top view of the semiconductor substrate.

One of the voltage-supplying pads provided in the same divided region as the gate pad may be a dummy gate pad electrically connected to the dummy gate metal layer. The inner electrode may be an emitter electrode, and one of the voltage-supplying pads provided in the same divided region as the gate pad may be a Kelvin pad electrically connected to the emitter electrode.

The gate metal layer may include an outer gate metal layer arranged in the peripheral region and an inner gate metal layer arranged above the active section and connected to the outer gate metal layer. The semiconductor device may include a gate runner containing a semiconductor material, provided above the semiconductor substrate in the active section, and having a first end connected to the inner gate metal layer and a second end connected to the inner gate metal layer or the outer gate metal layer. The inner electrode may include a first region and a second region separated by the inner gate metal layer and the gate runner in top view of the semiconductor substrate. The inner electrode may include a connecting region connecting the first region and the second region above the gate runner.

The dummy gate metal layer may include an outer dummy gate metal layer arranged in the peripheral region and an inner dummy gate metal layer arranged above the active section and connected to the outer dummy gate metal layer. The semiconductor device may include a dummy gate runner containing a semiconductor material, provided above the semiconductor substrate in the active section, and having a first end connected to the inner dummy gate metal layer and a second end connected to the inner dummy gate metal layer or the outer dummy gate metal layer. The inner electrode may include a first region and a second region separated by the inner dummy gate metal layer and the dummy gate runner in top view of the semiconductor substrate, and a connecting region connecting the first region and the second region above the dummy gate runner.

The longitudinal direction of the temperature-sensing wire may coincide with the array direction. The temperature-sensing unit may be disposed between two transistor sections, each being the transistor section, in top view of the semiconductor substrate.

The semiconductor device may include a gate runner containing a semiconductor material, provided in a region between the active section and the voltage-supplying pads in the peripheral region, and having first and second ends connected to the gate metal layer. In a direction connecting the first and second ends of the gate runner, a width between an end of the gate metal layer to which the first end of the gate runner is connected and an end of the gate metal layer to which the second end of the gate runner is connected may be larger than a width of the gate metal layer connected to the first end of the gate runner.

A part of the gate metal layer may be provided along the temperature-sensing wire.

A second aspect of the present invention provides a semiconductor device including a semiconductor substrate. The semiconductor device may include an active section provided in the semiconductor substrate and in which current flows between upper and lower surfaces of the semiconductor substrate. The semiconductor device may include a transistor section provided in the active section. The semiconductor device may include a gate metal layer electrically connected to the transistor section to supply a gate voltage to the transistor section. The semiconductor device may include a temperature-sensing unit provided on the upper surface of the semiconductor substrate and above the active section. The semiconductor device may include a temperature-measurement pad arranged on the upper surface of the semiconductor substrate and in a peripheral region between the active section and an outermost perimeter of the semiconductor substrate. The semiconductor device may include a temperature-sensing wire having a longitudinal portion extending in a predetermined longitudinal direction on the upper surface of the semiconductor substrate, and connecting the temperature-sensing unit and the temperature-measurement pad. A part of the gate metal layer may be provided along the temperature-sensing wire.

The summary clause does not necessarily describe all necessary features of the embodiments of the present invention. The present invention may also be a sub-combination of the features described above.

