CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2020-0063136 filed on May 26, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated by reference herein.

BACKGROUND

1. Technical Field

Various embodiments of the invention relate generally to an electronic device, and more particularly, to a semiconductor device and an operating method thereof.

2. Related Art

A storage device may store data in response to a host device, such as a computer or a smartphone. A storage device may include a memory device that stores data and a memory controller that controls the memory device. Memory devices may be divided into volatile memory devices and non-volatile memory devices.

A volatile memory device may retain data as long as power is being supplied and may lose the stored data in the absence of power. The types of volatile memory devices may include Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and the like.

A non-volatile memory device does not lose data even in the absence of power. The types of non-volatile memory devices may include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable and Programmable ROM (EEPROM) and flash memory.

SUMMARY

According to an embodiment, a memory device may include a cell string including a select transistor, a plurality of memory cells, and a plurality of dummy cells, wherein the plurality of dummy cells are coupled in series between the select transistor and the plurality of memory cells, a peripheral circuit configured to perform a dummy program operation on the plurality of dummy cells, and a control logic configured to control the peripheral circuit so that the plurality of dummy cells have different threshold voltage distributions during the dummy program operation.

According to an embodiment, a memory device may include a cell string including a select transistor, a plurality of memory cells, and a plurality of dummy cells, wherein the plurality of dummy cells are coupled in series between the select transistor and the plurality of memory cells, a peripheral circuit configured to perform a dummy program operation on the plurality of dummy cells, and a control logic configured to control the peripheral circuit so that a dummy cell that is closer to the plurality of memory cells has a lower threshold voltage than a dummy cell that is farther from the plurality of memory cells during the dummy program operation.

According to an embodiment, a method of operating a memory device including a select transistor, a plurality of memory cells, and a plurality of dummy cells, the plurality of dummy cells being coupled in series between the select transistor and the plurality of memory cells may include applying a dummy cell program voltage to a selected dummy word line among a plurality of dummy word lines that are coupled to the plurality of dummy cells, and applying a different range of dummy cell program verify voltages based on a distance between the selected dummy word line and the plurality of memory cells to the selected dummy word line.

According to an embodiment, a method of operating a memory device including a select transistor, a plurality of memory cells, and a plurality of dummy cells, the plurality of dummy cells being coupled in series between the select transistor and the plurality of memory cells, may include programming the plurality of dummy cells to have different threshold voltage distributions, applying a same voltage to a plurality of dummy word lines that are coupled to the plurality of dummy cells, and performing a normal program operation on the plurality of memory cells.

