BACKGROUND

1. Technical Field

Example embodiments relate generally to semiconductor memory devices, and more particularly to methods of erasing data in nonvolatile memory devices and nonvolatile memory devices performing the methods.

2. Description of the Related Art

Semiconductor memory devices can generally be divided into two categories depending upon whether or not they retain stored data when disconnected from a power supply. These categories include volatile memory devices, which lose stored data when disconnected from power, and nonvolatile memory devices, which retain stored data when disconnected from power. Volatile memory devices may perform read and write operations at a high speed, while contents stored therein may be lost at power-off. Nonvolatile memory devices may retain contents stored therein even at power-off, which means they may be used to store data that must be retained regardless of whether they are powered. Recently, semiconductor memory devices having memory cells that are stacked “vertically” (i.e., in three dimensions (3D)) have been researched to improve the capacity and integration density of the semiconductor memory devices.

SUMMARY

At least one example embodiment of the present disclosure provides a method of erasing data in a nonvolatile memory device that includes memory cells stacked in three dimensions capable of improving characteristics and reliability of a data erase operation.

At least one example embodiment of the present disclosure provides a nonvolatile memory device performing the method of erasing data.

According to example embodiments, a nonvolatile memory device includes a memory cell region, a peripheral circuit region. The memory cell region includes a memory block, and the peripheral circuit region includes a control circuit. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit determines whether a data erase characteristic for the memory block is degraded for each predetermined cycle of data erase operation, and performs a data erase operation by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.

According to example embodiments, a nonvolatile memory device includes a memory cell region and a peripheral circuit region. The memory cell region includes a memory block, and the peripheral circuit region includes a control circuit. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit determines whether a data erase characteristic for the memory block is degraded for each predetermined cycle of data erase operation, and performs a data erase operation by changing an amount of time during which a voltage is applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.

In the method of erasing data according to example embodiments and the nonvolatile memory device according to example embodiments, the data erase operation may be performed based on at least one of the first change operation and the second change operation when it is determined that the data erase characteristic is degraded. The first change operation may represent an operation of changing the level of the voltage applied to the selection transistors, and the second change operation may represent an operation of changing the time during which the voltage is applied to the selection transistors. Thus, the characteristic and reliability of the data erase operation may be improved or enhanced, and the nonvolatile memory device may have relatively extended lifetime.

