CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Section 371 National Stage Application of International Application No. PCT/CN2020/096856, filed Jun. 18, 2020, entitled “SHIFT REGISTER UNIT, DRIVING METHOD THEREOF, AND GATE DRIVING CIRCUIT,” which in turn claims priority to the Chinese Patent Application No. 201910534623.X filed on Jun. 19, 2019, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to the field of display technology, and in particular to a shift register unit, a driving method thereof, and a gate driving circuit.

BACKGROUND

In the field of display technology, for example, in a gate driving circuit of an OLED display device, a shift register unit is usually used to generate a scanning signal for scanning a corresponding row of pixel units on a display panel. A generation of an output signal of the shift register unit depends on potential of a pull-up node in the shift register. However, in practical applications, the potential of the pull-up node may be unstable due to various reasons, thereby affecting the output signal and further affecting display.

SUMMARY

The present disclosure provides a shift register unit, a driving method thereof, and a gate driving circuit.

According to an aspect of the present disclosure, there is provided a shift register unit, including:

an input circuit, coupled to a voltage stabilizer node and an input signal terminal of the shift register unit, and configured to receive an input signal from the input signal terminal and output the input signal to the voltage stabilizer node;

a voltage-stabilizing circuit, coupled to the voltage stabilizer node and a pull-up node of the shift register unit, and configured to input potential of the voltage stabilizer node to the pull-up node and control potential of the voltage stabilizer node under control of potential of the pull-up node;

an output circuit, coupled to the pull-up node and a clock signal terminal and an output signal terminal of the shift register unit, and configured to receive a clock signal from the clock signal terminal, and provide an output signal to the output signal terminal based on the clock signal received under control of the potential of the pull-up node; and

a control circuit, coupled to the pull-up node and the output signal terminal, and configured to control potential of the output signal terminal under control of the potential of the pull-up node.

For example, the voltage-stabilizing circuit includes:

a first transistor having a gate and a first electrode coupled to the voltage stabilizer node, and a second electrode coupled to the pull-up node; and

a second transistor having a gate coupled to the pull-up node, a first electrode coupled to a first power signal terminal, and a second electrode coupled to the voltage stabilizer node.

For example, the shift register unit further includes: a sensing circuit, coupled to a first control signal terminal, a second control signal terminal, the input signal terminal and the voltage stabilizer node, and configured to store a voltage under control of potential of the first control signal terminal and the input signal terminal, and input potential of the second control signal terminal to the voltage stabilizer node using the voltage stored.

For example, the sensing circuit includes a third transistor, a fourth transistor, a fifth transistor and a capacitor, wherein,

the third transistor has a gate coupled to the first control signal terminal, a first electrode coupled to the input signal terminal, and a second electrode coupled to a gate of the fourth transistor;

the fourth transistor has the gate coupled to the second electrode of the third transistor, a first electrode coupled to the second control signal terminal, and a second electrode coupled to a first electrode of the fifth transistor;

the fifth transistor has a gate coupled to the second control signal terminal, the first electrode coupled to the second electrode of the fourth transistor, and a second electrode coupled to the voltage stabilizer node; and

the capacitor has a first electrode coupled to the gate of the fourth transistor, and a second electrode coupled to the second electrode of the fourth transistor.

For example, the sensing circuit further includes:

a sixth transistor having a gate coupled to the first control signal terminal, a first electrode coupled to the second electrode of the third transistor, and a second electrode coupled to the gate of the fourth transistor, wherein the second electrode of the third transistor is coupled to the gate of the fourth transistor via the sixth transistor; and

a seventh transistor having a gate coupled to the gate of the fourth transistor, a first electrode coupled to the first power signal terminal, and a second electrode coupled to the second electrode of the third transistor.

For example, the input circuit includes an eighth transistor having a gate and a first electrode coupled to the input signal terminal and a second electrode coupled to the voltage stabilizer node.

For example, the control circuit includes:

a pull-down sub-circuit, coupled to the output signal terminal and a pull-down node of the shift register unit, and configured to control the potential of the output signal terminal under control of potential of the pull-down node; and

a pull-down control sub-circuit, coupled to the pull-up node, the pull-down node and a second power signal terminal, and configured to control the potential of the pull-down node under control of potential of the pull-up node and the second power signal terminal.

For example, the pull-down control sub-circuit includes a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor, wherein,

the ninth transistor has a gate and a first electrode coupled to the second power signal terminal, and a second electrode coupled to the pull-down node;

the tenth transistor has a gate coupled to the pull-up node, a first electrode coupled to a reference signal terminal, and a second electrode coupled to the pull-down node;

the eleventh transistor has a gate coupled to the pull-down node, a first electrode coupled to the voltage stabilizer node, and a second electrode coupled to the pull-up node; and

the twelfth transistor has a gate coupled to the pull-down node, a first electrode coupled to the reference signal terminal, and a second electrode coupled to the voltage stabilizer node.

For example, the shift register unit further includes: a reset circuit, coupled to the pull-up node and a reset signal terminal of the shift register unit, and configured to reset the pull-up node under control of potential of the reset signal terminal.

For example, the reset circuit includes:

a thirteenth transistor having a gate coupled to the reset signal terminal, a first electrode coupled to the voltage stabilizer node, and a second electrode coupled to the pull-up node; and

a fourteenth transistor having a gate coupled to the reset signal terminal, a first electrode coupled to the reference signal terminal, and a second electrode coupled to the voltage stabilizer node.

For example, the reset signal terminal includes a first reset signal terminal coupled to the thirteenth transistor and the fourteenth transistor, and a second reset signal terminal, and wherein the reset circuit further includes:

a fifteenth transistor having a gate coupled to the second reset signal terminal, a first electrode coupled to the voltage stabilizer node, and a second electrode coupled to the pull-up node; and

a sixteenth transistor having a gate coupled to the second reset signal terminal, a first electrode coupled to the reference signal terminal, and a second electrode coupled to the voltage stabilizer node.

According to another aspect of the present disclosure, there is provided a gate driving circuit including N stages of cascaded shift register units, where N is a natural number greater than 3.

According to another aspect of the present disclosure, there is provided a driving method of the shift register unit mentioned above, including:

in a first period, applying an input signal at a first level to an input signal terminal, wherein the input signal at the first level is output to a voltage stabilizer node by an input circuit, and potential of the voltage stabilizer node is input to a pull-up node by a voltage-stabilizing circuit;

in a second period, applying an input signal at a second level to the input signal terminal, wherein potential of the pull-up node causes an output circuit to provide a clock signal of a clock signal terminal to an output signal terminal; and

in a third period, applying a reset signal at the first level to a reset signal terminal of the shift register unit to reset the pull-up node, wherein the potential of the pull-up node causes a control circuit to pull down the output signal terminal to the second level,

wherein, in the first period and the second period, the potential of the pull-up node causes the voltage-stabilizing circuit to control potential of the voltage stabilizer node within a preset range.

