BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for producing a pillar-shaped semiconductor device.

2. Description of the Related Art

In these years, three-dimensional transistors have been used in LSI (Large Scale Integration). In particular, surrounding gate transistors (SGTs), which are pillar-shaped semiconductor devices, have been attracting attention as semiconductor elements that provide highly integrated semiconductor devices. There has been a demand for an SGT-including semiconductor device that has a higher degree of integration and a higher performance.

Ordinary planar MOS transistors have a channel that extends in a horizontal direction along the upper surface of the semiconductor substrate. By contrast, SGTs have a channel that extends in a direction perpendicular to the upper surface of the semiconductor substrate (for example, refer to Japanese Unexamined Patent Application Publication No. 2-188966 and Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol. 38, No. 3, pp. 573-578 (1991)). For this reason, compared with planar MOS transistors, SGTs enable an increase in the density of semiconductor devices.

FIG. 5is a schematic structural view of an N-channel SGT. A Si pillar100of a P or i (intrinsic) conductivity type (hereafter, silicon semiconductor pillars will be referred to as “Si pillars”) has, in its upper and lower portions, N+layers101aand101bone of which functions as a source and the other one of which functions as a drain (hereafter, semiconductor regions containing a donor impurity at a high concentration will be referred to as “N+layers”). A portion of the Si pillar100between the N+layers101aand101b, which function as a source and a drain, functions as a channel region102. Around this channel region102, a gate insulating layer103is formed. Around this gate insulating layer103, a gate conductor layer104is formed. In the SGT, the N+layers101aand101bfunctioning as the source and the drain, the channel region102, the gate insulating layer103, and the gate conductor layer104are formed so as to constitute a pillar. Thus, in plan view, the area occupied by the SGT corresponds to the area occupied by a single source-or-drain N+layer of a planar MOS transistor. Therefore, compared with a circuit chip including a planar MOS transistor, an SGT-including circuit chip enables a further reduction in the size of the chip.

In the SGT illustrated inFIG. 5, there has been a demand for a reduction in the resistance of N+layers101aand101bserving as the source and the drain. Such a reduction in the resistance of the N+layers101aand101benables a decrease in the power consumption of and an increase in the speed of the SGT-including circuit. There has been a demand for a higher degree of integration of an SGT-including circuit.

SUMMARY OF THE INVENTION

There has been a demand for a pillar-shaped semiconductor device having a higher density, a lower power consumption, and a higher speed.

A method for producing a pillar-shaped semiconductor device according to a first aspect of the present invention includes:

a step of forming a semiconductor pillar so as to stand on and in a direction perpendicular to a substrate;

a step of forming a gate insulating layer so as to surround the semiconductor pillar;

a step of forming a gate conductor layer so as to surround the gate insulating layer;

a step of forming a first impurity region that is located lower than, in the perpendicular direction, the gate insulating layer, that is in contact with a lower portion of the semiconductor pillar or a side surface of the lower portion, and that contains a donor or acceptor impurity; and

a step of forming a second impurity region that is located higher than, in the perpendicular direction, the gate insulating layer, that is located on a top portion of the semiconductor pillar, and that contains a donor or acceptor impurity,

wherein the step of forming the second impurity region includes a step of forming a first material layer so as to surround an outer periphery of the top portion of the semiconductor pillar, a step of etching the top portion of the semiconductor pillar through the first material layer serving as a mask, and a step of forming a recessed portion formed by the etching and located above the semiconductor pillar,

the method further including:

a step of forming a second material layer so as to surround an outer periphery of a side surface of the semiconductor pillar, the side surface being located lower than the gate insulating layer in the perpendicular direction; a step of etching the second material layer to form an opening portion in the side surface of the semiconductor pillar, the side surface being located lower than the gate insulating layer; and a step of simultaneously forming, in the recessed portion and the opening portion, the first impurity region and the second impurity region that contain donor or acceptor impurity atoms by a selective epitaxial crystal growth method.

More preferably, the second impurity region is formed so as to have an upper end located lower than the recessed portion.

More preferably, the method includes a step of forming a first conductor layer within the recessed portion so as to be in contact with an upper end of the second impurity region.

More preferably, the method includes:

a step of forming the semiconductor pillar by etching a semiconductor layer on the substrate through a mask material layer formed on the semiconductor layer and serving as a mask;

in the step of forming the first impurity region, a step of forming a third material layer on an entirety of a side surface of the semiconductor pillar; and

a step of performing oxidation through the mask material layer and the third material layer that serve as anti-oxidation masks to form an oxidized layer in a bottom portion of the semiconductor pillar and in a surface layer of the semiconductor layer, the surface layer being located in an outer peripheral region around the semiconductor pillar.

More preferably, the first impurity region is formed so as to have, in the perpendicular direction, a lower end separated from an upper end of the oxidized layer in the bottom portion of the semiconductor pillar.

More preferably, the method includes:

a step of forming a fourth material layer so as to surround, in plan view, a side surface of a bottom portion of the semiconductor pillar;

a step of forming a fifth material layer so as to be located on the fourth material layer, to surround, with a constant width in plan view, the semiconductor pillar, and to be constituted by a single layer or a plurality of layers in the perpendicular direction;

a step of etching, in the perpendicular direction, the fourth material layer through the fifth material layer serving as a mask;

a step of etching, in a horizontal direction, the fourth material layer through the fifth material layer serving as a mask, to form the opening portion through which a side surface of a lower portion of the semiconductor pillar is exposed; and

a step of forming, by a selective epitaxial crystal growth method, the first impurity region that extends, in plan view, outwardly from the side surface of the semiconductor pillar through the opening portion, and that contains a donor or acceptor impurity.

More preferably, the first impurity region is formed before the gate insulating layer is formed.

More preferably, the method includes:

a step of, after the first impurity region is formed, removing, with a constant width, an outer peripheral region around the semiconductor pillar, the outer peripheral region being located higher than, in the perpendicular direction, an upper end of the first impurity region; and a step of, after the removing step, forming the gate insulating layer.

More preferably, the method includes a step of, after the first impurity region and the second impurity region are formed, performing a heat treatment to diffuse a donor or acceptor impurity contained in the first impurity region into the semiconductor pillar to form a third impurity region and simultaneously to diffuse a donor or acceptor impurity contained in the second impurity region into the semiconductor pillar to form a fourth impurity region.

A method for producing a pillar-shaped semiconductor device according to a second aspect of the present invention includes:

a step of forming a semiconductor pillar so as to stand on and in a direction perpendicular to a substrate;

a step of forming a gate insulating layer so as to surround the semiconductor pillar;

a step of forming a gate conductor layer so as to surround the gate insulating layer;

a step of forming a first impurity region that is located lower than, in the perpendicular direction, the gate insulating layer, that is in contact with a lower portion of the semiconductor pillar or a side surface of the lower portion, and that contains a donor or acceptor impurity; and

a step of forming a second impurity region that is located higher than, in the perpendicular direction, the gate insulating layer, that is located on a top portion of the semiconductor pillar, and that contains a donor or acceptor impurity,

wherein the step of forming the first impurity region includes

a step of forming a first material layer so as to surround, in plan view, a side surface of a bottom portion of the semiconductor pillar;

a step of forming a second material layer so as to be located on the first material layer, to surround, with a constant width in plan view, the semiconductor pillar, and to be constituted by a single layer or a plurality of layers in the perpendicular direction;

a step of etching the first material layer through the second material layer serving as a mask, to form an opening portion through which a side surface of a lower portion of the semiconductor pillar is exposed; and

a step of forming, by a selective epitaxial crystal growth method, the first impurity region that extends, in plan view, outwardly from the side surface of the semiconductor pillar through the opening portion, and that contains a donor or acceptor impurity.

More preferably, the method includes:

a step of forming the semiconductor pillar by etching a semiconductor layer on the substrate through a mask material layer formed on the semiconductor layer and serving as a mask;

in the step of forming the first impurity region, a step of forming a third material layer on an entirety of a side surface of the semiconductor pillar; and

a step of performing oxidation through the mask material layer and the third material layer that serve as anti-oxidation masks to form an oxidized layer in a bottom portion of the semiconductor pillar and in a surface layer of the semiconductor layer, the surface layer being located in an outer peripheral region around the semiconductor pillar.

More preferably, the first impurity region is formed so as to have, in the perpendicular direction, a lower end separated from an upper end of the oxidized layer in the bottom portion of the semiconductor pillar.

More preferably, the first impurity region is formed before the gate insulating layer is formed.

More preferably, the method includes:

a step of, after the first impurity region is formed, removing, with a constant width, an outer peripheral region around the semiconductor pillar, the outer peripheral region being located higher than, in the perpendicular direction, an upper end of the first impurity region; and

a step of, after the removing step, forming the gate insulating layer.

More preferably, the method includes:

a step of performing, after the first impurity region is formed, a heat treatment to diffuse a donor or acceptor impurity contained in the first impurity region into the semiconductor pillar to form a third impurity region; and

a step of performing the heat treatment to diffuse the donor or acceptor impurity such that an upper end of the third impurity region in the perpendicular direction is located at a lower end of the outer peripheral region around the semiconductor pillar, the lower end being provided by the removing with the constant width.

More preferably, the second material layer includes the gate insulating layer, the gate conductor layer, and a fourth material layer surrounding a side surface of the gate conductor layer.

More preferably, the method includes a step of forming, in the perpendicular direction, a first insulating layer between the gate conductor layer and the first impurity region.

The present invention provides a pillar-shaped semiconductor device having a higher density, a lower power consumption, and a higher speed.

