FIELD

Disclosed embodiments relate to Error Correction Circuits (ECCs), and more particularly to hardware for fault detection of ECC logic circuitry.

BACKGROUND

Error correction code (ECC) memory is a type of computer data storage that can detect and correct most conventional types of internal data corruption. ECC memory circuits may be used in computers where data corruption cannot generally be tolerated, such as for scientific or for automotive memories for safety critical Advanced Driver Assistance Systems (ADAS) which need to comply with functional safety requirements.

Implementing ECC on memories (e.g., static random access memory (SRAM), read only memory (ROM), or flash memory) is a standard safety mechanism used in safety critical applications to ensure data integrity within the memories. Conventionally, ECC redundant bits (e.g., in a Hamming code) are added to the memory data contents by write path ECC logic circuitry and written together in the same cycle to the memory in order to provide checking of the data stored in the memory when the memory is read out by read path ECC logic circuitry. The ECC as used herein is for single bit error correction for single bit errors and a multi-bit error detection for multi-bit errors (e.g., double bit errors), generally using redundant bits in a Hamming code.

Conventionally generate ECC hardware units are provided in the write path and in the read path, with a generate ECC unit in the write path and a check ECC block including another generate ECC unit in the read path. The write path circuitry and read path circuitry have no cross coupling connections and thus operate independently from one another. During a memory read operation, the ECC is re-recomputed by the check ECC block which is compared with the stored ECC by an XOR circuit. The result (output) of this XOR circuit is called the syndrome. If the syndrome is zero, no error has occurred. If the syndrome is non-zero, it can be used to index a table to a “Syndrome decode” to determine which bits are in error in case of a single bit error correction (SEC), or that the error is uncorrectable in case of a double bit error detection (DED). Accordingly, conventional ECC memory can generally maintain a memory system effectively free from most bit errors.

SUMMARY

This Summary briefly indicates the nature and substance of this Disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Disclosed embodiments recognize there can be transient or permanent errors in the ECC logic hardware of ECC memory circuits in the write side which can result in wrong ECC bits being written into the memory during the write operation. Transient or permanent errors in the ECC logic hardware in the read side of ECC memory circuits can result in corruption of memory read data or in the wrong flagging of memory read data as corrupted when the read data is in fact not corrupted. Although it may be possible to detect transient/permanent errors in the ECC logic of ECC memory circuits, because the write path circuitry and read path circuitry are only known to operate independently this would require significant additional logic to implement including the need for extra ECC generation logic on both sides of the ECC memory circuit.

Disclosed embodiments solve this problem by providing lockstep ECC circuit hardware comprising an error correction circuit that utilizes cross-coupled connections between the write path circuitry and read path circuitry which enables the reuse of ECC generation logic on one side of the memory circuit to check for errors on the other side thus reducing the ECC logic requirement and saving significant semiconductor chip area. Disclosed embodiments include a method of fault detection for ECC circuitry for a memory circuit having write generation (Gen) ECC logic in a write path circuitry and check ECC logic including read Gen ECC logic in read path circuitry. An output of the read Gen ECC logic and an output of the write Gen ECC logic are compared by a digital comparator to check whether the respective bits strings match. A fault in the write Gen ECC logic or in the read Gen ECC logic is recognized when the bits strings do not match. In case of a lockstep error (mismatch in comparator output) during the write operation, the write operation can be repeated. In case of a lockstep error during the read operation, the single bit errors can be corrected and a multi-bit error interrupt signal sent.

