CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority benefit of Italian Application No. 102020000016393, filed on Jul. 7, 2020, which application is hereby incorporated herein by reference.

TECHNICAL FIELD

The description relates to digital signal processing circuits such as fast Fourier transform (FIT) processors, and associated methods.

BACKGROUND

Modern wideband communication systems based on Orthogonal Frequency Division Multiplexing (OFDM), such as Digital Video Broadcasting (DVB) and Digital Audio Broadcasting (DAB), or modern radar systems (as increasingly used, for instance, in the automotive sector) are exemplary of processing systems which involve the computation of fast Fourier transforms (FFTs) whose length (or size) can reach up to 8192 points, or even more.

Computation of fast Fourier transforms can be carried out by hardware-implemented FFT processors. A FFT processor may comprise one or more processing elements (PE), for instance radix-2 butterfly processing elements, and one or more read-only memories (ROM). The read-only memories in the FFT processor may be configured to store twiddle factors for fast Fourier transform computation.

In the case of long FIT algorithms which involve a high number of different twiddle factors, the ROM memories may represent a significant portion of the entire FFT processor (e.g., in terms of occupied silicon area).

The ROM memories may represent a significant portion of the FFT processor especially if the FFT processor relies on the use of parallel computation, i.e., in case the FFT processor comprises a plurality of processing elements and a respective plurality of ROM memories coupled thereto.

The twiddle factors are usually stored (e.g., hard-wired) in the ROM memories and retrieved for butterfly multiplication by means of ROM address generators (RAG) implemented inside the processing elements. The ROM address generators may provide the memory address where a required twiddle factor is stored.

If a plurality of processing elements is used in a FFT processor for parallel computation, a plurality of ROM lookup tables may be provided in the FFT processor (e.g., one dedicated ROM memory for each processing element) in order to avoid memory access conflicts when the processing elements access the ROM memories to fetch the twiddle factors.

Alternatively, complex conflict-free access schemes may be implemented, e.g., as disclosed by P. Jui, C. Wey and M. Shiue, “Low-cost parallel FFT processors with conflict-free ROM-based twiddle factor generator for DVB-T2 applications,” 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, Ohio, 2013, pp. 1003-1006, doi: 10.1109/MWSCAS.2013.6674821.

SUMMARY

An object of one or more embodiments is to contribute in providing a FFT processor having an efficient architecture for twiddle factor index generation (e.g., twiddle factor storage and fetching), e.g., in terms of trade-off between silicon area occupation and performance.

According to one or more embodiments, such an object can be achieved by means of a circuit (e.g., a digital signal processor) having the features set forth in the claims that follow.

One or more embodiments may relate to a corresponding method of operating the circuit.

The claims are an integral part of the technical teaching provided herein in respect of the embodiments.

One or more embodiments may rely on an advantageous scheme for storing twiddle factors in a ROM memory which may facilitate reducing the dimension of the ROM memory while avoiding memory access conflicts.

One or more embodiments may provide a corresponding ROM address generator which co-operates with a ROM controller circuit for fetching the twiddle factors from the ROM memory.

According to one or more embodiments, a circuit is provided which may comprise a plurality of processing units comprising a number P of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform, FFT, processing. The plurality of coefficient memory banks may comprise a number P of coefficient memory banks equal to the number P of processing units.

The circuit may be configured to apply fast Fourier transform processing having a size N, in the form N=2nwith n being an integer, to the data stored in the data memory banks. Applying fast Fourier transform processing having a size N may comprise processing the data in a plurality of FFT computation stages comprising a number n of FFT computation stages. Each FFT computation stage may comprise a number of FFT computation cycles.

The processing units may be configured to fetch (e.g., at each of the FFT computation stages) input data from the data memory banks with a burst read memory transaction, fetch (e.g., at each of the FFT computation cycles) a respective set of twiddle factors from the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store (e.g., at each of the FFT computation stages) the output data into the data memory banks with a burst write memory transaction.

The processing units may be configured to fetch, at each of the FFT computation cycles, different twiddle factors in the respective set of twiddle factors from different coefficient memory banks.

One or more embodiments may thus provide efficient twiddle factor index generation.

