FIELD

The present invention relates generally to integrated circuits, and, more particularly to a system for serializing and transmitting high speed data signals in the integrated circuits.

BACKGROUND

Typically, a wireline transmitter includes a digital circuit and a serializer circuit for providing an output data signal to a wireline. The digital circuit provides a parallel stream of input data signals to the serializer circuit. The serializer circuit converts the parallel stream of input data signals into a serial stream of output data signal and provides the serial stream of output data signal to the wireline. In one example, the digital circuit is a first-in-first-out (FIFO) memory that receives a clock signal and provides the parallel stream of input data signals when the clock signal is activated (also referred to as “launching the input data signals”).

In one example, a 2:1 serializer circuit is used to serialize two input data signals. The 2:1 serializer circuit includes a multiplexer and a latch. The multiplexer has a first input terminal connected to the FIFO memory to receive a first input data signal, a second input terminal connected to the FIFO memory by way of the latch to receive a second input data signal, and a select terminal to receive the clock signal. The FIFO memory launches the first and second input data signals at the same time instance. When the clock signal is deactivated, the latch latches the second input data signal and the multiplexer outputs the first input data signal. After half cycle of the clock signal, when the clock signal is activated, the latch provides the latched second input data signal, and the multiplexer outputs the latched second input data signal, thereby serializing the first and second input data signals. The timing interval between launching of the first and second input data signals by the FIFO memory and receiving of the first and second input data signals by the multiplexer is also referred to as a “critical path”. The critical path in the 2:1 serializer circuit is half cycle of the clock signal. Since, the FIFO memory launches the first and second input data signals at the same time instance, the 2:1 serializer circuit delays the second input data signal by half cycle of the clock signal to ensure that the first and second input data signals are outputted successively. Thus, the second input data signal is delayed to serialize the first and second input data signals. However, the delay of the second input data signal may introduce latency in the serializer circuit. Further, the multiplexer introduces additional delays due to set-up and hold time delays thereof because of which the critical path that is equal to half cycle of the clock signal is not sufficient to serialize high speed input data signals. Such a 2:1 serializer circuit provides incorrect input data signals. Moreover, a physical path between the FIFO memory and the 2:1 serializer circuit is large that further increases the time interval between outputting of the first and second input data signals by the FIFO memory, and receiving of the first and second input data signals by the 2:1 serializer circuit.

A known technique to overcome the aforementioned problems is to connect first and second flip-flops at the first and second input terminals of the multiplexer, respectively. The first and second flip-flops are placed in close proximity to the multiplexer. The first and second flip-flops receive the first and second input data signals, respectively, from the FIFO memory at the same time instance and launch the first and second input data signals, respectively, based on an external clock signal. Thus, the first and second flip-flops provide the first and second input data signals to the 2:1 serializer circuit based on the external clock signal. Since, the first and second flip-flops are placed in close proximity to the multiplexer, the time interval between outputting of the first and second input data signals by the first and second flip-flops, respectively, and receiving of the first and second input data signals by the serializer circuit is reduced. However, the first and second flip-flops introduce latency in the 2:1 serializer circuit which is undesirable. Further, as the first and second input data signals are launched at the same time instance, the critical path in such a 2:1 serializer circuit is half cycle of the external clock signal. Thus, for serializing high speed input data signals, the critical path is not sufficient.

Therefore, it would be advantageous to have an N:1 serializer circuit that has reduced latency in outputting launched input data signals, and that overcomes the aforementioned drawbacks of the existing serializer circuits.

