CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Taiwanese Application Serial No. 108129257, filed on Aug. 16, 2019. The entirety of the application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

1. Technical Field

The present disclosure relates to semiconductor packaging structures and methods for fabricating the same, and, more particularly, to an electronic package, an assemble substrate for the electronic package, and a method for fabricating the assemble substrate.

2. Description of the Prior Art

As technology evolves, electronic products are developed to have various types of components, and multichip module (MCM) and multichip package (MCP) come to the market, which integrate and package a plurality of chips into a single chip. The chip thus fabricated has a great number of I/O pins, increases the operation capability of a processor significantly, reduces the delay time of signal transmission, and can be applied to a high-level product, which has a high circuit density, high transmission speed, a large number of stacked layers, and a large size.

As shown inFIG. 1, in a method for fabricating a multichip packaging structure1according to the prior art, a plurality of semiconductor chips11are bonded via a plurality of solder bumps13to a packaging substrate10, an underfill12is formed between the semiconductor chips11and the packaging substrate10and encapsulates the solder bumps13, and a plurality of solder balls14are planted on a bottom side of the packaging substrate10for being disposed on a circuit board8of an electronic product.

The multichip packaging structure1does not have satisfied yield for the packaging substrate10of a large size, with layout area of 100·100 mm2, for example. The single packaging substrate10has an extremely high fabrication cost, and is not competitive in the market.

Therefore, how to overcome the drawbacks in the prior art is becoming an urgent issue in the art.

SUMMARY

In view of the drawbacks of the prior art, the present disclosure provides an assemble substrate, comprising: a plurality of circuit members spaced apart from one another; and at least one circuit portion stacked on and electrically connected to the plurality of circuit members, wherein the circuit portion has a first width less than or equal to a second width between two of the plurality of circuit members, with the second width being greater than a width between any other two of the plurality of circuit members.

In an embodiment, the circuit portion is disposed on both sides of the plurality of circuit members.

In an embodiment, the circuit members are stacked on and electrically connected via a plurality of conductive bodies to the circuit portion.

In an embodiment, the assemble substrate further comprises an encapsulation layer encapsulating the plurality of circuit members and the circuit portion. In another embodiment, the assemble substrate further comprises a functional component embedded in the encapsulation layer and surrounding the plurality of circuit members. In yet another embodiment, the functional component is exposed from the encapsulation layer.

In an embodiment, the plurality of circuit members are circuit boards.

In an embodiment, the assemble substrate is stacked on and electrically connected via a plurality of conductive bodies to an electronic component or a conductive element.

The present disclosure further provides a method for fabricating an assemble substrate, comprising: stacking a plurality of circuit members spaced apart from one another and at least one circuit portion on a carrying board, and electrically connecting the circuit portion to the plurality of circuit members, wherein the circuit portion has a first width less than or equal to a second width between two of the plurality of circuit members, with the second width being greater than a width between any other two of the plurality of circuit members; and removing the carrying board.

In an embodiment, the circuit portion is stacked on both sides of the plurality of circuit members.

In an embodiment, the circuit members are stacked on and electrically connected via a plurality of conductive bodies to the circuit portion.

In an embodiment, the method further comprises forming on the carrying board an encapsulation layer encapsulating the plurality of circuit members and the circuit portion. In another embodiment, the circuit members or the circuit portion are exposed from the encapsulation layer. In yet another embodiment, the assemble substrate has both sides exposed from the encapsulation layer and stacked on and electrically connected to via a plurality of conductive bodies an electronic component or a conductive element. In still another embodiment, the method further comprises, prior to forming an encapsulation layer, disposing on the carrying board a functional component surrounding the plurality of circuit members. In a further embodiment, the functional component is exposed from the encapsulation layer.

In an embodiment, the plurality of circuit members and the circuit portion are disposed by: placing the plurality of circuit members on the carrying board; and stacking the circuit portion on the plurality of circuit members.

In an embodiment, the plurality of circuit members and the circuit portion are disposed by: placing the circuit portion on the carrying board; and stacking the plurality of circuit members, with one side thereof, on the circuit portion. In another embodiment, the method further comprises stacking another circuit portion on the other side of the plurality of circuit members.

The present disclosure further provides an electronic package, which comprises: the aforementioned assemble substrate; and an electronic component disposed on one side of the assemble substrate and electrically connected to the assemble substrate.

In an embodiment, the electronic package further comprises a plurality of conductive elements disposed on the other side of the assemble substrate and electrically connected to the assemble substrate.

In the electronic package, the assemble substrate of the electronic package, and the method for fabricating the assemble structure according to the present disclosure, the plurality of circuit members are spaced apart from one another to increase a layout area. Compared to the prior art, the present disclosure meets the requirements for a packaging substrate of a large size, increases the yield, has an extremely low fabrication cost, and is very competitive in the market.

