CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 U.S.C. § 119 of Korean Patent Application No. 10-2020-0073733, filed on Jun. 17, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.

BACKGROUND

1. Field

The following description relates to memory devices for performing in-memory processing by using an in-memory operation unit.

2. Description of Related Art

Applications such as processing of a graphics algorithm, processing of a neural network, and the like are compute-intensive operations and require a computing system having a large amount of computation operations and memory capability. A memory device of a processor-in-memory (PIM) type, which is capable of performing some of the computation operations of the computing system via internal processing (or in-memory processing) of the memory device, is being developed. As such, the load of computation operations of the computing system may be reduced via the internal processing of the memory device. However, when separate pieces of processing hardware for the internal processing are added to the memory device, methods of efficiently performing interfacing and operation processing of the separate pieces of processing hardware may be required.

SUMMARY

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In one general aspect, a memory device for performing in-memory processing includes: a plurality of in-memory operation units configured to perform in-memory processing of an operation pipelined in multi-pipeline stages; a plurality of memory banks assigned to the plurality of in-memory operation units such that a set of n memory banks is assigned to each of the in-memory operation units, each memory bank configured to perform an access operation of data requested by each of the plurality of in-memory operation units while the pipelined operation is performed, wherein n is a natural number; and a memory die in which the plurality of in-memory operation units, the plurality of memory banks, and command pads configured to receive a command signal from an external source are arranged. Each set of the n memory banks includes a first memory bank having a first data transmission distance to the command pads and a second memory bank having a second data transmission distance to the command pads that is larger than the first data transmission distance.

Each of the in-memory operation units may be configured to access the first memory bank of the respective set of the n memory banks before accessing the second memory bank of the respective set of n memory banks to perform the in-memory processing of the pipelined operation.

The memory die may further include: a bank selector configured to sequentially select, for each set of n memory banks, the first memory bank and the second memory bank based on the first data transmission distance and the second data transmission distance; and a multiplexer configured to provide, to the respective in-memory operation unit, data accessed from the first memory bank or the second memory bank selected by the bank selector.

The plurality of memory banks may include a first set of memory banks arranged at one side on the memory die and a second set of memory banks arranged at another side on the memory die, and the plurality of in-memory operation units may include a first set of in-memory operation units arranged adjacent to the first set of memory banks and connected to the first set of memory banks in a region between the first set of memory banks and the second set of memory banks, and a second set of in-memory operation units arranged adjacent to the second set of memory banks and connected to the second set of memory banks in the region.

The command pads may be arranged between the first set of in-memory operation units and the second set of in-memory operation units in the region, and the first memory bank and the second memory bank of each set of n memory banks may be classified according to the first data transmission distance and the second data transmission distance within the region.

The first set of memory banks may be classified into two groups including a first group that is arranged closer to the command pads and a second group that is arranged farther away from the command pads, and the first memory bank of each set of n memory banks is selected from the first group and the second memory bank of each set of n memory banks is selected from the second group.

A first set of n memory banks from among the first set of memory banks may be assigned to a first in-memory operation unit from among the first set of in-memory operation units, and the first in-memory operation unit may process the pipelined operation with respect to data accessed from the first memory bank of the first set of n memory banks before data accessed from the second memory bank of the first set of n memory banks.

The memory device may be a double data rate 4 dynamic random-access memory (DDR4 DRAM) module, the first set of memory banks may include 8 memory banks and the second set of memory banks may include 8 memory banks, and the first set of in-memory operation units may include 8/n in-memory operation units and the second set of in-memory operation units may include 8/n in-memory operation units.

The first set of memory banks may include first, second, third, fourth, fifth, sixth, seventh, and eighth memory banks in an order of a first direction, the first set of in-memory operation units may include first, second, third, and fourth in-memory operation units in an order of the first direction, and the first and third memory banks may be assigned to the first in-memory operation unit, the second and fourth memory banks may be assigned to the second in-memory operation unit, the fifth and seventh memory banks may be assigned to the third in-memory operation unit, and the sixth and eighth memory banks may be assigned to the fourth in-memory operation unit.

A connection between the second set of memory banks and the second set of in-memory operation units may be symmetrical to a connection between the first set of memory banks and the first set of in-memory operation units.

Each of the in-memory operation units may include at least one pipeline register configured to buffer a sub-operation result in each pipeline stage of the pipelined operation.

The pipelined operation may include a multiply-accumulate (MAC) operation of a neural network.

In another general aspect, a memory device for performing in-memory processing includes: a plurality of in-memory operation units configured to perform in-memory processing of an operation pipelined in multi-pipeline stages; and a plurality of memory banks assigned to the plurality of in-memory operation units such that a set of n memory banks is assigned to each of the in-memory operation units, each memory bank configured to perform an access operation of data requested by each of the plurality of in-memory operation units while the pipelined operation is performed, wherein n is a natural number. Each set of the n memory banks may include a first memory bank having a first physical distance for data transmission of a command signal provided from an external source and a second memory bank having a second physical distance for the data transmission of the command signal that is larger than the first physical distance.

Each of the in-memory operation units may be configured to access the first memory bank of the respective set of the n memory banks before the second memory bank of the respective set of n memory banks to perform the in-memory processing of the pipelined operation.

The memory device may further include: a bank selector configured to sequentially select, for each set of n memory banks, the first memory bank and the second memory bank based on the first physical distance and the second physical distance; and a multiplexer configured to provide, to the respective in-memory operation unit, data accessed from the first memory bank or the second memory bank selected by the bank selector.

In another general aspect, a memory device includes in-memory operation units configured to perform in-memory processing of a pipelined operation of a neural network; memory banks, each memory bank being assigned to one of the in-memory operation units such that a set of n memory banks is assigned to each of the in-memory operation units, each memory bank configured to perform an access operation of data requested by the assigned in-memory operation unit while the pipelined operation is performed, where n is a whole number greater than or equal to 2; and command pads configured to receive a command signal from an external source. Each of the in-memory operation units is configured to access the memory banks from the respective assigned set of n memory banks in an order determined based on a distance from each of the memory banks in the respective set of n memory banks to the command pads.

The distance from each of the memory banks in the respective set of n memory banks to the command pad may be a data transmission distance, and each of the in-memory operation units may be configured to access the memory banks from the respective assigned set of n memory banks in an ascending order of the data transmission distance.

The distance from each of the memory banks in the respective set of n memory banks to the command pad may be a physical distance, and each of the in-memory operation units may be configured to access the memory banks from the respective assigned set of n memory banks in an ascending order of the physical distance.

Other features and aspects will be apparent from the following detailed description, the drawings, and the claims.

