This application claims priority of Application No. 109138841 filed in Taiwan on 6 Nov. 2020 under 35 U.S.C. § 119; the entire contents of all of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to process manufacturing techniques of an U-shaped gate metal-oxide-semiconductor field-effect transistor. More particularly, it is related to a manufacturing method for increasing an oxide thickness at trench corner of an U-shaped gate metal-oxide-semiconductor field-effect transistor.

Description of the Prior Art

In general, an U-shaped gate metal-oxide-semiconductor field-effect transistor (UMOSFET) is a kind of high-voltage metal-oxide-semiconductor field-effect transistor (HV MOSFET) which has small cell pitch, and thus makes an UMOSFET a semiconductor device with the low specific on-resistance.FIG.1shows a schematic diagram of a basic structure of a conventional N-type UMOSFET in the prior art. As shown, when a gate voltage is applied to the gate10and the gate voltage is sufficient to generate an inversion layer at the interface between the p-type substrate12and the gate oxide layer13, that is, the gate voltage is greater than a threshold voltage for the transistor to operate, under such condition, electrons will flow from the N+ source14in the upper place into the channel of the inversion layer, then enter the N− drift region15and finally reach the N+ drain16at its back end. In general, in order to form a complete channel, the trench depth of the gate10must exceed the p-type substrate12and enter the N-drift region15.

In view of the trending developments of the existing technologies, since silicon carbide (SiC) has a wider energy band and a higher breakdown voltage than silicon does, the UMOSFET which is made of silicon carbide, comparatively sustain ten times as large breakdown strength as the UMOSFET which is made of silicon does. Therefore, it achieves to sustain grandly high breakdown voltages with low impedance and thin drift layer. However, it draws our attention that, when a large voltage is applied to the drain, the effect of electric field crowding often occurs on both sides of its gate bottom of the transistor due to less radius of curvature on both sides of the gate bottom, as can be seen in the dotted-line region shown inFIG.2. In addition, for SiC devices, the wafer usually takes the (0001) crystal plane as its commonly used front side, and the (11-20) crystal plane as its trench sidewall. Normally, the electron mobility along the (11-20) crystal plane will be much higher than the electron mobility along the (0001) crystal plane, so that the transistor can have a lower on-resistance. Nevertheless, it is known that the thermal oxidation rate of the (0001) crystal plane is much lower than that of the (11-20) crystal plane. If the gate oxide layer of the transistor is formed by thermal oxidation, the thickness at the trench bottom will be thinner than the thickness at its sidewall. Moreover, taking consideration into the electric field enhancement effect at the corners on both sides of the trench bottom as illustrated inFIG.2, then the transistor will be very likely to fail due to its gate oxide breakdown. So far, there has been related technologies being proposed, which perform to control the chemical vapor deposition process parameters so as to make the deposition rate on the sidewall less than the deposition rate on its bottom. By doing so, the bottom oxide layer can be controlled to be thicker than the sidewalls. However, the electric field enhancement effect at the corners on both sides of the trench bottom still cannot be avoided, so the breakdown voltage of the transistor is still limited by breakdown of its gate oxide layer.

Based on these issues to be solved, another prior art, as indicated inFIG.3, proposes to use and dispose a P-type region31in the N-drift region30, which is configured to be close to the bottom of the gate32, and thus forms a depletion area by the p-n junction to deplete the trench bottom for reducing the electric field of the gate oxide layer. However, when the transistor is turned on, the depletion area formed by the p-n junction will also be an obstacle to its current flow, causing the JFET effect, thereby increasing the on-resistance of the device accordingly. Therefore, such method still has unavoidable issues to be solved. And yet, another prior art proposes to use a silicon dioxide to fill the trench first, after the trench is formed by etching. Afterwards, a chemical mechanical polishing (CMP) process is then employed to remove the silicon dioxide, which is located outside the trench. Later, for the remaining silicon dioxide which is located in the trench, a dry etching process is employed to etch the silicon dioxide in the trench, and merely leaves silicon dioxide of expected thickness as required. However, such method must be involved with a high-cost CMP process. Moreover, the thickness of the oxide layer at the bottom of the trench is also difficult to control precisely, and thus, cannot be brought into actual mass production stage.

And yet, another prior art proposes to use ion implantation to make amorphous silicon carbide at the bottom of the trench so as to increase its oxidation rate, and hopefully, to grow a thicker oxide layer by thermal oxidation. However, it is worth noticing that the oxidation temperature of such method is lower than the temperature required for the recrystallization of the silicon carbide. Therefore, it is very likely that defects will remain in the device structure and affect the performance of the device. As a result, it is believed that such method still fails to be practically applied.

Therefore, on account of above, to overcome the abovementioned problems, it should be obvious that there is indeed an urgent need for the professionals in the field for proposing a new manufacturing method to be developed that can effectively solve the above mentioned problems occurring in the prior design. And by using such manufacturing method, the oxide thickness at corners of the trench bottom of an UMOSFET can be effectively increased and those long-standing shortcomings in the prior arts can be successfully solved. Hereinafter, the detailed specific implementations will be fully described in the following paragraphs.

SUMMARY OF THE INVENTION

In order to overcome the above mentioned disadvantages, one major objective in accordance with the present invention is provided for a manufacturing method for increasing an oxide thickness at trench corner of an U-shaped gate metal-oxide-semiconductor field-effect transistor. By employing the proposed method of the invention, the oxide thickness at the trench corners of an UMOSFET can be effectively controlled in a better way, and the oxide thickness near the bottom of the trench sidewall can be increased without affecting a gate oxide thickness. Therefore, the electric field intensity within the oxide layer can be significantly lowered, and thus improve the breakdown voltages under the same given voltages being applied.

For achieving the above mentioned objectives, the technical solutions of the present invention are aimed to provide a method for increasing an oxide thickness at trench corner of an UMOSFET, comprising following steps.

(a): an N-type semiconductor substrate is provided, and an N-type drift region is formed on the N-type semiconductor substrate.

(b): an N-type heavily doped region is formed in the N-type drift region.

(c): a first P-type heavily doped region and a second P-type heavily doped region are respectively formed on opposite sides of the N-type heavily doped region, and a P-type body region is formed between the N-type heavily doped region, the first P-type heavily doped region, the second P-type heavily doped region and the N-type drift region.

(d): an etch hardmask layer is deposited on the N-type heavily doped region, the first P-type heavily doped region and the second P-type heavily doped region, and a trench is formed by using a lithography process. According to the embodiment of the present invention, the trench extends through the N-type heavily doped region and the P-type body region, and a bottom of the trench ends in the N-type drift region.

(e): a pad oxide is formed along two opposite sidewalls and a bottom of the trench, wherein a corner is correspondingly formed between each of the two opposite sidewalls and the bottom. According to the embodiment of the present invention, the pad oxide can be formed on the two opposite sidewalls and the bottom of the trench by using either an oxidation process or a deposition process. In addition, a thickness of the pad oxide can be between 0 and 100 nm.

(f): an oxidation barrier is provided on the pad oxide and a thermal oxidation process is performed, such that a corner oxide is formed at the corner of the trench by the thermal oxidation process. According to the embodiment of the present invention, the oxidation barrier can be made of silicon nitride (Si3N4), aluminum oxide (Al2O3), or aluminum nitride (AlN). And, a thickness of the oxidation barrier is between 50 and 300 nm.

Furthermore, the parameters and conditions for performing the proposed thermal oxidation process comprise setting the process temperature between 900 and 1300 Celsius degrees, controlling the process time between 10 and 600 minutes, and using oxygen (O2), water molecule (H2O), or a mixture of hydrogen (H2) and oxygen (O2) in the thermal oxidation process. Therefore, when the thermal oxidation process is being applied for growing the corner oxide, a thickness of the corner oxide is between 50 and 100 nm. In general, various modifications and variations to the present invention can be made by people who are skilled in the art, without departing from the scope or spirits of the invention. And yet, the present invention covers these modifications and/or variations provided that, they fall within the scope of the invention and its equivalent. The present invention is certainly not limited to the disclosed parameters and conditions as illustrated above.

(g): the pad oxide and the oxidation barrier are removed, and a gate oxide forming process is performed to generate a gate oxide, wherein the gate oxide forming process may comprise, and yet not limited to a high temperature oxidation process, a chemical vapor deposition, and so on for generating the gate oxide. The gate oxide is formed along the two opposite sidewalls and the bottom of the trench and in connection with the above mentioned corner oxide.

(h): a gate conductive layer is formed in the trench and a dielectric layer is further deposited on the gate conductive layer.

According to the embodiment of the present invention, the gate conductive layer is formed by using a low-pressure chemical vapor deposition (LPCVD) process first, to deposit a polysilicon as a gate material. And, subsequently using an etch back process to etch back the polysilicon, so as to form the gate conductive layer.

(i): at least one contact window is formed, which extends through the dielectric layer and the etch hardmask layer, and electrically connected to the N-type heavily doped region, the first P-type heavily doped region, and the second P-type heavily doped region for providing electrical paths.

Preferably, according to one embodiment of the present invention, the material for forming the semiconductor substrate can be silicon carbide, such that the corner oxide is formed by oxidation of the silicon carbide at the corner of the trench through the thermal oxidation process. In one embodiment, the corner oxide is made of silicon dioxide (SiO2), and a thickness of the corner oxide is between 50 and 100 nm.

To sum above, it is apparent that, the present invention mainly discloses an UMOSFET structure having increased oxide thickness at bottoms of its trench sidewalls and the manufacturing method for fabricating such an UMOSFET structure. According to the process techniques disclosed by the present invention, the thick oxide layer (i.e. the corner oxide) which grows at the trench sidewall bottoms is formed by a high-temperature thermal oxidation process using an oxidation barrier for covering its sidewalls, such that oxygen-containing molecules can diffuse into the gap between the oxidation barrier and the silicon carbide from the bottom of the oxidation barrier, and reacts with the silicon carbide to form silicon dioxide. As a result, the present invention achieves to effectively increase the oxide thickness at the bottom of the trench sidewalls and enhance the breakdown voltages without affecting its gate oxide thickness. Furthermore, a gate-to-drain capacitance of the transistor can also be reduced.

The applicants emphasize and assert that, the foregoing embodiments of the present invention are described with silicon carbide, merely for an illustrative example as to enable those skilled in the art to fully understand the technical features of the present invention and are not intended to limit the application of the present invention. In other words, the process method disclosed in the present invention can also be further applied to various semiconductor materials, and not limited to silicon carbide substrates.

These and other objectives of the present invention will become obvious to those of ordinary skill in the art after reading the following detailed description of preferred embodiments.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

