CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of India Provisional Application Number 2020/11032822, filed Jul. 30, 2020, which is hereby incorporated by reference in its entirety.

INTRODUCTION

Conventional core voltage domains have lower voltages than input/output voltage domains to provide for fast switching speeds and low power consumption in the cores while maintaining compatibility with external circuitry. Complementary metal-oxide-semiconductor based latch circuits are normally used to shift input signal voltages down from the input/output voltage domains to the core voltage domains. Latch circuit designs employ both p-channel field effect transistors and n-channel field effect transistors. However, the p-channel field effect transistors have low drain saturation currents relative to the n-channel field effects transistors of similar geometry. Combined with higher beta ratios of core devices relative to input/output devices, the latch circuits exhibit asymmetrical pull-up/pull-down performances. The pull-up performances often limit the speed at which the input signals are transferred into the core voltage domains. Increasing a size of the p-channel field effect transistors usually increases on-die area of the latch circuits and increases leakage currents.

SUMMARY

A level down shifter circuit is provided herein. The level down shifter circuit includes a latch and an assist circuit. The latch is configured to generate a digital shifted signal and a complementary shifted signal by a voltage downshift of a digital input signal and a complementary input signal. The digital input signal and the complementary input signal are in a first voltage domain. The digital shifted signal and the complementary shifted signal are in a second voltage domain. The second voltage domain has a smaller voltage range than the first voltage domain. The assist circuit is configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal. The intermediate voltage is in the second voltage domain.

A method for level down shifting is provided herein. The method includes generating a digital shifted signal and a complementary shifted signal by downshifting voltages of a digital input signal and a complementary input signal using a circuit. The digital input signal and the complementary input signal are in a first voltage domain. The digital shifted signal and the complementary shifted signal are in a second voltage domain. The second voltage domain has a smaller voltage range than the first voltage domain. The method further includes alternately pulling the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal. The intermediate voltage is in the second voltage domain.

A non-transitory computer readable storage medium storing a library cell defining a level down shifter circuit is provided herein. The level down shifter circuit includes a digital input node, a complementary input node, a digital output node, an intermediate node, a latch, and an assist circuit. The latch is coupled to the digital input node, the complementary input node, and the digital output node. The latch is configured to generate a digital shifted signal on the digital output node and a complementary shifted signal on a complementary shifted node by a voltage downshift of a digital input signal on the digital input node and a complementary input signal on the complementary input node. The digital input signal and the complementary input signal are in a first voltage domain. The digital shifted signal and the complementary shifted signal are in a second voltage domain. The second voltage domain has a smaller voltage range than the first voltage domain. The assist circuit is coupled to the digital input node, the complementary input node, the digital output node, and the complementary shifted node. The assist circuit is configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage on the intermediate node in response to the digital input signal and the complementary input signal. The intermediate voltage is in the second voltage domain.

The above features and advantages and other features and advantages of the present disclosure are readily apparent from the following detailed description of the best modes for carrying out the disclosure when taken in connection with the accompanying drawings.

