REFERENCE TO RELATED APPLICATION

This application claims priority to German Application No. 10 2019 107 139.9, filed on Mar. 20, 2019, the contents of which are hereby incorporated by reference in their entirety.

FIELD

The disclosure relates to the transformation of binary signals read from a memory.

BACKGROUND

U.S. Pat. No. 9,805,771 B2 discloses the evaluation of states which are read from memory cells to transform them into the time domain and to utilize states arriving earlier in time accordingly for efficient read-out of memory cells.

SUMMARY

The present disclosure improves existing solutions and provides an efficient approach for transforming binary signals read from a memory.

A method is proposed for transforming a first binary signal read from a memory,

wherein the first binary signal is transformed into a second binary signal when the first binary signal is a code word or a predefined code word of a k-out-of-n code,

wherein the first binary signal is transformed into a predefined signal when the first binary signal is not a code word or is not a predefined code word of the k-out-of-n code.

The predefined signal is different than the second binary signal.

The transformation can be realized for example by means of a logic circuit and/or a table.

In one embodiment the following can hold true: 1≤k≤n, wherein n and k are positive integers.

In one embodiment, there is a (dedicated) second binary signal for each predefined code word of the k-out-of-n code.

By way of example, in the error-free case, the first signals are predefined code words of the k-out-of-n code. If a predefined code word is thus detected, then the first binary signal is transformed into the second binary signal.

The first binary signal can be transformed into the predefined signal, wherein the predefined signal can comprise a validity signal (e.g. in the form of a validity bit) (the predefined signal can also be a validity signal). The validity signal can thus indicate that the first binary signal is not a code word or is not a predefined code word of the k-out-of-n code. Such a validity signal can optionally also indicate that the second binary signal is valid because the first binary signal is a code word or a predefined code word of the k-out-of-n code.

There are a number of possibilities appertaining to the fact that transformation into the second signal is not effected, rather instead the predefined signal is provided:

The first binary signal is a code word of the k-out-of-n code, but for this very code word there is no appropriate second binary signal.

The first binary signal is not a code word of the k-out-of-n code.

Consequently, the case where the amount of code words of the k-out-of-n code is greater than the amount of value combinations possible by means of the second signal is also covered. By way of example, a 3-out-of-6 code comprises 20 code words, which, in accordance with the transformation, can also be mapped onto 4 bits and thus 16 possible values by virtue of 4 code words remaining unused and these 4 code words being transformed into the predefined signal in accordance with the above specification.

It should be noted here that the term “code word” denotes a valid allocation of bits in accordance with the predefined code. The code word thus fulfills the properties of a code. This correspondingly applies to different code words of different codes.

Further explanation is given below of how the states are determined in the time domain. Supplementary, in this regard, reference may also be made to U.S. Pat. No. 9,805,771 B2. As a result of transforming the variables to be detected into the time domain, the individual states occur successively in time. By way of example, 0-states occur before the 1-states (the designations 0-state and 1-state have been chosen by way of example for illustration purposes). Consequently, after the arrival of the k 0-states, the determination of the n states can be ended and the value 1 can be assigned to the n−k remaining states (there is no need to wait until the 1-states have been determined because, on account of the k-out-of-n code, there are k 0-states and (n−k) 1-states).

In one embodiment, the first binary signal is read from n memory cells of the memory.

In one embodiment, a memory cell of the memory can assume two or more states.

In one embodiment, the predefined signal comprises at least one of the following possibilities:

a predefined bit sequence,

a predefined bit sequence having a validity signal, for example, a validity bit, and

a predefined bit sequence having the same number of digits as the second binary signal.

In this case, it should be noted that the validity signal can be a binary signal or an analog signal or can comprise at least one binary and/or at least one analog signal.

In one embodiment,

the first binary signal has n binary values, and

the second binary signal has a number of binary values which is less than or equal to n.

In one embodiment, the second binary signal or the predefined signal is stored in an arrangement of latches, wherein the number of latches corresponds to the number of binary values of the second binary signal.

By way of example, a signal for freezing the latch (hold signal of the latch) can be determined solely from the value present at the data input of said latch. Consequently, directly and without significant delay, the latch can react and freeze the signal present at its data input.

In one embodiment,

the first binary signal and the second binary signal each have n binary values, and

the first binary signal is transformed into the second binary signal, wherein the first and second binary signals are identical provided that the first binary signal is a code word or a predefined code word of the k-out-of-n code.

In one embodiment,

in each case n states are read from memory cells of a memory, and the k fastest states or the (n-k) fastest states of the first binary signal are determined in a time domain.

In one embodiment, the fastest states are 0-states.

Alternatively, it is also possible that, on account of the assignment of physical specifications to states, the fastest states are 1-states.

In one embodiment, the remaining states that do not belong to the fastest states are correspondingly set.

If the fastest states are 0-states, then after determining the k-th 0-state, those (n−k) states for which an assignment has not yet been effected can be set as 1-states.

In one embodiment, the memory comprises at least one of the following memories:

Floating gate cells;

PCRAM,

RRAM,

MRAM,

MONOS components,

Nanocrystal cells, and

ROM.

Moreover, a device is proposed for transforming a first binary signal read from a memory, comprising a processing circuit.

The processing circuit is configured to transform the first binary signal into a second binary signal provided that the first binary signal is a code word or a predefined code word of a k-out-of-n code.

The processing circuit is further configured to transform the first binary signal into a predefined signal provided that the first binary signal is not a code word or is not a predefined code word of the k-out-of-n code.

The predefined signal is different than the second binary signal.

In one embodiment, the method is carried out by a processing unit arranged functionally between the memory and an error processing facility coupled to a system bus.

In this case, the processing circuit can comprise software, hardware or mixed forms (firmware).

The device can be embodied in one component or in a distributed fashion in a plurality of components. Moreover, the processing circuit can comprise the error processing facility or be embodied separately from the latter. The memory can be part of the device or be embodied separately from the latter.

The processing circuit mentioned here can be embodied in particular as a processor unit and/or an at least partly hardwired or logic circuit arrangement, which is configured for example in such a way that the method as described herein is implementable. Said processing circuit can be or comprise any type of processor or computer with correspondingly required peripherals (memories, input/output interfaces, input-output devices, etc.).

The above explanations concerning the method are correspondingly applicable to the device.

In one embodiment the device furthermore comprises an arrangement of latches,

wherein the second binary signal or the predefined signal is stored in the arrangement of latches, wherein the number of latches corresponds to the number of binary values of the second binary signal.

Moreover, a system is specified comprising at least one device described herein.

Furthermore, a computer program product is proposed which is loadable directly into a memory of a digital computer, comprising program code parts suitable for carrying out steps of the method described herein.

Moreover, a non-transitory computer-readable storage medium is specified, comprising computer-executable instructions suitable for the computer to carry out steps of the method described herein.

The above-described properties, features and advantages and the way in which they are achieved are explained further in association with the following schematic description of example embodiments which are explained in greater detail in association with the drawings. In this case, identical or identically acting elements may be provided with identical reference signs for the sake of clarity.

