CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. 119(a) to Korean Patent Application No. 10-2019-0124037, filed on Oct. 7, 2019, which is herein incorporated by reference in its entirety.

BACKGROUND

1. Technical Field

The present disclosure relates generally to a method of manufacturing a semiconductor device and, more particularly, to a method of forming patterns.

2. Related Art

When integrating circuits of electronic devices into a semiconductor substrate, efforts have been made to integrate a larger number of patterns in a limited area. The degree of integration of electronic devices or semiconductor devices has been increased, and efforts have been made to realize fine patterns of smaller sizes. In order to form dense arrays of contact holes having a nanoscale line width of several nanometers (nm) level, various patterning techniques have been attempted.

Due to limitations in image resolution of photolithography equipment, there is a limitation in forming fine patterns below a certain size. It is difficult to form nanoscale fine patterns in a single exposure process. In order to overcome the resolution limitations of a photolithography technology to form dense and finely sized patterns, a technique of overlapping several patterning steps, such as the triple patterning technique, has been attempted.

SUMMARY

The present disclosure provides a method of forming patterns. The method of forming patterns may include forming a target layer on a semiconductor substrate, forming a plurality of first spacers, each of the first spacers having a cylindrical shape protruding from the target layer, forming a second spacer layer formed to cover the first spacers, provide interstitial spaces between the first spacers, and provide second inner spaces within first inner spaces of the first spacers, and etching the second spacer layer to form first opening portions in which the second inner spaces and the interstitial spaces extend into the target layer.

The present disclosure provides a method of forming patterns according to another example. The method of forming patterns may include forming an array of line patterns on a semiconductor substrate, forming a base layer covering the line patterns; forming a target layer on the base layer, forming a plurality of first spacers, each of the first spacers having a cylindrical shape protruding from the target layer, forming a second spacer layer formed to: cover the first spacers, provide interstitial spaces between the first spacers, and provide second inner spaces within first inner spaces of each of the first spacers, respectively, etching the second spacer layer to form first opening portions in which the second inner spaces and the interstitial spaces are extended in the target layer, thereby patterning the target layer, and performing pattern transfer for the first opening portions to the base layer and the line patterns using the target layer pattern as an etching mask.

The present disclosure provides a method of forming patterns according to another example. The method of forming patterns may include forming a target layer and a buffer layer on a semiconductor substrate including a first region and a second region, selectively etching the buffer layer to form a first buffer layer pattern providing second opening portions in the first region and a second buffer layer pattern spaced apart from the first buffer layer in the second region, forming a first spacer layer on the target layer to cover the first and second buffer layer patterns, forming a region blocking pattern exposing the first spacer layer covering the first buffer layer pattern and covering to block the second buffer layer pattern on the spacer layer, etching the first spacer layer portions exposed by the region blocking pattern to form first sub spacers positioned at inner side surfaces of the first buffer layer pattern and having a protruding cylindrical shape, protruding second sub spacer positioned at an outer side surface of the first buffer layer pattern facing the second buffer layer pattern, and a third sub spacer mask extending from the first spacer layer to at least cover the second buffer layer pattern, removing the first buffer layer pattern, forming a second spacer layer formed to cover the first spacers, the second spacer layer providing interstitial spaces between the first spacers and providing second inner spaces within first inner spaces of each of the first spacers, respectively, and etching the second spacer layer to form a first target layer pattern providing first opening portions formed by extending the second inner spaces and the interstitial spaces, a second target layer pattern overlapping the second sub spacer, and a third target layer pattern overlapping the second buffer layer pattern.

