BACKGROUND

1. Field

Embodiments relate to a semiconductor device and a method for manufacturing the same and, more particularly, to a semiconductor device including interconnection lines disposed on memory transistors of a substrate and a method for manufacturing the same.

2. Description of the Related Art

Semiconductor devices are widely used in an electronic industry because of their small sizes, multi-functional characteristics, and/or low manufacture costs. Semiconductor devices may be categorized as any one of semiconductor memory devices storing logical data, semiconductor logic devices processing logical data, and hybrid semiconductor devices having both the function of the semiconductor memory devices and the function of the semiconductor logic devices. Semiconductor devices with excellent characteristics have been increasingly demanded with the development of the electronic industry. For example, high-reliable, high-speed, and/or multi-functional semiconductor devices have been increasingly demanded. To satisfy these demands, semiconductor devices have been highly integrated and structures of semiconductor devices have been more and more complicated.

SUMMARY

In an aspect, a semiconductor device may include a substrate including a first region and a second region, memory transistors on the first region, a first interconnection layer on the memory transistors and including first interconnection lines, and a second interconnection layer on the first interconnection layer and including second interconnection lines. The second interconnection lines on the first region include a first line extending along a first direction and spaced from the second region by a first distance along the first direction, and a second line extending along the first direction, spaced from the first line along a second direction intersecting the first direction, and having a width smaller along the second direction than a width of the first line. The first line may include a protrusion extending along a third direction, intersecting the first and second directions, toward the substrate. The protrusion may be spaced from the second region by a second distance along the first direction, the second distance being greater than the first distance.

In an aspect, a semiconductor device may include a substrate including a memory cell region and a logic cell region, memory transistors on the memory cell region, logic transistors on the logic cell region, and an interconnection layer including interconnection lines on the memory transistors and the logic transistors. The interconnection lines may include a word line on the memory transistors and extending in a first direction, and a conductive line on the logic transistors and extending in a second direction intersecting the first direction. The word line may include a protrusion extending toward the substrate, and a distance in the first direction between the conductive line and the word line may be smaller than a distance in the first direction between the conductive line and the protrusion.

In an aspect, a semiconductor device may include a memory cell on a substrate, an interlayer insulating layer on the memory cell, and an interconnection layer including interconnection lines provided in an upper portion of the interlayer insulating layer. The memory cell may include first and second access transistors, first and second pull-up transistors, and first and second pull-down transistors. The interconnection lines may include a first line, and a second line having a width smaller than a width of the first line. The first line may include a protrusion extending toward the substrate. A level of a bottom surface of the protrusion may be lower than a level of a bottom surface of the second line, and the level of the bottom surface of the protrusion may be higher than a level of a bottom surface of the interlayer insulating layer.

In an aspect, a method for manufacturing a semiconductor device may include forming memory transistors on a substrate, sequentially forming an interlayer insulating layer and a hard mask layer on the memory transistors, performing a first patterning process on the hard mask layer to form a first opening, performing a second patterning process on the hard mask layer to form a second opening, and performing a third patterning process on the hard mask layer to form a recess region in an upper portion of the interlayer insulating layer exposed by the second opening. The performing of the third patterning process may include forming a photoresist pattern having a third opening on the hard mask layer. The third opening of the photoresist pattern vertically may overlap with the second opening of the hard mask layer.

In an aspect, a method for manufacturing a semiconductor device, may include forming a first layout pattern on a substrate, the first layout pattern including, in a first region of the substrate, a first layout portion extending in a first direction, and, in a second region of the substrate, a first layout portion extending in a second direction intersecting the first direction, forming a second layout pattern on the substrate, the second layout pattern including, in the first region of the substrate, a second layout portion extending in the first direction and spaced apart from the first layout portion in the first region along the second direction, and, in the second region of the substrate, a second layout portion extending in the second direction, forming a third layout pattern on the substrate, the third layout pattern including, in the first region of the substrate, a third layout portion extending in a third direction intersecting the first and second direction from the first layout portions in the first region, and, in the second region of the substrate, a third layout portion extending in the second direction and spaced from the first and second layout portions in the second region along the first direction. The third layout portion in the second region may be closer along the first direction to the first and second layout portions in the first region than to the third layout portion in the second region.

