TECHNICAL FIELD

This disclosure is related to a charge pump and associated regulation circuitry for generating program and erase voltages for use in a non-volatile memory.

BACKGROUND

Non-volatile memory devices are used in applications where it is desirable to store information that is to be retained even when the device into which the non-volatile memory is incorporated is not powered. Generally, each non-volatile memory device includes a matrix of memory cells utilizing floating gate MOS storage transistors; each such floating gate MOS storage transistor has a threshold voltage that may be set (according to an electric charge in its floating gate) to different levels to represent different logic values.

For example, in Electrically Erasable and Programmable Read-Only Memories (EEPROMs) each floating gate MOS storage transistor may be both programmed (by injecting electric charge into its floating gate) or erased (by removing electric charge from its floating gate) individually thanks to the use of a set of MOS selection transistors that selectively apply the required voltages to the corresponding storage floating gate MOS transistor (with a complex structure that limits the capacity of the EEPROMs). On the other hand, flash memories have a simple structure that allows obtainment of very high capacities of hundreds of Gigabytes or even higher thanks to the grouping of the floating gate MOS transistors in sectors, each integrated in a common well of semiconductor material without a selection transistor, but with a structure that enables the erasing at a sector level instead of at an individual level.

In both cases, as well as in the case of any non-volatile memory, program and erase efficiency is a function of the electric field applied across the floating gate MOS storage transistors. To generate these electric fields, a high voltage is generated by a charge pump and applied to a word line (for program operations) or applied to a substrate line (for erase operations). Floating gate MOS storage transistors have parasitic diodes formed by the PN junction between their source and drain. During both the program and erase operations, these parasitic diodes are reverse biased.

Some non-volatile memory cells may be made using a triple well technology where an isolated Pwell structure is used to make an NMOS device. There are two extra parasitic diodes present in triple well technology: one PN junction (and thus parasitic diode) is between the isolated Pwell and the Nwell and another PN junction (and thus parasitic diode) is between the Nwell and the substrate. In any design, these junctions should be reverse biased so that proper functionality can be maintained during at least program and erase operations.

Due to process and temperature variations, some parasitic diodes of a non-volatile memory cell can be being electrically stressed, which could lead to breakdown, and improper function (or even damage) of the non-volatile memory cell.

In order to avoid such condition, it is possible to define rail voltages for these parasitic PN junctions in triple well technology. Normally the PN junction between an isolated Pwell and an Nwell is named as “Intrail” and the PN junction between the Nwell and the substrate is named as “Extrail”. Rail voltage limits can be defined for these PN junctions, which serve to change the design rule for the PN junctions and eventually changes the break-down voltage as well. For example, if a designer knows that maximum voltage across the PN junctions is going to be 15V, then a rail voltage of more than 15V will be defined to avoid break-down of these PN junctions. However, this leads to an increased area cost and potentially an increased production cost.

Therefore, to avoid the defining of over-estimated rail voltages and the associated area and production cost, a new regulation scheme for the charge pump circuits has been developed. An example charge pump and regulation circuit50is shown inFIG. 1. The charge pump and regulation circuit50includes a charge pump52that generates a charge pump output voltage OUT under control of the clock signals CLK and CLKN, which are logical inverts of each other. A resistive divider formed from resistors R1and R2is coupled in series between the output of the charge pump52and ground. Node N denotes the partitioning of the resistive divider. A comparator54has its non-inverting input coupled to receive a bandgap voltage VBG (or any reference voltage which is stable across different processes, temperature, and supply conditions), its inverting input coupled to the partitioning of the resistive divider at node N, and generates a control signal OSTOP at its output, and OSTOP can be either an oscillator or a clock control signal. The oscillator control signal OSTOP is an on/off enable signal and controls an oscillator60that generates the clock signals CLK and CLKN that in turn control the charge pump52. When OSTOP is at a logic high, the oscillator60is enabled, and when OSTOP is at a logic low, the oscillator60is disabled.

In operation, the voltage divider serves to detect the output voltage OUT of the charge pump52at node N. The voltage at node N is then compared to the bandgap voltage VBG. If the voltage at node N is below the bandgap voltage VBG, the comparator54generates the oscillator control signal OSTOP at a logic high. When the oscillator control signal OSTOP is at a logic high, the oscillator60generates or outputs the clock signals CLK and CLKN to cause the charge pump52to ramp up the voltage of the charge pump output signal OUT. The voltage of the charge pump output signal OUT therefore continues to ramp up until the voltage at node N is equal to the bandgap voltage VBG, at which point the comparator54generates the oscillator control signal OSTOP at a logic low. As a result, the oscillator60deactivates or stops generation of the clock signals CLK and CLKN so as to stop ramp up of the charge pump52.

This regulation scheme is effective, but must be set to account for the worst case operating scenario of the non-volatile memory so that the voltage of the output signal OUT does not result in breakdown of a parasitic diode, such as one within the triple well of a non-volatile memory. This requirement to account for the worst case operating scenario arises out of the fact that the regulation scheme does not track variations over process or temperature.

Therefore, further development is needed.

SUMMARY

A circuit disclosed herein includes a negative charge pump circuit configured to generate a negative charge pump output signal at a first node, the negative charge pump circuit being enabled as a function of at least one charge pump control signal. A diode has an anode coupled to the first node and a cathode coupled to a second node. The diode draws a reverse current from the second node. A comparator has a non-inverting input coupled to the second node and an inverting input coupled to a third node. The comparator is configured to cause generation of the at least one charge pump control signal. A current mirror arrangement is configured to source a first current to the second node and sink a second current from the third node.

The first current and second current may have a same magnitude.

The comparator may generate an oscillator control signal, and an oscillator may be configured to generate the at least one charge pump control signal as a function of the oscillator control signal generated by the comparator.

The circuit further may include a non-volatile memory, and the diode may be formed using a same process as transistors of the non-volatile memory.

The circuit is formed on a semiconductor substrate. A non-volatile memory is also formed in the semiconductor substrate. The diode is also formed in the semiconductor substrate.

The current mirror arrangement may include a current sink configured to sink the second current from the third node, and a current source configured to source the first current to the second node.

The current sink may include: a first NMOS transistor having a drain coupled to the third node, a source coupled to ground, and a gate; and a second NMOS transistor having a drain coupled to receive a first current, a source coupled to ground, and a gate coupled to the drain of the second NMOS transistor and to the gate of the first NMOS transistor.

The current source may include: a first PMOS transistor having a source coupled to a supply node, a drain coupled to the second node, and a gate; and a second PMOS transistor having a source coupled to the supply node, a drain coupled to the third node, and a gate coupled to the third node and to the gate of the first PMOS transistor.

The supply node may be coupled to a DC voltage supply or to a voltage regulator to receive a regulated voltage therefrom.

The voltage regulator may include: an operational amplifier having a non-inverting terminal coupled to receive a reference voltage, an inverting terminal, and an output providing the regulated voltage; and a voltage divider coupled between the output of the operational amplifier and ground, wherein a tap of the voltage divider is coupled to the inverting terminal of the operational amplifier.

The at least one charge pump control signal may include a clock signal and a complement of the clock signal.

Also disclosed herein is a circuit including a charge pump circuit generating a negative charge pump output signal at a first node as a function of at least one charge pump control signal, a diode having an anode coupled to the first node and a cathode coupled to a second node, a first current mirror configured to source a first current to the second node, and a second current mirror configured to sink a second current from a third node (the second current having a same magnitude as the first current). A comparison circuit compares a voltage at the second node to a voltage at the third node, causes the at least one charge pump control signal to direct the charge pump circuit to generate the negative charge pump output signal having a voltage that ramps downward, based upon the voltage at the second node being greater than the voltage at the third node; causes the at least one charge pump control signal to direct the charge pump circuit to cease the downward ramping of the voltage of the charge pump output signal, if the voltage at the second node is at least equal to the voltage at the third node.

A method disclosed herein includes generating a charge pump output signal that has a voltage that ramps downwardly, receiving the charge pump output signal at an anode of a diode, sourcing a second current to a cathode of the diode, sinking a first current from a node, the first current being equal in magnitude to the second current, comparing a voltage at the node to a voltage at the cathode of the diode. When voltage at the cathode of the diode becomes equal to the voltage at the node, the method continued with causing the charge pump output signal to cease ramping.

The charge pump output signal has a voltage that ramps upward in magnitude but is negative in sign. When the voltage at the cathode of the diode becomes equal to the voltage at the node, the charge pump output signal is caused to cease ramping upward in magnitude.

