BACKGROUND

The present invention relates to phase interpolation. More particularly, the present invention relates to circuits to correct phase interpolator seam non-linearity errors.

Some circuit designs employ frequency synthesizers which synthesize any desired target frequency from a high frequency voltage controlled oscillator (VCO) clock. The VCO clock can be quantized into a fixed number of phase increments per cycle. As is well known in the art, some frequency synthesizers synthesize a target frequency by dividing the VCO clock output by a divisor that has an integer portion and may also include a fractional portion. One known way of accomplishing this frequency division is to provide a circuit with an accumulator that accumulates at every VCO clock cycle a frequency control word (FCW) equal to a number of accumulated phase increments of the VCO clock cycle that is selected based on the desired target frequency until the output value of the accumulator exceeds a predefined number (overflows) that is also selected based on the desired target frequency. The amount by which the output value of the accumulator exceeds the predefined number at overflow defines the fractional portion of the divisor. At the VCO clock cycle where the accumulated output value of the accumulator exceeds the predefined number, a CARRY signal is generated, and is delayed by the fractional portion of the divisor in the accumulator to define a clock edge of the synthesized target frequency. This signal output is shown as the rising edge of the synthesized target waveform inFIGS. 1A and 1B. This process of employing a divisor having a fractional portion is sometimes referred to as phase interpolation.

Where the VCO clock is divided by a whole number (an integer with no fractions), in each cycle of the synthesized target waveform the accumulated phase increments of the VCO clock (referred to herein as the cumulative phase integer (PHASE I) value) will increase by a constant phase integer delta (PHASE IΔ) value equal to the number of phase increments in each VCO clock cycle included in a single target output clock cycle. The increase will not include any VCO clock cycle phase fraction (PHASE F) value. This is illustrated inFIG. 1Ashowing a VCO clock waveform (top) and a synthesized target output waveform (bottom) where the VCO frequency has been divided by a whole number 8 to produce the synthesized target output waveform. As can be seen there is no phase fractional component PHASE F, i.e. the VCO clock cycle phase fraction (PHASE F) value is zero.

Where the VCO clock is divided by a number with a fractional component, the value of the phase integer delta (PHASE IΔ) will modulate between a maximum and a minimum value. This is illustrated inFIG. 1Bshowing a VCO clock waveform (top) and a synthesized target output waveform (bottom) where the VCO frequency has been divided by 8+⅛. The value of the phase integer delta PHASE IΔ is 8 during the first seven cycles of the synthesizer output waveform and is 9 during the eighth cycle. The value of the phase integer delta PHASE IΔ returns to 8 in the next cycle of the synthesized target clock waveform.

As can also be seen from an examination ofFIG. 1B, a VCO clock cycle phase fraction value (PHASE F) will be included in each complete cycle of the synthesized target waveform, as indicated by the pair of vertical dimension lines showing the VCO clock cycle phase fraction PHASE F value that exists at the rising edge of each cycle of the synthesized target output waveform. The rising edge of each cycle of the synthesized target waveform coincides with the end of the VCO clock cycle phase fraction PHASE F value as shown at the right hand one of each of the pair of vertical dimension lines inFIG. 1B. The VCO clock cycle phase fraction PHASE F value is also cyclical. In the example shown inFIG. 1B, the VCO clock cycle phase fraction PHASE F value is ⅛, then 2/8, then ⅜, then 4/8, then ⅝, then 6/8, then ⅞, then 0, before returning again to ⅛ in successive cycles of the synthesized target waveform.

A phase interpolator can be used to synthesize a waveform from a VCO clock output. As shown inFIG. 1C, and as is well known in the art, a digital portion of a phase interpolator is used to generate the cumulative phase integer PHASE I value and the VCO clock cycle phase fraction PHASE F value for synthesizing any output frequency from a given VCO clock output (e.g., by using the FCW accumulator technique described above). This information can then be used by an analog portion of the phase interpolator to generate the synthesized target waveform.

As noted above, when dividing a VCO clock signal by a number including a fractional component, the frequency synthesizer operation requires dynamic values for the integer and fraction inputs to a phase interpolator analog portion because the VCO clock output is not being divided by a constant integer for each cycle of the target output clock. For every frequency to be generated, a different pattern of dynamic values will be necessary.

Referring now toFIG. 2, a set of three tables showing the cumulative phase integer (PHASE I) value, the phase integer delta (PHASE IΔ) value and the VCO clock cycle phase fraction (PHASE F) value resulting from three illustrative VCO non-integer divisor values, 8+⅛, 8+⅜, and 9+⅞, respectively, used to generate output frequencies from a VCO oscillator. Each column of each table shows the cumulative phase integer PHASE I value, the phase integer delta PHASE IΔ value, and the VCO clock cycle phase fraction PHASE F value components of successive single cycles of the synthesized target waveform. The top line in each table is the cumulative phase integer (PHASE I) value which is the total number of accumulated quantized phase increments. This number resets every n cycles of the synthesized target waveform, where n is the denominator of the fractional portion of the divisor by which the VCO clock frequency is being divided to synthesize the synthesized target waveform. In each of the three illustrative examples shown inFIG. 2, n=8. The second line in each table is the phase integer delta (PHASE IΔ) value which is the integer number of VCO cycles that occur during a single cycle of the synthesized target waveform. For example, where the phase integer delta (PHASE IΔ) value is 8, the immediately prior cumulative phase integer PHASE I value for the previous single cycle of the synthesized target waveform will be 8 less than the current cumulative phase integer PHASE I value (e.g., if the immediately prior cumulative phase integer PHASE I value was 40, the cumulative phase integer PHASE I value for the current single cycle of the synthesized target waveform would then be 48). The third line in each table is the current VCO clock cycle phase fraction (PHASE F) value which is the fractional portion of a VCO cycle for the current single cycle of the synthesized target waveform. The fourth line in each table is the VCO clock cycle phase fraction PHASE F value expressed in terms of the VCO clock cycle phase in a system where, as an example, each VCO clock cycle is quantized into 1,024 phase increments. It is seen, for example, that in a system where each VCO clock cycle is quantized into 1,024 phase increments, a VCO clock cycle phase fraction of ⅜ equates to a VCO clock cycle phase of 384 (=1,024*⅜).

From an examination ofFIG. 2, persons of ordinary skill in the art will observe the cyclical behavior of the phase integer delta (PHASE IΔ) value and the VCO clock cycle phase fraction (PHASE F) value, where the integer portion modulates between 8 and 9 and the where the fractional portion of divisor for the VCO=8, the values in the ninth column in each table are the same as the values in the first column of that table. The modulation of the phase integer delta (PHASE IΔ) value may be referred to as a “seam”.

Persons of ordinary skill in the art will appreciate that a different table will be generated for each individual value of the VCO fractional divisor. Such skilled persons will also appreciate that the number of columns in any table before the values of the phase integer delta (PHASE IΔ) begin to repeat will be equal to the denominator of the value of the VCO cycle phase fraction PHASE F.

Because no phase interpolator will interpolate phase perfectly, it is expected that the phase interpolator will have integral non-linearity (INL) errors. This means that for a given fractional value, the phase interpolator will not perfectly interpolate that fractional value within the VCO clock cycle. Calibration RAM circuitry has been used in the prior art to correct the INL for a given fraction.

BRIEF DESCRIPTION

In accordance with an aspect of the invention, a circuit for correcting phase interpolator rollover integral non-linearity errors includes a rollover detector circuit for detecting when a rollover event of a phase interpolator (referred to hereinafter as an “interpolator rollover event”) has occurred, and a correction circuit that adds a signed predistortion correction to a VCO clock cycle phase fraction value when the rollover detector circuit has detected the interpolator rollover event.

In accordance with an aspect of the invention, the circuit further includes an integral non-linearity distortion pre-correction circuit for pre-correcting the VCO clock cycle phase fraction value for integral non-linearity distortion.

In accordance with an aspect of the invention, the rollover detector circuit includes a forward rollover detector circuit that detects when a forward interpolator rollover event has occurred, and a reverse rollover detector circuit that detects when a reverse interpolator rollover event has occurred.

In accordance with an aspect of the invention, the forward rollover detector circuit includes a circuit that compares an actual phase integer delta with an expected value of phase integer delta and detects that the forward interpolator rollover event has occurred when the actual value of the phase integer delta is equal to the expected value of the phase integer delta incremented by 1, and the reverse rollover detector circuit comprises a circuit that compares the delta between the actual value of the phase integer delta with the expected value of the phase integer delta and detects that the reverse interpolator rollover event has occurred when the actual value of the phase integer delta is equal to the expected value of the phase integer delta decremented by 1.

In accordance with an aspect of the invention, the circuit that compares the actual phase integer delta and detects that the forward interpolator rollover event has occurred when the compared delta is equal to the expected delta incremented by 1 includes a flip-flop having an input at which a current cumulative phase integer value appears and a output at which an immediately prior cumulative phase integer value appears, a subtractor that subtracts the current cumulative phase integer value from the immediately prior cumulative phase integer value to generate the actual phase integer delta, and a magnitude comparator that compares the output of the subtractor with the expected phase integer delta value incremented by 1, and the circuit that compares the actual phase integer delta and detects that the reverse interpolator rollover event has occurred when the delta is equal to the expected delta decremented by 1 includes the flip-flop having an input at which the current cumulative phase integer value appears and a output at which the immediately prior cumulative phase integer value appears, the subtractor that subtracts the current cumulative phase integer value from the immediately prior cumulative phase integer value to generate the actual phase integer delta, and a magnitude comparator that compares the output of the subtractor with the expected phase integer delta value decremented by 1.

In accordance with an aspect of the invention, the circuit further includes a circuit for setting a forward interpolator rollover event flag on a CARRY signal when a forward interpolator rollover event has been detected, and a circuit for setting a reverse interpolator rollover event flag on a CARRY signal when a reverse interpolator rollover event has been detected.

In accordance with an aspect of the invention, the correction circuit that adds a signed predistortion correction to the VCO clock cycle phase fraction value when the interpolator rollover event has been detected includes a forward signed predistortion correction circuit that adds a first forward signed predistortion correction to the VCO clock cycle phase fraction value on a CARRY signal following when the forward interpolator rollover event has been detected, and a reverse signed predistortion correction circuit that adds a first reverse signed predistortion correction to the VCO clock cycle phase fraction value on a CARRY signal following when the reverse interpolator rollover event has been detected.

In accordance with an aspect of the invention, the circuit further includes a circuit for setting a second forward interpolator rollover event flag on a CARRY signal following setting the forward interpolator rollover event flag, and a circuit for setting a second reverse interpolator rollover event flag on a CARRY signal following setting the reverse interpolator rollover event flag.

In accordance with an aspect of the invention, the circuit further includes a forward signed predistortion correction circuit for adding a forward signed predistortion correction to the VCO clock cycle phase fraction value on the CARRY signal following setting the second interpolator rollover event flag, and a reverse signed predistortion correction circuit for adding a reverse signed predistortion correction to the VCO clock cycle phase fraction value on the CARRY signal following setting the second interpolator rollover event flag.

In accordance with an aspect of the invention, the circuit further includes a second forward signed predistortion correction circuit for adding a second forward signed predistortion correction to the VCO clock cycle phase fraction value on the CARRY signal following setting the second interpolator rollover event flag, and a second reverse signed predistortion correction circuit for adding a second reverse signed predistortion correction to the VCO clock cycle phase fraction value on the CARRY signal following setting the second interpolator rollover event flag.

In accordance with an aspect of the invention, a method for correcting phase interpolator rollover integral non-linearity errors includes detecting when a rollover event of a phase interpolator has occurred, and adding a signed predistortion correction to the VCO clock cycle phase fraction value when the interpolator rollover event has been detected.

In accordance with an aspect of the invention, detecting when the interpolator rollover event has occurred includes determining whether a forward interpolator rollover event has occurred, and determining whether a reverse interpolator rollover event has occurred.

In accordance with an aspect of the invention, determining whether the forward interpolator rollover event has occurred includes comparing an actual phase integer delta between a current cumulative phase integer value and an immediately prior cumulative phase integer value with an expected phase integer delta and indicating that a forward interpolator rollover event has occurred when the actual phase integer delta is equal to the expected phase integer delta incremented by 1, and determining whether the reverse interpolator rollover event has occurred includes comparing the actual phase integer delta between the current cumulative phase integer value and the immediately prior cumulative phase integer value with the expected phase integer delta and indicating that a reverse interpolator rollover event has occurred when the actual phase integer delta is equal to the expected phase integer delta decremented by 1.

In accordance with an aspect of the invention, comparing the actual phase integer delta between the current cumulative phase integer value and the immediately prior cumulative phase integer value with the expected delta and indicating that the forward interpolator rollover event has occurred when the actual phase integer delta is equal to the expected delta incremented by 1 includes subtracting the current cumulative phase integer value from the immediately prior cumulative phase integer value, and comparing the difference with the expected phase integer delta value incremented by 1, and comparing the actual phase integer delta between the current cumulative phase integer value and the immediately prior cumulative phase integer value with the expected delta and indicating that the reverse interpolator rollover event has occurred when the actual phase integer delta is equal to the expected phase integer delta decremented by 1 includes subtracting the current cumulative phase integer value from the immediately prior cumulative phase integer value, and comparing the difference with the expected delta value decremented by 1.

In accordance with an aspect of the invention, indicating that the forward interpolator rollover event has occurred when the actual phase integer delta is equal to the expected phase integer delta incremented by 1 includes setting a forward interpolator rollover event flag, and indicating that the reverse interpolator rollover event has occurred when the actual phase integer delta is equal to the expected phase integer delta decremented by 1 includes setting a reverse interpolator rollover event flag.

In accordance with an aspect of the invention, adding the signed predistortion correction to the VCO clock cycle phase fraction value when the interpolator rollover event has been detected includes adding a first forward signed predistortion correction to the VCO clock cycle phase fraction value when the forward interpolator rollover event has been detected, and adding a first reverse signed predistortion correction to the VCO clock cycle phase fraction value when the reverse interpolator rollover event has been detected.

In accordance with an aspect of the invention, the method further includes adding a second forward signed predistortion correction to the VCO clock cycle phase fraction value after the first forward signed predistortion correction has been added to the VCO clock cycle phase fraction value, and adding a second reverse signed predistortion correction to the VCO clock cycle phase fraction value after the first forward signed predistortion correction has been added to the VCO clock cycle phase fraction value.

