CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2019-0164467, filed on Dec. 11, 2019, in the Korean Intellectual Property Office, and entitled: “Semiconductor Package and Method of Manufacturing the Same,” is incorporated by reference herein in its entirety.

BACKGROUND

1. Field

Embodiments relate to a semiconductor package and a method of manufacturing the same.

2. Description of the Related Art

A semiconductor package implements a semiconductor chip such as an integrated circuit in a form suitable for use in electronic products. Semiconductor packages have been developing in pursuit of miniaturization, weight reduction, and reduction of manufacturing costs.

SUMMARY

Embodiments are directed to a semiconductor package, including: a redistribution substrate having first and second surfaces, disposed opposite to each other, and including an insulating member and a plurality of redistribution layers disposed on a plurality of different levels in the insulating member, respectively, and electrically connected to each other; a plurality of under bump metallurgy (UBM) pads disposed in the insulating member and connected to a redistribution layer, among the plurality of redistribution layers, that is adjacent to the first surface of the redistribution substrate, the plurality of UBM pads having a lower surface exposed to the first surface of the redistribution substrate; a dummy pattern disposed between the plurality of UBM pads in the insulating member, the dummy pattern having a lower surface located at a level that is higher than the lower surface of the plurality of UBM pads; and at least one semiconductor chip disposed on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer, among the plurality of redistribution layers, that is adjacent to the second surface of the redistribution substrate.

Embodiments are also directed to a semiconductor package, including: a redistribution substrate having first and second surfaces disposed opposite to each other, and including a plurality of insulating layers and a plurality of redistribution layers disposed between the plurality of insulating layers, respectively; a plurality of under bump metallurgy (UBM) pads disposed in an insulating layer, among the plurality of insulating layers, that is adjacent to the first surface of the redistribution substrate, the plurality of UBM pads having a lower surface exposed to the first surface of the redistribution substrate and having a concave upper surface; a dummy pattern disposed on an adjacent insulating layer of the plurality of insulating layers, the dummy pattern having a lower surface located at a level that is higher than the lower surface of the plurality of UBM pads and having a convex upper surface; and at least one semiconductor chip disposed on the second surface of the redistribution substrate, and having a contact pad that is electrically connected to a redistribution layer of the plurality of redistribution layers.

Embodiments are also directed to a semiconductor package, including: a redistribution substrate having first and second surfaces disposed opposite to each other, and including an insulating member and a plurality of redistribution layers disposed on a plurality of different levels in the insulating member, respectively, to be electrically connected thereto; a plurality of under bump metallurgy (UBM) pads disposed in the insulating member to be exposed to the first surface of the redistribution substrate, and connected to a redistribution layer, among the plurality of redistribution layers, that is adjacent to the first surface of the redistribution substrate; a first dummy pattern spaced apart from the first surface of the redistribution substrate, and disposed between the plurality of UBM pads, the first dummy pattern having a thickness that is less than respective thicknesses of the plurality of UBM pads; and at least one semiconductor chip disposed on the second surface of the redistribution substrate, the at least one semiconductor chip having a plurality of contact pads electrically connected to a redistribution layer, among the plurality of redistribution layers, that is adjacent to the second surface of the redistribution substrate.

Embodiments are also directed to a method of manufacturing a semiconductor package, the method including: manufacturing a redistribution substrate; and disposing a semiconductor chip on the redistribution substrate. Manufacturing the redistribution substrate may include forming a first insulating film having a plurality of first openings; forming a first photoresist film having an opening overlapping the plurality of first openings, respectively, on the first insulating film; forming first metal patterns in the plurality of first openings, respectively; removing the first photoresist film, and forming a second photoresist film having a plurality of second openings in which the first metal pattern is opened, on the first insulating film, and a third opening disposed between the plurality of the second openings; forming second metal patterns in the plurality of second openings and the third opening, respectively; and removing the second photoresist film, and forming a second insulating film on the first insulating film to cover the second metal patterns. The first metal patterns of the plurality of first openings and the second metal patterns of the plurality of second openings may be provided as a plurality of under bump metallurgy (UBM) pads, and the second metal patterns of the third opening are provided as dummy patterns.

Embodiments are also directed to a method of manufacturing a semiconductor package, the method including: manufacturing a redistribution substrate; and disposing a semiconductor chip on the redistribution substrate. The manufacturing the redistribution substrate may include: forming a first insulating film having a plurality of first openings; forming a photoresist film having a plurality of second openings overlapping the plurality of first openings, respectively, on the first insulating film, and an opening for dummy pattern disposed between the second openings, the plurality of overlapping first and second openings providing a plurality of openings for under bump metallurgy (UBM) pads, respectively; forming a plurality of UBM pads and a dummy pattern in the opening for the plurality of UBMs and the opening for dummy pattern, respectively; and removing the photoresist film, and forming a second insulating film on the first insulating film to cover the plurality of UBM pads and the dummy pattern.

