TECHNICAL FIELD

The present disclosure relates to a circuit for selecting a voltage. In particular, the present disclosure relates to a voltage selection circuit for selecting a voltage from a plurality of input voltages.

BACKGROUND

FIG. 1Ais a schematic of a switch-based maximum voltage selector100in accordance with the prior art. The selector100is capable of directly driving a load102using an input voltage (Vin1, Vin2. . . VinN) when it is coupled to the load102via a closed switch.

Each input voltage may be selectively coupled to the load102via a switch104,106,108. In operation the switch104,106,108associated with the maximum of the input voltages is closed, whilst the other switches remain open.

FIG. 1Bis a schematic of a diode-based maximum voltage selector110in accordance with the prior art. The selector110is capable of directly driving the load102using the input voltage (Vin1, Vin2. . . VinN) with the largest value. Each input voltage is coupled to the load102via a diode112,114,116.

FIG. 1Cis a schematic of a circuit118that can provide an approximation of an ideal diode which may, for example, be provided as an implementation for the diodes112,114,116. The circuit118comprises an op-amp120and a real diode122.

The selector110ofFIG. 1Bmay be referred to as a diode network, which is for automatically selecting a maximum supply voltage. This circuit is seen commonly in battery back-up applications where a system has an internal power supply rail(s) powered primarily from an external supply (FIG. 1.83 on page 49, “The Art of Electronics”, P. Horowitz & W. Hill, 2nd edition, Cambridge University Press, 1990), but if the supply is removed then internal supply rail(s) must switch immediately to a (lower voltage) back-up battery without risking browning-out the internal rail(s) through any switch-over dead-time that leaves the internal rail(s) floating.

The selector110requires no additional power supplies beyond the input voltages to provide the power demanded by the load102; it is self-powered. If the diodes112.114,116are ideal (0 V forward voltage drop with no internal resistance and prefect reverse blocking) then:
Vout=max(Vin1,Vin2, . . . ,VinN)
and load current is supplied only from the largest input voltage source with all other diodes reverse-blocking. However, real diodes have a forward voltage drop when conducting current to a load102(typically 0.2-0.3 V for Schottky or germanium diodes, 0.7 V for silicon diodes—possibly more if diode forward resistance cannot be reduced) so that in practice, for silicon PN junction diodes:
Vout≈max(Vin1,Vin2, . . . ,VinN)−0.7 V.

In some applications the 0.7 V drop is unacceptable.

Ideal diodes can be implemented accurately using active circuits (e.g. sections 4.15-4.17, “The Art of Electronics”, P. Horowitz & W. Hill, 2nd edition, Cambridge University Press, 1990), e.g.FIG. 1Cand this implementation can provide an ideal rectifier network as the selector110. These are useful for applications such as analog computing, but they are usually not useful for driving the load102because:The output is driven by an op-amp(s)120not the input voltages. Using the op-amp120to drive the load102entails difficulties related to ensuring amplifier stability under possibly widely varying load impedances, designing the op-amp102for high output power handling etc.The diode122's forward voltage drop must still be overcome, requiring a supply voltage higher than any of the input voltages for the op-amp102, which may not be available; even if a higher supply is available, the op-amp102power dissipation could be considerable, giving heating problems and/or low power transfer efficiency.

FIG. 2is a schematic of a 2-input cross-coupled maximum selection switch circuit200. The circuit200uses pMOS transistors, however it will be appreciated that other transistor types may be used. The circuit200comprises transistors202,204. The transistor202is also labelled “M1”, and the transistor204is also labelled “M2”.

The circuit200outputs the larger of its two input voltages, Vin1and Vin2, by connecting the larger input voltage to the circuit200output via a switch (M1or M2). The circuit200comprises two pMOS power switches, M1and M2. Each switch M1, M2couples one of the input voltages Vin1, Vin2to the output and the switch gate is driven by the other input voltage Vin1, Vin2. Both FETs M1, M2have their bulk connected to the output voltage Vout to bias all bulks to the highest voltage and ensure all bulk-drain/source diodes stay reverse-biased.

The circuit200ofFIG. 2is simple and draws no current other than the load current but has a problem when both input voltages Vin1, Vin2are equal (or nearly equal). pMOS FETs have a threshold voltage, VTHP, and the gate voltage must be VTHP volts below the source (or drain) voltage for a conducting channel to form between the drain and source terminals (commonly referred to as the FET being “turned on”). If Vin1=Vin2then the desired Vout=max(Vin1, Vin2)=Vin1=Vin2, but this means both M1and M2have VGS=0 and so they will be turned-off (|VGS|<VTHP) and the output voltage Vout floats.

In practice, if the load current is drawn then the output voltage Vout will droop until one or both of the switches M1, M2turn on again, i.e. there is a dead-zone roughly ±VTHP wide around Vin1=Vin2(where VTHP is the pMOS threshold voltage) in which the output voltage Vout is driven only weakly via high switch resistances.FIG. 3is a graph showing results from a simulation of the circuit200, using simulation parameters that are representative of a practical implementation of the circuit200.FIG. 3is an example operation of the circuit200, showing the dead-zone problem when Vin1is approximately equal to Vin2.

FIG. 3shows a trace300of the input voltage Vin1as it varies with time, a trace302of the input voltage Vin2as it varies with time, a trace304of the output voltage Vout as it varies with time, a trace306of the maximum voltage Vmax as it varies with time, and a trace308of the load current as it varies with time.

The trace304shows the output voltage Vout as output by the circuit200, and the trace306shows the ideal output voltage which corresponds to the maximum voltage Vmax of the two input voltages Vin1, Vin2. For ideal operation of the circuit200, the traces304and306should be equal.

The following parameters were used in the simulation:0 V≤Vin1≤1.2 V and 0≤Vin2≤1.8 V and driving a 2 kΩ resistive load.The circuit implements M1and M2using pMOS FETs with VTHP≈0.64 V.

When Vin1=1.2 V or Vin2=1.8 V and the other input voltage=0V then Vout is switched strongly to the highest input voltage (the traces304and306are almost identical) even while driving load current, i.e. the circuit200operates as desired.

However, when Vin1and Vin2come within ≈0.64 V of each other both pMOS begin to turn off and Vout droops significantly (by up to 0.7 V in this example) below the desired Vout=max(Vin1, Vin2).

Also, Vout does not track max(Vin1, Vin2) well when Vin1and Vin2are below the pMOS threshold voltage as there is insufficient gate drive to properly turn on M1or M2.

The output voltage Vout droop caused by the dead-zone can be a problem in some applications.

FIG. 4is a schematic of a known improved 2-input cross-coupled maximum selection switch circuit400with a latch. The circuit400may be referred to as a cross-coupled pMOS switch with a latch.

The circuit400is a development of the circuit200that uses a latch to ensure that one switch, M1or M2, is always fully closed (gate pulled to ground for maximum possible VGS), and so avoid droop caused by both switches being off/weakly conductive when Vin1≈Vin2. Switches M3and M4with loads R1and R2form a cross-coupled latch driven by input voltages Vin1and Vin2.

When Vin1>Vin2, M3conducts pulling Vg2to Vin1, turning off M2and M4. With M4off, R2pulls Vg1to ground, ensuring M3and M1conduct strongly. M1turned on (conducting) connects Vin1to Vout as required.

When Vin2>Vin1, M4conducts pulling Vg1to Vin2, turning off M1and M3. With M3off, R1pulls Vg2to ground, ensuring M2and M4conduct strongly. M2turned on connects Vin2to Vout as required.

The latches are shown with resistive loads, but current sources, long-channel MOSFETs with large output conductance to emulate resistors, etc. can also be used as loads. It is also possible to use a latch with resistive pull-up and cross-coupled nMOS active pull-down. In all cases the basic operating principle is identical: use a voltage-driven latch to determine which of Vin1or Vin2is largest.

The M3and M4bulks are shown connected to Vout so that they can share a common N-well with M1and M2in integrated implementations, but the M3bulk could also connect to Vin1and the M4bulk to Vin2.

FIG. 5andFIG. 6are graphs showing results from a simulation of the circuit400, over different time scales and using simulation parameters that are representative of a practical implementation of the circuit400.

FIG. 5andFIG. 6shows a trace500of the input voltage Vin1as it varies with time, a trace502of the input voltage Vin2as it varies with time, a trace504of the output voltage Vout as it varies with time, and a trace506of the maximum voltage Vmax as it varies with time.

The trace504shows the output voltage Vout as output by the circuit200, and the trace506shows the ideal output voltage which corresponds to the maximum voltage Vmax of the two input voltages Vin1, Vin2. As for the circuit200, for ideal operation of the circuit400, the traces504and506should be equal.

The following parameters were used in the simulation:using pMOS devices with VTHP≈0.64 V,with R1=R1=1 MΩ,driving a 2 kΩ resistive load.

ComparingFIG. 5toFIG. 3, the Vout dead-zone/droop problem of the circuit200ofFIG. 2is resolved in the circuit400ofFIG. 4. However,FIG. 6shows that Vout does not always track max(Vin1, Vin2) accurately; there are input voltage tracking errors near Vin1=Vin2crossover comprising a narrow dip to a low Vout voltage just before Vout switch-over, and a Vout voltage error ≈0.4 V accumulates before Vout switches correctly to the new highest output voltage.

This tracking error arises because of the input voltage overdrive needed to flip the latch. ConsiderFIG. 6at time 8 ms when Vin1=1.2 V and Vin2=0 V, Vg1=0 V and Vg2=1.2 V, and Vout is connected to Vin1. As Vin2rises and exceeds Vin1, in order to flip the latch so that Vin2drives Vout, M4must turn on, which requires VGS(M4)≈VTHP; the circuit will not select the new largest input voltage until Vin2exceeds Vg2=Vin1by ≈VTHP. That is, there is a latch overdrive requirement that causes a Vout tracking error at input crossover. The same effect applies also when the largest voltage becomes the smallest voltage, as also seen inFIG. 6as Vin2ramps down from 1.8 V to 0 V. This can be a problem in low-voltage systems if the pMOS threshold voltage is high relative to the supply voltages.

Latch overdrive switching errors can be reduced by using low-VT devices for M3or M4, if available, or by reducing the threshold voltages of M3and M4via the body-effect using weak forward bias of the M3and M4source-bulk diodes. Bulk-switching/biasing for threshold voltage reduction is a well-known prior art (e.g. See T. Lehmann, M. Cassia “1 V power supply CMOS cascode amplifier”, IEE Journal of Solid-State Circuits, vol. 36, pp. 1082-1086, 2001). Bulk bias cannot reduce the threshold to 0 V though and reducing the threshold voltage too much increases off-state leakage which may inhibit correct latch function.

SUMMARY

It is desirable to provide a voltage selection circuit that overcomes or mitigates one or more of the above-mentioned problems.

According to a first aspect of the disclosure there is provided a voltage selection circuit for selecting a voltage from a plurality of input voltages comprising a plurality of diodes, each diode having a first terminal coupled to one of the input voltages, and a current sensor configured to sense a current flow through each diode, wherein the selected voltage is dependent on the sensed current flow.

Optionally, each diode comprises a transistor.

Optionally, the voltage selection circuit is configured to select a maximum voltage or a minimum voltage from the plurality of input voltages.

Optionally, each of the plurality of diodes comprises a second terminal, the voltage selection circuit comprising a resistive element, wherein the second terminals are coupled to a first node that is coupled to the resistive element, or a plurality of resistive elements wherein each of the second terminals is coupled to one of the resistive elements.

Optionally, the first terminal of each of the diodes is a cathode terminal and the second terminal of each of the diodes is an anode terminal, or the first terminal of each of the diodes is an anode terminal and the second terminal of each of the diodes is a cathode terminal.

Optionally, the voltage selection circuit comprises a plurality of power switches, wherein each power switch is configured to selectively couple one of the input voltages to an output terminal based on the selected voltage.

Optionally, each power switch comprises a power switch transistor.

Optionally, the selected voltage is the input voltage that is to be selectively coupled to the output terminal using one of the power switches.

Optionally, the current sensor is configured to sense the current flow through each of the diodes by mirroring the current flow through each of the diodes.

Optionally, the current sensor comprises a plurality of current mirrors, wherein each current mirror is i) associated with one of the diodes, and ii) configured to mirror the current flowing through its associated diode.

Optionally, each of the current mirrors comprises a current mirror transistor.

Optionally, the current sensor comprises a plurality of resistive elements, wherein each resistive element is i) coupled to one of the current mirror transistors and ii) configured to provide a sensed voltage that is dependent on the mirrored current provided to the resistive element.

Optionally, the voltage selection circuit comprises a plurality of power switches, wherein each power switch is configured to selectively couple one of the input voltages to an output terminal based on the selected voltage, and each of the power switches is configured to receive one or more of the sensed voltages, the selective coupling of each power switch being controlled by the one or more sensed voltages received by said power switch.

Optionally, each of the power switches is configured to receive one of the sensed voltages, the selective coupling of each power switch being controlled by the sensed voltage received by said power switch, each power switch comprises a transistor that comprises a gate, and the transistor has its gate coupled to the sensed voltage received by said power switch.

Optionally, each power switch comprises a logic circuit and the transistor has its gate coupled to the sensed voltage received by said power switch via the logic circuit.

Optionally, at least one of the logic circuits comprises an inverter.

Optionally, each of the power switches is configured to receive two or more of the sensed voltages, the selective coupling of each power switch being controlled by the two or more sensed voltages received by said power switch, each power switch comprises two or more transistors that each comprise a gate, and each transistor has its gate coupled to one of the two or more sensed voltages received by said power switch.

According to a second aspect of the disclosure there is provided a method of selecting a voltage from a plurality of input voltages comprising providing a plurality of diodes, each diode having a first terminal coupled to one of the input voltages, and sensing a current flow through each diode using a current sensor, wherein the selected voltage is dependent on the sensed current flow.

It will be appreciated that the method of the second aspect may include features set out in the first aspect and can incorporate other features as described herein.

