This application relates to U.S. Ser. No. 17/165,942, filed on Feb. 3, 2021, which is hereby incorporated by reference in its entirety.

FIELD OF THE INVENTION

The invention relates to data access generally and, more particularly, to a method and/or apparatus for implementing a hierarchical arbitration structure.

BACKGROUND

Modern computing demands low latency memory access. With an ever increasing need of more external memory bandwidth, the number of banks in a memory and the speed of memories is increasing. Memory access is efficient when accessing an open page and there is a penalty when there is a page miss. With high speed and high density memory, a page miss penalty also increases. LPDDR4 and LPDDR5 are examples of modern high speed and high density memories. A single LPDDR5 device, can have a 16 banks architecture that can be configured and accessed. However, without proper bank management, the memory access will not provide seamless data transfer.

The latest memories can have a burst size of 64 bytes and can complete a memory access transaction in two command cycles (32 bit DRAM bus). A page miss time (i.e., an amount of time taken to close a page and open another page in the same bank of a memory) can last for 50+ cycles. The page miss penalty results in a significant bandwidth loss.

Applications can be tuned to keep page misses to a minimum but, with so many processes running, page misses are hard to avoid completely. Memory controllers need to properly do page management to hide the time needed to close a page and open another page. To be able to sustain seamless data transfer, the opening and closing of pages in different memory banks need to be managed properly. However, memory controllers are also required to service requests in order to avoid memory coherency issues.

With the complexity of multiple DDR timing constraints and a large number of banks, a single arbitration logic becomes complicated. A complicated single arbitration logic has difficulty meeting the timing requirements in a high frequency system. A single arbitration logic also increases the difficulty in back-end design. Without efficient arbitration logic the advantages of modern memory devices will not be fully utilized.

It would be desirable to implement a hierarchical arbitration structure.

SUMMARY

The invention concerns an apparatus including a plurality of bank set arbitration circuits and a die arbitration circuit. The bank set arbitration circuits may each be configured to receive first commands and second commands and comprise a bank circuit configured to queue bank data in response to client requests and a set arbitration logic configured to queue the second commands in response to the bank data and perform arbitration for the first commands and said second commands. The die arbitration circuit may be configured to receive the first commands and the second commands from the bank set arbitration circuits and comprise a die-bank circuit configured to queue die data in response to the client requests and a die arbitration logic configured to queue the second commands in response to the die data and perform arbitration for the first commands and the second commands. Queuing the bank data and the die data for the second commands may enable the apparatus to maintain an order of the client requests for a random access memory and prioritize the first commands that correspond to a current bank set controller over the first commands that correspond to a non-current bank set controller.

