BACKGROUND

Some memory systems, e.g., NAND flash memories, experience data corruption which may impact data integrity. To prevent the data corruption, memory controllers can correct deficient memory cells or erase memory blocks suffering from severe data integrity such as read disturbance.

SUMMARY

The present disclosure describes systems and techniques for managing open blocks in memory systems, e.g., non-volatile memory systems such as NAND flash memory.

One aspect of the present disclosure features a memory system including: a memory including multiple blocks each having a plurality of pages associated with a plurality of word lines and a memory controller coupled to the memory. The memory controller is configured to: evaluate a read disturbance level of an open block, the open block including one or more programmed pages associated with one or more programmed word lines and one or more blank pages associated with one or more blank word lines; and in response to determining that the read disturbance level of the open block is beyond a threshold level, manage memory cells in at least one of the one or more blank word lines such that each memory cell in the at least one of the one or more blank word lines has a smaller data storing capacity than each memory cell in at least one of the one or more programmed word lines.

The memory controller can be configured to manage the memory cells in at least one of the one or more blank word lines such that data is represented by non-overlapping states of the memory cells in the at least one of one or more blank word lines.

In some embodiments, each memory cell in the at least one of the one or more programmed word lines has a first storing level for storing a first number of bits, and the memory controller can be configured to degrade each memory cell in the at least one of the one or more blank word lines to have a second storing level for storing a second number of bits, the second number being smaller than the first number. A difference between the first number and the second number can be identical to one of 1, 2, 3, and 4.

In some embodiments, the first number of bits represents a first number of states, and the second number of bits represents a second number of states, the second number of states being smaller than the first number of states, and the memory controller can be configured to degrade the memory cells in the at least one of the one or more blank word lines by configuring threshold voltage ranges of the memory cells in the at least one of the one or more blank word lines to represent the second number of states. The first number of states can be 2Nwhere N=2, 3 or 4 and the second number of states can be 2N-1.

In some embodiments, a first memory cell having the first storing level in a first erased state has a threshold voltage between a first higher limit voltage and a first lower limit voltage, and a second memory cell having the second storing level in a second erased state has a second threshold voltage between a second higher limit voltage and a second lower limit voltage, the second higher limit voltage being larger than the first higher limit voltage.

In some embodiments, the one or more programmed word lines include a first word line and a second word line, and memory cells in the second word line have a smaller storing level than memory cells in the first word line.

In some embodiments, each memory cell in the at least one of the one or more programmed word lines is capable of representing a first number of states, and the memory controller is configured to degrade each memory cell in the at least one of the one or more blank word lines to be capable of representing a second number of states, the second number being smaller than the first number. The memory controller can be configured to degrade the memory cells in the at least one of the one or more blank word lines by reconfiguring threshold voltage ranges of the second number of states representable by the memory cells in the at least one of the one or more blank word lines.

In some embodiments, the memory controller is configured to: degrade each memory cell in at least two adjacent blank word lines of the one or more blank word lines to be capable of representing the second number of states and combine at least two memory cells in the at least two adjacent word lines to represent a third number of states, each of the at least two memory cells being in a respective one of the at least two adjacent word lines, the third number of states being a combination of the second number of states of each of the at least two memory cells.

In some embodiments, each memory cell in the at least one of the one or more programmed word lines is capable of representing a series of states, and the memory controller is configured to: store data into memory cells in the at least one of the one or more blank word lines by representing the data by the memory cells in at least two selected states among the series of states, each of the at least two selected states having a threshold voltage higher than other unselected states among the series of states. For the memory cells in the at least one of the one or more blank word lines, the at least two selected states can be undisturbed states, and the other unselected states can be disturbed states.

In some embodiments, the memory cells in the at least one of the one or more blank word lines are programmable into a lower page and at least one higher page. The memory controller can be configured to program bits in the lower page to be a fixed pattern and program bits in the at least one higher page to represent the data. The lower page can include a least-significant-bit (LSB) page, and the at least one higher page can include a most-significant-bit (MSB) page.

In some embodiments, each memory cell in the at least one of the one or more programmed word lines is capable of representing a plurality of states including an erased state and a series of programmed states, each of the plurality of states having a respective threshold voltage range, and the memory controller is configured to determine that a memory cell in the open block has overlapping states at least by determining that the erased state of the memory cell has a higher limit voltage in a corresponding threshold voltage range of at least one of the series of programmed states. The memory controller can be configured to determine that the read disturbance level of the open block is beyond the threshold level by determining that a number of memory cells having overlapping states in one of the one or more blank word lines exceeds a threshold number.

In some embodiments, the memory controller is configured to determine that the read disturbance level of the open block is beyond the threshold level by determining that a number of error bits in one of the one or more programmed pages exceeds a threshold number. The memory controller can be configured to determine whether a bit in the one of the one or more programmed pages is an error bit by determining whether a state of a memory cell representing the bit has a threshold voltage higher than an original higher limit voltage of the state or whether the memory cell has overlapping states. The threshold number can be predetermined based on a number of correction bits in error correction codes (ECCs) for the one of the one or more programmed pages.

In some embodiments, the one of the one or more programmed pages is associated with a specific word line in the open block, memory cells in the specific word line being more sensitive to be disturbed than memory cells in other word lines in the open block.

In some cases, each bit in the one of the one or more programmed pages can be programmed to be a fixed value. In some cases, the one of the one or more programmed pages includes a series of sequential bits, and the memory controller can be configured to program at least one bit in at least one of a starting region or an ending region of the series of sequential bits to be a fixed value. In some cases, the one of the one or more programmed pages includes multiple chunks each having a series of sequential bits, and the memory controller can be configured to program at least one bit in at least one of a starting region or an ending region of the series of sequential bits in each of the chunks to be a fixed value. In some cases, the one of the one or more programmed pages includes a series of sequential bits, and the memory controller can be configured to program alternating bits in the series with data and a fixed value.

In some embodiments, the memory controller is configured to evaluate the read disturbance level based on at least one of characteristics of the open block, the characteristics of the open block including an erase count and a read count.

In some embodiments, the memory controller is configured to store user data or redundancy in memory cells in the at least one of the one or more blank word lines.

In some embodiments, the memory controller is configured to: evaluate a read disturbance level of a second open block, the second open block including one or more programmed pages and one or more blank pages, and in response to determining that the read disturbance level of the second open block is below the threshold level, store data in at least one of the one or more blank pages with a same data storing capacity as at least one of the one or more programmed pages.

In some embodiments, the memory controller is configured to: evaluate a read disturbance level of a second open block, the second open block including one or more second programmed pages and one or more second blank pages, and in response to determining that the read disturbance level of the second open block is beyond a second threshold level, migrate data stored in the one or more second programmed pages of the second open block then erase the second open block after the migration, the second threshold level being higher than the threshold level. The memory controller can be configured to manage the memory cells in the one or more blank word lines in the open block in response to determining that the read disturbance level of the open block is beyond the threshold level and below the second threshold level.

Another aspect of the present disclosure features a memory controller including at least one processor and at least one non-transitory machine-readable storage medium coupled to the at least one processor having machine-executable instructions stored thereon that, when executed by the at least one processor, cause the at least one processor to perform operations of the memory controller of the above aspect.

A further aspect of the present disclosure features a memory system including: a memory including multiple blocks each having a plurality of pages associated with a plurality of word lines; and a memory controller coupled to the memory and configured to manage memory cells in one or more blank word lines in an open block such that each memory cell in at least one of the one or more blank word lines has a smaller data storing capacity than each memory cell in at least one of one or more programmed word lines in the open block, then store data in the memory cells in the at least one of the one or more blank word line.

Implementations of the above techniques include methods, systems, computer program products and computer-readable media. In one example, a method can be performed by a memory controller coupled to a non-volatile memory and the method can include the above-described actions performed by the memory controller, e.g., the actions for managing open blocks in the non-volatile memory. In another example, one such computer program product is suitably embodied in a non-transitory machine-readable medium that stores instructions executable by one or more processors. The instructions are configured to cause the one or more processors to perform the above-described actions. One such computer-readable medium stores instructions that, when executed by one or more processors, are configured to cause the one or more processors to perform the above-described actions.

Implementations of the present disclosure provide systems and methods for managing open blocks in a memory device, such as an NAND flash memory, which can enable the use of open blocks that are impaired by read disturbance. In particular, blank pages in the open blocks that are impaired by read disturbance can be used to increase storage capability while maintaining data integrity and/or reducing write amplification (e.g., reducing to write more information due to read disturbance).

The techniques can be implemented for any type of memories suffering from read disturbance, data retention, and/or other disturbance effects. Besides blocks, the techniques can be implemented for sub-blocks within a block, which can better manage the block. The techniques can also be implemented for super blocks (or striped-blocks) that each combine multiple blocks from different planes, where the multiple blocks suffer from same read disturbance effect due to same read/erase/write operations.

The techniques can be applied to various types of volatile memory devices or non-volatile memory devices, such as NAND flash memory, NOR flash memory, resistive random-access memory (RRAM), phase-change random-access memory (PCRAM), among others. The techniques can be applied to two-dimensional (2D) memory devices or three-dimensional (3D) memory devices. The techniques can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices like 2-level cell devices, TLC (triple-level cell) devices, QLC (quad-level cell) devices, or PLC (penta-level cell) devices. Additionally or alternatively, the techniques can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC), or solid-state drives (SSDs), embedded systems, among others.

The details of one or more disclosed implementations are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings and the claims.

