CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims priority to Chinese patent application No. CN202010489472.3 filed on Jun. 2, 2020, and entitled “MANUFACTURING METHOD FOR A SEMICONDUCTOR DEVICE”, the disclosure of which is incorporated herein by reference in entirety.

TECHNICAL FIELD

The present invention relates to semiconductor device manufacturing technology, in particular, to a manufacturing method for a flash memory.

BACKGROUND

Flash memory devices have the advantages of non-volatility, easy programming and erasing, long service life, and low cost, etc. and have been widely applied to various fields including consumer electronics, network communication apparatuses, industrial instrument and meter embedded systems, automobile devices, etc.

In existing flash memory device structures, a NOR flash structure, for example, has three different gates:

1. a floating gate (also abbreviated as FG) of a memory transistor in a memory area, which is a basic data storage cell;

2. a control gate (also abbreviated as CG) of the memory transistor in the memory area, which is located over the floating gate, wherein an insulator is arranged between the floating gate and the control gate, and the control gate controls erasing, writing and reading of data in the floating gate; and

3. polycrystalline gates (also abbreviated as poly gate or PG) of various devices in a peripheral logic control area, wherein it can be understood that various devices in the peripheral logic control area may include a high-voltage P-type MOS transistor (HVPMOS), a high-voltage N-type MOS transistor (HVNMOS), a low-voltage P-type MOS transistor (LVPMOS), and a low-voltage N-type MOS transistor (LVNMOS), etc.

In the related arts, polycrystalline silicon of the CG and polycrystalline silicon of the PG grow simultaneously. Because of the differences of design rules and film structures, the polycrystalline silicon of the CG and the polycrystalline silicon of the PG are separately etched, the polycrystalline silicon of the CG is etched firstly to form the CG, and then the polycrystalline silicon of the PG is etched to form the PG. Different gate structures after etching are shown inFIG. 1. As shown inFIG. 1, a FG300and a CG400of the memory transistor are formed on the memory area A of the substrate100, and various peripheral device poly gates500are formed on a peripheral logic control area B of the substrate100.

For the flash memory device, cell lightly doped drain (Cell LDD) ion implantation is generally required on the memory transistor in the memory area, so as to inhibit a hot electron effect thereof. In the existing process, after the polycrystalline silicon of the CG and polycrystalline silicon of the PG are etched separately to form the CG and the PG, gate re-oxidation and self-aligned source etching, implantation and annealing processes are performed, and then a process step of lightly doped drain ion implantation for the transistor in the memory area is performed. That is, in the existing process, after the source800is formed through a self-aligned source process, the process step of lightly doped drain ion implantation for the transistor in the memory area is also performed.

FIG. 2shows a schematic diagram of lightly doped drain ion implantation for the transistor in the memory area in the existing process. Specifically, a photo resist (PR)600is used for covering the peripheral logic control area B, and lightly doped drain ion implantation is performed only on the memory area A, so as to form a memory cell lightly doped drain CLDD700on an outer side of a gate structure of the memory transistor.

There is room for improvement for the existing process integration at least for the two aspects below:

1. After self-aligned source etching, the structure of the memory transistor source is complicated, so it is easy to include defects such as particles in the trench, and these defects may block some of the cell LDD implantation; and

2. The thermal budget may not be sufficient after cell LDD implantation, leading to unrepaired lattice damage caused by ion implantation and non-uniform ion diffusion.

The above two aspects may result in poor device uniformity among memory transistors. When an erase function of all memory cells on the same chip does not occur in the same interval, a serious condition such as an erase failure may result in poor device performance.

Therefore, a proper manufacturing method for solving this problem is urgently needed, so as to improve the poor uniformity of lightly doped drain ion implantation of the memory cell of the flash memory device in the current process.

BRIEF SUMMARY

The following is a summary of the disclosure. This summary is not an extensive overview of all conceivable aspects and is not intended to identify key or critical elements of all aspects or delimit the scope of any or all aspects. The sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to more detailed description that is presented later.

A manufacturing method for a semiconductor device, comprising: providing a substrate comprising a memory area and a peripheral area, wherein the memory area comprises a memory transistor having a memory gate structure, wherein the peripheral area comprises a peripheral transistor having a peripheral gate structure, and wherein the peripheral gate structure comprises a first layer; performing ion implantation to form a lightly doped drain on two sides of the memory gate structure of the memory transistor on an upper part of the memory area of the substrate, wherein the first layer masks the peripheral area; and etching the first layer to form the peripheral gate structure of the peripheral transistor.

Optionally, the manufacturing method further comprises: performing gate re-oxidation treatment on the memory gate structure of the memory transistor and the peripheral gate structure of the peripheral transistor, wherein the gate re-oxidation treatment thermally treats the lightly doped drain.

Optionally, the manufacturing method further comprises: performing a self-aligned source process to form a source of the memory transistor on the upper part of the memory area of the substrate, wherein the lightly doped drain is thermally treated in the self-aligned source process.

Optionally, the self-aligned source process further comprises: performing a self-aligned source etching, a self-aligned source ion implantation and a self-aligned source annealing, wherein the lightly doped drain is thermally treated in the self-aligned source annealing.

Optionally, the memory area of the substrate comprises a stacked gate layer of the memory transistor formed on the upper surface of the memory area of the substrate; and wherein the stacked gate layer is etched to form the memory gate structure of the memory transistor.

Optionally, the method further comprising: sequentially from bottom up depositing a memory gate dielectric layer, a floating gate layer, a dielectric interlayer and a control gate layer on an upper surface of the memory area of the substrate.

Optionally, the first layer comprises a peripheral gate dielectric layer and a peripheral gate layer on the peripheral gate dielectric layer sequentially deposited on an upper surface of the peripheral area of the substrate.

Optionally, the peripheral gate dielectric layer of the peripheral area and the memory gate dielectric layer of the memory area are formed in a same process step.

Optionally, the peripheral gate layer of the peripheral area and the control gate layer of the memory area are formed in a same process step.

Optionally, the peripheral gate layer of the peripheral area and the control gate layer of the memory area comprise polycrystalline silicon.

In one embodiment of the above manufacturing method, optionally, the gate layer of the peripheral area and the CG layer of the memory area are formed in the same step.

In one embodiment of the above manufacturing method, optionally, the gate layer of the peripheral area and the CG layer of the memory area are polycrystalline silicon.

According to the manufacturing method for the semiconductor device provided in the present invention, the step of lightly doped drain ion implantation in the memory area is executed, and on the premise that we don't change the structure and the design of the original device and adjusting the ion implantation conditions, the physical structure before implantation is simpler, the possibility that implanted ions are blocked by defects is reduced, and in addition, damage caused by ion implantation is repaired by means of increased thermal budget from the subsequent process, and at the same time the ion diffusion is more uniform. Finally, the effect of improving the electrical uniformity of the memory cell is achieved, and the yield and the erase performance of the flash memory cell are effectively improved. Moreover, according to the manufacturing method for the semiconductor device provided in the present invention, when lightly doped drain ion implantation is performed on the memory area, no need to add the photo resist in the peripheral device area, such that we can save a layer of photomask, thus the manufacturing cost may be reduced.

