CROSS-REFERENCE TO RELATED APPLICATION

This application is a national stage application under 35 U.S.C. § 371 of International Application No. PCT/CN2019/077691, filed Mar. 11, 2019, the contents of which are incorporated by reference in the entirety.

TECHNICAL FIELD

The present invention relates to display technology, more particularly, to a display substrate, a display apparatus, and a method of fabricating a display substrate.

BACKGROUND

Organic light emitting diode (OLED) display apparatuses are self-emissive devices, and do not require backlights. OLED display apparatuses also provide more vivid colors and a larger color gamut as compared to the conventional liquid crystal display (LCD) apparatuses. Further, OLED display apparatuses can be made more flexible, thinner, and lighter than a typical LCD apparatuses.

SUMMARY

In one aspect, the present invention provides a display substrate having a display area and a peripheral area, comprising a base substrate; a first power pad on the base substrate, the first power pad comprising a first portion in the peripheral area and along a power line interface side of the display substrate; a planarization layer on a side of the first power pad away from the base substrate; a pixel definition layer on a side of the planarization layer away from the base substrate, defining a plurality of subpixel apertures; and an encapsulating layer on a side of the pixel definition layer away from the base substrate; wherein the display substrate comprises a first groove extending through one or a combination of the planarization layer and the pixel definition layer, exposing a surface of the first portion of the first power pad in the peripheral area; and the encapsulating layer extends into the first groove and is in direct contact with the surface of the first portion, thereby encapsulating the display substrate.

Optionally, the encapsulating layer completely covers the surface of the first portion.

Optionally, the first portion comprises a first side away from the base substrate, a second side opposite to the first side and closer to the base substrate, a third side connecting the first side and the second side and closer to the display area, and a fourth side connecting the first side and the second side, the fourth side being opposite to the third side and away from the display area the fourth side of the first portion is covered by one or a combination of the pixel definition layer and the planarization layer; and the first groove exposes a portion of the first side.

Optionally, the fourth side has a concave surface.

Optionally, the first portion comprises at least one sublayer that is over-etched on the fourth side, thereby forming the concave surface.

Optionally, the encapsulating layer comprises a first inorganic encapsulating sub-layer, the first inorganic encapsulating sub-layer extending into the first groove and being in direct contact with the surface of the first portion.

Optionally, in a region corresponding to the first groove, the encapsulating layer further comprises an organic encapsulating sub-layer on a side of the first inorganic encapsulating sub-layer away from the base substrate, and a second inorganic encapsulating sub-layer on a side of the organic encapsulating sub-layer away from the first inorganic encapsulating sub-layer.

Optionally, the first power pad further comprises at least one second portion connected to the first portion and extending from the first portion away from the display area; and the at least one second portion is at least partially covered by one or a combination of the pixel definition layer and the planarization layer.

Optionally, the display substrate further comprises a second groove extending through one or a combination of the planarization layer and the pixel definition layer, exposing a surface of the at least one second portion of the first power pad in the peripheral area; and the encapsulating layer extends into the second groove and is in direct contact with the surface of the at least one second portion.

Optionally, the encapsulating layer comprises a first inorganic encapsulating sub-layer, the first inorganic encapsulating sub-layer extending into the second groove and being in direct contact with the surface of the at least one second portion.

Optionally, in a region corresponding to the second groove, the encapsulating layer further comprises an organic encapsulating sub-layer on a side of the first inorganic encapsulating sub-layer away from the base substrate, and a second inorganic encapsulating sub-layer on a side of the organic encapsulating sub-layer away from the first inorganic encapsulating sub-layer.

Optionally, the at least one second portion comprises two second portions connected to the first portion respectively at different locations and extending from the first portion away from the display area; and the first portion and the two second portions form a pi-shaped structure.

Optionally, the display substrate further comprises a second power pad on the base substrate and in the peripheral area, the second power pad spaced apart from the first power pad; wherein the second power pad comprises at least one third portion on the power line interface side of the display substrate, the at least one third portion at least partially covered by one or a combination of the pixel definition layer and the planarization layer; the second groove extends through one or a combination of the planarization layer and the pixel definition layer, further exposing a surface of the at least one third portion of the second power pad in the peripheral area; and the encapsulating layer extends into the second groove and is in direct contact with the surface of the at least one third portion.

Optionally, the display substrate further comprises a second power pad on the base substrate and in the peripheral area, the second power pad spaced apart from the first power pad; wherein the second power pad comprises at least one third portion on the power line interface side of the display substrate, the at least one third portion at least partially covered by one or a combination of the pixel definition layer and the planarization layer; the at least one third portion is on a side of the first portion extending away from the display area, the first portion and a respective one of the at least one third portion being spaced apart by a first gap; and the first groove is on a side of the first gap closer to the display area.

Optionally, the planarization layer at least extends into the first gap.

Optionally, the first power pad further comprises at least one second portion connected to the first portion and extending from the first portion away from the display area; the at least one second portion is at least partially covered by one or a combination of the pixel definition layer and the planarization layer; and the at least one second portion and the at least one third portion are on a side of the first portion extending away from the display area, a respective one of the at least one second portion being spaced apart from a respective one of the at least one third portion by a second gap connected to the first gap.

Optionally, the planarization layer extends into the first gap and the second gap.

Optionally, the display substrate further comprises a third groove extending through one or a combination of the planarization layer and the pixel definition layer, exposing a surface of the at least one second portion of the first power pad in the peripheral area; the encapsulating layer comprises a first inorganic encapsulating sub-layer, the first inorganic encapsulating sub-layer extending into the third groove and being in direct contact with the surface of the at least one second portion; in a region corresponding to the third groove, the encapsulating layer further comprises a second inorganic encapsulating sub-layer on a side of the first inorganic encapsulating sub-layer away from the base substrate, the second inorganic encapsulating sub-layer being in direct contact with the first inorganic encapsulating sub-layer.

Optionally, the first power pad is selected from a group consisting of a VDD power pad connected to a plurality of VDD high voltage power lines and a VSS power pad connected to a plurality of VSS low voltage power lines.

In another aspect, the present invention provides a display apparatus, comprising the display substrate described herein or fabricated by a method described herein, and one or more integrated circuits connected to the display substrate.

In another aspect, the present invention provides a method of fabricating a display substrate, comprising forming a first power pad on a base substrate, the first power pad formed to comprise a first portion in the peripheral area and along a power line interface side of the display substrate; forming a planarization layer on a side of the first power pad away from the base substrate; forming a pixel definition layer on a side of the planarization layer away from the base substrate, defining a plurality of subpixel apertures; forming a first groove extending through one or a combination of the planarization layer and the pixel definition layer, exposing a surface of the first portion of the first power pad in the peripheral area; and forming an encapsulating layer on a side of the pixel definition layer away from the base substrate, the encapsulating layer formed to extend into the first groove and be in direct contact with the surface of the first portion, thereby encapsulating the display substrate.

