This application is a US National Stage of International Application No. PCT/CN2019/098231, filed Jul. 29, 2019, which claims priority to Chinese Patent Application No. 201811345139.4, filed with Chinese Patent Office on Nov. 13, 2018, entitled “Shift Register Unit, Driving Method thereof, Gate Drive Circuit, and Related Device”, which is incorporated herein by reference in its entirety.

FIELD

The present disclosure relates to the field of display technology, and particularly relates to a shift register, a driving method thereof, a gate drive circuit, an array substrate and a display device.

BACKGROUND

With the rapid development of display technology, display panels are increasingly developing towards high integration and a low cost. The gate driver on array (GOA) technology integrates a thin film transistor (TFT) gate drive circuit on an array substrate of a display panel to achieve scanning drive of the display panel, so that a wiring space for a bonding area and fan-out area of a gate integrated circuit (IC) can be omitted. A general gate drive circuit includes a plurality of cascaded shift registers, where the shift register in each stage is correspondingly connected to one gate line, so as to successively input scan signals to rows of gate lines on the display panel through the shift registers in the stages.

However, as each row of gate line is correspondingly connected to one shift register, the structural design of the gate drive circuit is complicated, and the space occupied by the display panel is large, which is not conducive to the design of a narrow frame.

SUMMARY

An embodiment of the present disclosure provides a shift register, including: a signal control circuit coupled to an input signal terminal and a reset signal terminal; a branch control circuit coupled to a first output terminal of the signal control circuit; a cascade signal output circuit coupled to a cascade signal output terminal and a second output terminal of the signal control circuit; and at least two scan signal output circuits, where one of the at least two scan signal output circuits is coupled to the second output terminal of the signal control circuit, at least one corresponding scan signal output terminal, and one corresponding output terminal of the branch control circuit.

Optionally, in an embodiment of the present disclosure, the cascade signal output circuit is coupled to one output terminal of the branch control circuit.

Optionally, in an embodiment of the present disclosure, the at least two scan signal output circuits include two scan signal output circuits, which are a first scan signal output circuit and a second scan signal output circuit; the first scan signal output circuit is coupled to a first output terminal of the branch control circuit; and the second scan signal output circuit is coupled to a second output terminal of the branch control circuit.

Optionally, in an embodiment of the present disclosure, the branch control circuit includes a first transistor and a second transistor; under the control of an effective level, the first transistor communicates the first output terminal of the signal control circuit with the first output terminal of the branch control circuit; and under the control of an effective level, the second transistor communicates the first output terminal of the signal control circuit with the second output terminal of the branch control circuit.

Optionally, in an embodiment of the present disclosure, a gate of the first transistor and a first electrode of the first transistor are coupled to the first output terminal of the signal control circuit, and a second electrode of the first transistor is the first output terminal of the branch control circuit; and a gate of the second transistor and a first electrode of the second transistor are coupled to the first output terminal of the signal control circuit, and a second electrode of the second transistor is the second output terminal of the branch control circuit.

Optionally, in an embodiment of the present disclosure, a gate of the first transistor is coupled to a first reference signal terminal, a first electrode of the first transistor is coupled to the first output terminal of the signal control circuit, and a second electrode of the first transistor is the first output terminal of the branch control circuit; and a gate of the second transistor is coupled to the first reference signal terminal, a first electrode of the second transistor is coupled to the first output terminal of the signal control circuit, and a second electrode of the second transistor is the second output terminal of the branch control circuit.

Optionally, in an embodiment of the present disclosure, the first scan signal output circuit includes at least one first sub-scan signal output circuit, where one of the at least one first sub-scan signal output circuit is coupled to a second reference signal terminal, one corresponding first clock signal terminal, and one corresponding first sub-scan signal output terminal, respectively.

Optionally, in an embodiment of the present disclosure, the first sub-scan signal output circuit includes a third transistor, a fourth transistor and a first capacitor; a gate of the third transistor is coupled to the first output terminal of the branch control circuit, a first electrode of the third transistor is coupled to the corresponding first clock signal terminal, and a second electrode of the third transistor is coupled to the corresponding first sub-scan signal output terminal; a gate of the fourth transistor is coupled to the second output terminal of the signal control circuit, a first electrode of the fourth transistor is coupled to the second reference signal terminal, and a second electrode of the fourth transistor is coupled to the corresponding first sub-scan signal output terminal; and the first capacitor is coupled between the gate of the third transistor and the corresponding first sub-scan signal output terminal.

Optionally, in an embodiment of the present disclosure, the second scan signal output circuit includes at least one second sub-scan signal output circuit, where one of the at least one second sub-scan signal output circuit is coupled to a second reference signal terminal, one corresponding second clock signal terminal, and one corresponding second sub-scan signal output terminal, respectively.

Optionally, in an embodiment of the present disclosure, the second sub-scan signal output circuit includes a fifth transistor, a sixth transistor and a second capacitor; a gate of the fifth transistor is coupled to the second output terminal of the branch control circuit, a first electrode of the fifth transistor is coupled to the corresponding second clock signal terminal, and a second electrode of the fifth transistor is coupled to the corresponding second sub-scan signal output terminal; a gate of the sixth transistor is coupled to the second output terminal of the signal control circuit, a first electrode of the sixth transistor is coupled to the second reference signal terminal, and a second electrode of the sixth transistor is coupled to the corresponding second sub-scan signal output terminal; and the second capacitor is coupled between the gate of the fifth transistor and the second sub-scan signal output terminal.

Optionally, in an embodiment of the present disclosure, the cascade signal output circuit includes a seventh transistor and an eighth transistor; a gate of the seventh transistor is coupled to the first output terminal of the branch control circuit, a first electrode of the seventh transistor is coupled to a third clock signal terminal, and a second electrode of the seventh transistor is coupled to the cascade signal output terminal; and a gate of the eighth transistor is coupled to the second output terminal of the signal control circuit, a first electrode of the eighth transistor is coupled to a third reference signal terminal, and a second electrode of the eighth transistor is coupled to the cascade signal output terminal.

Optionally, in an embodiment of the present disclosure, the signal control circuit includes an input circuit, a reset circuit, and a node control circuit; the input circuit is coupled to the input signal terminal, a first reference signal terminal and the first output terminal of the signal control circuit, respectively; the reset circuit is coupled to the reset signal terminal, a third reference signal terminal, and the first output terminal of the branch control circuit and the second output terminal of the branch control circuit, respectively; and the node control circuit is coupled to the first reference signal terminal, the third reference signal terminal, the first output terminal of the signal control circuit and the second output terminal of the signal control circuit, and the first output terminal of the branch control circuit and the second output terminal of the branch control circuit, respectively.

Optionally, in an embodiment of the present disclosure, the input circuit includes a ninth transistor, where a gate of the ninth transistor is coupled to the input signal terminal, a first electrode of the ninth transistor is coupled to the first reference signal terminal, and a second electrode of the ninth transistor is coupled to the first output terminal of the signal control circuit; the reset circuit includes a tenth transistor and an eleventh transistor, where a gate of the tenth transistor is coupled to the reset signal terminal, a first electrode of the tenth transistor is coupled to the third reference signal terminal, and a second electrode of the tenth transistor is coupled to the first output terminal of the branch control circuit; and a gate of the eleventh transistor is coupled to the reset signal terminal, a first electrode of the eleventh transistor is coupled to the third reference signal terminal, and a second electrode of the eleventh transistor is coupled to the second output terminal of the branch control circuit; and the node control circuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a fifteenth transistor, where a gate of the twelfth transistor is coupled to the second output terminal of the signal control circuit, a first electrode of the twelfth transistor is coupled to the third reference signal terminal, and a second electrode of the twelfth transistor is coupled to the first output terminal of the branch control circuit; a gate of the thirteen transistor is coupled to the second output terminal of the signal control circuit, a first electrode of the thirteen transistor is coupled to the third reference signal terminal, and a second electrode of the thirteen transistor is coupled to the second output terminal of the branch control circuit; a gate of the fourteenth transistor and a first electrode of the fourteenth transistor are coupled to the first reference signal terminal, and a second electrode of the fourteenth transistor is coupled to the second output terminal of the signal control circuit; and a gate of the fifteenth transistor is coupled to the first output terminal of the signal control circuit, a first electrode of the fifteenth transistor is coupled to the third reference signal terminal, and a second electrode of the fifteenth transistor is coupled to the second output terminal of the signal control circuit.

Optionally, in an embodiment of the present disclosure, the reset circuit further includes a sixteenth transistor, where the first electrode of the tenth transistor and the first electrode of the eleventh transistor are coupled to the third reference signal terminal through the sixteenth transistor; and a gate of the sixteenth transistor is coupled to the reset signal terminal; and the node control circuit further includes a seventeenth transistor, where the first electrode of the twelfth transistor and the first electrode of the thirteenth transistor are respectively coupled to the third reference signal terminal through the seventeenth transistor; and a gate of the seventeenth transistor is coupled to the second output terminal of the signal control circuit.

Optionally, in an embodiment of the present disclosure, the shift register a detection circuit, where the detection circuit includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor and a third capacitor; a gate of the eighteenth transistor is coupled to a first detection control signal terminal, a first electrode of the eighteenth transistor is coupled to the input signal terminal, and a second electrode of the eighteenth transistor is coupled to a first electrode of the twentieth transistor; a gate of the nineteenth transistor is coupled to the first detection control signal terminal, a first electrode of the nineteenth transistor is coupled to a gate of the twenty-first transistor, and a second electrode of the nineteenth transistor is coupled to the first electrode of the twentieth transistor; a gate of the twentieth transistor is coupled to the gate of the twenty-first transistor, and a second electrode of the twentieth transistor is coupled to a fourth reference signal terminal; a first electrode of the twenty-first transistor is coupled to the fourth reference signal terminal, and a second electrode of the twenty-first transistor is coupled to a first electrode of the twenty-second transistor; a gate of the twenty-second transistor is coupled to a second detection control signal terminal, and a second electrode of the twenty-second transistor is coupled to the first output terminal of the signal control circuit; and the third capacitor is coupled between the first electrode of the twenty-first transistor and the gate of the twenty-first transistor.

Correspondingly, an embodiment of the present disclosure also provides a gate drive circuit, including a plurality of cascaded shift registers provided in the above embodiments of the present disclosure; an input signal terminal of a first-stage shift register is coupled to a frame start signal terminal; in every adjacent four stages of shift registers, an input signal terminal of a fourth-stage shift register is coupled to a cascade signal input terminal of the first-stage shift register; and in every adjacent five stages of shift registers, a reset signal terminal of the first-stage shift register is coupled to a cascade signal input terminal of a fifth-stage shift register.

Correspondingly, an embodiment of the present disclosure also provides an array substrate, including the gate drive circuit provided in an embodiment of the present disclosure.

Correspondingly, an embodiment of the present disclosure also provides a display device, including the array substrate provided in an embodiment of the present disclosure.

Correspondingly, an embodiment of the present disclosure also provides a driving method of the shift register provided in an embodiment of the present disclosure, including a display scanning phase, where the display scanning phase includes an input phase, an output phase and a reset phase; in the input phase, the signal control circuit controls a signal of the first output terminal of the signal control circuit and a signal of the second output terminal of the signal control circuit in response to a signal of the input signal terminal; the branch control circuit controls output signals of output terminals of the branch control circuit in response to the signal of the first output terminal of the signal control circuit; the cascade signal output circuit controls the cascade signal output terminal to output a cascade signal in response to the output signal of one output terminal of the branch control circuit; and each of the scan signal output circuits controls at least one corresponding scan signal output terminal to output a different scan signal in response to the signal of one corresponding output terminal of the branch control circuit; in the output phase, the branch control circuit controls output signals of output terminals of the branch control circuit in response to a signal of the first output terminal of the signal control circuit; the cascade signal output circuit controls the cascade signal output terminal to output a cascade signal in response to the output signal of one output terminal of the branch control circuit; and each of the scan signal output circuits controls at least one corresponding scan signal output terminal to output a different scan signal in response to the signal of one corresponding output terminal of the branch control circuit; and in the reset phase, the signal control circuit controls signals of the first output terminal and the second output terminal of the signal control circuit in response to a signal of the reset signal terminal; the cascade signal output circuit controls the cascade signal output terminal to output a cascade signal in response to the output signal of one output terminal of the branch control circuit; and each of the scan signal output circuits outputs a different scan signal in response to a signal of a corresponding output control node.

Optionally, in an embodiment of the present disclosure, the scan signal output circuits include two scan signal output circuits, which are a first scan signal output circuit and a second scan signal output circuit; the first scan signal output circuit includes a plurality of first sub-scan signal output circuits; and the second scan signal output circuit includes a plurality of second sub-scan signal output circuits; in the input phase and the output phase, each of the first sub-scan signal output circuits provides a signal of a corresponding first clock signal terminal to a corresponding first sub-scan signal output terminal in response to a signal of a first output terminal of the branch control circuit; each of the second sub-scan signal output circuits provides a signal of a corresponding second clock signal terminal to a corresponding second sub-scan signal output terminal in response to a signal of a second output terminal of the branch control circuit; and the cascade signal output circuit provides a signal of a third clock signal terminal to the cascade signal output terminal in response to a signal of the first output terminal of the branch control circuit; and in the reset phase, each of the first sub-scan signal output circuits provides a signal of a second reference signal terminal to a corresponding first sub-scan signal output terminal in response to a signal of the second output terminal of the signal control circuit; each of the second sub-scan signal output circuits provides the signal of the second reference signal terminal to a corresponding second sub-scan signal output terminal in response to the signal of the second output terminal of the signal control circuit; and the cascade signal output circuit provides a signal of a third reference signal terminal to the cascade signal output terminal in response to the signal of the second output terminal of the signal control circuit.

Optionally, in an embodiment of the present disclosure, in the display scanning phase, signal timings of the first clock signal terminals are same, and signal timings of the second clock signal terminals are same, and the signal timings of the first clock signal terminals are different from those of the second clock signal terminals.

