CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims priority under 35 USC 119 from Japanese Patent Application No. 2018-042577 filed Mar. 9, 2018.

BACKGROUND

(i) Technical Field

The present invention relates to an image processing apparatus and a non-transitory computer readable medium storing a program.

(ii) Related Art

There is known a technique relating to a storage process of storing image data or the like to be processed by an image processing apparatus in a storage unit such as a memory.

For example, JP2000-029782A discloses a memory control device that converts a logical address group representing two segments including a predetermined number of consecutive identical column address groups on the same row addresses of two frame buffers into a real address group representing two consecutive segments on the same row address.

Further, JP2014-178745A discloses a memory control device which executes address mapping by allocating lower N bits of a burst transfer size, among main-scanning addresses, to lower bits of column addresses, and a predetermined number of bits following the higher side to the bank addresses, in allocation of main-scanning addresses indicating pixel positions in a main-scanning direction and sub-scanning addresses indicating pixel positions in a sub-scanning direction in an image to column addresses, row addresses, and bank addresses on an SDRAM, and reads or writes one line in the main-scanning direction by consecutively executing burst transfer plural times by multi-bank operation while changing the sub-scanning addresses at the break of the burst transfer.

Further, JP2012-168372A discloses an imaging forming apparatus which sets sub-scanning position information according to the profile of misregistration and constitutes an image correction process by processes of two stages, that is, a high-resolution correction process using a line buffer including a memory capable of high-speed random access and a low-resolution correction process using a memory that is easy to increase in capacity.

SUMMARY

In a case of performing a process of shifting plural pieces of pixel data so as to suppress deviation in the sub-scanning direction at the time of image formation, a process of writing data to a storage unit through a cache memory may be performed in some cases. In the process of writing pixel data to the cache memory, in a case where the storage destination address of each piece of pixel data, which is the unit of processing of a shift process, is apart by not less than the page size of the cache memory, after performing the process of writing pixel data of a unit of processing to the cache memory, it is necessary to perform extra processes such as sweeping out data from the cache memory before performing the process of writing the next pixel data of the same unit of processing. Aspects of non-limiting embodiments of the present disclosure relate to an image processing apparatus and a non-transitory computer readable medium storing a program, in which such extra processes are reduced.

Aspects of certain non-limiting embodiments of the present disclosure overcome the above disadvantages and other disadvantages not described above. However, aspects of the non-limiting embodiments are not required to overcome the disadvantages described above, and aspects of the non-limiting embodiments of the present disclosure may not overcome any of the problems described above.

According to an aspect of the present disclosure, there is provided an image processing apparatus including a processing unit that shifts a plurality of pieces of pixel data so as to suppress deviation in a sub-scanning direction at the time of image formation; a storage unit that stores the plurality of pieces of pixel data; and a converting unit that converts addresses of the plurality of pieces of pixel data such that a predetermined number of pieces of pixel data which are a unit of processing of the shift process are stored in a cache memory used by the storage unit at once.

