CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0055520, filed on May 13, 2019, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field

The present disclosure relates to semiconductor devices having landing pads.

2. Description of Related Art

Due to demands for miniaturization and weight reduction of semiconductor devices, circuit patterns of semiconductor devices have been downscaled. With a reduction in design rules, sizes of lower electrodes of capacitors have decreased, and aspect ratios have increased. Thus, resistances of the lower electrodes may increase, and/or device reliability may decrease.

SUMMARY

Example embodiments of the inventive concept provide a semiconductor device including a landing pad and an electrode connected to the landing pad.

According to example embodiments, there is provided a semiconductor device including a landing pad, a first insulating pattern in contact with a lower portion of a first side surface of the landing pad, a pad oxide layer having a lateral portion disposed on a portion of an upper surface of the landing pad and a vertical portion in contact with an upper portion of the first side surface of the landing pad, a second insulating pattern in contact with an upper surface of the first insulating pattern and covering the first insulating pattern and the pad oxide layer, and a lower electrode that vertically passes through the second insulating pattern and is in contact with a portion of the upper surface and an upper portion of a second side surface of the landing pad, the second side surface opposite to the first side surface.

According to example embodiments, there is provided a semiconductor device including a plurality of landing pads, a plurality of first insulating patterns in contact with lower portions of first side surfaces of the plurality of landing pads, a plurality of pad oxide layers each of which includes a lateral portion disposed on an upper surface of one of the plurality of landing pads and a vertical portion in contact with an upper portion of a first side surface of the one of the plurality of landing pads, a plurality of second insulating patterns in contact with upper surfaces of the plurality of first insulating patterns and covering the plurality of first insulating patterns and the plurality of pad oxide layers, and a plurality of lower electrodes vertically passing through the plurality of second insulating patterns, each of the plurality of lower electrodes having a first portion in contact with a second side surface of the one of the plurality of landing pads and a second portion disposed between the plurality of second insulating patterns, the second side surface opposite to the first side surface. A lateral width of the first portion is less than a lateral width of the second portion.

According to example embodiments, there is provided a semiconductor device including a substrate including a plurality of active regions and a plurality of word lines crossing the plurality of active regions and extending in a first direction, a plurality of bit lines disposed on the substrate and extending in a second direction intersecting the first direction, a plurality of storage node contacts disposed between the plurality of bit lines and between the plurality of word lines and connected to the plurality of active regions, a plurality of landing pads disposed on the plurality of storage node contacts, a plurality of first insulating patterns in contact with lower portions of first side surfaces of the plurality of landing pads, a plurality of pad oxide layers, each of which having a lateral portion disposed on an upper surface of one of the plurality of landing pads and a vertical portion in contact with an upper portion of a side surface of the one of the plurality of landing pads, a plurality of second insulating patterns in contact with upper surfaces of the plurality of first insulating patterns and covering the plurality of first insulating patterns and the plurality of pad oxide layers, and a plurality of lower electrodes vertically passing through the plurality of second insulating patterns and in contact with the upper surfaces and upper portions of second side surfaces of the plurality of landing pads, the second side surfaces opposite to the first side surfaces.

