CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of Korean Patent Application No. 10-2019-0127835 filed on Oct. 15, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

BACKGROUND

Field

The present disclosure relates to a method of producing a multi-negative differential transconductance device, and more particularly, to a method of producing a multi-negative differential transconductance (NDT) device having a plurality of peaks and valleys by serial junctions of three or more ambipolar semiconductors having different threshold voltages.

Description of the Related Art

In the negative differential transconductance device, the current decreases despite the increase in the gate voltage, so that a gate voltage-drain current characteristic curve is shown as an “N” shape.

Such a negative differential transconductance device is generally known as being observed in a heavily doped p-n-p or n-p-n junction structure, a resonant tunneling transistor (RTT), or a single electron transistor (SET).

In the heavily doped p-n-p or n-p-n structure, when a gate voltage is applied to an n-region or a p-region, an interband tunneling section is reduced so that the negative differential transconductance characteristic is implemented.

However, this structure has a problem in that the current is consistently increased after passing a section where the current decreases so that only a single peak and valley is implemented.

An RTT structure and a SET structure are structures in which a quantum well is formed between a source and a drain using nanowire and quantum dots. This structure adjusts a position of a quantized energy level in the quantum well by a gate voltage to form a peak current so that the NDT may be implemented.

However, there is a problem in that due to a device size of several nano scales, the process is complex, and it operates only at a low temperature.

In order to overcome the above-mentioned problems, a channel layer conductivity of the n-type and p-type semiconductor materials or an energy barrier of a junction surface is adjusted by bonding an n-type semiconductor material and a p-type semiconductor material to implement an NDT phenomenon. However, it is confirmed that there is a new problem in that this structure implements only a single peak and valley.

RELATED ART DOCUMENT

Patent Document

US Publication No. US 20020096690 (2002.07.25)

SUMMARY

In order to solve the above-described problems, an object of the present disclosure is to provide a method of producing a multi-negative differential transconductance device which has a plurality of peaks and valleys by 1) using semiconductors with different band structures, 2) adjusting a permittivity of a gate dielectric layer, 3) adjusting a thickness of a gate dielectric layer to generate a plurality of threshold voltages in a single semiconductor device or connecting devices with different threshold voltages.

In order to achieve the above-described object, a multi-negative differential transconductance device according to the present disclosure includes a substrate conductive portion; a gate insulating layer formed by being laminated on the substrate conductive portion; first, second, and third semiconductors which have different threshold voltages and are formed to be horizontally connected in series on the gate insulating layer; and an electrode formed at both ends of the first semiconductor and the third semiconductor.

Further, in order to achieve the above-described object, a multi-negative differential transconductance device according to the present disclosure includes a substrate conductive portion; first, second, and third insulating layers which have different dielectric constants and are formed by being horizontally connected in series on the substrate conductive portion; an ambipolar semiconductor formed by being laminated on the first, second, and third insulating layers; and an electrode formed at both ends of the ambipolar semiconductor.

Further, in order to achieve the above-described object, a multi-negative differential transconductance device according to the present disclosure includes a substrate conductive portion; an insulating layer formed on the substrate conductive portion to have different thicknesses by forming steps in three or more sections; an ambipolar semiconductor formed with different thicknesses above the insulating layer by forming steps corresponding to the insulating layer; and an electrode formed at both ends of the ambipolar semiconductor.

Further, in order to achieve the above-described object, a multi-negative differential transconductance device according to the present disclosure includes a substrate conductive portion; first, second, and third semiconductors which have different threshold voltages and are formed to be vertically laminated in this order on the substrate conductive portion; a gate insulating layer formed so as to at least partially or entirely enclose the first, second, and third semiconductors which are laminated; a gate electrode formed so as to at least partially or entirely enclose the gate insulating layer; and an anode formed on the third semiconductor.

Further, in order to achieve the above-described object, a multi-negative differential transconductance device according to the present disclosure includes a substrate conductive portion; an ambipolar semiconductor vertically (longitudinally) formed on the substrate conductive portion; first, second, and third insulating layers with different dielectric constants which are formed at all or a part of a side surface of the ambipolar semiconductor; an electrode formed so as to at least partially or entirely enclose the side surfaces of the first, second, and third insulating layers; and an anode formed on the ambipolar semiconductor.

Further, in order to achieve the above-described object, a multi-negative differential transconductance device according to the present disclosure includes a substrate conductive portion; an ambipolar semiconductor vertically (longitudinally) formed on the substrate conductive portion; an insulating layer formed in all or at least a part of a side surface of the ambipolar semiconductor; an electrode formed so as to at least partially or entirely enclose a side surface of the insulating layer with a structure corresponding to the insulator; and an anode formed on the ambipolar semiconductor.

Further, in order to achieve the above-described object, the electrode of the multi-negative differential transconductance device according to the present disclosure uses, for the p-type semiconductor, a metal having a high work function, such as platinum (Pt) or palladium (Pd) to lower a contact resistance, and for the n-type semiconductor, uses a metal having a low work function, such as titanium (Ti) or aluminum (Al).

Further, in order to achieve the above-described object, the electrode of the multi-negative differential transconductance device according to the present disclosure is formed by thermal evaporation, e-beam evaporation, sputtering, or chemical vapor deposition.

Further, in order to achieve the above-described object, the insulating layer of the multi-negative differential transconductance device according to the present disclosure is formed by any one process of thermal evaporation, e-beam evaporation, sputtering, chemical vapor deposition, physical vapor deposition, and oxidation.

Further, in order to achieve the above-described object, the first semiconductor, the second semiconductor, and the third semiconductor of the multi-negative differential transconductance device according to the present disclosure are formed with various thickness of several nm to several hundreds of μm and may be silicon, germanium, group III-V semiconductor, oxide semiconductor, organic semiconductor, transition metal dichalcogenide, phosphorene, or semiconductor materials operating as a p-type, an n-type, or an ambipolar semiconductor.

Further, in order to achieve the above-described object, the silicon, the germanium, the group III-V semiconductors, the oxide semiconductors, and organic semiconductors of the multi-negative differential transconductance device according to the present disclosure are formed using thermal evaporation, e-beam evaporation, sputtering, chemical vapor deposition, or spin coating.

Further, in order to achieve the above-described object, the transition metal dichalcogenide or phosphorene of the multi-negative differential transconductance device according to the present disclosure is exfoliated using a tape, grown using chemical vapor deposition (CVD), or obtained using an impregnation of a chalcogen element in a transition metal.

Further, in order to achieve the above-described object, the first semiconductor, the second semiconductor, and the third semiconductor of the multi-negative differential transconductance device according to the present disclosure have a common conductivity range.

Further, in order to achieve the above-described object, the insulating layer of the multi-negative differential transconductance device according to the present disclosure has a thickness which decreases from the lower portion to the upper portion to be stepped so that the thickness varies depending on the position.

Further, in order to achieve the above-described object, the thickness of the insulating layer of the multi-negative differential transconductance device according to the present disclosure is adjusted by varying a growing time for every section of the insulating layer, dry etching using plasma, or wet etching using etchant.

Further, in order to achieve the above-described object, in the multi-negative differential transconductance device according to the present disclosure, the anode electrode is formed between the first semiconductor and the second semiconductor and between the second semiconductor and the third semiconductor.

Further, in order to achieve the above-described object, in the multi-negative differential transconductance device according to the present disclosure, the anode electrode is formed between the ambipolar semiconductors enclosed by the first insulating layer and the second insulating layer and between the ambipolar semiconductors enclosed by the second insulating layer and the third insulating layer.

Further, in order to achieve the above-described object, in the multi-negative differential transconductance device according to the present disclosure, the anode electrode is formed between the ambipolar semiconductors in which the insulating layer or the electrodes has different thicknesses.

A multi-negative differential transconductance device produced by a method according to the present disclosure forms a junction of three or more semiconductor materials in one device to have a plurality of peaks and valleys to be utilized to implement a multi-valued logic circuit which is capable of representing four or more logical states (for example, when one transistor is connected to one multi-negative differential transconductance device, a quaternary inverter or a quaternary memory is implemented) without significantly increasing an area of the negative differential transconductance device which occupies the chip. Therefore, effects of low power consumption, a reduced size, and high speed of a chip may be achieved.

