TECHNICAL FIELD

The disclosure generally relates to simulation of circuitry based on a high-level language specification.

BACKGROUND

High-level synthesis is a process by which a high-level language (HLL) specification is translated into a register transfer language (RTL) specification. HLLs are languages that have been historically used to create software programs that can be compiled into program code that is executable by a computer processor. The RTL specification generated from an HLL specification can be processed into implementation data, which can then be used to configure a programmable integrated circuit (IC) or fabricate an application-specific integrated circuit (ASIC). Thus, high-level synthesis supports creating a circuit from an HLL specification, can expedite the process of creating circuit designs, and allow designers having a wider range of technical backgrounds to create circuit designs.

Simulation is an important part of the design flow for implementing a circuit from a circuit design. Simulating operation of a circuit based on a circuit design is critical to verify the function of the circuit as well as performance. However, simulation can require a significant amount of the designer's time as well as a significant amount of computer resources. A simulation model based on the RTL specification of the circuit design can include a finite state machine, which has a state for each signal in the circuit design. Transitions between states are in response to simulation events, and each active state generates an event with each simulation clock cycle. With vast gate counts in present day circuit designs, simulation can require a significant amount of computer resources and time.

SUMMARY

A disclosed method includes executing on a computer system, simulator-parallel processes that correspond to states of a finite state machine representation of a circuit design. The method initiates execution of each simulator-parallel process of the simulator-parallel processes in response to an event generated by another one of the simulator-parallel processes. A data access transaction of the circuit design is simulated in the method by calling a first function of a wrapper from a first process of the simulator-parallel processes, and waiting by the first process for an estimated number of simulation clock cycles. The estimated number of simulation clock cycles represents an actual time period required to complete an actual data access transaction.

A disclosed system includes a processor and a memory arrangement coupled to the processor. The memory arrangement is configured with instructions that when executed cause the processor to execute simulator-parallel processes that correspond to states of a finite state machine representation of a circuit design. In executing the instructions, the processor initiates execution of each simulator-parallel process in response to an event generated by another one of the simulator-parallel processes. The processor simulates a data access transaction of the circuit design in executing the instructions by calling a first function of a wrapper from a first process of the simulator-parallel processes and making the first process wait for an estimated number of simulation clock cycles. The estimated number of simulation clock cycles represents an actual time period required to complete an actual data access transaction.

Other features will be recognized from consideration of the Detailed Description and Claims, which follow.

