FIELD

This application relates to non-volatile memory apparatuses and the operation of non-volatile memory apparatuses.

BACKGROUND

This section provides background information related to the technology associated with the present disclosure and, as such, is not necessarily prior art.

Semiconductor memory apparatuses have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices.

A charge-storing material such as a floating gate or a charge-trapping material can be used in such memory apparatuses to store a charge which represents a data state. A charge-trapping material can be arranged vertically in a three-dimensional (3D) stacked memory structure, or horizontally in a two-dimensional (2D) memory structure. One example of a 3D memory structure is the Bit Cost Scalable (BiCS) architecture which comprises a stack of alternating conductive and dielectric layers.

SUMMARY

This section provides a general summary of the present disclosure and is not a comprehensive disclosure of its full scope or all of its features and advantages.

An object of the present disclosure is to provide a memory apparatus and a method of operation of the memory apparatus that address and overcome shortcomings described herein.

Accordingly, it is an aspect of the present disclosure to provide a storage device. The storage device comprises a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines, and a controller that is coupled to the non-volatile memory. The controller is configured to: determine data states for a first set of memory cells of a first neighboring word line of the set of word lines and a second set of memory cells of a second neighboring word line of the set of word lines, each of the data states being any of a plurality of data states that the first set and second set of memory cells are configured to store, the first and the second neighboring word lines being adjacent to a selected word line of the set of word lines; identify a zone of a plurality of zones for each data state combination of the data states, each data state combination comprising a data state of a memory cell of the first set of memory cells and a data state of a memory cell of the second set of memory cells, the memory cell of the first set of memory cells and the memory cell of the second set of memory cells being adjacent to a memory cell of a third set of memory cells of the selected word line, and wherein each zone of the plurality of zones corresponds to a data retention compensation scheme; and perform a read operation on the selected word line including applying each data retention compensation scheme corresponding to any zones of the plurality of zones identified for the third set of memory cells of the selected word line.

Further areas of applicability will become apparent from the description provided herein. The description and specific examples in this summary are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

