CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2020-0001796, filed on Jan. 7, 2020, in the Korean Intellectual Property Office, and entitled: “Semiconductor Device,” is incorporated by reference herein in its entirety.

BACKGROUND

1. Field

Embodiments relate to a semiconductor device.

2. Description of the Related Art

Semiconductor devices have become highly integrated and the length of channels has decreased.

SUMMARY

The embodiments may be realized by providing a semiconductor device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.

The embodiments may be realized by providing a semiconductor device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on at least parts of top surfaces of the spacers and on a top surface of the gate electrode, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure.

The embodiments may be realized by providing a semiconductor device including nanosheets; a gate electrode surrounding the nanosheets; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern, the first capping pattern including a conductive material and the second capping patterns including an insulating material; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.

The embodiments may be realized by providing a method of fabricating a semiconductor device, the method including forming a fin-type pattern on a substrate such that the fin-type pattern extends in a first direction; forming pre-spacers on the fin-type pattern, the pre-spacers defining a gate trench that extends in a second direction, which is different from the first direction; forming a pre-gate electrode that fills the gate trench; forming a gate electrode by recessing part of the pre-gate electrode; forming spacers by etching parts of the pre-spacers; forming a first capping pattern along top surfaces of the spacers and a top surface of the gate electrode such that the first capping pattern includes a conductive material; and forming a second capping pattern on the first capping pattern such that the second capping pattern includes a material different from the first capping pattern.

