CROSS-REFERENCE TO RELATED APPLICATIONS AND INCORPORATION BY REFERENCE

This application claims priority to PCT/CN2020/072624 filed on Jan. 17, 2020, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure generally relates to the field of semiconductor technology, and more particularly, to a method for forming a three-dimensional (3D) memory.

BACKGROUND

As memory devices are shrinking to smaller die size to reduce manufacturing cost and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. A three-dimensional (3D) memory architecture can address the density and performance limitation in planar memory cells.

To further increase storage capacity in a 3D memory, the number of vertically stacked memory cells has been increased greatly while the lateral dimensions of the memory cells are reduced. As a result, the aspect ratio of the 3D memory cells has increased significantly, introducing complexity in manufacturing. For example, it is challenging to form channel layers without damaging the memory films on the sidewalls of the channel holes. Thus, a need exists for an improvement in fabrication process for a 3D memory to achieve high density and good reliability.

BRIEF SUMMARY

Embodiments of a three-dimensional (3D) memory device and methods for forming the same are described in the present disclosure.

One aspect of the present disclosure provides a method for forming a three-dimensional (3D) memory device that includes forming an alternating dielectric stack on a substrate, and forming a plurality of channel holes, where the plurality of channel holes penetrate the alternating dielectric stack vertically, in a direction perpendicular to the substrate, to expose at least a portion of the substrate. The method also includes forming a first mask covering the plurality of channel holes in a first area and exposing the plurality of channel holes in a second area. The method further includes forming a recess in the alternating dielectric stack in the second area. The method also includes forming a second mask in the recess, where the second mask covers the plurality of channel holes in the second area and exposes the plurality of channel holes in the first area. The method further includes forming dips at bottom of the plurality of channel holes in the first area.

In some embodiments, forming the first mask includes disposing a hard mask layer to cover the plurality of channel holes, where the hard mask layer does not fill inside the plurality of channel holes. A first photoresist mask can then be formed on top of the hard mask layer, and patterns of the first photoresist mask can be transferred to the hard mask layer.

In some embodiments, disposing the hard mask layer includes disposing an amorphous carbon layer.

In some embodiments, forming the alternating dielectric stack includes forming a plurality of dielectric layer pairs stacked vertically in the direction perpendicular to the substrate, where each dielectric layer pair includes a first dielectric layer and a second dielectric layer that is different from the first dielectric layer.

In some embodiments, forming the recess in the alternating dielectric stack includes removing one or more pairs of the first and second dielectric layers.

In some embodiments, the method also includes disposing epitaxial layers on the exposed portion of substrate inside the plurality of channel holes. In some embodiments, the method further includes disposing a memory film on sidewalls of the plurality of channel holes and top surfaces of the epitaxial layers. In some embodiments, the method also includes disposing a first capping layer on the memory film.

In some embodiments, the method further includes disposing a channel layer on sidewalls of the memory films and on the epitaxial layers inside the plurality of channel holes after forming dips at the bottom of the plurality of channel holes in the first area. The method also includes disposing a core filling film inside the plurality of the channel holes, and removing excess core filling film, channel layer and memory films outside the plurality of channel holes.

In some embodiments, the removal of the excess core filling film, channel layer and memory films outside the plurality of channel holes comprises chemical mechanical polishing.

In some embodiments, after removing excess core filling film, channel layer and memory films outside the plurality of channel holes, top contact structures are formed in upper portions of the plurality of channel holes in the first area, where the top contact structures are connected with the channel layers inside the plurality of the channel holes.

In some embodiments, forming a second mask in the recess includes disposing a second photoresist mask over the alternating dielectric stack in the second area, where the second photoresist mask does not fill inside the plurality of channel holes. The second photoresist mask is then planarized to form a top surface coplanar with the alternating dielectric stack.

In some embodiments, forming dips at the bottom of the plurality of channel holes includes disposing a second capping layer inside the plurality of channel holes in the first area and on top of the second mask in the second area, followed by removing the second capping layer from the bottom of the plurality of channel holes in the first area to expose the substrate or an epitaxial layer on the substrate.

In some embodiments, the method further includes replacing the alternating dielectric stack with a film stack of alternating conductive and dielectric layers.

Another aspect of the present disclosure provides a dual deck three-dimensional (3D) memory device that includes an alternating dielectric stack with an upper deck and a lower deck disposed on a substrate, each deck including alternatingly stacked first and second dielectric layers in a direction perpendicular to the substrate, where the second dielectric layer is different from the first dielectric layer. The dual deck 3D memory device also includes a plurality of channel holes penetrating through the upper and lower decks of the alternating dielectric stack into the substrate. The dual deck 3D memory device further includes a memory film, a channel layer, and a core filling film covering a sidewall of each of the plurality of channel holes. The dual deck 3D memory device also includes a dip at a bottom of each of the plurality of channel holes in a first area, and a recess in the upper deck of the alternating dielectric stack in a second area.

In some embodiments, the dual deck 3D memory device also includes an epitaxial layer at the bottom of each of the plurality of channel holes, where the epitaxial layer is connected to the channel layer through the dip in the first area; and the memory film is sandwiched between the epitaxial layer and the channel layer in the second area.

In some embodiments, the dual deck 3D memory device further includes a capping layer sandwiched between the epitaxial layer and the channel layer at the bottom of each of the plurality of channel holes in the second area.

In some embodiments, the recess in the upper deck of the alternating dielectric stack in the second area includes the epitaxial layer and the core filling film.

In some embodiments, the dual deck 3D memory device further includes a top contact structure on top of the core filling film inside each of the plurality of channel holes in the first area, where the top contact structure is connected with the channel layer.

In some embodiments, the alternating dielectric stack is coplanar with the top contact structure in the first area and coplanar with the core filling film inside the recess in the second area.

Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.

