CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of Korean Patent Application No. 10-2020-0186375 filed on Dec. 29, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

BACKGROUND OF THE DISCLOSURE

Technical Field

The present disclosure relates to artificial neural networks.

Background Art

Humans are equipped with intelligence that can perform recognition, classification, inference, prediction, and control/decision making. Artificial intelligence (AI) refers to artificially mimicking human intelligence.

The human brain is made up of a multitude of nerve cells called neurons. Each neuron is connected to hundreds to thousands of other neurons through connections called synapses. The modeling of the working principle of biological neurons and the connection relationship between neurons operates to mimic human intelligence and is called an artificial neural network (ANN) model. In other words, an artificial neural network is a system in which nodes imitating neurons are connected in a layer structure.

The ANN model is divided into a monolayer neural network and a multilayer neural network according to the number of layers, and a general multilayer neural network consists of input layers, hidden layers, and output layers. Here, the input layer is a layer receiving external data, in which the number of neurons of the input layer is the same as the number of input variables; the hidden layer is located between the input layer and the output layer and receives a signal from the input layer to extract features and transmit the features to the output layer; and the output layer receives a signal from the hidden layer and outputs the received signal to the outside. The input signal between the neurons is multiplied and then summed by each connection strength with a value of zero (0) to one (1), and if the sum is greater than a threshold of the neuron, neurons are activated and implemented as an output value through an activation function.

Meanwhile, in order to implement higher artificial intelligence, an increase in the number of hidden layers of an artificial neural network is called a deep neural network (DNN).

There are several types of DNNs, but convolutional neural networks (CNNs) are known to be easy to extract features from input data and identify patterns of features.

A convolutional neural network (CNN) is a neural network that functions similar to image processing in the visual cortex of the human brain. Convolutional neural networks are known to be suitable for image processing.

Referring toFIG. 7, the convolutional neural network is configured in a form in which convolutional channels and pooling channels are alternately repeated. In a convolutional neural network, most of the computation time is occupied by the operation of convolution. A convolutional neural network recognizes objects by extracting image features of each channel by a matrix-type kernel, and providing homeostasis such as movement or distortion by pooling. For each channel, a feature map is obtained by convolution of the input data and the kernel, and an activation function such as Rectified Linear Unit (ReLU) is applied to generate an activation map of the corresponding channel. Pooling may then be applied. The neural network that actually classifies the pattern is located at the end of the feature extraction neural network, and is called a fully connected layer. In the computational processing of convolutional neural networks, most computations are performed through convolution or matrix multiplication. At this time, the frequency of reading the necessary kernels from memory is quite frequent. A significant portion of the operation of the convolutional neural network takes time to read the kernels corresponding to each channel from the memory.

A memory consists of a plurality of memory cells, and each memory cell of the memory has a unique memory address. When the artificial neural network processor generates a kernel read command stored in the memory, a latency of several clock cycles may occur until the memory cell corresponding to the address of the memory is accessed.

Therefore, there is a problem in that the time and power consumed to read the necessary kernels from the memory and perform the convolution are significant.

SUMMARY OF THE DISCLOSURE

The inventor of the present disclosure has recognized that during the inference operation of the artificial neural network model, the NPU frequently reads the weight value of the node and/or the kernel of each layer of the artificial neural network model from a separate memory.

The inventor of the present disclosure has recognized that the processing speed of the neural processing unit (NPU) reading the weight values of nodes and/or kernels of the artificial neural network model from a separate memory is slow and consumes a lot of energy.

The inventor of the present disclosure has recognized that the kernels of the artificial neural network model that have been trained have very high similarity to each other.

The inventor of the present disclosure has recognized that the inference accuracy of the artificial neural network model may not substantially decrease even if the weight values of some kernels of the artificial neural network model are partially adjusted within a certain range.

Accordingly, the inventor of the present disclosure has recognized that kernels having a very high similarity to each other can be expressed by a simple equation with the reference kernel.

In addition, the inventor of the present disclosure has recognized that the inference accuracy of the artificial neural network model can be maintained at a commercially usable level even if the model is trained or retrained so that the similarity between the kernels of the artificial neural network model is very high, that is, the deviation between the kernels is small.

Accordingly, the inventor of the present disclosure has recognized that the artificial neural network model can be trained by setting the cost function during training for increasing the target accuracy and minimizing the maximum deviation between the reference kernel and the other kernels of the artificial neural network model.

In addition, the inventor of the present disclosure has recognized that it is possible to improve the processing speed and/or reduce power consumption of a system for processing an artificial neural network model when minimizing reading of node and/or kernel weight values from separate memory, and using a simple operation within the neural processing unit (NPU) to calculate and use the weight value of a node and/or kernel that is close to the reference node and/or kernel.

Accordingly, an aspect of the present disclosure is to provide a neural processing unit capable of generating a modulation kernel with a simple algorithm, reducing the number of read operations of a memory, reducing power consumption, and an operating method thereof.

However, the present disclosure is not limited thereto, and other aspects will be clearly understood by those skilled in the art from the following description.

According to an embodiment of the present disclosure, there is provided a neural processing unit (NPU) including a circuit. The circuit may include at least one processing element (PE) configured to process an operation of an artificial neural network (ANN) model; and at least one memory configurable to store a first kernel and a first kernel filter. The NPU may be configured to generate a first modulation kernel based on the first kernel and the first kernel filter.

The first kernel may include a K×M matrix, K and M being integers, and the K×M matrix may include at least one first weight value or weight values applicable to a first layer of the ANN model.

The first kernel filter may be configured to be generated based on a difference between at least one kernel weight value of the first kernel and at least one modulation kernel weight value of the first modulation kernel.

The first kernel filter may be set during a training process of the ANN model.

The circuit may be configured to generate the first modulation kernel based on the first kernel and the first kernel filter.

The circuit may be configured to generate a second modulation kernel based on the first kernel and a second kernel filter. The second kernel filter may set to be generated by applying a mathematical function to the first kernel filter, and the mathematical function may include at least one of a delta function, a rotation function, a transpose function, a bias function, and a global weight function.

The circuit may be configured to generate a third modulation kernel based on one among the first kernel, the first kernel filter, the mathematical function applied to the first kernel or the first kernel filter, a coefficient applied to the first kernel or the first kernel filter, and an offset applied to the first kernel or the first kernel filter.

The at least one memory may be further configurable to store mapping information between at least one kernel and at least one kernel filter for generating at least one modulation kernel.

The ANN model may include information on bit allocation of first weight bits that are included in the first kernel filter for a first mode.

The NPU may operate in one of a plurality of modes, the plurality of modes including a first mode in which a first portion of a plurality of weight bits included in the first kernel to the ANN model are applied; and a second mode in which all of the plurality of weight bits included in the first kernel to the ANN model are applied. The weight bits in the first portion may be selected if the first portion is activated according to the first mode.

The first kernel may include a plurality of weight bits grouped into a first portion and a second portion, and the first portion and the second portion may be configured to be used selectively.

The first kernel filter may be configured such that a bit width for a value in the first kernel filter is smaller than a bit width of a weight of the first kernel.

According to another embodiment of the present disclosure, there is provided a method for driving an artificial neural network (ANN) model. The method may include performing a plurality of operations for the ANN model; and storing a plurality of kernels with a plurality of kernel filters for the plurality of operations. The plurality of operations may include generating a plurality of modulation kernels based on at least one of the plurality of kernels and a corresponding kernel filter of at least one of the plurality of kernel filters.

The plurality of operations performed for the ANN model may further include setting an arbitrary kernel among the plurality of kernels of the ANN model, the arbitrary kernel corresponding to a base kernel among the plurality of kernels; and setting an arbitrary kernel filter among the plurality of kernel filters for the arbitrary kernel corresponding to the base kernel.

The plurality of operations performed for the ANN model may further include training the ANN model based on a training data set and a validation data set with respect to an accuracy cost function and a weight size cost function; and determining mapping data between a base kernel among the plurality of kernels and an arbitrary kernel filter among the plurality of kernel filters.

The plurality of operations performed for the ANN model may be performed by a neural processing unit (NPU) comprising a circuit, the circuit including at least one processing element (PE) and at least one memory. The plurality of operations performed for the ANN model may further include reading a first kernel of the plurality of kernels from the at least one memory; performing a first operation by applying the first kernel of the plurality of kernels to a first layer of the ANN model or to a first channel of the ANN model; reading the kernel filter from the at least one memory; generating a first modulation kernel based on the first kernel of the plurality of kernels and a first kernel filter of the plurality of kernel filters; and performing a second operation for the ANN model by applying the first modulation kernel to a second layer of the ANN model or to a second channel of the ANN model.

According to another embodiment of the present disclosure, there is provided an apparatus. The apparatus may include a semiconductor substrate on which an electrically conductive pattern is formed; at least one first memory electrically connected to the semiconductor substrate and configurable to store information about a first kernel; and at least one neural processing unit (NPU) electrically connected to the substrate and configurable to access the at least one first memory, the NPU including a semiconductor circuit comprising at least one processing element (PE) configured to process an operation of an artificial neural network (ANN) model, and at least one internal memory configurable to store information about a first kernel filter. If the information about the first kernel is read from the at least one first memory, the first kernel may be stored in the at least one internal memory, and the operation of the ANN model may include generating a first modulation kernel based on the first kernel and the first kernel filter.

According to the present disclosure, by generating at least one base kernel and processing the convolution operation of the convolutional neural network, the power consumption required to read the corresponding kernel for each convolution operation can be reduced and the memory read time can be shortened.

According to the present disclosure, by utilizing the base kernel and the kernel filter, the number of kernels and/or the data size stored in the memory may be reduced.

In addition, there is an effect of reducing power consumption and reducing memory read time due to a decrease in the data size of the kernel read from memory to the artificial neural network processor and/or a decrease in the number of memory read requests.

In addition, according to the present disclosure, the amount of data transfer and/or the number of memory read requests of the memory and neural processing unit can be reduced. Since the occurrence of data starvation and/or the idle (IDLE) time of the artificial neural network processor is reduced, the operation efficiency of the artificial neural network processor can be improved.

