BACKGROUND

The demand for handling complex computational tasks (such as video transcoding and artificial intelligence operations, among others) is expanding at an ever-increasing rate. Complex computational tasks are often assigned to powerful data center servers (e.g., domain controllers) since other devices (e.g., edge servers) may lack the computing resources necessary to effectively complete these demanding tasks. However, deploying and maintaining domain controllers may be expensive, and adding domain controllers to scale a data center for high-demand computing tasks may be inefficient and/or impractical, especially in high-growth points-of-presence (POPS) traditionally serviced by edge servers. Moreover, due to their general-purpose design, domain controllers may struggle with and/or inefficiently handle some highly specific and demanding tasks. Thus, traditional data center resources and scaling techniques may be unable to efficiently and effectively keep pace with the ever-increasing demand for computationally intensive tasks.

SUMMARY

As will be described in greater detail below, the instant disclosure presents various apparatuses, systems, and methods for effectively and efficiently handling complex computational tasks by hardware accelerating the same using compact expansion cards. In one example, such an expansion card may include a printed circuit board and a hardware accelerator. The hardware accelerator may be disposed on the printed circuit board and may include application-specific hardware circuitry designed to perform a computing task. The hardware accelerator may offload at least a portion of the computing task from a central processing unit of a computing device by executing, via the application-specific hardware circuitry, at least a portion of the computing task. The expansion card may also include an edge connector, disposed on the printed circuit board, that is dimensioned to be inserted into an expansion socket of the computing device. The edge connector may couple the hardware accelerator to the central processing unit via a computing bus connected to the expansion socket. The edge connector may also include a pinout that is more compact than a pinout specification defined for the computing bus.

In some examples, the pinout of the edge connector may conform to an M.2 pinout specification, a U.2 pinout specification, and/or an mSATA pinout specification. In additional or alternative examples, the hardware accelerator may include a field-programmable gate array and/or an application-specific integrated circuit.

In some embodiments, the expansion card may further include a voltage regulator that stabilizes voltage received via the expansion socket and supplies the stabilized voltage to the hardware accelerator. In one example, the computing task that the application-specific hardware circuitry is designed to perform may include an artificial intelligence inference task that applies a model trained on known data to infer at least one label for new data. In additional or alternative examples, the computing task that the application-specific hardware circuitry is designed to perform may include a video transcoding task.

Similarly, a system incorporating the above-described apparatus may include a central processing unit, a memory device, an expansion socket, and an expansion card. The expansion card may include a printed circuit board and a hardware accelerator that is disposed on the printed circuit board. In one example, the hardware accelerator may include application-specific hardware circuitry designed to perform a computing task. In this example, the hardware accelerator may offload at least a portion of the computing task from the central processing unit by executing, via the application-specific hardware circuitry, at least a portion of the computing task. The expansion card may also include an edge connector, disposed on the printed circuit board, that is dimensioned to be inserted into the expansion socket. The edge connector may couple the hardware accelerator to the central processing unit via a computing bus connected to the expansion socket. The edge connector may also include a pinout that is more compact than a pinout specification defined for the computing bus.

In some examples, the expansion socket may be disposed on an intermediary expansion card that includes a pinout that conforms to the pinout specification defined for the computing bus. In further examples, the system may include a chassis that is dimensioned to accept a plurality of modular computing devices. In these examples, the expansion socket may be disposed on a modular computing device inserted into the chassis. Additionally or alternatively, the system may include a chassis that is dimensioned to accept a plurality of modular storage devices. In these examples, the expansion socket may be disposed on a modular storage device inserted into the chassis.

In some embodiments, the system may represent a domain controller server and/or or an edge server. In embodiments where the system represents an edge server, offloading at least a portion of the computing task from the central processing unit of the edge server may enable the edge server to perform the computing task.

In some examples, the system may represent a backend data center of a corporate networking enterprise that provides at least one online service to corresponding users of client devices. The online service may, for example, represent a social networking service, a virtual reality service, and/or a cloud storage service.

A corresponding method may include inserting an expansion card into an expansion socket of a computing device. The expansion card may include a printed circuit board and a hardware accelerator that is disposed on the printed circuit board. The hardware accelerator may include application-specific hardware circuitry designed to perform a computing task. The expansion card may also include an edge connector, disposed on the printed circuit board, that is dimensioned to be inserted into the expansion socket of the computing device. The edge connector may couple the hardware accelerator to a central processing unit of the computing device via a computing bus connected to the expansion socket. The edge connector may also include a pinout that is more compact than a pinout specification defined for the computing bus. In addition, the method may include offloading at least a portion of the computing task from the central processing unit by executing, via the application-specific hardware circuitry, at least a portion of the computing task.

In some examples, the method may further include scaling the hardware acceleration capabilities of the computing device by inserting an additional expansion card into an additional expansion socket of the computing device. The additional expansion card may include at least one additional hardware accelerator that includes additional application-specific hardware circuitry designed to perform the computing task. The additional expansion card may also include an additional edge connector that includes an additional pinout that is more compact than the pinout specification defined for the computing bus. In additional examples, inserting the expansion card into the expansion socket may include inserting the expansion card into a socket of an intermediary expansion card that is inserted into the expansion socket of the computing device. In these examples, the intermediary expansion card may include a pinout that conforms to the pinout specification defined for the computing bus.

Features from any of the above-mentioned embodiments may be used in combination with one another in accordance with the general principles described herein. These and other embodiments, features, and advantages will be more fully understood upon reading the following detailed description in conjunction with the accompanying drawings and claims.

