BACKGROUND

Field of Invention

The present invention relates generally to amplifier circuits, and more particularly to circuits and techniques for reducing the Dynamic Error Vector Magnitude in a cascode power amplifier circuit.

Discussion of Related Art

The Error Vector Magnitude (EVM) performance of a power amplifier (PA) is an important parameter if the power amplifier is intended for a linear mode of operation in applications such as WiFi. In order to achieve good EVM, constellation points in a modulated waveform must be amplified as accurately as possible by the power amplifier so that there is no amplitude or phase distortion in the waveform at the output of the amplifier. Since the amplitude of a signal in a complex modulation scheme varies greatly with time, the phase shift and the gain of the amplifier must be very stable over a wide range of power levels to keep the EVM as low as possible.

There are two ways to measure the EVM of an amplifier. The first is called static EVM. In this case the amplifier is turned on before the measurement is performed and therefore the amplifier has time to find a stable operating point. The second type of measurement is called Dynamic EVM (DEVM). In this case the amplifier is enabled or switched on just as the measurement is about to commence. In this case, even if the amplifier had a completely linear phase and amplitude characteristic versus power level, the amplifier can still experience a change in amplitude and phase during the measurement due to a shift in its operating point. This is usually due to the amplifier heating up from room temperature to a new thermal equilibrium point due to its own power dissipation. Thus, DEVM is generally worse than static EVM in most amplifiers.

In modern RF devices, changes in the operating point of a power amplifier occur frequently. For example, many electronic RF devices, such as smart phones and tablets are powered by a battery. Because the transmit power of a power amplifier consumes a significant portion of the total system DC power, a number of techniques are employed to reduce power amplifier power usage. For example, many power amplifiers offer an adjustable DC supply voltage to optimize the maximum RF output power level versus its DC power consumption. Further, most power amplifiers can be powered-down or disabled when not in use to conserve power, such as while receiving or between packets during transmission, and then powered back on or re-enabled as needed. Still other power amplifiers may use envelope tracking, where the power supplied to the power amplifier tracks the envelope of the output signal. As a result, changes in the operating point of a power amplifier occur frequently during normal operation, and accordingly the DEVM performance of a power amplifier is a very important parameter for many applications.

There are existing solutions for improving the DEVM of a power amplifier. Most of these typically involve controlling the current through the amplifier with the use of off-chip filters and biasing ICs which control the current through the amplifier. In such solutions, just as the amplifier turns on and is relatively cool and has relatively high gain, the amplifier is supplied with less current, but as the amplifier heats up more current is supplied in an effort to keep the gain constant. However, such existing solutions typically involve complex off-chip circuitry to fix this problem.

SUMMARY OF INVENTION

Aspects and embodiments of the present disclosure are directed to circuits and techniques for reducing the DEVM in a cascode power amplifier circuit.

In accordance with an aspect of the present disclosure, a power amplifier is provided comprising a cascode output stage, a bias circuit, and a temperature compensation and bias boost circuit. The cascode output stage has an input to receive a radio frequency input signal and an output to provide an amplified radio frequency output signal. The cascode output stage includes a first transistor and a second transistor connected in series between a first supply voltage and a reference potential, the first and second transistors each having a base, a collector, and an emitter, the base of the first transistor being coupled to the input to receive the radio frequency input signal, the emitter of the first transistor being coupled to the reference potential, the collector of the first transistor being coupled to the emitter of the second transistor, and the collector of the second transistor being coupled to the first supply voltage and the output to provide the amplified radio frequency output signal. The bias circuit is coupled to the base of the second transistor to bias the second transistor, and the temperature compensation and bias boost circuit is coupled to the base of the first transistor. The temperature compensation and bias boost circuit is configured to compensate for changes in temperature of the cascode output stage and to increase a bias current provided to the first transistor in response to an increase in the temperature of the cascode output stage.

In accordance with an aspect of the present disclosure, the temperature compensation and bias boost circuit includes a third transistor, first and second resistors, a first capacitor, and first, second, and third diodes. The third transistor has a base, a collector, and an emitter, the collector being coupled to a second supply voltage different than the first supply voltage, the emitter being coupled to the base of the first transistor through the first resistor, and the base being coupled to the reference potential through the first capacitor. The second resistor is coupled in series with the first diode between the second supply voltage and the base of the third transistor, and the second and third diodes are coupled in series between the base of the third transistor and the reference potential.

In accordance with an aspect of the present disclosure, changes with temperature of a voltage dropped across the second and third diodes substantially matches changes with temperature of a base to emitter voltage dropped across the first and third transistors.

In accordance with an embodiment, the cascode output stage and the temperature compensation and bias boost circuit are integrated on a GaAs semiconductor die, and the first, second, and third diodes are physically disposed on the GaAs semiconductor die adjacent the first transistor to be closely thermally coupled thereto. In accordance with a further aspect of this embodiment, the second transistor is physically spaced apart on the GaAs semiconductor die from the first transistor to be thermally isolated from the first transistor.

In accordance with an aspect of the present disclosure, the bias circuit includes third and fourth resistors coupled in series between the first supply voltage and the reference potential, and a fourth transistor having a base, a collector, and an emitter, the base being connected a node connecting the third and fourth resistors, the collector being coupled to the supply voltage, and the emitter being coupled to a second capacitor that is coupled to the reference potential and the base of the second transistor.

In accordance with a further aspect of the present disclosure, the power amplifier further comprises an enable circuit coupled to the temperature compensation and bias boost circuit to receive an enable signal and enable the temperature compensation and bias boost circuit and the cascode output stage responsive to the enable signal.

In accordance with various embodiments, the power amplifier may further comprise an input impedance matching circuit coupled between the input and the base of the first transistor, the input impedance matching circuit including an inductor coupled between the input and the reference potential and a third capacitor coupled between the input and the base of the first transistor.

In accordance with various embodiments, the enable circuit includes fifth and sixth transistors and fifth and sixth resistors. The fifth transistor and the sixth transistor each have a base, a collector, and an emitter, the base of the fifth transistor being coupled to the collector of the sixth transistor, the emitter of the fifth transistor and the emitter of the sixth transistor being coupled together and to the reference potential, and the collector of the fifth transistor being coupled to a cathode of the first diode, an anode of the second diode, and the base of the third transistor. The fifth resistor is coupled between the second supply voltage and the collector of the sixth transistor, and the sixth resistor is coupled between the base of the sixth transistor and an enable contact to receive the enable signal.

In accordance with various embodiments, the power amplifier can further comprise at least one additional gain stage coupled to the input of the cascode output stage.

Still other aspects, embodiments, and advantages of these exemplary aspects and embodiments are discussed in detail below. Embodiments disclosed herein may be combined with other embodiments in any manner consistent with at least one of the principles disclosed herein, and references to “an embodiment,” “some embodiments,” “an alternate embodiment,” “various embodiments,” “one embodiment” or the like are not necessarily mutually exclusive and are intended to indicate that a particular feature, structure, or characteristic described may be included in at least one embodiment. The appearances of such terms herein are not necessarily all referring to the same embodiment.

