BACKGROUND

To date, transistors used in power electronic applications have typically been fabricated with silicon (Si) semiconductor materials. Common transistor devices for power applications include Si CoolMOS®, Si Power MOSFETs, and Si Insulated Gate Bipolar Transistors (IGBTs).

A transistor device for power applications may be based on the charge compensation principle and may include an active cell field including a plurality of trenches, each including a field plate for charge compensation. In some designs, the trenches and mesas that are formed between adjacent trenches may each have an elongate striped structure. In some other designs, the trenches have a columnar needle-like shape, as for example disclosed in DE 10 2014 112371 A1.

Typically, the active cell field of the transistor device is laterally surrounded by an edge termination structure which serves to avoid breakdown of the semiconductor device due to edge effects. DE 10 2017 114 681 A1 discloses an arrangement of an edge termination region in which surface charging in the edge region is reduced by using a local doped region at the surface in order to improve the blocking capability of the edge termination structure.

However, further improvements would be desirable to allow higher doping in the mesas in the active cell area which in turn leads to a reduction of the RDSON of the transistor device and to reduce the risk that avalanche generation moves to the surface at the outer edge of the termination structure.

SUMMARY

In some embodiments, a semiconductor device is provided that comprises a semiconductor body having a first surface, a second surface opposing the first surface and side faces, an active area and an edge termination region laterally surrounding the active area. The active area comprises a plurality of active transistor cells. Each active transistor cell comprises a columnar trench comprising a field plate and a mesa comprising a drift region of a first conductivity type. The edge termination region comprises a plurality of inactive cells, each inactive cell comprising a columnar termination trench comprising a field plate and a termination mesa comprising a drift region of a first conductivity type. The edge termination region comprises a transition region laterally surrounding the active region and an outer termination region laterally surrounding the transition region. In the transition region, the termination mesa comprises a body region of the second conductivity type that is arranged on the drift region. In the outer termination region, the drift region of the termination mesa extends to the first surface. The edge termination region further comprises a buried doped region that has a lateral extent such that it is positioned in the transition region and in the outer termination region.

The semiconductor device may provide a transistor device, such as a vertical transistor device, for example a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device.

In some embodiments, the buried doped region comprises an inner edge that is positioned under the body region in the transition region.

In some embodiments, the edge termination region further comprises an outer region that is free of inactive cells and that laterally surrounds the outer termination region.

In some embodiments, the buried doped region has an outer edge that is positioned in the outer region.

In some embodiments, the outer edge of the buried doped region is positioned laterally between the side face of the semiconductor body and the plurality of inactive cells.

In some embodiments, the buried doped region has the second conductivity type.

In some embodiments, the buried doped region is fully depletable.

In some embodiments, in the transition region, the buried doped region is vertically spaced apart from the body region of the termination mesa by a portion of the drift region.

In some embodiments, the columnar trenches have a base positioned at a depth d from the first surface and the buried doped region is positioned at a depth dburiedfrom the first surface, wherein 0.6 μm≤dburied≤2 μm.

In some embodiments, in the transition region the body region of the termination mesas extends to the first In these embodiments, the termination mesas in the transition region do not include a source region.

In some embodiments, the buried doped region forms a portion of side walls of at least two rows of columnar termination trenches.

In some embodiments, each mesa of the active transistor cells comprises a drift region of a first conductivity type, a body region of a second conductivity type opposing the first conductivity type arranged on the drift region, a source region of the first conductivity type arranged on the body region and a gate trench comprising a gate electrode, wherein the gate trench extends through the source region and the body region into the drift region. Each of the columnar trenches extends from the first surface through the body region and into the drift region.

The gate electrode is insulted from the mesa by an insulating layer that lines the sidewalls and base of the gate trench. The field plate in the columnar trenches is also electrically insulated from the drift region of the mesas of the active transistor cells by an insulating layer that lines the sidewalk and base of the columnar trench. The field plate also has a columnar structure. The columnar trenches have a greater height that the gate trenches and, therefore, extend to a greater depth from the first surface into the semiconductor body.

The gate trenches of each active transistor cell may be connected to one another active transistor cells to form a grid like pattern that is positioned between the columnar trenches. A gate trench may be arranged between neighbouring trenches such that the grid surrounds each of the columnar trenches. In some embodiments, the grid-like pattern is interrupted or partially interrupted.

In some embodiments, the gate trenches have a strip or stripe form.

In some embodiments, the semiconductor device further comprises at least one gate finger extending on the first surface of the semiconductor body. The at least one gate finger may extend from the active area over the edge termination region to a gate runner that is positioned laterally between the side face of the semiconductor body and the columnar termination trenches of the outer termination region.

In some embodiments, the gate runner is positioned laterally between and laterally spaced apart from the side face of the semiconductor body and the outer edge of the buried doped region.

In some embodiments, the semiconductor device further comprises a to contact extending from the gate finger to gate electrodes of the active transistor cells, wherein the gate contact and a portion of the gate runner is positioned above the body region of the termination mesas arranged in the transition region.

Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

