CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority to Chinese Patent Application No. 202011621871.7 filed Dec. 31, 2020, the disclosure of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to the field of display panel and, in particular, to a display panel and a display device.

BACKGROUND

In the field of display, the shift register is often used in order to implement scanning display or other functions. However, when the shift register operates, the voltage of the control node inside the shift register inevitably has a threshold loss. Therefore, the transistor in the corresponding shift register cannot sufficiently be on so that the level of the output terminal of the shift register cannot reach the target voltage, causing the tailing phenomenon to occur and affecting the display effect.

When the output signal of the p-type metal oxide semiconductor (PMOS) transistor in the shift register is transitioned from a high level to a low level, the potential of the gate of the PMOS transistor is potential Vgl, and the potential of the source of the PMOS transistor is also potential Vgl, that is, the potential of both the gate and the source of the PMOS transistor are potential Vgl, and the PMOS transistor operates in an unsaturated state, causing the voltage of the drain output to be |Vgl|−|Vth|, where Vth is the threshold voltage of the PMOS transistor.

Since the voltage of the drain output of the PMOS transistor does not reach the effect of the predetermined output Vgl, there is the tailing phenomenon when the output pulse signal of the existing shift register transitions from a high level to a low level.

SUMMARY

The present disclosure provides a display panel and a display device.

In a first aspect, the embodiments of the present disclosure provide a display panel. The display panel includes a driver circuit.

The driver circuit includes an N-stage cascaded shift register, where N is greater than or equal to 2.

The shift register includes a first control unit, a second control unit, a third control unit, and a fourth control unit.

The first control unit is configured to receive an input signal and control a signal of a first node in response to a first clock signal.

The second control unit is configured to receive a first voltage signal and a second voltage signal and control a signal of a second node in response to the signal of the first node, the first clock signal, and a second clock signal.

The third control unit is configured to receive the first voltage signal and generate an output signal in response to a signal of a third node, or receive the second voltage signal and generate an output signal in response to the signal of the second node, where the third node is connected to the first node, the first voltage signal is a low level signal, and the second voltage signal is a high level signal.

The fourth control unit is connected to the third node and configured to control a potential of the third node to be a first low level signal for at least a first time period within time when the first node is a low level signal, where the potential of the first low level signal is lower than the potential of the first voltage signal.

In a second aspect, the embodiments of the present disclosure further provide a display device including the display panel described in the first aspect.

The display panel provided by the embodiments of the present disclosure includes a driver circuit, where the driver circuit includes an N-stage cascaded shift register which includes a first control unit, a second control unit, a third control unit, and a fourth control unit, where the third control unit is configured to receive the first voltage signal and generate the output signal in response to the signal of a third node, or receive the second voltage signal and generate the output signal in response to the signal of the second node. Since the fourth control unit is connected to the third node and can control the potential of the third node to be the potential of the first low level signal for at least the first time period within time when the first node is the low level signal, and the potential of the first low level signal is lower than the potential of the first voltage signal, that is, the potential of the third node is lower than the potential of the first voltage signal so that the transistor in the third control unit rapidly approaches the saturation state and outputs the first voltage signal, thereby avoiding the tailing problem.

