BACKGROUND

Field

The described embodiments relate to computing devices. More specifically, the described embodiments relate to using multiple memory elements in an input-output memory management unit (IOMMU) in a computing device for performing virtual address to physical address translations.

RELATED ART

Many computing devices include peripherals such as graphics processing units (GPUs), digital signal processors (DSPs), etc. In some computing devices, some or all of the peripherals are provided with access to a memory in the computing device (e.g., a main memory in the computing device). In some of these computing devices, the peripherals use a “virtual memory” technique for accessing memory. For the virtual memory technique, peripherals (or workloads executed by the peripherals) address memory using “virtual addresses” in “virtual address spaces,” which are address spaces that are specific to corresponding peripherals, instead of addressing memory using the “physical addresses” of the physical locations where data is located in the shared memory. The virtual addresses used by peripherals may not map directly to the physical addresses—and therefore may not indicate the locations in the shared memory where corresponding data is actually stored. The computing devices therefore include mechanisms such as input-output memory management units (IOMMUs) that are configured to provide virtual address to physical address translations for the peripherals. An IOMMU, upon receiving a request from a peripheral that includes virtual addresses, translates the virtual address into a corresponding physical address. The IOMMU then provides the physical address to the requesting peripheral, which can then perform memory access(es) using the physical address.

In order to enable the above-described virtual address to physical address translation, the computing devices include “page tables.” A page table is a record stored in a memory of a computing device that includes an entry, or a “page table entry,” with virtual address to physical address translation information for pages (e.g., 4 KB blocks of data) that are stored in the memory. Upon receiving a request from a peripheral to translate a given virtual address, an IOMMU acquires corresponding physical address information from the page table by performing a “page table walk,” during which the page table is searched, possibly entry-by-entry, for a page table entry that provides the physical address associated with the virtual address.

Because page table walks are relatively slow, it is desirable to avoid performing page table walks. IOMMUs therefore include translation lookaside buffers (“TLBs”), which are local caches that are used for storing a limited number of copies of page table entries acquired during page table walks. An IOMMU will first attempt to acquire cached page table entry information from a corresponding TLB for performing a virtual address to physical address translation. When the page table entry information is not present in the corresponding TLB (i.e., when a “TLB miss” occurs), the IOMMU performs the above-described page table walk—and may then cache a copy of information from the acquired page table entry in the TLB.

Because different arrangements of peripherals can be found in different computing devices, using a one-size-fits-all approach to TLB design can result in less than optimal performance for the IOMMU. For example, a TLB in an IOMMU may be implemented using a type of memory (e.g., synchronous dynamic random access memory (SRAM)) that is not optimally-suited for at least some of the numerous possible arrangements of peripherals.

