BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while feature size (i.e., the smallest component that can be created using a fabrication process) has decreased. Such accomplishment of decreasing feature size is attributable in part to improved lithography processes, such as, an extreme ultraviolet (EUV) lithography.

However, while the EUV lithography may result in smaller feature size (e.g., feature size smaller than 20 nanometers), some issues, such as increasing sizes of line edge roughness (LER) and/or line width roughness (LWR), may occur. Generally, the size of LWR may not be scaled with the decreasing feature size. That is, the smaller the feature size is, the larger percentage of the LWR is. Such increasing size of LWR and increasing percentage of LWR may disadvantageously impact performance and reliability of a later formed device. Thus, a process and material that reduce, minimize or remove issues with a patterning material are desired.

