CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority under 35 U.S.C. § 119 of European Patent application no. 19205479.9, filed on 25 Oct. 2019, the contents of which are incorporated by reference herein.

FIELD

The present disclosure relates to a low drop-out (LDO) regulator and a method of operating a LDO regulator.

BACKGROUND

LDO regulators may be used to provide an output voltage for other circuitry, LDO regulators may be controlled by digital logic controllers. Digital logic controllers may provide signalling to the LDO regulator to control an operating mode of the LDO, which may affect the output voltage. The digital logic controller also requires a source of power to operate.

SUMMARY

According to a first aspect of the present disclosure there is provided a system comprising:a low drop-out, LDO, regulator configured to receive a supply voltage at an input terminal and provide an output voltage at an output terminal based on a function of the supply voltage, the LDO regulator configured to be switchable between at least a first mode and a second mode, wherein the first and second modes each define the output voltage provided to the output terminal based on different functions of the supply voltage; anda digital logic controller configured to select the mode of the LDO regulator by providing control signalling to the LDO regulator, the digital logic controller configured to receive power for the provision of the control signalling from the output voltage provided by the LDO regulator;wherein the LDO regulator comprises LDO start-up circuitry configured to cause the LDO regulator, during start-up, to default to a predetermined one of the first and second mode and the LDO start-up circuitry further configured to prevent the digital logic controller from controlling the mode of the LDO regulator.

In one or more embodiments, the LDO start-up circuitry is configured to monitor the voltage at the output terminal of the LDO regulator and, based on the monitored voltage being below a threshold, cause the LDO regulator to default to the predetermined one of the first and second mode and prevent the digital logic controller from controlling the mode of the LDO regulator.

In one or more embodiments, the LDO regulator is provided on an integrated circuit and the digital logic controller is provided on the same integrated circuit.

In one or more embodiments, the LDO regulator includes LDO digital logic to receive the control signalling from the digital logic controller and place the LDO regulator in one of the first and second mode; andthe system comprises a level shifter configured to provide for shifting of voltage levels of the control signalling output by the digital logic controller prior to receipt of said control signalling by the LDO digital logic, and wherein the LDO start-up circuitry is configured to control the output of the level shifter such that the LDO start-up circuitry and the level shifter provide:a first state wherein the control signalling is prevented from being provided to the LDO digital logic and, instead, predetermined signalling is provided to the LDO digital logic to cause the LDO regulator to operate in the predetermined mode; anda second state wherein the control signalling from the digital logic controller is provided to the LDO digital logic.

In one or more embodiments, the LDO start-up circuitry is configured to monitor the output voltage provided to the digital logic controller by the LDO regulator wherein the LDO start-up circuitry is further configured to provide signalling to the level shifter to provide the first state and the second state based on the output voltage.

In one or more embodiments, the LDO start-up circuitry is configured to provide signalling to the level shifter to provide:the first state when the output voltage is above a first threshold voltage and below a second threshold voltage, the second threshold voltage greater than the first threshold voltage; andthe second state when the output voltage is above the second threshold.

In one or more embodiments, the first threshold voltage may be 0, or less than 0.2, 0.3, 0.4, 0.5, 0.6 Volts or any other voltage value suitable for the system in question. In one or more embodiments, the second threshold voltage may be at least 1V, 1.5V, or 2V.

In one or more embodiments, the first mode is configured to provide an output voltage that is greater than or equal to a minimum acceptable operating voltage of the digital logic controller to the digital logic controller and the second mode is configured to provide an output voltage which is below the minimum acceptable operating voltage of the digital logic controller to the digital logic controller, wherein the predetermined one of the first and second mode is the first mode.

In one or more embodiments, the minimum acceptable operating voltage is a voltage below which the digital logic controller will not operate or will not operate optimally. The minimum operating voltages of electronic components are typically well defined values which are often contained in specification sheets for the components. The minimum acceptable operating voltage in the first mode may be provided to the digital logic controller after the start-up period, during which the voltage may increase until it reaches at least the minimum acceptable operating voltage.

In one or more embodiments, the first mode comprises one of:a regulating mode wherein the output voltage provided at the output terminal is a substantially constant, non-zero output voltage; anda zero-current bypass mode wherein the output voltage provided at the output terminal is dependent on the input voltage received at the input terminal; and

the second mode comprises one of:a zero-voltage mode wherein the output voltage is equal to, or substantially equal to zero relative to a reference voltage; anda test mode.

In one or more embodiments, the reference voltage may be a ground.

In one or more embodiments, the mode to which the LDO regulator is configured to default during start-up is selectable. In one or more embodiments, said predetermined mode of the first and second modes is set at the time of manufacture.

In one or more embodiments, the LDO regulator comprises a test terminal for receiving a test signal indicative that the system is to be tested, wherein the LDO regulator is configured to, based on receipt of the test signal, override the control signalling from the digital logic controller and enter a test mode.

In one or more embodiments, a test signal may be sent to the test terminal post-manufacture for early testing of the device, thereby reducing wait times for post-manufacture testing.

In one or more examples the LDO regulator comprises an analog LDO regulator.

In one or more embodiments, the output voltage is configured to be provided to load circuitry in addition to the digital logic controller for the provision of power to the load circuitry.

According to a second aspect of the present disclosure there is provided a method of operating a system, the system comprisinga low drop-out LDO, regulator configured to receive a supply voltage at an input terminal and provide an output voltage at an output terminal based on a function of the supply voltage, the LDO regulator configured to be switchable between at least a first mode and a second mode, wherein the first and second modes each define the output voltage provided to the output terminal based on different functions of the supply voltage; anda digital logic controller configured to select the mode of the LDO regulator by providing control signalling to the LDO regulator, the digital logic controller configured to receive power for the provision of the control signalling from the output voltage provided by the LDO regulator;

the method comprising:during start-up, by LDO start-up circuitry, causing the LDO regulator to default to a predetermined one of the first and second mode; andduring start-up, LDO start-up circuitry, preventing the digital logic controller from controlling the mode of the LDO regulator.

In one or more embodiments, the method comprises switching, LDO start-up circuitry, from a first state to a second state;the first state comprising preventing the digital logic controller from providing the control signalling to the LDO regulator and, instead, providing predetermined signalling to the LDO regulator to cause the LDO regulator to operate in the predetermined mode; andthe second state comprising allowing the digital logic controller to provide the control signalling to the LDO regulator.wherein the method further comprises monitoring the output voltage provided to the digital logic controller by the LDO regulator and controlling said switching based on the output voltage.

In one or more embodiments, the method comprises causing the system to operate in:the first state when the output voltage is above a first threshold voltage; andthe second state when the output voltage is above a second threshold.

In one or more embodiments, the method comprises the system includes a level shifter configured to provide for shifting of voltage levels of the control signalling output by the digital logic controller prior to receipt of said control signalling by the LDO digital logic, and wherein said first state and said second state are provided by the LDO start-up circuitry controlling the output of the level shifter.

In one or more examples, the method comprises;based on receipt of the test signal at the LDO regulator, preventing the digital logic controller from controlling the mode of the LDO regulator; andcausing the LDO regulator to operate in a test mode.

According to a third aspect of the present disclosure there is provided a telecommunications system comprising the system of the first aspect.

While the disclosure is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that other embodiments, beyond the particular embodiments described, are possible as well. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of the appended claims are covered as well.

The above discussion is not intended to represent every example embodiment or every implementation within the scope of the current or future Claim sets. The figures and Detailed Description that follow also exemplify various example embodiments. Various example embodiments may be more completely understood in consideration of the following Detailed Description in connection with the accompanying Drawings.

