REFERENCE TO PRIORITY APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0070658, filed Jun. 11, 2020, the disclosure of which is hereby incorporated herein by reference.

BACKGROUND

Embodiments of the inventive concept described herein relate to memory modules and methods of operating same, and, more particularly, to memory modules capable of performing an offloaded operation through a standard memory interface and methods of operating same.

A memory device may store data input from an external host. Also, the memory device may output data stored therein in response to a request from the external host. A substrate on which one or more memory devices and one or more parts associated with the memory devices are mounted may be referred to as a “memory module”. A memory module including a processor capable of processing data may perform an operation on data stored in the memory module, based on a command received from the host. In other words, the memory module may have a near data processing (NDP) structure.

SUMMARY

Embodiments of the inventive concept provide a memory module, which includes a processor that supports an offloaded operation(s) using a standard DDR memory interface, and which is capable of accessing data in the memory module without intervention of a host, and methods of operating same.

According to an exemplary embodiment, a memory module may include a first memory device, a second memory device, and a processing buffer circuit. This processing buffer circuit is connected to the first memory device and the second memory device (independently of each other) and is connected to a host. The processing buffer circuit may include a processing circuit that processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host, and a buffer that stores data processed by the processing circuit. The processing buffer circuit may communicate with the host in compliance with a DDR SDRAM standard.

According to an exemplary embodiment, an operating method may be provided for a memory module, which includes a normal memory channel and a processing memory channel, and with each of the normal memory channel and the processing memory channel sharing a router of a processing buffer circuit (and including a memory cell array). This method may include setting an operating mode of the router to one of an extension mode or a mirror mode, based on a mode register set command received from a host. In addition, data stored in the normal memory channel and the processing memory channel is accessed based on an address and a command received from the host and the set operating mode of the router (i.e., extension mode or mirror mode). Then, the accessed data is processed at a processing circuit included in the processing buffer circuit, based on a processing command received from the host. The mode register set command, the address, the command, and the processing command may be transmitted from the host to the memory module in compliance with a DDR SDRAM standard.

According to another exemplary embodiment, a memory module may include a processing buffer chip, and one or more DRAM chips that store data. The one or more DRAM chips may form a normal memory channel and a processing memory channel. The processing buffer chip may include a physical layer that receives a command/address signal and a data signal from a host, as well as a first memory controller and a second memory controller that respectively access the normal memory channel and the processing memory channel based on the command/address signal. A processing circuit is also provided that processes at least a portion of data stored in the normal memory channel accessed through the first memory controller and data stored in the processing memory channel accessed through the second memory controller, based on a processing command included in the data signal. In addition, a buffer is provided that stores data processed by the processing circuit, and a router is provided that receives the command/address signal and the data signal from the physical layer and transmits the command/address signal and the data signal to the first memory controller and the buffer. The processing buffer circuit communicates with the host in compliance with a DDR SDRAM standard.

