PRIORITY CLAIM

This patent application claims priority to Chinese Patent Application No. 202011060967.0, filed on Sep. 30, 2020, entitled “Split-Gate Non-volatile Memory Cells With Erase Gates Disposed Over Word Line Gates, And Method Of Making Same.”

FIELD OF THE INVENTION

The present invention relates to non-volatile memory arrays, and more particularly to a split gate, memory cell design and method of manufacture.

BACKGROUND OF THE INVENTION

Split gate non-volatile memory cells, and arrays of such cells, are well known. For example, U.S. Pat. No. 5,029,130 (“the '130 patent”) discloses an array of split gate non-volatile memory cells, and is incorporated herein by reference for all purposes. The memory cell is shown inFIG. 1. Each memory cell110includes source and drain regions114/116formed in a semiconductor substrate112, with a channel region118there between. A floating gate120is formed over and insulated from (and controls the conductivity of) a first portion of the channel region118, and over a portion of the drain region116. A control gate122has a first portion122athat is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region118, and a second portion122bthat extends up and over the floating gate120. The floating gate120and control gate122are insulated from the substrate112by a gate oxide126.

The memory cell is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the control gate122, which causes electrons on the floating gate120to tunnel through the intermediate insulation123from the floating gate120to the control gate122via Fowler-Nordheim tunneling.

The memory cell is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the control gate122, and a positive voltage on the drain region116. Electron current will flow from the source region114towards the drain region116. The electrons will accelerate and become heated when they reach the gap between the control gate122and the floating gate120. Some of the heated electrons will be injected through the gate oxide126onto the floating gate120due to the attractive electrostatic force from the floating gate120.

The memory cell is read by placing positive read voltages on the drain region116and control gate122(which turns on the channel region118under the control gate first portion122a). If the floating gate120is positively charged (i.e. erased of electrons and positively coupled to the drain region116), then the portion of the channel region118under the floating gate120is turned on as well, and current will flow across the channel region118, which is sensed as the erased or “1” state. If the floating gate120is negatively charged (i.e. programmed with electrons), then the portion of the channel region under the floating gate120is mostly or entirely turned off, and current will not flow (or there will be little flow) across the channel region118, which is sensed as the programmed or “0” state. Those skilled in the art understand that the source and drain regions can be interchangeable, where the floating gate120can extend partially over the source region114instead of the drain region116, as shown inFIG. 2.

Split gate memory cells having more than two gates are also known. For example, U.S. Pat. No. 8,711,636 (“the '636 patent”) discloses memory cells with an additional coupling gate disposed over and insulated from the source region, for better capacitive coupling to the floating gate. See for exampleFIG. 3showing coupling gate124disposed over source region14.

A four gate memory disclosed in U.S. Pat. No. 6,747,310 (“the '310 patent”). For example, as shown inFIG. 4, the memory cells have source region114, drain region116, floating gate120over a first portion of channel region118, a select (word line) gate128over a second portion of the channel region118, a control gate122over the floating gate120, and an erase gate130over the source region14. Programming is shown by heated electrons from the channel region118injecting themselves onto the floating gate120. Erasing is shown by electrons tunneling from the floating gate120to the erase gate130by placing a positive voltage on the erase gate130(and optionally a negative voltage on the control gate122). However, this configuration is not ideal because erase efficiency can be compromised by the high coupling ratio between the erase gate and the floating gate, and it can be complex to manufacture.

Conventional memory cell designs and methods of fabrication make it challenging to scale the memory cells down in size while maintaining or even enhancing performance, and streamlining fabrication processes.

BRIEF SUMMARY OF THE INVENTION

The aforementioned problems and needs are addressed by a memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region, a first coupling gate disposed over and insulated from the first floating gate, a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region, and a first erase gate disposed over and insulated from the first word line gate.

A method of forming memory cells includes forming a first insulation layer on a semiconductor substrate having a first conductivity type, forming a first conductive layer on the first insulation layer, forming a second insulation layer on the first conductive layer, forming a second conductive layer on the second insulation layer, forming a third insulation layer on the second conductive layer, forming a trench that extends through the third insulation layer, the second conductive layer, and the second insulation layer, forming insulation spacers along a sidewall of the trench, extending the trench through the first conductive layer between the insulation spacers, forming a first block of conductive material in the trench, wherein the first block of conductive material is disposed vertically over and insulated from the substrate and laterally adjacent to and insulated from the first conductive layer, forming first and second erase gates in the trench, wherein the first and second erase gates are disposed vertically over and insulated from the first block of conductive material, removing a portion of the first block of conductive material between the first and second erase gates, while maintaining first and second portions of the first block of conductive material as respective first and second word line gates, forming a first region in a portion of the substrate between the first and second word line gates and having a second conductivity type different than the first conductivity type, removing portions of the second conductive layer while maintaining first and second portions of the second conductive layer as respective first and second coupling gates, removing portions of the first conductive layer while maintaining first and second portions of the first conductive layer as respective first and second floating gates, and forming second and third regions in the substrate and having the second conductivity type, wherein the second region is adjacent to the first floating gate and the third region is adjacent to the second floating gate, wherein a first channel region in the substrate extends between the first and second regions and a second channel region in the substrate extends between the first and third regions. The first floating gate is disposed over and insulated from the substrate and laterally adjacent to and insulated from the first word line gate. The second floating gate is disposed over and insulated from the substrate and laterally adjacent to and insulated from the second word line gate. The first coupling gate is disposed over and insulated from the first floating gate. The second coupling gate is disposed over and insulated from the second floating gate. The first erase gate is disposed over and insulated from the first word line gate. The second erase gate is disposed over and insulated from the second word line gate.

Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.

