CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0108222, filed on Sep. 2, 2019, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present disclosure relates to a three-dimensional semiconductor memory device, and in particular, to a three-dimensional semiconductor memory device with improved electric characteristics.

Higher integration of semiconductor devices is required to satisfy consumer demands for superior performance and inexpensive prices. In the case of semiconductor devices, since their integration is an important factor in determining product prices, increased integration is especially beneficial. In the case of two-dimensional or planar semiconductor devices, since their integration is mainly determined by the area occupied by a unit memory cell, integration is greatly influenced by the level of a fine pattern forming technology. However, the extremely expensive process equipment needed to increase pattern fineness sets a practical limitation on increasing integration for two-dimensional or planar semiconductor devices. Thus, three-dimensional semiconductor memory devices including three-dimensionally arranged memory cells have recently been proposed.

SUMMARY

An embodiment of the inventive concept provides a three-dimensional semiconductor memory device with improved electric characteristics.

According to an embodiment of the inventive concept, a three-dimensional semiconductor memory device, including a first chip and a second chip stacked on the first chip may be provided. The first chip may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs on the first peripheral circuit region of the first substrate, and second contact plugs on the second peripheral circuit region of the first substrate, and a first passive device on and electrically connected to the second contact plugs. The second chip may include a second substrate disposed on the first chip, the second substrate including a cell array region and a contact region, which vertically overlap the second peripheral circuit region and the first peripheral circuit region of the first chip, respectively. The second chip may further include gate electrodes stacked on the cell array region and the contact region of the second substrate and disposed between the first chip and the second substrate of the second chip, and cell contact plugs disposed on the contact region of the second substrate and on end portions of the gate electrodes and connected to the first contact plugs. The first passive device may be vertically between the gate electrodes and the second contact plugs and may include a first contact line.

According to an embodiment of the inventive concept, a three-dimensional semiconductor memory device, including a first substrate having a first peripheral circuit region and a second peripheral circuit region, first transistors on the first peripheral circuit region of the first substrate, first contact plugs connected to the first transistors, first contact lines on the first contact plugs, second transistors on the second peripheral circuit region of the first substrate, and second contact plugs connected to the second transistors. The three-dimensional semiconductor memory device may further include a second substrate disposed on the first contact lines, the second substrate comprising a first region and a second region, which vertically overlap the first peripheral circuit region and the second peripheral circuit region, respectively, gate electrodes stacked on the second region of the second substrate and between the second substrate and the second contact plugs, and cell contact plugs, which are disposed on the second region of the second substrate and on end portions of the gate electrodes and are connected to the second contact plugs. The first contact lines may be electrically disconnected from the second substrate.

According to an embodiment of the inventive concept, a three-dimensional semiconductor memory device, including a first substrate having a first peripheral circuit region and a second peripheral circuit region, first transistors on the first peripheral circuit region of the first substrate, an interlayered insulating layer covering the first transistors on the first substrate, and first contact plugs, which are provided to penetrate the interlayered insulating layer and are connected to the first transistors. The three-dimensional semiconductor memory device may further include first contact lines on the first contact plugs, a second substrate disposed on the interlayered insulating layer, the second substrate comprising a first region and a second region, which vertically overlap with the first peripheral circuit region and the second peripheral circuit region, respectively, gate electrodes, which are disposed between the second substrate and the interlayered insulating layer and are stacked on the second region of the second substrate, and vertical channel portions penetrating the gate electrodes. The adjacent contact lines of the first contact lines may constitute electrodes of a capacitor.

