The present application claims priority to the Chinese Patent Application No. CN201910089177.6, filed with the Chinese Patent Office on Jan. 30, 2019, and entitled “DRIVING METHOD, DISPLAY PANEL AND DRIVING CIRCUIT”, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present application relates to the technical field of display, and in particular, to a driving method, a display panel and a driving circuit.

BACKGROUND

The statements herein merely provide background information related to the present application and do not necessarily constitute the prior art.

With the development and advancement of technologies, flat panel displays have become mainstream products of displays due to their thin bodies, power-saving and low radiation, and thus have been widely used. The flat panel displays include Thin Film Transistor-Liquid Crystal Displays (TFT-LCDs), Organic Light-Emitting Diode (OLED) displays, etc. The TFT-LCDs control the rotation direction of liquid crystal molecules to refract light of a backlight module to generate a picture, and has many advantages such as thin bodies, power-saving and no radiation. Moreover, the OLED displays are prepared by OLEDs, and have many advantages such as self-illumination, short response time, high definition and contrast, and can realize flexible display and large-area full-color display.

In the use of a general liquid crystal display, changes of the pixel voltage generally cause flickers, affecting the display effect.

SUMMARY

The present application provides a driving method, a display panel and a driving circuit for reducing flickers caused by a kickback voltage.

To achieve the foregoing objective, the present application provides a driving method, applied to a display panel. The display panel includes: a plurality of data lines and a plurality of gate lines, the gate lines being intersected with the data lines, further includes a plurality of pixels, each respectively driven by corresponding data line and gate line, each pixel including a corresponding pixel electrode; and a plurality of common lines respectively disposed between upper and lower gate lines, the common lines overlapping with a pixel electrode of a pixel corresponding to the previous gate line and overlapping with a pixel electrode of a pixel corresponding to the next gate line; the driving method includes a step of outputting a gate driving signal to a corresponding gate line of the display panel; where a signal period of a common level signal of the common line includes a first time and a second time, the first time corresponds to a first common level, the second time corresponds to a second common level, and a voltage value of the first common level in the first time is less than a voltage value of the second common level in the second time; for the common line corresponding to the Nthgate line, a start moment of the first time is no later than an open moment of the corresponding Nthgate line, and a start moment of the second time is no earlier than a close moment of the (N+1)thgate line; and N is a natural number at least equal to 1.

Optionally, at a same moment, the common line corresponding to the Nthgate line is open at the first time, and the corresponding Nthgate line is also open.

Optionally, the start moment of the second time and the close moment of the (N+1)thgate line are the same moment.

Optionally, the each pixel includes a pixel electrode, a same common line is connected to two adjacent pixels to form a pixel group, the pixel group includes a first pixel and a second pixel, and the first pixel and the second pixel are connected to different data lines and gate lines; where a pixel electrode of the first pixel of the pixel group overlaps with the common line to form a first overlap region; a first storage capacitance formed by the first overlap region of the first pixel and the common line is Cst1, a pixel capacitance of the first pixel is Clc1, and a parasitic capacitance formed by the pixel electrode of the first pixel and the Nthgate line is Cgs1; the first common level corresponding to the first time is Vcom, and the second common level corresponding to the second time is V′com; a voltage value of a high level of the gate open time is VGH, and a voltage value of a low level of the gate close time is VGL; Cst1=(VGH−VGL)*Cgs1(V′com−Vcom).

Optionally, a pixel electrode of the second pixel of the pixel group overlaps with a same common line corresponding to the first pixel to form a second overlap region, a second storage capacitance formed by the second overlap region of the second pixel and the common line is Cst2, a pixel capacitance of the second pixel is Clc2, and a parasitic capacitance formed by the pixel electrode of the second pixel and the (N+1)thgate line is Cgs2; Cst2=(VGH−VGL)*Cgs2/(V′com−Vcom).

The present application discloses a display panel using the driving method, including: a plurality of pixels, a plurality of data lines and a plurality of gate lines, the gate lines being intersected with the data lines, each pixel being separately driven by corresponding data line and gate line, and the each pixel corresponding to a pixel electrode; and a plurality of common lines disposed between upper and lower gate lines; where a same common line is connected to two adjacent pixels to form a pixel group, the pixel group includes a first pixel and a second pixel, and the first pixel and the second pixel are connected to different data lines and gate lines; where pixel electrodes of the first pixel and the second pixel overlap with the same common line to form a first overlap region and a second overlap region, respectively.

Optionally, the common lines include main common lines and auxiliary common lines conducted to each other; the main common lines are intersected with the data lines, and the auxiliary common lines and the data lines are arranged in parallel; the main common lines overlap with the pixel electrode of the first pixel and the pixel electrode of the second pixel to form a first main overlap region and a second main overlap region, respectively; the auxiliary common lines include first auxiliary common lines and second auxiliary common lines, the pixel electrode of the first pixel and the first auxiliary common lines form a first auxiliary overlap region, and the pixel electrode of the second pixel and the second auxiliary common lines form a second auxiliary overlap region.

Optionally, there are two first auxiliary common lines, respectively disposed at both sides of the first pixel close to the data lines; and the two first auxiliary common lines overlap with the pixel electrode of the first pixel to form two overlap regions; there are two second auxiliary common lines, respectively disposed at both sides of the second pixel close to the data lines; and the two second auxiliary common lines overlap with the pixel electrode of the second pixel to form two overlap regions.

Optionally, the first auxiliary common line and the second auxiliary common line are a straight line.

Optionally, the two second auxiliary common lines and the two first auxiliary common lines form two straight lines.

Optionally, a first safety distance is arranged between the first auxiliary common line and the pixel electrode of the first pixel.

Optionally, a second safety distance is arranged between the auxiliary common line and the corresponding data line.

The present application discloses a driving method configured to driving a display panel. The display panel includes: a plurality of data lines and a plurality of gate lines intersected with each other, and further includes a plurality of pixels, each respectively driven by corresponding data line and gate line, each pixel including a corresponding pixel electrode; and a plurality of common lines respectively disposed between upper and lower gate lines, where a same common line is connected to two adjacent pixels to form a pixel group, the pixel group includes a first pixel and a second pixel, and the first pixel and the second pixel are connected to different data lines and gate lines, where the common line overlaps with a pixel electrode of a first pixel corresponding to the previous gate line to form a first overlap region, and the common line overlaps with a pixel electrode of a second pixel corresponding to the next gate line to form a second overlap region. The driving circuit includes a gate driving circuit configured to output a gate driving signal to a corresponding gate line of the display panel; where a signal period of a common level signal of the common line includes a first time and a second time, the first time corresponds to a first common level, the second time corresponds to a second common level, and a voltage value of the first common level in the first time is less than a voltage value of the second common level in the second time; for the common line corresponding to the Nthgate line, a start moment of the first time is no later than an open moment of the corresponding Nthgate line, and a start moment of the second time is later than a close moment of the (N+1)thgate line, and N is a natural number at least equal to 1.

Optionally, the common line corresponding to the Nthgate line is open at the first time, and the Nthgate line is also open.

Optionally, the start moment of the second time and the close moment of the (N+1)thgate line are the same moment.

Optionally, the each pixel includes a pixel electrode, a same common line is connected to two adjacent pixels to form a pixel group, the pixel group includes a first pixel and a second pixel, and the first pixel and the second pixel are connected to different data lines and gate lines; where a pixel electrode of the first pixel of the pixel group overlaps with the common line to form a first overlap region; a first storage capacitance formed by the first overlap region of the first pixel and the common line is Cst1, a pixel capacitance of the first pixel is Clc1, and a parasitic capacitance formed by the pixel electrode of the first pixel and the Nthgate line is Cgs1; the first common level corresponding to the first time is Vcom, and the second common level corresponding to the second time is V′com; a voltage value of a high level of the gate open time is VGH, and a voltage value of a low level of the gate close time is VGL; Cst1=(VGH−VGL)*Cgs1/(V′com−Vcom).

Optionally, a period of the first time is triple a period of the open time of a gate line.

Optionally, a pixel electrode of the second pixel of the pixel group overlaps with a same common line corresponding to the first pixel to form a second overlap region, a second storage capacitance formed by the second overlap region of the second pixel and the common line is Cst2, a pixel capacitance of the second pixel is Clc2, and a parasitic capacitance formed by the pixel electrode of the second pixel and the (N+1)thgate line is Cgs2; Cst2=(VGH−VGL)*Cgs2/(V′com−Vcom).

Compared to the solution of further dividing RGB sub-pixels into main/sub-pixels so that the overall large view-angle brightness is closer to the front view with the voltage change, i.e., applying different driving voltages by the main/sub-pixels spatially to solve the color offset of the view angle, in the present application, the gate electrode and the pixel electrode generate a parasitic capacitance Cgs, and a kickback voltage generated by the parasitic capacitance Cgs redistributes a storage capacitance and a liquid crystal capacitance, two pixels corresponding to the upper and lower gate lines of the same common line are respectively formed with a storage capacitance Cst; when the corresponding n gate lines are closed, the charging voltage of the pixel electrode may have a drop due to the influence of the parasitic capacitance. In this solution, two different common levels are provided, and the voltage value of the first common level in the first time is less than the voltage value of the second common level in the second time; the common line increases from a lower first common level to a higher second common level after the close moment of the (N+1)thgate line, and thus has a rising edge, which would affect the charging voltage of the corresponding pixel and can cancel at least a part of the drop. Increasing the storage capacitance as far as possible can reduce the flickers formed by the kickback voltage, increase the voltage maintenance rate and reduce the voltage drop of the pixel electrode, without sacrificing a light-transmission opening region, influencing the penetration rate of the panel, or increasing the backlight cost.

