CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2020-0065283, filed on May 29, 2020, which is incorporated herein by reference in its entirety.

BACKGROUND

Field of Invention

The present disclosure relates to an electronic device, and more particularly, to an error correction circuit.

DESCRIPTION OF RELATED ART

A memory system may include a storage medium that temporarily or permanently stores data. During various operations such as write, read, transmission or processing, a data error or data corruption may occur.

In order to ensure reliability of the data, the memory system may use error correction techniques such as error correction encoding and error correction decoding.

SUMMARY

Embodiments of the present disclosure provide an error correction circuit capable of differently applying an RAID technique according to the circuit's error correction capability.

According to an embodiment of the present disclosure, an error correction circuit performing error correction encoding on a plurality of messages to be stored in a memory device includes a first error correction encoder and a second error correction encoder. The first error correction encoder generates a plurality of codewords by performing first error correcting encoding on each of the plurality of messages. The second error correction encoder performs a second error correction encoding operation by performing an exclusive OR operation on symbols of an identical column layer within the codewords. The second error correction encoder determines a data unit as a target of the second error correction encoding operation based on a use period of the memory device.

According to another embodiment of the present disclosure, a method of performing an error correction encoding on a plurality of messages to be stored in a memory device includes generating a plurality of codewords by performing first error correcting encoding on each of the plurality of messages, and performing a second error correction encoding operation of performing an exclusive OR operation on symbols of an identical column layer within the codewords. A data unit as a target of the second error correction encoding operation is determined based on a use period of the memory device.

According to another embodiment of the present disclosure, an operating method of an error correction encoder including performing a first error correction encoding operation on a message to generate a plurality of codewords, grouping the codewords into a plurality of groups, a number of the codewords in each of the groups depending on a use period of a memory device, and performing a second error correction encoding operation on the respective groups to generate a plurality of maximum distance separable (MDS) codewords. The MDS codewords are to be stored into the memory device.

According to the present technology, RAID techniques having different resource consumption may be applied according to error correction capability, and thus efficient use of resources may be achieved.

