CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2018-0059180, filed on May 24, 2018, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a semiconductor circuit, and more particularly, to a semiconductor apparatus with a domain crossing function.

2. Related Art

In a semiconductor apparatus, a clock signal used on a transmitter side may have a different frequency from a clock signal used on a receiver side.

When the clock signals used on the transmitter side and the receiver side have different frequencies, a signal received by the receiver side may not have a value of ‘0’ or ‘1’. Then, the semiconductor apparatus may be trapped in a metastable state so as not to recognize the corresponding signal. In this case, the semiconductor apparatus might not perform a normal receiving operation.

Therefore, when the transmitter side and the receiver side have different clock domains, the receiver-side circuit requires a circuit for removing a frequency difference between the clock signals.

SUMMARY

In accordance with the present teachings, a semiconductor apparatus may include a first semiconductor apparatus configured to transmit a first input signal as first data in synchronization with a first edge of a first clock signal having a first frequency. The semiconductor apparatus may also include a second semiconductor apparatus including: a first storage unit, configured to receive the first data as a set signal and output a second input signal as a first internal signal in synchronization with a first edge of a second clock signal having a second frequency; and a second storage unit, configured to output the internal signal as second data in synchronization with a second edge of the second clock signal.

Also in accordance with the present teachings, a semiconductor apparatus may include a first semiconductor apparatus configured to transmit a first input signal as first data in synchronization with a first edge of a first clock signal having a first frequency. The semiconductor apparatus may also include a second semiconductor apparatus including: a first storage unit, configured to receive the first data as a set signal and output a second input signal as an internal signal in synchronization with a first edge of a second clock signal having a second frequency; a second storage unit, configured to output the first internal signal as a second internal signal in synchronization with the first edge of the second clock signal; and an edge detection circuit, configured to generate second data by detecting a first edge of the second internal signal according to the second clock signal.

