CROSS-REFERENCE TO RELATED APPLICATION

This U.S. nonprovisional application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0006638 filed on Jan. 17, 2020 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

The present inventive concepts relate to a three-dimensional semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device with increased reliability.

Semiconductor devices have been highly integrated to meet higher performance and/or lower manufacturing cost which are required by customers. Because integration of the semiconductor devices is a factor in determining product price, high integration is increasingly requested. Integration of typical two-dimensional or planar semiconductor devices is primarily determined by the area occupied by a unit memory cell, such that it is influenced by the level of technology for forming fine patterns. However, the expensive processing equipment needed to increase pattern fineness may set a practical limitation on increasing the integration of the two-dimensional or planar semiconductor devices. Therefore, there have been proposed three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells.

SUMMARY

Some example embodiments of the present inventive concepts provide a three-dimensional semiconductor memory device with increased reliability.

An advantage of the present inventive concepts is not limited to the mentioned above, and other advantages which have not been mentioned above will be clearly understood to those skilled in the art from the following description.

According to some example embodiments of the present inventive concepts, a three-dimensional semiconductor memory device may comprise: a substrate including a cell region and a connection region; a plurality of inter-electrode dielectric layers and a plurality of electrode layers alternately stacked on the substrate, ends of the plurality of electrode layers forming a stepwise shape on the connection region; a planarized dielectric layer on the connection region, the planarized dielectric layer covering the ends of the plurality of electrode layers; and a first abnormal dummy vertical pattern on the connection region, the first abnormal dummy vertical pattern penetrating the planarized dielectric layer in a first direction perpendicular to a top surface of the substrate. At least one of the plurality of electrode layers may be positioned between the first abnormal dummy vertical pattern and the substrate and may be insulated from the first abnormal dummy vertical pattern.

According to some example embodiments of the present inventive concepts, a three-dimensional semiconductor memory device may comprise: a substrate including a cell region and a connection region; a first stack structure including a plurality of first inter-electrode dielectric layers and a plurality of first electrode layers alternately stacked on the substrate; a second stack structure including a plurality of second inter-electrode dielectric layers and a plurality of second electrode layers alternately stacked on the first stack structure; a cell vertical pattern on the cell region, the cell vertical pattern penetrating the first and second stack structures in a first direction perpendicular to a top surface of the substrate; and an abnormal dummy vertical pattern on the connection region, the abnormal dummy vertical pattern penetrating one or more of the plurality of second electrode layers. A sidewall of the cell vertical pattern may have an inflection point adjacent to a boundary between the first stack structure and the second stack structure. At least one of the plurality of first electrode layers may be interposed in the first direction between the abnormal dummy vertical pattern and the substrate.

According to some example embodiments of the present inventive concepts, a three-dimensional semiconductor memory device may comprise: a peripheral circuit structure including a transistor and a peripheral wiring line; and a cell array structure on the peripheral circuit structure. The cell array structure may include: a first substrate including a cell region and a connection region; a first stack structure including a plurality of first inter-electrode dielectric layers and a plurality of first electrode layers alternately stacked on the first substrate; a second stack structure including a plurality of second inter-electrode dielectric layers and a plurality of second electrode layers alternately stacked on the first stack structure; an abnormal dummy vertical pattern on the connection region, the abnormal dummy vertical pattern penetrating one or more of the second plurality of electrode layers in a first direction perpendicular to a top surface of the substrate; and a sacrificial buried pattern in the first stack structure on the connection region, the sacrificial buried pattern being spaced apart from the abnormal dummy vertical pattern.

