BACKGROUND

Technical Field

Some embodiments relate to an apparatus for compensating parasitic impedance for integrated circuits and in particular but not exclusively to an apparatus for compensating parasitic impedance for integrated circuits for supplying current for laser diodes.

Description of the Related Art

Circuits and methods of driving Laser Diodes (LD) such as vertical cavity surface emitting laser (VCSEL) diodes are known.

An issue with conventional current drivers and laser diode technologies is one of driving current to the laser diode and the inductance produced by the connections between the driver circuitry and the laser diode.

Laser diode driver circuit modules and other circuit modules such as time of flight determination modules are typically mounted as dies on a sub-mount away from the laser diode die. This is done in order to physically, optically and electrically isolate the laser diode as far as possible from other circuitry. Furthermore this allows the production of the laser diode to be fabricated using a first process technology and the driver circuitry and other circuitry using a second process technology, where each process technology is optimized for the respective module.

Connections between modules are then formed by the use of contact pads and bonding wires. These contact pads and bonding wires form parasitic inductances which are significant with respect to the currents (10s-100s A) and pulse widths (2-7 ns with 1 ns rise time) used for example in time of flight range detecting applications.

BRIEF SUMMARY

According to a first aspect, there is provided a laser diode driver circuit comprising: a first pair of contacts and connectors coupled to an anode of the laser diode, wherein an inductance of each of the first pair of contacts and connectors is the same; a second pair of contacts and connectors coupled to a cathode of the laser diode, wherein an inductance of each of the second pair of contacts and connectors is the same; current driving circuitry, wherein the current driving circuitry is configured to operate such that: in a first phase a first current passes through the first pair of contacts and connectors and a further current passes through the a second pair of contacts and connectors such that a potential difference between the cathode and anode is below a diode activation value; in a second phase, succeeding the first phase, the further current passes through a first of the first pair of contacts and connectors, the laser diode and a first of the second pair of contacts and connectors such that the potential difference between the cathode and anode is above the diode activation value; in a third phase, succeeding the second phase, a current passes through a first of the first pair of contacts and connectors, the laser diode and a first of the second pair of contacts and connectors and the potential difference between the cathode and anode is below the diode activation value.

The current driving circuitry may comprise: a first switch configured to selectively couple the first of the first pair of contacts and connectors to a high potential supply node wherein in the first, second and third phase the first switch is configured to couple the first of the first pair of contacts and connectors to a high potential supply node.

The first switch may comprise a pMOS transistor controlled by a safety control signal.

The current driving circuitry may further comprise: a diode with an anode coupled to the second of the first pair of contacts and connectors and a cathode coupled to the high potential supply node; a current source for providing the first current; and a second switch configured to selectively couple the second of the first pair of contacts and connectors to a low potential supply node via the current source, wherein: in the first phase the second switch is configured to couple the second of the first pair of contacts and connectors to a low potential supply node via the current source so that the first current passes through the first pair of contacts and connectors; in the second phase the second switch is configured to uncouple the second of the first pair of contacts and connectors to a low potential supply node via the current source so that the first current passes through the first pair of contacts and connectors and the diode is configured to provide a shunt current path to shunt current from the inductance of the second of the first pair of contacts and connectors; in the third phase the second switch is configured to uncouple the second of the first pair of contacts and in combination with the diode provide a high impedance node.

The second switch may comprise an nMOS transistor controlled by an anode control signal.

The current driving circuitry may further comprise: a further switch configured to selectively couple the second of the second pair of contacts and connectors to a high potential supply node; and a further diode with a cathode coupled to the second of the second pair of contacts and connectors and an anode coupled to a low potential supply node; wherein: in the first phase the further switch is configured to couple the second of the second pair of contacts and connectors to a high potential supply node; in the second phase the further switch is configured to uncouple the second of the second pair of contacts and connectors from the high potential supply node such that the further diode is configured to provide a shunt current path to shunt current from the inductance of the second of the second pair of contacts and connectors; and in the third phase the further switch is configured to uncouple the second of the second pair of contacts and in combination with the further diode provide a high impedance node.

The further switch may comprise a pMOS transistor controlled by a cathode control signal.

The current driving circuitry may further comprise: a current source for providing the further current and selectively coupling the first of the second pair of contacts and connectors to a low potential supply node; and a second further switch configured to selectively couple the first of the second pair of contacts and connectors to a high potential supply node, wherein: in the first phase the current source is configured to couple the first of the second pair of contacts and connectors to a low potential supply node such that the further current passes through the second pair of contacts and connectors; in the second phase the current source is configured to couple the first of the second pair of contacts and connectors to a low potential supply node such that the further current passes through a first of the first pair of contacts and connectors, the laser diode and a first of the second pair of contacts and connectors; and in the third phase the second further switch configured to selectively couple the first of the second pair of contacts and connectors to a high potential supply node and provide a snub current path to snub current from the inductance of the first of the second pair of contacts and connectors.

The further switch may comprise a pMOS transistor controlled by a further cathode control signal.

The laser diode driver circuit may further comprise: timing generating circuitry configured to generate four phase shifted clock signals; combinational logic configured to receive the four phase shifted clock signals and generate phase defining signals for defining a start of the first phase, a start of the second phase and a start of the third phase, wherein the phase defining signals are based on one of: falling edges from the four phase shifted clock signals and falling edges from the four phase shifted clock signals; a level shifter for receiving the phase defining signals and output signals for controlling the current driving circuitry in order to operate in the first phase, the second phase and the third phase.

The timing generating circuitry may be configured to generate: a first clock signal; a second clock signal, which is a first phase-shifted version of the first clock signal and wherein; a third clock signal, which is a second phase-shifted version of the first clock signal and wherein subsequent falling or rising edges of the first clock signal and the third clock signal define the passing of the first current passing through the first pair of contacts and connectors and wherein subsequent falling or rising edges of the second clock signal and the third clock signal define the passing of the further current passing through the second pair of contacts and connectors; a fourth clock signal, which is a third phase-shifted version of the first clock signal, wherein a falling or rising edge of the third clock signal and the rising or falling edge of the fourth clock signal define the passing of the further current through the first of the first pair of contacts and connectors, the laser diode and the first of the second pair of contacts and connectors.

According to a second aspect there is provided a method comprising providing a laser diode driver circuit comprising: a first pair of contacts and connectors coupled to an anode of the laser diode, wherein an inductance of each of the first pair of contacts and connectors is the same; a second pair of contacts and connectors coupled to a cathode of the laser diode, wherein an inductance of each of the second pair of contacts and connectors is the same; current driving circuitry, wherein the method further comprises: operating the laser diode driver circuit in a first phase such that a first current passes through the first pair of contacts and connectors and a further current passes through the a second pair of contacts and connectors such that a potential difference between the cathode and anode is below a diode activation value;

operating the laser diode driver circuit in a second phase, succeeding the first phase, such that the further current passes through a first of the first pair of contacts and connectors, the laser diode and a first of the second pair of contacts and connectors such that the potential difference between the cathode and anode is above the diode activation value;

operating the laser diode driver circuit in a third phase, succeeding the second phase, such that a current passes through a first of the first pair of contacts and connectors, the laser diode and a first of the second pair of contacts and connectors and the potential difference between the cathode and anode is below the diode activation value.

The method may further comprise providing a first switch, the method further comprising using the first switch to selectively couple the first of the first pair of contacts and connectors to a high potential supply node wherein in the first, second and third phase the first switch is configured to couple the first of the first pair of contacts and connectors to a high potential supply node.

The first switch may comprise a pMOS transistor. The method may comprise controlling the pMOS transistor by a safety control signal.

The current driving circuitry may further comprise: a diode with an anode coupled to the second of the first pair of contacts and connectors and a cathode coupled to the high potential supply node; a current source for providing the first current; and a second switch configured to selectively couple the second of the first pair of contacts and connectors to a low potential supply node via the current source.

The method may further comprise coupling, using the second switch, in the first phase the second of the first pair of contacts and connectors to a low potential supply node via the current source so that the first current passes through the first pair of contacts and connectors.

The method may further comprise: uncoupling, using the second switch, in the second phase the second of the first pair of contacts and connectors to a low potential supply node via the current source so that the first current passes through the first pair of contacts and connectors and the diode is configured to provide a shunt current path to shunt current from the inductance of the second of the first pair of contacts and connectors. The method may further comprise: uncoupling, using the second switch, in the third phase the second of the first pair of contacts and in combination with the diode provide a high impedance node.

The second switch may comprise an nMOS transistor controlled by an anode control signal.

The current driving circuitry may further comprise: a further switch configured to selectively couple the second of the second pair of contacts and connectors to a high potential supply node; and a further diode with a cathode coupled to the second of the second pair of contacts and connectors and an anode coupled to a low potential supply node; wherein the method may comprise coupling using the further switch in the first phase the second of the second pair of contacts and connectors to a high potential supply node.

The method may further comprise uncoupling, using the further switch, in the second phase the second of the second pair of contacts and connectors from the high potential supply node such that the further diode is configured to provide a shunt current path to shunt current from the inductance of the second of the second pair of contacts and connectors.

The method may further comprise uncoupling, using the further switch, in the third phase the second of the second pair of contacts and in combination with the further diode provide a high impedance node.

The further switch may comprise a pMOS transistor controlled by a cathode control signal.

The current driving circuitry may further comprise: a current source for providing the further current and selectively coupling the first of the second pair of contacts and connectors to a low potential supply node; and a second further switch configured to selectively couple the first of the second pair of contacts and connectors to a high potential supply node, wherein the method may further comprise coupling using the current source the first of the second pair of contacts and connectors to a low potential supply node such that the further current passes through the second pair of contacts and connectors.

The method may further comprise coupling, using the current source, in the second phase the first of the second pair of contacts and connectors to a low potential supply node such that the further current passes through a first of the first pair of contacts and connectors, the laser diode and a first of the second pair of contacts and connectors.

The method may further comprise selectively coupling using the second further switch in the third phase the first of the second pair of contacts and connectors to a high potential supply node and provide a snub current path to snub current from the inductance of the first of the second pair of contacts and connectors.

The further switch may comprise a pMOS transistor controlled by a further cathode control signal.

The method may further comprise: generating four phase shifted clock signals; generating phase defining signals for defining a start of the first phase, a start of the second phase and a start of the third phase, wherein the phase defining signals are based on one of: falling edges from the four phase shifted clock signals and falling edges from the four phase shifted clock signals; generating output signals for controlling the current driving circuitry in order to operate in the first phase, the second phase and the third phase based on the phase defining signals.

The method may comprise generating: a first clock signal; a second clock signal, which is a first phase-shifted version of the first clock signal and wherein; a third clock signal, which is a second phase-shifted version of the first clock signal and wherein subsequent falling or rising edges of the first clock signal and the third clock signal define the passing of the first current passing through the first pair of contacts and connectors and wherein subsequent falling or rising edges of the second clock signal and the third clock signal define the passing of the further current passing through the second pair of contacts and connectors; a fourth clock signal, which is a third phase-shifted version of the first clock signal, wherein a falling or rising edge of the third clock signal and the rising or falling edge of the fourth clock signal define the passing of the further current through the first of the first pair of contacts and connectors, the laser diode and the first of the second pair of contacts and connectors.

According to a third aspect there is provided an apparatus comprising: laser diode driver means comprising: a first pair of contacts and connectors coupled to an anode of the laser diode, wherein an inductance of each of the first pair of contacts and connectors is the same; a second pair of contacts and connectors coupled to a cathode of the laser diode, wherein an inductance of each of the second pair of contacts and connectors is the same; current driving circuitry, wherein the current driver means is configured to operate such that: in a first phase a first current passes through the first pair of contacts and connectors and a further current passes through the a second pair of contacts and connectors such that a potential difference between the cathode and anode is below a diode activation value; in a second phase, succeeding the first phase, the further current passes through a first of the first pair of contacts and connectors, the laser diode and a first of the second pair of contacts and connectors such that the potential difference between the cathode and anode is above the diode activation value; in a third phase, succeeding the second phase, a current passes through a first of the first pair of contacts and connectors, the laser diode and a first of the second pair of contacts and connectors and the potential difference between the cathode and anode is below the diode activation value.

The current driver means may comprise: a first switch means configured to selectively couple the first of the first pair of contacts and connectors to a high potential supply node wherein in the first, second and third phase the first switch means is configured to couple the first of the first pair of contacts and connectors to a high potential supply node.

The first switch means may comprise a pMOS transistor controlled by a safety control signal.

The current driver means may further comprise: a diode with an anode coupled to the second of the first pair of contacts and connectors and a cathode coupled to the high potential supply node; a current source for providing the first current; and a second switch means configured to selectively couple the second of the first pair of contacts and connectors to a low potential supply node via the current source, wherein: in the first phase the second switch means is configured to couple the second of the first pair of contacts and connectors to a low potential supply node via the current source so that the first current passes through the first pair of contacts and connectors; in the second phase the second switch means is configured to uncouple the second of the first pair of contacts and connectors to a low potential supply node via the current source so that the first current passes through the first pair of contacts and connectors and the diode is configured to provide a shunt current path to shunt current from the inductance of the second of the first pair of contacts and connectors; in the third phase the second switch means is configured to uncouple the second of the first pair of contacts and in combination with the diode provide a high impedance node.

The second switch means may comprise an nMOS transistor controlled by an anode control signal.

The current driver means may further comprise: a further switch means configured to selectively couple the second of the second pair of contacts and connectors to a high potential supply node; and a further diode with a cathode coupled to the second of the second pair of contacts and connectors and an anode coupled to a low potential supply node; wherein: in the first phase the further switch means is configured to couple the second of the second pair of contacts and connectors to a high potential supply node; in the second phase the further switch means is configured to uncouple the second of the second pair of contacts and connectors from the high potential supply node such that the further diode is configured to provide a shunt current path to shunt current from the inductance of the second of the second pair of contacts and connectors; and in the third phase the further switch means is configured to uncouple the second of the second pair of contacts and in combination with the further diode provide a high impedance node.

The further switch means may comprise a pMOS transistor controlled by a cathode control signal.

The current driver means may further comprise: a current source for providing the further current and selectively coupling the first of the second pair of contacts and connectors to a low potential supply node; and a second further switch means configured to selectively couple the first of the second pair of contacts and connectors to a high potential supply node, wherein: in the first phase the current source is configured to couple the first of the second pair of contacts and connectors to a low potential supply node such that the further current passes through the second pair of contacts and connectors; in the second phase the current source is configured to couple the first of the second pair of contacts and connectors to a low potential supply node such that the further current passes through a first of the first pair of contacts and connectors, the laser diode and a first of the second pair of contacts and connectors; and in the third phase the second further switch means may be configured to selectively couple the first of the second pair of contacts and connectors to a high potential supply node and provide a snub current path to snub current from the inductance of the first of the second pair of contacts and connectors.

The further switch means may comprise a pMOS transistor controlled by a further cathode control signal.

The current driver means may further comprise: means for generating timing signals configured to generate four phase shifted clock signals; means for combining timing signals configured to receive the four phase shifted clock signals and generate phase defining signals for defining a start of the first phase, a start of the second phase and a start of the third phase, wherein the phase defining signals are based on one of: falling edges from the four phase shifted clock signals and falling edges from the four phase shifted clock signals; means for level shifting configured to receive the phase defining signals and output signals for controlling the current driving circuitry in order to operate in the first phase, the second phase and the third phase.

The means for generating timing signals may be configured to generate: a first clock signal; a second clock signal, which is a first phase-shifted version of the first clock signal and wherein; a third clock signal, which is a second phase-shifted version of the first clock signal and wherein subsequent falling or rising edges of the first clock signal and the third clock signal define the passing of the first current passing through the first pair of contacts and connectors and wherein subsequent falling or rising edges of the second clock signal and the third clock signal define the passing of the further current passing through the second pair of contacts and connectors; a fourth clock signal, which is a third phase-shifted version of the first clock signal, wherein a falling or rising edge of the third clock signal and the rising or falling edge of the fourth clock signal define the passing of the further current through the first of the first pair of contacts and connectors, the laser diode and the first of the second pair of contacts and connectors.

