FIELD

The present disclosure relates to multi-phase switched-mode power supplies, and particularly critically discontinuous multi-phase switched-mode power supplies.

BACKGROUND

This section provides background information related to the present disclosure which is not necessarily prior art.

Many customers are requiring power supplies to have a titanium-rated efficiency or higher, so the use of soft-switching power topologies is becoming more popular, such as the critically discontinuous mode for a front-end power factor correction (PFC) circuit. In order to reduce high peak currents that limit maximum output power, interleaved multi-phase operation is used.

Interleaved operation provides good ripple cancellation in the output voltage, but interleaving critically discontinuous mode circuits is difficult because the difference in switching frequencies between phases inhibits synchronization due to the zero current detection function of the critically discontinuous mode of operation.

SUMMARY

This section provides a general summary of the disclosure, and is not a comprehensive disclosure of its full scope or all of its features.

According to one aspect of the present disclosure, a multi-phase switched-mode power supply includes a pair of input terminals for receiving an alternating current (AC) or direct current (DC) voltage input from an input power source, a pair of output terminals for supplying a direct current (DC) voltage output to a load, and a first phase circuit coupled between the pair of input terminals and the pair of output terminals. The first phase circuit includes a first inductor coupled with a first switch. The power supply also includes a second phase circuit interleaved with the first phase circuit between the pair of input terminals and the pair of output terminals. The second phase circuit includes a second inductor coupled with a second switch. The power supply further includes a control circuit configured to output a first PWM signal to the first switch, and output a second PWM signal to the second switch. An on time of the second PWM signal is equal to an on time of the first PWM signal plus a fixed offset time period. The control circuit is configured to determine a period between at least two rising edges of the first PWM signal, determine an off trigger PWM signal according to the determined period, and change the second PWM signal to a logical low value when a falling edge of the off trigger PWM signal occurs while the second PWM signal has a logical high value.

According to another aspect of the present disclosure, a method controlling a multi-phase power supply is disclosed. The power supply includes a pair of input terminals for receiving an alternating current (AC) or direct current (DC) voltage input from an input power source, a pair of output terminals for supplying a direct current (DC) voltage output to a load, a first phase circuit coupled between the pair of input terminals and the pair of output terminals and including a first inductor coupled with a first switch, and a second phase circuit interleaved with the first phase circuit between the pair of input terminals and the pair of output terminals and including a second inductor coupled with a second switch. The method includes outputting a first PWM signal to the first switch, and outputting a second PWM signal to the second switch. An on time of the second PWM signal is equal to an on time of the first PWM signal plus a fixed offset time period. The method also includes determining a period between at least two rising edges of the first PWM signal, determining an off trigger PWM signal according to the determined period, an changing the second PWM signal to a logical low value when a falling edge of the off trigger PWM signal occurs while the second PWM signal has a logical high value.

Further aspects and areas of applicability will become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

