TECHNICAL FIELD

Integrated components which have both horizontally-oriented transistors and vertically-oriented transistors.

BACKGROUND

A continuing goal is to achieve ever-increasing levels of integration of integrated memory. A related goal is to increase the packing density of memory components. It is also desired to develop integrated memory having strong signal, good durability over a large number of read/write cycles, fast access rates, protection against cell-to-cell disturb mechanisms, etc.

An example memory device is a two-transistor-one-capacitor (2T-1C) device. An example prior art 2T-1C memory cell configuration is schematically illustrated inFIG. 1as a device2. The 2T-1C memory cell includes two transistors (T1and T2), and a capacitor (CAP) between the transistors. Each of the transistors comprises a gate. The gates are electrically coupled to one another, and are also electrically coupled to a wordline (WL). The transistors have source/drain regions coupled with comparative bitlines (BL-1and BL-2). The bitlines are coupled with a sense amplifier4configured to compare electrical properties (e.g., voltage) of the comparative bitlines to one another.

The 2T-1C memory cell may have many attractive features, including high signal strength, reduced cell-to-cell disturb mechanisms, good refresh, etc. However, difficulties are encountered in fabricating highly-integrated memory comprising 2T-1C devices.

Another example memory device is a ferroelectric memory device utilizing a ferroelectric capacitor for memory/storage. For instance, ferroelectric capacitors may be incorporated into ferroelectric random access memory (FeRAM). FeRAM may have many attractive features, including nonvolatility, low power consumption, high-speed operation, etc. However, difficulties are encountered in fabricating highly-integrated memory comprising FeRAM.

It is desired to develop improved memory devices, and to develop improved memory arrays incorporating such devices.

