TECHNICAL FIELD

The present disclosure relates generally to the technical field of integrated circuits (ICs) and more specifically, but not by way of limitation, to an IC power-up testing method, an IC power-up testing device, a memory medium and an electronic equipment.

BACKGROUND

In an IC fabrication process, a plurality of tests needs to be conducted in different stages of the fabrication so that potential defects in a product can be detected before the product is released to the market. As a result, the yield of the IC products can be improved. Existing IC test devices, however, are designed to test only some specific functionalities, and the power-up process of the IC is performed by a separated power-up device different from the test device used in the subsequent functional tests. An issue in the power-up process may affect the following functional tests. Due to different test environments, it is difficult to determine whether there exists any problem in the power-up process based on the test result of the subsequent functional tests. Therefore, there is an urgent need to integrate the power-up process and subsequent functional tests of an IC.

It is to be noted that the information disclosed in this Background section is only for facilitating the understanding of the background of the disclosure and therefore may contain information that does not form the prior art known to a person of ordinary skill in the art.

SUMMARY

In view of the limitation of existing technologies described above, the present disclosure provides a power-up testing method applicable to an integrated circuit (IC), an IC power-up testing device, a computer-readable memory medium and an electronic equipment that address at least some of the above-discussed limitations and deficiencies in the related art, including the difficulty in testing and analyzing an issue raised in the power-up process of an IC using existing test devices.

One aspect of the present disclosure is directed to a power-up testing method, applicable to an integrated circuit (IC). The method may include: obtaining power-up testing parameters for the IC; obtaining a plurality of power-up testing waveforms; generating a plurality of power-up test instances by conducting parameter assignments for the power-up testing waveforms based on the power-up testing parameters; and performing power-up tests on the IC using the plurality of power-up test instances.

In some embodiments of the present disclosure, obtaining power-up testing parameters for the IC may include: obtaining a target voltage and power-up duration for the IC.

In some embodiments of the present disclosure, obtaining power-up testing parameters for the IC may further include: obtaining a number for voltage steps for the IC.

In some embodiments of the present disclosure, obtaining a number of voltage steps for the IC may include: obtaining a maximum number and a minimum number of voltage steps; and choosing a number between the maximum number and the minimum numbers as the number for voltage steps.

In some embodiments of the present disclosure, generating a plurality of power-up test instances by conducting parameter assignments for the power-up testing waveforms based on the power-up testing parameters may include: determining a step height of the voltage steps based on the target voltage and the number of voltage steps; determining a step width of the voltage steps based on the power-up duration and the number of voltage steps; and generating the plurality of power-up test instances by conducting parameter assignments for the power-up testing waveforms based on the step height and the step width.

In some embodiments of the present disclosure, obtaining a plurality of power-up testing waveforms may include: obtaining a plurality of initial waveforms and a plurality of noise waveforms; and obtaining the plurality of power-up testing waveforms by superimposing the plurality of initial waveforms and the plurality of noise waveforms.

In some embodiments of the present disclosure, the plurality of initial waveforms and the plurality of noise waveforms may be step voltage waveforms.

In some embodiments of the present disclosure, each of the plurality of initial waveforms may be an ascending step waveform, and each of the plurality of noise waveforms may be a randomly distributed step waveform.

In some embodiments of the present disclosure, obtaining a plurality of initial waveforms and a plurality of noise waveforms may include: choosing the plurality of initial waveforms and the plurality of noise waveforms from a predefined test waveform library.

In some embodiments of the present disclosure, performing power-up tests on the IC using the plurality of power-up test instances may include: arranging the power-up test instances into a test sequence; and performing power-up tests on the IC by successively using each of the power-up test instances in the test sequence. If a test result of using one of the power-up test instances in the test sequence is a failure, the power-up tests on the IC continue by using a next one of the power-up test instances in the test sequence.

In some embodiments of the present disclosure, performing power-up tests on the IC using the plurality of power-up test instances may include: arranging the power-up test instances into a test sequence; and performing power-up tests on the IC by successively using each of the power-up test instances in the test sequence. If a test result of using one of the power-up test instances in the test sequence is a failure, the power-up tests on the IC is terminated.

Another aspect of the present disclosure is directed to an IC power-up testing device. The device may include: an acquisition circuit, an assignment circuit, and a testing circuit. The acquisition circuit may be configured to obtain power-up testing parameters for an IC, and a plurality of power-up testing waveforms. The assignment circuit may be configured to generate a plurality of power-up test instances by conducting parameter assignments for the power-up testing waveforms based on the power-up testing parameters. The testing circuit may be configured to perform power-up tests on the IC using the plurality of power-up test instances.

Another aspect of the present disclosure is directed to an electronic equipment. The electronic equipment may include: a processor and a memory. The memory may be configured to store instructions executable by the processor. The processor may be configured to, by executing the instructions, perform a power-up testing method applicable to an IC. The method may include: obtaining power-up testing parameters for the IC; obtaining a plurality of power-up testing waveforms; generating a plurality of power-up test instances by conducting parameter assignments for the power-up testing waveforms based on the power-up testing parameters; and performing power-up tests on the IC using the plurality of power-up test instances.

In some embodiments of the present disclosure, when obtaining power-up testing parameters for the IC, the processor may be further configured to obtain a target voltage and a power-up duration for the IC.

In some embodiments of the present disclosure, when obtaining power-up testing parameters for the IC, the processor may be further configured to obtain a number of voltage steps for the IC.

In some embodiments of the present disclosure, to obtain a number of voltage steps for the IC, the process may be further configured to obtain a maximum number and a minimum number of voltage steps; and choose a number between the maximum number and the minimum number as the number of voltage steps.

In some embodiments of the present disclosure, when generating a plurality of power-up test instances, the processor may be further configured to determine a step height of the voltage steps based on the target voltage and the number of voltage steps; determine a step width of the voltage steps based on the power-up duration and the number of voltage steps; and generate the plurality of power-up test instances by conducting parameter assignments for the power-up testing waveforms based on the step height and the step width.

In some embodiments of the present disclosure, when obtaining power-up testing parameters for the IC, the processor may be further configured to obtain a plurality of initial waveforms and a plurality of noise waveforms; and obtain the plurality of power-up testing waveforms by superimposing the plurality of initial waveforms with the plurality of noise waveforms.

In some embodiments of the present disclosure, the plurality of initial waveforms and the plurality of noise waveforms may be step voltage waveforms.

In some embodiments of the present disclosure, each of the plurality of initial waveforms may be an ascending step waveform, and each of the plurality of noise waveforms may be a randomly distributed step waveform.

According to the embodiments of the present disclosure, a plurality of power-up test instances may be generated based on various power-up testing waveforms and power-up testing parameters, which may be used to simulate various IC power-up scenarios. In addition, the various power-up test instances can be implemented as program codes executable by a functional test device. Thus, both the power-up test and subsequent functional tests can be performed and controlled by one single functional test device, which facilitates the interpretation of the test results.

The above general description and the following detailed description are intended to be illustrative and do not limit the present disclosure.

