CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2019-092452, filed on May 15, 2019, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the invention relate to a superjunction semiconductor device and method of manufacturing a superjunction semiconductor device.

2. Description of the Related Art

In a general vertical n-type-channel metal oxide semiconductor field effect transistor (MOSFET), among plural semiconductor layers formed in a semiconductor substrate, the semiconductor layer having a resistance that is highest is an n-type conductive layer (drift layer). Electrical resistance of this n-type drift layer greatly affects ON resistance of the vertical MOSFET overall. Reduction of the ON resistance of the vertical MOSFET overall may be realized by reducing a thickness of the n-type drift layer and thereby, shortening a current path.

Nonetheless, the vertical MOSFET has a function of sustaining breakdown voltage by the spreading of a depletion layer to the high-resistance n-type drift layer in an OFF state. Therefore, when the n-type drift layer is made thinner to reduce the ON resistance, a distance that the depletion layer spreads during the OFF state decreases, whereby critical electric field strength is easily reached by application of low voltage and the breakdown voltage decreases. On the other hand, to increase the breakdown voltage of the vertical MOSFET, the thickness of the n-type drift layer has to be increased, whereby the ON resistance increases. This type of relationship between the ON resistance and the breakdown voltage is called a tradeoff relationship and in general, it is difficult to enhance both counterparts having a tradeoff relationship. The tradeoff relationship between the ON resistance and the breakdown resistance is known to similarly exist in semiconductor devices such as insulated gate bipolar transistors (IGBTs), bipolar transistors, and diodes.

A superjunction (SJ) structure is known as a structure of a semiconductor device that solves the problems described above. For example, a MOSFET (hereinafter, SJ-MOSFET) having a superjunction structure is known.FIG. 23is a cross-sectional view of a structure of a conventional SJ-MOSFET.

As depicted inFIG. 23, in a SJ-MOSFET150, an n-type layer102is grown on an n+-type semiconductor substrate101having a high impurity concentration. At a depth not reaching the n+-type semiconductor substrate101from a surface of the n-type layer102, p-type columns104are provided. Bottoms of the p-type columns104reach an n-type buffer layer102′ provided between the n+-type semiconductor substrate101and the n-type layer102. InFIG. 23, while the p-type columns104do not reach the n+-type semiconductor substrate101, the p-type columns104may reach the n+-type semiconductor substrate101.

Further, the SJ-MOSFET150has a parallel structure (hereinafter, parallel pn region120) in which in the n-type layer102, p-type regions (the p-type columns104) and n-type regions (portions of the n-type layer102each sandwiched by the p-type columns104adjacent to each other, hereinafter, n-type column regions103) are disposed to repeatedly alternate each other in a plane parallel to a substrate main surface, the p-type columns104and the n-type column regions103extending in a direction orthogonal to a substrate main surface and having a narrow width in a plane parallel to the substrate main surface. The p-type columns104and the n-type column regions103configuring the parallel pn region120are regions having impurity concentrations that are increased corresponding to the n-type layer102. In the parallel pn region120, impurity concentrations included in the p-type columns104and the n-type column regions103are set to be substantially equal, whereby during an OFF state, from PN junctions between the p-type columns104and the n-type column regions103configured according to a cell pitch, a depletion layer spreads in the p-type columns104and the n-type column regions103along a horizontal direction (direction along which the p-type columns104and the n-type column regions103are disposed to repeatedly alternate one other). The cell pitch is an interval between adjacent gate electrodes. As a result, the depletion layer is easily connected in the horizontal direction, enabling high breakdown voltage to be achieved. Therefore, even when the impurity concentration of the n-type column regions103is increased, it becomes possible to reduce ON resistance without the breakdown voltage decreasing.

On a portion of the parallel pn region120in an active region130of the SJ-MOSFET150, the active region130in which an element is formed and through which current flows during an ON state, a p-type base region105is provided. In the p-type base region105, n+-type source regions106are provided. The n+-type source regions106are provided in the active region130and are disposed in a trench gate structure described hereinafter.

Further, trenches118that penetrate the p-type base region105and the n+-type source regions106, and reach the n-type column regions103are provided. The n+-type source regions106are disposed so as to be in contact with side surfaces of the trenches118.

Inner wall surfaces of the trenches118are covered by a gate insulating film107formed by an oxide film, etc. and the trenches118are embedded respectively with gate electrodes108that are formed on a surface of the gate insulating film107. In this manner, the trench gate structure is configured. A portion of each of the gate electrodes108may be provided with gate wiring115that protrudes from a top (side where a source electrode10described hereinafter is provided) of the trenches118toward the source electrode110.

Further, on surfaces of the p-type base region105and the n+-type source regions106and surfaces of the gate electrodes108, the source electrode110is provided via an interlayer insulating film109. The source electrode110is electrically insulated on the interlayer insulating film109. Through contact holes formed in the interlayer insulating film109, the source electrode110is electrically in contact with the p-type base region105and the n+-type source regions106. At a perimeter of the source electrode110, gate metal wiring114is provided so as to surround the source electrode110. The gate metal wiring114is embedded in an opening116provided in the interlayer insulating film109above the gate wiring115and is electrically connected to the gate electrodes108via the gate wiring115.

Further, on a back surface side of the n+-type semiconductor substrate101, a drain electrode (not depicted) that is electrically connected to the n+-type semiconductor substrate101is formed. By such a structure, a MOSFET having an enhancement-type trench gate structure of an n-channel type is formed.

In an edge termination region140the SJ-MOSFET150, the edge termination region140surrounding a periphery of the active region130, the parallel pn region120is provided in the n-type layer102, similarly to the active region130, and on a back surface of the n+-type semiconductor substrate101, the drain electrode (not depicted) is provided. The edge termination region140is formed by a breakdown voltage sustaining region144that mitigates electric field on a semiconductor-base-front-side of a drift region and sustains breakdown voltage and a border region143that is between the breakdown voltage sustaining region144and the active region130. Further, in the breakdown voltage sustaining region144, from a portion beneath the gate wiring115and spanning to an outer periphery of the breakdown voltage sustaining region144, for example, a thick insulating film117such as a LOCOS film may be provided. In a length direction of the p-type columns104, spanning the breakdown voltage sustaining region144from the border region143, a p-type region125deeper (longer) than the p-type base region105is provided.

For example, as a superjunction semiconductor device, a commonly known semiconductor device includes first semiconductor regions each having lower portions facing each other across a second semiconductor region and in contact with a main surface of a first semiconductor layer, and a third semiconductor region provided between the adjacent first semiconductor regions and having a lower portion that forms a pn junction with the second semiconductor region (for example, refer to Japanese Laid-Open Patent Publication No. 2008-210899).

SUMMARY OF THE INVENTION

According to an embodiment, a superjunction semiconductor device has an active region through which current passes, and an edge termination structure region disposed at an outer side of the active region and in which a voltage withstanding structure that surrounds a periphery of the active region is formed. The superjunction semiconductor device includes a semiconductor substrate of a first conductivity type, having a front surface and a back surface opposite to the front surface, a first semiconductor layer of the first conductivity type, provided on the front surface of the semiconductor substrate and having an impurity concentration that is lower than an impurity concentration of the semiconductor substrate, a parallel pn structure provided on a surface of the first semiconductor layer and including a plurality of first columns of the first conductivity type and a plurality of second columns of a second conductivity type, the first columns and the second columns being disposed to repeatedly alternate with one another on a plane parallel to the front surface, a first semiconductor region of the second conductivity type, provided on a surface of the parallel pn structure in the active region, a second semiconductor region of the first conductivity type, selectively provided in a surface layer of the first semiconductor region in the active region, a gate insulating film having a first surface in contact with the first semiconductor region and a second surface opposite to the first surface, and a gate electrode provided on the second surface of the gate insulating film. The plurality of second columns in the active region includes at least one first region each having a bottom surface and at least one second region each having a bottom surface, a first distance from the front surface of the semiconductor substrate to the bottom surface of one of the at least one first region is greater than a second distance from the front surface of the semiconductor substrate to the bottom surface of one of the at least one second region.

In the embodiment, the superjunction semiconductor device further includes a trench penetrating the first semiconductor region and the second semiconductor region, and reaching a corresponding one of the at least one first column. The gate electrode is provided on the gate insulating film in the trench.

In the embodiment, the at least one first region includes a plurality of first regions that are disposed in alignment, with a constant interval between adjacent first regions among the plurality of first regions.

In the embodiment, the superjunction semiconductor device further includes a current detecting region having the first semiconductor layer, the parallel pn structure, the first semiconductor region, the second semiconductor region, the gate insulating film, and the gate electrode. The plurality of second columns of the current detecting region includes a third region having a bottom surface and a fourth region having a bottom surface, a third distance from the front surface of the semiconductor substrate to the bottom surface of the third region is greater than a fourth distance from the front surface of the semiconductor substrate to the bottom surface of the fourth region.

In the embodiment, a volume of the plurality of second columns in the active region is at least 90% of a volume of the plurality of first columns in the active region.

According to another embodiment, a method of manufacturing a superjunction semiconductor device having an active region through which current passes, and an edge termination structure region disposed at an outer side of the active region and in which a voltage withstanding structure that surrounds a periphery of the active region is formed, the method includes forming a first semiconductor layer of a first conductivity type on a front surface of a semiconductor substrate of the first conductivity type, the first semiconductor layer having an impurity concentration lower than an impurity concentration of the semiconductor substrate; forming a parallel pn structure on a surface of the first semiconductor layer, the parallel pn structure including a plurality of first columns of the first conductivity type and a plurality of second columns of a second conductivity type, the first columns and the second columns being disposed to repeatedly alternate with one another on a plane parallel to the front surface; forming a first semiconductor region of the second conductivity type, on a surface of the parallel pn structure in the active region; selectively forming a second semiconductor region of the first conductivity type, in a surface layer of the first semiconductor region in the active region; forming a gate insulating film having a first surface in contact with the first semiconductor region and a second surface opposite to the first surface; and forming a gate electrode on the second surface of the gate insulating film. The plurality of second columns in the active region is formed to include a first region having a bottom surface and a second region having a bottom surface, and a first distance from the front surface of the semiconductor substrate to the bottom surface of the first region is greater than a second distance from the front surface of the semiconductor substrate to the bottom surface of the second region.

According to another embodiment, a method of manufacturing a superjunction semiconductor device having an active region through which current passes, and an edge termination structure region disposed at an outer side of the active region and in which a voltage withstanding structure that surrounds a periphery of the active region is formed, the method includes forming a first semiconductor layer of a first conductivity type on a front surface of a semiconductor substrate of the first conductivity type, the first semiconductor layer having an impurity concentration lower than an impurity concentration of the semiconductor substrate; forming a parallel pn structure on a surface of the first semiconductor layer, the parallel pn structure including a plurality of first columns of the first conductivity type and a plurality of second columns of a second conductivity type, the first columns and the second columns being disposed to repeatedly alternate with one another on a plane parallel to the front surface; forming a plurality of trenches from an upper surface of the parallel pn structure in the active region, in a direction toward the semiconductor substrate to selectively reach the plurality of first columns; forming a gate insulating film along a contour of each of the plurality of trenches; forming a plurality of gate electrodes on a surface of the gate insulating film; forming a first semiconductor region of the second conductivity type, on a surface of the parallel pn structure in the active region, the first semiconductor region having a surface layer on a first side thereof opposite a second side thereof facing the semiconductor substrate; and selectively forming a plurality of second semiconductor regions of the first conductivity type, in the surface layer of the first semiconductor region so that each is in contact with a corresponding trench of the plurality of trenches. The plurality of second columns in the active region is formed to include a first region having a bottom surface and a second region having a bottom surface, and a first distance from the front surface of the semiconductor substrate to the bottom surface of the first region is greater than a second distance from the front surface of the semiconductor substrate to the bottom surface of the second region.

Objects, features, and advantages of the present invention are specifically set forth in or will become apparent from the following detailed description of the invention when read in conjunction with the accompanying drawings.

