CLAIM OF PRIORITY

This Application is a National Stage Entry of, and claims priority to, PCT Application No. PCT/US16/54381, filed on Sep. 29, 2016 and titled “METHODS OF UTILIZING LOW TEMPERATURE SOLDER ASSISTED MOUNTING TECHNIQUES FOR PACKAGE STRUCTURES”, which is incorporated by reference in its entirety for all purposes.

BACKGROUND OF THE INVENTION

Warpage in microelectronic package structures, especially in thin microelectronic packages, can be a fabrication challenge for semiconductor manufacturers. Differences in coefficients of thermal expansion (CTE) between various materials in the microelectronic package structures, such as differences between substrates and microelectronic die, for example, may contribute to such warpage, especially when the packaged die/device undergoes temperature cycling.

