CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2020-0070400, filed on Jun. 10, 2020, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Embodiments of the disclosure may generally relate to an electronic device which corrects an error included in data and checks an error included in data.

2. Related Art

In order to increase the operating speed of a semiconductor device, a scheme of inputting/outputting a plurality of data in each clock cycle is used. In the case where an input/output speed of data is increased, the probability of an error occurring during a data transmission process also increases. Therefore, a separate device and method for ensuring the reliability of data transmission are additionally used.

There is used a method of generating error codes capable of checking the occurrence of an error and transmitting the error codes together with data, at each time of transmitting data, thereby ensuring the reliability of data transmission. The error codes include a cyclic redundancy check (CRC) code and an error detection code (EDC) capable of detecting an error that has occurred and an error correction code (ECC) capable of self-correcting an error when it has occurred.

SUMMARY

Various embodiments are directed to an electronic device which compensates for a difference in delay amounts and a difference in time between error check signals including error information on data inputted and outputted to and from memory regions located at different locations, and sums and outputs the error check signals between which the difference in delay amounts and the difference in time are compensated for.

In an embodiment, an electronic device may include: a replica delay circuit configured to generate a delayed error check signal by delaying a first error check signal including error information of first data stored in a first memory region; and an error sum signal generation circuit configured to generate an error sum signal by summing a second error check signal including error information of second data stored in a second memory region and the delayed error check signal.

In an embodiment, an electronic device may include: a first error correction circuit configured to generate a first error check signal which is enabled in the case where an error occurs in first data stored in a first memory region, correct the error of the first data and store the error-corrected first data in the first memory region; a second error correction circuit configured to generate a second error check signal which is enabled in the case where an error occurs in second data stored in a second memory region, correct the error of the second data and store the error-corrected second data in the second memory region; a replica delay circuit configured to generate a delayed error check signal by delaying the first error check signal; and an error sum signal generation circuit configured to generate an error sum signal by summing the second error check signal and the delayed error check signal.

In an embodiment, an electronic device may include: a controller configured to output a clock and a command address, sequentially output first to fourth data, and receive an error sum signal; and a semiconductor module including first to fourth memory devices, the semiconductor module configured to output the error sum signal by compensating for differences in delay amount among first to fourth error check signals including error information for the first to fourth data in a write operation depending on the clock and the command address.

In an embodiment, an electronic device may include: a controller configured to output a clock and a command address, and receive first to fourth data and an error sum signal; and a semiconductor module including first to fourth memory devices, the semiconductor module configured to output the error sum signal by compensating for differences in delay amount among first to fourth error check signals including error information for the first to fourth data, stored therein, in a read operation depending on the clock and the command address.

According to the embodiments of the disclosure, an electronic device may compensate for a difference in delay amounts and a difference in time between error check signals including error information on data inputted and outputted to and from memory regions located at different locations, and may sum and output the error check signals between which the difference in delay amount and the difference in time are compensated for, thereby securing the reliability of an error check operation.

Also, according to the embodiments of the disclosure, an electronic device may compensate for a difference in delay amounts and a difference in time between error check signals generated in a plurality of memory devices included in a semiconductor module, and may sum and output, to a controller, the error check signals between which the difference in delay amount and the difference in time are compensated for, thereby allowing the controller to detect an error check operation.

