BACKGROUND

Field

This disclosure is generally related to testing of physical systems, such as digital Integrated Circuits (ICs). More specifically, this disclosure is related to a system and method for generating testing vectors that facilitate efficient testing of the physical systems.

Related Art

Digital Integrated Circuits (ICs) are ubiquitously present in people's life, from washing machines to spaceships. Advances in the lithography technologies have enabled the feature size of the circuits to decrease continuously, thus facilitating the development of high-density ICs. However, as the feature size decreases, defects (e.g., due to impurities in the substrate, misalignments of masks, trembling during exposure, etc.) in ICs become more common and can lead to the malfunction of the circuits. Testing of the ICs is an important step to ensure the quality of the final product comprising the ICs. The increasing complexity of the ICs also increases the cost for testing. It is estimated that testing cost can be up to 40% of the total production cost of modern digital ICs.

SUMMARY

One embodiment provides a method and a system for generating test vectors for testing a computational system. During operation, the system obtains a design of the computational system, the design comprising an original system. The system generates a design of a fault-augmented system block by adding a plurality of fault-emulating subsystems to the original system; generates a design of an equivalence-checking system based on the original system and the fault-augmented system block; encodes the design of the equivalence-checking system into a logic formula, with variables within the logic formula comprising inputs and outputs of the original system and inputs and outputs of the fault-augmented system block; and solves the logic formula to obtain a test vector used for testing at least one fault in the computational system.

In a variation on this embodiment, the design of the equivalence-checking system comprises the original system and one or more fault-augmented system blocks, and generating the design of the equivalence-checking system comprises: coupling the inputs of the original system to corresponding inputs of each fault-augmented system block and coupling the outputs of the original system and corresponding outputs of each fault-augmented system block to a comparison module.

In a further variation, the fault-augmented system block comprises a set of fault-assumable inputs. A respective fault-assumable input corresponds to a fault-emulating subsystem. Generating the design of the equivalence-checking system further comprises coupling the set of fault-assumable inputs to a first constraint system.

In a further variation, the first constraint system is configured to apply a constraint on the set of fault-assumable inputs to ensure that the fault-augmented system block simulates one fault.

In a further variation, generating the design of the equivalence-checking system further comprises coupling the fault-assumable inputs in the one or more fault-augmented system block to a second constraint system. The second constraint system is configured to apply a constraint to ensure that different fault-augmented system blocks have different sets of fault-assumable inputs.

In a further variation, generating the design of the equivalence-checking system comprises adding one fault-augmented system block at a time until there is no satisfying solution to the logic formula.

In a further variation, the system generates a design of an extended system, which includes the equivalence-checking system and at least one copy of the equivalence-checking system, and solves a logic formula corresponding to the design of the extended system. Generating the design of the extended system comprises coupling corresponding fault-assumable inputs from different fault-augmented system blocks of each of the equivalence-checking systems to a third constraint system configured to apply a constraint to ensure that an arbitrary fault is simulated by at least one fault-augmented system block.

In a further variation, generating the design of the extended system comprises adding one copy of the equivalence-checking system at a time until a satisfying solution to the logic formula corresponding to the design of the extended system is found.

In a further variation, the satisfying solution to the logic formula corresponding to the design of the extended system comprises a plurality of sets of assignments to the inputs of the original systems included in the extended system. A respective set of assignments form a test vector, and test vectors corresponding to the plurality of sets of assignments form a test suite capable of testing any arbitrary fault in the computational system.

In a variation on this embodiment, the computational system comprises one or more of: a digital circuit; an analog circuit; a quantum circuit; a reversible computing circuit; an optical circuit; a quantum optical circuit; a processor; and a computer program.

