TECHNICAL FIELD

The present disclosure relates to the field of chip-to-chip signaling; signaling between integrated circuit devices.

BACKGROUND

In strobe-timed signaling systems, “active” strobe edges that mark data sampling instants are preceded and succeeded by characteristic strobe preamble and postamble waveforms having idle-to-ready transitions and vice-versa—overhead transitions that are gated-out of the timing signal supplied to trigger signaling sampling operations within link receivers. The interval between preamble transition and the first active strobe edge (and/or final active strobe edge and postamble transition) may be as brief as a bit-time, allowing scant margin of error within the receiver-generated gating signal used to suppress overhead (non-active) strobe edges. In the face of ever-present demand for increased signaling bandwidth, gating signal timing margins are approaching limits imposed by chip-to-chip timing drift, reference clock jitter and other timing skew sources, threatening to impede further bit time reduction/bandwidth gain.

