BACKGROUND

The present invention relates to semiconductor device fabrication, and more specifically, to stacked FET gates.

Stacked nanosheet designs provide a significant gain for both logic and memory device structural scaling by stacking FETs above one another. The stacked nanosheet device allows for 2 n-FETs, 2 p-FETs, or a combination of n-FET and p-FET devices located in the same footprint of a nanosheet.

BRIEF SUMMARY

An embodiment of the invention may include a semiconductor structure and method of manufacturing. The semiconductor structure may include a top channel and a bottom channel, wherein the top channel includes a plurality of vertically oriented channels. The bottom channel includes a plurality of horizontally oriented channels. The semiconductor structure may include a gate surrounding the top channel and the bottom channel. The semiconductor structure may include spacers located on each side of the gate. A first spacer includes a dielectric material located between the plurality of vertically oriented channels. A second spacer includes a dielectric material located between the plurality of horizontally oriented channels. This may enable spacer formation between the vertical spacers.

In another embodiment the semiconductor structure may have a thickness of the first spacer is different from a thickness of the second spacer.

In another embodiment the semiconductor structure may include the second spacer further includes a top element, and wherein the top element includes a dielectric material in contact with a bottom surface of the top channel and a top surface of the bottom channel.

In another embodiment the semiconductor structure may include a structural interface exists between the first spacer and the second spacer.

In another embodiment the semiconductor structure may include the top element has a top portion and a bottom portion, wherein the top portion includes a plurality of fin protrusions, wherein each fin protrusion is located beneath each of the plurality of vertically oriented channels, and wherein the bottom portion includes a horizontal layer connecting each of the fin protrusions of the top portion. This may enable spacer formation between the top channel and bottom channel.

In another embodiment the semiconductor structure may include the top channel is part of a first transistor, and wherein the bottom channel is part of a second transistor. This may enable the semiconductor device to act as a stacked gate structure.

In another embodiment the semiconductor structure may include the first transistor and the second transistor form a complimentary field effect transistor. This may enable the semiconductor device to act as a stacked gate structure.

An embodiment of the invention may include a semiconductor structure and method of manufacturing. The semiconductor structure may include a gate structure. The semiconductor structure may include a top channel. The top channel includes at least one vertically oriented channel. A bottom surface of the at least one vertically oriented channel is in contact with an insulator layer. A top surface and vertical surfaces of the at least one vertically oriented channel are in contact with the gate structure. The semiconductor structure may include a bottom channel, wherein the bottom channel includes a plurality of horizontally oriented channels, and wherein the gate surrounds the bottom channel. This may provide structural support to the top channel.

In another embodiment the semiconductor structure may include a dielectric of the gate is located on each surface of the bottom channel, and the dielectric of the gate is located on the top surface and the vertical surfaces of the at least one vertically oriented channel are in contact with the gate structure, and wherein the gate dielectric is located on surfaces of the insulator layer that are not in contact with the at least one vertically oriented channel.

In another embodiment the semiconductor structure may include the top channel is part of a first transistor, and wherein the bottom channel is part of a second transistor. This may enable the semiconductor device to act as a stacked gate structure.

In another embodiment the semiconductor structure may include the first transistor and the second transistor form a complimentary field effect transistor. This may enable the semiconductor device to act as a stacked gate structure.

