The disclosure relates to maintaining integrity of content stored on integrated circuits.

BACKGROUND FOR THIS DISCLOSURE

Verification of an integrated circuit's memory content, aka memory protection, error detection, or error correction, is recognized as an important objective. Therefore, an integrated circuit may include a memory array and on-the-fly memory error detection/correction functionality e.g. parity or error correction code (ECC) circuitry. However ECC is very costly for large memories, and it is not as strong as cryptographic memory verification. Thus cryptographic memory verification is typically achieved using what may be termed as digest-redo-compare technology, implemented e.g. in firmware or dedicated hardware, in which memory content may be digested once to generate a reference. Then the digest is redone on occasion e.g. periodically, and each time a comparison is performed to verify that the new digest is the same as the reference digest. For example, memory space may be divided or partitioned into plural “chunks”. A processor then computes and stores a hash for each chunk, typically storing a secret key on-chip. When the processor reads a block from chunk C in memory, the processor may read or load the entire chunk C, re-compute the hash of the loaded chunk, and compare the newly recomputed hash with the hash stored in memory for chunk C. If the comparison yields no difference, all is well, whereas if the newly recomputed hash differs from the stored hash, assuming that the physical and electrical integrity of the memory array is known to be intact, this indicates that the memory content has been tampered with.

Conventional register doubling/duplication, which is an existing register content verification method, is described in U.S. Pat. No. 8,146,028. Typically, given a register comprising plural flip-flops combined in parallel, this is believed to include doubling of a register's flip-flops to yield plural flip-flops, maintaining all of the plural flip-flops, and, on occasion, or periodically, e.g. continuously, comparing the values between the plural flip-flops, to detect mismatches between duplicated instances which, if detected, are indicative of tampering. Typically, when doubling is implemented, there is no dependency or interlink between registers since each register has its own shadow and comparison logic.

Integrity checks of logical elements (but not of content thereof), which may be used in conjunction with any embodiments shown and described herein, are described in U.S. Pat. No. 8,341,473 to Bertacco. Bertacco https://patents.google.com/patent/U.S. Pat. No. 8,341,473B2/en, describes a method by which “register file integrity may be checked using a four phase split-transaction test procedure”.

SUMMARY OF CERTAIN EMBODIMENTS

Improving the security of integrated circuits is a constant concern in the integrated circuit industry. One way to improve security, is to better secure the contents of registers on the integrated circuit. Securing the contents of registers typically assures that, other than intentional modifications, register contents remain intact throughout the period of normal operation of the device in which the registers reside.

Certain embodiments seek to provide a system or method configured for maintaining integrity of configuration and/or control settings of integrated circuits.

Certain embodiments seek to provide a system or method configured for checking integrity of content of at least one register aboard an integrated circuit.

Verification of an integrated circuit's register content, as an objective, has—to put it kindly—received considerably less emphasis in the literature, than has verification of an integrated circuit's memory content, which is a very well recognized objective. When register content verification is discussed at all, it is typically achieved by doubling e.g. Duplicating. A few registers (from among thousands that may be provided on modern integrated circuits, and the number is growing) may be deemed to need content verification, and dedicated protection hardware may then be implemented for those registers accordingly.

Certain embodiments herein seek to provide broad protection (content verification) for large numbers of registers e.g. for all of the thousands of registers that may be provided on modern integrated circuits.

Certain embodiments herein seek to provide digest-based register-content integrity verification which is more efficient in terms of die area (requires less die area) when a few thousand registers or more are present on an integrated circuit.

Certain embodiments seek to provide hardware which performs integrity checks for contents of an integrated circuit's registers (e.g. register file/s), in a manner which is transparent to, or does not disrupt, the regular functionality of the integrated circuit. Hashes may be computed for IC memory content verification, using logic implemented in HW, SW or FW, typically depending on a designer's choice of the easiest option or the option least costly in terms of hardware. Computation of hashes may be performed similarly or identically when verifying memory content and when verifying register content, however, typically, memory cannot be used or accessed while a hash thereof is being computed, whereas registers values may be obtained without causing any interruptions.

The following terms may be construed either in accordance with any definition thereof appearing in the prior art literature or in accordance with the specification, or to include in their respective scopes, the following:

Register file: typically is intended to include a set of multiple registers aboard a single integrated circuit. Conventional register files are described in Wikipedia's entry on “register file”. According to an embodiment, an integrated circuit includes one or more register files, and one digest is computed for all registers in a given register file, or set of register files. According to an embodiment, an integrated circuit includes one or more register banks, and one digest is computed for all registers in a given register bank, or set of register banks. However, it is appreciated that the Register file referred to inFIG. 1and elsewhere herein is intended to include at least one file or more generally, any multiplicity of registers aboard a single integrated circuit e.g. a “register bank” which includes plural register files, or any other group of registers.

Auth: intended to include a digest.

“digest” aka “digest function”: computational algorithm or logic that maps data of arbitrary size to a bit string of a fixed size; this bit string which is an output of a digest function is sometimes termed “the digest”. The term digest as used herein includes cryptographic digests in which the data is mapped by a crypto function such as a cryptographic hash function. However, not all digests are cryptographic, and, more generally, any suitable digest may be employed, depending e.g. on the strength preferred by the designers of the IC. For example, a digest may comprise a checksum digest, in which case the data is typically mapped by a fixed-size sum.

snapshot: hash of current content of an integrated circuit's register/s, which is stored aboard the integrated circuit. Typically, the hashes stored as snapshots are not timestamped, since it is typically sufficient to know only that the stored hash is the most recent. There can be one or more currently valid snapshots, e.g. depending on whether one full digest is stored, or whether several partial digests are stored as per the stepwise embodiment described herein.

There are thus provided at least the following embodiments:

Embodiment 1. A system for verifying integrity of content of an integrated circuit's registers, the system typically operative in conjunction with an integrated circuit including at least one memory and/or at least one processor and/or a multiplicity of registers, the system comprising: register content verification logic configured, e.g. when or only when in a first mode aka “Study Mode”, to read at least some of the registers' content and/or to compute a first auth or digest e.g. hash on the content, and/or to store the first hash thereby to provide an up-to-date reference hash, and, at least on occasion, when in or only when in a second mode aka “Verify Mode”, to compute at least one second auth or digest e.g. hash on the content and/or to compare the second hash to the reference hash and, accordingly, to provide a content verification output (aka “fault detection” output) typically indicative of whether the reference and second hashes are equal.

Typically, a fault is detected when the two hashes are not equal.

The content verification output (aka “fault detection” output) (e.g. as shown inFIG. 1) typically comprises an indication that the two hashes are not equal and may be received by hardware which may, responsively, perform certain action/s. And/or, the “fault detection” output may comprise a flag/interrupt raised to firmware which may, responsively, trigger (or give a command to perform) certain action/s. Any suitable action/s may be performed, by hardware and/or by firmware, responsive to the “fault detection” output, such as but not limited to reset and restart, halt until power is cycled, halt forever.

A particular advantage of register content verification as described herein is that registers as opposed to memory are always available for obtaining their values (in order to digest and compare them). The interface to the register does not need to be “owned”, or taken over, in order to discern the register's content for digest/compare purposes. In contrast, when conventionally verifying memory content, the memory's normal operation is disrupted as the memory is arbitrated to or taken over for the memory content verification, verified and then released, and once the memory is taken over, the memory becomes unusable for any other operation, until release.

Another particular advantage of embodiments herein is in overcoming the problem that doubling, as is known in the art, was mainly practical for register content verification which only sought to protect a small number of registers. This modest objective could have been either because only a subset of the registers on board the integrated circuit was, rightly or wrongly, regarded as needing protection and/or because only a small number of registers were present on the integrated circuit in the first place—as was the case for earlier integrated circuits but increasingly is no longer the case. Thus, for whatever reason, the overhead generated by use of doubling for register content verification was, historically, not large. Currently, it is believed that many or most integrated circuits would benefit from protection of thousands of registers, but providing this protection by using conventional doubling would cause large overhead even today, and this overhead may be expected to become larger, as integrated circuits are designed to include more and more registers. Thus, while doubling may have been efficient enough when each integrated circuit included only a few registers, this is becoming less and less satisfactory the more registers each integrated circuit is designed to have, and indeed the number of registers per chip keeps growing. Embodiments shown and described herein provide a greater degree of efficiency.

It is appreciated that embodiments herein add less cells than doubling, assuming that a relatively large number of flip-flops are present, in practice.

It is appreciated that as soon as an integrated circuit has a certain number of registers, the system herein becomes cost effective: implementing digest and verification logic on that integrated circuit becomes justified (becomes more efficient than using doubling) because once that certain number of registers is exceeded, digesting becomes more efficient than doubling e.g. because doubling requires logic to compare each pair, to ensure each pair is identical; this logic is not needed/is obviated in the digest and verification logic described herein.

The number of registers which renders the system cost effective is present even in today's integrated circuits, not to speak of the fact that the number of registers per integrated circuit has been tending to increase over the years.

Typically, the first hash and the second hash each comprise a single hash from the following group: MD5, SHA-1, SHA-2, NTLM, and LANMAN.MD. Typically, the first and second hash must be computed using the same algorithm, otherwise there will be no meaning to comparing the first and second hashes (no basis for comparison).

Embodiment 2. The system of any of the preceding embodiments wherein if a legitimate modification of register content (aka register value modification) occurs while the logic is in the Study Mode, operation of the Study Mode is arrested and is re-started when the modification is over, including replacing any reference hash previously stored with a newly computed first hash.

Any register write (e.g. to a “surveilled register”) may be considered a legitimate register modification—which then facilitates detection or prevention of hardware tampering by embodiments herein—whereas malicious firmware writing a register may not be detectable if the write is considered legit.

Any suitable method may be employed by the logic herein, to determine when a legitimate register modification is over, at which point in time the logic may switch modes and compute a new hash/digest. For example, a register write typically requires a known maximum number of IC clock cycles, c. Thus, the logic may count c clocks and then the logic may safely (assume that the register now holds the new value and) compute a new hash/digest.

Embodiment 3. The system of any of the preceding embodiments wherein if a legitimate modification of register content occurs while the logic is not in the Study Mode, the logic activates the Study Mode after the modification is over and before activating the Verify Mode.

Embodiment 4. The system of any of the preceding embodiments wherein if a legitimate modification of register content occurs while the logic is in the Verify Mode, operation of the Verify Mode is arrested, and when the modification is over, the logic reverts to Study Mode before returning to Verify Mode.

Embodiment 5. A method for checking integrity of contents of at least one register, the method comprising: at least once, performing a cycle including the following operations: digesting the contents of (aka values in) at least one register, thereby to generate a digest; and verifying integrity of the contents by comparing the digest to a reference.

Embodiment 6. The system of any of the preceding embodiments wherein when the logic is in the Verify Mode, registers are continuously hashed and compared, thereby to provide frequent content verification outputs, yielding a high degree of security.

Embodiment 7. The system of any of the preceding embodiments wherein each time the reference and second hashes are not equal, the content verification output causes at least one action to be performed by being received by at least one of:

firmware which, responsively, triggers the action; and

hardware which performs the action.

Embodiment 8. The system of any of the preceding embodiments wherein the action comprises resetting a device incorporating the integrated circuit.

Embodiment 9. The system of any of the preceding embodiments wherein if the reference and second hashes are not equal, the content verification output may comprise a flag/interrupt raised to firmware which is operative to warn higher levels of software that the system incorporating the integrated circuit system may be under hacking attack.

Embodiment 10. The system of any of the preceding embodiments wherein the action comprises a complete hardware reset for all of the integrated circuit's hardware.

This command may be “hardware to hardware”. Typically, a signal in the hardware triggers a complete or partial/selective IC reset.

Embodiment 11. The system of any of the preceding embodiments wherein the action comprises a system reset, e.g. re-init.

Embodiment 12. The system of any of the preceding embodiments wherein the action comprises halting a device incorporating the integrated circuit until the device has been powered off and switched back on.

Alternatively or in addition to embodiments 7-12, the logic may trigger a suitable output message to a human engineer, recommending that the IC should be halted forever or retired. The logic may assert some output signal, or may respond to some access in a manner indicative of being in such a halt state.

Embodiment 13. The method of any of the preceding embodiments wherein the reference comprises a digest previously computed at a time t by digesting the contents present in the at least one register at time t.

Embodiment 14. The system of any of the preceding embodiments wherein each of the hashes is computed over a set of registers including plural registers.

Embodiment 15. The system of any of the preceding embodiments wherein the integrated circuit includes one or more register files, and wherein each of the hashes is computed over all registers in a given register file.

Embodiment 16. The system of any of the preceding embodiments wherein the integrated circuit includes one or more register banks, and wherein each of the hashes is computed over all registers in a given register bank.

Embodiment 17. The system of any of the preceding embodiments and also comprising an integrated circuit including a multiplicity of registers; and wherein the register content verification logic is deployed aboard the integrated circuit.

Embodiment 18. The method of any of the preceding embodiments wherein the at least one register comprises at least one register file.

Embodiment 19. The method of any of the preceding embodiments wherein the digest comprises a hash.

Embodiment 20. The system of any of the preceding embodiments wherein the integrated circuit includes a processor having a first entry point including a first command to be executed after reset, and wherein, if the reference and second hashes are not equal, the content verification output triggers a hardware reset signal which causes the processor to revert to the first entry point.

Embodiment 21. The system of any of the preceding embodiments wherein the logic is implemented in hardware residing on the integrated circuit.

Embodiments referred to above, and other embodiments, are described in detail in the next section.

Any trademark occurring in the text or drawings is the property of its owner and occurs herein merely to explain or illustrate one example of how an embodiment of the invention may be implemented.

Unless specifically stated otherwise, as apparent from the following discussions, it is appreciated that throughout the specification discussions, utilizing terms such as, “processing”, “computing”, “estimating”, “selecting”, “ranking”, “grading”, “calculating”, “determining”, “generating”, “reassessing”, “classifying”, “generating”, “producing”, “stereo-matching”, “registering”, “detecting”, “associating”, “superimposing”, “obtaining” or the like, refer to the action and/or processes of at least one computer/s or computing system/s, or processor/s or similar electronic computing device/s, that manipulate and/or transform data represented as physical, such as electronic, quantities within the computing system's registers and/or memories, into other data similarly represented as physical quantities within the computing system's memories, registers or other such information storage, transmission or display devices. The term “computer” should be broadly construed to cover any kind of electronic device with data processing capabilities, including, by way of non-limiting example, personal computers, servers, embedded cores, computing systems, communication devices, processors (e.g. digital signal processor (DSP), microcontrollers, field programmable gate array (FPGA), application specific integrated circuit (ASIC), etc.) and other electronic computing devices.

Elements separately listed herein need not be distinct components and alternatively may be the same structure. A statement that an element or feature may exist is intended to include (a) embodiments in which the element or feature exists; (b) embodiments in which the element or feature does not exist; and (c) embodiments in which the element or feature exist selectably e.g. a user may configure or select whether the element or feature does or does not exist.

