FIELD OF THE INVENTION

This invention relates to neural networks, and more particularly, to systems and methods for implementing resistive memories in an analog neuromorphic circuit.

BACKGROUND OF THE INVENTION

Traditional computing systems use conventional microprocessor technology in that operations are performed in chronological order such that each operation is completed before the subsequent operation is initiated. The operations are not performed simultaneously. For example, an addition operation is completed before the subsequent multiplication operation is initiated. The chronological order of operation execution limits the performance of conventional microprocessor technology. Conventional microprocessor design is limited in how small the microprocessors can be designed, the amount of power that the microprocessors consume, as well as the speed in which the microprocessors execute operations in chronological order. Thus, conventional microprocessor technology is proving insufficient in applications that require significant computational efficiency, such as in image recognition.

It is becoming common wisdom to use conventional neuromorphic computing networks which are laid out in a similar fashion as the human brain. Hubs of computing power are designed to function as a neuron in the human brain where different layers of neurons are coupled to other layers of neurons. This coupling of neurons enables the neuromorphic computing network to execute multiple operations simultaneously. Therefore, the neuromorphic computing network has exponentially more computational efficiency than traditional computing systems.

Conventional neuromorphic computing networks are implemented in large scale computer clusters which include computers that are physically large in order to attain the computational efficiency necessary to execute applications such as image recognition. For example, applications of these large scale computer clusters include rows and rows of physically large servers that may attain the computational efficiency necessary to execute image recognition when coupled together to form a conventional neuromorphic computing network. Such large scale computer clusters not only take up a significant amount of physical space but also require significant amounts of power to operate.

The significant amount of physical space and power required to operate conventional neuromorphic computing networks severely limits the types of applications for which conventional neuromorphic computing networks may be implemented. For example, industries such as biomedical, military, robotics, and mobile devices are industries that cannot implement conventional neuromorphic computing networks due to the significant space limitations in such industries as well as the power limitations. Therefore, an effective means to decrease the space and the power required by conventional neuromorphic computing is needed.

SUMMARY OF THE INVENTION

The present invention provides an analog neuromorphic circuit that implements a plurality of resistive memories, including a plurality of input voltages, and at least one output signal. The plurality of input voltages is applied to a plurality of inputs of the analog neuromorphic circuit. The plurality of resistive memories is configured to provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. At least one output signal is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. Multiplying each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.

The present invention also provides a method for generating computer operations in parallel by implementing a plurality of resistive memories. The method starts with applying a plurality of input voltages to a plurality of inputs of an analog neuromorphic circuit. The method further includes providing, by a plurality of resistive memories, a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The method further includes generating at least one output signal from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. Multiplying each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.

The present invention also provides an analog neuromorphic system that implements a plurality of resistive memories, including a first plurality of wires, and a second plurality of wires. The first plurality of wires is positioned to intersect with a second plurality of wires forming a first wire grid. Each resistive memory is positioned at an intersection of the first plurality of wires and the second plurality of wires. The plurality of resistive memories is configured to provide a resistance to each input voltage applied to each of the first plurality of wires so that each input voltage of the first wire grid is multiplied in parallel by the corresponding resistance to generate a corresponding current for each input voltage and each corresponding current is added in parallel. At least one output signal is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. Multiplying each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.

