BACKGROUND

The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. However, these advances have also increased complexity of manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.

For example, IC fabrication typically involves forming a device layer that includes various IC devices on a wafer (substrate) and then forming a multilayer interconnect (MLI) feature over the device layer that facilitates operation of the various IC devices. In some implementations, the MLI feature includes an interlayer dielectric (ILD) layer disposed over the device layer and intermetal dielectric (IMD) layers disposed over the ILD layer. The IMD layers include electrically conductive interconnect structures (for example, metal interconnect structures) that are configured to route and/or distribute signals between the IC devices and/or components of the IC devices. Since topography of the ILD layer conforms to topography of underlying layer(s), such as the device layer, any topography variation in the underlying layer(s) is often transferred to the ILD layer. For example, height variation among the IC devices that cause topography variation in the device layer (in other words, some regions of the device layer are “taller” or “shorter” than other regions) lead to the ILD layer exhibiting topography variation even after performing a planarization process (for example, a chemical mechanical polishing process). Such topography variation can lead to degraded IC device performance or even IC device failure. Accordingly, although existing IC fabrication methods have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects (for example, in adequately controlling ILD topography).

