CROSS REFERENCE TO RELATED APPLICATION

This is a National Phase Application filed under 35 U.S.C. 371 as a national stage of PCT/CN2019/108411, filed on Sep. 27, 2019, an application claiming the benefit of Chinese patent application No. 201811169550.0, filed on Oct. 8, 2018, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The embodiments of the present disclosure relate to, but are not limited to, the field of circuit boards, and particularly relate to, but are not limited to, a circuit board, an apparatus and a method for forming a via hole structure.

BACKGROUND

At present, as system capacity becomes larger and larger and signal rates become higher and higher, density in Printed Circuit Board (PCB) design is increased, and thicknesses and layers of PCBs are increased as well, resulting more and more requirements for signal integrity than before. A via hole is a structure inevitably used in high-speed and high-density design, and the performance of the via hole directly affects performance of a high-speed and high-density product. Impedance continuity is one of the important indexes for measuring performance of a via hole, and the impedance of a via hole is generally much smaller than characteristic impedance of a PCB transmission line connected to the via hole, which results in poor impedance continuity of a whole link and causes a signal integrity problem.

The impedance of a via hole is related to parasitic capacitance and parasitic inductance of the via hole. The greater the parasitic capacitance is, the smaller the impedance of the via hole is; and the greater the parasitic inductance is, the greater the impedance of the via hole is. In order to increase the impedance of the via hole, a method in existing art is to enlarge an anti-pad of the via hole through cutout to a certain extent. However, the size of the cutout cannot be unlimited in practical applications; otherwise, completeness of a reference plane of signals is affected, which may cause other signal integrity problems. Moreover, when the size of the cutout is increased to a certain extent, the effect of increasing the impedance of the via hole hits a bottleneck. Another method in the existing art is to decrease a diameter of the via hole. The smaller the diameter of the via hole is, the smaller the parasitic capacitance is, the greater the impedance of the via hole is, the better the impedance continuity of system link is.

However, with the increase of the system capacity, the PCBs become thicker and thicker. Since an aspect ratio (i.e., a ratio of thickness of a PCB to diameter of a via hole), which is one of the key indexes that affect the difficulty of PCB manufacturing, gets greater with the decrease of the diameter of the via hole, the manufacturing difficulty of design of small holes is larger, so that a yield rate of the PCBs is affected, which further affects cost and reliability of the products. The failure of the manufacturing of the PCBs caused by the large aspect ratio may even lead to the discarding of the PCBs. Therefore, how to effectively increase the impedance of a via hole is an urgent technical problem at present.

SUMMARY

The embodiments of the present disclosure provide a circuit board, an apparatus, and a method for forming a via hole structure, and mainly aim to at least solve the technical problem of how to improve the impedance of a via hole.

The embodiments of the present disclosure provide a circuit board, including a main body with a multi-layer structure and a via hole structure disposed therein. The via hole structure includes a hole enclosed by a conductive layer in the main body, and the conductive layer constitutes a wall of the hole; and the via hole structure further includes a dielectric filling layer, which is disposed between at least a portion of the wall and the main body, and has a dielectric constant smaller than that of the main body.

The embodiments of the present disclosure further provide an apparatus, including a main body and the above circuit board disposed thereon.

The embodiments of the present disclosure further provide a method for forming a via hole structure, including: forming a first hole in a main body of a circuit board with a multi-layer structure; filling the first hole with a dielectric having a dielectric constant smaller than that of the main body of the circuit board; forming a second hole, which penetrates the dielectric and has a diameter smaller than that of the first hole, in the region of the dielectric in the first hole, the dielectric having the second hole formed therein being a dielectric filling layer; and forming a conductive layer on a wall of the second hole to obtain a via hole structure, with a hole enclosed by the conductive layer which constitutes a wall of the hole.

The beneficial effects of the present disclosure are as follows.

According to the circuit board, the apparatus and the method for forming a via hole structure provided by the embodiments of the present disclosure, the via hole structure formed in the main body of the circuit board includes the hole enclosed by the conductive layer in the main body of the circuit board, the conductive layer constitutes the wall of the hole, and the dielectric filling layer, which has the dielectric constant smaller than that of the main body of the circuit board, is disposed between at least a portion of the wall of the hole and the main body of the circuit board, that is, a dielectric constant of the dielectric around the via hole can be made smaller than that of the main body of the circuit board in some implementations, so that the parasitic capacitance of the via hole is decreased, and the impedance of the via hole is increased to become closer to the impedance of a transmission line, thereby effectively improving the impedance continuity of system link.

Other features and corresponding beneficial effects of the present disclosure are described in the latter part of the specification, and it should be understood that at least part of the beneficial effects will become apparent from the description in the specification of the present disclosure.

