BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including semiconductor sheets.

2. Description of the Prior Art

The conventional planar metal-oxide-semiconductor (MOS) transistor has difficulty when scaling down in the development of the semiconductor device. Therefore, the stereoscopic transistor technology or the non-planar transistor technology that allows smaller size and higher performance is developed to replace the planar MOS transistor. For example, dual-gate fin field effect transistor (FinFET) device, tri-gate FinFET device, and omega-FinFET device have been provided. Furthermore, gate-all-around (GAA) nanowire FET device is progressed for achieving the ongoing goals of high performance, increased miniaturization of integrated circuit components, and greater packaging density of integrated circuits. However, under the concept of the GAA, how to further enhance device characteristics (such as electrical performance) through process and/or structural design is still the direction of continuous efforts by people in related fields.

SUMMARY OF THE INVENTION

It is one of the objectives of the present invention to provide a semiconductor device. A second doped layer is sandwiched between two first doped layers having a conductivity type different from that of the second doped layer for forming a semiconductor sheet, and the electrical performance of the semiconductor device may be enhanced accordingly.

A semiconductor device is provided in an embodiment of the present invention. The semiconductor device includes a substrate and a first transistor disposed on the substrate. The first transistor includes a plurality of first semiconductor sheets and two first source/drain structures. The first semiconductor sheets are stacked in a vertical direction and separated from one another. Each of the first semiconductor sheets includes two first doped layers and a second doped layer disposed between the two first doped layers in the vertical direction. A conductivity type of the second doped layer is complementary to a conductivity type of each of the two first doped layers. The two first source/drain structures are disposed at two opposite sides of each of the first semiconductor sheets in a horizontal direction respectively, and the two first source/drain structures are connected with the first semiconductor sheets.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

