STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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TECHNICAL FIELD

The present disclosure relates to the field of charged particle sources including plasma sources for direct etching and deposition, broad-beam ion sources for ion beam deposition and etching, and electron sources for surface modification.

BACKGROUND

FIG. 1illustrates an ion beam etch (IBE) system. In an IBE process, wafer180is placed in front of an ion source105. At least one surface of the wafer180can be exposed to a beam130. Ion source105can be comprised of a plasma chamber110, and an ion extraction grid system150. Ion extraction grid system150is comprised of a plurality of conducting plates that have multiple holes therein aligned from plate to plate. Grid system150extracts and helps collimate ion beamlets coming out of each of the holes of the plates, and forms a substantially collimated ion beam130. Plasma in the plasma source may be generated by methods known in the art including direct current (DC) and radio frequency (RF) inductively coupled plasma (ICP) coils160. The energy of the ions extracted from the ion source105is defined by the voltages applied to the grid system150.

An electron source230, may be placed between the ion extraction grid system150and a wafer stage to prevent charge damage from the impinging ions on the wafer. Wafer180, is placed on wafer stage140. The stage140can rotate the wafer about a central axis220. The stage140can tilt the wafer180with respect to the ion beam130for at least a portion of the etching process. Ions from the beam130can be directed at any angle with respect to the wafer surface by tilting the wafer180. Any solid material can be etched with an IBE process. Provisions may be made on the wafer stage140to cool the wafer180during the etching process to prevent thermal damage to the devices on the wafer180. Wafer180may also be heated to a specific temperature to enhance the ion beam etching process.

A typical wafer180can include many devices and may be covered with photoresist masks or other type of masks. The devices can be processed with ion beam exposure to etch the desired shape of the devices on the wafer180. The desired shape of the devices can be achieved by adjusting process parameters including, for example: wafer tilt angle during etch, duration of etch, beam energy, beam current, Photoresist mask sidewall angles, wafer temperature, etc. An end point detector240may be placed in line of sight of the wafer180when the devices are made of multilayer materials and precise end pointing of the etch at a predetermined layer is often desired.

The devices on wafer180being etched are expected to show similar shapes (e.g., sidewall profiles, etc.) However, devices can show different shapes depending on the location of the devices on the wafer180. One example of a specific type of shape difference is called inboard and outboard asymmetry.FIGS. 2a-2cshow a schematic representation of the asymmetry of the inboard (IB) side191of a device and the outboard (OB) side192of a device after ion beam etching. The asymmetry may be quantified as the sidewall angle differences on one side α versus the opposite side β.FIG. 2ashows symmetric etching.FIG. 2bandFIG. 2cshow asymmetric etching.

The asymmetry of the IB side191, and the OB side192of devices in ion beam etching often has a specific relationship to the tilting of the wafer180. This relationship is shown inFIGS. 3a-3b.FIG. 3ais a top view of a wafer180being etched. The tilt axis runs along the diagonal of the wafer as shown with respect to the wafer top view. InFIG. 3a, wafer180is being etched by an ion beam impinging on it from a direction perpendicular to the plane of the paper.FIG. 3bis a cross section view ofFIG. 3aalong the wafer diagonal perpendicular to the tilt axis. InFIG. 3b, the wafer cross-section, direction of tilt axis runs along the middle of the wafer, and perpendicular to the plane of the paper. Asymmetry between the IB side191of the device and the OB side192of the device can be seen on the devices located towards the top and bottom of the wafer180. The asymmetry becomes more pronounced the further away the device is from the tilt axis, and as the tilt angle is increased, e.g., the wafer180is tilted further from the normal angle of incidence of the incident beam.

In a perfect ion source, and grid system, all beamlets would be perfectly collimated, with no divergence of the ions from the intended direction. In such a system, all features etched on the wafer180would be perfectly symmetrical. Practical ion beam etch systems have non-zero beam divergence.

In practice, ion sources generate an ion beam that is a collection of beamlets with a finite non-zero beam divergence, as illustrated inFIG. 4. Beamlet divergence131is shown in this figure. A consequence of the beamlet divergence is that as the wafer is tilted away from normal beam incidence, there will be more intense etching on the side of the wafer180nearer to the ion source, and less intense etching on the side of the wafer180farther from the ion source. By rotating the wafer180about an axis220, the etch depths can be made more uniform in the areas of the wafer180that are feature free. Devices on the wafers180however are typically made of features in 3-dimensions and not flat surfaces. On 3-dimensional features on the wafer180, the effect of the tilting of the wafer180away from normal beam incidence, in conjunction with beam divergence, is that the inboard side191of the devices on the wafer180will experience a different amount of beam exposure than the outboard side192of the devices. This inboard and outboard asymmetry becomes more pronounced as the location of the devices is farther away from the tilt axis of the wafer180, and as the tilt angle is increased away from normal beam incidence.

Translating (e.g., scanning) the wafer180across the beam can address asymmetry between the inboard side191of the device and the outboard side192of the device. InFIG. 5, the region marked by double ended arrow550is the region where ion beam exposure of the wafer occurs. A single instance of translation of the wafer, translation starting at any point where all regions of the wafer is outside of the region shown by550, translation path taking the wafer through the region represented by550, is considered one scan. InFIG. 7, region550, where ion beam exposure occurs is defined through the introduction of physical beam blocks171, and172.

In some embodiments, the path of the wafer180during translation is defined as the scan path. The scan path can be within a plane that is parallel (or nearly parallel) to the plane of the tilted wafer surface for at least one scan. The scan path of wafer translation can be linear for at least one scan. The path of wafer translation can be non-linear (e.g., curved) for at least one scan. The scan path can be parallel to the tilted wafer180for at least one scan. The wafer tilt can be constant during the scan path for at least one scan. The wafer tilt can vary along the path of the scan for at least one scan. The scan path can be parallel to the wafer180during at least one point in the scan for at least one scan. The scan path can be parallel to the wafer180at all points during the scan for at least one scan. The scan path can be in a different plane than the wafer180for at least one scan. The scan path can be within a plane that is parallel (or nearly parallel) to the plane of the tilted wafer surface for all scans. The scan path of wafer translation can be linear for all scans. The path of wafer translation can be non-linear (e.g., curved) for all scans. The scan path can be parallel to the tilted wafer180for all scans. The wafer tilt can be constant during the scan path for all scans. The wafer tilt can vary along the path of the scan for all scans. The scan path can be parallel to the wafer180during at least one point in the scan for all scans. The scan path can be parallel to the wafer180at all points during the scan for all scans. The scan path can be in a different plane than the wafer180for all scans.

SUMMARY OF THE INVENTION

In accordance with an embodiment, the present disclosure relates to using asymmetric scanning velocity in an ion beam etch process to correct asymmetry of etching between the inboard side and the outboard side of device structures on a wafer while maintaining the overall uniformity of etch across the full wafer.

In accordance with another embodiment, the present disclosure relates to using asymmetric scanning velocity in an ion beam etch process to generate exaggerated asymmetry of etching between inboard and outboard sides of devices on a wafer, while maintaining the overall uniformity of etch across the full wafer.

In accordance with another embodiment, the present disclosure relates to using symmetric velocity scanning to enable control of inboard and outboard asymmetry even when the ion beam system is configured with a small ion source, and small grids. Without asymmetric velocity scanning, the ion source and grids will need to be of a lateral dimension larger than the sum of the wafer diameter, two times the beamlet divergence projected on the plane of the scan, and the ion beam density will need to be highly uniform across the lateral dimension.

In accordance with another embodiment, the present disclosure relates to using asymmetric velocity scans combined with symmetric velocity scans to address the inboard and outboard asymmetry and wafer etch uniformity, where the number of scans needed to finish the etch process may be a single scan or multiple scans.

In accordance with another embodiment, the present disclosure relates to a process whereby scan motion may be a straight linear motion of the wafer center across the ion beam or may include slight deviations from straight lines such as curved paths of motion of the wafer center across the ion beam.

In accordance with another embodiment, the present disclosure relates to an alternative to asymmetric velocity scan motion of the wafer where the ion beam current or the ion beam voltage is modulated as the wafer moves across the ion beam. The wafer may be exposed to either larger beam current or higher beam voltage when the wafer center is scanning on the far side of the scan beyond the mid-plane of the ion source.

In accordance with another embodiment, the present disclosure relates to an alternative to an asymmetric velocity profile scan by modulating the path of the scan, so that the wafer spends more time exposed to the ion beam on the far side of the scan after the wafer has passed the mid-plane of the ion source.

In accordance with another embodiment, the present disclosure relates to an alternative to the asymmetric velocity scan of the wafer across an ion beam by placing beam blocks in an asymmetric fashion with respect to the mid-plane of the ion source and grids, so that the wafer spends more time exposed to the ion beam on the far side of the scan even with the symmetrical velocity profile of the scan.

According to one aspect of an embodiment of the present disclosure, a method of correcting asymmetry during a wafer etching process is provided, where the method includes producing a plasma from a plasma source, the plasma source comprising a plasma chamber and an ion extraction grid system, the ion extraction grid system configured to produce an ion beam from the plasma, the ion beam having a central axis, supporting a wafer on a stage, scanning the wafer relative to the ion beam along a scan path, and modifying applied beam flux as a function of a position of the wafer.

According to another aspect of an embodiment of the present disclosure, a method of correcting asymmetry during a wafer etching process is provided, where the method includes producing a plasma from a plasma source, the plasma source comprising a plasma chamber and an ion extraction grid system, the ion extraction grid system configured to produce an ion beam from the plasma, the ion beam having a central axis, supporting a wafer on a stage including at least one of rotating the stage about the central axis and tilting the stage with respect to the ion beam during at least a portion of the etching process, scanning the wafer relative to the ion beam along a scan path in accordance with a scan velocity function, and modifying applied beam flux as a function of a position of the wafer by varying the scan velocity function as the wafer travels along the scan path.

According to another aspect of an embodiment of the present disclosure, a method of correcting asymmetry during a wafer etching process is provided, where the method includes producing a plasma from a plasma source, the plasma source comprising a plasma chamber and an ion extraction grid system, the ion extraction grid system configured to produce an ion beam from the plasma, the ion beam having a central axis, supporting a wafer on a stage, scanning the wafer relative to the ion beam along a scan path, the scan path comprising a scan out path from the first end of the ion beam to the second end of the ion beam according to a scan out velocity function and a scan back path from the second end of the ion beam to the first end of the ion beam according to a scan back velocity function, wherein one of the scan out velocity function and the scan back velocity function varies as a function of time, and modifying applied beam flux as a function of a position of the wafer.

According to another aspect of an embodiment of the present disclosure, a method of correcting asymmetry during a wafer deposition process is provided, where the method includes producing a plasma from a plasma source, the plasma source comprising a plasma chamber and an ion extraction grid system, the ion extraction grid system configured to produce an ion beam from the plasma, the ion beam having a central axis, supporting a wafer on a stage, scanning the wafer relative to the ion beam along a scan path, and modifying applied beam flux as a function of a position of the wafer.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or can be learned by practice of the herein disclosed principles. The features and advantages of the disclosure can be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. These and other features of the disclosure will become more fully apparent from the following description and appended claims, or can be learned by the practice of the principles set forth herein.

