BACKGROUND

Level shifters are used in applications where there is a need to interface between different voltage domains. Level shifters can be full-swing or floating, which can be distinguished by whether the voltage domains share a common ground potential. Floating level shifters are used to shift the potential of control signals from circuits powered by low voltage power rails to the potential of circuits with floating power and ground rails. Floating level shifters are often used in gate drivers to drive power output stages in applications such as DC-DC converters, biomedical transducer drivers, Class-D audio amplifiers, MEMS, LCD drivers, high voltage charge pumps, switched-capacitor supplies, etc.

While the gate driver typically is exposed to relatively low voltages, the level shifter and possibly other components such as a bootstrap switch or diode must use high-voltage components, i.e., components which can withstand the whole input voltage range. If the high voltage range is higher than the maximum allowed voltage for the single component but still within the technology capability, cascoding approaches can also be used.

There are several ways to implement a high voltage level shifter such as cascading a high voltage device, transformer based level shifting and capacitance based level shifting. The cascoding approach tends to be slower due to the stacking of devices which typically are high voltage and therefore consume layout area, degrade (speed) performance and require accurate parasitic modelling and extraction. For high speed gate driver applications such as full-bridge, half-bridge, non-isolated buck topologies, etc. where high common mode rejection is crucial to ensure a reliable output signal, the main advantage of transformer and capacitive based level shifting solutions is that they are dynamically driven. Since inductors and capacitors block any DC component of the signal, the control signal is transformed into a sequence of pulses, either single-ended or differential, which drive the transformer or capacitor. A static control input signal is therefore translated into a continuous sequence of pulses which refresh the stage of the gate driver in order to prevent false triggering due to noise. The repetition rate is defined by application conditions like switching frequency and duty cycle and may translate in sub-nanosecond requirements. This in turn implies high current consumption.

Thus, there is a need for an improved level shifter design.

SUMMARY

According to an embodiment of a capacitive-coupled level shifter, the capacitive-coupled level shifter comprises: an input having a positive input terminal and a negative input terminal, the input configured to receive a modulated signal in a first voltage domain; a comparator circuit configured to shift the modulated signal to a second voltage domain higher than the first voltage domain; and a capacitive divider circuit comprising a first capacitive divider branch coupling the positive input terminal of the input to a positive input terminal of the comparator circuit and a second capacitive divider branch coupling the negative input terminal of the input to a negative input terminal of the comparator circuit, the first capacitive divider branch and the second capacitive divider branch being symmetric so as to cancel out a common mode voltage of the modulated signal.

In one embodiment, the first capacitive divider branch comprises a first capacitor coupling the positive input terminal of the input to the positive input terminal of the comparator circuit, a second capacitor coupling a voltage supply for the comparator circuit to the positive input terminal of the comparator circuit, and a third capacitor coupling a switched voltage node to the positive input terminal of the comparator circuit, and the second capacitive divider branch comprises a fourth capacitor coupling the negative input terminal of the input to the negative input terminal of the comparator circuit, a fifth capacitor coupling the voltage supply for the comparator circuit to the negative input terminal of the comparator circuit, and a sixth capacitor coupling the switched voltage node to the negative input terminal of the comparator circuit.

Separately or in combination, the capacitive-coupled level shifter may further comprise a resistor ladder connected between the voltage supply for the comparator circuit and the switched voltage node. The resistor ladder may comprise a first resistor, a second resistor and a third resistor connected in series, the first resistor may be electrically connected between the voltage supply for the comparator circuit and a first terminal of the second resistor, the third resistor electrically may be electrically connected between the switched voltage node and a second terminal of the second resistor, the first terminal of the second resistor may be electrically connected to the negative input terminal of the comparator circuit, and the second terminal of the second resistor may be electrically connected to the positive input terminal of the comparator circuit. The first resistor and the third resistor may be approximately equal, and the second resistor may be less than the first resistor and the third resistor.

Separately or in combination, the input may also have a reference terminal, the capacitive divider circuit may comprise a third capacitive divider branch coupling the reference terminal of the input to a common mode reference terminal of the comparator circuit, and the modulated signal may be single-ended between the positive input terminal of the input and the reference terminal of the input, and between the negative input terminal of the input and the reference terminal of the input.

Separately or in combination, the capacitive-coupled level shifter may further comprise: a first resistor ladder connected between the voltage supply for the comparator circuit and the switched voltage node; a second resistor ladder connected between the voltage supply for the comparator circuit and the switched voltage node; and a third resistor ladder connected between the voltage supply for the comparator circuit and the switched voltage node.

The first resistor ladder may comprise a first resistor, a second resistor and a third resistor connected in series. The first resistor may be electrically connected between the voltage supply for the comparator circuit and a first terminal of the second resistor. The third resistor may be electrically connected between the switched voltage node and a second terminal of the second resistor. The second terminal of the second resistor may be electrically connected to the common mode reference terminal of the comparator circuit.

The second resistor ladder may comprise a fourth resistor and a fifth resistor connected in series. The fourth resistor may be electrically connected between the voltage supply for the comparator circuit and a first terminal of the fifth resistor. A second terminal of the fifth resistor may be electrically connected to the switched voltage node. The first terminal of the fifth resistor may be electrically connected to the negative input terminal of the comparator circuit.

The third resistor ladder may comprise a sixth resistor and a seventh resistor connected in series. The sixth resistor may be electrically connected between the voltage supply for the comparator circuit and a first terminal of the seventh resistor. A second terminal of the seventh resistor may be electrically connected to the switched voltage node. The first terminal of the seventh resistor may be electrically connected to the positive input terminal of the comparator circuit.

Separately or in combination, the capacitive-coupled level shifter of claim1may further comprise a resistor ladder configured to fix a DC biasing point of the positive and the negative inputs of the comparator circuit.

Separately or in combination, the comparator circuit may comprise: a differential pair of transistors configured to output an amplified version of the modulated signal in the second voltage domain; and a converter circuit configured to convert the amplified version of the modulated signal into a rail-to-rail digital output signal which is a replica, in the second voltage domain, of a digital control signal from which the modulated signal is generated in the first voltage domain.

Separately or in combination, the capacitive-coupled level shifter may further comprise a speed booster circuit configured to increase gain of the converter circuit. The speed booster circuit may comprise: a PMOS current source electrically connected in series with an NMOS switch between the voltage supply for the comparator circuit and the switched voltage node; and a PMOS switch configured to enable or disable a PMOS current source of the converter circuit based on a state of the rail-to-rail digital output signal provided by the converter circuit.

Separately or in combination, a voltage hysteresis of the capacitive-coupled level shifter may be greater than a6asigma equivalent input offset of the comparator circuit and less than the modulated signal input to the comparator circuit with a common mode voltage of the modulated signal cancelled out.

Separately or in combination, no reference terminal may be provided between the positive input terminal and the negative input terminal of the input, no common mode reference terminal may be provided between the positive input terminal and the negative input terminal of the comparator circuit, and the modulated signal may be differential between the positive input terminal of the input and the negative input terminal of the input.

Separately or in combination, the capacitive-coupled level shifter may further comprise a speed booster circuit configured to increase gain of the converter circuit, the comparator circuit may comprise a differential pair of transistors configured to output an amplified version of the modulated signal in the second voltage domain and a first PMOS current source electrically connected to a first NMOS switch driven by a positive output of the differential pair of transistors and electrically connected to a second NMOS switch driven by a negative output of the differential pair of transistors, and the speed booster circuit may comprise a second PMOS current source electrically connected in series with a third NMOS switch driven by the positive output of the differential pair of transistors, and a PMOS switch configured to enable or disable the first PMOS current source based on a state of a rail-to-rail digital output signal provided by the converter circuit.

Separately or in combination, a reference terminal may be provided between the positive input terminal and the negative input terminal of the input, a common mode reference terminal may be provided between the positive input terminal and the negative input terminal of the comparator circuit, and the modulated signal may be single-ended between the positive input terminal of the input and the reference terminal of the input, and between the negative input terminal of the input and the reference terminal of the input.

Separately or in combination, the capacitive-coupled level shifter may further comprise a first speed booster circuit and a second speed booster circuit configured to increase gain of the converter circuit, the comparator circuit may comprise a first differential pair of transistors configured to output a first amplified version of the modulated signal applied between the positive input terminal and the common mode reference terminal of the comparator circuit in the second voltage domain, a second differential pair of transistors configured to output a second amplified version of the modulated signal applied between the negative input terminal and the common mode reference terminal of the comparator circuit in the second voltage domain, a first PMOS current source electrically connected to a first NMOS switch driven by a positive output of the first differential pair of transistors and electrically connected to a second NMOS switch driven by a common reference output of the first and the second differential pairs of transistors, and a second PMOS current source electrically connected to a third NMOS switch driven by a negative output of the second differential pair of transistors and electrically connected to a fourth NMOS switch driven by the common reference output, the first speed booster circuit may comprise a third PMOS current source electrically connected in series with a fifth NMOS switch driven by the common reference output, and a first PMOS switch configured to enable or disable the first PMOS current source based on a state of a rail-to-rail positive digital output signal provided by the converter circuit, and the second speed booster circuit may comprise a fourth PMOS current source electrically connected in series with a sixth NMOS switch driven by the common reference output, and a second PMOS switch configured to enable or disable the second PMOS current source based on a state of a rail-to-rail negative digital output signal provided by the converter circuit.

According to an embodiment of a level shifter system, the level shifter system comprises at least one capacitive-coupled level shifter comprising: an input having a positive input terminal and a negative input terminal, the input configured to receive a modulated signal in a first voltage domain; a comparator circuit configured to shift the modulated signal to a second voltage domain higher than the first voltage domain; and a capacitive divider circuit comprising a first capacitive divider branch coupling the positive input terminal of the input to a positive input terminal of the comparator circuit and a second capacitive divider branch coupling the negative input terminal of the input to a negative input terminal of the comparator circuit, the first capacitive divider branch and the second capacitive divider branch being symmetric so as to cancel out a common mode voltage of the modulated signal. The level shifter system further comprises: a modulator configured to modulate a carrier with a digital control signal to form a continuous sequence of pulses, and input the continuous sequence of pulses as the modulated signal to the input of the at least one capacitive-coupled level shifter; and an SR latch having a set input electrically connected to a first output of the at least one capacitive-coupled level shifter and a reset input electrically connected to a second output of the at least one capacitive-coupled level shifter, the SR latch configured to output a level-shifted signal based on a state of the set input and the reset input.

Separately or in combination, the level shifter system may comprise a first capacitive-coupled level shifter and a second capacitive-coupled level shifter. For each capacitive-coupled level shifter, no reference terminal may be provided between the positive input terminal and the negative input terminal of the input, no common mode reference terminal may be provided between the positive input terminal and the negative input terminal of the comparator circuit, and the modulated signal may be differential between the positive input terminal of the input and the negative input terminal of the input. The modulator may be configured to apply the differential modulated signal to the first capacitive-coupled level shifter when the digital control signal is in a first state and apply the differential modulated signal to the second capacitive-coupled level shifter when the digital control signal is in a second state. The first capacitive-coupled level shifter may be configured to apply the shifted modulated signal to the set input of the SR latch when the digital control signal is in the first state. The second capacitive-coupled level shifter may be configured to apply the shifted modulated signal to the reset input of the SR latch when the digital control signal is in the second state.

Separately or in combination, the level shifter system may comprise a single capacitive-coupled level shifter. The single capacitive-coupled level shifter may comprise a reference terminal between the positive input terminal and the negative input terminal of the input, and a common mode reference terminal between the positive input terminal and the negative input terminal of the comparator circuit. The modulated signal may be single-ended between the positive terminal and the reference terminal of the input, and between the negative input terminal and the reference terminal of the input. The modulator may be configured to apply the single-ended modulated signal between the positive input terminal and the negative input terminal of the input of the single capacitive-coupled level shifter when the digital control signal is in a first state, and to apply the single-ended modulated signal between the negative input terminal and the negative input terminal of the input of the single capacitive-coupled level shifter when the digital control signal is in a second state. The single capacitive-coupled level shifter may be configured to apply the shifted modulated signal to the set input of the SR latch when the digital control signal is in the first state and to the reset input of the SR latch when the digital control signal is in the second state.

Separately or in combination, the level shifter system may be configured to apply the level-shifted signal to a high-side gate driver.

Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

