TECHNICAL FIELD

Embodiments of the present disclosure pertain to the field of electronic device manufacturing, and in particular, to an integrated circuit (IC) manufacturing. More particularly, embodiments of the disclosure are directed to methods of producing self-aligned bit-line-contacts (BLC).

BACKGROUND

Generally, an integrated circuit (IC) refers to a set of electronic devices, e.g., transistors formed on a small chip of semiconductor material, typically, silicon. Typically, the IC includes one or more layers of metallization having metal lines to connect the electronic devices of the IC to one another and to external connections. Typically, layers of the interlayer dielectric material arc placed between the metallization layers of the IC for insulation.

As the size of the IC decreases, the spacing between the metal lines decreases and misalignment of contact becomes less tolerable. Conventional processes for dynamic random access memory (DRAM) bit-line-contact (BLC) layers use a Lithography-Etch-Lithography-Etch (LELE) patterning scheme. The LELE scheme has strict edge placement error (EPE) requirements on DRAM manufacturers to correctly land BLC on the Active material. Slight misalignments of the contacts can cause shorting between adjacent memory cells.

Accordingly, there is a need in the art for methods of forming bit line contacts with decreased edge placement errors.

SUMMARY

One or more embodiments of the disclosure are directed to electronic devices comprising: a plurality of spaced wordlines defining a third direction, each of the wordlines spaced from adjacent wordlines by a dielectric; and a plurality of substrate islands within the dielectric between the wordlines, the substrate islands extending in a first direction, second direction and third direction, the substrate islands comprising trapezoid-like shaped islands (TI), right-facing rhombus-like islands (RFI) and left-facing rhombus-like islands (LFI) arranged in repeating patterns along the first direction, the second direction and the third direction, the first direction and the third direction, the islands form a repeating pattern of TI, RFI and LFI, along the second direction, the islands appearing as a line of single type to have a line of TI, a line of RFI and a line of LFI

Additional embodiments are directed to methods of forming an electronic device comprising reusing hardmask materials and lithography reticles.

One or more embodiments are directed to method of forming an electronic device. In one or more embodiments, a method of forming an electronic device comprises: forming a set of first lines, the set of first lines having a top surface and spaced to form a recess; forming a dielectric layer, a portion of the dielectric layer filling the recess; planarizing a top surface of the dielectric layer; selectively patterning the dielectric layer to form a first hardmask, the first hardmask having a first hardmask top surface and plurality of trenches exposing the top surface of the set of first lines; patterning the first hardmask; forming a second hardmask, the second hardmask having raised portions and lower portions; planarizing to exposing an alternating pattern of first hardmask and second hardmask; forming and patterning a third hardmask, the patterned third hardmask having a top surface and a plurality of channels formed therein; forming and patterning a fourth hardmask; forming diamond-shaped or rhomboid shaped openings bound by sidewalls of the first hardmask and sidewalls of the second hardmask; forming a fifth hard mask; selectively removing the first hardmask to form diamond-shaped or rhomboid shaped openings bound by sidewalls of the first hardmask under the third hardmask and by sidewalls of the second hardmask; and selectively removing the third hardmask and the fifth hardmask.

