BACKGROUND

Digital signal processors (DSP) are optimized for processing streams of data that may be derived from various input signals, such as sensor data, a video stream, a voice channel, radar signals, biomedical signals, etc. Digital signal processors operating on real-time data typically receive an input data stream, perform a filter function on the data stream (such as encoding or decoding) and output a transformed data stream. The system is called real-time because the application fails if the transformed data stream is not available for output when scheduled. Typical video encoding requires a predictable but non-sequential input data pattern. A typical application requires memory access to load data registers in a data register file and then supply data from the data registers to functional units which perform the data processing.

One or more DSP processing cores can be combined with various peripheral circuits, blocks of memory, etc. on a single integrated circuit (IC) die to form a system on chip (SoC). These systems can include multiple interconnected processors that share the use of on-chip and off-chip memory. A processor can include some combination of instruction cache (ICache) and data cache (DCache) to improve processing. Furthermore, multiple processors with shared memory can be incorporated in a single embedded system. The processors can physically share the same memory without accessing data or executing code located in the same memory locations or can use some portion of the shared memory as common shared memory.

SUMMARY

Embodiments of the present disclosure relate to methods and systems for vector permutation. In one aspect, a method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.

In one aspect, a processor is provided that includes a control storage location configured to store permute control input for each lane of an output vector, and a permutation component coupled to the control storage location, wherein the permutation component is configured to store any value in any lane of an input vector in any lane of the output vector based on the permute control input for each lane of the output vector, the storing of values performed responsive to a vector permutation instruction.

In one aspect, a method is provided that includes generating, by a processor in response to a vector permutation instruction, an intermediate vector, wherein one half of the intermediate vector consists of values of selected lanes of a first vector and another half of the intermediate vector consists of values from selected lanes of a second vector, permuting the intermediate vector by the processor to generate a permuted vector, the permuting performed based on a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane indicates a value to be store in the lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.

