BACKGROUND

Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and fabrication methods thereof.

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A 3D memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

SUMMARY

Embodiments of 3D memory devices and methods for forming the same are disclosed herein.

In one example, a method for forming a 3D memory device is disclosed. A first semiconductor layer, a first block layer, and a sacrificial layer are sequentially formed on a substrate. A block plug extending vertically through the sacrificial layer and the first block layer is formed to divide the sacrificial layer into a supporting portion and a sacrificial portion. A dielectric stack is formed above the sacrificial layer and has a staircase region, such that the supporting portion of the sacrificial layer is below and overlaps the staircase region of the dielectric stack. A channel structure extending vertically through the dielectric stack, the sacrificial portion of the sacrificial layer, and the first block layer, into the first semiconductor layer is formed. An opening extending vertically through the dielectric stack is formed to expose part of the sacrificial portion of the sacrificial layer. The sacrificial portion of the sacrificial layer is replaced with a second semiconductor layer coplanar with the supporting portion of the sacrificial layer through the opening.

In another example, a method for forming a 3D memory device is disclosed. A first semiconductor layer, a first block layer, and a sacrificial layer are sequentially formed on a substrate. Part of the first block layer and the sacrificial layer is replaced with a supporting structure. A dielectric stack is formed above the supporting structure and a remainder of the sacrificial layer and has a staircase region, such that the supporting structure overlaps the staircase region of the dielectric stack. A channel structure extending vertically through the dielectric stack, the remainder of the sacrificial layer, and the first block layer, into the first semiconductor layer is formed. An opening extending vertically through the dielectric stack is formed to expose part of the remainder of the sacrificial layer. The remainder of the sacrificial layer is replaced with a second semiconductor layer coplanar with the supporting structure through the opening.

In still another example, a method for forming a 3D memory device is disclosed. A peripheral circuit is formed on a first substrate. A first semiconductor layer is formed on a second substrate. A supporting structure and a second semiconductor layer coplanar with the supporting structure are formed on the first semiconductor layer. A memory stack is formed above the supporting structure and the second semiconductor layer. The memory stack has a staircase region overlapping the supporting structure. A channel structure extending vertically through the memory stack and the second semiconductor layer into the first semiconductor layer is formed. The first substrate and the second substrate are bonded in a face-to-face manner.

