BACKGROUND OF THE INVENTION

1. Field of the Invention

One embodiment of the present invention relates to a semiconductor device and an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. One embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Specific examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a memory device, a signal processing device, a processor, an electronic device, a system, a method for driving any of them, a method for manufacturing any of them, and a method for inspecting any of them.

2. Description of the Related Art

In recent years, electronic components such as central processing units (CPUs), graphics processing units (GPUs), memory devices, and sensors have been used in various electronic devices such as personal computers, smartphones, and digital cameras. The electronic components have been improved to achieve miniaturization, lower power consumption, and other various objectives.

Memory devices with large memory capacity are required because the amount of data handled in the aforementioned electronic devices and the like has increased. As an example of a way to increase the memory capacity, Patent Documents 1 and 2 disclose a three-dimensional NAND memory element using a metal oxide in a channel formation region.

REFERENCE

Patent Document

[Patent Document 1] PCT International Publication No. 2019/003060[Patent Document 2] Japanese Published Patent Application No. 2018-207038

SUMMARY OF THE INVENTION

One object of one embodiment of the present invention is to provide a highly reliable memory device. Another object of one embodiment of the present invention is to provide a memory device having large memory capacity. Another object of one embodiment of the present invention is to provide a novel memory device. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device having large memory capacity. Another object of one embodiment of the present invention is to provide a novel semiconductor device.

Note that the objects of one embodiment of the present invention are not limited to the objects mentioned above. The objects listed above do not preclude the existence of other objects. The other objects are the ones that are not described above and will be described below. The other objects will be apparent from and can be derived from the description of the specification, the drawings, and the like by those skilled in the art. One embodiment of the present invention achieves at least one of the above objects and the other objects. One embodiment of the present invention does not necessarily achieve all the above objects and the other objects.

One embodiment of the present invention is a semiconductor device that includes an arithmetic processing device and a memory device. The arithmetic processing device and the memory device have an overlap region. The memory device includes a plurality of memory cells. Each of the memory cells contains an oxide semiconductor. The memory device is of NAND type and operates as a RAM.

One embodiment of the present invention is a semiconductor device including a component extending in a first direction, and a first conductor and a second conductor extending in a second direction. The component includes a third conductor extending in the first direction, a first insulator adjacent to the third conductor, a first semiconductor adjacent to the first insulator, and a second insulator adjacent to the first semiconductor. In a first intersection portion where the component and the first conductor cross each other, a second semiconductor adjacent to the second insulator and a third insulator adjacent to the second semiconductor are provided between the component and the first conductor. In a second intersection portion where the component and the second conductor cross each other, the component includes a fourth conductor adjacent to the second insulator and a fourth insulator adjacent to the fourth conductor. In the first intersection portion, the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are provided concentrically around the third conductor. In the second intersection portion, the first insulator, the first semiconductor, the second insulator, the fourth conductor, and the fourth insulator are provided concentrically around the third conductor.

The first direction is orthogonal to the second direction. Note that the first intersection portion functions as a transistor for data writing, and the second intersection portion functions as a transistor for data reading and a capacitor.

The first intersection portion can function as a first transistor. The second intersection portion can function as a second transistor and a capacitor. The semiconductor device can function as a NAND memory device, for example.

At least one of the first semiconductor and the second semiconductor is preferably an oxide semiconductor. The oxide semiconductor preferably contains at least one of indium and zinc.

Another embodiment of the present invention is an electronic device including at least one of an operation switch, a battery, and a display portion, and a plurality of the above semiconductor devices.

According to one embodiment of the present invention, a highly reliable memory device can be provided. Alternatively, a memory device having large memory capacity can be provided. A novel memory device can be provided. A highly reliable semiconductor device can be provided. A semiconductor device having large memory capacity can be provided. A novel semiconductor device can be provided.

Note that the effects of one embodiment of the present invention are not limited to the effects mentioned above. The effects described above do not preclude the existence of other effects. The other effects are the ones that are not described above and will be described below. The other effects will be apparent from and can be derived from the description of the specification, the drawings, and the like by those skilled in the art. One embodiment of the present invention has at least one of the above effects and the other effects. Accordingly, one embodiment of the present invention does not have the above effects in some cases.

