BACKGROUND

Field of the Invention

The present invention relates to semiconductor devices, more particularly, to device structures and methods of forming trench metal oxide semiconductor field effect transistor (MOSFET) as part of Power MOSFET or Insulated Gate Bipolar Transistor (IGBT) devices.

Description of the Related Art

In power metal oxide semiconductor field effect transistor (MOSFET) devices, as the resistance per square area is kept decreasing due to the availability of new structures, advanced process techniques and tools, die sizes for MOSFET products are also getting smaller and smaller. There are several challenges to be addressed in advanced trench MOSFET products with smaller die sizes, for example: (1) increasing thermal resistance of the smaller die, (2) increasing robustness of the MOSFETs to handle much higher current density under unclamped inductive, high dv/dt and diode recovery mode of operations compared to low performing larger die area type power MOSFETs, and (3) minimizing Rds and Cgd variations due to large variation of Inter Poly Oxide (IPO) thickness.

Manufacturing thinner dies and improved power device packaging can address the thermal resistance related issues in power MOSFET devices. Improving the robustness of power MOSFET devices in smaller dies includes, for example, (1) providing structures and processes to localize breakdown in the middle of the MOSFET body, (2) ensuring device avalanche breakdown to occur in the active device cells (MOSFETs) rather than the termination areas, (3) keeping extremely low p body to source shorting resistance to prevent turn on of parasitic NPN bipolar transistor of the MOSFET. Mask misalignment of a non-self-aligned p body contact to trench causes an increased shorting resistance between the p body and the n+ source of the MOSFET. Therefore, there is a need for new processes to form p+ body contact structures to minimize the adverse effect of the non-self-aligned p body contacts. Insulated Gate Bipolar Transistors can also benefit from having self-aligned p+ contact to have more uniform threshold voltage distribution and more robust IGBT.

SUMMARY

An aspect of the present invention provides a method of forming shielded gate trench MOSFET devices, including: providing a silicon layer having n type conductivity layer overlying a semiconductor substrate; forming, on a mesa surface of the silicon layer, a plurality of gate trenches in an active region, the gate trenches extending orthogonally from the mesa surface toward the semiconductor substrate; forming in each gate trench a gate trench stack including: a shield layer lining side walls and bottom wall of each gate trench, wherein the shield layer is silicon oxide; forming a first doped poly silicon layer on a portion of the shield layer lining the bottom wall and lower portions of the side walls of the gate trench; forming an inter poly oxide (IPO) layer, on top of the first doped poly silicon layer, having a predefined thickness; growing a gate oxide and forming a second doped poly silicon layer on the IPO layer; etching back top surface of the second doped poly silicon layer to lower the top surface, within the gate trench, below the mesa surface; forming oxide plugs on top surface of the second doped poly silicon inside the trench; etching down the mesa surface to make the mesa surface substantially coplanar with the top surface of the second doped polysilicon layer; forming p body and n+ source regions of the MOSFET in the mesa surface; forming silicon dioxide spacers defining the self-aligned p+ contact trench; and filling the self-aligned p+ contact trench with a metal plug.

Another aspect of the present invention provides a method of forming trench MOSFET devices, including: providing a silicon layer having n type conductivity layer overlying a semiconductor substrate; forming, on a mesa surface of the silicon layer, a plurality of gate trenches in an active region, the gate trenches extending orthogonally from the mesa surface toward the semiconductor substrate; forming in each gate trench a gate trench stack including: growing a gate oxide and forming a doped poly silicon layer on the gate oxide layer; etching back top surface of the doped poly silicon layer to lower the top surface, within the gate trench, below the mesa surface; forming oxide plug on top surface of the doped poly silicon inside the trench; etching down the mesa surface to make the mesa surface substantially coplanar with the top surface of the second doped polysilicon layer; forming p body and n+ source regions of the MOSFET in the mesa surface; forming silicon dioxide spacers defining the self-aligned p+ contact trench; and filling the self-aligned p+ contact trench with a metal plug.

Another aspect of the present invention provides a method of forming shielded gate trench MOSFET devices, including: providing a silicon layer having n type conductivity overlying a semiconductor substrate; forming, on a mesa surface of the silicon layer, a plurality of gate trenches in an active region, the gate trenches extending orthogonally from the mesa surface toward the semiconductor substrate; forming in each gate trench a gate trench stack including: forming a shield layer lining side walls and bottom wall of each gate trench, wherein the shield layer is silicon oxide; forming a first doped poly silicon layer on a portion of the shield layer lining the bottom wall and lower portions of the side walls of the gate trench; removing upper portions of the shield layer to expose upper portions of the side walls; forming an Inter Poly Oxide (IPO) layer on the first doped poly silicon layer by filling the trench with dielectric, planarizing and etching back to predefined thickness; growing gate oxide, depositing and planarizing a second doped poly silicon; etching back the second doped poly silicon below the mesa surface; forming an oxide plug to fill in the upper portion of the second doped poly silicon layer inside the trench by deposition of oxide, planarizing and leaving a thin layer oxide on the silicon mesa and also exposed surface portions of the first doped poly silicon layer; etching down oxide from the mesa surfaces by using an active area mask; etching down the mesa surface; forming silicon dioxide spacer to widen oxide plugs laterally after ion implantation of boron for p body and of arsenic implant for n+ source; forming p+ contact trenches by etching the front surface of the silicon layer utilizing widened oxide plugs as a self-aligned mask; forming metal plug contacting n+ source and the p base by deposition of Ti and W and CMP of W; forming an Interlayer Dielectric by deposition of oxide and BPSG or PSG; and forming gate, first poly silicon layer and second polysilicon layer contact windows before metallization.

Another aspect of the present invention provides a method of forming shielded gate trench MOS devices, including: providing a silicon layer having a first type conductivity overlying a semiconductor substrate; forming, on a mesa surface of the silicon layer, a plurality of gate trenches in an active region, the gate trenches extending orthogonally from the mesa surface toward the semiconductor substrate; forming in each gate trench a gate trench stack including: forming a shield layer lining side walls and bottom wall of each gate trench, wherein shield layer is silicon oxide; forming a first doped poly silicon layer on a portion of the shield layer lining the bottom wall and lower portions of the side walls of the gate trench; removing upper portions of the shield layer to expose upper portions of the side walls; forming an inter poly oxide (IPO) layer including a thermally grown oxide over first poly silicon, wherein forming of the IPO layer results in forming silicon oxide layer on upper portions of the side walls; depositing a high density plasma (HDP) oxide layer on the oxide layer to further thicken IPO layer, wherein a thickness ratio of the HDP oxide layer on the side walls to on the IPO layer is about 1/5; removing the HDP oxide and the silicon oxide from the trench side walls using wet etching while retaining the HDP oxide over the IPO layer and major portions of the HDP oxide layer on the mesa surface; growing a gate oxide layer on the upper portions of the side walls and forming a second doped poly silicon layer or gate poly Si, on the gate oxide layer and the IPO layer, filling the gate trench; recessing the second doped poly silicon about 0.2-0.5 micron below the mesa surface; forming oxide plugs by depositing oxide on top surface of the second doped poly silicon, which is recessed, in the gate trench and planarizing the oxide by using chemical mechanical polishing (CMP); etching back the remaining oxide after CMP until the silicon mesa exposed, leaving oxide plug on top of the gate poly silicon by using an active area mask to protect the first doped poly silicon layer exposure at the first doped poly silicon layer regions where contact to source metal occurs; utilizing oxide plugs as a self-aligned mask to etch down silicon mesa 0.2 to 0.5 micron below the mesa surface of the silicon layer; forming p body regions and n+ source regions extending between the gate trenches; forming oxide spacers by depositing and reactive ion etching (RIE) of the oxide to widen oxide plugs laterally to narrow down silicon mesa; forming p+ body contact trenches self-aligned to gate trenches by RIE etching of the silicon mesa 0.2-0.5 micron below the silicon mesa surface; forming p+ body contact regions by ion implantation; forming W plugs by sputter deposing Ti/TiN and CVD deposition of W and CMP W and then etching of Ti/TiN; depositing oxide and BPSG layer; and opening source, p body, first poly Si and gate contacts by oxide/BPSG etching.

