CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Japan application serial no. 2020-107842, filed on Jun. 23, 2020. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

Technical Field

The disclosure relates to an input receiver, and in particular, relates to an input receiver adopting a multilevel inverter circuit structure.

Description of Related Art

Semiconductor devices such as dynamic random access memory (DRAM) are provided with input receivers configured to receive external input signals. Generally, in an input receiver, an input signal is compared with a reference voltage, and according to the voltage difference therebetween, a differential-type amplifier circuit configured to amplify a signal is generated.

In a conventional design, an input receiver may perform operations correctly in a high-speed environment through an output-level shunt resistor disposed in the input receiver. Nevertheless, due to the effect of leakage current, the use of the shunt resistor may lead to additional power consumption, overall DRAM performance is thereby lowered.

SUMMARY

The disclosure provides an input receiver in which an inverter circuit structure connected to an amplifier circuit in parallel between nodes is used to replace a shunt resistor used in a conventional design.

An input receiver provided by the disclosure includes a first current source circuit, a second current source circuit, a first rail-to-rail amplifier circuit, a first inverter circuit, and a second inverter circuit. The first current source circuit is coupled between an operating voltage and a first node and adjusts an operating current flowing through the first node according to a first bias signal. The second current source circuit is coupled between a second node and a ground voltage and adjusts a ground current flowing through the second node according to a second bias signal. The first rail-to-rail amplifier circuit is coupled between the first node and the second node. The first rail-to-rail amplifier circuit receives an input signal and compares the input signal with a reference voltage and accordingly outputs an amplified signal. The first inverter circuit is connected to the first rail-to-rail amplifier circuit in parallel between the first node and the second node. The first inverter circuit is configured to receive the amplified signal and provide an inverted signal. The second inverter circuit is coupled between an operating voltage and a ground voltage. The second inverter circuit is configured to generate an output signal according to the inverted signal.

To sum up, in the input receiver provided by the disclosure, the inverter circuit and the rail-to-rail amplifier circuit are connected in parallel between two nodes. Since the inverter circuit may be configured to be operated in voltage swing equal to the amplified signal outputted by the rail-to-rail amplifier circuit, the input receiver may not only perform operations correctly in a high-speed environment but also may work at a high operating speed and require low power consumption.

