CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority of Taiwan Patent Application No. 108142881, filed on Nov. 26, 2019, the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

Field of the Invention

The present disclosure relates to a semiconductor structure and a method for forming the same, and in particular it relates to a self-aligned contact and a method for forming the same.

Description of the Related Art

As the size of integrated circuits is reduced, the distance between the self-aligned contact structure and the gate structure becomes smaller. This increases the probability of leakage current due to a short circuit. In the traditional method of manufacturing self-aligned contact structures, sidewall spacers of the gate structure may be damaged when forming the self-aligned contact structure. Such incomplete sidewall spacers may not be able to effectively isolate the self-aligned contact structure from the gate structure, and leakage current may occur between the gate structure and the self-aligned contact structure.

Although existing self-aligned contact structures have been adequate for their intended purposes, they have not been entirely satisfactory in all respects. Therefore, the development of a process that can further improve the yield of the self-aligned contact structure is still one of the goals that the industry is aiming at.

BRIEF SUMMARY OF THE INVENTION

In accordance with some embodiments of the present disclosure, a method for forming the semiconductor structure is provided. The method includes the following steps: providing a substrate; forming a plurality of gate structures on the substrate; forming a lining layer on the substrate and the plurality of gate structures; forming a first spacer layer on the lining layer; forming a stop layer on the first spacer layer; forming a first sacrificial layer on the stop layer and between the plurality of gate structures; removing a portion of the first sacrificial layer so that the top surface of the first sacrificial layer is located between the upper portions of the gate structures; forming a second spacer layer on the first sacrificial layer and the plurality of gate structures; removing a portion of the second spacer layer so that the remaining second spacer layer is located between the upper portions of the gate structures; forming a second sacrificial layer on the plurality of gate structures and between the gate structures; removing the first sacrificial layer and the second sacrificial layer, and removing portions of the lining layer, the first spacer layer, and the stop layer to form a plurality of contact openings between the gate structures, wherein the contact openings expose a part of the surface of the substrate; and filling a conductive material into the contact openings to form a plurality of contact plugs.

In accordance with some embodiments of the present disclosure, a semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of gate structures, a lining layer, a first spacer layer, a stop layer, a second spacer layer, and a plurality of contact plugs. The plurality of gate structures are located on the substrate. The lining layer is located on the plurality of gate structures. The first spacer layer is located on the lining layer. The stop layer is located on the first spacer layer. The second spacer layer is located on the upper portions of the gate structures and the contact plugs are located between the gate structures.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

