CROSS REFERENCE TO RELATED APPLICATIONS

The present disclosure claims priority to Chinese Patent Application No. 202110207206.1 filed with the China National Intellectual Property Administration on Feb. 24, 2021, the entire contents of which are incorporated herein by its reference.

FIELD

The present disclosure relates to the field of display technology, and in particular to a BOE Dual cell (BD cell) display panel, a manufacturing method and a driving method thereof, and a display device.

BACKGROUND

Due to the process capability of equipment, large-sized display panel products often show large-area bulk mura, a dividing line is 1-2 pixels wide in a vertical or horizontal direction, and there is a brightness difference on both sides.

SUMMARY

Embodiments of the present disclosure provide a BD cell display panel, a manufacturing method and a driving method thereof, and a display device.

In a first aspect, an embodiment of the present disclosure provides a BD cell display panel including a main cell including a first display area; a sub cell stacked on the main cell, wherein the sub cell including a second display area; an X-printed circuit board assembly (X-PCBA) plate on a side of the sub cell away from the main cell, wherein the X-PCBA plate is bound with the main cell and the sub cell by a chip on film (COF), and stores a pixel offset amount and mura compensation data, the pixel offset amount is a quantity of pixels misaligned by the first display area with the second display area after the main cell is fitted with the sub cell, and the mura compensation data is data that compensates for mura in the main cell and the sub cell; and a control plate configured to read the pixel offset amount and the mura compensation data from the XPCBA plate, and adjust at least one of the first display area and the second display area according to the pixel offset amount, thus causing pixels in the first display area and the second display area that are orthogonally projected within an actual display area of the BD cell display panel to be displayed, and compensating for the mura in the main cell and the sub cell according to the mura compensation data.

In some embodiments, the pixel offset amount is determined based on an offset distance measured after the main cell is fitted with the sub cell and a size of a single pixel in the main cell or the sub cell.

In some embodiments, the offset distance is determined according to an alignment gap of at least one pair of alignment marks arranged in the main cell and the sub cell, respectively, after the main cell is fitted with the sub cell.

In some embodiments, when there are multiple pairs of alignment marks is located in the main cell and the sub cell, the offset distance is an average offset distance determined by the multiple pairs of alignment marks.

In some embodiments, data displayed by pixels in the first display area and the second display area that are orthogonally projected outside the actual display area is black.

In some embodiments, the mura compensation data is obtained by adjusting, according to the pixel offset amount, at least one of the first display area and the second display area.

In some embodiments, at least one of the main cell and the sub cell includes auxiliary pixels, the auxiliary pixels are arranged around a display area of the corresponding cell, and the actual display area is either the first display area or the second display area.

In some embodiments, in a condition that the actual display area is the first display area, the control plate is further configured to reset an actual display area of the sub cell based on a size of the first display area and the pixel offset amount, such that pixels, orthographic projections of which are in the first display area, of the sub cell are used as pixels in the actual display area of the sub cell.

In some embodiments, in a condition that the actual display area is the second display area, the control plate is further configured to reset an actual display area of the main cell based on a size of the second display area and the pixel offset amount, such that pixels, orthographic projections of which are in the second display area, of the main cell are used as pixels in the actual display area of the main cell.

In some embodiments, the control plate is further configured to control the sub cell to blur a location corresponding to a boundary appearing in the actual display area.

In some embodiments, the pixel offset amount includes a first sub-pixel offset amount along a first direction and a second sub-pixel offset amount along a second direction; wherein the first direction intersects the second direction.

In some embodiments, the first sub-pixel offset amount is a quotient of an offset distance of the main cell and the sub cell in the first direction divided by a length of a single pixel in the first direction.

In some embodiments, the second sub-pixel offset amount is a quotient of an offset distance of the main cell and the sub cell in the second direction divided by a length of a single pixel in the second direction.

In some embodiments, when the first sub-pixel offset amount or the second sub-pixel offset amount is less than a set threshold, data of pixels at an edge of the actual display area in the BD cell is displayed directly; when the first sub-pixel offset amount or the second sub-offset amount is greater than or equal to the set threshold, data of pixels at the edge of the actual display area in the BD cell is displayed after being processed by edge blurring or gradient insertion.

In a second aspect, an embodiment of the disclosure provides a manufacturing method of the BD cell display panel according to the first aspect, including: setting a first alignment mark on a non-display area of the main cell and a second alignment mark opposite to the first alignment mark on a same location on a non-display area of the sub cell, wherein the first alignment mark and the second alignment mark are aligned to form a complete mark; fitting the main cell and the sub cell and collecting an offset distance of the first alignment mark relative to the second alignment mark; calculating the pixel offset amount based on the offset distance and a size of a single pixel in the main cell or the sub cell, and storing the pixel offset amount; during an optical demura adjusting and testing phase, obtain the actual display area of the BD cell display panel by adjusting at least one of the first display area of the main cell and the second display area of the sub cell according to the pixel offset amount; and acquiring mura data of the actual display area and determining mura compensation data according to the mura data and data displayed in the actual display area and storing the mura compensation data.

In a third aspect, an embodiment of the disclosure provides a driving method of the BD cell display panel according to the first aspect, including: reading the pixel offset amount and the mura compensation data stored in the XPCBA; determining actual display areas of the main cell and the sub cell according to the pixel offset amount; and compensating the actual display areas of the main cell and the sub cell, respectively, according to the mura compensation data, obtaining and displaying compensated images to be displayed corresponding to the main cell and the sub cell.

In a fourth aspect, an embodiment of the disclosure provides a BD cell display device including the BD cell display panel as described in the first aspect.

