FIELD OF THE TECHNOLOGY

At least some embodiments disclosed herein relate generally to semiconductor devices and, in particular, to improving the security of Flash memory devices.

BACKGROUND

A Flash memory device stores data in an array of cells, each cell comprising one or more transistor elements storing electrical charge representing bits of the data. The underlying physical properties of the transistor cause each cell to support a fixed number, or range, of operations affecting the contents of the cell. The number of times a memory cell can be programmed to or erased before malfunctioning is referred to as the endurance of a memory cell.

To improve the lifespan of a Flash memory device, these devices generally utilize wear leveling to “spread” program/erase (P/E) cycles across all cells. Specifically, wear leveling routines implemented by Flash memory controllers arrange data so that erasures and re-writes are distributed evenly across the memory cells. Controllers implement this re-arranging by distributing physical block address (PBA) values allocated for logical block address (LBA) values. As a result, each memory cell is theoretically programmed and erased evenly, and no single cell fails faster than another.

Despite the use of wear leveling routines, memory devices such as NAND Flash devices are still subject to expedited endurance failures due to malicious or poorly written software that rapidly “uses up” a memory array's P/E cycles.

