FIELD OF THE DISCLOSURE

The present disclosure generally relates to the field of semiconductor fabrication technology and, more particularly, relates to methods for fabricating semiconductor devices.

BACKGROUND

The major semiconductor devices for integrated circuits (ICs), especially in very-large scale integrated (VLSI) circuits, include metal-oxide-semiconductor field-effect transistors (MOSFETs). With the continuous development of IC manufacturing technology, the technical nodes of semiconductor devices continue to decrease, and the geometrical dimensions of semiconductor devices become smaller and smaller following the Moore's law. When the reduction of the dimensions of semiconductor devices reaches a certain level, various secondary effects due to approaching to the physical limits of semiconductor devices begin to emerge, and thus further scaling down the feature size of semiconductor devices becomes more and more difficult. Among all the problems in the field of semiconductor manufacturing, the most challenging one is to solve the large leakage current issue in semiconductor devices. Specifically, a large leakage current in a semiconductor device is mainly caused by the continuous decrease in the thickness of the conventional dielectric layer in the semiconductor devices.

Conventional solutions include use of a high-k material to replace the commonly-used SiO2as the gate dielectric material and also use a metal material as the gate electrode material to avoid Fermi level pinning between the high-k material and the conventional gate electrode material and also avoid boron penetration. Such a gate structure using a high-k material to form the gate dielectric layer and a metal material to form the gate electrode is known as a high-k metal gate (HKMG). The introduction of the HKMG reduces the leakage current in semiconductor structures.

Although the introduction of the HKMG may have improved the electrical performance of semiconductor devices to a certain extent, the electrical performance of existing semiconductor devices may still need to be improved. The disclosed semiconductor structures and fabrication methods thereof are directed to solve one or more problems set forth above and other problems in the art.

BRIEF SUMMARY OF THE DISCLOSURE

One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a base substrate. The base substrate includes an N-type metal-oxide-semiconductor (NMOS) region and a P-type metal-oxide-semiconductor (PMOS) region adjacent to the NMOS region. The PMOS region includes a first P-type region adjacent to the NMOS region and a second P-type region adjacent to the first P-type region. An N-type device is formed in the NMOS region, and a P-type device is formed in the PMOS region. The semiconductor device also includes an interlayer dielectric layer formed on the base substrate, a gate structure formed through the interlayer dielectric layer and including an N-type region gate structure formed on the base substrate in the NMOS region, a first gate structure formed on the substrate in the first P-type region and connected to the N-type region gate structure, and a second gate structure formed on the substrate in the second P-type region and connected to the first gate structure. The direction from the N-type region gate structure to the second gate structure is an extending direction of the gate structure, and along a direction perpendicular to the extending direction of the gate structure, the width of the first gate structure is larger than the width of the second gate structure.

Another aspect of the present disclosure provides a method for fabricating a semiconductor device. The method includes forming an interlayer dielectric layer on a base substrate. The base substrate includes an NMOS region and a PMOS region adjacent to the NMOS region. The PMOS region includes a first P-type region adjacent to the NMOS region and a second P-type region adjacent to the first P-type region. The NMOS region is used to form an N-type device, and the PMOS region is used to form a P-type device. The method also includes forming an N-type region opening in the NMOS region through the interlayer dielectric layer, a first opening in the first P-type region through the interlayer dielectric layer and connected to the N-type region opening, and a second opening in the second P-type region through the interlayer dielectric layer and connected to the first P-type opening. The direction from the N-type region opening to the second opening is an extending direction of a subsequently-formed gate structure, and along a direction perpendicular to the extending direction of the gate structure, the width of the first opening is larger than the width of the second opening.

Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.

