BACKGROUND

In the semiconductor integrated circuit (IC) industry, there is a continuing demand for smaller device dimensions and higher circuit packing densities. This demand has driven the semiconductor industry to develop new materials and complex processes. For example, when a feature (e.g., a gate/drain/source feature of a transistor, a horizontal interconnect line, or a vertical via, etc.) is to be formed on a wafer, the wafer typically goes through a production line which comprises multiple processing stations typically using different process tools to perform various operations such as cleaning, photolithography, dielectric deposition, dry/wet etching, and metal deposition, for example.

Maintaining flatness of the semiconductor wafer throughout the various process steps prevents defects and improves manufacturing yield. A high degree of non-flatness, i.e., a warping or warpage of semiconductor wafers, can result in non-uniformity features along the surface of the semiconductor wafers during the semiconductor manufacturing processes. For example, the warping of semiconductor wafers during exposure can cause non-uniform exposure due to the differences in positions of the surface relative to the focal plane of the exposure system. For another example, the warping of semiconductor wafers during etching can cause non-uniform etching. Therefore, there exists a need to develop a method to increase the degree of the flatness of semiconductor wafers for quality-control purposes in order to correct warping of semiconductors and to improve manufacturing yield.

