FIELD

Embodiments described herein relate generally to a method for manufacturing a semiconductor memory device and a semiconductor memory device.

BACKGROUND

A memory device having a three-dimensional structure is proposed. In the memory device, a memory hole is formed in a stacked body having a plurality of electrode layers functioning as control gates in memory cells stacked in the stacked body with insulating layers interposed between the electrode layers, and a silicon body serving as a channel is provided on a sidewall of the memory hole with a charge storage film interposed between the sidewall and the silicon body.

In a method for manufacturing a memory cell array having such a three-dimensional structure, a technique for forming holes and grooves in the stacked body having different kinds of materials alternately stacked therein is required. However, when the number of electrode layers stacked increases, particularly, with an increase in storage capacity, and aspect ratios of the holes and the grooves increase, the degree of processing difficulty becomes larger, and further technology development is required.

