CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims the benefit of priority to Taiwan Patent Application No. 109139301, filed on Nov. 11, 2020. The entire content of the above identified application is incorporated herein by reference.

Some references, which may include patents, patent applications and various publications, can be cited and discussed in the description of this disclosure. The citation and/or discussion of such references is provided merely to clarify the description of the present disclosure and is not an admission that any such reference is “prior art” to the disclosure described herein. All references cited and discussed in this specification are incorporated herein by reference in their entireties and to the same extent as if each reference was individually incorporated by reference.

FIELD OF THE DISCLOSURE

The present disclosure relates to a multi-channel timing calibration device and method, and more particularly to a multi-channel timing calibration device and a method applicable thereto, which are applicable on channels of a massive level number and capable of effectively calibrating timing difference among each of the channels through a single calibration device.

BACKGROUND OF THE DISCLOSURE

Referring toFIG.1, currently, regarding the transmission of multi-channel signals, due to respective differences among components, differences among timings of the channels occur. As shown inFIG.1, on the left side ofFIG.1, it is demonstrated that, under a comparison between each of channels1to4and a reference standard, respectively, the respective timing differences exist among the channels. The arrow indicates that after a timing calibration, a timing diagram as shown on the right side ofFIG.1can be expected, i.e., the timing of each of the channels are consistent, and the timing of each of the channels from channel1to channel4are synchronized without deviations. Furthermore, referring toFIG.2, a basic circuit structure having a single channel is provided, the basic circuit structure includes a driving data, the driving data is connected to a delayer and then connected to a driver, and an output end of the driver is a terminal of the channel. The terminal of the channel is then feedback connected to an input end of a comparator, and another input end of the comparator is connected to a reference voltage. Afterwards, the comparator outputs a comparison data as a reference data for comparing the timing differences.

As shown in the circuit structure ofFIG.2, since there are differences of characteristics of the drivers and the comparators, differences of length of the circuit, etc., the timing differences of timing comparison between multiple channels exist. However, when differences of the timings of the channels occur, as shown in the timing diagram on the left side ofFIG.1, the timing differences cannot produce aligned waveforms at the terminal of the channel, and a time difference also exists between the terminal of the channel and the comparison data of the comparator. Currently, a conventional solution is to adopt the “short-circuit device interface panel”. The conventional structure that adopts the short-circuit device interface panel calibrates a path of the comparator and then calibrates a path of the driver. However, as shown inFIG.3, when a number of the channels is large or of a massive level, a calibration method is usually required to further include a second or even a third device interface panel for further calibration. In order to apply the conventional technology inFIG.3to a condition with a large number of the channels, the device interface panel is arranged to include two calibration panels, i.e., the device interface panel1and the device interface panel2(the device interface panel is also known as the calibration panel). Convergent points on the right side of the device interface panel1and a convergent point on the right side of the device interface panel2are both regarded as signal sources. However, the conventional technology disclosed inFIG.3requires two calibration panels, i.e., two circuit boards to perform the multi-channel timing calibration. Furthermore, when more channels are required for input, additional circuit boards must be added. In this way, not only is the calibration complicated and the cost increased, the calibration efficiency also decreases.

SUMMARY OF THE DISCLOSURE

In response to the above-referenced technical inadequacies, the present disclosure provides a multi-channel timing calibration device and a method applicable thereto, which are applicable on channels of a massive level number and capable of effectively detecting and then calibrating the timing differences among each of the channels through a single calibration device (i.e., a single calibration panel), such that timing of the terminal have consistent and aligned waveforms, and that the calibration of the timing differences is accurately performed. Therefore, time differences are prevented from occurring, and using only a single circuit board significantly reduces the cost.

In one aspect, the present disclosure provides a multi-channel timing calibration device including a plurality of channel inputs, at least one relay switch, at least one comparator, at least one first multiplexer, and a time measurement chip. A timing signal is loaded in a channel of each of the channel inputs. An input end of the at least one relay switch is connected to the channel inputs. A first input end of the at least one comparator is connected to an output end of the at least one relay switch, a second input end of the at least one comparator is connected to a reference voltage, an output end of the at least one comparator outputs a first channel group. The at least one first multiplexer includes a plurality of input ends and an output end. One of the input ends of the at least one first multiplexer is connected to the first channel group. The input ends of the at least one first multiplexer are further connected to a plurality of channel groups. The output end of the at least one first multiplexer is channel groups1-8. The time measurement chip includes a synchronizing signal input end and at least one event end, the at least one event end is connected to the channel groups1-8, and the synchronizing signal input end is connected to a reference signal. The time measurement chip calculates a timing difference of each of the channels of each of the channel inputs as a basis for delay of the timing signals.

These and other aspects of the present disclosure will become apparent from the following description of the embodiment taken in conjunction with the following drawings and their captions, although variations and modifications therein can be affected without departing from the spirit and scope of the novel concepts of the disclosure.

