CROSS REFERENCE TO RELATED APPLICATIONS

This application is a National Stage of International Application No. PCT/JP2019/013142 filed on Mar. 27, 2019, claiming priority based on Japanese Patent Application No. 2018-120436 filed on Jun. 26, 2018.

TECHNICAL FIELD

The present invention relates to methods for manufacturing semiconductor devices such as so-called power semiconductor devices.

BACKGROUND ART

In some semiconductor device productions, a semiconductor chip is die-bonded to a supporting substrate such as a lead frame or an insulated substrate (insulated circuit board) while establishing and keeping electrical connection with the supporting substrate. Known examples of this technique include a technique of forming a Au—Si eutectic alloy layer between the supporting substrate and the chip to actually provide a bonding state; and a technique of using a bonding material such as solder, or a resin containing conductive particles.

Power semiconductor devices, which assume power supply and control, have become remarkably widespread. Many of such power semiconductor devices output large heat due to the passage of large current during operation. The power semiconductor device productions therefore require a technique that can actually provide a highly reliable bonding state even in a high-temperature operation, in die-bonding of semiconductor chips onto a supporting substrate while allowing the semiconductor chips to establish and keep electrical connection with the supporting substrate. In particular, this requirement is significant in power semiconductor devices that employ SiC or GaP as a semiconductor material and are to operate at high temperatures. To meet the requirement with electrical connection, a proposed die bonding technique employs a material for sinter bonding (sinter-bonding material) containing, for example, sinterable particles and a solvent (vehicle).

In such die bonding using a sinter-bonding material containing sinterable particles, initially, a semiconductor chip is placed on a predetermined chip-mounting area of a supporting substrate, through the sinter-bonding material under predetermined temperature-load conditions. Then, between the supporting substrate and the semiconductor chip over the supporting substrate, a heating process operates under predetermined temperature-pressurization conditions so that the solvent in the sinter-bonding material undergoes, for example, volatilization and the sintering proceeds between the sinterable particles. This forms a sintered layer between the supporting substrate and the semiconductor chip and allows the semiconductor chip to electrically connect with, and mechanically bond to, the supporting substrate. The technique as above is taught typically by Patent Literature (PTL) 1 and PTL 2 as follows.

CITATION LIST

Patent Literature

PTL 1: PCI International Publication Number 902008/065728

PTL 2: Japanese Unexamined Patent Application Publication (JP-A) No. 2013-09580

SUMMARY OF INVENTION

Technical Problem

Some conventional semiconductor device manufacturing processes using die bonding through sinter bonding may perform coating of semiconductor chips with a pasty composition containing sinterable particles on an individual chip basis. This technique, however, is inefficient.

Another possible technique for use in semiconductor device manufacturing processes including die bonding through sinter bonding is the technique of laminating a sheet of a sinter-bonding material containing sinterable particles onto a semiconductor wafer on which semiconductor elements have been built, and then dicing (singularizing) the semiconductor wafer with the sheet by blade dicing. This technique, however, may suffer from large losses of the sinter-bonding material in some yields of the elements to be built in the semiconductor wafer. For example, manufacture of power semiconductor devices using SiC or GaN as a semiconductor material may suffer from insufficiently high yields of semiconductor elements to be built in the wafer made of the semiconductor material. In this case, the technique of laminating the sinter-bonding material sheet onto the semiconductor wafer before dicing into semiconductor chips suffers from relatively large losses of the sinter-bonding material. This is because the sinter-bonding material is supplied not only to non-defective chips, but also to defective chips. With a decreasing yield of elements to be built in a semiconductor wafer, losses of the sinter-bonding material tend to increase.

The present invention has been made under these circumstances and has an object to provide a manufacturing method for a semiconductor device including semiconductor chips in sinter-bonded areas, which method is suitable for efficiently supplying a sinter-bonding material to the semiconductor chips while reducing losses of the sinter-bonding material.

Solution to Problem

The present invention provides, in a first aspect, a semiconductor device manufacturing method that includes an arrangement step, a transfer step, a picking-up step, a temporary securing step, and a sinter bonding step as described below. The method according to the aspect is suitable for manufacturing power semiconductor devices and other semiconductor devices including semiconductor chips in sinter-bonded areas.

In the arrangement step, semiconductor chips are arranged on an adhesive face of a processing tape. Spacing between adjacent semiconductor chips is typically 50 to 2000 μm, preferably 50 to 1000 μm, and more preferably 50 to 700 μm, while the spacing may be set depending typically on the viscosity and/or the thickness of a sinter-bonding sheet for use in the manufacturing method according to the aspect.

In the transfer step, initially, a sheet assembly is laminated onto the semiconductor chips on the processing tape through compression bonding, where the sheet assembly has a multilayer structure including a base and a sinter-bonding sheet and is laminated so that the sinter-bonding sheet faces the semiconductor chips. Preferably, the sinter-bonding sheet contains a binder component, and sinterable particles containing a conductive metal. Next, the base is removed from the sinter-bonding sheet while leaving the sinter-bonding sheet on the semiconductor chips.

In the picking-up step, each semiconductor chip on the processing tape is picked up together with a portion of the sinter-bonding sheet adhering to the semiconductor chip, to give sinter-bonding material layer-associated semiconductor chips. When the step of dividing the sinter-bonding sheet into pieces is not performed before the picking-up step, the picking-up step operates to divide the sinter-bonding sheet into pieces each forming a sinter-bonding material layer on each semiconductor chip.

In the temporary securing step, the sinter-bonding material laver-associated semiconductor chips are compression-bonded and temporarily secured through the sinter-bonding material layer to a substrate.

In the sinter bonding step, the sinter-bonding material layers lying between the temporarily secured semiconductor chips and the substrate are converted, through a heating process, into sintered layers, to sinter-bond the semiconductor chips to the substrate.

The semiconductor device manufacturing method according to the aspect includes the arrangement step as above. In the arrangement step, known good dies (KGDs) can be selected from among produced semiconductor chips and arranged on the processing tape, where the known good dies are chips that are acknowledged as non-defective chips through inspections after production process. The manufacturing method according to the aspect therefore enables batchwise transfer (transfer in one operation) of the sinter-bonding sheet serving as a sinter-bonding material to KGDs (semiconductor chips) alone in the transfer step by arranging KGDs alone as semiconductor chips on a processing tape and subjecting this processing tape bearing the KGDs alone to the transfer step. The manufacturing method according to the aspect as above is suitable for eliminating or minimizing supply of a sinter-bonding material to semiconductor chips that are acknowledged as defective ones, and suitable for reducing losses of the sinter-bonding material in batchwise supply of the sinter-bonding material to semiconductor chips.

The transfer step of the manufacturing method according to the aspect includes laminating the sinter-bonding sheet (sinter-bonding material) side of the sheet assembly onto the semiconductor chips on the processing tape, and removing the base of the sheet assembly while leaving the sinter-bonding sheet on the processing tape or on the semiconductor chips, as described above. The configuration as above is suitable for efficient batchwise supply of a sinter-bonding material to each of semiconductor chips.

In addition, the manufacturing method according to the aspect performs the arrangement step at a short chip-to-chip spacing of the semiconductor chips to be arranged on the processing tape, namely, at a short spacing between adjacent semiconductor chips, so as to leave the sinter-bonding sheet on the semiconductor chips upon removal of the base in the transfer step. The chip-to-chip spacing is typically 50 to 2000 μm, preferably 50 to 1000 μm, and more preferably 50 to 700 μm, as described above. Assume that the step of laminating a sinter-bonding sheet side of a sheet assembly having a multilayer structure including a base and the sinter-bonding sheet onto chips on a processing tape, and subsequently removing the base of the sheet assembly is performed at an excessively long chip-to-chip spacing. In this case, a portion or the sinter-bonding sheet is removed as being associated with the sheet assembly base upon removal of the base. Such removed portions of the sinter-bonding sheet lead to losses of the sinter-bonding material. In contrast, with the manufacturing method according to the embodiment, the chip-to-chip spacing of the chips C to be arranged on the processing tape in the arrangement step is set to such an extent as to avoid the removal of the sinter-bonding sheet in the transfer step as above, while the chip-to-chip spacing may be determined according typically to the viscosity and/or the thickness of the sinter-bonding sheet to be used. The configuration as above is suitable for reducing losses of the sinter-bonding material.

As described above, the semiconductor device manufacturing method according to the present invention is suitable for efficiently supplying a sinter-bonding material to each of semiconductor chips while reducing loses of the sinter-bonding material.

The manufacturing method according to the aspect preferably further includes an expansion step between the transfer step and the picking-up step. In the expansion step, the processing tape that holds the semiconductor chips adhering to one sinter-bonding sheet temporarily expands, to cleave the sinter-bonding sheet on the semiconductor chips into pieces each forming a sinter-bonding material layer on each semiconductor chip. The configuration as above is preferred in the picking-up step for appropriately picking up a target semiconductor chip with a sinter-bonding material layer which has already been separated from an adjacent sinter-bonding material layer or layers.

The manufacturing method according to the aspect preferably further includes a blade dicing step between the transfer step and the picking-up step. In the blade dicing step, blade dicing is performed on the sinter-bonding sheet adhering to the semiconductor chips held by the processing tape, to divide the sinter-bonding sheet into pieces each forming a sinter-bonding material layer on each semiconductor chip. The configuration as above is preferred in the picking-up step for appropriately picking up a target semiconductor chip with a sinter-bonding material layer which has already been separated from an adjacent sinter-bonding material layer or layers.

The manufacturing method according to the aspect preferably further includes a bending step between the transfer step and the picking-up step. In the bending step, the processing tape that holds the semiconductor chips adhering to one sinter-bonding sheet is bent, to cleave the sinter-bonding sheet on the semiconductor chips into pieces each forming a sinter-bonding material layer on each semiconductor chip. The “bending” of the processing tape includes “bending” and “curving” of the processing tape. The configuration as above is preferred in the picking-up step for appropriately picking up a target semiconductor chip with a sinter-bonding material layer which has already been separated from an adjacent sinter-bonding material layer or layers.

The sintered layers formed in the sinter bonding step each have a thickness of preferably from 60% to 140%, more preferably from 80% to 120%, and still more preferably from 90% to 110%, of the average thickness of the sintered layers. With increasing uniformity in the thicknesses of the sintered layers, the sintered layers more tend to provide high bonding reliability. The sintered layers formed in the sinter bonding step have an average thickness of preferably 5 to 200 μm, and more preferably 10 to 150 μm. The configuration as above is preferred for relaxing internal stress in the sintered layers, where the internal stress is caused by heat stress, to surely provide sufficient thermal shock reliability, and for reducing not only sinter bonding cost, but also semiconductor device manufacturing cost.

The sinterable particles in the sinter-bonding sheet for use in the manufacturing method according to the aspect preferably include at least one selected from the group consisting of silver, copper, silver oxide, and copper oxide. The configuration as above is advantageous for the formation of firm, strong sintered layers between the substrate and the semiconductor chips which are sinter-bonded to each other. The binder component in the sinter-bonding sheet is preferably a thermally decomposable polymer binder.

