BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various implementations of the disclosure.

FIG. 1illustrates an example device with freeze logic in accordance with some embodiments.

FIG. 2illustrates an example freeze logic of a device in accordance with some embodiments of the present disclosure.

FIG. 3is a flow diagram of an example method to generate output signals with dual rails of freeze logic in accordance with some embodiments of the present disclosure.

FIG. 4illustrates an example implementation of freeze logic in accordance with some embodiments.

FIG. 5Aillustrates an example implementation of freeze logic based on an exclusive-or (XOR) gate functionality in accordance with some embodiments.

FIG. 5Billustrates a truth table corresponding to the operation of an example implementation of freeze logic based on the XOR gate functionality in accordance with some embodiments.

FIG. 6Aillustrates another example implementation of freeze logic based on a negative AND (NAND) gate functionality in accordance with some embodiments.

FIG. 6Billustrates a truth table corresponding to the operation of an example implementation of freeze logic based on the NAND gate functionality in accordance with some embodiments.

FIG. 7illustrates another example implementation of freeze logic based on the NAND gate functionality in accordance with some embodiments of the present disclosure.

FIG. 8illustrates a block diagram of an embodiment of a computer system in which some embodiments of the disclosure may operate.

