TECHNICAL FIELD

The disclosure generally relates to artificial reality systems, such as augmented reality, mixed reality, and/or virtual reality systems.

BACKGROUND

Artificial reality systems are becoming increasingly ubiquitous with applications in many fields such as computer gaming, health and safety, industrial, and education. As a few examples, artificial reality systems are being incorporated into mobile devices, gaming consoles, personal computers, movie theaters, and theme parks. In general, artificial reality is a form of reality that has been adjusted in some manner before presentation to a user, which may include, e.g., a virtual reality, an augmented reality, a mixed reality, a hybrid reality, or some combination and/or derivatives thereof.

Typical artificial reality systems include one or more devices for rendering and displaying content to users. As one example, an artificial reality system may incorporate a head-mounted display (HMD) worn by a user and configured to output artificial reality content to the user. The artificial reality content may entirely comprise content that is generated by the system or may include generated content combined with captured content (e.g., real-world video and/or images). During operation, the user typically interacts with the artificial reality system to select content, launch applications, configure the system and, in general, experience artificial reality environments.

SUMMARY

In general, the disclosure describes techniques for inter-processor communication (IPC) mechanisms that are shared among computer processors. In particular, the application will describe one or more System-on-Chip (SoC) integrated circuits comprising a plurality of processors, a network-on-chip (NoC), and an IPC unit. Each of the processors may use registers of the IPC unit to (1) initiate an interrupt request for a target processor or (2) to acquire a lock for a shared resource (e.g., memory, I/O device).

In one example, the IPC unit includes an address map comprising a plurality of doorbell registers, each of the doorbell registers corresponding to a different pair of the processors. Sets of doorbell registers may be associated with different target processors and associated with interrupt request (IRQ) lines for the processors. A security processor configures the pair of processors (e.g., source processor and target processor) for each doorbell register, at boot time for instance. To generate an interrupt to a target processor, a source processor sends a memory access request including a hardware identifier (HWID) of the source processor, via the NoC, to write a value (e.g., ‘1’) to the doorbell register that corresponds to the source processor, target processor pair. The IPC unit determines whether the HWID of the source processor included in the memory access request matches the HWID stored in the doorbell register at the memory location specified in the memory access request. If the HWIDs of the source processor and the doorbell register do not match, the IPC unit rejects the memory access request and an error is returned. The IPC unit may log the error, e.g., to the security processor. If the HWIDs of the source processor and the doorbell register match, the IPC unit writes the value to the doorbell register. Writing the value to the doorbell register triggers an interrupt, e.g., raising an interrupt request (IRQ) input, to the target processor. Once the target processor completes processing of the interrupt request, the target processor sends a second memory access request to write a value (e.g., ‘0’) to the same doorbell register to clear the doorbell register for another interrupt request. In some examples, only the source processor can write a value to the doorbell register for a source processor, target processor pair, and only the target processor can clear the value from that doorbell register.

In another example, the above-described IPC unit includes a plurality of hardware mutual exclusion (mutexes) registers, each used to prevent simultaneous access to a corresponding shared resource (e.g., memory, I/O devices). To use a resource, a first process running on a first processor must acquire ownership of a mutex object (referred to herein as simply a “mutex”) corresponding to that resource. To acquire ownership of the mutex, the first process attempts to write, using a memory access request via the NoC, a value (e.g., ‘1’) and its software ID (SWID) to the mutex register. The first processor inserts its HWID into the memory access request. If the acquisition succeeds (e.g., because no other process owns the mutex), the IPC unit stores the value, the SWID of the first process, and the HWID of the first processor in the mutex register. If the acquisition fails (e.g., because another process owns the mutex), no error will be returned. The first process will then read the data stored in the mutex register. For example, if an SWID of another process is stored in the mutex register, then the first process does not own the mutex and cannot use the resource. If the SWID of the first process is stored in the mutex register, the first process owns the mutex and can use the resource. To release the mutex (and the resource), the first process issues, via the NoC, a memory access request to write a value (e.g., ‘0’) to the mutex register to clear it. In some examples, only the process that owns the mutex object can clear it (e.g., the HWID and SWID of the write request must match what is stored in the mutex register). If a processor having an HWID attempts to clear a mutex register storing a different HWID, the IPC unit may register an error with the security processor.

In one example, an artificial reality system includes a plurality of processors. The artificial reality system also includes an inter-processor communication (IPC) unit comprising a register, wherein the IPC unit is configured to: receive a memory access request from a first processor of the processors, wherein the memory access request includes information indicative of a hardware identifier (HWID) associated with the first processor; determine whether the HWID associated with the first processor matches an HWID for the register of the IPC unit; and permit, based on determining that the HWID associated with the first processor matches the HWID for the register of the IPC unit, the memory access request to indicate a communication from the first processor to at least one other processor.

In another example, a method for inter-processor communication (IPC) includes receiving a memory access request from a first processor of a plurality of processors, wherein the memory access request includes information indicative of a hardware identifier (HWID) associated with the first processor. The method also includes determining whether the HWID associated with the first processor matches an HWID for the register of the IPC unit. The method further includes permitting, based on determining that the HWID associated with the first processor matches the HWID for the register of the IPC unit, the memory access request to indicate a communication from the first processor to at least one other processor.

In yet another example, a computer-readable storage medium includes instructions that, when executed, configure processing circuitry to: receive a memory access request from a first processor of a plurality of processors, wherein the memory access request includes information indicative of a hardware identifier (HWID) associated with the first processor; determine whether the HWID associated with the first processor matches an HWID for the register of the IPC unit; and permit, based on determining that the HWID associated with the first processor matches the HWID for the register of the IPC unit, the memory access request to indicate a communication from the first processor to at least one other processor.

The details of one or more examples of the techniques described herein are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the techniques described herein will be apparent from the description and drawings, and from the claims.

