CROSS REFERENCE TO THE RELATED APPLICATIONS

This application is based upon and claims priority to Chinese Patent Application No. 202110436194.X filed on Apr. 22, 2021, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present invention belongs to a power semiconductor device field and more particularly, relates to a power semiconductor device for improving hot carrier injection.

BACKGROUND

Power semiconductors are widely applied in power integrated circuits, especially DC-DC, AC-DC and other driving circuits, wherein a power LDMOS (Laterally-Diffused Metal-Oxide Semiconductor) attracts attention due to its feature of easy integration. In the developing process of the LDMOS, a plurality of innovative techniques aim to improve the LDMOS's figure of merit (FOM)=BV2/Ron-sp(FOM, Figure Of Merit). There is a plurality of measures to improve the trade-off between BV and Ron-sp: Super Junction (SJ), REduce SURface Field (RESURF), Local Oxidation of Silicon (LOCOS), Shallow Trench Isolation (STI) and Silicon On Insulator (SOI) etc. Structural types of the LDMOS have their respective features. The LDMOS using a dielectric trench is popular due to the features of folding a drift region, reducing a size of a cell and easy integration.

A hot carrier injection effect refers to energy obtained by carriers inside a device under high electric field, the carriers having an effective temperature higher than lattice temperature of carriers in balance. Changes occur to a motion track of these carriers and these carriers have probability to injected into dielectric along a direction perpendicular to surface of the dielectric (for example an oxide layer), such as being captured by a trapped charge in an oxidized layer. The captured charge exists in a dielectric layer and has an effect on motion of normal carriers in a semiconductor. Such effect is irreversible, causing problems like decreasing ON-resistance of the device, and shifting threshold voltage. Meanwhile, problems like causing current of a substrate and increasing current of a gate are likely caused, thus affecting normal work of a circuit.

With the progress of technology, sizes becoming smaller and smaller, and decreases of the device channel length, the drift region length and a gate dielectric thickness enable increase of transverse electric field and longitudinal electric field inside the device at a certain rate. Under long-term operations of the device, when the differential of voltage applied to source-drain of a power LDMOS increases, the integral of the impact ionization coefficient at a depletion region will reach 1 and the avalanche breakdown occurs in the device, in which case numerous hot carriers appear, resulting in hot carrier injection effect. Due to presence of the dielectric trench at the drift region, electric field concentrates at a corner, such that hot carriers are more likely to be generated here. The harm caused by injection of hot carriers will affect long-term reliability of the device, further worsening properties of the device. What's more, when the device is applied to an environment with high-speed switch, high electric field and high magnetic field, the hot carrier injection effect will become more prominent.

Nowadays, the LDMOS device is developed with features of low ON-resistance, high blocking voltage and low gate-drain capacitance Cgd. In order to obtain low gate-drain capacitance Cgd, the common method of the power MOS mainly includes decreasing an overlapping area of a gate-drain region. According to the capacitance formula C=ε*S/d, it can be known that the gate-drain capacitance will decrease if the overlapping area S decreases. Another common method involves introducing a shield gate. The electric potential of the shield gate is connected to the ground, such that the shield gate performs the function of a Faraday cage, thereby shielding connection of electric potential between gate and drain and also improving the gate-drain capacitance Cgdto a certain extent. Some conventional LDMOS's structural defects having the dielectric trench are described below.

Some conventional LDMOS structures having dielectric trenches are shown inFIG. 1. A dielectric trench107exists in an LDMOS drift region102and paths of carriers between source and drain are folded. For LOCOS, the ON-resistance of a device of STI may be made smaller. However, it cannot be avoided that at the left and right sides of the dielectric trench107, when the differential of voltage applied to source-drain ends, the strength of the electric field inside the device increases to a certain value. In particular, due to the electric field concentration effects at a corner of the dielectric trench107, the value of the electric field is higher, thereby more easily to generate hot carriers. At the left side of the dielectric trench107, there is injection of hot electrons. At the right side of the dielectric trench107, there is injection of hot holes. Such hot carrier injection brings problems to long-term reliability of the device.

Some conventional LDMOS structures having a dielectric trench are shown inFIG. 2. By extending a first gate electrode114above a part of the drift region102, a second gate electrode141is embedded into the dielectric trench107, performing the function of the field plate. Under an ON situation, an accumulation layer is formed at one side of the drift region102close to high electric potential gate electrode. The design of the structure decreases ON-resistance. However, it also improves the hot carrier injection effect at the source electrode side of the dielectric trench at the same time. On the other hand, the extending of the first gate electrode114enables increase of the overlapping area of the gate electrode and the drift region102, resulting in increase of the gate-drain parasitic capacitance Cgdof the LDMOS device. In this case, leading to a series of problems such as slower switching speed and higher switching power etc.

Some conventional LDMOS structures having a dielectric trench are shown inFIG. 3. By introducing a Faraday cage113connected to a source end on the dielectric trench107, the function of the Faraday cage is performed, blocking connection of electric potential between gate and drain and decreasing gate-drain parasitic capacitance Cgdof the LDMOS device. However, the defect concerns that only decrease of switching loss is considered for such a design, without relieving the long-term reliability problem caused by injection of hot carriers into the dielectric trench.

Therefore, for the above problem, it is necessary to improve hot carrier injection caused by the dielectric trench in the LDMOS device and to simultaneously optimize switching loss caused by gate-drain parasitic capacitance Cgdto a certain extent. Specific embodiments of the present invention appear under such background.

SUMMARY

This invention provides a novel power LDMOS device having a dielectric trench. The device can be used to improve long-term reliability of the device caused by injection of hot carriers into the dielectric trench. In the dielectric trench of a LDMOS drift region, with introduction of high electric potential by inserting a drain electrode field plate, electric field force pointing to an outer side of the dielectric trench is applied to a hole, to thus impact motion track of a hole carrier. Meanwhile, the shield gate is placed inside the trench to not only provide the Faraday cage to lower gate-drain capacitance Cgd, but also introduce low electric potential region. Electric field force pointing to an outer side of the dielectric trench is applied to electrons, to thus impact motion track of an electron carrier. On the other hand, when the device is at an OFF state, the shield gate has the function to assist in depletion of drift region. Introduction of the drain field plate and the shield gate electrode is able to improve injection of holes and electrons at two sides of the dielectric trench to a certain extent especially at the corner. Meanwhile, in order to improve injection of hot carriers to the dielectric trench, collision of carriers against side walls of the dielectric trench can also be avoided by introducing deep electrodes to change motion track of carriers. On the basis of improving hot carrier injection, the present invention makes some improvements to parasitic effect. For example, embedding of the dielectric trench introduces JFET resistance locally. By increasing the doping concentration of this region, JFET effect will be improved and meanwhile ON-resistance on the current path will decrease.

In order to realize the above objectives of the present invention, the technical solution of the present invention is provided as follows:

The present invention provides a power semiconductor device for improving hot carrier injection, comprising a second doping type substrate101, a first doping type drift region102provided on the substrate101and a dielectric trench107on a surface of the drift region102;

wherein the dielectric trench107comprises a drain field plate115positioned at one side of the dielectric trench107close to a drain, and a shield gate electrode120entirely positioned between gate and drain and positioned at one side of the dielectric trench107close to a source electrode, a first oxide layer131is provided at one side of the shield gate electrode120close to the source electrode, a third oxide layer133is provided at the bottom of the shield gate electrode120, and a second oxide layer132is provided at one side of the drain field plate115close to the drain; the drain field plate115in the dielectric trench is connected to a drain electrode110, having a same electric potential; and the shield gate electrode120in the dielectric trench107is connected to a source electrode111, having a same low electric potential or ground connection;

the power semiconductor device comprises a first body region103of a second doping type on a surface of the drift region102, a drain region106of a first doping type, a second body region104of the second doping type and a source region105of the first doping type, the second body region104and the source region105being provided inside the first body region103; the gate dielectric108covers an upper surface of the first body region103and covers a part of upper surfaces the source region105and the drift region102, a first gate electrode114is provided on an upper surface of the gate dielectric108, the drain electrode110is provided on an upper surface of the drain region106, and the source electrode111is provided on upper surfaces of the second body region104and the source region105;

The gate dielectric108of the power semiconductor device is a gate oxide layer, and the first oxide layer131, the second oxide layer132and the third oxide layer133can be a gate oxide layer or a field oxide layer; and the material of the shield gate electrode120, the first gate electrode114and the drain field plate115can be metal or polysilicon.

As a preferred solution, a JFET region121is provided between the dielectric trench107and the first body region103, the JFET region is of a first doping type and a doping concentration of the JFET region121is higher than a doping concentration of the drift region102.

For the JFET region121provided between the dielectric trench107and the first body region103, the present invention further provides a preparation method, comprising the following steps of:

1) using a manner of ion implanting to form a drift region and a first body region successively;

2) using a first photomask to etch on a surface of the drift region to form a dielectric trench;

3) filling dielectric into the dielectric trench;

4) using a second photomask to etch at the dielectric trench two needed empty trenches, the two empty trenches being located at positions corresponding to electrodes needing to be deposited;

5) using a manner of thermal oxidation to generate, on a silicon surface, an oxide layer, comprising an additional oxide layer, a gate oxide layer, a first oxide layer, a second oxide layer and a third oxide layer;

6) using a depositing technique to form a shield gate electrode120, a drain field plate115and a first gate electrode114at positions of the two empty trenches' region and a position corresponding to a gate electrode;

7) using an ion implanting technique to respectively form a drain region106, a JFET region121, a source region105and a second body region104;

8) etching through holes and depositing electrodes above the drain region106, the source region105and the second body region104to form a drain electrode110and a source electrode111.

As a preferred solution, a second gate electrode141is provided under the shield gate electrode120; and one side of the first body region103close to the drain extends to the first oxide layer131. Channel length modulation effects are improved by introducing a vertical channel.

The present invention further provides a second type power semiconductor device for improving hot carrier injection, comprising a first doping type substrate101, a first doping type drift region102provided on the substrate101, and a dielectric trench107on a surface of the drift region102;

wherein the dielectric trench107comprises a drain field plate115positioned at one side of the dielectric trench107close to a drain and a second gate electrode120extending into the dielectric trench107and positioned at one side of the dielectric trench107close to a source electrode, a first oxide layer131is provided at one side of the second gate electrode141close to the source electrode, and a second oxide layer132is provided at one side of the drain field plate115close to the drain; the drain field plate115in the dielectric trench is connected to a drain electrode110, having a same electric potential;

the power semiconductor device comprises a first body region103) on a surface of the drift region102in which a second body region104and a source region105are provided, and a drain region106; a gate dielectric108covers an upper surface of the first body region103and covers a part of upper surfaces of the source region105and the drift region102, a first gate electrode114is provided on an upper surface of the gate dielectric108, a drain electrode110is provided on an upper surface of the drain region106, and a source electrode111is provided on upper surfaces of the second body region104and the source region105;

the gate dielectric108of the power semiconductor device is a gate oxide layer, and the first oxide layer131and the second oxide layer132can be a gate oxide layer or a field oxide layer; and the material of the shield gate electrode120, the first gate electrode114, the drain field plate115and the second gate electrode141can be metal or polysilicon.

As a preferred manner, a third oxide layer133is provided at the bottom of the shield gate electrode141. Thus ON-resistance of the device is lowered.

As a preferred manner, a shield gate electrode120is provided between the second gate electrode141and the third oxide layer133, the shield gate electrode120in the dielectric trench107is connected to the source electrode111, having a same low electric potential or ground connection. The third oxide layer133can be a gate oxide layer or a field oxide layer; and the material of the shield gate electrode120can be metal or polysilicon.

As a preferred manner, the dielectric trench107intersects the drain region106or a second drift region140is provided between the dielectric trench107and the drain region106, wherein the second drift region140is of a first doping type.

The present invention further provides a third type power semiconductor device for improving hot carrier injection, comprising a first doping type substrate101, a first doping type drift region102provided on the substrate101, and a dielectric trench107on a surface of the drift region102;

wherein the dielectric trench107comprises a shield gate electrode120; the shield gate electrode120is positioned at one side of the dielectric trench107close to a source electrode, a first oxide layer131is provided at one side of the shield gate electrode120close to the source electrode, and a third oxide layer133is provided at the bottom of the shield gate electrode120;

the power semiconductor device comprises a first body region103on a surface of the drift region102in which a second body region104and a source region105are provided; a gate dielectric108covers an upper surface of the first body region103and covers a part of upper surfaces of the source region105and the drift region102, a first gate electrode114is provided on an upper surface of the gate dielectric108, a drain electrode110is provided on an upper surface of the drain region106, and a source electrode111is provided on upper surfaces of the second body region104and the source region105;

a drain of the device comprises a deeply-embedded drain electrode129and a deep drain region130under the deeply-embedded drain electrode129, the deep drain region130contacting a position of the dielectric trench107close to a corner of the drain;

the gate dielectric108of the power semiconductor device is a gate oxide layer, and the first oxide layer131and the second oxide layer132can be a gate oxide layer or a field oxide layer; and the material of the shield gate electrode120and the first gate electrode114can be metal or polysilicon.

As a preferred manner, the material of the dielectric trench107and the gate dielectric108is silicon oxide or high dielectric constant material.

As a preferred manner, the first doping type is N-type doping and the second doping type is P-type doping; or the first doping type is P-type doping and the second doping type is N-type doping.

The present invention has the advantageous effects of: with introduction of the shield gate and the drain field plate, making electric potential existing inside the dielectric trench and introduced from the outside when the device is in a breakdown state so as to improve injections of hot electrons and hot holes into the dielectric trench in different directions, thus achieving long-term reliability of the device. The introduction of the shield gate can also lower the gate-drain parasitic capacitance Cgdand switching loss of the device. Meanwhile, a deeply-embedded drain electrode can also be used to perform the function of the drain field plate.

