BACKGROUND

NAND flash memory is one memory technology with granularity issues and latency issues that can constrain system performance. A conventional NAND flash memory device is typically characterized by programming and erasing latencies in the hundreds of microseconds, and little flexibility in the quantum of write read data and write data exchanged with memory. Thus, use of this type of memory is often characterized by substantial bus idle time and retrieval of excess data. Further, a program/erase (“P/E”) asymmetry in NAND flash memory can further complicate latency, because data cannot be written to a previously-used memory location until an impacted erase unit (“EU”) has been erased; in turn, an EU cannot be erased until all previously-written physical pages within that EU have been released, with still-active data being moved or scrapped as necessary. These and other maintenance operations, typically transparently managed by a memory controller, can result in delays occasioned by memory controller competition with host commands for memory bandwidth. Each of these issues is not necessarily unique to NAND flash memory and, to a lesser or greater extent, can affect different types of volatile and non-volatile memory.

To make more efficient use of memory, designers have increasingly turned to bus management techniques such as interleaving requests to multiple devices to improve bus utilization and to hide (or conceal) latency. Thus, for example, latency associated with a second memory access can be masked against the latency associated with a first, overlapping (parallel) memory access. With NAND flash memory in particular, multi-plane designs have emerged which permit accesses to data stored in parallel planes or arrays (typically two), but subject to certain addressing and/or timing restrictions. That is, because these devices typically use common input/output (IO) circuitry and address circuitry to handle requests, overlapping multi-plane access has traditionally been limited to situations where a common or base address is used for all planes.

Unfortunately, it is difficult to realize the benefits of multi-plane or multi-die architecture at an application or operating system level. That is to say, logical addresses typically arrive at the memory controller from the host as a stream of random accesses, and are sequentially assigned to first available physical space by the memory controller; as memory, particularly flash memory, is erased and recycled via read, write, wear leveling, garbage collection and other processes, sequential logical addresses become scattered throughout physical memory space. For multi-plane memory therefore, there is no practical mechanism for the host or memory controller to group related data in a manner geared for multi-plane access (i.e., there is no guarantee available physical addresses used for related data will be consistent with device multi-plane addressing restrictions). Thus, in practice, the benefits of multi-plane and multi-die capabilities tend to be restricted to multi-plane writes by a memory controller of coincidentally-related data uniquely for the purpose of bandwidth management, with read access by either the host and memory controller being inefficiently performed and largely restricted to independent, single page accesses. For both multi-die and multi-plane designs, as channel bandwidth continues to improve, the issues associated with a logical-to-physical translation later at the memory controller can be expected to create additional latency.

A need therefore exists for improvements that provide additional flexibility to systems and application designers. Ideally, such improvements would provide flexibility in storing and accessing multiple pages of data, for example, across multiple dies or planes. Applied to multi-plane memory, a need exists for techniques that permit effective use of multi-plane capabilities notwithstanding device IO and addressing restrictions. The present invention satisfies these needs and provides further, related advantages.

