BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an unified micro system with memory IC and logic IC, and particularly to an unified IC system and a related DRAM chip thereof that include high performance logic 3D-shaped transistors, such as fin-structured transistors or gate around-structured transistors.

2. Description of the Prior Art

An IC system for high performance computing or artificial intelligence (AI) system is conventionally composed of a plurality of DRAM chips and a logic chip. The logic chip now could be made in silicon die by using a 10-nanometers process node, or a 7-nanometers process node and toward a 5-nanometers process node. These process nodes basically follow the Moore's Law by device scaling design to increase 2 times of transistors in a specified area per each process node. But the key contribution to be able to follow the Moore's Law is due to the invention and execution of 3D transistor structures (e.g. gate around, Tri-gate or FINFET). The 3D shaped or structured transistor does deliver high performance, low leakage and high reliability, etc.

On the other hand the DRAM technology scaling was slowed down after 45 nanometer process node and the introduction of1xnm after the 25 nanometer process node takes much longer than the two years per process node which did happen in the DRAM history following the Moore's Law's prediction. A key reason is that the DRAM's using stacked capacitor structure which needs high temperature processing steps after the transistor structure has been formed and thus the transistor's source and drain junctions are hard to be controlled as shallow as the transistor scaling rules require. As a result, most DRAM technologies do not use the tri-gate transistor structure which has well been used in the Logic process for sub-20 nanometer process nodes and accelerates the necessary circuit-performance enhancement and achieves good leakage controllability and allows the power-supply voltage being scaled down from 1.2 Volts to 0.6-0.7 Volts. In addition, building up the stacked capacitor structure after the transistor formation really adds a lot of difficulties to use the Tri-gate or FINFET transistor structure. The ending result is that the DRAM scaling is getting harder to be scaled down below 15 nanometer and the sub-10 nanometer process node is not yet available.

When the Logic/SOC performance can be highly accelerated by sub-10 nanometer processing and design technologies, especially due to the use and improvement of the 3D Tri-gate transistor structures, the slowed-down DRAM technology migration makes the worse well-known Memory-Wall effect (actually DRAM-Wall) which reduces the data transfer rate between logic and memory. The data bandwidth and random access time are both getting a larger and larger performance gap: the conventional DRAM just cannot perform as a memory vehicle to provide or to store data to the Logic/SOC chip.

In order to solve the memory-wall problem, the DRAM technology development is led to a 3D-DRAM technology called high-bandwidth DRAM (HBM). However, in the HBM standard published by the Joint Electron Device Engineering Council (JEDEC), a supply voltage of the each DRAM chip is defined at 1.2V. However, a supply voltage of the tri-gate transistor used in the logic chip is at 0.6 to 0.7V. An incompatibility of the supply voltages between the each DRAM chip and the logic chip leads to difficulties in optimization of the energy efficiency and performance synchronization. Moreover, HBM uses 3D technologies of stacking multiple DRAMs (2, 4 or 8 dices) and each DRAM may have its capacity over 8 or 16 Gb and its IO paths wider than 1K and the total data rate using DDR3 can be over 128 GB/sec. The most difficult challenge is these 1K IOs need to be vertically connected by thousands of TSV (Through Silicon Via) connectors which challenges the final yield of HBM and thus its high cost in addition to very long manufacturing time. On the other hand, another solution of the memory-wall problem was also proposed to build up a DRAM cell with tri-gate access transistor as disclosed in U.S. Pat. No. 9,935,109, however, leakage issue for such a DRAM cell was not addressed therein.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides an unified micro system which includes a base memory IC and a logic IC. The base memory IC could be a DRAM chip which includes a plurality of DRAM cells (e.g. core area of DRAM) and a DRAM bridge area which may include part of or all peripheral circuits of DRAM chip, wherein each DRAM cell includes a first fin-structured transistor and a capacitor, and the DRAM bridge area includes a plurality of third fin-structured transistors and a plurality of DRAM input/output (I/O) pads. The logic chip is physically separated from the base DRAM chip and includes a plurality of second fin-structured transistors and a logic bridge area, wherein the logic bridge area includes a plurality of logic I/O pads, and the plurality of DRAM I/O pads are electrically coupled to the plurality of logic I/O pads.

An embodiment of the present invention provides an unified IC system. The unified IC system includes a base memory chip, a plurality of stacked memory chips, and a logic chip. The base memory chip includes a memory region and a bridge area, the memory region includes a plurality of memory cells, and the bridge area includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The plurality of stacked memory chips is positioned above the base memory chip. The logic chip includes a logic bridge area and a plurality of second transistors, the logic bridge includes a plurality of logic I/O pads, wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.

An embodiment of the present invention provides an unified IC system. The unified IC system includes a base DRAM chip and a logic chip. The base DRAM chip includes a plurality of DRAM cells and a DRAM bridge area. Each plurality of DRAM cells includes a first 3D shaped transistor and a capacitor, and the DRAM bridge area includes a plurality of DRAM input/output (I/O) pads and a plurality of third 3D shaped transistors. The logic chip is physically separated from the base DRAM chip and includes a plurality of second 3D shaped transistors and a logic bridge area, wherein the logic bridge area comprises a plurality of logic I/O pads, the plurality of DRAM I/O pads are electrically coupled to the plurality of logic I/O pads, and a structure of the third 3D shaped transistor is the same or substantially the same as that of the second 3D shaped transistor.

An embodiment of the present invention provides an unified IC system. The unified IC system includes a base DRAM chip and a logic chip. The base DRAM chip includes a first memory region, a second memory region, and a DRAM bridge area. The first memory region includes a first plurality of DRAM cells, and the second memory region includes a second plurality of DRAM cells, wherein each DRAM cell includes a first 3D shaped transistor and a first capacitor. The DRAM bridge area includes a plurality of DRAM I/O pads and a plurality of third 3D shaped transistors. The logic chip includes a plurality of second 3D shaped transistors and a logic bridge area including a plurality of logic I/O pads, wherein the plurality of DRAM I/O pads are electrically coupled to the plurality of logic I/O pads, the logic chip is physically separated from the DRAM chip, a structure of the third 3D shaped transistor is substantially the same as that of the second 3D shaped transistor, and the first memory region is not vertically separate from the second memory region.

An embodiment of the present invention provides an unified IC system. The unified IC system includes a base DRAM chip and a logic chip. The base DRAM chip includes at least a first memory region, the first memory region having a plurality of DRAM cells and each DRAM cell including a capacitor and a first transistor coupled to the capacitor, wherein the first memory region has row address interface and column address interface physically independent from the row address interface. The logic chip includes a plurality of second transistors, wherein a voltage level of an input signal of the first transistor is the same or substantially the same as that of the second transistor.

Therefore, the present invention provides a high bandwidth, low latency, low power architecture for an unified micro system with a memory IC and a logic IC. Compared to the prior art, the present invention could significantly improve the memory-wall problem.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

