BACKGROUND

The present disclosure relates to the processing of substrates. In particular, it provides a method of etching self-aligned contacts on substrates.

Substrate processing typically involves a series of manufacturing techniques related to the formation, patterning and removal of a number of layers of material on a substrate. As device linewidths continue to shrink, various individual processing steps require associated improvements. For example, as device sizes shrink, layer thicknesses shrink, and aspect ratios increase, the etch selectivity between one layer and another layer may need to increase accordingly. At times, as device criteria continue to shrink, improvements to an individual processing step may not be sufficient to meet the desired device criteria. Thus, the integration of the overall process flow of the individual process steps also may be modified to provide a repeatable, stable process flow which satisfies shrinking device criteria.

One process integration technique utilized to satisfy demanding design criteria is the formation of self-aligned structures. The use of such self-aligned structures allows the formation of structures that may be smaller than the normal lithography or etch tolerances and allows tighter layer-to-layer alignment tolerances. Thus, as is known in the art, a variety of self-aligned techniques may be utilized to form structures.

One exemplary self-aligned structure is a self-aligned contact. Self-aligned contacts may be utilized at a variety of points in a process integration flow. For example, self-aligned contacts have been known to be used for the formation of contacts to the gates of a semiconductor transistor. Self-aligned contacts may also be utilized for the formation of contacts to the source and drain regions of a transistor. Other self-aligned structures are known and it will be recognized that the structures described above are merely exemplary.

When forming self-aligned contacts to a transistor gate, differing cap materials are typically provided on the tops of the transistor gates and other structures (such as, for example, on top of conductors that are used for trench and source and drain regions). The differing cap materials provide different etch characteristics, so that the etch of the gate contact is selective to the other structures, and vice-versa. The other structures may include conductors at trench and source/drain regions. One known cap material utilized for on the conductors in source and drain contact regions is a chemical vapor deposition (CVD) silicon carbide (SiC) material. When CVD SiC is used as the cap material for source and drain contacts, silicon nitride (SiN) may be used as the gate cap.

As tolerances and thicknesses become more demanding, processes that use CVD SiC as a cap material for trench contacts have become unsatisfactory for self-aligned contacts. For example, the contact filling property of CVD SiC is not ideal and often leads to void formation. In addition, the planarization process (e.g., chemical mechanical polishing, (CMP)) used to remove excess CVD SiC to form caps for trench contacts is difficult, and often leads to further defects.

It would be desirable to provide an improved self-aligned gate contact process flow.

SUMMARY

Methods and improved process flows are provided herein for forming self-aligned contacts using spin-on silicon carbide (SiC). More specifically, the disclosed methods and process flows form self-aligned contacts by using spin-on SiC as a cap layer for at least one other structure, instead of depositing a SiC layer via plasma vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The other structure may be a conductor to which a source and drain contact is made. By utilizing spin-on SiC as a cap layer material, the disclosed methods and process flows avoid problems that typically occur when SiC is deposited, for example by CVD, and subsequently planarized. As such, the disclosed methods and process flows improve upon conventional methods and process flows for forming self-aligned contacts by reducing defectivity and improving yield.

In a first embodiment, a method to form self-aligned contacts on a substrate is provided, the method comprising providing a plurality of first conductors on the substrate, providing a plurality of second conductors on the substrate and providing a first cap layer over the plurality of first conductors, the first cap layer comprising a first dielectric material. The method further comprises forming a second cap layer over the plurality of second conductors, wherein the second cap layer is formed by spin coating a second dielectric material onto the substrate, wherein the second dielectric material differs from the first dielectric material, and wherein the second dielectric material comprises silicon carbide (SiC). The method also comprises forming a dielectric layer on the substrate, such that the dielectric layer is formed on the first cap layer and the second cap layer. The method further comprises utilizing a first etch process to etch portions of the dielectric layer and the first cap layer according to a first masking pattern formed above the dielectric layer to form a plurality of first self-aligned contacts to the first conductors. The method also comprises utilizing a second etch process to etch portions of the dielectric layer and the second cap layer according to a second masking pattern formed above the dielectric layer to form a plurality second self-aligned contacts to the second conductors. According to the method, the second cap layer prevents exposure of the second conductors during the first etch process and the first cap layer prevents exposure of the first conductors during the second etch process.

Various embodiments of the first embodiment described herein are provided. In one embodiment, the first dielectric material comprises silicon nitride (SiN). In another embodiment, after the second cap layer is formed, the method further comprises planarizing the second cap layer to remove excess portions of the second cap layer and form a plurality of second dielectric caps on the plurality of second conductors. In another embodiment, the method further comprises providing recesses above the plurality of second conductors, wherein the spin coating of the second dielectric material onto substrate fills the recesses with the second dielectric material. In other embodiments, the method prevents void formation in the plurality of second dielectric caps by spinning the second dielectric material onto the substrate. In yet another embodiment, by spinning the second dielectric material onto the substrate, the method reduces or eliminates defects that occur in the plurality of second dielectric caps that occur when planarizing the second cap layer. In still another embodiment, the first etch process has a higher etch rate of the first dielectric material than of the silicon carbide and the second etch process has a higher etch rate of the silicon carbide than of the first dielectric material.

In a second embodiment, a method for processing a substrate to form self-aligned contacts to conductors of a semiconductor transistor, the method comprising providing a gate conductor of the semiconductor transistor on the substrate, providing a first dielectric cap on the gate conductor, the first dielectric cap comprising a first dielectric material, and providing trench conductors on either side of the gate conductor, wherein the trench conductors are in contact with source and drain regions of the transistor. The method further comprises forming second dielectric caps over the trench conductors by spin coating a film comprising a second dielectric material onto the substrate, wherein the second dielectric material differs from the first dielectric material, and wherein the second dielectric material comprises silicon carbide (SiC). The method also comprises depositing a dielectric layer onto the semiconductor transistor, such that the dielectric layer is deposited over the first dielectric cap and the second dielectric caps. The method further comprises etching portions of the dielectric layer and the first dielectric cap to form a self-aligned gate contact to the gate conductor. The method also comprises etching portions of the dielectric layer and the second dielectric caps to form self-aligned source and drain contacts to the trench conductors. According to the method, the second dielectric caps prevent exposure of the trench conductors while forming the self-aligned gate contact and the first dielectric cap prevents exposure of the gate conductor while forming the self-aligned source and drain contacts.

Various embodiments of the second embodiment described herein are provided. In one embodiment, the method further comprises providing recesses above the trench conductors, wherein the spin coating of the film comprising the second dielectric material onto the substrate fills the recesses with the film. In another embodiment of the method, after spin coating of the film, the method further comprises planarizing the film to remove excess portions of the film to leave the second dielectric caps over the trench conductors. In another embodiment, the method includes a first etch process utilized to etch the self-aligned gate contact has a higher etch rate of the first dielectric material than of the silicon carbide and a second etch process utilized to etch the self-aligned source and drain contacts has a higher etch rate of the silicon carbide than of the first dielectric material. Some embodiments of the method, the second etch process comprises a chlorine-based plasma etch chemistry. In one embodiment of the method. the second etch process comprises a chlorine-oxygen (Cl2/O2) plasma etch chemistry. In some embodiments of the method, the first etch process comprises fluoromethane based plasma etch chemistry. In some embodiments of the method, the first etch process comprises a fluoromethane-hydrogen-argon (CH3F/H2/Ar) plasma etch chemistry. In one embodiment of the method, the first dielectric material comprises silicon nitride, and the etching portions of the dielectric layer and the first dielectric cap to form the self-aligned gate contact to the gate conductor comprises utilizing a fluoromethane based plasma etch chemistry.

