CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority under 35 U.S.C. § 119 of European Patent application no. 20208427.3, filed on 18 Nov. 2020, the contents of which are incorporated by reference herein.

FIELD

The disclosure relates to detecting jitter in phase locked loop (PLL) circuits.

BACKGROUND

Jitter in the output clock signal of PLLs is critical for the data integrity of an integrated circuit (IC). Excessive jitter can compromise data transmission to and from an IC, cause internal failures and jeopardize safety-critical functions. For smaller processes, excessive PLL jitter spikes are mainly due to single event upsets (SEU), which may be caused by cosmic radiation. Other potential contributors to jitter include ground bounce and power rail spikes, as well as cross-talk and external electromagnetic interference. All these effects are hard to predict, and an IC's sensitivity to them strongly depends on factors such as the application mode, aging, process corner, supply voltage and temperature. In many cases, safety requirements can only be met when safety-critical parameters are continuously supervised in the field. In the worst case, data corruption caused by jitter may be large enough to jeopardize safety, but still small enough to escape immediate detection.

Automotive standards such as ISO 26262, relating to functional safety of road vehicles, require detection of faults, as can be caused e.g. by excessive jitter in real-time to enable a defined Failure in Time (FIT) limit to be maintained, defined as the number of safety-critical failures per 109operating hours. The defined FIT for a particular application may typically be around 100 or even as low as 10 for some applications. The FIT may apply to an entire system, resulting in an even tighter requirement for multiple circuits making up a complete system. These standards require proof of a sufficient diagnostic coverage for SEUs. This means that excessive jitter needs to be detected irrespective of data corruption or other faults visible in other parts of the IC. A problem therefore exists of how to detect jitter in a PLL, particularly where this may arise in the form of jitter spikes during operation. This is particularly applicable to safety critical applications such as in automotive applications but may also apply in other applications where detection of jitter is important. A solution to this problem should ideally be usable in addition to existing mechanisms of PLL performance monitoring or may be used as a stand-alone detection mechanism.

SUMMARY

According to a first aspect there is provided a PLL circuit comprising:a phase comparison module;a loop filter;a voltage controller oscillator, VCO;a feedback divider; anda jitter evaluation module,wherein the phase comparison module is configured to receive an application clock signal and a feedback clock signal, the loop filter is configured to receive an output signal from the phase comparison module, the VCO is configured to receive an output signal from the loop filter and provide the output clock signal, and the feedback divider is configured to receive the output clock signal and provide the feedback clock signal to the phase comparison module,wherein the phase comparison module comprises a phase comparator and a measurement module configured to detect a metastable output in the phase comparator over active clock cycles of the application and feedback clock signals and provide an output signal to the jitter evaluation module indicating a metastability resolution time for the phase comparator, the jitter evaluation module being configured to provide an output indicative of jitter based on the metastability resolution time.

The phase comparator may be a flip-flop configured to receive the application and feedback clock signals, and the phase comparison module may comprise a synchronizer configured to receive an output signal from the flip-flop and provide the output signal from the phase comparison module, the measurement module configured to detect a metastable output in the output signal from the flip-flop.

The measurement module may be configured to detect oscillations in the output signal from the flip-flop over active clock cycles of the application and feedback clock signals.

The measurement module may be configured to count a number of oscillations in the output signal from the flip-flop over active clock cycles of the application and feedback clock signals.

The measurement module may be configured to detect a propagation delay time in the output signal from the flip-flop over active clock cycles of the application and feedback clock signals.

The phase comparator may be a time-to-digital converter, TDC, configured to receive the application and feedback clock signals, the phase comparison module comprising a synchronizer configured to receive an output signal from the TDC and provide the output signal from the phase comparison module, the measurement module configured to detect a metastable output in the output signal from the TDC.

The PLL may be a 2ndor higher order PLL.

The feedback divider may be configured to operate as an integer divider. In other arrangements the feedback divider may be configured to operate as a fractional-N divider when the PLL is operating in a first operational mode and as an integer divider when the PLL is operating in a second test mode.

According to a second aspect there is provided a method of detecting jitter in an output clock signal of a phase-locked loop, PLL comprising a phase comparison module, a loop filter, a voltage controller oscillator, VCO and a feedback divider, wherein the phase comparison module receives an application clock signal and a feedback clock signal, the loop filter receives an output signal from the phase comparison module, the VCO receives an output signal from the loop filter and provides the output clock signal, and the feedback divider receives the output clock signal and provides the feedback clock signal to the phase comparison module, the method comprising detecting a metastable output in a phase comparator of the phase comparison module over active clock cycles of the application and feedback clock signals and providing an output signal indicating a metastability resolution time for the phase comparator.

The phase comparator may be a flip-flop that receives the application and feedback clock signals and a synchronizer may receive an output signal from the flip-flop, the synchronizer providing the output signal from the phase comparison module, wherein the measurement module detects a metastable output in the output signal from the flip-flop.

The measurement module may detect oscillations in the output signal from the flip-flop over active clock cycles of the application and feedback clock signals.

The measurement module may count a number of oscillations in the output signal from the flip-flop over active clock cycles of the application and feedback clock signals.

The measurement module may detect a propagation delay time in the output signal from the flip-flop over active clock cycles of the application and feedback clock signals.

The phase comparator may be a time-to-digital converter, TDC, that receives the application and feedback clock signals, a synchronizer receiving an output signal from the TDC and providing the output signal from the phase comparator, the measurement module detects a metastable output in the output signal from the TDC.

These and other aspects of the invention will be apparent from, and elucidated with reference to, the embodiments described hereinafter.

