TECHNICAL FIELD

The present disclosure relates to the field of communication technologies, and in particular to a startup circuit device, a filter, and a receiver.

BACKGROUND

In a traditional receiver, a radio frequency signal received from an antenna may be sequentially passed through a band-pass filter or low-pass filter, a matching network (MN), a low noise amplifier (LNA), a mixer, another band-pass filter, an analog-to-digital converter (ADC) and a digital demodulator on a printed circuit board (PCB) to obtain the desired signal. The band-pass filter herein includes a fully-differential operational amplifier and a common-mode feedback (CMFB) circuit. Generally, the fully-differential operational amplifier is expected to operate at a static operating point, for example, with an input voltage and an output voltage of the amplifier being fixed at a preset value. The common-mode feedback circuit is used to stabilize the static operating point of the fully-differential operational amplifier, that is, to fix values of the common mode voltages input to and output from the amplifier at the preset value. However, the common-mode feedback circuit not only consumes a lot of power, but also cannot well stabilize the static operating point of the fully-differential operational amplifier at the preset value upon powering-up, as a result, the static operating point may become higher or lower than the preset value. In this case, the fully-differential operational amplifier may fall into a non-operating state, resulting in a poor operating stability of the fully-differential operational amplifier.

SUMMARY

The present disclosure provides a startup circuit device, a filter, and a receiver to solve one or more technical problems in the prior art.

In a first aspect, the embodiments of the present application provide a startup circuit device applicable to a filter including a fully-differential operational amplifier and a common-mode feedback circuit device connected in sequence. The startup circuit device includes a first startup input terminal, a second startup input terminal, a first startup output terminal and a second startup output terminal, where the first startup input terminal is connected to a first amplification input terminal of the fully-differential operational amplifier, the second startup input terminal is connected to a second amplification input terminal of the fully-differential operational amplifier, the first startup output terminal is connected to the first amplification input terminal, and the second startup output terminal is connected to the second amplification input terminal.

The startup circuit device is configured to adjust a received input voltage to a target voltage during startup of the fully-differential operational amplifier, and output the target voltage to the fully-differential operational amplifier, such that the fully-differential operational amplifier operates at the target voltage.

According to an embodiment, the startup circuit device includes a first resistor, a second resistor, a comparator, a first transistor, and a second transistor.

An end of the first resistor serves as the first startup input terminal, and an end of the second resistor serves as the second startup input terminal; both another end of the first resistor and another end of the second resistor are connected to an input terminal of the comparator, and an output terminal of the comparator is connected to both a gate of the first transistor and a gate of the second transistor.

The gate of the first transistor and the gate of the second transistor are connected to each other; a drain of the first transistor serves as the first startup output terminal, and a drain of the second transistor serves as the second startup output terminal; and both a source of the second transistor and a source of the first transistor are grounded or connected to a power supply terminal VDD.

The input terminal of the comparator is configured to receive an average value of the input voltage, the average value being acquired by dividing the input voltage by the first resistor and the second resistor; and the output terminal of the comparator is configured to output a high level or a low level based on a comparison result between a threshold voltage and the average value of the input voltage.

The first transistor and the second transistor are configured to pull up or down the average value of the input voltage to the target voltage according to the high level or the low level, where the threshold voltage is greater than or equal to the target voltage.

In an embodiment, the output terminal of the comparator is configured to output a high level when the comparison result shows that the average value of the input voltage is greater than the threshold voltage.

The first transistor and the second transistor are both NMOS transistors and configured to be turned on after receiving the high level and thereby pull down the average value of the input voltage to the target voltage.

In an embodiment, the output terminal of the comparator is configured to output the low level when the average value of the input voltage is pulled down to the target voltage and less than or equal to the threshold voltage.

The first transistor and the second transistor are configured to be turned off after receiving the low level, such that the fully-differential operational amplifier operates at the target voltage.

In an embodiment, the output terminal of the comparator is configured to output the low level when the average value of the input voltage is less than the threshold voltage.

The first transistor and the second transistor are both PMOS transistors and configured to be turned on after receiving the low level and thereby pull up the average value of the input voltage to the target voltage.

In an embodiment, the comparator includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor.

A gate of the third transistor of the comparator is connected to a gate of the fourth transistor of the comparator, and serves as the input terminal of the comparator; a drain of the third transistor of the comparator and a drain of the fourth transistor of the comparator are connected to a first connection point; a source of the third transistor of the comparator is connected to a source of the fifth transistor of the comparator; and a source of the fourth transistor of the comparator is grounded.

A gate of the fifth transistor of the comparator and a gate of the sixth transistor of the comparator are connected to a second connection point which is connected to the first connection point; a drain of the fifth transistor of the comparator is connected to a drain of the sixth transistor of the comparator, and serves as the output terminal of the comparator; and a source of the sixth transistor of the comparator is grounded.

In an embodiment, the comparator includes a comparison module and a reference voltage source that provides the threshold voltage.

The comparison module includes a first comparison input terminal and a second comparison input terminal, where the first comparison input terminal serves as the input terminal of the comparator; the second comparison input terminal is connected to an end of the reference voltage source, and another end of the reference voltage source is grounded; and an output terminal of the comparison module serves as the output terminal of the comparator and is connected to both the gate of the first transistor and the gate of the second transistor.

In an embodiment, the comparison module includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor.

A gate of the seventh transistor of the comparison module serves as the first comparison input terminal, a gate of the eighth transistor of the comparison module serves as the second comparison input terminal, and a source of the seventh transistor of the comparison module and a source of the eighth transistor of the comparison module are grounded.

A drain of the seventh transistor of the comparison module is connected to a drain of the ninth transistor of the comparison module; a drain of the eighth transistor of the comparison module is connected to a drain of the tenth transistor of the comparison module; a drain of the ninth transistor of the comparison module is connected to a gate of the ninth transistor of the comparison module; and a gate of the ninth transistor of the comparison module is connected to a gate of the tenth transistor of the comparison module.

A source of the ninth transistor of the comparison module, a source of the tenth transistor of the comparison module, and a source of the eleventh transistor of the comparison module are connected; a gate of the eleventh transistor of the comparison module is connected to a drain of the tenth transistor of the comparison module; and a drain of the eleventh transistor of the comparison module is grounded and serves as the output terminal of the comparison module.

In a second aspect, the embodiments of the present disclosure provide a filter, including at least one startup circuit device described above.

In a third aspect, the embodiments of the present disclosure provide a receiver, including at least one filter described above.

The present disclosure adopting the aforesaid technical solutions may have following advantages. During startup of the fully-differential operational amplifier, the common-mode feedback circuit device may be at a low power consumption mode and thus cannot fix the operating voltage of the fully-differential operational amplifier at the target voltage. Under this case, the input voltage can be received and adjusted by the startup circuit device to a target voltage, which enables the fully-differential operational amplifier to operate at the target voltage, and thereby effectively improves the stability of the fully-differential operational amplifier during the startup.

The above summary is only for the purpose of description and is not intended to be construed as any limitation. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present disclosure will be easily understood by referring to the accompanying drawings and the following detailed description.

