CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C 119(a) to Korean Patent Application No. 10-2019-0060870, filed on May 23, 2019, which is herein incorporated by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments of the present disclosure genera y relate to a semiconductor device and, more particularly, to a nonvolatile memory device having a tunneling structure.

2. Related Art

As demand for enhanced integration and more versatile electronic devices has increased, research for memory device structures that can improve the structural stability and reliability of data storage and operation has continued unabated.

Currently, a transistor-type nonvolatile memory device employing a three-layered structure of a charge tunneling layer, a charge trap layer and a charge barrier layer is used widely as a charge storage structure.

Typically, a nonvolatile memory device performs an operation of introducing electric charges from a substrate into the charge trap layer (programming operation) or erasing the electric charges of the charge trap layer (erasing operation), and the charge trap layer can perform a memory operation by storing the introduced electric charges in a nonvolatile manner. Also, a nonvolatile memory device can be implemented in a NAND-type structure in which pluralities of cell transistors are connected to each other to have a string shape.

SUMMARY

Various embodiments of the present invention are directed to a nonvolatile memory device having an improved tunneling structure. The nonvolatile memory device may exhibit improved program and erase operation efficiency. The nonvolatile memory device may also exhibit an improved retention characteristic.

The nonvolatile memory device according to an embodiment of the present disclosure includes a substrate having a channel layer, a first tunneling layer disposed on the channel layer, a second tunneling layer disposed on the first tunneling layer, a third tunneling layer disposed on the second tunneling layer, a charge trap layer disposed on the third tunneling layer, a charge barrier layer disposed on the charge trap layer, and a gate electrode layer disposed on the charge barrier layer. The first tunneling layer includes a first insulative material. The second tunneling layer includes a second insulative material. The third tunneling layer includes a second insulative material. The resistance switching material is a material whose electric resistance varies reversibly between a high resistance state and a low resistance state depending on a magnitude of an applied electric field.

The nonvolatile memory device according to another embodiment of the present disclosure includes a substrate, an electrode stack structure disposed on the substrate, the electrode stack structure including gate electrode layers and interlayer insulation layers, which are alternately stacked in a direction perpendicular to the substrate, a first trench penetrating the electrode stack structure on the substrate to expose sidewall surfaces of the gate electrode layers and the interlayer insulation layers, a charge barrier layer disposed to cover the interlayer insulation layers and the gate electrode layers along an inner surface of the trench, a charge trap layer disposed on the charge barrier layer along the inner surface of the trench, a tunneling structure disposed on the charge trap layer along the inner surface of the trench, and a channel layer disposed to contact the tunneling structure. The tunneling structure includes a first tunneling layer including a first insulative material, a second tunneling layer including a resistance switching material, and a third tunneling layer including a second insulative material.

These and other features and advantages of the present invention will become apparent to those skilled in the art of the invention from the following detailed description in conjunction with the following drawings.

