BACKGROUND

Semiconductor development organizations at integrated device manufacturers (IDMs) and independent foundries spend significant resources developing the integrated sequence of process operations used to fabricate the chips (integrated circuits (ICs)) they sell from wafers (“wafers” are thin slices of semiconductor material, frequently, but not always, composed of silicon crystal). A large portion of the resources is spent on fabricating experimental wafers and associated measurement, metrology (“metrology” refers to specialized types of measurements conducted in the semiconductor industry) and characterization structures, all for the purpose of ensuring that the integrated process produces the desired semiconductor device structures. These experimental wafers are used in a trial-and-error scheme to develop individual processes for the fabrication of a device structure and also to develop the total, integrated process flow. Due to the increasing complexity of advanced technology node process flows, a large portion of the experimental fabrication runs result in negative or null characterization results. These experimental runs are long in duration, weeks to months in the “fab” (fabrication environment), and expensive. Recent semiconductor technology advances, including FinFET, TriGate, High-K/Metal-Gate, embedded memories and advanced patterning, have dramatically increased the complexity of integrated semiconductor fabrication processes. The cost and duration of technology development using this trial-and-error experimental methodology has concurrently increased.

A virtual fabrication environment for semiconductor device structures offers a platform for performing semiconductor process development at a lower cost and higher speed than is possible with conventional trial-and-error physical experimentation. In contrast to conventional CAD and TCAD environments, a virtual fabrication environment is capable of virtually modeling an integrated process flow and predicting the complete 3D structures of all devices and circuits that comprise a full technology suite. Virtual fabrication can be described in its most simple form as combining a description of an integrated process sequence with a subject design, in the form of 2D design data (masks or layout), and producing a 3D structural model that is predictive of the result expected from a real/physical fabrication run. A 3D structural model includes the geometrically accurate 3D shapes of multiple layers of materials, implants, diffusions, etc. that comprise a chip or a portion of a chip. Virtual fabrication is done in a way that is primarily geometric, however the geometry involved is instructed by the physics of the fabrication processes. By performing the modeling at the structural level of abstraction (rather than physics-based simulations), construction of the structural models can be dramatically accelerated, enabling full technology modeling, at a circuit-level area scale. The use of a virtual fabrication environment thus provides fast verification of process assumptions, and visualization of the complex interrelationship between the integrated process sequence and the 2D design data.

BRIEF SUMMARY

Embodiments of the present invention provide the ability to perform depth-dependent oxidation modeling in a virtual fabrication environment. More particularly, embodiments enable the virtual fabrication environment to model, as part of a process sequence, oxidant dispersion in a depth-dependent manner and simulate the subsequent oxidation reaction based on the determined oxidant thickness along an air/silicon interface in a 3D structural model. Further, embodiments of the present invention provide the ability to perform depth-dependent etch modeling in a virtual fabrication environment. More particularly, embodiments enable the virtual fabrication environment to model, as part of a process sequence, etchant concentration in a depth-dependent manner and simulate the subsequent etching of material along the air/material interface in a 3D structural model.

In one embodiment, a computing device-implemented method for performing depth-dependent oxidation modeling in a virtual fabrication environment includes receiving a process sequence for a semiconductor device structure to be virtually fabricated. The process sequence includes a depth-dependent oxidation modeling step that indicates a point during the process sequence for depth-dependent oxidation modeling to be performed. The method also includes performing with the computing device a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, material addition and/or material removal steps performed to physically fabricate the semiconductor device structure. The virtual fabrication run executes the process sequence up until the depth-dependent oxidation modeling step and builds a 3D structural model of the semiconductor device structure. The 3D structural model is predictive of a result of a physical fabrication of the semiconductor device structure. The virtual fabrication run also performs the depth-dependent oxidation modeling step within a region of the 3D structural model. The depth-dependent oxidation modeling step generates depth-dependent oxidation data. The method additionally outputs the depth-dependent oxidation data generated from the depth-dependent oxidation modeling step.

In another embodiment, a system for performing depth-dependent oxidation modeling in a virtual fabrication environment includes at least one computing device equipped with one or more processors that is configured to generate a virtual fabrication environment that includes a depth-dependent modeling module. The virtual fabrication environment is configured to receive a process sequence for a semiconductor device structure to be virtually fabricated. The process sequence includes a depth-dependent oxidation modeling step that indicates a point during the process sequence for depth-dependent oxidation modeling to be performed. The virtual fabrication environment is also configured to perform with the computing device a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, material addition and/or material removal steps performed to physically fabricate the semiconductor device structure. The virtual fabrication run executes the process sequence up until the depth-dependent oxidation modeling step, the executing building a 3D structural model of the semiconductor device structure. The 3D structural model is predictive of a result of a physical fabrication of the semiconductor device structure. The virtual fabrication run further performs the depth-dependent oxidation modeling step within a region of the 3D structural model. The depth-dependent oxidation modeling step generates depth-dependent oxidation data. The system additionally includes a display surface in communication with the at least one computing device. The display surface is configured to display the depth-dependent oxidation modeling data.

In an embodiment, a computing device-implemented method for performing depth-dependent etch modeling in a virtual fabrication environment includes receiving a process sequence for a semiconductor device structure to be virtually fabricated. The process sequence includes a depth-dependent etch modeling step that indicates a point during the process sequence for depth-dependent etch modeling to be performed. The method also includes performing with the computing device a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, material addition and/or material removal steps performed to physically fabricate the semiconductor device structure. The virtual fabrication run executes the process sequence up until the depth-dependent etch modeling step and builds a 3D structural model of the semiconductor device structure. The 3D structural model is predictive of a result of a physical fabrication of the semiconductor device structure. The virtual fabrication run also performs the depth-dependent etch modeling step within a region of the 3D structural model. The depth-dependent etch modeling step generates depth-dependent etch result data. The method additionally outputs the depth-dependent etch result data generated from the depth-dependent etch modeling step.

In another embodiment, a system for performing depth-dependent etch modeling in a virtual fabrication environment includes at least one computing device equipped with one or more processors that is configured to generate a virtual fabrication environment that includes a depth-dependent modeling module. The virtual fabrication environment is configured to receive a process sequence for a semiconductor device structure to be virtually fabricated. The process sequence includes a depth-dependent etch modeling step that indicates a point during the process sequence for depth-dependent etch modeling to be performed. The virtual fabrication environment is also configured to perform with the computing device a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, material addition and/or material removal steps performed to physically fabricate the semiconductor device structure. The virtual fabrication run executes the process sequence up until the depth-dependent etch modeling step, the executing building a 3D structural model of the semiconductor device structure. The 3D structural model is predictive of a result of a physical fabrication of the semiconductor device structure. The virtual fabrication run further performs the depth-dependent etch modeling step within a region of the 3D structural model. The depth-dependent etch modeling step generates depth-dependent etch result data. The system additionally includes a display surface in communication with the at least one computing device. The display surface is configured to display the depth-dependent etch result data.

