BACKGROUND

Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and fabrication methods thereof.

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A 3D memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

SUMMARY

Embodiments of 3D memory devices and methods for forming the same are disclosed herein.

In one example, a 3D memory device includes a P-type doped region of a substrate, an N-type doped semiconductor layer on the P-type doped region, a memory stack including interleaved conductive layers and dielectric layers on the N-type doped semiconductor layer, a channel structure extending vertically through the memory stack and the N-type doped semiconductor layer into the P-type doped region, an N-type doped semiconductor plug extending vertically into the P-type doped region, and a source contact structure extending vertically through the memory stack to be in contact with the N-type doped semiconductor plug.

In another example, a 3D memory device includes a P-type doped region of a substrate, a memory stack including interleaved conductive layers and dielectric layers above the P-type doped region, a single N-type doped semiconductor layer between the P-type doped region and the memory stack and having a uniform doping concentration profile, and a channel structure extending vertically through the memory stack and the N-type doped semiconductor layer into the P-type doped region.

In still another example, a method for forming a 3D memory device is provided. A recess is formed in a P-type doped region of a substrate. A sacrificial layer on the P-type doped region and in the recess, and a dielectric stack on the sacrificial layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the sacrificial layer into the P-type doped region is formed. An opening extending vertically through the dielectric stack into the sacrificial layer in the recess is formed. The sacrificial layer is replaced, through the opening, with an N-type doped semiconductor layer between the P-type doped region and the dielectric stack. An N-type doped semiconductor plug is formed in the recess.

