FIELD

Certain example embodiments of the disclosure relate to semiconductor chip packaging. More specifically, certain example embodiments of the disclosure relate to a semiconductor package using a coreless signal distribution structure.

BACKGROUND

Present semiconductor packages and methods for forming semiconductor packages (e.g. multi-dimensional packages and methods utilizing interposer technology with through-silicon vias) are inadequate, for example resulting in excess cost, decreased reliability, or package sizes that are too large. For example, current interposer technology further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such approaches with the present disclosure as set forth in the remainder of the present application with reference to the drawings.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present disclosure as set forth in the remainder of the present application with reference to the drawings.

BRIEF SUMMARY

Various aspects of the present disclosure provide a semiconductor package, and a method of manufacturing thereof. For example and without limitation, various aspects of the present disclosure provide a three-dimensional semiconductor package, using a coreless signal distribution structure, and a method of manufacturing thereof, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

Various advantages, aspects and novel features of the present disclosure, as well as details of various illustrated example supporting embodiments, will be more fully understood from the following description and drawings.

