BACKGROUND

Field of the Invention

The present invention relates to field effect transistors (FETs) and, particularly, to lateral double-diffused metal oxide semiconductor field effect transistors (LDMOSFETs) and to methods of forming the LDMOSFETs.

Description of Related Art

Radio frequency (RF) applications typically require field effect transistors (FETs) with a high breakdown voltage (BV). Lateral double-diffused metal oxide semiconductor field effect transistors (LDMOSFETs) have been developed to provide this high BV; however, an even higher BV may be beneficial for some applications. Current techniques for further increasing the BV of an LDMOSFET include implant engineering. Unfortunately, implant engineering may be insufficient to achieve the high BV required for emerging technologies (e.g., sub-6 GHz WiFi power amplifier (PA) applications).

SUMMARY

Disclosed herein are embodiments of a transistor. The transistor can include a semiconductor body. The transistor can further include, within the semiconductor body, a first-type well and a second-type well positioned laterally adjacent to the first-type well. The first-type well can have a first-type conductivity and the second-type well can have a second-type conductivity that is different from the first-type conductivity. The transistor can further include a gate structure on the semiconductor body at the junction between the first-type well and the second-type well. The gate structure can have a first section, which traverses the semiconductor body adjacent to the first-type well, and a second section, which is positioned laterally adjacent to the first section and which traverses the semiconductor body adjacent to the second-type well. The gate structure can include, within both the first section and the second section, a first-type work function layer and second-type work function layer on the first-type work function layer. The first-type work function layer can have a first-type work function, which is within a first range of work functions, and the second-type work function layer can have a second-type work function, which is within a second range of work functions that is different from the first range. Additionally, a first portion of the first-type work function layer within the first section can have a first thickness and a second portion of the first-type work function layer within the second section can have a second thickness that is less than the first thickness such that the gate structure is asymmetric.

In some embodiments, the transistor can be an N-type field effect transistor (NFET). The NFET can include a semiconductor body and, within the semiconductor body, a Pwell and an Nwell positioned laterally adjacent to the Pwell. The NFET can further include a gate structure on the semiconductor body at the junction between the Pwell and the Nwell. The gate structure can have a first section, which traverses the semiconductor body adjacent to the Pwell, and a second section, which is positioned laterally adjacent to the first section and which traverses the semiconductor body adjacent to the Nwell. The gate structure can include, within both the first section and the second section, a P-type work function layer and an N-type work function layer on the P-type work function layer. Additionally, a first portion of the P-type work function layer within the first section can have a first thickness and a second portion of the P-type work function layer within the second section can have second thickness that is less than the first thickness such that the gate structure is asymmetric.

Also disclosed herein are embodiments of a method for forming a transistor. The method can include forming, within a semiconductor body, a first-type well, which has a first-type conductivity, and a second-type well, which is positioned laterally adjacent to the first-type well and which has a second-type conductivity that is different from the first-type conductivity. The method can also include forming a gate structure on the semiconductor body at the junction between the first-type well and the second-type well. This gate structure can be formed such it has a first section, which traverses the semiconductor body adjacent to the first-type well, and such that it has a second section, which is positioned laterally adjacent to the first section, which is different from the first section, and which traverses the semiconductor body adjacent to the second-type well. Specifically, the process of forming the gate structure can include forming a first-type work function layer, which has a first-type work function within a first range of work functions, in both the first section and the second section and further doing so such that a first portion of the first-type work function layer within the first section has a first thickness and a second portion of the first-type work function layer within the second section has a second thickness that is less than the first thickness. The process of forming the gate structure can further include forming a second-type work function layer, which has a second-type work function within a second range of work functions that is different from the first range, on the first-type work function layer in both the first section and in the second section.

