TECHNICAL FIELD

The disclosure relates to a component carrier and to a method of manufacturing the same.

BACKGROUND

A conventional component carrier comprises a stack having electrically conductive layer structures and electrically insulating layer structures. A cavity is formed in the stack, and a component is embedded in the cavity. Some component carriers comprise a printed circuit board having a cavity, in which a component of a high thermally conductive dielectric material is embedded. Some of these components of high thermally conductive dielectric material can be brittle and can break, especially during a placement of the component into a cavity of a component carrier stack and during a final lamination of the stack with the component placed therein.

SUMMARY

There may be a need to provide a component carrier and a method of manufacturing the same, which enable a more robust and reliable component carrier which is easy to manufacture with reduced rejects due to defects.

This need is achieved by a component carrier and a method of manufacturing a component carrier according to the independent claims.

According to an exemplary embodiment of the invention, a component carrier is provided. The component carrier comprises a stack comprising at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; a cavity formed in the stack and having a non-polygonal outline; and a component in the cavity.

According to another exemplary embodiment of the invention, a method of manufacturing a component carrier is provided. The method comprises steps of providing a stack comprising at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; forming in the stack a cavity having a non-polygonal outline; and inserting a component in the cavity.

OVERVIEW OF EMBODIMENTS

A stress lowering effect in the component carrier could be observed due to the non-polygonal outline of the cavity.

In an embodiment, at least a part of corners of the outline is rounded.

In an embodiment, a rounding in a corner of the outline has a radius of at least 0.05 mm, in particular at least 0.2 mm, more particularly at least 1 mm.

In an embodiment, the outline is substantially rectangular with rounded, in particular circular, extensions in at least a part of corners, in particular in all corners, of the outline. Such a non-polygonal outline is easy to manufacture.

In an embodiment, the outline is at least partly rounded along its entire perimeter, in particular has circular, oval or ellipsoidal portions. In an embodiment, at least part of edges of the outline is rounded, in particular comprises a wave structure. Advantageously, the circular, oval or ellipsoidal portions and the wave structure allow for an additional increase in placement and registration accuracy of the component. A stress relaxation can be achieved due to an adapted cavity size and form.

In an embodiment, the component has a polygonal outline, in particular a rectangular outline.

In an embodiment, the component has a rounded outline, in particular with circular, oval or ellipsoidal portions.

In an embodiment, a volume between the component and walls of the stack delimiting the cavity is configured as a stress buffer. For example, the volume can be filled by a resin from the electrically insulating layer structure during laminating the stack. The resin can compensate for different coefficients of thermal expansion (CTE) between the stack and the component. For example, a resin flows into the (bulged) roundings at the corners of the cavity and a resin excess is created there, which is further helpful for compensating the CTE mismatch.

In an embodiment, a volume between the component and walls of the stack delimiting the cavity is at least partially filled with a fiber-free resin. In an embodiment, the fiber-free resin is inserted into the volume by laminating at least one further at least partially uncured electrically insulating layer structure on the stack and the component in the cavity. The fiber-free resin enables an appropriate resin flow, an improved (gap) filling, and can compensate for a possible CTE mismatch.

In an embodiment, the at least one electrically insulating layer structure has sidewalls delimiting at least part of the cavity and comprises fibers so that the component carrier, in particular the stack, is more robust and exhibits less warpage.

In an embodiment, the component is a ceramic block, in particular having a metal cladding on at least part of at least one of its two opposing main surfaces, for example a copper-cladded AlN (Aluminum Nitride)-Inlay. In a modification, the component can be or comprise a copper block.

In an embodiment, a difference between an area delimited by the outline and an area of the component is adjusted to be substantially proportional to a square root of the area of the component.

In an embodiment, the component has a stepped profile at at least one of its main surfaces and is laterally engaged by a resin clamping structure. The clamping effect, preferably together with the ability of a cured resin of the electrically insulating layer structure of the stack to adapt to the surfaces of the component and the cavity, increases the stability of the component carrier. In another embodiment, this effect can also be achieved by a component having chamfered edges. If the component is a block of an insulating material, in particular a ceramic block, a metal cladding in the shape of metal layers such as copper layers can be provided on at least part of at least one of its two opposing main surfaces (for example a copper-cladded AlN (Aluminum Nitride)-Inlay). The metal layers can be retracted from edges of the block. It is also conceivable that the component is or comprises a structured metal block such as a structured copper block, wherein the stepped profile at at least one of its main surfaces is achieved by structuring the at least one main surface of the metal block.

In an embodiment of the method, a difference between an area delimited by the outline and an area of the component is adjusted to be substantially proportional to a square root of the area of the component.

In an embodiment of the method, the component has a stepped profile at at least one of its main surfaces and is laterally engaged by a resin clamping structure.

In the following, further exemplary embodiments of the present invention will be explained.

In the context of the present application, the term “non-polygonal outline’ may particularly denote an outline which does not define a polygon in its entirety. A polygon generally is a plane geometrical figure that is defined by a finite number of straight-line segments which are connected to form a closed chain or circuit. For example, any plane geometrical figure, which does not fulfill this condition, can be considered as a non-polygonal outline.

In the context of the present application, the term “stepped profile” may particularly denote a shoulder or a level difference of stacked layers, in particular where an upper layer is retracted from an edge of a subjacent layer. A stepped profile may also be formed by chamfered edges.

In the context of the present application, the term “component carrier” may particularly denote any support structure which is capable of accommodating one or more components thereon and/or therein for providing mechanical support and/or electrical connectivity. In other words, a component carrier may be configured as a mechanical and/or electronic carrier for components. A component carrier may comprise a laminated layer stack. In particular, a component carrier may be one of a printed circuit board, an organic interposer, and an IC (integrated circuit) substrate. A component carrier may also be a hybrid board combining different ones of the above-mentioned types of component carriers.

In the context of the present application, the term “stack” may particularly denote an arrangement of multiple planar layer structures which are mounted in parallel on top of one another.

In the context of the present application, the term “layer structure” may particularly denote a continuous layer, a patterned layer or a plurality of non-consecutive islands within a common plane.

In the context of the present application, the term “electronic component” may particularly denote a component fulfilling an electronic task. For instance, such an electronic component may be a semiconductor chip comprising a semiconductor material, in particular as a primary or basic material. The semiconductor material may for instance be a type IV semiconductor such as silicon or germanium, or may be a type III-V semiconductor material such as gallium arsenide. In particular, the semiconductor component may be a semiconductor chip such as a naked die or a molded die.

In an embodiment, the component carrier comprises a stack of at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier may be a laminate of the mentioned electrically insulating layer structure(s) and electrically conductive layer structure(s), in particular formed by applying mechanical pressure and/or thermal energy. The mentioned stack may provide a plate-shaped component carrier capable of providing a large mounting surface for further components and being nevertheless very thin and compact.

In an embodiment, the component carrier is shaped as a plate. This contributes to the compact design, wherein the component carrier nevertheless provides a large basis for mounting components thereon. Furthermore, in particular a naked die as example for an embedded electronic component, can be conveniently embedded, thanks to its small thickness, into a thin plate such as a printed circuit board.

In an embodiment, the component carrier is configured as one of the group consisting of a printed circuit board, a substrate (in particular an IC substrate), and an interposer.

In the context of the present application, the term “printed circuit board” (PCB) may particularly denote a plate-shaped component carrier which is formed by laminating several electrically conductive layer structures with several electrically insulating layer structures, for instance by applying pressure and/or by the supply of thermal energy. As preferred materials for PCB technology, the electrically conductive layer structures are made of copper, whereas the electrically insulating layer structures may comprise resin and/or glass fibers, so-called prepreg or FR4 material. The various electrically conductive layer structures may be connected to one another in a desired way by forming holes through the laminate, for instance by laser drilling or mechanical drilling, and by partially or fully filling them with electrically conductive material (in particular copper), thereby forming vias or any other through-hole connections. The filled hole either connects the whole stack, (through-hole connections extending through several layers or the entire stack), or the filled hole connects at least two electrically conductive layers, called via. Similarly, optical interconnections can be formed through individual layers of the stack in order to receive an electro-optical circuit board (EOCB). Apart from one or more components which may be embedded in a printed circuit board, a printed circuit board is usually configured for accommodating one or more components on one or both opposing surfaces of the plate-shaped printed circuit board. They may be connected to the respective main surface by soldering. A dielectric part of a PCB may be composed of resin with reinforcing fibers (such as glass fibers).

In the context of the present application, the term “substrate” may particularly denote a small component carrier. A substrate may be a, in relation to a PCB, comparably small component carrier onto which one or more components may be mounted and that may act as a connection medium between one or more chip(s) and a further PCB. For instance, a substrate may have substantially the same size as a component (in particular an electronic component) to be mounted thereon (for instance in case of a Chip Scale Package (CSP)). More specifically, a substrate can be understood as a carrier for electrical connections or electrical networks as well as component carrier comparable to a printed circuit board (PCB), however with a considerably higher density of laterally and/or vertically arranged connections. Lateral connections are for example conductive paths, whereas vertical connections may be for example drill holes. These lateral and/or vertical connections are arranged within the substrate and can be used to provide electrical, thermal and/or mechanical connections of housed components or unhoused components (such as bare dies), particularly of IC chips, with a printed circuit board or intermediate printed circuit board. Thus, the term “substrate” also includes “IC substrates”. A dielectric part of a substrate may be composed of resin with reinforcing particles (such as reinforcing spheres, in particular glass spheres).

The substrate or interposer may comprise or consist of at least a layer of glass, silicon (Si) and/or a photo-imageable or dry-etchable organic material like epoxy-based build-up material (such as epoxy-based build-up film) or polymer compounds (which may or may not include photo- and/or thermosensitive molecules) like polyimide or polybenzoxazole.

In an embodiment, the at least one electrically insulating layer structure comprises at least one of the group consisting of a resin or a polymer, such as epoxy resin, cyanate ester resin, benzocyclobutene resin, bismaleimide-triazine resin, polyphenylene derivate (e.g. based on polyphenylenether, PPE), polyimide (PI), polyamide (PA), liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE) and/or a combination thereof. Reinforcing structures such as webs, fibers, spheres or other kinds of filler particles, for example made of glass (multilayer glass) in order to form a composite, could be used as well. A semi-cured resin in combination with a reinforcing agent, e.g., fibers impregnated with the above-mentioned resins is called prepreg. These prepregs are often named after their properties e.g., FR4 or FR5, which describe their flame retardant properties. Although prepreg particularly FR4 are usually preferred for rigid PCBs, other materials, in particular epoxy-based build-up materials (such as build-up films) or photo-imageable dielectric materials, may be used as well. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymer and/or cyanate ester resins, may be preferred. Besides these polymers, low temperature cofired ceramics (LTCC) or other low, very low or ultra-low DK materials may be applied in the component carrier as electrically insulating structures.

In an embodiment, the at least one electrically conductive layer structure comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium, tungsten and magnesium. Although copper is usually preferred, other materials or coated versions thereof are possible as well, in particular materials coated with supra-conductive material or conductive polymers, such as graphene or poly(3,4-ethylenedioxythiophene) (PEDOT), respectively.

At least one component may be embedded in the component carrier and/or may be surface mounted on the component carrier. Such a component can be selected from a group consisting of an electrically non-conductive inlay, an electrically conductive inlay (such as a metal inlay, preferably comprising copper or aluminum), a heat transfer unit (for example a heat pipe), a light guiding element (for example an optical waveguide or a light conductor connection), an electronic component, or combinations thereof. An inlay can be for instance a metal block, with or without an insulating material coating (IMS-inlay), which could be either embedded or surface mounted for the purpose of facilitating heat dissipation. Suitable materials are defined according to their thermal conductivity, which should be at least 2 W/mK. Such materials are often based, but not limited to metals, metal-oxides and/or ceramics as for instance copper, aluminum oxide (Al2O3) or aluminum nitride (AlN). In order to increase the heat exchange capacity, other geometries with increased surface area are frequently used as well. Furthermore, a component can be an active electronic component (having at least one p-n-junction implemented), a passive electronic component such as a resistor, an inductance, or capacitor, an electronic chip, a storage device (for instance a DRAM or another data memory), a filter, an integrated circuit (such as field-programmable gate array (FPGA), programmable array logic (PAL), generic array logic (GAL) and complex programmable logic devices (CPLDs)), a signal processing component, a power management component (such as a field-effect transistor (FET), metal-oxide-semiconductor field-effect transistor (MOSFET), complementary metal-oxide-semiconductor (CMOS), junction field-effect transistor (JFET), or insulated-gate field-effect transistor (IGFET), all based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs) and/or any other suitable inorganic compound), an optoelectronic interface element, a light-emitting diode, a photocoupler, a voltage converter (for example a DC/DC converter or an AC/DC converter), a cryptographic component, a transmitter and/or receiver, an electromechanical transducer, a sensor, an actuator, a microelectromechanical system (MEMS), a microprocessor, a capacitor, a resistor, an inductance, a battery, a switch, a camera, an antenna, a logic chip, and an energy harvesting unit. However, other components may be embedded in the component carrier. For example, a magnetic element can be used as a component. Such a magnetic element may be a permanent magnetic element (such as a ferromagnetic element, an antiferromagnetic element, a multiferroic element or a ferrimagnetic element, for instance a ferrite core) or may be a paramagnetic or soft magnetic element. However, the component may also be an IC substrate, an interposer or a further component carrier, for example in a board-in-board configuration. The component may be surface mounted on the component carrier and/or may be embedded in an interior thereof. Moreover, also other components, in particular those which generate and emit electromagnetic radiation and/or are sensitive with regard to electromagnetic radiation propagating from an environment, may be used as component.

In an embodiment, the component carrier is a laminate-type component carrier. In such an embodiment, the component carrier is a compound of multiple layer structures which are stacked and connected together by applying a pressing force and/or heat.

After processing interior layer structures of the component carrier, it is possible to cover (in particular by lamination) one or both opposing main surfaces of the processed layer structures symmetrically or asymmetrically with one or more further electrically insulating layer structures and/or electrically conductive layer structures. In other words, a build-up may be continued until a desired number of layers is obtained.

After having completed formation of a stack of electrically insulating layer structures and electrically conductive layer structures, it is possible to proceed with a surface treatment of the obtained layers structures or component carrier.

In particular, an electrically insulating solder resist may be applied to one or both opposing main surfaces of the layer stack or component carrier in terms of surface treatment. For instance, it is possible to form such a solder resist on an entire main surface and to subsequently pattern the layer of solder resist so as to expose one or more electrically conductive surface portions which shall be used for electrically coupling the component carrier to an electronic periphery. The surface portions of the component carrier remaining covered with solder resist may be efficiently protected against oxidation or corrosion, in particular surface portions containing copper.

It is also possible to apply a surface finish selectively to exposed electrically conductive surface portions of the component carrier in terms of surface treatment. Such a surface finish may be an electrically conductive cover material on exposed electrically conductive layer structures (such as pads, conductive tracks, etc., in particular comprising or consisting of copper) on a surface of a component carrier. If such exposed electrically conductive layer structures are left unprotected, then the exposed electrically conductive component carrier material (in particular copper) might oxidize, making the component carrier less reliable. A surface finish may then be formed for instance as an interface between a surface mounted component and the component carrier. The surface finish has the function to protect the exposed electrically conductive layer structures (in particular copper circuitry) and enable a joining process with one or more components, for instance by soldering. Examples for appropriate materials for a surface finish are Organic Solderability Preservative (OSP), Electroless Nickel Immersion Gold (ENIG), Electroless Nickel Immersion Palladium Immersion Gold (ENIPIG), gold (in particular hard gold), chemical tin, nickel-gold, nickel-palladium, etc.

The aspects defined above and further aspects of the invention are apparent from the examples of embodiment to be described hereinafter and are explained with reference to these examples of embodiment.

