FIELD OF THE INVENTION

The present invention relates generally to configurable and reconfigurable computing circuitry, and more specifically to a configurable and reconfigurable arithmetic engine having electronic circuitry for arithmetic and logical computations.

BACKGROUND

Many existing computing systems have reached significant limits for computation processing capabilities, such as insufficient speed of computation for mathematically intensive applications, such as involving neural network computations, digital currencies, blockchain, and so on. In addition, many existing computing systems have excessive energy (or power) consumption, and associated heat dissipation. For example, existing computing solutions have become increasingly inadequate as the need for advanced computing technologies grows, such as to accommodate artificial intelligence, neural networking, encryption, decryption, and other significant computing applications.

Accordingly, there is an ongoing need for a computing architecture capable of providing high performance and energy efficient solutions for mathematically intensive applications, such as involving artificial intelligence, neural network computations, digital currencies, blockchain, encryption, decryption, computation of Fast Fourier Transforms (FFTs), and machine learning, for example and without limitation.

In addition, there is an ongoing need for a configurable and reconfigurable computing architecture capable of being configured for any of these various applications. Such a configurable and reconfigurable computing architecture should be readily scalable, such as to millions or processing cores, should have low latency, should be computationally and energy efficient, should be capable of processing streaming data in real time, should be reconfigurable to optimize the computing hardware for a selected application, and should be capable of massively parallel processing.

Numerous other advantages and features of the present invention will become readily apparent from the following detailed description of the invention and the embodiments thereof, from the claims and from the accompanying drawings.

SUMMARY OF THE INVENTION

As discussed in greater detail below, the representative apparatus, system and method provide for a computing architecture capable of providing high performance and energy efficient solutions for mathematically intensive applications, such as involving artificial intelligence, neural network computations, digital currencies, encryption, decryption, blockchain, computation of Fast Fourier Transforms (FFTs), and machine learning, for example and without limitation.

In addition, the reconfigurable processor disclosed herein, as an apparatus and system, is capable of being configured for any of these various applications, with several such examples illustrated and discussed in greater detail below. Such a reconfigurable processor is readily scalable, such as to millions of computational cores, has low latency, is computationally and energy efficient, is capable of processing streaming data in real time, is reconfigurable to optimize the computing hardware for a selected application, and is capable of massively parallel processing. For example, on a single chip, a plurality of the reconfigurable processors may also be arrayed and connected, using an interconnection network, to provide hundreds to thousands of computational cores per chip. In turn, a plurality of such chips may be arrayed and connected on a circuit board, resulting in thousands to millions of computational cores per board. Any selected number of computational cores may be implemented in reconfigurable processor, and any number of reconfigurable processors may be implemented on a single integrated circuit, and any number of such integrated circuits may be implemented on a circuit board. As such, the reconfigurable processor having an array of computational cores is scalable to any selected degree (subject to other constraints, however, such as routing and heat dissipation, for example and without limitation).

In a representative embodiment, a reconfigurable arithmetic circuit comprises: input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and at least one control logic circuit coupled to the multiplier shifter and combiner network and to the accumulator circuit.

In a representative embodiment, such a reconfigurable arithmetic circuit may further comprise: a configurable multiplier having a plurality of operating modes, the configurable multiplier coupled to the input reordering queues and to the multiplier shifter and combiner network, the plurality of operating modes comprising a fixed point operating mode and a floating point operating mode, wherein the configurable multiplier has a native operating mode of a 27×27 unsigned multiplier further configurable to process signed inputs. For example, the configurable multiplier may be further configurable to become four 8×8 multipliers, two 16×16 single-instruction multiple-data (SIMD) multipliers, one 32×32 multiplier and one 54×54 multiplier. For example, the configurable multiplier may be further configurable to reassign one or more partial products to become the 32×32 multiplier.

In a representative embodiment, the multiplier shifter and combiner network may comprise: a shifter circuit; and a plurality of series-coupled adder circuits coupled to the shifter circuit. In a representative embodiment, the multiplier shifter and combiner network may be adapted to shift a multiplier product to convert a floating point product to a product having a radix-32 exponent. In a representative embodiment, the multiplier shifter and combiner network may be adapted to sum a plurality of single-instruction multiple-data (SIMD) products to form a SIMD dot product.

In a representative embodiment, such a reconfigurable arithmetic circuit may further comprise: a configurable interconnection network selectively coupling the multiplier shifter and combiner network to one or more adjacent reconfigurable arithmetic circuits to perform single cycle 32×32 and 54×54 multiplication, single precision 24×24 multiplication, and single-instruction multiple-data (SIMD) dot products.

In a representative embodiment, the input reordering queues are adapted to store a plurality of inputs, and the input reordering queues further comprise: input reordering logic circuitry adapted to reorder a sequence of the plurality of inputs, and to adjust a sign bit for negate and absolute value functions. In a representative embodiment, the input reordering logic circuitry may be further adapted to de-interleave I (in phase) and Q (quadrature) data inputs and odd and even data inputs.

In a representative embodiment, such a reconfigurable arithmetic circuit may further comprise output reorder queues coupled to receive and reorder outputs from a plurality of reconfigurable arithmetic circuits. In a representative embodiment, the accumulator circuit may be a single-clock cycle fixed and floating point accumulator having a 128 bit carry-save format.

In a representative embodiment, the reconfigurable arithmetic circuit has a plurality of inputs, the plurality of inputs comprising a first, X input; a second, Y input, and a third, Z input, and wherein the at least one control logic circuit comprises one or more circuits selected from the group consisting of: a compare circuit; a Boolean logic circuit; a Z input shifter; an exponent logic circuit; an add, saturate and round circuit; and combinations thereof.

In a representative embodiment, the Z input shifter may be adapted to shift a floating point Z-input value to a radix-32 exponent value, to shift by multiples of 32 bits to match a scaling of multiplier sum outputs, and has a plurality of integer modes in which the Z input shifter is used as a shifter or rotator with 64, 32, 2×16 and 4×8 bit shift or rotate modes.

In a representative embodiment, the Boolean logic circuit may comprise an AND-OR-INVERT logic unit adapted to perform AND, NAND, OR, NOR, XOR, XNOR, and selector operations on 32 bit integer inputs.

In a representative embodiment, the compare circuit may be adapted to extract a minimum or maximum data value from an input data stream, an index from the input data stream, and is further adapted to compare two input data streams. In a representative embodiment, the compare circuit may be adapted to swap two input data streams and to put the minimum of the two input data streams on a first output and the maximum of the two input data streams on a second output. In a representative embodiment, the compare circuit may be adapted to perform data steering, to generate address sequences, and to generate comparison flags for equality, greater than and less than.

A plurality of reconfigurable arithmetic circuits arranged in an array is also disclosed, with a representative embodiment of each reconfigurable arithmetic circuit, of the plurality of reconfigurable arithmetic circuits, comprising: input reordering queues adapted to store a plurality of inputs, the input reordering queues further comprising input reordering logic circuitry adapted to reorder a sequence of the plurality of inputs of the reconfigurable arithmetic circuit and an adjacent reconfigurable arithmetic circuit of the plurality of reconfigurable arithmetic circuits; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; at least one control logic circuit coupled to the multiplier shifter and combiner network and to the accumulator circuit; and output reorder queues coupled to receive and reorder outputs from the reconfigurable arithmetic circuit and the adjacent reconfigurable arithmetic circuit of the plurality of reconfigurable arithmetic circuits.

In a representative embodiment, such an array of reconfigurable arithmetic circuits may further comprise a configurable interconnection network coupled to the multiplier shifter and combiner network to merge the plurality of reconfigurable arithmetic circuits to perform double precision multiply-adds, single precision single cycle complex multiply, FFT butterfly, exponent resolution, multiply-accumulate, and logic operations. For example, the configurable interconnection network may comprise a plurality of direct connections to link adjacent reconfigurable arithmetic circuits of the plurality of reconfigurable arithmetic circuits as a pair configuration of reconfigurable arithmetic circuits and as a quad configuration of reconfigurable arithmetic circuits.

In a representative embodiment, in such an array of reconfigurable arithmetic circuits, a single reconfigurable arithmetic circuit may be adapted to perform at least two mathematical computation or functions selected from the group consisting of: one IEEE single or integer 27×27 multiply per cycle; two parallel IEEE half precision, 16-bit brain floating point (“BFLOAT”) (BLOAT16), or 16-bit integer for signed and unsigned 16-bit integer values (INT16) multiplies per cycle; four parallel IEEE quarter precision or 8-bit integer for signed and unsigned 8-bit integer values (INT8) multiplies per cycle; sum of two parallel IEEE half precision, BFLOAT16 or INT16 multiplies per cycle; sum of four parallel IEEE quarter precision or 8-bit integer for signed and unsigned 8-bit integer values (INT8) multiplies per cycle; one quarter-precision or INT8 complex multiply per cycle; fused add; accumulation; 64, 32, 2×16 or 4×8 bit shifts by any number of bits; 64, 32, 2×16 or 4×8 bit rotate by any number of bits; 32-bit bitwise Boolean logic; compare, minimum or maximum of a data stream; two operand sort; and combinations thereof.

In a representative embodiment, in such an array of reconfigurable arithmetic circuits, two adjacent linked reconfigurable arithmetic circuits having the pair configuration may be adapted to perform at least two mathematical computation or functions selected from the group consisting of: one 32-bit integer for signed and unsigned 32-bit integer values (INT32) multiply per cycle; one 64-bit integer for signed and unsigned 64-bit integer values (INT64) multiply in a 4 cycle sequence using the accumulator circuit to add four 32×32 partial products); sum of two IEEE single precision or two 24-bit integer for signed and unsigned 24-bit integer values (INT24) multiplies per cycle; sum of four parallel IEEE half precision, 16-bit brain floating point (“BFLOAT”) (BLOAT16) or 16-bit integer for signed and unsigned 16-bit integer values (INT16) multiplies per cycle; sum of eight parallel IEEE quarter precision or 8-bit integer for signed and unsigned 8-bit integer values (INT8) multiplies per cycle; one half-precision or INT16 complex multiply per cycle; four multiplies and two adds; fused add; accumulation; and combinations thereof.

In a representative embodiment, in such an array of reconfigurable arithmetic circuits, four linked reconfigurable arithmetic circuits having the quad configuration may be adapted to perform at least two mathematical computation or functions selected from the group consisting of: two 64-bit integer for signed and unsigned 64-bit integer values (INT64) multiplies in four cycles; two 32-bit integer for signed and unsigned 32-bit integer values (INT32) multiplies per cycle; sum of two INT32 multiplies per cycle; sum of four IEEE single precision or 24-bit integer for signed and unsigned 24-bit integer values (INT24) per cycle; sum of eight parallel IEEE half precision, 16-bit brain floating point (“BFLOAT”) (BLOAT16) or 16-bit integer for signed and unsigned 16-bit integer values (INT16) multiplies per cycle; sum of sixteen parallel IEEE quarter precision or 8-bit integer for signed and unsigned 8-bit integer values (INT8) multiplies per cycle; one single precision or 24-bit integer for signed and unsigned 24-bit integer values (INT24) complex multiply per cycle; fused add; accumulation; and combinations thereof.

In a representative embodiment, in such an array of reconfigurable arithmetic circuits, each reconfigurable arithmetic circuit, of the plurality of reconfigurable arithmetic circuits, may further comprise: a configurable multiplier having a plurality of operating modes, the configurable multiplier coupled to the input reordering queues and to the multiplier shifter and combiner network; the plurality of operating modes comprising a fixed point operating mode and a floating point operating mode, wherein the configurable multiplier has a native operating mode of a 27×27 unsigned multiplier further configurable to process signed inputs. For example, the configurable multiplier may be further configurable to become four 8×8 multipliers, two 16×16 single-instruction multiple-data (SIMD) multipliers, one 32×32 multiplier and one 54×54 multiplier. For example, the configurable multiplier may be further configurable to reassign one or more partial products to become a 32×32 multiplier.

In a representative embodiment, in such an array of reconfigurable arithmetic circuits, the multiplier shifter and combiner network may comprise: a shifter circuit; and a plurality of series-coupled adder circuits coupled to the shifter circuit. For example, the multiplier shifter and combiner network may be adapted to shift a multiplier product to convert a floating point product to a product having a radix-32 exponent; and to sum a plurality of single-instruction multiple-data (SIMD) products to form a SIMD dot product. In a representative embodiment, in such an array of reconfigurable arithmetic circuits, the multiplier shifter and combiner network may further comprise: a plurality of direct connections coupling the multiplier shifter and combiner network to one or more multiplier shifter and combiner networks of adjacent reconfigurable arithmetic circuits of the plurality of reconfigurable arithmetic circuits to perform single cycle 32×32 and 54×54 multiplication, single precision 24×24 multiplication, and single-instruction multiple-data (SIMD) dot products.

In a representative embodiment, in such an array of reconfigurable arithmetic circuits, the multiplier shifter-combiner network may be adapted to add products from another reconfigurable arithmetic circuit in a pair configuration of reconfigurable arithmetic circuits and to generate a sum of products from another half of a reconfigurable arithmetic circuit quad configuration of reconfigurable arithmetic circuits. For example, the multiplier shifter-combiner network is adapted to additionally shift by multiples of 32 bits to match scaling of a Z input and inputs from the other reconfigurable arithmetic circuits in the quad configuration in order to sum the products.

In a representative embodiment, a reconfigurable arithmetic circuit may comprise: a plurality of data inputs, the plurality of data inputs comprising a first, X data input; a second, Y data input, and a third, Z data input; a plurality of data outputs; output reorder queues coupled to the plurality of data outputs to receive and reorder output data; input reordering queues coupled to the plurality of data inputs and adapted to store input data, the input reordering queues further comprising input reordering logic circuitry adapted to reorder a sequence of the input data; a configurable multiplier coupled to the input reordering queues, the configurable multiplier having a plurality of operating modes, the plurality of operating modes comprising a fixed point operating mode and a floating point operating mode, wherein the configurable multiplier has a native operating mode of a 27×27 unsigned multiplier further configurable to process signed inputs, and further configurable to become four 8×8 multipliers, two 16×16 single-instruction multiple-data (SIMD) multipliers, one 32×32 multiplier and one 54×54 multiplier; a multiplier shifter and combiner network coupled to the configurable multiplier, the multiplier shifter and combiner network comprising: a shifter circuit; a plurality of series-coupled adder circuits coupled to the shifter circuit; and a plurality of direct connections coupling the multiplier shifter and combiner network to one or more adjacent reconfigurable arithmetic circuits to perform single cycle 32×32 and 54×54 multiplication, single precision/24×24 multiplication, and single-instruction multiple-data (SIMD) dot products; a single-clock cycle fixed and floating point carry-save accumulator circuit; and a plurality of control logic circuits coupled to the multiplier shifter and combiner network and to the accumulator circuit, the plurality of control logic circuits comprising: a compare circuit adapted to extract a minimum or maximum data value from an input data stream, an index from the input data stream, and is further adapted to compare two input data streams, to swap the two input data streams to put the minimum of the two input data streams on a first output and the maximum of the two input data streams on a second output, to perform data steering, to generate address sequences, and to generate comparison flags for equality, greater than and less than; a Boolean logic circuit comprising an AND-OR-INVERT logic unit adapted to perform AND, NAND, OR, NOR, XOR, XNOR, and selector operations on 32 bit integer inputs; a Z input shifter adapted to shift a floating point Z-input value to a radix-32 exponent value, to shift by multiples of 32 bits to match a scaling of multiplier sum outputs, and has a plurality of integer modes in which the Z input shifter is used as a shifter or rotator with 64, 32, 2×16 and 4×8 bit shift or rotate modes; an exponent logic circuit; and an add, saturate and round circuit.

A reconfigurable processor circuit is also disclosed, with a representative embodiment comprising: a first interconnection network; a processor coupled to the first interconnection network; and a plurality of computational cores arranged in an array, the plurality of computational cores coupled to the first interconnection network and to a second interconnection network directly coupling adjacent computational cores of the plurality of computational cores, each computational core comprising: a memory circuit; and a reconfigurable arithmetic circuit comprising: input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and at least one control logic circuit coupled to the multiplier shifter and combiner network and to the accumulator circuit.

In a representative embodiment, the reconfigurable arithmetic circuit may further comprise: a configurable multiplier having a plurality of operating modes, the configurable multiplier coupled to the input reordering queues and to the multiplier shifter and combiner network, the plurality of operating modes comprising a fixed point operating mode and a floating point operating mode, wherein the configurable multiplier has a native operating mode of a 27×27 unsigned multiplier further configurable to process signed inputs.

In a representative embodiment, the reconfigurable processor circuit may further comprise: a third interconnection network selectively coupling the multiplier shifter and combiner network to one or more adjacent reconfigurable arithmetic circuits to perform single cycle 32×32 and 54×54 multiplication, single precision 24×24 multiplication, and single-instruction multiple-data (SIMD) dot products.

In a representative embodiment, the configurable multiplier is further configurable to become four 8×8 multipliers, two 16×16 single-instruction multiple-data (SIMD) multipliers, one 32×32 multiplier and one 54×54 multiplier.

In a representative embodiment, each computational core of the plurality of computational cores may further comprise: a plurality of input multiplexers coupled to the reconfigurable arithmetic circuit, to the first interconnection network and to the second interconnection network; a plurality of input registers, each input register coupled to a corresponding input multiplexer of the plurality of input multiplexers; a plurality of output multiplexers coupled to the reconfigurable arithmetic circuit, each output multiplexer coupled to a corresponding input register of the plurality of input registers; and a plurality of output registers, each output register coupled to a corresponding output multiplexer of the plurality of output multiplexers, to the first interconnection network and to the second interconnection network.

In a representative embodiment, each computational core of the plurality of computational cores may further comprise: a plurality of zeros decompression circuits, each zeros decompression circuit coupled to a corresponding input multiplexer of the plurality of input multiplexers; and a plurality of zeros compression circuits, each zeros compression circuit coupled to a corresponding output multiplexer of the plurality of output multiplexers.

In a representative embodiment, a number of data packets having all zeros in a date payload is encoded as a suffix in a next data packet having a nonzero data payload.

In a representative embodiment, the first interconnection network may be a hierarchical network having a fat tree configuration and comprises a plurality of data routing circuits.

In a representative embodiment, the reconfigurable processor circuit is adapted to perform any and all RISC-V processor instructions using the processor and the plurality of computational cores.

In another representative embodiment, a reconfigurable processor circuit may comprise: a first interconnection network; a processor coupled to the first interconnection network; and plurality of computational cores arranged in an array, the plurality of computational cores coupled to the first interconnection network and to a second interconnection network directly coupling adjacent computational cores of the plurality of computational cores, each computational core comprising: a memory circuit; and a reconfigurable arithmetic circuit comprising: input reordering queues adapted to store a plurality of inputs, the input reordering queues further comprising input reordering logic circuitry adapted to reorder a sequence of the plurality of inputs of the reconfigurable arithmetic circuit and an adjacent reconfigurable arithmetic circuit of the plurality of computational cores; a configurable multiplier having a plurality of operating modes, the configurable multiplier coupled to the input reordering queues, the plurality of operating modes comprising a fixed point operating mode and a floating point operating mode, wherein the configurable multiplier has a native operating mode of a 27×27 unsigned multiplier further configurable to process signed inputs, and wherein the configurable multiplier is further configurable to become four 8×8 multipliers, two 16×16 single-instruction multiple-data (SIMD) multipliers, one 32×32 multiplier and one 54×54 multiplier; a multiplier shifter and combiner network coupled to the configurable multiplier, the multiplier shifter and combiner network comprising: a shifter circuit; and a plurality of series-coupled adder circuits coupled to the shifter circuit; an accumulator circuit; at least one control logic circuit coupled to the multiplier shifter and combiner network and to the accumulator circuit; and output reorder queues coupled to receive and reorder outputs from the reconfigurable arithmetic circuit and the adjacent reconfigurable arithmetic circuit of the plurality of computational cores.

In another representative embodiment, a reconfigurable processor circuit may comprise: a first interconnection network; a processor coupled to the first interconnection network; and a plurality of computational cores arranged in an array, the plurality of computational cores coupled to the first interconnection network and to a second interconnection network directly coupling adjacent computational cores of the plurality of computational cores, each computational core comprising: a plurality of input multiplexers coupled to the first interconnection network and to the second interconnection network; a plurality of input registers, each input register coupled to a corresponding input multiplexer of the plurality of input multiplexers; a plurality of output multiplexers, each output multiplexer coupled to a corresponding input register of the plurality of input registers; a plurality of output registers, each output register coupled to a corresponding output multiplexer of the plurality of output multiplexers, to the first interconnection network and to the second interconnection network; a plurality of zeros decompression circuits, each zeros decompression circuit coupled to a corresponding input multiplexer of the plurality of input multiplexers; a plurality of zeros compression circuits, each zeros compression circuit coupled to a corresponding output multiplexer of the plurality of output multiplexers; a memory circuit; and a reconfigurable arithmetic circuit coupled to the memory circuit, to the plurality of input registers, and to the plurality of output multiplexers, the reconfigurable arithmetic circuit comprising: input reordering queues adapted to store a plurality of inputs, the input reordering queues further comprising input reordering logic circuitry adapted to reorder a sequence of the plurality of inputs of the reconfigurable arithmetic circuit and an adjacent reconfigurable arithmetic circuit of the plurality of computational cores; a configurable multiplier having a plurality of operating modes, the configurable multiplier coupled to the input reordering queues, the plurality of operating modes comprising a fixed point operating mode and a floating point operating mode, wherein the configurable multiplier has a native operating mode of a 27×27 unsigned multiplier further configurable to process signed inputs, and wherein the configurable multiplier is further configurable to become four 8×8 multipliers, two 16×16 single-instruction multiple-data (SIMD) multipliers, one 32×32 multiplier and one 54×54 multiplier; a multiplier shifter and combiner network coupled to the configurable multiplier, the multiplier shifter and combiner network comprising: a shifter circuit; and a plurality of series-coupled adder circuits coupled to the shifter circuit; an accumulator circuit; at least one control logic circuit coupled to the multiplier shifter and combiner network and to the accumulator circuit; output reorder queues coupled to receive and reorder outputs from the reconfigurable arithmetic circuit and the adjacent reconfigurable arithmetic circuit of the plurality of computational cores; and a third interconnection network selectively coupling the multiplier shifter and combiner network to one or more adjacent reconfigurable arithmetic circuits to perform single cycle 32×32 and 54×54 multiplication, single precision 24×24 multiplication, and single-instruction multiple-data (SIMD) dot products.

Numerous other advantages and features of the present invention will become readily apparent from the following detailed description of the invention and the embodiments thereof, from the claims and from the accompanying drawings.

