CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-099505, filed on May 28, 2019, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device.

BACKGROUND

For example, a DC/DC converter and other high-speed switching operation circuits include a switching element for switching a power source voltage at a high speed. A metal-oxide-semiconductor field-effect-transistor (MOSFET) having an active layer formed of a silicon semiconductor is applied to the switching element.

In such a circuit, a source-drain voltage of the switching element may rise suddenly at the time of turn-off due to parasitic inductance in the circuit and cause a large loss. This kind of loss can be reduced by installing a capacitor (snubber circuit) between the source and the drain.

In a related art, as a semiconductor device mounted with a snubber circuit, disclosed is a semiconductor device, which includes: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type installed on a part of the semiconductor substrate; a plurality of first electrodes installed in the semiconductor layer via a gate insulating film; a second electrode separated from the semiconductor layer and installed in the semiconductor substrate via a capacitance insulating film; and a source electrode installed on the semiconductor substrate, brought into contact with the semiconductor layer between the plurality of first electrodes and between the first electrodes and the second electrode, and electrically connected to the second electrode.

In the semiconductor device of the related art, a capacitor constituting the snubber circuit is arranged in a region on the side of a gate pad. Therefore, the region for the capacitor must be provided at the expense of a portion of a MOSFET region, which may reduce an allowable amount of current of the MOSFET region.

SUMMARY

Some embodiments of the present disclosure provide a semiconductor device capable of suppressing a reduction in an allowable amount of current flowing in an active region and suppressing generation of noise at the time of turn-off, compared with the related art.

According to one embodiment of the present disclosure, there is provided a semiconductor device, which includes: a semiconductor layer having a surface and a rear surface; an insulating film formed on the surface of the semiconductor layer; a first surface electrode layer and a second surface electrode layer formed on the insulating film and arranged at an interval from each other; a rear electrode layer formed on the rear surface of the semiconductor layer; an active region set in a region of the surface of the semiconductor layer covered with the first surface electrode layer; a capacitor region set in a region of the surface of the semiconductor layer covered with the second surface electrode layer; at least one first trench formed in the active region; a first insulating film formed on an inner surface of the at least one first trench; a first embedded electrode embedded in the at least one first trench and configured to control ON and OFF of current flowing between the first surface electrode layer and the rear electrode layer; at least one second trench formed in the capacitor region; a second insulating film formed on an inner surface of the at least one second trench; and a second embedded electrode embedded in the at least one second trench and electrically connected to the first surface electrode layer.

With this configuration, it is not necessary to sacrifice the active region for securing the capacitor region by effectively utilizing a region covered with the second surface electrode layer as the capacitor region. As a result, since the active region can be widely used, it is possible to suppress a reduction in allowable amount of current flowing in the active region.

Furthermore, a capacitor constituted by the second embedded electrode and a portion of the semiconductor layer facing each other with the second insulating film interposed therebetween is formed in the capacitor region. This capacitor is connected in parallel to a current path between the first surface electrode layer and the rear electrode layer. Thus, it is possible to suppress generation of noise when the current path between the first surface electrode layer and the rear electrode layer is turned off.

In some embodiments, wherein the at least one first trench includes a plurality of first trenches, and the at least one second trench includes a plurality of second trenches, wherein the plurality of first trenches are arranged in a stripe shape at intervals from each other, and wherein the plurality of second trenches are arranged in a stripe shape extending in a direction intersecting a stripe direction of the first trenches at intervals from each other.

With this configuration, it is possible to suppress warpage of the wafer when manufacturing an element structure of the semiconductor device according to an embodiment of the present disclosure on the semiconductor wafer. For example, when the first trenches and the second trenches have a stripe shape extending in the same direction as each other, the wafer is likely to be warped when the insulating film extending over the entire surface of the semiconductor wafer (for example, the insulating film on the surface of the semiconductor layer) is formed.

In some embodiments, the stripe direction of the first trenches and a stripe direction of the second trenches are orthogonal to each other.

In some embodiments, each of the first trenches has a width larger than a width of each of the second trenches.

In some embodiments, a pitch P1of the plurality of first trenches is larger than a pitch P2of the plurality of second trenches.

In some embodiments, the second insulating film includes a first portion formed on a side portion of the at least one second trench and a second portion formed on a bottom portion of the at least one second trench, and the second portion of the second insulating film has a thickness smaller than a thickness of the first portion of the second insulating film.

With this configuration, since the distance between the second embedded electrode and a portion of the semiconductor layer facing each other with the second insulating film (second portion) interposed therebetween can be reduced, it is possible to increase capacity of the capacitor.

In some embodiments, the semiconductor layer includes a source region of a first conductivity type, a channel region of a second conductivity type and a drift region of the first conductivity type sequentially formed along the at least one first trench in a direction from the surface to the rear surface of the semiconductor layer, the first embedded electrode includes a gate electrode, the first surface electrode layer includes a source electrode electrically connected to the source region and the channel region via the insulating film, the second surface electrode layer includes a gate pad electrically connected to the gate electrode, and the rear electrode layer includes a drain electrode electrically connected to the drift region.

In some embodiments, wherein the semiconductor layer includes an emitter region of a first conductive type, a base region of a second conductive type, a drift region of the first conductivity type sequentially formed along the at least one first trench in a direction from the surface to the rear surface of the semiconductor layer and a collector region of the second conductivity type arranged on the rear surface side of the semiconductor layer with respect to the drift region, the first embedded electrode includes a gate electrode, the first surface electrode layer includes an emitter electrode electrically connected to the emitter region and the base region via the insulating film, the second surface electrode layer includes a gate pad electrically connected to the gate electrode, and the rear electrode layer includes a collector electrode electrically connected to the collector region.

In some embodiments, the semiconductor device further includes a first conductivity type region formed on a bottom portion of the at least one second trench and having an impurity concentration higher than an impurity concentration of the drift region.

With this configuration, since the distance between the second embedded electrode and the first conductivity type region is reduced, it is possible to increase capacity of the capacitor.

