CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2019-163383 filed in Japan on Sep. 6, 2019; the entire contents of which are incorporated herein by reference.

FIELD

An embodiment described herein relates generally to a semiconductor device.

BACKGROUND

In general, with respect to semiconductor chips sealed in a package, a connection state inspection for detecting a normal state or a defective state relating to connection such as short-circuiting of various terminals (pins), a bonding failure, or a disconnection is performed by making use of external terminals of the package.

For example, when NAND memory chips each forming a single body are sealed in a package, a connection state inspection of the NAND memory chip is performed by connecting a tester to an external terminals of the package to which various terminals such as control terminals and I/O terminals of the NAND memory chip are connected.

However, in the structure where a plurality of single-body of NAND memory chips are disposed in a package in a stacked manner, terminals having the same function of the respective NAND memory chips may be connected in common in the form of links, and be connected to an external terminal of the package. In this case, it is difficult to determine in which NAND memory chip a connection failure has occurred.

Further, there may be a case where a NAND memory chip on which a controller is mounted is sealed in a package. In such a configuration, a connection portion between the controller and the NAND memory chip is sealed in the chip and hence, it is difficult to perform a connection state inspection of the various terminals of the NAND memory chip.

