BACKGROUND

Electrostatic discharge (ESD) is a rapid discharge that flows between two objects due to the build-up of static charge. ESD may destroy semiconductor devices because the rapid discharge can produce a relatively large current. In order to reduce the semiconductor failures due to ESD, ESD protection circuits have been developed to provide a current discharge path. When an ESD event occurs, the discharge current is conducted through the discharge path without going through the internal circuits to be protected.

In the semiconductor technology, ESD protection solutions such as NMOS transistors, Silicon-Controlled Rectifiers (SCRs) and RC triggered PMOS transistors are widely used. Each ESD protection device may comprise a detection circuit and an ESD current discharge path. For example, an RC triggered ESD protection circuit may comprise a discharge transistor, a driver and an ESD spike detection circuit. The ESD spike detection circuit may include a resistance element and a capacitance element connected in series to form an RC detection circuit. The node between the resistance element and the capacitance element is coupled to the gate of the discharge transistor via the driver. The time constant formed by the resistance element and the capacitance element is so chosen that the discharge transistor is turned off when the ESD protection device operates in a normal power up mode. On the other hand, the discharge transistor is turned on when an ESD spike occurs at a power bus to which the ESD protection circuit is coupled. The turn-on of the discharge transistor may provide a bypass of the ESD current from the power bus to ground so as to clamp the voltage of the power bus to a level below the maximum rating voltage to which the internal circuit is specified, so that it helps to prevent the large voltage spike from damaging the internal circuits being protected.

Similarly, a PNP transistor can be used as an ESD protection device. More particularly, the emitter of the PNP transistor is coupled to an input/output (I/O) pad of an integrated circuit and the collector of the PNP transistor is coupled to ground. When an ESD event occurs, an external voltage across the I/O pad and ground increases beyond the reverse-bias breakdown voltage of the PNP transistor. As a result, a conductive path is established between the emitter and the collector of the PNP transistor. Such a conductive path allows the large amount of ESD energy to be discharged in a relatively short amount of time. As a consequence, the internal circuit components of the integrated circuit can be protected from being damaged by the ESD event.

