BACKGROUND

This document relates generally to semiconductor devices and, more specifically, to insulated gate device structures and methods.

Insulated gate field effect transistors (IGFETs), such as metal oxide semiconductor field effect transistors (MOSFETs), have been used in many power switching applications, such as dc-dc converters. In a typical MOSFET, a gate electrode provides turn-on and turn-off control with the application of an appropriate gate voltage. By way of example, in an n-type enhancement mode MOSFET, turn-on occurs when a conductive n-type inversion layer (i.e., channel region) is formed in a p-type body region in response to the application of a positive gate voltage, which exceeds an inherent threshold voltage. The inversion layer connects n-type source regions to n-type drain regions and allows for majority carrier conduction between these regions.

The Safe Operating Area or “SOA” of an IGFET device is defined as the voltage and current conditions over which the device can be expected to operate without self-damage. In general, there are three operating conditions often referred to in typical enhancement mode IGFET current-voltage output characteristics: a) a fully turned-on condition where the gate-to-source voltage (VGS) is biased well above the threshold voltage (VT) and a good conduction channel region connects the source and drain regions (a characteristic where the drain-source voltage (VDS) is low and drain-source current (IDS) is high); b) an off condition where VGS<VTand no channel region is formed (a characteristic where VDSis high and IDSis essentially zero); and c) a condition between a and b where the channel region is pinched-off referred to as a linear mode or constant current condition where neither VDSor IDSare low.

When an IGFET device functions in the linear mode of operation, junction temperature (TJ) increases due to high power dissipation through the device because neither VDSnor IDSare low. With the increase of junction temperature at certain gate biases below what is referred to as the zero temperature coefficient point, the IDScurrent will increase causing the junction temperature to further increase. This positive feedback effect can result in a thermal runaway condition resulting in device failure. This effect can be exasperated by localized current hot-spots within a device caused by, for example, localized defects, process variations, or bonding wire placement. In addition, with the continued industry push to reduce on-resistance, smaller pitched devices have been developed to meet the reduced on-resistance demand. However, the change in current with respect to change in temperature or dI/dT is increased in smaller pitched devices, thus exacerbating the thermal runaway condition during the linear mode of operation.

Accordingly, structures and methods are needed that improve the ability of semiconductor devices, such as IGFET devices to operate under linear mode conditions. It would be beneficial for the structure and method to be cost effective and to minimize effect on other device operating parameters.

BRIEF SUMMARY

The present description includes, among other features, a structure and method for improving the operation of a semiconductor device, such as an insulated gate field effect transistor (IGFET) device, which includes a power metal oxide semiconductor FET (MOSFET) device, in a linear mode of operation where higher power dissipation occurs. Specifically, a structure and method is provided where during linear mode of operation the channel current is configured to flow only in certain segments of the device. In some examples, the structure comprises a source region of a first conductivity type having a first segment bounded underneath by a first segment of well region of a second conductivity type. In some examples, the first segment of the source region is laterally bounded by a second segment of the well region where the dopant concentration of the second segment of the well region is less than the dopant concentration of the first segment of the well region. In operation, the second segment of the well region has a lower threshold voltage VTthan the first segment of the well region and turns on first facilitating the lateral and vertical current flow in the device. During the linear mode of operation, a channel is not formed in the first segment of the well region, which functions to shield the first segment of the source region from vertical current flow to reduce the likelihood of thermal runaway.

In some examples, a second segment of the source region is configured to provide a series ballast resistance to provide a negative feedback between current and junction temperature in the linear mode of operation (i.e., as temperature increases the series resistance increases thereby reducing current through the ballast resistor portion of the source region), which improves current uniformity across the device thus improving the forward-biased safe operating area (FBSOA). In addition, the first segment of the well region having the increased dopant concentration functions to improve on-resistance when the device is in a fully-on condition.

More particularly, in one example, a semiconductor device structure comprises a region of semiconductor material comprising a first semiconductor layer of a first conductivity type and having a first major surface. A first body region of a second conductivity type opposite to the first conductivity type is disposed in the first semiconductor layer extending from the first major surface. The first body region comprises a first segment having a first doping concentration, and a second segment laterally adjacent to the first segment and adjacent to the first major surface having a second doping concentration less than the first doping concentration. A first source region of the first conductivity type is disposed in the first segment of the body region but is not disposed in at least a portion of the second segment. An insulated gate electrode is disposed adjacent to the region of semiconductor material adjoining the first segment, the second segment, and the first source region. A first conductive layer is electrically connected to the first segment, the second segment, and the first source region. A second conductive layer adjacent to a second major surface of the region of semiconductor material opposite to the first major surface. In another example, the structure can include a ballast resistor structure electrically connected to the first source region, wherein the ballast resistor structure does not physically contact the first conductive layer.

In a further example, the first body region comprises a first stripe region; and the semiconductor device structure further includes a second body region comprising a second stripe region generally parallel to the first stripe region; a second body region first segment having the first doping concentration; and a second body region second segment having the second doped concentration; and a second source region of the first conductivity type disposed within the second body region first segment and laterally offset with respect to the first source region.

In a further example, a semiconductor device structure comprises a region of semiconductor material comprising a first semiconductor layer of a first conductivity type and having a first major surface. A first body region of a second conductivity type opposite to the first conductivity type is disposed in the first semiconductor layer extending from the first major surface, wherein the first body region comprises a first body region first segment having a first doping concentration; and a first body region second segment laterally adjacent to the first body region first segment and adjacent to the first major surface having a second doping concentration less than the first doping concentration. A first source region of the first conductivity type is disposed in the first body region first segment but not disposed in at least a portion of the first body region second segment. An insulated gate electrode is disposed adjacent to the region of semiconductor material adjoining the first body region first segment, the first body region second segment, and the first source region. A first conductive layer is disposed in a contact trench and electrically connected to the first body region first segment, the first body region second segment, and the first source region. In a still further example, the first body region first segment extends into the first semiconductor layer to a first depth, and the first body region second segment extends into the first semiconductor layer to a second depth that is different than the first depth.

In another example, the first doping concentration has a first peak dopant concentration, the second doping concentration has a second peak dopant concentration, and the first peak dopant concentration is at least twice the second peak dopant concentration.

In a further example, a method of forming a semiconductor device structure includes providing a region of semiconductor material comprising a first semiconductor layer of a first conductivity type and having a first major surface. The method includes providing a first body region of a second conductivity type opposite to the first conductivity type disposed in the first semiconductor layer extending from the first major surface, wherein the first body region includes a first body region first segment having a first doping concentration, and a first body region second segment laterally adjacent to the first body region first segment and adjacent to the first major surface having a second doping concentration less than the first doping concentration. The method includes providing a first source region of the first conductivity type disposed in the first body region first segment but not disposed in at least a portion of the first body region second segment. The method includes providing an insulated gate electrode disposed within the region of semiconductor material adjoining the first body region first segment, the first body region second segment, and the first source region. The method includes providing a first conductive layer disposed in a contact trench and electrically connected to the first body region first segment, the first body region second segment, and the first source region.

In a further example, the method further includes providing a ballast resistor structure electrically connected to the first source region, wherein the ballast resistor structure does not physically contact the first conductive layer; and the ballast resistor structure comprises a doped region of the first conductivity type disposed within the first body region second segment and laterally extends to overlap a portion of the first body region first segment.

Other examples are included in the present disclosure. Such examples may be found in the figures, in the claims, and/or in the description of the present disclosure.

