FIELD OF THE DISCLOSURE

This disclosure relates generally to die having through silicon/substrate vias (TSVs) and specifically to the testing of the TSVs.

BACKGROUND OF THE DISCLOSURE

Integrated circuit die may be designed for stacking using TSVs. TSVs are vertical conductive paths formed between the bottom surface of the die and top surface of the die. TSVs may be formed in the die using conductive material, such as but not limited to copper. TSVs allow thousands or tens of thousands of vertical connections to be made between the dies in a stack. The advantage of stacking die using TSVs over older approaches, such as die stacking based on peripheral bond wire connections, is a greater number of higher speed interconnects may exist between die in a stack. Also the physical size of the die stack is reduced since the TSV connections are made between the bottom and top surfaces of the die, i.e. the die do not need a periphery connection area.

FIG. 1illustrates a die100including TSVs102-106. Each TSV is a conductive path between the bottom surface and top surface of the die. A TSV could be used for providing a voltage bus, a ground bus or a signal bus between the bottom and top surface of the die. As seen each TSV102-106is electrically connected to a contact point108, for example metal pad or a micro bump, on the bottom surface and a contact point110on the top surface. The wording bottom and top surfaces used herein are for simplifying the descriptions of the Figures of this disclosure, they are not intended to define or specify any orientation of how the die surfaces in a stack are connected.

During the manufacture of Die100, each TSV102-106should be tested for connectivity between contact points108and110. In addition to connectivity, the resistance of TSVs between contact points108and110need to be tested. For example the resistance of TSVs that provide power, ground and high performance signaling paths should be tested. If die100had ten thousand TSVs to test, a tester would have to have the resources to test all ten thousand TSVS, which can be very expensive proposition.

The following disclosure describes a method and apparatus for testing TSVs using a scan path architecture that includes scan cells adapted for testing TSVs.

BRIEF SUMMARY OF THE DISCLOSURE

The following disclosure describes a method of testing TSVs using a scan path architecture including scan cells adapted for testing TSVs.

