This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-142679, filed Aug. 2, 2019, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device.

BACKGROUND

A power shut-down region is provided in a semiconductor integrated circuit including a memory, a logic circuit, and the like, and power switch cells (PSWs) are often disposed in a boundary between a power supply and the power shut-down region for the purpose of lowering power consumption. Power supplied from the PSWs to the power shut-down region is controlled to lower power consumption. The PSWs each have a switch element having a small channel width to prevent a rush current generated in the power shut-down region at a time of power-on and to reduce power-supply noise.

In order to suppress the rush current, the switch element having the small channel width is turned on first, which, however, delays a startup time of the semiconductor integrated circuit because of the low capability to supply power.

