BACKGROUND

I. Field of the Disclosure

The technology of the disclosure relates generally to limiting power consumption in a multi-threaded processor.

II. Background

Computing devices have become increasingly popular in part due to ever increasing functionality. Such increased functionality comes from increasingly powerful integrated circuits (ICs) having increasingly powerful processing capabilities. These ICs operate at increasingly high frequencies with more internal transistors, which in turn, consume more power than earlier ICs. An additional reason for increased popularity of computing devices is a growth in the availability of mobile computing devices. Such mobile computing devices typically rely on a battery for power. Batteries effectively have maximum current values that can be provided to the ICs in the mobile computing devices. Excess current levels may result in undesired thermal activity in the computing device.

While existing computing devices have struck a balance that allows desired performance without compromising heat dissipation or performance, new generations of ICs are imposing ever greater demands on the power control circuits. Traditionally, processing system hardware or software is usually constrained by global mechanisms such as limiting clock frequency and/or operating at low voltage modes. Both of these techniques may result in performance loss including unacceptable latency. Accordingly, there is room for new power management methods that result in power demand reduction.

SUMMARY OF THE DISCLOSURE

Aspects disclosed in the detailed description include systems and methods for multi-thread power limiting via a shared limit. In particular, exemplary aspects of the present disclosure estimate power consumed in a processing core on a thread-by-thread basis by counting how many power events occur in each thread. Power consumed by each thread is approximated based on the number of power events that have occurred. Power consumed by individual threads is compared to a shared power limit derived from a sum of the power consumed by all threads. Threads that are above the shared power limit are stalled while threads below the shared power limit are allowed to continue without throttling. In this fashion, the most power intensive threads are throttled to stay below the shared power limit while still maintaining performance.

In this regard in one aspect, a method for controlling power consumption in a computing device is disclosed. The method includes measuring power on a thread-by-thread basis for a plurality of threads at a plurality of thread execution circuits in the computing device. The method also includes calculating a total power consumed by all threads of the plurality of threads. The method also includes generating a shared power limit based on the total power and a predefined limit. The method also includes comparing a value associated with power consumed by an individual thread of the plurality of threads to the shared power limit. The method also includes, when the power consumed by the individual thread exceeds the shared power limit, stalling the individual thread at the plurality of thread execution circuits.

In another aspect, a method for controlling power consumption in a computing device is disclosed. The method includes measuring power on a core-by-core basis for a plurality of processing cores in the computing device. The method also includes calculating a total power consumed by all processing cores. The method also includes generating a shared power limit based on the total power and a predefined limit. The method also includes comparing a value associated with power consumed by an individual processing core of the plurality of processing cores to the shared power limit. The method also includes, when the power consumed by the individual processing core exceeds the shared power limit, stalling the individual processing core.

In another aspect, an integrated circuit (IC) is disclosed. The IC includes a multi-thread processing core. The multi-thread processing core includes a thread logic. The multi-thread processing core also includes a plurality of digital power meters configured to measure power on a thread-by-thread basis at the thread logic. The multi-thread processing core also includes a summation circuit configured to sum outputs from the plurality of digital power meters. The multi-thread processing core also includes a first comparator configured to compare an output of the summation circuit to a predefined limit. The multi-thread processing core also includes a second comparator configured to compare an output of a digital power meter of the plurality of digital power meters to a shared power limit derived from an output of the first comparator.

In another aspect, an IC is disclosed. The IC includes a multi-thread processing core. The multi-thread processing core includes a plurality of thread execution circuits. The multi-thread processing core also includes a plurality of digital power meters configured to measure power on a thread-by-thread basis at a corresponding thread execution circuit. The multi-thread processing core also includes a summation circuit configured to sum outputs from the plurality of digital power meters. The multi-thread processing core also includes a manipulation circuit configured to operate on the sum. The multi-thread processing core also includes a first comparator configured to compare an output of the manipulation circuit to a predefined limit. The multi-thread processing core also includes a multiplexor configured to use the compare result from the first comparator to select a minimum limit or a maximum limit. The multi-thread processing core also includes a circuit that uses a multiplexor output to generate a shared power limit. The multi-thread processing core also includes a second comparator configured to compare an output of a digital power meter of the plurality of digital power meters to the shared power limit.

