CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a non-provisional patent application claiming priority to European Patent Application No. 19217958.8, filed Dec. 19, 2019, the contents of which are hereby incorporated by reference.

FIELD OF THE DISCLOSURE

The application relates to on-chip reconstruction of transient settling behavior. In particular, this application relates to foreground and background monitoring of transient settling behavior of an amplifier in a discrete-time switched capacitor circuit.

BACKGROUND

Generally, the performance monitoring and behavioral analysis for a switched capacitor circuit, for instance, an analog to digital converter (ADC), can be performed by either foreground or background techniques. The background monitoring techniques facilitate additional robustness and flexibility because the circuit remains in its normal mode of operation while monitoring is being performed. In addition, the background monitoring techniques allow for cost-effective on-the-fly calibration of the circuit across process, voltage, or temperature (PVT) variations.

Furthermore, in circuit design, it is possible to simulate the transient operation of a circuit and to use knowledge of the resulting transient waveforms to optimize the circuit design or to find the correct biasing. Due to the virtualization of a simulated environment, there is full observability of all nodes in the system. In-circuit test and measurement, it is also possible to acquire similar transient waveform data for certain externals observable ports that can be probed by an oscilloscope, and to use this information to optimize the behavior of a circuit through analog or digital tuning adjustments.

However, the requirement that the node be externally observable makes this impractical for most high-speed integrated circuits, because it becomes impractical to buffer an internal analog signal to an external pad with high precision and high bandwidth. Moreover, this is only practically useful for test and measurement applications, not for industrialization. In mass production, it is not practical to do such external probing due to the cost and size of the measurement equipment, and the time required to do the measurement. Rather, the integrated circuit must be able to configure and optimize itself internally.

For example, Ahmed ElShater, et al., “A 10-mW 16-b 15-MS/s Two-Step SAR ADC with 95-dB DR using Dual-Deadzone Ring Amplifier”, IEEE Journal of Solid-State Circuits, Volume 54, Issue 12, December 2019, pp. 3410-3420; discloses an on-chip circuit monitoring technique. In particular, the technique utilizes a scope-on-chip to measure the settling behavior of a ring amplifier. However, the monitoring is limited to only foreground monitoring, where a high-resolution quantizer is utilized due to the necessity for quantizing the full output range.

SUMMARY

Accordingly, an aspect of the application provides an apparatus that facilitates cost-effective and lightweight monitoring and a method of operation of the apparatus, which can be implemented on-chip alongside the integrated circuit of interest.

In a first aspect, an apparatus is provided for on-chip reconstruction of transient settling behavior. The apparatus comprises a first sampling circuit configured to sample a tracked analog signal output from a circuit under test over a transient settling period of the circuit under test at a first sampling time, thereby generating a first sample output. In addition, the apparatus comprises a second sampling circuit configured to sample the tracked analog signal output at a second sampling time, thereby generating a second sample output. In this context, the first sampling time is tunable over the operating period at a plurality of sampling moments in time, and the second sampling time is fixed at an endpoint of the operating period.

The apparatus further comprises a signal subtraction circuit configured to perform subtraction of the first sample output and the second sample output, thereby generating a difference signal. Moreover, the apparatus comprises a signal conversion circuit configured to output the difference signal in the digital domain.

Therefore, the first sampling circuit samples the output, e.g., a voltage of the circuit under test at certain intermediate points throughout the circuit operation, and the second sampling circuit samples the final settled output voltage. The relative comparison between the intermediate and final values effectively subtracts the settled signal value and only compares the relative difference between them. This facilitates performing quantization of the difference signal by a relatively simple signal conversion circuit. Thus, it is possible to reconstruct a digitized representation of the transient settling behavior of the circuit under test without significantly reducing the performance requirements for on-chip monitoring.

In a first implementation of the first aspect, the first sample output and the second sample output are repeatedly generated and recombined across a plurality of operating periods, thereby reconstructing the transient settling behavior of the circuit under test. In this context, the input to the circuit under test is, in an example, similar for the plurality of operating periods, such that the output settling behavior of the circuit under test will be nearly identical across the plurality of cycles.

In a second implementation of the first aspect, the circuit under test is an integrated circuit, and in some examples, a discrete-time switched capacitor circuit comprising an amplifier, whereby the apparatus is configured to be implemented in-situ alongside the integrated circuit.

In a further implementation of the first aspect, the tracked analog signal output corresponds to a transient waveform output from the amplifier of the circuit under test with similar input conditions. Furthermore, the first sample output represents a transient value at an arbitrary time instant, and the second sample output represents a final transient value of the transient waveform over the operating period. It is possible to vary the first sampling time across multiple periods where similar or similar-enough signal is present at the output of the circuit under test, thereby reconstructing the transient waveform of the circuit under test.

In a further implementation of the first aspect, the signal conversion circuit is an analog to digital converter. This allows a lightweight solution for on-chip monitoring.

In a further implementation of the first aspect, the analog to digital converter is realized in the form of a single comparator having a first input and a second input, respectively conveying the first sample output and the second sample output. The signal conversion is performed in a cost-effective and simplified manner.

In a further implementation of the first aspect, the apparatus further comprises a controller configured to provide the first sampling time and the second sampling time in order to operate the first sampling circuit and the second sampling circuit, respectively. Preferably, the controller includes logic and timing circuitry for generating the sampling times and thereby operating the first and second sampling circuit.

In this context, the controller may generate the first sampling time by means of a programmable time delay. In addition, the controller may generate the second sampling time based on the operating period of the circuit under test. In particular, the second sampling time can be generated in correspondence to the overall sampling time provided for the integrated circuit.

In a further implementation of the first aspect, the first sampling circuit and the second sampling circuit each comprises at least one sampling switch and at least one sampling capacitor.

In a further implementation of the first aspect, the sampling capacitors are formed with signal lines conveying the tracked analog signal output from the circuit under test. Therefore, the sampling capacitors are realized by means of wire capacitors, which leads to a very compact layout. As a result, any additional capacitive loading on the circuit under test, especially caused by the monitoring apparatus can be effectively minimized.

In a second aspect, a method is provided for on-chip reconstruction of transient settling behavior. The method comprises sampling a tracked analog signal output from a circuit under test over an operating period at a first sampling time, thereby generating a first sample output. In addition, the method comprises sampling the tracked analog signal output at a second sampling time, thereby generating a second sample output. The method further comprises performing subtraction of the first sample output and the second sample output, thereby generating a difference signal. Moreover, the method comprises outputting the difference signal in the digital domain.

In a first implementation of the second aspect, the first sampling time is tunable over the operating period at a plurality of sampling moments in time, and the second sampling time is fixed at an end point of the operating period. Furthermore, the method further comprises repeatedly generating and combining the sampling outputs across a plurality of operating periods, thereby reconstructing the transient settling behavior of the circuit under test. Therefore, it is possible to reconstruct a digitized representation of the transient settling behavior of the circuit under test that significantly reduces the performance requirements for on-chip monitoring. Furthermore, in addition to the reconstruction of the settling behavior of the circuit under test, the repetitive/iterative generation of the sample outputs and the averaging of the sample outputs further allows for noise filtration during the monitoring of the circuit under test.

In a second implementation of the second aspect, the method further comprises generating the first sample output and the second sample output for a similar input to the circuit under test. It is possible to vary the first sampling time across multiple periods where a similar signal is present, thereby reconstructing the transient waveform of the circuit under test.

In a further implementation of the second aspect, the method further comprises generating the first sample output and the second sample output for random inputs to the circuit under test, whereby the sample outputs are binned according to their level, and the averaging is performed per bin. Hence, the monitoring is further performed for random inputs to the circuit under test, where the sample outputs are binned or grouped as per their level in the output range, and the averaging is done per bin, which additionally allows for noise filtration.

These aspects and implementations provide a general method for on-chip reconstruction of transient settling behavior that relaxes the performance requirements for on-chip monitoring significantly. The method is not limited to the nature of the input acting on the circuit under test. The only requirement is a constant or sufficiently-similar final settled value that can be achieved by applying similar input to the circuit under test, thereby facilitating foreground monitoring. Additionally, the input to the circuit under test can be random in nature, where the output settled value is binned, thereby facilitating background monitoring.

