@inproceedings{
nam2023npcnis,
title={{NPC}-{NIS}: Navigating Semiconductor Process Corners with Neural Importance Sampling},
author={Hong Chul Nam and Chanwoo Park},
booktitle={NeurIPS 2023 Workshop on Adaptive Experimental Design and Active Learning in the Real World},
year={2023},
url={https://openreview.net/forum?id=QIwA1zUd2t}
}
Traditional corner case analysis in semiconductor circuit design typically involves the
use of predetermined semiconductor process parameters, including Fast, Typical, and Slow
corners for PMOS and NMOS devices, frequently yielding overly conservative designs due
to the utilization of fixed, and potentially non-representative, process parameter values
for circuit simulations. Identifying the worst cases of circuit FoMs within typical semiconductor process variation ranges presents a considerable challenge, especially given the
complexities associated with accurately sampling rare semiconductor events. In response,
we introduce NPC-NIS, a model specifically developed for estimating rare cases in semiconductor circuit analysis, leveraging a learnable importance sampling strategy. We model
the distribution of process parameters that exhibit the worst FoMs within a realistic range.
This adaptable framework dynamically identifies and addresses rare semiconductor cases
within typical process variation ranges, enhancing our circuit design optimization capabilities under realistic conditions. Our empirical results validate the effectiveness of the Neural
Importance Sampling (NIS) approach in identifying and mitigating rare semiconductor scenarios, thereby contributing to the development of more robust and reliable semiconductor
circuit designs and connecting traditional semiconductor corner case analysis with realworld semiconductor applications.
NPC-NIS: Navigating Semiconductor Process Corners with Neural Importance Sampling
Hong Chul Nam Chanwoo Park