<story><title>The Belt CPU Architecture</title><url>http://ootbcomp.com/docs/belt/index.html</url></story><parent_chain></parent_chain><comment><author>ChuckMcM</author><text>I got to talk with Ivan after he gave an earlier version of this talk at Asilomar and the good news was he&amp;#x27;s the real deal, pretty much every question I could think to throw at him he had a solid answer for, the bad news was I felt the same way about the Mill architecture as I did about Intel&amp;#x27;s iapx432 architecture [1], which was elegant to a fault.&lt;p&gt;That said, I got the sense that this was what Intel was going for when they did Larrabee [2] and just missed because of the focus on Graphics. Unlike Larrabee is suspect OOTBC will need to build it themselves like Chip did for the Propeller [3].&lt;p&gt;That said, the challenge of these bespoke architectures are the requirement for software, or first a GCC port :-). I believe Ivan said they had a port that talked to their simulator, but I don&amp;#x27;t know if that was an optimizing thing like SGI&amp;#x27;s compiler for Itanium or a proof of concept thing.&lt;p&gt;The weird thing is of course &amp;quot;Why?&amp;quot;, and one might say &amp;quot;But Chuck, faster and cheaper, why not?&amp;quot; and I look at the explosion of ARM SoC&amp;#x27;s (cheaper, not necessarily faster than x86) and look back at ARM and think 99% of this was getting the ecosystem built, not the computer architecture. So who can afford to invest the billions to build the eco-system? Who would risk that investment? (Google might but that is a different spin on things).&lt;p&gt;So playing around with the Zynq-7020 (same chip that is on the Parallea but not the Epiphany co-processor) I can see a nice dual core ARM9 where you have full speed access to a bespoke DSP if you want for the &amp;#x27;tricky&amp;#x27; bits. Will that be &amp;quot;good enough&amp;quot; for the kinds of things this would also excel at? I don&amp;#x27;t know, so I don&amp;#x27;t know how to handicap OOTBC&amp;#x27;s chances for success. But I really enjoy novel computer architectures, like this one and Chuck Moore&amp;#x27;s &amp;#x27;1000 forth chickens&amp;#x27; chip [4] (it was a reference to the Seymour Cray&amp;#x27;s quote, &amp;quot;Would you have 1,000 chickens pull your plow or an Ox?&amp;quot;&lt;p&gt;A really interesting time will be had when &amp;#x27;paid off&amp;#x27; fab capacity is sitting idle and the cost for a wafer start becomes a function of how badly the fab wants to keep the line busy.&lt;p&gt;[1] &lt;a href=&quot;http://en.wikipedia.org/wiki/Intel_iAPX_432&quot; rel=&quot;nofollow&quot;&gt;http:&amp;#x2F;&amp;#x2F;en.wikipedia.org&amp;#x2F;wiki&amp;#x2F;Intel_iAPX_432&lt;/a&gt;&lt;p&gt;[2] &lt;a href=&quot;http://en.wikipedia.org/wiki/Larrabee_(microarchitecture)#Differences_with_CPUs&quot; rel=&quot;nofollow&quot;&gt;http:&amp;#x2F;&amp;#x2F;en.wikipedia.org&amp;#x2F;wiki&amp;#x2F;Larrabee_(microarchitecture)#Di...&lt;/a&gt;&lt;p&gt;[3] &lt;a href=&quot;http://www.parallax.com/propeller/&quot; rel=&quot;nofollow&quot;&gt;http:&amp;#x2F;&amp;#x2F;www.parallax.com&amp;#x2F;propeller&amp;#x2F;&lt;/a&gt;&lt;p&gt;[4] &lt;a href=&quot;http://www.colorforth.com/S40.htm&quot; rel=&quot;nofollow&quot;&gt;http:&amp;#x2F;&amp;#x2F;www.colorforth.com&amp;#x2F;S40.htm&lt;/a&gt;</text></comment>
<story><title>The Belt CPU Architecture</title><url>http://ootbcomp.com/docs/belt/index.html</url></story><parent_chain></parent_chain><comment><author>CoffeeDregs</author><text>First off, I love the post!  Super meaty goodness.&lt;p&gt;I read-ish the whole set of slides and it sounds pretty good (the devil is always in the details), but I got a little worried about VLIW-ish issues when [in the slides] he said on slide #57:&lt;p&gt;&lt;pre&gt;&lt;code&gt;    The compiler controls when ops issue
&lt;/code&gt;&lt;/pre&gt;
One of the big issues with VLIW was that the compiler had to be intimately aware of processor architecture.  So when you upgraded your &amp;#x27;886 to a &amp;#x27;986 you needed new binaries because the &amp;#x27;986 had more registers or executions units.  [I assume Itanium fixed some of this, but it also sunk my interest in VLIW.]&lt;p&gt;Is this architecture going to face the same issue?&lt;p&gt;Edit: I watching the video and heard that &amp;quot;nearly all of what the super scalar is doing is [not calculating]&amp;quot;.  One of the other VLIW issues was that chip area was dominated by cache-area, so all the stuff about [not calculating] shrank and shrank relatively as cache area grew (see: &lt;a href=&quot;http://techreport.com/review/15818/intel-core-i7-processors&quot; rel=&quot;nofollow&quot;&gt;http:&amp;#x2F;&amp;#x2F;techreport.com&amp;#x2F;review&amp;#x2F;15818&amp;#x2F;intel-core-i7-processors&lt;/a&gt;).  This claim concerns me.&lt;p&gt;Edit V2: but damn...  Exciting stuff.</text></comment>