<story><title>Intel Releases x86-SIMD-sort 2.0 With Faster AVX-512 Sorting, New Algorithms</title><url>https://www.phoronix.com/news/Intel-x86-simd-sort-2.0</url></story><parent_chain><item><author>cientifico</author><text>A interesting reading related to this is the thoughts of Linus about AVX-512 back in 2020: &lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;www.phoronix.com&amp;#x2F;news&amp;#x2F;Linus-Torvalds-On-AVX-512&quot; rel=&quot;nofollow noreferrer&quot;&gt;https:&amp;#x2F;&amp;#x2F;www.phoronix.com&amp;#x2F;news&amp;#x2F;Linus-Torvalds-On-AVX-512&lt;/a&gt;&lt;p&gt;My conclusion (feel free to enlighten me if I am wrong) is that a system will profit by having more cores instead of AVX-512 for the same power consumption.</text></item></parent_chain><comment><author>janwas</author><text>(Frequent AVX-512 user, opinions are my own.)&lt;p&gt;It is time to stop quoting this rant, which is rather far removed from actual practice and reality.&lt;p&gt;Specifically for sorting, Intel&amp;#x27;s sort and ours can be about 10x as fast as scalar.&lt;p&gt;AVX-512 has high power? Great! Power is work per time. Let&amp;#x27;s have more of that.
It is _useful_ work per _energy spent_ that we want to maximize, and there scalar code falls flat. Consider that OoO scheduling&amp;#x2F;control overhead is the real culprit; executing one instruction costs far more energy than the actual operation. SIMD divides that fixed cost over 16 elements, leading to 5-10x higher power efficiency.&lt;p&gt;Top frequency reduction? Not since the first implementation on Skylake, and even there a non-issue, see &lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;github.com&amp;#x2F;google&amp;#x2F;highway&amp;#x2F;blob&amp;#x2F;master&amp;#x2F;hwy&amp;#x2F;contrib&amp;#x2F;sort&amp;#x2F;README.md#study-of-avx-512-downclocking&quot;&gt;https:&amp;#x2F;&amp;#x2F;github.com&amp;#x2F;google&amp;#x2F;highway&amp;#x2F;blob&amp;#x2F;master&amp;#x2F;hwy&amp;#x2F;contrib&amp;#x2F;so...&lt;/a&gt;.&lt;p&gt;More cores? The shared-memory fabric is already bursting at the seams (see on-chip bottlenecks of Genoa), we are already cramming in too many for the current memory interface.&lt;p&gt;What would actually be necessary: more bandwidth! A64FX CPUs actually beat GPUs in 2019 for supercomputing applications thanks to their HBM. Intel&amp;#x27;s Sappire Rapids Max also has this. Let&amp;#x27;s build more of those, at a decent price. And start using the wide vector units, they are there precisely because lots of highly-clocked cores in one big NUMA domain is not always the best way forward.</text></comment>
<story><title>Intel Releases x86-SIMD-sort 2.0 With Faster AVX-512 Sorting, New Algorithms</title><url>https://www.phoronix.com/news/Intel-x86-simd-sort-2.0</url></story><parent_chain><item><author>cientifico</author><text>A interesting reading related to this is the thoughts of Linus about AVX-512 back in 2020: &lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;www.phoronix.com&amp;#x2F;news&amp;#x2F;Linus-Torvalds-On-AVX-512&quot; rel=&quot;nofollow noreferrer&quot;&gt;https:&amp;#x2F;&amp;#x2F;www.phoronix.com&amp;#x2F;news&amp;#x2F;Linus-Torvalds-On-AVX-512&lt;/a&gt;&lt;p&gt;My conclusion (feel free to enlighten me if I am wrong) is that a system will profit by having more cores instead of AVX-512 for the same power consumption.</text></item></parent_chain><comment><author>jackmott42</author><text>A lot of the downclocking issues he was talking about then are less severe now on newer Intel cpus and AMD cpus, which changes the calculus a lot.&lt;p&gt;You could probably find a workload where your conclusion is correct but I think the vast majority of workloads would be faster with AVX-512 if you have the time to leverage it.</text></comment>