<story><title>Examining ARM vs. x86 Memory Models with Rust</title><url>https://www.nickwilcox.com/blog/arm_vs_x86_memory_model/</url></story><parent_chain></parent_chain><comment><author>ajross</author><text>&amp;gt; Where the memory model of ARM differs from X86 is that ARM CPU’s will re-order writes relative to other writes, whereas X86 will not.&lt;p&gt;May.  Not will.  The difference here is important, because the actual memory ordering presented is an issue of hardware implementation choice (and of course the local vagaries like cache line alignment, interrupt order and the behavior of other CPUs on the bus).  You can&amp;#x27;t just write some sample code to demonstrate it and expect it&amp;#x27;s going to work the same on &amp;quot;ARM&amp;quot;.&lt;p&gt;In fact I&amp;#x27;d be really curious how Apple handles this during the Mac transition.  I wouldn&amp;#x27;t be at all surprised if, purely for the sake of compatibility, they implement an strongly ordered x86-style cache hierarchy.  Bugs in this world can be extremely difficult to diagnose, and honestly cache coherence transistors aren&amp;#x27;t that expensive relative to the rest of the system.</text></comment>
<story><title>Examining ARM vs. x86 Memory Models with Rust</title><url>https://www.nickwilcox.com/blog/arm_vs_x86_memory_model/</url></story><parent_chain></parent_chain><comment><author>RcouF1uZ4gsC</author><text>&amp;gt; The x86 processor was able to run the test successfully all 10,000 times, but the ARM processor failed on the 35th attempt.&lt;p&gt;I think this issue might prove a problem in the long tail of desktop and server software running on ARM.&lt;p&gt;A lot of desktop and server applications try to take advantage of all the cores. Many times, they are using libraries that were either implemented prior to C and C++ having defined memory models or else without that much care for memory model as long as it ran without issues on the developer computer (x86) and server (x86). Going to ARM is going to expose a lot of these bugs as developers recompile their code for ARM without making sure that their code actually adheres to the C&amp;#x2F;C++ memory models.</text></comment>