<story><title>RISC-V J extension – Instructions for JITs</title><url>https://github.com/riscv/riscv-j-extension</url></story><parent_chain></parent_chain><comment><author>aidenn0</author><text>For tagged values, I loved the POWER rlwinm: Rotate Left Word Immediate aNd with Mask (and it&amp;#x27;s companion rlimi).  Pretty much any sane tagging scheme could be converted to the unboxed value with that single instruction; even somewhat exotic tagging schemes like mixing high-bit and low-bit tagging could be handled by it.&lt;p&gt;Of course in modern architectures being able to do something in one instruction is only tenuously related to being able to do something quickly, but it was a super handy instruction back in the day.</text></comment>
<story><title>RISC-V J extension – Instructions for JITs</title><url>https://github.com/riscv/riscv-j-extension</url></story><parent_chain></parent_chain><comment><author>Taniwha</author><text>It&amp;#x27;s worth noting that on systems with real cache coherency (MOESI for example) where for example writing data into the dcache to an address A results in cache line shootdown in the icache as part of fetching an &amp;#x27;exclusive&amp;#x2F;modified&amp;#x27; line into the dcache - in this world EXPORT.I is essentially a no-op because what it requires  the icache implement (shootdown of icache lines) has already happened naturally.&lt;p&gt;Equally on such a system the only thing left for FENCE.I to do is to flush any (potentially now bogus) subsequent instructions that are in the execution pipe that might have been prefetched before the writes occurred. In such a system FENCE.I and IMPORT.I are identical.&lt;p&gt;Hopefully the people writing this spec are listening ... please make sure your spec understands high end systems like this and doesn&amp;#x27;t add stuff that require special cases in systems that do ubiquitous coherency right</text></comment>