<story><title>Why do CPUs have multiple cache levels?</title><url>https://fgiesen.wordpress.com/2016/08/07/why-do-cpus-have-multiple-cache-levels/</url></story><parent_chain><item><author>rwmj</author><text>I was &amp;quot;enlightened&amp;quot; many years ago when I asked a colleague (a great electronic engineer) why we didn&amp;#x27;t do fast task switching by having two sets of registers.  His reply was that this would require every regular access to a register to go through an extra gate (to decide which bank of registers you want to hit), making every access slightly slower.&lt;p&gt;Larger registers&amp;#x2F;caches&amp;#x2F;memories are slower because they need more address decoding, that time scaling approximately linearly as the storage doubles in size.</text></item></parent_chain><comment><author>brigade</author><text>For all the siblings describing various forms of register banking, you&amp;#x27;re actually literally describing SMT in which one core executes two or more tasks at the same time, dividing the register set and other processor resources between the threads and effectively switching between the tasks every cycle. Modern x86, Power, and SPARC CPUs implement this, as do basically all GPUs for a while now, all for very good reasons.&lt;p&gt;Which is to say, it&amp;#x27;s quite easy for low-level architectural knowledge to become obsolete :p</text></comment>
<story><title>Why do CPUs have multiple cache levels?</title><url>https://fgiesen.wordpress.com/2016/08/07/why-do-cpus-have-multiple-cache-levels/</url></story><parent_chain><item><author>rwmj</author><text>I was &amp;quot;enlightened&amp;quot; many years ago when I asked a colleague (a great electronic engineer) why we didn&amp;#x27;t do fast task switching by having two sets of registers.  His reply was that this would require every regular access to a register to go through an extra gate (to decide which bank of registers you want to hit), making every access slightly slower.&lt;p&gt;Larger registers&amp;#x2F;caches&amp;#x2F;memories are slower because they need more address decoding, that time scaling approximately linearly as the storage doubles in size.</text></item></parent_chain><comment><author>pkroll</author><text>As cesarb points out the ARM did that, and so did the Z-80 IIRC: basically, your friend was either trolling you or had no idea what he was saying. Addressing is done in parallel. The address decoding isn&amp;#x27;t the part that drinks time.</text></comment>