<story><title>Why is Apple&apos;s M1 chip so fast?</title><url>https://erik-engheim.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2</url></story><parent_chain><item><author>benjaminl</author><text>Unlike what has been said on Twitter the answer to why the M1 is fast isn’t due to technical tricks, but due to Apple throwing a lot of hardware at the problem.&lt;p&gt;The M1 is really wide (8 wide decode) and has a lot of execution units. It has a huge 630 deep reorder buffer to keep them all filled, multiple large caches and a lot of memory bandwidth.&lt;p&gt;It is just a monster of a chip, well designed balanced and executed.&lt;p&gt;BTW this isn’t really new. Apple has been making incremental progress year by year on these processor for their A-series chips. Just nobody believed those Geekbench benchmarks showing that in short benchmarks your phone could be faster than your laptop. Well turns out that given the right cooling solution those benchmarks were accurate.&lt;p&gt;Anandtech has a wonderful deep dive into the processor architecture.&lt;p&gt;&lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;www.anandtech.com&amp;#x2F;show&amp;#x2F;16226&amp;#x2F;apple-silicon-m1-a14-deep-dive&amp;#x2F;2&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;www.anandtech.com&amp;#x2F;show&amp;#x2F;16226&amp;#x2F;apple-silicon-m1-a14-de...&lt;/a&gt;&lt;p&gt;Edit: I didn’t mean to disparage Apple or the M1 by saying that Apple threw hardware at the problem. That Apple was able to keep power low with such a wide chip is extremely impressive and speaks to how finely tuned the chip is. I was trying to say that Apple got the results they did the hard way by advancing every aspect of the chip.</text></item></parent_chain><comment><author>rayiner</author><text>The answer of wide decode and deep reorder buffer gets much closer than the “tricks” mentioned in tweets. That still doesn’t explain how Apple built an 8-wide CPU with such deep OOO that operates on 10-15 watts.&lt;p&gt;The limit that keeps you from arbitrarily scaling up these numbers isn’t transistor count. It’s delay—how long it takes for complex circuits to settle, which drives the top clock speed. And it’s also power usage. The timing delay of many circuits inside a CPU scare super-linearly with things like decode width. For example, the delay in the decode stage itself scales quadratically with the width of the decoder: ftp:&amp;#x2F;&amp;#x2F;ftp.cs.wisc.edu&amp;#x2F;sohi&amp;#x2F;trs&amp;#x2F;complexity.1328.pdf (p. 15). The delay of the issue queues is quadratic both in the issue width and the depth of the queues. The delay of a full bypass network is quadratic in execution width. Decoding N instructions at a time also requires a register renaming unit that can perform register renaming for that many instructions per cycle, and the register file must have enough ports  to be able to feed 2-3 operands to N different instructions per cycle. Additionally, big, multi-ported register files, deep and wide issue queues, and big reorder buffers also tend to be extremely power hungry.&lt;p&gt;On the flip side, the conventional wisdom is that most code doesn’t have enough inherent parallelism to take advantage of an 8-wide machine: &lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;www.realworldtech.com&amp;#x2F;shrinking-cpu&amp;#x2F;2&amp;#x2F;&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;www.realworldtech.com&amp;#x2F;shrinking-cpu&amp;#x2F;2&amp;#x2F;&lt;/a&gt; (“The first sign that the party was over was diminishing returns from wider and wider superscalar designs. As CPUs went from being capable of executing 1, to 2, to 4, to even 6 instructions per cycle, the percentage of cycles during which they actually hit their full potential was dropping rapidly as both a function of increasing width and increasing clock rate.”). At the very least, such designs tend to be very application-dependent. Branch-y integer code like compilers tend to perform poorly on such wide and slow designs. The M1 by contrast manages to come close to Zen 3, which is already a high ILP CPU to begin with, despite a large clock speed deficit (3.2 ghz versus 5 ghz). And the performance seems to be robust—doing well on everything from compilation to scientific kernels. That’s really phenomenal and blows a lot of the conventional wisdom out of the water.&lt;p&gt;An insane amount of good engineering went into this CPU.</text></comment>
<story><title>Why is Apple&apos;s M1 chip so fast?</title><url>https://erik-engheim.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2</url></story><parent_chain><item><author>benjaminl</author><text>Unlike what has been said on Twitter the answer to why the M1 is fast isn’t due to technical tricks, but due to Apple throwing a lot of hardware at the problem.&lt;p&gt;The M1 is really wide (8 wide decode) and has a lot of execution units. It has a huge 630 deep reorder buffer to keep them all filled, multiple large caches and a lot of memory bandwidth.&lt;p&gt;It is just a monster of a chip, well designed balanced and executed.&lt;p&gt;BTW this isn’t really new. Apple has been making incremental progress year by year on these processor for their A-series chips. Just nobody believed those Geekbench benchmarks showing that in short benchmarks your phone could be faster than your laptop. Well turns out that given the right cooling solution those benchmarks were accurate.&lt;p&gt;Anandtech has a wonderful deep dive into the processor architecture.&lt;p&gt;&lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;www.anandtech.com&amp;#x2F;show&amp;#x2F;16226&amp;#x2F;apple-silicon-m1-a14-deep-dive&amp;#x2F;2&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;www.anandtech.com&amp;#x2F;show&amp;#x2F;16226&amp;#x2F;apple-silicon-m1-a14-de...&lt;/a&gt;&lt;p&gt;Edit: I didn’t mean to disparage Apple or the M1 by saying that Apple threw hardware at the problem. That Apple was able to keep power low with such a wide chip is extremely impressive and speaks to how finely tuned the chip is. I was trying to say that Apple got the results they did the hard way by advancing every aspect of the chip.</text></item></parent_chain><comment><author>sliken</author><text>You mention most of the big changes, except one.  Assuming a random (but TLB friendly) pattern the M1 manages a latency of around 30-33ns to main memory, about half of what I&amp;#x27;ve seen anywhere else.  Impressive.&lt;p&gt;Maybe motherboards should stop coming with dimms and use the apple approach to get great bandwidth and latency and come in 16, 32, and 64GB varieties by soldering LPDDR4x on the motherboard.</text></comment>