<story><title>Where’s the Apple M2?</title><url>https://www.tbray.org/ongoing/When/202x/2021/07/12/Slow-M1</url></story><parent_chain><item><author>dev_tty01</author><text>Hmm.  Not very interesting take.  First, the M1 is the 12th chip design in the Apple Silicon series (excluding the X variants).  They have cranked out a more capable, higher performing, lower power chip every year since 2010.&lt;p&gt;&lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;en.wikipedia.org&amp;#x2F;wiki&amp;#x2F;Apple_silicon&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;en.wikipedia.org&amp;#x2F;wiki&amp;#x2F;Apple_silicon&lt;/a&gt;&lt;p&gt;Second, it&amp;#x27;s not about clock rate.  That is only one small part of the story.  It is really about instructions per cycle per core.  Apple is killing it on that front and running wider at lower rates is a big part of how they are outperforming in performance per watt while still winning in single core performance.  We may see some clock rate increase in an M2, but I suspect their basic design philosophy won&amp;#x27;t change.  It is just working too well.&lt;p&gt;For the curious, see &lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;travisdowns.github.io&amp;#x2F;blog&amp;#x2F;2019&amp;#x2F;06&amp;#x2F;11&amp;#x2F;speed-limits.html#ooo-table&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;travisdowns.github.io&amp;#x2F;blog&amp;#x2F;2019&amp;#x2F;06&amp;#x2F;11&amp;#x2F;speed-limits.h...&lt;/a&gt;.&lt;p&gt;That table shows that the M1 has a much bigger reorder buffer, large load and store buffers, huge integer and vector register files, way more branches in flight, etc.  By eschewing high clock rates, they are able to really go after massive concurrency at the hardware level in a single core.  7 simultaneous integer operations, 4 simultaneous floating point, multiple load and store.  It&amp;#x27;s a beast.&lt;p&gt;&lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;www.anandtech.com&amp;#x2F;show&amp;#x2F;16226&amp;#x2F;apple-silicon-m1-a14-deep-dive&amp;#x2F;2&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;www.anandtech.com&amp;#x2F;show&amp;#x2F;16226&amp;#x2F;apple-silicon-m1-a14-de...&lt;/a&gt;&lt;p&gt;Of course they will come out with an M2 soon.  They&amp;#x27;ve been doing this year after year for over a decade.</text></item></parent_chain><comment><author>gopalv</author><text>&amp;gt; 7 simultaneous integer operations, 4 simultaneous floating poin&lt;p&gt;The floating point is going to be an interesting thing to look at - the CPUs made targeting HPC workloads tend to be flops heavy, but the flops tend to be starved for memory bandwidth unless you&amp;#x27;re doing exactly the best vector processing you can &amp;amp; that fortran can do a great job with.&lt;p&gt;So you throw in a lot more oomph on the vector side and leave single operation float arithmetic at 2.&lt;p&gt;Floating point operations of a smaller size of values (more realistically, quarternions or rgba) would be the reason that M1 feels a little bit more snappy when it comes to basic things like text-layout code or graphics images which don&amp;#x27;t do SIMD very well, but still consume a lot of arithmetic.&lt;p&gt;I&amp;#x27;d suspect that the vertical integration is going to be the secret, because it looks like more profile information of desktop apps going into chip design here.&lt;p&gt;A similar story is expected of the Graviton series as well, with AWS having a good idea what to build for.</text></comment>
<story><title>Where’s the Apple M2?</title><url>https://www.tbray.org/ongoing/When/202x/2021/07/12/Slow-M1</url></story><parent_chain><item><author>dev_tty01</author><text>Hmm.  Not very interesting take.  First, the M1 is the 12th chip design in the Apple Silicon series (excluding the X variants).  They have cranked out a more capable, higher performing, lower power chip every year since 2010.&lt;p&gt;&lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;en.wikipedia.org&amp;#x2F;wiki&amp;#x2F;Apple_silicon&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;en.wikipedia.org&amp;#x2F;wiki&amp;#x2F;Apple_silicon&lt;/a&gt;&lt;p&gt;Second, it&amp;#x27;s not about clock rate.  That is only one small part of the story.  It is really about instructions per cycle per core.  Apple is killing it on that front and running wider at lower rates is a big part of how they are outperforming in performance per watt while still winning in single core performance.  We may see some clock rate increase in an M2, but I suspect their basic design philosophy won&amp;#x27;t change.  It is just working too well.&lt;p&gt;For the curious, see &lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;travisdowns.github.io&amp;#x2F;blog&amp;#x2F;2019&amp;#x2F;06&amp;#x2F;11&amp;#x2F;speed-limits.html#ooo-table&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;travisdowns.github.io&amp;#x2F;blog&amp;#x2F;2019&amp;#x2F;06&amp;#x2F;11&amp;#x2F;speed-limits.h...&lt;/a&gt;.&lt;p&gt;That table shows that the M1 has a much bigger reorder buffer, large load and store buffers, huge integer and vector register files, way more branches in flight, etc.  By eschewing high clock rates, they are able to really go after massive concurrency at the hardware level in a single core.  7 simultaneous integer operations, 4 simultaneous floating point, multiple load and store.  It&amp;#x27;s a beast.&lt;p&gt;&lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;www.anandtech.com&amp;#x2F;show&amp;#x2F;16226&amp;#x2F;apple-silicon-m1-a14-deep-dive&amp;#x2F;2&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;www.anandtech.com&amp;#x2F;show&amp;#x2F;16226&amp;#x2F;apple-silicon-m1-a14-de...&lt;/a&gt;&lt;p&gt;Of course they will come out with an M2 soon.  They&amp;#x27;ve been doing this year after year for over a decade.</text></item></parent_chain><comment><author>zelon88</author><text>Why doesn&amp;#x27;t anyone ever bother to mention that the M1 is a RISC CPU when discussing that it can do more IPS than x86?&lt;p&gt;There are 1024 possible Armv8 instructions [1] as opposed to 1,503 x86 instructions [2] and 3,684 x86-64 instructions [3]. There are things x86 and x86-64 can do in a single instruction that would take dozens of instructions to accomplish on Arm.&lt;p&gt;[1] &lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;www.csie.ntu.edu.tw&amp;#x2F;~cyy&amp;#x2F;courses&amp;#x2F;assembly&amp;#x2F;10fall&amp;#x2F;lectures&amp;#x2F;handouts&amp;#x2F;lec09_ARMisa.pdf&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;www.csie.ntu.edu.tw&amp;#x2F;~cyy&amp;#x2F;courses&amp;#x2F;assembly&amp;#x2F;10fall&amp;#x2F;lec...&lt;/a&gt;&lt;p&gt;[2] &lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;fgiesen.wordpress.com&amp;#x2F;2016&amp;#x2F;08&amp;#x2F;25&amp;#x2F;how-many-x86-instructions-are-there&amp;#x2F;&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;fgiesen.wordpress.com&amp;#x2F;2016&amp;#x2F;08&amp;#x2F;25&amp;#x2F;how-many-x86-instru...&lt;/a&gt;&lt;p&gt;[3] &lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;www.csie.ntu.edu.tw&amp;#x2F;~cyy&amp;#x2F;courses&amp;#x2F;assembly&amp;#x2F;10fall&amp;#x2F;lectures&amp;#x2F;handouts&amp;#x2F;lec09_ARMisa.pdf&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;www.csie.ntu.edu.tw&amp;#x2F;~cyy&amp;#x2F;courses&amp;#x2F;assembly&amp;#x2F;10fall&amp;#x2F;lec...&lt;/a&gt;</text></comment>