<story><title>Microsoft ports Windows 10, Linux to homegrown “E2” CPU design</title><url>https://www.theregister.co.uk/2018/06/18/microsoft_e2_edge_windows_10/</url></story><parent_chain><item><author>tinus_hn</author><text>The obvious answer is to completely to the instructions the cpu uses internally. That would mean recompiling for every cpu revision though.</text></item><item><author>PeCaN</author><text>I like that this architecture tackles a large problem in existing architectures, which Mike Pall put rather nicely:&lt;p&gt;&amp;gt; All modern and advanced compilers convert source code through various stages and representation into an internal data-flow representation, usually a variant of SSA. The compiler backend converts that back to an imperative representation, i.e. machine code. That entails many complicated transforms e.g. register allocation, instruction selection, instruction scheduling and so on. Lots of heuristics are used to tame their NP-complete nature. That implies missing some optimization opportunities, of course.&lt;p&gt;&amp;gt; OTOH a modern CPU uses super-scalar and out-of-order execution. So the first thing it has to do, is to perform data-flow analysis on the machine code to turn that back into an (implicit) data-flow representation! Otherwise the CPU cannot analyze the dependencies between instructions.&lt;p&gt;&amp;gt; Sounds wasteful? Oh, yes, it is. Mainly due to the impedance loss between the various stages, representations and abstractions.&lt;p&gt;&lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;www.freelists.org&amp;#x2F;post&amp;#x2F;luajit&amp;#x2F;Ramblings-on-languages-and-architectures-was-Re-any-benefit-to-throwing-off-lua51-constraints&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;www.freelists.org&amp;#x2F;post&amp;#x2F;luajit&amp;#x2F;Ramblings-on-languages...&lt;/a&gt;</text></item></parent_chain><comment><author>zik</author><text>That approach has (sort of) been tried before for superscalar architectures. VLIW architectures were the Next Big Thing in the early 1990s. The general idea is that the machine code explicitly told the CPU what to do with each of its execution units. It seems like a good idea. Intel released their i860 processor and waited for the cash to roll in.&lt;p&gt;The trouble was that because the machine code is pretty specific to the internal structure of the CPU every time they released a new major revision of the CPU the existing executables all had to be recompiled. All of their customers needed to get an entirely new OS, new third party software, they had to recompile all their own code, everything. This proved too much of a burden for many and popularity of the architecture suffered.&lt;p&gt;The other problem of these kinds of architectures is that they&amp;#x27;re quite inefficient at encoding code with lacks inherent parallelism. The instructions are long and most of them have to be NOPs if most of the execution units are idle - which is a lot of the time. This code bloat in turn wastes memory bandwidth and instruction cache space, making them overall not as efficient at using precious cache space as architectures with more compact instructions.</text></comment>
<story><title>Microsoft ports Windows 10, Linux to homegrown “E2” CPU design</title><url>https://www.theregister.co.uk/2018/06/18/microsoft_e2_edge_windows_10/</url></story><parent_chain><item><author>tinus_hn</author><text>The obvious answer is to completely to the instructions the cpu uses internally. That would mean recompiling for every cpu revision though.</text></item><item><author>PeCaN</author><text>I like that this architecture tackles a large problem in existing architectures, which Mike Pall put rather nicely:&lt;p&gt;&amp;gt; All modern and advanced compilers convert source code through various stages and representation into an internal data-flow representation, usually a variant of SSA. The compiler backend converts that back to an imperative representation, i.e. machine code. That entails many complicated transforms e.g. register allocation, instruction selection, instruction scheduling and so on. Lots of heuristics are used to tame their NP-complete nature. That implies missing some optimization opportunities, of course.&lt;p&gt;&amp;gt; OTOH a modern CPU uses super-scalar and out-of-order execution. So the first thing it has to do, is to perform data-flow analysis on the machine code to turn that back into an (implicit) data-flow representation! Otherwise the CPU cannot analyze the dependencies between instructions.&lt;p&gt;&amp;gt; Sounds wasteful? Oh, yes, it is. Mainly due to the impedance loss between the various stages, representations and abstractions.&lt;p&gt;&lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;www.freelists.org&amp;#x2F;post&amp;#x2F;luajit&amp;#x2F;Ramblings-on-languages-and-architectures-was-Re-any-benefit-to-throwing-off-lua51-constraints&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;www.freelists.org&amp;#x2F;post&amp;#x2F;luajit&amp;#x2F;Ramblings-on-languages...&lt;/a&gt;</text></item></parent_chain><comment><author>zokier</author><text>Yeah, it was &amp;quot;obvious&amp;quot; to Intel too when they made Itanium. And the rest is history.&lt;p&gt;&amp;gt; the &amp;quot;Itanium&amp;quot; approach that was supposed to be so terrific—until it turned out that the wished-for compilers were basically impossible to write&lt;p&gt;- Donald Knuth, source: &lt;a href=&quot;http:&amp;#x2F;&amp;#x2F;www.informit.com&amp;#x2F;articles&amp;#x2F;article.aspx?p=1193856&quot; rel=&quot;nofollow&quot;&gt;http:&amp;#x2F;&amp;#x2F;www.informit.com&amp;#x2F;articles&amp;#x2F;article.aspx?p=1193856&lt;/a&gt;</text></comment>