<story><title>TSMC confirms 3nm tech for 2022, could enable epic 80B transistor GPUs</title><url>https://www.pcgamer.com/tsmc-confirms-3nm-tech-for-2022-could-enable-epic-80-billion-transistor-gpus/</url></story><parent_chain><item><author>ChuckNorris89</author><text>3nm, 5nm, 7nm are all marketing names now since the fabs switched to 3D transistors and not a measure of any exact feature size.&lt;p&gt;When examined via electron microscope, TSMC&amp;#x27;s 7nm is just slightly denser than Intel&amp;#x27;s 14nm++ and not half the size.&lt;p&gt;&lt;i&gt;“You need to understand that this naming scheme reflects only the process. It’s just the process called 14nm or 7nm … It could be called Intel Blueberry Construction 5 or if it is called AMD Strawberry Process 3, it would give you the same amount of information as having 14nm or 7nm (in the name).”&lt;/i&gt;&lt;p&gt;&lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;www.time24.news&amp;#x2F;2020&amp;#x2F;09&amp;#x2F;der8auer-compares-tsmcs-7nm-process-with-intels-14nm-using-electron-microscope.html&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;www.time24.news&amp;#x2F;2020&amp;#x2F;09&amp;#x2F;der8auer-compares-tsmcs-7nm-...&lt;/a&gt;</text></item><item><author>runeks</author><text>&amp;gt; TSMC reckons its 3nm node will pack in somewhere north of 250 million transistors per square millimetre of silicon [...]&lt;p&gt;&amp;gt; TSMC is already producing chips for Apple’s iPhones on its new 5nm node, which is good for 173 million transistors per square millimetre [...]&lt;p&gt;&lt;i&gt;3nm™&lt;/i&gt;: a transistor is 1 &amp;#x2F; 250e6 = 4e-9 square millimeters, which is sqrt(4e-9) = 63.2 nanometers by nanometers.&lt;p&gt;&lt;i&gt;5nm™&lt;/i&gt;: a transistor is 1 &amp;#x2F; 173e6 = 5.78e-9 square millimeters, which is sqrt(5.78e-9) = 76.0 by 76.0 nanometers.&lt;p&gt;So is it reasonable to say that &lt;i&gt;3nm™&lt;/i&gt; -- compared to &lt;i&gt;5nm™&lt;/i&gt; -- is closer to 63.2 &amp;#x2F; 76.0 * 5 (&lt;i&gt;nm™&lt;/i&gt;) = &lt;i&gt;~4.16nm™&lt;/i&gt;? Ie. a reduction in feature size of ~17%?</text></item></parent_chain><comment><author>petra</author><text>A better measurement would be million transistors per square milimeter(Mtr&amp;#x2F;mm2).&lt;p&gt;So Intel&amp;#x27;s self reported 44Mtr&amp;#x2F;mm2 @ 14nm, and 100Mtr&amp;#x2F;mm2 @ 10nm(but currently 10nm is having problems).&lt;p&gt;Comparing this to Tsmc&amp;#x27;s 170Mtr&amp;#x2F;mm2 @ 7nm and 250Mtr&amp;#x2F;mm2 @ 5nm - is a pretty valid comparison, I think.</text></comment>
<story><title>TSMC confirms 3nm tech for 2022, could enable epic 80B transistor GPUs</title><url>https://www.pcgamer.com/tsmc-confirms-3nm-tech-for-2022-could-enable-epic-80-billion-transistor-gpus/</url></story><parent_chain><item><author>ChuckNorris89</author><text>3nm, 5nm, 7nm are all marketing names now since the fabs switched to 3D transistors and not a measure of any exact feature size.&lt;p&gt;When examined via electron microscope, TSMC&amp;#x27;s 7nm is just slightly denser than Intel&amp;#x27;s 14nm++ and not half the size.&lt;p&gt;&lt;i&gt;“You need to understand that this naming scheme reflects only the process. It’s just the process called 14nm or 7nm … It could be called Intel Blueberry Construction 5 or if it is called AMD Strawberry Process 3, it would give you the same amount of information as having 14nm or 7nm (in the name).”&lt;/i&gt;&lt;p&gt;&lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;www.time24.news&amp;#x2F;2020&amp;#x2F;09&amp;#x2F;der8auer-compares-tsmcs-7nm-process-with-intels-14nm-using-electron-microscope.html&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;www.time24.news&amp;#x2F;2020&amp;#x2F;09&amp;#x2F;der8auer-compares-tsmcs-7nm-...&lt;/a&gt;</text></item><item><author>runeks</author><text>&amp;gt; TSMC reckons its 3nm node will pack in somewhere north of 250 million transistors per square millimetre of silicon [...]&lt;p&gt;&amp;gt; TSMC is already producing chips for Apple’s iPhones on its new 5nm node, which is good for 173 million transistors per square millimetre [...]&lt;p&gt;&lt;i&gt;3nm™&lt;/i&gt;: a transistor is 1 &amp;#x2F; 250e6 = 4e-9 square millimeters, which is sqrt(4e-9) = 63.2 nanometers by nanometers.&lt;p&gt;&lt;i&gt;5nm™&lt;/i&gt;: a transistor is 1 &amp;#x2F; 173e6 = 5.78e-9 square millimeters, which is sqrt(5.78e-9) = 76.0 by 76.0 nanometers.&lt;p&gt;So is it reasonable to say that &lt;i&gt;3nm™&lt;/i&gt; -- compared to &lt;i&gt;5nm™&lt;/i&gt; -- is closer to 63.2 &amp;#x2F; 76.0 * 5 (&lt;i&gt;nm™&lt;/i&gt;) = &lt;i&gt;~4.16nm™&lt;/i&gt;? Ie. a reduction in feature size of ~17%?</text></item></parent_chain><comment><author>stunt</author><text>They are adding more layers. But nobody said there are no other improvements.&lt;p&gt;Up to 30% power reduction, up to 70% logic density gain, and up to 15% performance gain is all that matters.</text></comment>