<story><title>LDM: My Favorite ARM Instruction</title><url>https://keleshev.com/ldm-my-favorite-arm-instruction/</url></story><parent_chain><item><author>thesz</author><text>This instruction makes design of ARM CPUs harder.&lt;p&gt;As an example, consider page fault handling for a situation where part of access is valid and other part is not, especially for store operation. Or out-of-order execution. Or, for whatever sake, &amp;quot;load multiple&amp;quot; from PC (which is exposed to programmer in quite peculiar way) - you have to have it.&lt;p&gt;ARM is full of these quirks. I can see why they did that back in the day, but today or even 30 years ago these quirks are not a good decisions.</text></item></parent_chain><comment><author>panpanna</author><text>Yes, this instruction was removed in 64-bit arm for this very reason.&lt;p&gt;It has been replaced with LDP (load pair, i.e load two registers) which is not nearly as nice for software developers but made the life of the ARM designers much easier. For comparison:&lt;p&gt;&lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;elixir.bootlin.com&amp;#x2F;linux&amp;#x2F;v4.14.52&amp;#x2F;source&amp;#x2F;arch&amp;#x2F;arm64&amp;#x2F;kernel&amp;#x2F;entry.S#L308&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;elixir.bootlin.com&amp;#x2F;linux&amp;#x2F;v4.14.52&amp;#x2F;source&amp;#x2F;arch&amp;#x2F;arm64&amp;#x2F;...&lt;/a&gt;&lt;p&gt;&lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;elixir.bootlin.com&amp;#x2F;linux&amp;#x2F;v4.14.52&amp;#x2F;source&amp;#x2F;arch&amp;#x2F;arm&amp;#x2F;kernel&amp;#x2F;entry-armv.S#L167&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;elixir.bootlin.com&amp;#x2F;linux&amp;#x2F;v4.14.52&amp;#x2F;source&amp;#x2F;arch&amp;#x2F;arm&amp;#x2F;ke...&lt;/a&gt;&lt;p&gt;BUT, I don&amp;#x27;t think we will see real benefits of this unless we remove aarch32 support from ARMv8.</text></comment>
<story><title>LDM: My Favorite ARM Instruction</title><url>https://keleshev.com/ldm-my-favorite-arm-instruction/</url></story><parent_chain><item><author>thesz</author><text>This instruction makes design of ARM CPUs harder.&lt;p&gt;As an example, consider page fault handling for a situation where part of access is valid and other part is not, especially for store operation. Or out-of-order execution. Or, for whatever sake, &amp;quot;load multiple&amp;quot; from PC (which is exposed to programmer in quite peculiar way) - you have to have it.&lt;p&gt;ARM is full of these quirks. I can see why they did that back in the day, but today or even 30 years ago these quirks are not a good decisions.</text></item></parent_chain><comment><author>smallpipe</author><text>Very true, but that’s the classic 32b arch only, aarch64 is much cleaner. The next big A class CPUs will be aarch64 only.</text></comment>