<story><title>Verilog Is Weird</title><url>https://danluu.com/why-hardware-development-is-hard/</url></story><parent_chain></parent_chain><comment><author>Taniwha</author><text>I think that really the hard part of learning to design chip stuff really is other stuff - understanding where&amp;#x2F;how to use storage (flops) and combinatorial logic - and simultaneity: how to handle things that happen at the same time.&lt;p&gt;Initially you really need a strong understanding of digital logic (not a language), in particular pipelines.&lt;p&gt;Once you have that stuff in your head you can turn to verilog (or vhdl or whatever) and learn how to map these ideas into the language&lt;p&gt;In System Verilog it&amp;#x27;s easy this is the only way to reliably make synthesisable flops:&lt;p&gt;&lt;pre&gt;&lt;code&gt;    bit a, b;
    always @(posedge clk)
         a &amp;lt;= b;
&lt;/code&gt;&lt;/pre&gt;
And you can make combinatorial logic 2 ways:&lt;p&gt;&lt;pre&gt;&lt;code&gt;    wire c; bit d;
    assign c = a&amp;amp;b;
    always @(*)
        d = a&amp;amp;b;
&lt;/code&gt;&lt;/pre&gt;
They&amp;#x27;ll make the same gates, notice the use of = vs &amp;lt;=, you typically use the always when you want something more complex&lt;p&gt;&amp;quot;always X&amp;quot; just means loop waiting for X, &amp;#x27;*&amp;#x27; means &amp;quot;anything important changes&amp;quot;&lt;p&gt;That&amp;#x27;s it, the most important concepts you have to get your head around, everything else is just this at scale - also please ignore the async reset in the &amp;quot;Verilog is Weird&amp;quot; example - they tend to be timing nightmares in the real world, use a synchronous reset instead.&lt;p&gt;One more thing - Verilog is an early object oriented language - modules are objects - but they are static, the entire design can be elaborated at compile (or synthesis) time - why? because you can&amp;#x27;t new or malloc more gates on the fly on a real chip - almost everything in verilog is static by design (it does support local variables in functions but anything that&amp;#x27;s vaguely recursive wont make gates in synthesis)</text></comment>
<story><title>Verilog Is Weird</title><url>https://danluu.com/why-hardware-development-is-hard/</url></story><parent_chain></parent_chain><comment><author>jwilk</author><text>&amp;gt; maybe try copy+pasting that URL&lt;p&gt;That doesn&amp;#x27;t work either, because the generator dropped the underscore.&lt;p&gt;&lt;a href=&quot;http:&amp;#x2F;&amp;#x2F;en.wikipedia.org&amp;#x2F;wiki&amp;#x2F;Flip-flop_(electronics)&quot; rel=&quot;nofollow&quot;&gt;http:&amp;#x2F;&amp;#x2F;en.wikipedia.org&amp;#x2F;wiki&amp;#x2F;Flip-flop_(electronics)&lt;/a&gt;&lt;p&gt;Hugo would normally handle such links fine, but earlier on there&amp;#x27;s an unescaped underscore in &amp;quot;d_out&amp;quot;, which makes it go off the rails.</text></comment>