<story><title>Computing sin and cos in hardware with synthesisable Verilog</title><url>http://kierdavis.com/cordic.html</url></story><parent_chain></parent_chain><comment><author>GeertB</author><text>While CORDIC is great for fixed point, it has limitations for floating point. The original 8087 fsin and fcos instructions used CORDIC, but later versions of the architecture switched to polynomial approximations, see &lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;software.intel.com&amp;#x2F;sites&amp;#x2F;default&amp;#x2F;files&amp;#x2F;managed&amp;#x2F;f8&amp;#x2F;9c&amp;#x2F;x87TrigonometricInstructionsVsMathFunctions.pdf&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;software.intel.com&amp;#x2F;sites&amp;#x2F;default&amp;#x2F;files&amp;#x2F;managed&amp;#x2F;f8&amp;#x2F;9c...&lt;/a&gt;. Today it&amp;#x27;s possible to develop implementations of these elementary functions on x86 CPUs that are more precise and more performant using regular multiply&amp;#x2F;addition&amp;#x2F;fused multiply add than even the current improved post-CORDIC fsin and fcos functions.&lt;p&gt;The main issue is that having an instruction executing a fixed-function block with a given (high) latency and little if any pipelining tends to be far worse than having many more fully pipelined multiply&amp;#x2F;add instructions. The other issue is that argument reduction and approximation over the reduced domain are not independent. For some parts of the domain, such as computing the sine of a number very close to a multiple of pi, you may need to spend more cycles reducing the argument accurately to counter cancelation effects. However, as the reduced argument is then very close to zero, a simple polynomial suffices.&lt;p&gt;So, for most modern systems, I&amp;#x27;d put the effort in efficient pipelined fused-multiply-add and use that for all elementary functions. Fixed-function hardware for elementary functions has generally been proved sub-optimal.</text></comment>
<story><title>Computing sin and cos in hardware with synthesisable Verilog</title><url>http://kierdavis.com/cordic.html</url></story><parent_chain></parent_chain><comment><author>hatsunearu</author><text>Oh wow, I literally &lt;i&gt;just&lt;/i&gt; finished my quadrature sinusoid DDS generator using MyHDL last night. I didn&amp;#x27;t use CORDIC but rather a LUT. I found out I can optimize generating quadrature sinusoids by having two separate LUTs where each one stores from 0 to pi&amp;#x2F;2 and the other from pi&amp;#x2F;2 to pi, and this has an advantage because when the sine output takes inputs from the first LUT, the cos output takes inputs from the second LUT and vice versa, thus saving duplicates.&lt;p&gt;I&amp;#x27;m still cleaning up the testbench code and I plan to put out a blog post here if y&amp;#x27;all are interested: hatsunearu.github.io</text></comment>