<story><title>Intel announces Cascade Lake Xeons: 48 cores and 12-channel memory per socket</title><url>https://arstechnica.com/gadgets/2018/11/intel-announces-cascade-lake-xeons-48-cores-and-12-channel-memory-per-socket/</url></story><parent_chain><item><author>SantiagoElf</author><text>Desperate move by Intel. They are stuck with Cascade Lake until 2021, when their &amp;#x27;new&amp;#x27; architecture will be available.
In order this Xeon to be under 300W TDP, they disabled the Hyper Threading and when they benchmark vs AMD Epyc they disabled AMD&amp;#x27;s SMT. Just wow.</text></item></parent_chain><comment><author>einr</author><text>Not only that, but they also apparently recompiled Linpack with the Intel compiler -- which is notorious for favoring Intel chips -- before running the benchmarks. Some really shady stuff going on here.</text></comment>
<story><title>Intel announces Cascade Lake Xeons: 48 cores and 12-channel memory per socket</title><url>https://arstechnica.com/gadgets/2018/11/intel-announces-cascade-lake-xeons-48-cores-and-12-channel-memory-per-socket/</url></story><parent_chain><item><author>SantiagoElf</author><text>Desperate move by Intel. They are stuck with Cascade Lake until 2021, when their &amp;#x27;new&amp;#x27; architecture will be available.
In order this Xeon to be under 300W TDP, they disabled the Hyper Threading and when they benchmark vs AMD Epyc they disabled AMD&amp;#x27;s SMT. Just wow.</text></item></parent_chain><comment><author>c2h5oh</author><text>One theory is that the new xeon comes with no HT to keep the power draw under 300W, which is why the footnotes mention no HT&amp;#x2F;SMT in test configuration...&lt;p&gt;This would also &amp;quot;fix&amp;quot; a lot of side channel attacks without new silicon being ready and Intel claims this CPU includes some hardware mitigations.</text></comment>