<story><title>Verilog Is Weird</title><url>https://danluu.com/why-hardware-development-is-hard/</url></story><parent_chain></parent_chain><comment><author>Taniwha</author><text>I think that really the hard part of learning to design chip stuff really is other stuff - understanding where&amp;#x2F;how to use storage (flops) and combinatorial logic - and simultaneity: how to handle things that happen at the same time.&lt;p&gt;Initially you really need a strong understanding of digital logic (not a language), in particular pipelines.&lt;p&gt;Once you have that stuff in your head you can turn to verilog (or vhdl or whatever) and learn how to map these ideas into the language&lt;p&gt;In System Verilog it&amp;#x27;s easy this is the only way to reliably make synthesisable flops:&lt;p&gt;&lt;pre&gt;&lt;code&gt;    bit a, b;
    always @(posedge clk)
         a &amp;lt;= b;
&lt;/code&gt;&lt;/pre&gt;
And you can make combinatorial logic 2 ways:&lt;p&gt;&lt;pre&gt;&lt;code&gt;    wire c; bit d;
    assign c = a&amp;amp;b;
    always @(*)
        d = a&amp;amp;b;
&lt;/code&gt;&lt;/pre&gt;
They&amp;#x27;ll make the same gates, notice the use of = vs &amp;lt;=, you typically use the always when you want something more complex&lt;p&gt;&amp;quot;always X&amp;quot; just means loop waiting for X, &amp;#x27;*&amp;#x27; means &amp;quot;anything important changes&amp;quot;&lt;p&gt;That&amp;#x27;s it, the most important concepts you have to get your head around, everything else is just this at scale - also please ignore the async reset in the &amp;quot;Verilog is Weird&amp;quot; example - they tend to be timing nightmares in the real world, use a synchronous reset instead.&lt;p&gt;One more thing - Verilog is an early object oriented language - modules are objects - but they are static, the entire design can be elaborated at compile (or synthesis) time - why? because you can&amp;#x27;t new or malloc more gates on the fly on a real chip - almost everything in verilog is static by design (it does support local variables in functions but anything that&amp;#x27;s vaguely recursive wont make gates in synthesis)</text></comment>
<story><title>Verilog Is Weird</title><url>https://danluu.com/why-hardware-development-is-hard/</url></story><parent_chain></parent_chain><comment><author>tails4e</author><text>Any idea when this was written? It seems a bit out dated, and I&amp;#x27;m especially surprised at the mention of hardware companies not using linters, that seems insane to me. Lint, Logic Equalivance, CDC, etc are all absolutely required sanity checks on hardware design, irrespective of the language. Also SystemVerilog is quite esperessive. I definitely agree Verilog has many pitfalls you basically get used to and know to avoid, but I don&amp;#x27;t agree that knowing in your head the hardware that will be generated is a bad thing. Knowing how the hardware will be constructed from your code is key to getting it running at 4Ghz instead of 100Mhz. What your code will infer could be less or more area efficient, etc. Modern synthesis tools do help map sometimes inefficient code to the right hardware, but still knowing what it should create is a positive thing.</text></comment>