<story><title>Epiphany-V: A 1024-core 64-bit RISC processor</title><url>https://www.parallella.org/2016/10/05/epiphany-v-a-1024-core-64-bit-risc-processor/?</url></story><parent_chain><item><author>mamcx</author><text>I have a naive question based in my dreams:&lt;p&gt;Is possible to design a CPU that ON-DEMAND switch between parallel and linear operation? So, if we have a 1000 cores, it switch to 10 with the linear power of 10 x 10?&lt;p&gt;In my dreams this was very usefull, but wonder how feasible clould be ;)</text></item><item><author>valarauca1</author><text>Two things immediately jump out&lt;p&gt;&lt;pre&gt;&lt;code&gt;    Custom ISA extensions for deep learning, communication, and cryptography
    DARPA&amp;#x2F;MTO
    autonomous drones cognitive radio
&lt;/code&gt;&lt;/pre&gt;
The radar geeks are gonna love to get their hands on ~250GFLOP, 4watt processor.</text></item></parent_chain><comment><author>pjc50</author><text>No.&lt;p&gt;Basically the limiting factor in most designs isn&amp;#x27;t so much arithmetic as fetches and branches. Especially cache misses. Theses are inherently linear operations - if you need to fetch from memory and then jump based on the result, for example.&lt;p&gt;Superscalar &amp;#x27;cheats&amp;#x27; somewhat by spending area to keep the pipeline fed, through branch prediction and suchlike.&lt;p&gt;The nearest thing is the graphics card, which has a very large number of arithmetic units but less flow control, so you can run the same subroutine on lots of different data in parallel.&lt;p&gt;Highly multicore chips make a different tradeoff: external memory bandwidth is &lt;i&gt;very&lt;/i&gt; limited. Ideal for video codecs etc where you can take a small chunk and chew heavily. Very bad for running random unadapted C code, Java etc.</text></comment>
<story><title>Epiphany-V: A 1024-core 64-bit RISC processor</title><url>https://www.parallella.org/2016/10/05/epiphany-v-a-1024-core-64-bit-risc-processor/?</url></story><parent_chain><item><author>mamcx</author><text>I have a naive question based in my dreams:&lt;p&gt;Is possible to design a CPU that ON-DEMAND switch between parallel and linear operation? So, if we have a 1000 cores, it switch to 10 with the linear power of 10 x 10?&lt;p&gt;In my dreams this was very usefull, but wonder how feasible clould be ;)</text></item><item><author>valarauca1</author><text>Two things immediately jump out&lt;p&gt;&lt;pre&gt;&lt;code&gt;    Custom ISA extensions for deep learning, communication, and cryptography
    DARPA&amp;#x2F;MTO
    autonomous drones cognitive radio
&lt;/code&gt;&lt;/pre&gt;
The radar geeks are gonna love to get their hands on ~250GFLOP, 4watt processor.</text></item></parent_chain><comment><author>wmf</author><text>There has been a bunch of academic research about this topic under names like core fusion and dynamic multicore. A recent sample: &lt;a href=&quot;https:&amp;#x2F;&amp;#x2F;www.microsoft.com&amp;#x2F;en-us&amp;#x2F;research&amp;#x2F;wp-content&amp;#x2F;uploads&amp;#x2F;2016&amp;#x2F;02&amp;#x2F;2013-hpca-t3.pdf&quot; rel=&quot;nofollow&quot;&gt;https:&amp;#x2F;&amp;#x2F;www.microsoft.com&amp;#x2F;en-us&amp;#x2F;research&amp;#x2F;wp-content&amp;#x2F;uploads&amp;#x2F;...&lt;/a&gt;</text></comment>