<story><title>PCI-Sig Releases 256GBps PCIe 6.0 X16 Spec</title><url>https://www.servethehome.com/pci-sig-releases-256gbps-pcie-6-0-x16-spec/</url></story><parent_chain><item><author>azalemeth</author><text>Stupid question from me: how the hell do they prototype and debug this? It&amp;#x27;s very far from my EE knowledge. Communication analysers will show the eye diagram and tell you a lot about stray capacitance and inductance, but I know that most 10GSa&amp;#x2F;s+ devices cost more than a house and have a tendency to live in a lab for a long time. It seems to my mind like there are so many difficulties in driving pci-e fast, from timing to voltage drop and current limitations. All of this must be implemented, somehow, if the spec is finalised. Right? They wouldn&amp;#x27;t write it up otherwise (right?!).&lt;p&gt;So -- how do you prove that your infrastructure can blow the socks off everything without building two of them and testing?</text></item></parent_chain><comment><author>Lramseyer</author><text>Not a stupid question at all!&lt;p&gt;Any communication protocol has functional layers to them, and at the very bottom is what&amp;#x27;s called the Phy layer (or physical layer.) While pretty much every layer can be implemented in digital logic, the physical layer has a lot of analog circuitry. (It&amp;#x27;s programmable analog circuitry, so it&amp;#x27;s technically mixed signal.) Most wired communication protocols that you are familiar with (including SAS&amp;#x2F;SATA, USB, HDMI&amp;#x2F;DP, PCIe&amp;#x2F;NVMe, and Ethernet) all use what&amp;#x27;s known as a &amp;quot;SerDes Phy&amp;quot; which is short for Serializer Deserializer. It takes parallel data in, and serializes it to transmit data, and does the reverse when receiving data. In the example of PCIe Gen 4, it takes 32 bits of data in at 500 Mb&amp;#x2F;s (per bit) and serializes it to 16 Gb&amp;#x2F;s.&lt;p&gt;Because the SerDes Phy is such a common part of all communication protocols, it&amp;#x27;s often reused in other designs. For example - a GPU may use the same SerDes Phy design for its PCIe lanes as it does for its HDMI ports (at least on the transmit side.) They are however programmed differently.&lt;p&gt;Because these designs see so much reuse in so many different chips, there are companies that specialize in designing SerDes Phys, and their development is usually ahead of protocol development. Though in today&amp;#x27;s day and age, it&amp;#x27;s super complicated, and consists of way more than shift registers and a PLL. But there are SerDes designs that exist in products that are capable of 112Gb&amp;#x2F;s (not sure if 224Gb&amp;#x2F;s exists outside of test chips yet.)&lt;p&gt;You can buy modern FPGAs that have PCIe Gen 5, but with a SerDes Phy capable of going way faster. And if you want, you could bypass that hard block and talk straight to the SerDes, and program your own PCIe 6.0 controller.&lt;p&gt;But to answer your question on how they prototype it and test it, they run computer simulations that are exceedingly complicated and slow, and once a test chip comes back from the fab, eye diagrams are usually collected using what&amp;#x27;s known as a repeating signal scope. Since it&amp;#x27;s insanely difficult to sample a 112Gb&amp;#x2F;s signal at any reasonable resolution, it&amp;#x27;s sampled statistically (in time) over billions of samples, and plotted by knowing the frequency of the target signal. An eye diagram is what comes out of a traditional NRZ (non return to zero) where each cycle represents either a 1 or a 0. In an eye diagram, you see all permutations of bit transitions overlayed on each other, since you&amp;#x27;re sampling billions of cycles statistically. This is important because you can see other anomalies of your signal like jitter and rise&amp;#x2F;fall times.&lt;p&gt;There&amp;#x27;s a lot more to it, and this comment is already getting to be a wall of text but definitely feel free to ask more questions!</text></comment>
<story><title>PCI-Sig Releases 256GBps PCIe 6.0 X16 Spec</title><url>https://www.servethehome.com/pci-sig-releases-256gbps-pcie-6-0-x16-spec/</url></story><parent_chain><item><author>azalemeth</author><text>Stupid question from me: how the hell do they prototype and debug this? It&amp;#x27;s very far from my EE knowledge. Communication analysers will show the eye diagram and tell you a lot about stray capacitance and inductance, but I know that most 10GSa&amp;#x2F;s+ devices cost more than a house and have a tendency to live in a lab for a long time. It seems to my mind like there are so many difficulties in driving pci-e fast, from timing to voltage drop and current limitations. All of this must be implemented, somehow, if the spec is finalised. Right? They wouldn&amp;#x27;t write it up otherwise (right?!).&lt;p&gt;So -- how do you prove that your infrastructure can blow the socks off everything without building two of them and testing?</text></item></parent_chain><comment><author>dragontamer</author><text>I&amp;#x27;m not in EE, but I&amp;#x27;d imagine that you start with x1 lane and work your way up.&lt;p&gt;Each PCIe lane is an independent SERDES. Its not like a parallel memory controller where they share a clock, when you have x16 lanes, you have 16x independent streams you&amp;#x27;re shoving to the device downstream.</text></comment>