<story><title>An Open-Source FPGA-Optimized Out-of-Order RISC-V Soft Processor (2019) [pdf]</title><url>http://www.rsg.ci.i.u-tokyo.ac.jp/members/shioya/pdfs/Mashimo-FPT%2719.pdf</url></story><parent_chain><item><author>jeff-davis</author><text>If I understand this correctly:&lt;p&gt;Typically, I think of an FPGA as something used to accelerate specialized operations. But sometimes, in the middle of one of these specialized operations, you might want to do something more general, like run a network stack, without returning to the CPU. A soft processor like this allows you to run an ordinary network stack (with ordinary code) inside the FPGA.&lt;p&gt;Is that right?&lt;p&gt;I thought one of the things people used FPGAs for was accelerating network stacks, so I don&amp;#x27;t quite know why you&amp;#x27;d want to use a soft processor for that. But it does make sense that you&amp;#x27;d want to be able to run ordinary code in an FPGA (as part of a larger FPGA operation that is not ordinary code).&lt;p&gt;EDIT: Also, I don&amp;#x27;t understand this statement: &amp;quot;for example,  one main compute kernel, which is too complex to deploy on dedicated hardware, is run by specialized soft processors&amp;quot;. What do the authors mean &amp;quot;too complex to deploy on dedicated hardware&amp;quot;?</text></item><item><author>Symmetry</author><text>To push this up from the comments, if you&amp;#x27;re interested in why this is important or what the authors are trying to do the PDF where they describe their approach and architecture is really interesting.&lt;p&gt;&lt;a href=&quot;http:&amp;#x2F;&amp;#x2F;www.rsg.ci.i.u-tokyo.ac.jp&amp;#x2F;members&amp;#x2F;shioya&amp;#x2F;pdfs&amp;#x2F;Mashimo-FPT&amp;#x27;19.pdf&quot; rel=&quot;nofollow&quot;&gt;http:&amp;#x2F;&amp;#x2F;www.rsg.ci.i.u-tokyo.ac.jp&amp;#x2F;members&amp;#x2F;shioya&amp;#x2F;pdfs&amp;#x2F;Mashim...&lt;/a&gt;</text></item></parent_chain><comment><author>rcxdude</author><text>FPGAs are frequently not connected with a dedicated CPU at all, and even when they are they may be connected over a link with lower bandwidth&amp;#x2F;higher latency than you would like. In these cases you usually have a bunch of management and logic tasks which are better suited to a CPU (basically anything with a large number of different serial steps and complex control flow will probably synthesize poorly directly to an FPGA: this is probably what the authors described as &amp;#x27;too complex for dedicated hardware&amp;#x27;), so you synthesize a CPU in the FPGA fabric which usually has a direct memory map to whatever registers you need in the FPGA design to accomplish your goals. This is common enough basically every FPGA vendor also sells FPGA SOCs which have a hard CPU attached to the fabric, and if you are using one of those then you will generally not synthesize a CPU in the fabric because it&amp;#x27;ll usually be slower and less power efficient than the hard CPU you have. But that CPU also isn&amp;#x27;t free and if your CPU compute requirements are not particularly high than the soft CPU might be more efficient for your usecare (or a hard CPU may not be an option in the range you need).</text></comment>
<story><title>An Open-Source FPGA-Optimized Out-of-Order RISC-V Soft Processor (2019) [pdf]</title><url>http://www.rsg.ci.i.u-tokyo.ac.jp/members/shioya/pdfs/Mashimo-FPT%2719.pdf</url></story><parent_chain><item><author>jeff-davis</author><text>If I understand this correctly:&lt;p&gt;Typically, I think of an FPGA as something used to accelerate specialized operations. But sometimes, in the middle of one of these specialized operations, you might want to do something more general, like run a network stack, without returning to the CPU. A soft processor like this allows you to run an ordinary network stack (with ordinary code) inside the FPGA.&lt;p&gt;Is that right?&lt;p&gt;I thought one of the things people used FPGAs for was accelerating network stacks, so I don&amp;#x27;t quite know why you&amp;#x27;d want to use a soft processor for that. But it does make sense that you&amp;#x27;d want to be able to run ordinary code in an FPGA (as part of a larger FPGA operation that is not ordinary code).&lt;p&gt;EDIT: Also, I don&amp;#x27;t understand this statement: &amp;quot;for example,  one main compute kernel, which is too complex to deploy on dedicated hardware, is run by specialized soft processors&amp;quot;. What do the authors mean &amp;quot;too complex to deploy on dedicated hardware&amp;quot;?</text></item><item><author>Symmetry</author><text>To push this up from the comments, if you&amp;#x27;re interested in why this is important or what the authors are trying to do the PDF where they describe their approach and architecture is really interesting.&lt;p&gt;&lt;a href=&quot;http:&amp;#x2F;&amp;#x2F;www.rsg.ci.i.u-tokyo.ac.jp&amp;#x2F;members&amp;#x2F;shioya&amp;#x2F;pdfs&amp;#x2F;Mashimo-FPT&amp;#x27;19.pdf&quot; rel=&quot;nofollow&quot;&gt;http:&amp;#x2F;&amp;#x2F;www.rsg.ci.i.u-tokyo.ac.jp&amp;#x2F;members&amp;#x2F;shioya&amp;#x2F;pdfs&amp;#x2F;Mashim...&lt;/a&gt;</text></item></parent_chain><comment><author>mng2</author><text>&amp;gt;What do the authors mean &amp;quot;too complex to deploy on dedicated hardware&amp;quot;?&lt;p&gt;It costs time and effort to translate a software function to HDL&amp;#x2F;FPGA, so it&amp;#x27;s not always worth doing. For example you could do TCP&amp;#x2F;IP in hardware, but unless you have particular performance requirements (say HFT) you&amp;#x27;re probably better off with a soft core and a tested software TCP&amp;#x2F;IP stack.&lt;p&gt;Also each feature translated to hardware takes up space in the fabric. When you crunch numbers on an FPGA, it&amp;#x27;s ideal if you can lay out the entire sequence of operations as one big pipeline, so you can keep throughput as high as possible. Sufficiently long or complex sequences may not translate efficiently to FPGA.</text></comment>