refresh release command executed during a first cycle of the at least two cycles and a second refresh release command executed during a second cycle of the at least two cycles. The first refresh release command may include receiving a plurality of control signals having a first predetermined logic combination and the second refresh release command may include receiving the plurality of control signals having the first predetermined logic combination.
According to another aspect of the embodiments, the refresh release command include a first refresh release command executed during a first cycle of the at least two cycles and a second refresh release command executed during a second cycle of the at least two cycles. The first refresh release command may include receiving a plurality of control signals havingplurality of input signals. The release signal output circuit may provide a release signal that releases the refresh mode based on the plurality of input signals in synchronism with the internal clock indicating a refresh release command. The refresh release command may include a first refresh release command and a second refresh release command and the second refresh release command may be received after the first refresh release command. A status latch signal output circuit may be coupled to receive the set signal and the release signal. The status latch signal output circuit may provide a status latch signal indicating a refresh mode state. The refresh mode state may be set in response to the set signal and the refresh mode may be released in response to the