invention, a band-gap reference circuit with offset cancellation is provided that includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first first-state switch, and a first second-state switch. The first PMOS transistor has a source coupled to a power supply. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor and a gate coupled to a first input node. The third PMOS transistor has a source coupled to the power supply and a gate coupled to a gate of the first PMOS transistor. The fourth PMOS transistor has a source coupled to a drain of the third PMOS transistor, a drain coupled to a drain of the second PMOS transistor and to ground,and a gate coupled to a second input node. The first first-state switch is operable to couple the drain of the first PMOS transistor to the gate of the first PMOS transistor when the band-gap reference circuit is in a first state. The first second-state switch is operable to couple the drain of the third PMOS transistor to the gate of the third PMOS transistor when the band-gap reference circuit is in a second state.
Technical advantages of one or more embodiments of the present invention include providing an improved band-gap reference circuit. In a particular embodiment, the band-gap reference circuit alternates between a first state and a second state based on a specified duty cycle. When the band-gap reference circuit is in the first state, a first input