	.file	"extr_a10_ahci.c_ahci_a10_phy_reset.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC0:
	.string	"PHY Power Failed PHYCS0R = %#x\n"
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"PHY Cal Failed PHYCS2R %#x\n"
	.text
	.p2align 4
	.type	ahci_a10_phy_reset, @function
ahci_a10_phy_reset:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	mov	r13d, edi
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	sub	rsp, 8
	.cfi_def_cfa_offset 48
	call	device_get_softc@PLT
	mov	esi, DWORD PTR AHCI_RWCR[rip]
	xor	edx, edx
	mov	edi, DWORD PTR [rax]
	mov	rbp, rax
	call	ATA_OUTL@PLT
	mov	edi, 100
	call	DELAY@PLT
	mov	rdx, QWORD PTR PHYCS1R_HIGHZ[rip]
	mov	esi, DWORD PTR AHCI_PHYCS1R[rip]
	mov	edi, DWORD PTR 0[rbp]
	call	ahci_set@PLT
	mov	edx, DWORD PTR PHYCS0R_UF2_MASK[rip]
	mov	edi, DWORD PTR 0[rbp]
	mov	esi, DWORD PTR AHCI_PHYCS0R[rip]
	mov	ecx, DWORD PTR PHYCS0R_UF2_INIT[rip]
	not	edx
	or	ecx, DWORD PTR PHYCS0R_BIT23[rip]
	or	ecx, DWORD PTR PHYCS0R_BIT18[rip]
	call	ahci_mask_set@PLT
	mov	edx, DWORD PTR PHYCS1R_UF1_MASK[rip]
	mov	edi, DWORD PTR 0[rbp]
	mov	esi, DWORD PTR AHCI_PHYCS1R[rip]
	or	edx, DWORD PTR PHYCS1R_UF2_MASK[rip]
	or	edx, DWORD PTR PHYCS1R_UF3_MASK[rip]
	mov	ecx, DWORD PTR PHYCS1R_UF1_INIT[rip]
	not	edx
	or	ecx, DWORD PTR PHYCS1R_UF2_INIT[rip]
	or	ecx, DWORD PTR PHYCS1R_UF3_INIT[rip]
	call	ahci_mask_set@PLT
	mov	esi, DWORD PTR AHCI_PHYCS1R[rip]
	mov	edi, DWORD PTR 0[rbp]
	mov	rdx, QWORD PTR PHYCS1R_BIT15[rip]
	or	rdx, QWORD PTR PHYCS1R_BIT28[rip]
	call	ahci_set@PLT
	mov	rdx, QWORD PTR PHYCS1R_HIGHZ[rip]
	mov	esi, DWORD PTR AHCI_PHYCS1R[rip]
	mov	edi, DWORD PTR 0[rbp]
	call	ahci_clr@PLT
	mov	edx, DWORD PTR PHYCS0R_UF1_MASK[rip]
	mov	ecx, DWORD PTR PHYCS0R_UF1_INIT[rip]
	mov	esi, DWORD PTR AHCI_PHYCS0R[rip]
	mov	edi, DWORD PTR 0[rbp]
	not	edx
	call	ahci_mask_set@PLT
	mov	edx, DWORD PTR PHYCS2R_UF1_MASK[rip]
	mov	ecx, DWORD PTR PHYCS2R_UF1_INIT[rip]
	mov	esi, DWORD PTR AHCI_PHYCS2R[rip]
	mov	edi, DWORD PTR 0[rbp]
	not	edx
	call	ahci_mask_set@PLT
	mov	edi, 100
	call	DELAY@PLT
	mov	rdx, QWORD PTR PHYCS0R_POWER_ENABLE[rip]
	mov	esi, DWORD PTR AHCI_PHYCS0R[rip]
	mov	edi, DWORD PTR 0[rbp]
	call	ahci_set@PLT
	mov	rbx, QWORD PTR PHY_RESET_TIMEOUT[rip]
	test	rbx, rbx
	jg	.L4
	jmp	.L2
	.p2align 4,,10
	.p2align 3
.L16:
	mov	edi, 10
	call	DELAY@PLT
	sub	rbx, 1
	je	.L5
.L4:
	mov	esi, DWORD PTR AHCI_PHYCS0R[rip]
	mov	edi, DWORD PTR 0[rbp]
	call	ATA_INL@PLT
	mov	r12, rax
	mov	rax, QWORD PTR PHYCS0R_POWER_STATUS_MASK[rip]
	and	rax, r12
	cmp	rax, QWORD PTR PHYCS0R_PS_GOOD[rip]
	jne	.L16
.L3:
	mov	rdx, QWORD PTR PHYCS2R_CALIBRATE[rip]
	mov	esi, DWORD PTR AHCI_PHYCS2R[rip]
	mov	edi, DWORD PTR 0[rbp]
	call	ahci_set@PLT
	mov	rbx, QWORD PTR PHY_RESET_TIMEOUT[rip]
	test	rbx, rbx
	jg	.L9
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L17:
	mov	edi, 10
	call	DELAY@PLT
	sub	rbx, 1
	je	.L10
.L9:
	mov	esi, DWORD PTR AHCI_PHYCS2R[rip]
	mov	edi, DWORD PTR 0[rbp]
	call	ATA_INL@PLT
	mov	r12, rax
	test	QWORD PTR PHYCS2R_CALIBRATE[rip], rax
	jne	.L17
.L8:
	mov	edi, 1000
	call	DELAY@PLT
	mov	edi, DWORD PTR 0[rbp]
	mov	esi, DWORD PTR AHCI_RWCR[rip]
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	pop	rbx
	.cfi_def_cfa_offset 32
	mov	edx, 7
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	jmp	ATA_OUTL@PLT
.L2:
	.cfi_restore_state
	jne	.L3
	.p2align 4,,10
	.p2align 3
.L5:
	cmp	QWORD PTR bootverbose[rip], 0
	je	.L3
	mov	rdx, r12
	lea	rsi, .LC0[rip]
	mov	edi, r13d
	call	device_printf@PLT
	jmp	.L3
.L6:
	jne	.L8
	.p2align 4,,10
	.p2align 3
.L10:
	cmp	QWORD PTR bootverbose[rip], 0
	je	.L8
	mov	rdx, r12
	lea	rsi, .LC1[rip]
	mov	edi, r13d
	call	device_printf@PLT
	jmp	.L8
	.cfi_endproc
.LFE0:
	.size	ahci_a10_phy_reset, .-ahci_a10_phy_reset
	.comm	bootverbose,8,8
	.comm	PHY_RESET_TIMEOUT,8,8
	.comm	PHYCS2R_UF1_MASK,4,4
	.comm	PHYCS2R_UF1_INIT,4,4
	.comm	PHYCS2R_CALIBRATE,8,8
	.comm	PHYCS1R_UF3_MASK,4,4
	.comm	PHYCS1R_UF3_INIT,4,4
	.comm	PHYCS1R_UF2_MASK,4,4
	.comm	PHYCS1R_UF2_INIT,4,4
	.comm	PHYCS1R_UF1_MASK,4,4
	.comm	PHYCS1R_UF1_INIT,4,4
	.comm	PHYCS1R_HIGHZ,8,8
	.comm	PHYCS1R_BIT28,8,8
	.comm	PHYCS1R_BIT15,8,8
	.comm	PHYCS0R_UF2_MASK,4,4
	.comm	PHYCS0R_UF2_INIT,4,4
	.comm	PHYCS0R_UF1_MASK,4,4
	.comm	PHYCS0R_UF1_INIT,4,4
	.comm	PHYCS0R_PS_GOOD,8,8
	.comm	PHYCS0R_POWER_STATUS_MASK,8,8
	.comm	PHYCS0R_POWER_ENABLE,8,8
	.comm	PHYCS0R_BIT23,4,4
	.comm	PHYCS0R_BIT18,4,4
	.comm	AHCI_RWCR,4,4
	.comm	AHCI_PHYCS2R,4,4
	.comm	AHCI_PHYCS1R,4,4
	.comm	AHCI_PHYCS0R,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_a10_ahci.c_ahci_a10_phy_reset.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"PHY Power Failed PHYCS0R = %#x\012\000"
	.align	2
.LC1:
	.ascii	"PHY Cal Failed PHYCS2R %#x\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	ahci_a10_phy_reset, %function
ahci_a10_phy_reset:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	sub	sp, sp, #12
	str	r0, [sp, #4]
	bl	device_get_softc
	mov	r5, r0
	ldr	r3, .L24
	ldr	r6, .L24+4
	ldr	r1, [r3]
	mov	r2, #0
	ldr	r8, .L24+8
	ldr	r0, [r0]
	bl	ATA_OUTL
	mov	r0, #100
	bl	DELAY
	ldr	r2, [r8]
	ldr	r1, [r6]
	ldr	r0, [r5]
	bl	ahci_set
	ldr	r1, .L24+12
	ldr	r3, .L24+16
	ldr	r0, .L24+20
	ldr	r2, .L24+24
	ldr	r1, [r1]
	ldr	r3, [r3]
	ldr	r0, [r0]
	ldr	r7, .L24+28
	ldr	r2, [r2]
	orr	r3, r1, r3
	orr	r3, r3, r0
	mvn	r2, r2
	ldr	r1, [r7]
	ldr	r0, [r5]
	bl	ahci_mask_set
	ldr	r2, .L24+32
	ldr	r0, .L24+36
	ldr	r2, [r2]
	ldr	r0, [r0]
	ldr	ip, .L24+40
	ldr	r1, .L24+44
	ldr	r3, .L24+48
	orr	r2, r2, r0
	ldr	r0, .L24+52
	ldr	ip, [ip]
	ldr	r1, [r1]
	ldr	r3, [r3]
	ldr	r0, [r0]
	orr	r2, r2, ip
	orr	r3, r1, r3
	orr	r3, r3, r0
	ldr	r1, [r6]
	mvn	r2, r2
	ldr	r0, [r5]
	bl	ahci_mask_set
	ldr	r2, .L24+56
	ldr	r3, .L24+60
	ldr	r2, [r2]
	ldr	r3, [r3]
	ldr	r1, [r6]
	orr	r2, r2, r3
	ldr	r0, [r5]
	bl	ahci_set
	ldr	r2, [r8]
	ldr	r1, [r6]
	ldr	r0, [r5]
	bl	ahci_clr
	ldr	r2, .L24+64
	ldr	r3, .L24+68
	ldr	r2, [r2]
	ldr	r1, [r7]
	mvn	r2, r2
	ldr	r3, [r3]
	ldr	r0, [r5]
	bl	ahci_mask_set
	ldr	r2, .L24+72
	ldr	r3, .L24+76
	ldr	r2, [r2]
	ldr	r8, .L24+80
	mvn	r2, r2
	ldr	r3, [r3]
	ldr	r1, [r8]
	ldr	r0, [r5]
	bl	ahci_mask_set
	mov	r0, #100
	bl	DELAY
	ldr	r3, .L24+84
	ldr	fp, .L24+88
	ldr	r0, [r5]
	ldr	r1, [r7]
	ldr	r2, [r3]
	bl	ahci_set
	ldr	r6, [fp]
	cmp	r6, #0
	ble	.L2
	ldr	r10, .L24+92
	ldr	r9, .L24+96
	b	.L4
.L22:
	mov	r0, #10
	bl	DELAY
	subs	r6, r6, #1
	beq	.L5
.L4:
	ldr	r1, [r7]
	ldr	r0, [r5]
	bl	ATA_INL
	ldr	r3, [r10]
	ldr	r2, [r9]
	and	r3, r3, r0
	cmp	r3, r2
	mov	r4, r0
	bne	.L22
.L3:
	ldr	r7, .L24+100
	ldr	r1, [r8]
	ldr	r2, [r7]
	ldr	r0, [r5]
	bl	ahci_set
	ldr	r6, [fp]
	cmp	r6, #0
	bgt	.L9
	b	.L6
.L23:
	mov	r0, #10
	bl	DELAY
	subs	r6, r6, #1
	beq	.L10
.L9:
	ldr	r1, [r8]
	ldr	r0, [r5]
	bl	ATA_INL
	ldr	r3, [r7]
	mov	r4, r0
	tst	r0, r3
	bne	.L23
.L8:
	mov	r0, #1000
	bl	DELAY
	mov	r2, #7
	ldr	r3, .L24
	ldr	r0, [r5]
	ldr	r1, [r3]
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	b	ATA_OUTL
.L2:
	bne	.L3
.L5:
	ldr	r3, .L24+104
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L3
	mov	r2, r4
	ldr	r1, .L24+108
	ldr	r0, [sp, #4]
	bl	device_printf
	b	.L3
.L6:
	bne	.L8
.L10:
	ldr	r3, .L24+104
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L8
	mov	r2, r4
	ldr	r0, [sp, #4]
	ldr	r1, .L24+112
	bl	device_printf
	b	.L8
.L25:
	.align	2
.L24:
	.word	AHCI_RWCR
	.word	AHCI_PHYCS1R
	.word	PHYCS1R_HIGHZ
	.word	PHYCS0R_UF2_INIT
	.word	PHYCS0R_BIT23
	.word	PHYCS0R_BIT18
	.word	PHYCS0R_UF2_MASK
	.word	AHCI_PHYCS0R
	.word	PHYCS1R_UF1_MASK
	.word	PHYCS1R_UF2_MASK
	.word	PHYCS1R_UF3_MASK
	.word	PHYCS1R_UF1_INIT
	.word	PHYCS1R_UF2_INIT
	.word	PHYCS1R_UF3_INIT
	.word	PHYCS1R_BIT15
	.word	PHYCS1R_BIT28
	.word	PHYCS0R_UF1_MASK
	.word	PHYCS0R_UF1_INIT
	.word	PHYCS2R_UF1_MASK
	.word	PHYCS2R_UF1_INIT
	.word	AHCI_PHYCS2R
	.word	PHYCS0R_POWER_ENABLE
	.word	PHY_RESET_TIMEOUT
	.word	PHYCS0R_POWER_STATUS_MASK
	.word	PHYCS0R_PS_GOOD
	.word	PHYCS2R_CALIBRATE
	.word	bootverbose
	.word	.LC0
	.word	.LC1
	.size	ahci_a10_phy_reset, .-ahci_a10_phy_reset
	.comm	bootverbose,4,4
	.comm	PHY_RESET_TIMEOUT,4,4
	.comm	PHYCS2R_UF1_MASK,4,4
	.comm	PHYCS2R_UF1_INIT,4,4
	.comm	PHYCS2R_CALIBRATE,4,4
	.comm	PHYCS1R_UF3_MASK,4,4
	.comm	PHYCS1R_UF3_INIT,4,4
	.comm	PHYCS1R_UF2_MASK,4,4
	.comm	PHYCS1R_UF2_INIT,4,4
	.comm	PHYCS1R_UF1_MASK,4,4
	.comm	PHYCS1R_UF1_INIT,4,4
	.comm	PHYCS1R_HIGHZ,4,4
	.comm	PHYCS1R_BIT28,4,4
	.comm	PHYCS1R_BIT15,4,4
	.comm	PHYCS0R_UF2_MASK,4,4
	.comm	PHYCS0R_UF2_INIT,4,4
	.comm	PHYCS0R_UF1_MASK,4,4
	.comm	PHYCS0R_UF1_INIT,4,4
	.comm	PHYCS0R_PS_GOOD,4,4
	.comm	PHYCS0R_POWER_STATUS_MASK,4,4
	.comm	PHYCS0R_POWER_ENABLE,4,4
	.comm	PHYCS0R_BIT23,4,4
	.comm	PHYCS0R_BIT18,4,4
	.comm	AHCI_RWCR,4,4
	.comm	AHCI_PHYCS2R,4,4
	.comm	AHCI_PHYCS1R,4,4
	.comm	AHCI_PHYCS0R,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
