	.file	"extr_i2c-sis96x.c_sis96x_access.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Unsupported transaction %d\n"
	.text
	.p2align 4
	.type	sis96x_access, @function
sis96x_access:
.LFB0:
	.cfi_startproc
	endbr64
	lea	eax, -132[r9]
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	mov	r12d, r9d
	push	rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	push	rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	cmp	eax, 4
	ja	.L2
	lea	rdx, .L4[rip]
	add	esi, esi
	mov	ebx, ecx
	mov	ebp, r8d
	movsx	rax, DWORD PTR [rdx+rax*4]
	movzx	esi, sil
	add	rax, rdx
	notrack jmp	rax
	.section	.rodata
	.align 4
	.align 4
.L4:
	.long	.L6-.L4
	.long	.L7-.L4
	.long	.L6-.L4
	.long	.L5-.L4
	.long	.L3-.L4
	.text
	.p2align 4,,10
	.p2align 3
.L6:
	mov	eax, ecx
	mov	edi, DWORD PTR SMB_ADDR[rip]
	and	eax, 1
	or	esi, eax
	call	sis96x_write@PLT
	mov	edi, DWORD PTR SMB_CMD[rip]
	mov	esi, ebp
	call	sis96x_write@PLT
	cmp	BYTE PTR I2C_SMBUS_WRITE[rip], bl
	je	.L36
.L16:
	cmp	r12d, 134
	je	.L37
	mov	edi, 128
	call	sis96x_transaction@PLT
	test	eax, eax
	jne	.L1
	cmp	bl, BYTE PTR I2C_SMBUS_WRITE[rip]
	je	.L33
	cmp	DWORD PTR SIS96x_QUICK[rip], 128
	je	.L33
.L21:
	mov	edi, DWORD PTR SMB_BYTE[rip]
	call	sis96x_read@PLT
	mov	ebx, eax
	mov	eax, DWORD PTR SMB_BYTE[rip]
	lea	edi, 1[rax]
	call	sis96x_read@PLT
	sal	eax, 8
	add	eax, ebx
	mov	rbx, QWORD PTR 32[rsp]
	mov	DWORD PTR [rbx], eax
.L33:
	xor	eax, eax
.L1:
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L3:
	.cfi_restore_state
	mov	eax, ecx
	mov	edi, DWORD PTR SMB_ADDR[rip]
	and	eax, 1
	or	esi, eax
	call	sis96x_write@PLT
	cmp	BYTE PTR I2C_SMBUS_WRITE[rip], bl
	je	.L38
	mov	edi, 131
	call	sis96x_transaction@PLT
	test	eax, eax
	jne	.L1
.L34:
	cmp	bl, BYTE PTR I2C_SMBUS_WRITE[rip]
	je	.L33
	cmp	DWORD PTR SIS96x_QUICK[rip], 131
	jne	.L13
	xor	eax, eax
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L5:
	mov	eax, ecx
	mov	edi, DWORD PTR SMB_ADDR[rip]
	and	eax, 1
	or	esi, eax
	call	sis96x_write@PLT
	mov	edi, DWORD PTR SMB_CMD[rip]
	mov	esi, ebp
	call	sis96x_write@PLT
	cmp	BYTE PTR I2C_SMBUS_WRITE[rip], bl
	je	.L39
	mov	edi, 130
	call	sis96x_transaction@PLT
	test	eax, eax
	jne	.L1
.L32:
	cmp	bl, BYTE PTR I2C_SMBUS_WRITE[rip]
	je	.L33
	cmp	DWORD PTR SIS96x_QUICK[rip], 130
	je	.L33
.L13:
	mov	edi, DWORD PTR SMB_BYTE[rip]
	call	sis96x_read@PLT
	mov	rcx, QWORD PTR 32[rsp]
	mov	DWORD PTR [rcx], eax
	xor	eax, eax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L7:
	.cfi_restore_state
	mov	eax, ecx
	mov	edi, DWORD PTR SMB_ADDR[rip]
	and	eax, 1
	or	esi, eax
	call	sis96x_write@PLT
	mov	ebp, DWORD PTR SIS96x_QUICK[rip]
	mov	edi, ebp
	call	sis96x_transaction@PLT
	test	eax, eax
	jne	.L1
	cmp	ebp, 129
	je	.L21
	cmp	BYTE PTR I2C_SMBUS_WRITE[rip], bl
	je	.L33
	cmp	DWORD PTR SIS96x_QUICK[rip], ebp
	je	.L33
	cmp	ebp, 129
	jg	.L20
	cmp	ebp, 127
	jle	.L1
	jmp	.L21
	.p2align 4,,10
	.p2align 3
.L2:
	mov	edx, r9d
	lea	rsi, .LC0[rip]
	call	dev_warn@PLT
	mov	eax, DWORD PTR EOPNOTSUPP[rip]
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	neg	eax
	ret
	.p2align 4,,10
	.p2align 3
.L37:
	.cfi_restore_state
	mov	edi, 129
	call	sis96x_transaction@PLT
	test	eax, eax
	je	.L21
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L38:
	mov	edi, DWORD PTR SMB_CMD[rip]
	mov	esi, ebp
	call	sis96x_write@PLT
	mov	edi, 131
	call	sis96x_transaction@PLT
	test	eax, eax
	je	.L34
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L36:
	mov	rax, QWORD PTR 32[rsp]
	mov	edi, DWORD PTR SMB_BYTE[rip]
	movzx	esi, BYTE PTR [rax]
	call	sis96x_write@PLT
	mov	rax, QWORD PTR 32[rsp]
	mov	eax, DWORD PTR [rax]
	movzx	esi, ah
	mov	eax, DWORD PTR SMB_BYTE[rip]
	lea	edi, 1[rax]
	call	sis96x_write@PLT
	jmp	.L16
	.p2align 4,,10
	.p2align 3
.L39:
	mov	rax, QWORD PTR 32[rsp]
	mov	edi, DWORD PTR SMB_BYTE[rip]
	mov	esi, DWORD PTR [rax]
	call	sis96x_write@PLT
	mov	edi, 130
	call	sis96x_transaction@PLT
	test	eax, eax
	je	.L32
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L20:
	sub	ebp, 130
	cmp	ebp, 1
	ja	.L1
	jmp	.L13
	.cfi_endproc
.LFE0:
	.size	sis96x_access, .-sis96x_access
	.comm	SMB_CMD,4,4
	.comm	SMB_BYTE,4,4
	.comm	SMB_ADDR,4,4
	.comm	SIS96x_QUICK,4,4
	.comm	I2C_SMBUS_WRITE,1,1
	.comm	EOPNOTSUPP,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_i2c-sis96x.c_sis96x_access.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"Unsupported transaction %d\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	sis96x_access, %function
sis96x_access:
	@ args = 12, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	ldr	r5, [sp, #28]
	mov	r4, r3
	sub	r2, r5, #132
	cmp	r2, #4
	ldrls	pc, [pc, r2, asl #2]
	b	.L2
.L4:
	.word	.L6
	.word	.L7
	.word	.L6
	.word	.L5
	.word	.L3
.L6:
	ldr	r3, .L56
	lsl	r1, r1, #1
	and	r2, r4, #1
	and	r1, r1, #255
	orr	r1, r1, r2
	ldr	r0, [r3]
	bl	sis96x_write
	ldr	r3, .L56+4
	ldr	r7, .L56+8
	ldr	r0, [r3]
	ldr	r1, [sp, #24]
	bl	sis96x_write
	ldrb	r3, [r7]	@ zero_extendqisi2
	cmp	r3, r4
	beq	.L52
.L16:
	cmp	r5, #134
	beq	.L53
	mov	r0, #128
	bl	sis96x_transaction
	cmp	r0, #0
	popne	{r4, r5, r6, r7, r8, pc}
	ldrb	r3, [r7]	@ zero_extendqisi2
	cmp	r3, r4
	beq	.L12
	ldr	r3, .L56+12
	ldr	r3, [r3]
	cmp	r3, #128
	beq	.L12
.L21:
	ldr	r4, .L56+16
	ldr	r0, [r4]
	bl	sis96x_read
	ldr	r3, [r4]
	mov	r4, r0
	add	r0, r3, #1
	bl	sis96x_read
	mov	r3, r0
	add	r4, r4, r3, lsl #8
	ldr	r3, [sp, #32]
	mov	r0, #0
	str	r4, [r3]
	pop	{r4, r5, r6, r7, r8, pc}
.L3:
	ldr	r3, .L56
	lsl	r1, r1, #1
	and	r2, r1, #255
	ldr	r5, .L56+8
	and	r1, r4, #1
	ldr	r0, [r3]
	orr	r1, r2, r1
	bl	sis96x_write
	ldrb	r3, [r5]	@ zero_extendqisi2
	cmp	r3, r4
	beq	.L54
.L50:
	mov	r0, #131
	bl	sis96x_transaction
	cmp	r0, #0
	popne	{r4, r5, r6, r7, r8, pc}
	ldrb	r3, [r5]	@ zero_extendqisi2
	cmp	r3, r4
	beq	.L12
	ldr	r3, .L56+12
	ldr	r3, [r3]
	cmp	r3, #131
	bne	.L45
.L12:
	mov	r0, #0
	pop	{r4, r5, r6, r7, r8, pc}
.L5:
	ldr	r3, .L56
	lsl	r1, r1, #1
	and	r2, r4, #1
	and	r1, r1, #255
	orr	r1, r1, r2
	ldr	r0, [r3]
	bl	sis96x_write
	ldr	r3, .L56+4
	ldr	r5, .L56+8
	ldr	r0, [r3]
	ldr	r1, [sp, #24]
	bl	sis96x_write
	ldrb	r3, [r5]	@ zero_extendqisi2
	cmp	r3, r4
	beq	.L55
	mov	r0, #130
	bl	sis96x_transaction
	cmp	r0, #0
	popne	{r4, r5, r6, r7, r8, pc}
	ldrb	r3, [r5]	@ zero_extendqisi2
	cmp	r3, r4
	beq	.L12
	ldr	r3, .L56+12
	ldr	r3, [r3]
	cmp	r3, #130
	beq	.L12
.L45:
	ldr	r6, .L56+16
.L13:
	ldr	r0, [r6]
	bl	sis96x_read
	mov	r3, r0
	ldr	r2, [sp, #32]
	mov	r0, #0
	str	r3, [r2]
	pop	{r4, r5, r6, r7, r8, pc}
.L7:
	ldr	r3, .L56
	lsl	r1, r1, #1
	and	r2, r1, #255
	ldr	r6, .L56+12
	and	r1, r4, #1
	ldr	r0, [r3]
	orr	r1, r2, r1
	bl	sis96x_write
	ldr	r5, [r6]
	mov	r0, r5
	bl	sis96x_transaction
	cmp	r0, #0
	popne	{r4, r5, r6, r7, r8, pc}
	cmp	r5, #129
	beq	.L21
	ldr	r3, .L56+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, r4
	beq	.L12
	ldr	r3, [r6]
	cmp	r3, r5
	beq	.L12
	cmp	r5, #129
	bgt	.L20
	cmp	r5, #127
	pople	{r4, r5, r6, r7, r8, pc}
	b	.L21
.L53:
	mov	r0, #129
	bl	sis96x_transaction
	cmp	r0, #0
	beq	.L21
	pop	{r4, r5, r6, r7, r8, pc}
.L55:
	ldr	r3, [sp, #32]
	ldr	r6, .L56+16
	ldr	r1, [r3]
	ldr	r0, [r6]
	bl	sis96x_write
	mov	r0, #130
	bl	sis96x_transaction
	cmp	r0, #0
	popne	{r4, r5, r6, r7, r8, pc}
	ldrb	r3, [r5]	@ zero_extendqisi2
	cmp	r3, r4
	beq	.L12
	ldr	r3, .L56+12
	ldr	r3, [r3]
	cmp	r3, #130
	bne	.L13
	b	.L12
.L52:
	ldr	r3, [sp, #32]
	ldr	r6, .L56+16
	ldrb	r1, [r3]	@ zero_extendqisi2
	ldr	r0, [r6]
	bl	sis96x_write
	ldr	r0, [r6]
	ldr	r3, [sp, #32]
	add	r0, r0, #1
	ldrb	r1, [r3, #1]	@ zero_extendqisi2
	bl	sis96x_write
	b	.L16
.L54:
	ldr	r3, .L56+4
	ldr	r1, [sp, #24]
	ldr	r0, [r3]
	bl	sis96x_write
	b	.L50
.L20:
	sub	r5, r5, #130
	cmp	r5, #1
	pophi	{r4, r5, r6, r7, r8, pc}
	b	.L45
.L2:
	mov	r2, r5
	ldr	r1, .L56+20
	bl	dev_warn
	ldr	r3, .L56+24
	ldr	r0, [r3]
	rsb	r0, r0, #0
	pop	{r4, r5, r6, r7, r8, pc}
.L57:
	.align	2
.L56:
	.word	SMB_ADDR
	.word	SMB_CMD
	.word	I2C_SMBUS_WRITE
	.word	SIS96x_QUICK
	.word	SMB_BYTE
	.word	.LC0
	.word	EOPNOTSUPP
	.size	sis96x_access, .-sis96x_access
	.comm	SMB_CMD,4,4
	.comm	SMB_BYTE,4,4
	.comm	SMB_ADDR,4,4
	.comm	SIS96x_QUICK,4,4
	.comm	I2C_SMBUS_WRITE,1,1
	.comm	EOPNOTSUPP,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
