	.file	"extr_radeon_accel.c_radeonfb_engine_init.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	radeonfb_engine_init
	.type	radeonfb_engine_init, @function
radeonfb_engine_init:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	mov	rbx, rdi
	mov	edi, DWORD PTR RB3D_CNTL[rip]
	xor	esi, esi
	call	OUTREG@PLT
	mov	rdi, rbx
	call	radeonfb_engine_reset@PLT
	mov	edi, 1
	call	radeon_fifo_wait@PLT
	mov	rdi, rbx
	call	IS_R300_VARIANT@PLT
	test	rax, rax
	je	.L2
	mov	edi, DWORD PTR RB2D_DSTCACHE_MODE[rip]
	call	INREG@PLT
	mov	esi, DWORD PTR RB2D_DC_AUTOFLUSH_ENABLE[rip]
	mov	edi, DWORD PTR RB2D_DSTCACHE_MODE[rip]
	or	esi, DWORD PTR RB2D_DC_DC_DISABLE_IGNORE_PE[rip]
	or	esi, eax
	call	OUTREG@PLT
.L3:
	mov	edi, 3
	call	radeon_fifo_wait@PLT
	mov	edi, DWORD PTR MC_FB_LOCATION[rip]
	call	INREG@PLT
	mov	esi, DWORD PTR 4[rbx]
	mov	edi, DWORD PTR DEFAULT_PITCH_OFFSET[rip]
	sal	eax, 16
	mov	DWORD PTR [rbx], eax
	sal	esi, 22
	sar	eax, 10
	or	esi, eax
	call	OUTREG@PLT
	mov	esi, DWORD PTR 4[rbx]
	mov	eax, DWORD PTR [rbx]
	mov	edi, DWORD PTR DST_PITCH_OFFSET[rip]
	sar	eax, 10
	sal	esi, 22
	or	esi, eax
	call	OUTREG@PLT
	mov	esi, DWORD PTR 4[rbx]
	mov	eax, DWORD PTR [rbx]
	mov	edi, DWORD PTR SRC_PITCH_OFFSET[rip]
	sar	eax, 10
	sal	esi, 22
	or	esi, eax
	call	OUTREG@PLT
	mov	edi, 1
	call	radeon_fifo_wait@PLT
	mov	edx, DWORD PTR HOST_BIG_ENDIAN_EN[rip]
	mov	edi, DWORD PTR DP_DATATYPE[rip]
	xor	esi, esi
	not	edx
	call	OUTREGP@PLT
	mov	edi, 2
	call	radeon_fifo_wait@PLT
	mov	edi, DWORD PTR DEFAULT_SC_TOP_LEFT[rip]
	xor	esi, esi
	call	OUTREG@PLT
	mov	edi, DWORD PTR DEFAULT_SC_BOTTOM_RIGHT[rip]
	mov	esi, DWORD PTR DEFAULT_SC_RIGHT_MAX[rip]
	or	esi, DWORD PTR DEFAULT_SC_BOTTOM_MAX[rip]
	call	OUTREG@PLT
	mov	edi, DWORD PTR 16[rbx]
	call	radeon_get_dstbpp@PLT
	mov	edi, 1
	sal	rax, 8
	or	rax, QWORD PTR GMC_CLR_CMP_CNTL_DIS[rip]
	mov	QWORD PTR 8[rbx], rax
	call	radeon_fifo_wait@PLT
	mov	edi, DWORD PTR DP_GUI_MASTER_CNTL[rip]
	mov	esi, DWORD PTR GMC_BRUSH_SOLID_COLOR[rip]
	or	esi, DWORD PTR GMC_SRC_DATATYPE_COLOR[rip]
	or	esi, DWORD PTR 8[rbx]
	call	OUTREG@PLT
	mov	edi, 7
	call	radeon_fifo_wait@PLT
	mov	edi, DWORD PTR DST_LINE_START[rip]
	xor	esi, esi
	call	OUTREG@PLT
	mov	edi, DWORD PTR DST_LINE_END[rip]
	xor	esi, esi
	call	OUTREG@PLT
	mov	edi, DWORD PTR DP_BRUSH_FRGD_CLR[rip]
	mov	esi, -1
	call	OUTREG@PLT
	mov	edi, DWORD PTR DP_BRUSH_BKGD_CLR[rip]
	xor	esi, esi
	call	OUTREG@PLT
	mov	edi, DWORD PTR DP_SRC_FRGD_CLR[rip]
	mov	esi, -1
	call	OUTREG@PLT
	mov	edi, DWORD PTR DP_SRC_BKGD_CLR[rip]
	xor	esi, esi
	call	OUTREG@PLT
	mov	edi, DWORD PTR DP_WRITE_MSK[rip]
	mov	esi, -1
	call	OUTREG@PLT
	xor	eax, eax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	radeon_engine_idle@PLT
	.p2align 4,,10
	.p2align 3
.L2:
	.cfi_restore_state
	mov	edi, DWORD PTR RB2D_DSTCACHE_MODE[rip]
	xor	esi, esi
	call	OUTREG@PLT
	jmp	.L3
	.cfi_endproc
.LFE0:
	.size	radeonfb_engine_init, .-radeonfb_engine_init
	.comm	SRC_PITCH_OFFSET,4,4
	.comm	RB3D_CNTL,4,4
	.comm	RB2D_DSTCACHE_MODE,4,4
	.comm	RB2D_DC_DC_DISABLE_IGNORE_PE,4,4
	.comm	RB2D_DC_AUTOFLUSH_ENABLE,4,4
	.comm	MC_FB_LOCATION,4,4
	.comm	HOST_BIG_ENDIAN_EN,4,4
	.comm	GMC_SRC_DATATYPE_COLOR,4,4
	.comm	GMC_CLR_CMP_CNTL_DIS,8,8
	.comm	GMC_BRUSH_SOLID_COLOR,4,4
	.comm	DST_PITCH_OFFSET,4,4
	.comm	DST_LINE_START,4,4
	.comm	DST_LINE_END,4,4
	.comm	DP_WRITE_MSK,4,4
	.comm	DP_SRC_FRGD_CLR,4,4
	.comm	DP_SRC_BKGD_CLR,4,4
	.comm	DP_GUI_MASTER_CNTL,4,4
	.comm	DP_DATATYPE,4,4
	.comm	DP_BRUSH_FRGD_CLR,4,4
	.comm	DP_BRUSH_BKGD_CLR,4,4
	.comm	DEFAULT_SC_TOP_LEFT,4,4
	.comm	DEFAULT_SC_RIGHT_MAX,4,4
	.comm	DEFAULT_SC_BOTTOM_RIGHT,4,4
	.comm	DEFAULT_SC_BOTTOM_MAX,4,4
	.comm	DEFAULT_PITCH_OFFSET,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_radeon_accel.c_radeonfb_engine_init.c"
	.text
	.align	2
	.global	radeonfb_engine_init
	.syntax unified
	.arm
	.fpu softvfp
	.type	radeonfb_engine_init, %function
radeonfb_engine_init:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, lr}
	mov	r4, r0
	ldr	r3, .L6
	mov	r1, #0
	ldr	r0, [r3]
	bl	OUTREG
	mov	r0, r4
	bl	radeonfb_engine_reset
	mov	r0, #1
	bl	radeon_fifo_wait
	mov	r0, r4
	bl	IS_R300_VARIANT
	subs	r1, r0, #0
	ldr	r3, .L6+4
	beq	.L2
	ldr	r5, [r3]
	mov	r0, r5
	bl	INREG
	mov	r1, r0
	ldr	r3, .L6+8
	ldr	r2, .L6+12
	ldr	r3, [r3]
	ldr	r2, [r2]
	mov	r0, r5
	orr	r3, r3, r2
	orr	r1, r3, r1
	bl	OUTREG
.L3:
	mov	r0, #3
	bl	radeon_fifo_wait
	ldr	r3, .L6+16
	ldr	r0, [r3]
	bl	INREG
	ldr	r1, [r4, #4]
	ldr	r3, .L6+20
	lsl	r0, r0, #16
	asr	r2, r0, #10
	str	r0, [r4]
	orr	r1, r2, r1, lsl #22
	ldr	r0, [r3]
	bl	OUTREG
	ldr	r3, [r4]
	ldr	r1, [r4, #4]
	ldr	r2, .L6+24
	asr	r3, r3, #10
	orr	r1, r3, r1, lsl #22
	ldr	r0, [r2]
	bl	OUTREG
	ldr	r3, [r4]
	ldr	r2, .L6+28
	ldr	r1, [r4, #4]
	asr	r3, r3, #10
	orr	r1, r3, r1, lsl #22
	ldr	r0, [r2]
	bl	OUTREG
	mov	r0, #1
	bl	radeon_fifo_wait
	ldr	r2, .L6+32
	ldr	r3, .L6+36
	ldr	r2, [r2]
	mov	r1, #0
	mvn	r2, r2
	ldr	r0, [r3]
	bl	OUTREGP
	mov	r0, #2
	bl	radeon_fifo_wait
	ldr	r3, .L6+40
	mov	r1, #0
	ldr	r0, [r3]
	bl	OUTREG
	ldr	r2, .L6+44
	ldr	r3, .L6+48
	ldr	r1, [r2]
	ldr	r2, [r3]
	ldr	r3, .L6+52
	orr	r1, r1, r2
	ldr	r0, [r3]
	bl	OUTREG
	ldr	r0, [r4, #12]
	bl	radeon_get_dstbpp
	mov	r2, r0
	ldr	r3, .L6+56
	mov	r0, #1
	ldr	r3, [r3]
	orr	r3, r3, r2, lsl #8
	str	r3, [r4, #8]
	bl	radeon_fifo_wait
	ldr	r2, .L6+60
	ldr	r3, .L6+64
	ldr	r0, [r2]
	ldr	r3, [r3]
	ldr	r2, .L6+68
	ldr	r1, [r4, #8]
	orr	r3, r3, r0
	orr	r1, r3, r1
	ldr	r0, [r2]
	bl	OUTREG
	mov	r0, #7
	bl	radeon_fifo_wait
	ldr	r3, .L6+72
	mov	r1, #0
	ldr	r0, [r3]
	bl	OUTREG
	ldr	r3, .L6+76
	mov	r1, #0
	ldr	r0, [r3]
	bl	OUTREG
	ldr	r3, .L6+80
	mvn	r1, #0
	ldr	r0, [r3]
	bl	OUTREG
	ldr	r3, .L6+84
	mov	r1, #0
	ldr	r0, [r3]
	bl	OUTREG
	ldr	r3, .L6+88
	mvn	r1, #0
	ldr	r0, [r3]
	bl	OUTREG
	ldr	r3, .L6+92
	mov	r1, #0
	ldr	r0, [r3]
	bl	OUTREG
	ldr	r3, .L6+96
	mvn	r1, #0
	ldr	r0, [r3]
	bl	OUTREG
	pop	{r4, r5, r6, lr}
	b	radeon_engine_idle
.L2:
	ldr	r0, [r3]
	bl	OUTREG
	b	.L3
.L7:
	.align	2
.L6:
	.word	RB3D_CNTL
	.word	RB2D_DSTCACHE_MODE
	.word	RB2D_DC_AUTOFLUSH_ENABLE
	.word	RB2D_DC_DC_DISABLE_IGNORE_PE
	.word	MC_FB_LOCATION
	.word	DEFAULT_PITCH_OFFSET
	.word	DST_PITCH_OFFSET
	.word	SRC_PITCH_OFFSET
	.word	HOST_BIG_ENDIAN_EN
	.word	DP_DATATYPE
	.word	DEFAULT_SC_TOP_LEFT
	.word	DEFAULT_SC_RIGHT_MAX
	.word	DEFAULT_SC_BOTTOM_MAX
	.word	DEFAULT_SC_BOTTOM_RIGHT
	.word	GMC_CLR_CMP_CNTL_DIS
	.word	GMC_SRC_DATATYPE_COLOR
	.word	GMC_BRUSH_SOLID_COLOR
	.word	DP_GUI_MASTER_CNTL
	.word	DST_LINE_START
	.word	DST_LINE_END
	.word	DP_BRUSH_FRGD_CLR
	.word	DP_BRUSH_BKGD_CLR
	.word	DP_SRC_FRGD_CLR
	.word	DP_SRC_BKGD_CLR
	.word	DP_WRITE_MSK
	.size	radeonfb_engine_init, .-radeonfb_engine_init
	.comm	SRC_PITCH_OFFSET,4,4
	.comm	RB3D_CNTL,4,4
	.comm	RB2D_DSTCACHE_MODE,4,4
	.comm	RB2D_DC_DC_DISABLE_IGNORE_PE,4,4
	.comm	RB2D_DC_AUTOFLUSH_ENABLE,4,4
	.comm	MC_FB_LOCATION,4,4
	.comm	HOST_BIG_ENDIAN_EN,4,4
	.comm	GMC_SRC_DATATYPE_COLOR,4,4
	.comm	GMC_CLR_CMP_CNTL_DIS,4,4
	.comm	GMC_BRUSH_SOLID_COLOR,4,4
	.comm	DST_PITCH_OFFSET,4,4
	.comm	DST_LINE_START,4,4
	.comm	DST_LINE_END,4,4
	.comm	DP_WRITE_MSK,4,4
	.comm	DP_SRC_FRGD_CLR,4,4
	.comm	DP_SRC_BKGD_CLR,4,4
	.comm	DP_GUI_MASTER_CNTL,4,4
	.comm	DP_DATATYPE,4,4
	.comm	DP_BRUSH_FRGD_CLR,4,4
	.comm	DP_BRUSH_BKGD_CLR,4,4
	.comm	DEFAULT_SC_TOP_LEFT,4,4
	.comm	DEFAULT_SC_RIGHT_MAX,4,4
	.comm	DEFAULT_SC_BOTTOM_RIGHT,4,4
	.comm	DEFAULT_SC_BOTTOM_MAX,4,4
	.comm	DEFAULT_PITCH_OFFSET,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
