	.file	"extr_phy-ti-pipe3.c_ti_pipe3_calibrate.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	ti_pipe3_calibrate, @function
ti_pipe3_calibrate:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	mov	esi, DWORD PTR PIPE3_PHY_RX_ANA_PROGRAMMABILITY[rip]
	mov	rbx, rdi
	mov	edi, DWORD PTR 8[rdi]
	call	ti_pipe3_readl@PLT
	mov	ecx, DWORD PTR INTERFACE_SHIFT[rip]
	mov	edx, DWORD PTR 12[rbx]
	mov	edi, DWORD PTR 16[rbx]
	mov	r8d, eax
	mov	eax, DWORD PTR INTERFACE_MASK[rip]
	sal	edx, cl
	mov	ecx, DWORD PTR LOSD_SHIFT[rip]
	or	eax, DWORD PTR LOSD_MASK[rip]
	or	eax, DWORD PTR MEM_PLLDIV[rip]
	mov	esi, DWORD PTR PIPE3_PHY_RX_ANA_PROGRAMMABILITY[rip]
	sal	edi, cl
	not	eax
	and	eax, r8d
	or	edx, edi
	mov	edi, DWORD PTR 8[rbx]
	or	edx, eax
	call	ti_pipe3_writel@PLT
	mov	edi, DWORD PTR 8[rbx]
	mov	esi, DWORD PTR PIPE3_PHY_RX_DIGITAL_MODES[rip]
	call	ti_pipe3_readl@PLT
	mov	ecx, DWORD PTR MEM_HS_RATE_SHIFT[rip]
	mov	edx, DWORD PTR MEM_HS_RATE_MASK[rip]
	mov	esi, DWORD PTR 20[rbx]
	or	edx, DWORD PTR MEM_OVRD_HS_RATE[rip]
	or	edx, DWORD PTR MEM_CDR_FASTLOCK[rip]
	or	edx, DWORD PTR MEM_CDR_LBW_MASK[rip]
	or	edx, DWORD PTR MEM_CDR_STEPCNT_MASK[rip]
	or	edx, DWORD PTR MEM_CDR_STL_MASK[rip]
	sal	esi, cl
	or	edx, DWORD PTR MEM_CDR_THR_MASK[rip]
	or	edx, DWORD PTR MEM_CDR_THR_MODE[rip]
	or	edx, DWORD PTR MEM_CDR_2NDO_SDM_MODE[rip]
	mov	ecx, DWORD PTR MEM_OVRD_HS_RATE_SHIFT[rip]
	not	edx
	mov	edi, DWORD PTR 8[rbx]
	and	edx, eax
	mov	eax, DWORD PTR 24[rbx]
	sal	eax, cl
	mov	ecx, DWORD PTR MEM_CDR_FASTLOCK_SHIFT[rip]
	or	esi, eax
	mov	eax, DWORD PTR 28[rbx]
	sal	eax, cl
	mov	ecx, DWORD PTR MEM_CDR_LBW_SHIFT[rip]
	or	esi, eax
	mov	eax, DWORD PTR 32[rbx]
	sal	eax, cl
	mov	ecx, DWORD PTR MEM_CDR_STEPCNT_SHIFT[rip]
	or	esi, eax
	mov	eax, DWORD PTR 36[rbx]
	sal	eax, cl
	mov	ecx, DWORD PTR MEM_CDR_STL_SHIFT[rip]
	or	esi, eax
	mov	eax, DWORD PTR 40[rbx]
	sal	eax, cl
	mov	ecx, DWORD PTR MEM_CDR_THR_SHIFT[rip]
	or	esi, eax
	mov	eax, DWORD PTR 44[rbx]
	sal	eax, cl
	mov	ecx, DWORD PTR MEM_CDR_THR_MODE_SHIFT[rip]
	or	esi, eax
	mov	eax, DWORD PTR 48[rbx]
	sal	eax, cl
	mov	ecx, DWORD PTR MEM_CDR_2NDO_SDM_MODE_SHIFT[rip]
	or	esi, eax
	mov	eax, DWORD PTR 52[rbx]
	sal	eax, cl
	or	esi, eax
	or	edx, esi
	mov	esi, DWORD PTR PIPE3_PHY_RX_DIGITAL_MODES[rip]
	call	ti_pipe3_writel@PLT
	mov	edi, DWORD PTR 8[rbx]
	mov	esi, DWORD PTR PIPE3_PHY_RX_TRIM[rip]
	call	ti_pipe3_readl@PLT
	mov	edx, DWORD PTR MEM_DLL_TRIM_SEL_MASK[rip]
	mov	edi, DWORD PTR 8[rbx]
	mov	ecx, DWORD PTR MEM_DLL_TRIM_SHIFT[rip]
	mov	esi, DWORD PTR PIPE3_PHY_RX_TRIM[rip]
	not	edx
	and	eax, edx
	mov	edx, DWORD PTR 56[rbx]
	sal	edx, cl
	or	edx, eax
	call	ti_pipe3_writel@PLT
	mov	edi, DWORD PTR 8[rbx]
	mov	esi, DWORD PTR PIPE3_PHY_RX_DLL[rip]
	call	ti_pipe3_readl@PLT
	mov	edx, DWORD PTR MEM_DLL_PHINT_RATE_MASK[rip]
	mov	edi, DWORD PTR 8[rbx]
	mov	ecx, DWORD PTR MEM_DLL_PHINT_RATE_SHIFT[rip]
	mov	esi, DWORD PTR PIPE3_PHY_RX_DLL[rip]
	not	edx
	and	eax, edx
	mov	edx, DWORD PTR 60[rbx]
	sal	edx, cl
	or	edx, eax
	call	ti_pipe3_writel@PLT
	mov	edi, DWORD PTR 8[rbx]
	mov	esi, DWORD PTR PIPE3_PHY_RX_EQUALIZER[rip]
	call	ti_pipe3_readl@PLT
	mov	ecx, DWORD PTR MEM_EQLEV_SHIFT[rip]
	mov	edx, DWORD PTR MEM_EQLEV_MASK[rip]
	mov	esi, DWORD PTR 64[rbx]
	or	edx, DWORD PTR MEM_EQFTC_MASK[rip]
	or	edx, DWORD PTR MEM_EQCTL_MASK[rip]
	or	edx, DWORD PTR MEM_OVRD_EQLEV[rip]
	or	edx, DWORD PTR MEM_OVRD_EQFTC[rip]
	sal	esi, cl
	mov	ecx, DWORD PTR MEM_EQFTC_SHIFT[rip]
	not	edx
	mov	edi, DWORD PTR 8[rbx]
	and	edx, eax
	mov	eax, DWORD PTR 68[rbx]
	sal	eax, cl
	mov	ecx, DWORD PTR MEM_EQCTL_SHIFT[rip]
	or	esi, eax
	mov	eax, DWORD PTR 72[rbx]
	sal	eax, cl
	mov	ecx, DWORD PTR MEM_OVRD_EQLEV_SHIFT[rip]
	or	esi, eax
	mov	eax, DWORD PTR 76[rbx]
	sal	eax, cl
	mov	ecx, DWORD PTR MEM_OVRD_EQFTC_SHIFT[rip]
	or	esi, eax
	mov	eax, DWORD PTR 80[rbx]
	sal	eax, cl
	or	esi, eax
	or	edx, esi
	mov	esi, DWORD PTR PIPE3_PHY_RX_EQUALIZER[rip]
	call	ti_pipe3_writel@PLT
	mov	rax, QWORD PTR PIPE3_MODE_SATA[rip]
	cmp	QWORD PTR [rbx], rax
	je	.L5
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L5:
	.cfi_restore_state
	mov	edi, DWORD PTR 8[rbx]
	mov	esi, DWORD PTR SATA_PHY_RX_IO_AND_A2D_OVERRIDES[rip]
	call	ti_pipe3_readl@PLT
	mov	edx, DWORD PTR MEM_CDR_LOS_SOURCE_MASK[rip]
	mov	edi, DWORD PTR 8[rbx]
	mov	esi, DWORD PTR SATA_PHY_RX_IO_AND_A2D_OVERRIDES[rip]
	pop	rbx
	.cfi_def_cfa_offset 8
	not	edx
	and	edx, eax
	jmp	ti_pipe3_writel@PLT
	.cfi_endproc
.LFE0:
	.size	ti_pipe3_calibrate, .-ti_pipe3_calibrate
	.comm	SATA_PHY_RX_IO_AND_A2D_OVERRIDES,4,4
	.comm	PIPE3_PHY_RX_TRIM,4,4
	.comm	PIPE3_PHY_RX_EQUALIZER,4,4
	.comm	PIPE3_PHY_RX_DLL,4,4
	.comm	PIPE3_PHY_RX_DIGITAL_MODES,4,4
	.comm	PIPE3_PHY_RX_ANA_PROGRAMMABILITY,4,4
	.comm	PIPE3_MODE_SATA,8,8
	.comm	MEM_PLLDIV,4,4
	.comm	MEM_OVRD_HS_RATE_SHIFT,4,4
	.comm	MEM_OVRD_HS_RATE,4,4
	.comm	MEM_OVRD_EQLEV_SHIFT,4,4
	.comm	MEM_OVRD_EQLEV,4,4
	.comm	MEM_OVRD_EQFTC_SHIFT,4,4
	.comm	MEM_OVRD_EQFTC,4,4
	.comm	MEM_HS_RATE_SHIFT,4,4
	.comm	MEM_HS_RATE_MASK,4,4
	.comm	MEM_EQLEV_SHIFT,4,4
	.comm	MEM_EQLEV_MASK,4,4
	.comm	MEM_EQFTC_SHIFT,4,4
	.comm	MEM_EQFTC_MASK,4,4
	.comm	MEM_EQCTL_SHIFT,4,4
	.comm	MEM_EQCTL_MASK,4,4
	.comm	MEM_DLL_TRIM_SHIFT,4,4
	.comm	MEM_DLL_TRIM_SEL_MASK,4,4
	.comm	MEM_DLL_PHINT_RATE_SHIFT,4,4
	.comm	MEM_DLL_PHINT_RATE_MASK,4,4
	.comm	MEM_CDR_THR_SHIFT,4,4
	.comm	MEM_CDR_THR_MODE_SHIFT,4,4
	.comm	MEM_CDR_THR_MODE,4,4
	.comm	MEM_CDR_THR_MASK,4,4
	.comm	MEM_CDR_STL_SHIFT,4,4
	.comm	MEM_CDR_STL_MASK,4,4
	.comm	MEM_CDR_STEPCNT_SHIFT,4,4
	.comm	MEM_CDR_STEPCNT_MASK,4,4
	.comm	MEM_CDR_LOS_SOURCE_MASK,4,4
	.comm	MEM_CDR_LBW_SHIFT,4,4
	.comm	MEM_CDR_LBW_MASK,4,4
	.comm	MEM_CDR_FASTLOCK_SHIFT,4,4
	.comm	MEM_CDR_FASTLOCK,4,4
	.comm	MEM_CDR_2NDO_SDM_MODE_SHIFT,4,4
	.comm	MEM_CDR_2NDO_SDM_MODE,4,4
	.comm	LOSD_SHIFT,4,4
	.comm	LOSD_MASK,4,4
	.comm	INTERFACE_SHIFT,4,4
	.comm	INTERFACE_MASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_phy-ti-pipe3.c_ti_pipe3_calibrate.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	ti_pipe3_calibrate, %function
ti_pipe3_calibrate:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	mov	r4, r0
	ldr	r6, .L5
	ldr	r0, [r0, #4]
	ldr	r1, [r6]
	bl	ti_pipe3_readl
	ldr	r1, .L5+4
	ldr	ip, .L5+8
	ldr	r3, .L5+12
	ldr	ip, [ip]
	ldr	r1, [r1]
	ldr	r3, [r3]
	ldr	r2, .L5+16
	orr	r1, r1, ip
	ldr	ip, .L5+20
	ldr	r2, [r2]
	orr	r1, r1, r3
	ldr	r3, [r4, #12]
	ldr	ip, [ip]
	ldr	lr, [r4, #8]
	lsl	r3, r3, r2
	orr	r3, r3, lr, lsl ip
	ldr	r5, .L5+24
	bic	r2, r0, r1
	orr	r2, r3, r2
	ldr	r1, [r6]
	ldr	r0, [r4, #4]
	bl	ti_pipe3_writel
	ldr	r1, [r5]
	ldr	r0, [r4, #4]
	bl	ti_pipe3_readl
	ldr	r1, .L5+28
	ldr	r2, .L5+32
	ldr	r1, [r1]
	ldr	r2, [r2]
	ldr	ip, .L5+36
	orr	r1, r1, r2
	ldr	r2, .L5+40
	ldr	ip, [ip]
	ldr	r2, [r2]
	orr	r1, r1, ip
	orr	r1, r1, r2
	ldr	r2, .L5+44
	ldr	r3, .L5+48
	ldr	r2, [r2]
	ldr	ip, [r4, #20]
	orr	r1, r1, r2
	ldr	r2, .L5+52
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	lr, .L5+56
	orr	r1, r1, r2
	ldr	r2, .L5+60
	ldr	lr, [lr]
	ldr	r6, [r4, #16]
	ldr	r2, [r2]
	lsl	r3, ip, r3
	ldr	ip, .L5+64
	orr	r3, r3, r6, lsl lr
	ldr	ip, [ip]
	ldr	r6, [r4, #24]
	orr	r1, r1, r2
	ldr	lr, .L5+68
	ldr	r2, .L5+72
	ldr	lr, [lr]
	ldr	r2, [r2]
	orr	r3, r3, r6, lsl ip
	ldr	r6, [r4, #28]
	ldr	ip, .L5+76
	orr	r3, r3, r6, lsl lr
	ldr	ip, [ip]
	ldr	r6, [r4, #32]
	orr	r1, r1, r2
	ldr	lr, .L5+80
	ldr	r2, .L5+84
	ldr	lr, [lr]
	ldr	r2, [r2]
	orr	r3, r3, r6, lsl ip
	ldr	r6, [r4, #36]
	ldr	ip, .L5+88
	orr	r1, r1, r2
	ldr	ip, [ip]
	orr	r3, r3, r6, lsl lr
	ldr	r2, .L5+92
	ldr	lr, [r4, #40]
	ldr	r2, [r2]
	orr	r3, r3, lr, lsl ip
	ldr	lr, [r4, #44]
	ldr	ip, .L5+96
	orr	r3, r3, lr, lsl r2
	ldr	ip, [ip]
	ldr	lr, [r4, #48]
	bic	r2, r0, r1
	orr	r3, r3, lr, lsl ip
	ldr	r7, .L5+100
	orr	r2, r3, r2
	ldr	r1, [r5]
	ldr	r0, [r4, #4]
	bl	ti_pipe3_writel
	ldr	r1, [r7]
	ldr	r0, [r4, #4]
	bl	ti_pipe3_readl
	ldr	r2, .L5+104
	ldr	r3, .L5+108
	ldr	r1, [r2]
	ldr	r3, [r3]
	ldr	r2, [r4, #52]
	ldr	r6, .L5+112
	bic	r0, r0, r1
	orr	r2, r0, r2, lsl r3
	ldr	r1, [r7]
	ldr	r0, [r4, #4]
	bl	ti_pipe3_writel
	ldr	r1, [r6]
	ldr	r0, [r4, #4]
	bl	ti_pipe3_readl
	ldr	r2, .L5+116
	ldr	r3, .L5+120
	ldr	r1, [r2]
	ldr	r3, [r3]
	ldr	r2, [r4, #56]
	bic	r0, r0, r1
	ldr	r5, .L5+124
	orr	r2, r0, r2, lsl r3
	ldr	r1, [r6]
	ldr	r0, [r4, #4]
	bl	ti_pipe3_writel
	ldr	r1, [r5]
	ldr	r0, [r4, #4]
	bl	ti_pipe3_readl
	ldr	r1, .L5+128
	ldr	r2, .L5+132
	ldr	r1, [r1]
	ldr	r2, [r2]
	ldr	r3, .L5+136
	orr	r1, r1, r2
	ldr	r2, .L5+140
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	ip, .L5+144
	orr	r1, r1, r3
	ldr	ip, [ip]
	ldr	r3, [r4, #64]
	orr	r1, r1, r2
	ldr	lr, .L5+148
	ldr	r2, .L5+152
	ldr	lr, [lr]
	ldr	r2, [r2]
	ldr	r6, [r4, #60]
	lsl	r3, r3, ip
	ldr	ip, .L5+156
	orr	r1, r1, r2
	ldr	ip, [ip]
	orr	r3, r3, r6, lsl lr
	ldr	r2, .L5+160
	ldr	lr, [r4, #68]
	ldr	r2, [r2]
	orr	r3, r3, lr, lsl ip
	ldr	lr, [r4, #72]
	ldr	ip, .L5+164
	orr	r3, r3, lr, lsl r2
	ldr	ip, [ip]
	ldr	lr, [r4, #76]
	bic	r2, r0, r1
	orr	r3, r3, lr, lsl ip
	orr	r2, r3, r2
	ldr	r1, [r5]
	ldr	r0, [r4, #4]
	bl	ti_pipe3_writel
	ldr	r3, .L5+168
	ldr	r2, [r4]
	ldr	r3, [r3]
	cmp	r2, r3
	popne	{r4, r5, r6, r7, r8, pc}
	ldr	r5, .L5+172
	ldr	r0, [r4, #4]
	ldr	r1, [r5]
	bl	ti_pipe3_readl
	mov	r3, r0
	ldr	r2, .L5+176
	ldr	r1, [r5]
	ldr	r2, [r2]
	ldr	r0, [r4, #4]
	bic	r2, r3, r2
	pop	{r4, r5, r6, r7, r8, lr}
	b	ti_pipe3_writel
.L6:
	.align	2
.L5:
	.word	PIPE3_PHY_RX_ANA_PROGRAMMABILITY
	.word	INTERFACE_MASK
	.word	LOSD_MASK
	.word	MEM_PLLDIV
	.word	LOSD_SHIFT
	.word	INTERFACE_SHIFT
	.word	PIPE3_PHY_RX_DIGITAL_MODES
	.word	MEM_HS_RATE_MASK
	.word	MEM_OVRD_HS_RATE
	.word	MEM_CDR_FASTLOCK
	.word	MEM_CDR_LBW_MASK
	.word	MEM_CDR_STEPCNT_MASK
	.word	MEM_OVRD_HS_RATE_SHIFT
	.word	MEM_CDR_STL_MASK
	.word	MEM_HS_RATE_SHIFT
	.word	MEM_CDR_THR_MASK
	.word	MEM_CDR_FASTLOCK_SHIFT
	.word	MEM_CDR_LBW_SHIFT
	.word	MEM_CDR_THR_MODE
	.word	MEM_CDR_STEPCNT_SHIFT
	.word	MEM_CDR_STL_SHIFT
	.word	MEM_CDR_2NDO_SDM_MODE
	.word	MEM_CDR_THR_SHIFT
	.word	MEM_CDR_THR_MODE_SHIFT
	.word	MEM_CDR_2NDO_SDM_MODE_SHIFT
	.word	PIPE3_PHY_RX_TRIM
	.word	MEM_DLL_TRIM_SEL_MASK
	.word	MEM_DLL_TRIM_SHIFT
	.word	PIPE3_PHY_RX_DLL
	.word	MEM_DLL_PHINT_RATE_MASK
	.word	MEM_DLL_PHINT_RATE_SHIFT
	.word	PIPE3_PHY_RX_EQUALIZER
	.word	MEM_EQLEV_MASK
	.word	MEM_EQFTC_MASK
	.word	MEM_EQCTL_MASK
	.word	MEM_OVRD_EQLEV
	.word	MEM_EQFTC_SHIFT
	.word	MEM_EQLEV_SHIFT
	.word	MEM_OVRD_EQFTC
	.word	MEM_EQCTL_SHIFT
	.word	MEM_OVRD_EQLEV_SHIFT
	.word	MEM_OVRD_EQFTC_SHIFT
	.word	PIPE3_MODE_SATA
	.word	SATA_PHY_RX_IO_AND_A2D_OVERRIDES
	.word	MEM_CDR_LOS_SOURCE_MASK
	.size	ti_pipe3_calibrate, .-ti_pipe3_calibrate
	.comm	SATA_PHY_RX_IO_AND_A2D_OVERRIDES,4,4
	.comm	PIPE3_PHY_RX_TRIM,4,4
	.comm	PIPE3_PHY_RX_EQUALIZER,4,4
	.comm	PIPE3_PHY_RX_DLL,4,4
	.comm	PIPE3_PHY_RX_DIGITAL_MODES,4,4
	.comm	PIPE3_PHY_RX_ANA_PROGRAMMABILITY,4,4
	.comm	PIPE3_MODE_SATA,4,4
	.comm	MEM_PLLDIV,4,4
	.comm	MEM_OVRD_HS_RATE_SHIFT,4,4
	.comm	MEM_OVRD_HS_RATE,4,4
	.comm	MEM_OVRD_EQLEV_SHIFT,4,4
	.comm	MEM_OVRD_EQLEV,4,4
	.comm	MEM_OVRD_EQFTC_SHIFT,4,4
	.comm	MEM_OVRD_EQFTC,4,4
	.comm	MEM_HS_RATE_SHIFT,4,4
	.comm	MEM_HS_RATE_MASK,4,4
	.comm	MEM_EQLEV_SHIFT,4,4
	.comm	MEM_EQLEV_MASK,4,4
	.comm	MEM_EQFTC_SHIFT,4,4
	.comm	MEM_EQFTC_MASK,4,4
	.comm	MEM_EQCTL_SHIFT,4,4
	.comm	MEM_EQCTL_MASK,4,4
	.comm	MEM_DLL_TRIM_SHIFT,4,4
	.comm	MEM_DLL_TRIM_SEL_MASK,4,4
	.comm	MEM_DLL_PHINT_RATE_SHIFT,4,4
	.comm	MEM_DLL_PHINT_RATE_MASK,4,4
	.comm	MEM_CDR_THR_SHIFT,4,4
	.comm	MEM_CDR_THR_MODE_SHIFT,4,4
	.comm	MEM_CDR_THR_MODE,4,4
	.comm	MEM_CDR_THR_MASK,4,4
	.comm	MEM_CDR_STL_SHIFT,4,4
	.comm	MEM_CDR_STL_MASK,4,4
	.comm	MEM_CDR_STEPCNT_SHIFT,4,4
	.comm	MEM_CDR_STEPCNT_MASK,4,4
	.comm	MEM_CDR_LOS_SOURCE_MASK,4,4
	.comm	MEM_CDR_LBW_SHIFT,4,4
	.comm	MEM_CDR_LBW_MASK,4,4
	.comm	MEM_CDR_FASTLOCK_SHIFT,4,4
	.comm	MEM_CDR_FASTLOCK,4,4
	.comm	MEM_CDR_2NDO_SDM_MODE_SHIFT,4,4
	.comm	MEM_CDR_2NDO_SDM_MODE,4,4
	.comm	LOSD_SHIFT,4,4
	.comm	LOSD_MASK,4,4
	.comm	INTERFACE_SHIFT,4,4
	.comm	INTERFACE_MASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
