	.file	"extr_r100.c_r100_cp_init.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC0:
	.string	"Failed to register debugfs file for CP !\n"
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Failed to load firmware!\n"
.LC2:
	.string	"radeon: ring at 0x%016lX\n"
	.section	.rodata.str1.8
	.align 8
.LC3:
	.string	"radeon: cp isn't working (%d).\n"
	.align 8
.LC4:
	.string	"failed to get scratch reg for rptr save (%d).\n"
	.text
	.p2align 4
	.globl	r100_cp_init
	.type	r100_cp_init, @function
r100_cp_init:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	mov	r13d, esi
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	sub	rsp, 8
	.cfi_def_cfa_offset 48
	mov	rax, QWORD PTR RADEON_RING_TYPE_GFX_INDEX[rip]
	lea	rdx, [rax+rax*2]
	mov	rax, QWORD PTR 8[rdi]
	lea	rbx, [rax+rdx*8]
	call	r100_debugfs_cp_init@PLT
	test	rax, rax
	jne	.L24
.L2:
	mov	eax, DWORD PTR 40[rbp]
	test	eax, eax
	jne	.L3
	mov	rdi, rbp
	call	r100_cp_init_microcode@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L25
.L3:
	mov	edi, r13d
	shr	edi, 3
	call	order_base_2@PLT
	mov	rdi, rbp
	mov	r13d, eax
	call	r100_cp_load_microcode@PLT
	lea	ecx, 1[r13]
	mov	rsi, rbx
	mov	rdi, rbp
	mov	edx, 4
	mov	r8d, DWORD PTR RADEON_CP_PACKET2[rip]
	sal	edx, cl
	mov	ecx, DWORD PTR RADEON_WB_CP_RPTR_OFFSET[rip]
	call	radeon_ring_init@PLT
	mov	r12d, eax
	test	eax, eax
	je	.L26
.L1:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	eax, r12d
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L26:
	.cfi_restore_state
	mov	DWORD PTR [rbx], 15
	mov	esi, 64
	mov	edi, 1816
	call	WREG32@PLT
	mov	edi, DWORD PTR RADEON_RB_BUFSZ[rip]
	mov	esi, r13d
	call	REG_SET@PLT
	mov	edi, DWORD PTR RADEON_RB_BLKSZ[rip]
	mov	esi, 9
	mov	r12d, eax
	call	REG_SET@PLT
	mov	edi, DWORD PTR RADEON_MAX_FETCH[rip]
	mov	esi, 1
	or	r12d, eax
	call	REG_SET@PLT
	mov	esi, DWORD PTR RADEON_RB_NO_UPDATE[rip]
	mov	edi, DWORD PTR RADEON_CP_RB_CNTL[rip]
	or	r12d, eax
	or	esi, r12d
	call	WREG32@PLT
	movsx	rsi, DWORD PTR 4[rbx]
	lea	rdi, .LC2[rip]
	call	DRM_INFO@PLT
	mov	esi, DWORD PTR 4[rbx]
	mov	edi, DWORD PTR RADEON_CP_RB_BASE[rip]
	call	WREG32@PLT
	mov	esi, DWORD PTR RADEON_RB_RPTR_WR_ENA[rip]
	mov	edi, DWORD PTR RADEON_CP_RB_CNTL[rip]
	or	esi, DWORD PTR RADEON_RB_NO_UPDATE[rip]
	or	esi, r12d
	call	WREG32@PLT
	mov	edi, DWORD PTR RADEON_CP_RB_RPTR_WR[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	DWORD PTR 8[rbx], 0
	mov	edi, DWORD PTR RADEON_CP_RB_WPTR[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	edi, DWORD PTR RADEON_WB_CP_RPTR_OFFSET[rip]
	add	edi, DWORD PTR 24[rbp]
	sar	edi, 2
	call	S_00070C_RB_RPTR_ADDR@PLT
	mov	edi, DWORD PTR R_00070C_CP_RB_RPTR_ADDR[rip]
	mov	esi, eax
	call	WREG32@PLT
	mov	edi, DWORD PTR R_000774_SCRATCH_ADDR[rip]
	mov	esi, DWORD PTR RADEON_WB_SCRATCH_OFFSET[rip]
	add	esi, DWORD PTR 24[rbp]
	call	WREG32@PLT
	cmp	QWORD PTR 32[rbp], 0
	je	.L5
	mov	edi, DWORD PTR R_000770_SCRATCH_UMSK[rip]
	mov	esi, 255
	call	WREG32@PLT
.L6:
	mov	edi, DWORD PTR RADEON_CP_RB_CNTL[rip]
	mov	esi, r12d
	call	WREG32@PLT
	mov	edi, 10
	call	udelay@PLT
	mov	edi, DWORD PTR RADEON_INDIRECT2_START[rip]
	mov	esi, 80
	call	REG_SET@PLT
	mov	edi, DWORD PTR RADEON_INDIRECT1_START[rip]
	mov	esi, 16
	mov	r12d, eax
	call	REG_SET@PLT
	mov	edi, DWORD PTR RADEON_CP_CSQ_MODE[rip]
	mov	esi, r12d
	or	esi, eax
	call	WREG32@PLT
	mov	edi, DWORD PTR RADEON_CP_RB_WPTR_DELAY[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	edi, DWORD PTR RADEON_CP_CSQ_MODE[rip]
	mov	esi, 19789
	call	WREG32@PLT
	mov	esi, DWORD PTR RADEON_CSQ_PRIBM_INDBM[rip]
	mov	edi, DWORD PTR RADEON_CP_CSQ_CNTL[rip]
	call	WREG32@PLT
	mov	edi, DWORD PTR 16[rbp]
	call	pci_set_master@PLT
	mov	rsi, QWORD PTR RADEON_RING_TYPE_GFX_INDEX[rip]
	mov	rax, QWORD PTR 8[rbp]
	mov	rdi, rbp
	lea	rdx, [rsi+rsi*2]
	lea	rdx, [rax+rdx*8]
	call	radeon_ring_start@PLT
	mov	rsi, QWORD PTR RADEON_RING_TYPE_GFX_INDEX[rip]
	mov	rdx, rbx
	mov	rdi, rbp
	call	radeon_ring_test@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L27
	mov	DWORD PTR 12[rbx], 1
	mov	esi, DWORD PTR 0[rbp]
	mov	rdi, rbp
	call	radeon_ttm_set_active_vram_size@PLT
	cmp	QWORD PTR 16[rbx], 0
	jne	.L1
	mov	rsi, rbx
	mov	rdi, rbp
	call	radeon_ring_supports_scratch_reg@PLT
	test	rax, rax
	je	.L1
	lea	rsi, 16[rbx]
	mov	rdi, rbp
	call	radeon_scratch_get@PLT
	test	eax, eax
	je	.L1
	mov	esi, eax
	lea	rdi, .LC4[rip]
	xor	eax, eax
	call	DRM_ERROR@PLT
	mov	QWORD PTR 16[rbx], 0
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L24:
	lea	rdi, .LC0[rip]
	xor	eax, eax
	call	DRM_ERROR@PLT
	jmp	.L2
	.p2align 4,,10
	.p2align 3
.L5:
	mov	edi, DWORD PTR R_000770_SCRATCH_UMSK[rip]
	xor	esi, esi
	or	r12d, DWORD PTR RADEON_RB_NO_UPDATE[rip]
	call	WREG32@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L25:
	lea	rdi, .LC1[rip]
	xor	eax, eax
	call	DRM_ERROR@PLT
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	eax, r12d
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L27:
	.cfi_restore_state
	mov	esi, eax
	lea	rdi, .LC3[rip]
	xor	eax, eax
	call	DRM_ERROR@PLT
	add	rsp, 8
	.cfi_def_cfa_offset 40
	mov	eax, r12d
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE0:
	.size	r100_cp_init, .-r100_cp_init
	.comm	R_000774_SCRATCH_ADDR,4,4
	.comm	R_000770_SCRATCH_UMSK,4,4
	.comm	R_00070C_CP_RB_RPTR_ADDR,4,4
	.comm	RADEON_WB_SCRATCH_OFFSET,4,4
	.comm	RADEON_WB_CP_RPTR_OFFSET,4,4
	.comm	RADEON_RING_TYPE_GFX_INDEX,8,8
	.comm	RADEON_RB_RPTR_WR_ENA,4,4
	.comm	RADEON_RB_NO_UPDATE,4,4
	.comm	RADEON_RB_BUFSZ,4,4
	.comm	RADEON_RB_BLKSZ,4,4
	.comm	RADEON_MAX_FETCH,4,4
	.comm	RADEON_INDIRECT2_START,4,4
	.comm	RADEON_INDIRECT1_START,4,4
	.comm	RADEON_CSQ_PRIBM_INDBM,4,4
	.comm	RADEON_CP_RB_WPTR_DELAY,4,4
	.comm	RADEON_CP_RB_WPTR,4,4
	.comm	RADEON_CP_RB_RPTR_WR,4,4
	.comm	RADEON_CP_RB_CNTL,4,4
	.comm	RADEON_CP_RB_BASE,4,4
	.comm	RADEON_CP_PACKET2,4,4
	.comm	RADEON_CP_CSQ_MODE,4,4
	.comm	RADEON_CP_CSQ_CNTL,4,4
	.comm	RADEON_BUF_SWAP_32BIT,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_r100.c_r100_cp_init.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"Failed to register debugfs file for CP !\012\000"
	.align	2
.LC1:
	.ascii	"Failed to load firmware!\012\000"
	.align	2
.LC2:
	.ascii	"radeon: ring at 0x%016lX\012\000"
	.align	2
.LC3:
	.ascii	"radeon: cp isn't working (%d).\012\000"
	.align	2
.LC4:
	.ascii	"failed to get scratch reg for rptr save (%d).\012\000"
	.text
	.align	2
	.global	r100_cp_init
	.syntax unified
	.arm
	.fpu softvfp
	.type	r100_cp_init, %function
r100_cp_init:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r8, .L28
	ldr	r9, [r0, #4]
	ldr	r3, [r8]
	sub	sp, sp, #12
	add	r3, r3, r3, lsl #2
	mov	r4, r0
	mov	r7, r1
	add	r10, r9, r3, lsl #2
	lsl	r6, r3, #2
	bl	r100_debugfs_cp_init
	cmp	r0, #0
	bne	.L24
.L2:
	ldr	r3, [r4, #20]
	cmp	r3, #0
	bne	.L3
	mov	r0, r4
	bl	r100_cp_init_microcode
	subs	r5, r0, #0
	bne	.L25
.L3:
	lsr	r0, r7, #3
	bl	order_base_2
	mov	fp, r0
	mov	r0, r4
	bl	r100_cp_load_microcode
	mov	r1, #4
	ldr	r3, .L28+4
	ldr	r7, .L28+8
	ldr	r3, [r3]
	add	r2, fp, #1
	str	r3, [sp]
	lsl	r2, r1, r2
	mov	r0, r4
	mov	r1, r10
	ldr	r3, [r7]
	bl	radeon_ring_init
	subs	r5, r0, #0
	beq	.L26
.L1:
	mov	r0, r5
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L26:
	mov	r3, #15
	mov	r1, #64
	str	r3, [r9, r6]
	ldr	r0, .L28+12
	bl	WREG32
	ldr	r3, .L28+16
	mov	r1, fp
	ldr	r0, [r3]
	bl	REG_SET
	ldr	r3, .L28+20
	mov	r6, r0
	mov	r1, #9
	ldr	r0, [r3]
	bl	REG_SET
	mov	r3, r0
	ldr	r2, .L28+24
	mov	r1, #1
	ldr	r0, [r2]
	orr	r6, r6, r3
	bl	REG_SET
	ldr	fp, .L28+28
	ldr	r9, .L28+32
	ldr	r1, [fp]
	orr	r6, r6, r0
	orr	r1, r6, r1
	ldr	r0, [r9]
	bl	WREG32
	ldr	r1, [r10, #4]
	ldr	r0, .L28+36
	bl	DRM_INFO
	ldr	r3, .L28+40
	ldr	r1, [r10, #4]
	ldr	r0, [r3]
	bl	WREG32
	ldr	r2, .L28+44
	ldr	r3, [fp]
	ldr	r1, [r2]
	ldr	r0, [r9]
	orr	r1, r1, r3
	orr	r1, r1, r6
	bl	WREG32
	ldr	r3, .L28+48
	mov	r1, r5
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L28+52
	mov	r1, r5
	ldr	r0, [r3]
	str	r5, [r10, #8]
	bl	WREG32
	ldr	r2, [r7]
	ldr	r0, [r4, #12]
	ldr	r3, .L28+56
	add	r0, r0, r2
	asr	r0, r0, #2
	ldr	r5, [r3]
	bl	S_00070C_RB_RPTR_ADDR
	mov	r1, r0
	mov	r0, r5
	bl	WREG32
	ldr	r3, .L28+60
	ldr	r1, [r4, #12]
	ldr	r2, [r3]
	ldr	r3, .L28+64
	add	r1, r1, r2
	ldr	r0, [r3]
	bl	WREG32
	ldr	r1, [r4, #16]
	cmp	r1, #0
	ldrne	r3, .L28+68
	ldreq	r2, .L28+68
	ldreq	r3, [fp]
	movne	r1, #255
	orreq	r6, r6, r3
	ldrne	r0, [r3]
	ldreq	r0, [r2]
	bl	WREG32
	mov	r1, r6
	ldr	r0, [r9]
	bl	WREG32
	mov	r0, #10
	bl	udelay
	ldr	r3, .L28+72
	ldr	r6, .L28+76
	mov	r1, #80
	ldr	r0, [r3]
	ldr	r7, [r6]
	bl	REG_SET
	ldr	r3, .L28+80
	mov	r5, r0
	mov	r1, #16
	ldr	r0, [r3]
	bl	REG_SET
	mov	r1, r0
	mov	r0, r7
	orr	r1, r5, r1
	bl	WREG32
	ldr	r3, .L28+84
	mov	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	ldr	r1, .L28+88
	ldr	r0, [r6]
	bl	WREG32
	ldr	r2, .L28+92
	ldr	r3, .L28+96
	ldr	r1, [r2]
	ldr	r0, [r3]
	bl	WREG32
	ldr	r0, [r4, #8]
	bl	pci_set_master
	ldr	r1, [r8]
	ldr	r3, [r4, #4]
	add	r2, r1, r1, lsl #2
	add	r2, r3, r2, lsl #2
	mov	r0, r4
	bl	radeon_ring_start
	mov	r2, r10
	mov	r0, r4
	ldr	r1, [r8]
	bl	radeon_ring_test
	subs	r5, r0, #0
	bne	.L27
	mov	r3, #1
	ldr	r1, [r4]
	mov	r0, r4
	str	r3, [r10, #12]
	bl	radeon_ttm_set_active_vram_size
	ldr	r3, [r10, #16]
	cmp	r3, #0
	bne	.L1
	mov	r1, r10
	mov	r0, r4
	bl	radeon_ring_supports_scratch_reg
	cmp	r0, #0
	beq	.L1
	add	r1, r10, #16
	mov	r0, r4
	bl	radeon_scratch_get
	subs	r1, r0, #0
	beq	.L1
	ldr	r0, .L28+100
	bl	DRM_ERROR
	str	r5, [r10, #16]
	b	.L1
.L24:
	ldr	r0, .L28+104
	bl	DRM_ERROR
	b	.L2
.L25:
	ldr	r0, .L28+108
	bl	DRM_ERROR
	mov	r0, r5
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L27:
	mov	r1, r5
	ldr	r0, .L28+112
	bl	DRM_ERROR
	mov	r0, r5
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L29:
	.align	2
.L28:
	.word	RADEON_RING_TYPE_GFX_INDEX
	.word	RADEON_CP_PACKET2
	.word	RADEON_WB_CP_RPTR_OFFSET
	.word	1816
	.word	RADEON_RB_BUFSZ
	.word	RADEON_RB_BLKSZ
	.word	RADEON_MAX_FETCH
	.word	RADEON_RB_NO_UPDATE
	.word	RADEON_CP_RB_CNTL
	.word	.LC2
	.word	RADEON_CP_RB_BASE
	.word	RADEON_RB_RPTR_WR_ENA
	.word	RADEON_CP_RB_RPTR_WR
	.word	RADEON_CP_RB_WPTR
	.word	R_00070C_CP_RB_RPTR_ADDR
	.word	RADEON_WB_SCRATCH_OFFSET
	.word	R_000774_SCRATCH_ADDR
	.word	R_000770_SCRATCH_UMSK
	.word	RADEON_INDIRECT2_START
	.word	RADEON_CP_CSQ_MODE
	.word	RADEON_INDIRECT1_START
	.word	RADEON_CP_RB_WPTR_DELAY
	.word	19789
	.word	RADEON_CSQ_PRIBM_INDBM
	.word	RADEON_CP_CSQ_CNTL
	.word	.LC4
	.word	.LC0
	.word	.LC1
	.word	.LC3
	.size	r100_cp_init, .-r100_cp_init
	.comm	R_000774_SCRATCH_ADDR,4,4
	.comm	R_000770_SCRATCH_UMSK,4,4
	.comm	R_00070C_CP_RB_RPTR_ADDR,4,4
	.comm	RADEON_WB_SCRATCH_OFFSET,4,4
	.comm	RADEON_WB_CP_RPTR_OFFSET,4,4
	.comm	RADEON_RING_TYPE_GFX_INDEX,4,4
	.comm	RADEON_RB_RPTR_WR_ENA,4,4
	.comm	RADEON_RB_NO_UPDATE,4,4
	.comm	RADEON_RB_BUFSZ,4,4
	.comm	RADEON_RB_BLKSZ,4,4
	.comm	RADEON_MAX_FETCH,4,4
	.comm	RADEON_INDIRECT2_START,4,4
	.comm	RADEON_INDIRECT1_START,4,4
	.comm	RADEON_CSQ_PRIBM_INDBM,4,4
	.comm	RADEON_CP_RB_WPTR_DELAY,4,4
	.comm	RADEON_CP_RB_WPTR,4,4
	.comm	RADEON_CP_RB_RPTR_WR,4,4
	.comm	RADEON_CP_RB_CNTL,4,4
	.comm	RADEON_CP_RB_BASE,4,4
	.comm	RADEON_CP_PACKET2,4,4
	.comm	RADEON_CP_CSQ_MODE,4,4
	.comm	RADEON_CP_CSQ_CNTL,4,4
	.comm	RADEON_BUF_SWAP_32BIT,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
