	.file	"extr_phy-fsl-usb.c_fsl_otg_init_timers.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	fsl_otg_init_timers
	.type	fsl_otg_init_timers, @function
fsl_otg_init_timers:
.LFB0:
	.cfi_startproc
	endbr64
	sub	rsp, 24
	.cfi_def_cfa_offset 32
	mov	rdx, rdi
	mov	esi, DWORD PTR TA_WAIT_VRISE[rip]
	mov	QWORD PTR 8[rsp], rdi
	add	rdx, 20
	lea	rdi, set_tmout[rip]
	call	otg_timer_initializer@PLT
	mov	QWORD PTR a_wait_vrise_tmr[rip], rax
	test	rax, rax
	je	.L14
	mov	rax, QWORD PTR 8[rsp]
	mov	esi, DWORD PTR TA_WAIT_BCON[rip]
	lea	rdi, set_tmout[rip]
	lea	rdx, 16[rax]
	call	otg_timer_initializer@PLT
	mov	QWORD PTR a_wait_bcon_tmr[rip], rax
	test	rax, rax
	je	.L14
	mov	rax, QWORD PTR 8[rsp]
	mov	esi, DWORD PTR TA_AIDL_BDIS[rip]
	lea	rdi, set_tmout[rip]
	lea	rdx, 12[rax]
	call	otg_timer_initializer@PLT
	mov	QWORD PTR a_aidl_bdis_tmr[rip], rax
	test	rax, rax
	je	.L14
	mov	rax, QWORD PTR 8[rsp]
	mov	esi, DWORD PTR TB_ASE0_BRST[rip]
	lea	rdi, set_tmout[rip]
	lea	rdx, 8[rax]
	call	otg_timer_initializer@PLT
	mov	QWORD PTR b_ase0_brst_tmr[rip], rax
	test	rax, rax
	je	.L14
	mov	rax, QWORD PTR 8[rsp]
	mov	esi, DWORD PTR TB_SE0_SRP[rip]
	lea	rdi, set_tmout[rip]
	lea	rdx, 4[rax]
	call	otg_timer_initializer@PLT
	mov	QWORD PTR b_se0_srp_tmr[rip], rax
	test	rax, rax
	je	.L14
	mov	rdx, QWORD PTR 8[rsp]
	mov	esi, DWORD PTR TB_SRP_FAIL[rip]
	lea	rdi, set_tmout[rip]
	call	otg_timer_initializer@PLT
	mov	QWORD PTR b_srp_fail_tmr[rip], rax
	test	rax, rax
	je	.L14
	lea	rdx, 8[rsp]
	mov	esi, 10
	lea	rdi, a_wait_enum[rip]
	call	otg_timer_initializer@PLT
	mov	QWORD PTR a_wait_enum_tmr[rip], rax
	test	rax, rax
	je	.L14
	mov	esi, DWORD PTR TB_SRP_WAIT[rip]
	xor	edx, edx
	lea	rdi, b_srp_end[rip]
	call	otg_timer_initializer@PLT
	mov	QWORD PTR b_srp_wait_tmr[rip], rax
	test	rax, rax
	je	.L14
	mov	esi, DWORD PTR TB_DATA_PLS[rip]
	xor	edx, edx
	lea	rdi, b_data_pulse_end[rip]
	call	otg_timer_initializer@PLT
	mov	QWORD PTR b_data_pulse_tmr[rip], rax
	test	rax, rax
	je	.L14
	mov	esi, DWORD PTR TB_VBUS_PLS[rip]
	xor	edx, edx
	lea	rdi, b_vbus_pulse_end[rip]
	call	otg_timer_initializer@PLT
	mov	rdx, rax
	mov	QWORD PTR b_vbus_pulse_tmr[rip], rax
	xor	eax, eax
	test	rdx, rdx
	jne	.L1
	.p2align 4,,10
	.p2align 3
.L14:
	mov	eax, DWORD PTR ENOMEM[rip]
	neg	eax
.L1:
	add	rsp, 24
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE0:
	.size	fsl_otg_init_timers, .-fsl_otg_init_timers
	.comm	set_tmout,4,4
	.comm	b_vbus_pulse_tmr,8,8
	.comm	b_vbus_pulse_end,4,4
	.comm	b_srp_wait_tmr,8,8
	.comm	b_srp_fail_tmr,8,8
	.comm	b_srp_end,4,4
	.comm	b_se0_srp_tmr,8,8
	.comm	b_data_pulse_tmr,8,8
	.comm	b_data_pulse_end,4,4
	.comm	b_ase0_brst_tmr,8,8
	.comm	a_wait_vrise_tmr,8,8
	.comm	a_wait_enum_tmr,8,8
	.comm	a_wait_enum,4,4
	.comm	a_wait_bcon_tmr,8,8
	.comm	a_aidl_bdis_tmr,8,8
	.comm	TB_VBUS_PLS,4,4
	.comm	TB_SRP_WAIT,4,4
	.comm	TB_SRP_FAIL,4,4
	.comm	TB_SE0_SRP,4,4
	.comm	TB_DATA_PLS,4,4
	.comm	TB_ASE0_BRST,4,4
	.comm	TA_WAIT_VRISE,4,4
	.comm	TA_WAIT_BCON,4,4
	.comm	TA_AIDL_BDIS,4,4
	.comm	ENOMEM,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_phy-fsl-usb.c_fsl_otg_init_timers.c"
	.text
	.align	2
	.global	fsl_otg_init_timers
	.syntax unified
	.arm
	.fpu softvfp
	.type	fsl_otg_init_timers, %function
fsl_otg_init_timers:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	str	lr, [sp, #-4]!
	ldr	r3, .L16
	sub	sp, sp, #12
	ldr	r1, [r3]
	str	r0, [sp, #4]
	add	r2, r0, #20
	ldr	r0, .L16+4
	bl	otg_timer_initializer
	ldr	r3, .L16+8
	cmp	r0, #0
	str	r0, [r3]
	beq	.L14
	ldr	r3, .L16+12
	ldr	r2, [sp, #4]
	ldr	r1, [r3]
	ldr	r0, .L16+4
	add	r2, r2, #16
	bl	otg_timer_initializer
	ldr	r3, .L16+16
	cmp	r0, #0
	str	r0, [r3]
	beq	.L14
	ldr	r3, .L16+20
	ldr	r2, [sp, #4]
	ldr	r1, [r3]
	ldr	r0, .L16+4
	add	r2, r2, #12
	bl	otg_timer_initializer
	ldr	r3, .L16+24
	cmp	r0, #0
	str	r0, [r3]
	beq	.L14
	ldr	r3, .L16+28
	ldr	r2, [sp, #4]
	ldr	r1, [r3]
	ldr	r0, .L16+4
	add	r2, r2, #8
	bl	otg_timer_initializer
	ldr	r3, .L16+32
	cmp	r0, #0
	str	r0, [r3]
	beq	.L14
	ldr	r3, .L16+36
	ldr	r2, [sp, #4]
	ldr	r1, [r3]
	ldr	r0, .L16+4
	add	r2, r2, #4
	bl	otg_timer_initializer
	ldr	r3, .L16+40
	cmp	r0, #0
	str	r0, [r3]
	beq	.L14
	ldr	r3, .L16+44
	ldr	r2, [sp, #4]
	ldr	r1, [r3]
	ldr	r0, .L16+4
	bl	otg_timer_initializer
	ldr	r3, .L16+48
	cmp	r0, #0
	str	r0, [r3]
	beq	.L14
	mov	r1, #10
	ldr	r0, .L16+52
	add	r2, sp, #4
	bl	otg_timer_initializer
	ldr	r3, .L16+56
	cmp	r0, #0
	str	r0, [r3]
	beq	.L14
	ldr	r3, .L16+60
	mov	r2, #0
	ldr	r1, [r3]
	ldr	r0, .L16+64
	bl	otg_timer_initializer
	ldr	r3, .L16+68
	cmp	r0, #0
	str	r0, [r3]
	beq	.L14
	ldr	r3, .L16+72
	mov	r2, #0
	ldr	r1, [r3]
	ldr	r0, .L16+76
	bl	otg_timer_initializer
	ldr	r3, .L16+80
	cmp	r0, #0
	str	r0, [r3]
	beq	.L14
	ldr	r3, .L16+84
	mov	r2, #0
	ldr	r1, [r3]
	ldr	r0, .L16+88
	bl	otg_timer_initializer
	ldr	r3, .L16+92
	cmp	r0, #0
	str	r0, [r3]
	movne	r0, #0
	bne	.L1
.L14:
	ldr	r3, .L16+96
	ldr	r0, [r3]
	rsb	r0, r0, #0
.L1:
	add	sp, sp, #12
	@ sp needed
	ldr	pc, [sp], #4
.L17:
	.align	2
.L16:
	.word	TA_WAIT_VRISE
	.word	set_tmout
	.word	a_wait_vrise_tmr
	.word	TA_WAIT_BCON
	.word	a_wait_bcon_tmr
	.word	TA_AIDL_BDIS
	.word	a_aidl_bdis_tmr
	.word	TB_ASE0_BRST
	.word	b_ase0_brst_tmr
	.word	TB_SE0_SRP
	.word	b_se0_srp_tmr
	.word	TB_SRP_FAIL
	.word	b_srp_fail_tmr
	.word	a_wait_enum
	.word	a_wait_enum_tmr
	.word	TB_SRP_WAIT
	.word	b_srp_end
	.word	b_srp_wait_tmr
	.word	TB_DATA_PLS
	.word	b_data_pulse_end
	.word	b_data_pulse_tmr
	.word	TB_VBUS_PLS
	.word	b_vbus_pulse_end
	.word	b_vbus_pulse_tmr
	.word	ENOMEM
	.size	fsl_otg_init_timers, .-fsl_otg_init_timers
	.comm	set_tmout,4,4
	.comm	b_vbus_pulse_tmr,4,4
	.comm	b_vbus_pulse_end,4,4
	.comm	b_srp_wait_tmr,4,4
	.comm	b_srp_fail_tmr,4,4
	.comm	b_srp_end,4,4
	.comm	b_se0_srp_tmr,4,4
	.comm	b_data_pulse_tmr,4,4
	.comm	b_data_pulse_end,4,4
	.comm	b_ase0_brst_tmr,4,4
	.comm	a_wait_vrise_tmr,4,4
	.comm	a_wait_enum_tmr,4,4
	.comm	a_wait_enum,4,4
	.comm	a_wait_bcon_tmr,4,4
	.comm	a_aidl_bdis_tmr,4,4
	.comm	TB_VBUS_PLS,4,4
	.comm	TB_SRP_WAIT,4,4
	.comm	TB_SRP_FAIL,4,4
	.comm	TB_SE0_SRP,4,4
	.comm	TB_DATA_PLS,4,4
	.comm	TB_ASE0_BRST,4,4
	.comm	TA_WAIT_VRISE,4,4
	.comm	TA_WAIT_BCON,4,4
	.comm	TA_AIDL_BDIS,4,4
	.comm	ENOMEM,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
