	.file	"extr_ni_dpm.c_ni_init_smc_spll_table.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	ni_init_smc_spll_table, @function
ni_init_smc_spll_table:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	mov	r12, rdi
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 72
	.cfi_def_cfa_offset 128
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 56[rsp], rax
	xor	eax, eax
	call	rv770_get_pi@PLT
	mov	rdi, r12
	mov	QWORD PTR 16[rsp], rax
	call	ni_get_pi@PLT
	cmp	QWORD PTR [rax], 0
	mov	QWORD PTR 24[rsp], rax
	jne	.L2
	mov	r8d, DWORD PTR EINVAL[rip]
	neg	r8d
.L1:
	mov	rax, QWORD PTR 56[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L26
	add	rsp, 72
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	eax, r8d
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L2:
	.cfi_restore_state
	mov	esi, DWORD PTR GFP_KERNEL[rip]
	mov	edi, 16
	xor	ebx, ebx
	call	kzalloc@PLT
	mov	r8d, DWORD PTR ENOMEM[rip]
	mov	rbp, rax
	lea	rax, 32[rsp]
	mov	QWORD PTR 8[rsp], rax
	neg	r8d
	test	rbp, rbp
	jne	.L4
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L28:
	mov	ecx, DWORD PTR SPLL_PDIV_A_SHIFT[rip]
	mov	esi, DWORD PTR 32[rsp]
	and	esi, DWORD PTR SPLL_PDIV_A_MASK[rip]
	mov	edx, DWORD PTR 40[rsp]
	sar	esi, cl
	mov	edi, DWORD PTR 44[rsp]
	mov	ecx, DWORD PTR CLK_S_SHIFT[rip]
	and	edx, DWORD PTR CLK_S_MASK[rip]
	and	edi, DWORD PTR CLK_V_MASK[rip]
	sar	edx, cl
	mov	ecx, DWORD PTR CLK_V_SHIFT[rip]
	mov	r10d, DWORD PTR SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK[rip]
	mov	r11d, DWORD PTR SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT[rip]
	mov	eax, DWORD PTR 36[rsp]
	mov	r14d, edx
	sar	edi, cl
	mov	ecx, DWORD PTR SPLL_FB_DIV_SHIFT[rip]
	and	eax, DWORD PTR SPLL_FB_DIV_MASK[rip]
	mov	r8d, r10d
	sar	edi, 6
	sar	eax, cl
	mov	ecx, r11d
	mov	r13d, edi
	sar	r8d, cl
	sar	eax
	not	r8d
	and	eax, -4096
	and	r8d, esi
	je	.L6
	mov	r8d, DWORD PTR EINVAL[rip]
	neg	r8d
.L6:
	mov	ecx, DWORD PTR SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT[rip]
	mov	edx, DWORD PTR SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK[rip]
	sar	edx, cl
	mov	ecx, edx
	not	ecx
	test	ecx, r14d
	je	.L7
	mov	r8d, DWORD PTR EINVAL[rip]
	neg	r8d
.L7:
	mov	ecx, DWORD PTR SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT[rip]
	mov	edx, DWORD PTR SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK[rip]
	sar	edx, cl
	mov	ecx, edx
	not	ecx
	test	ecx, r13d
	je	.L8
	mov	r8d, DWORD PTR EINVAL[rip]
	neg	r8d
.L8:
	test	r8d, r8d
	jne	.L5
	mov	ecx, DWORD PTR SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT[rip]
	mov	r15, QWORD PTR 8[rbp]
	sal	eax, cl
	mov	ecx, r11d
	and	eax, DWORD PTR SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK[rip]
	add	r15, rbx
	sal	esi, cl
	and	r10d, esi
	or	eax, r10d
	mov	edi, eax
	call	cpu_to_be32@PLT
	mov	ecx, DWORD PTR SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT[rip]
	mov	edi, r13d
	mov	edx, r14d
	mov	QWORD PTR [r15], rax
	mov	r15, QWORD PTR 0[rbp]
	sal	edi, cl
	mov	ecx, DWORD PTR SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT[rip]
	and	edi, DWORD PTR SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK[rip]
	add	r15, rbx
	add	rbx, 8
	sal	edx, cl
	and	edx, DWORD PTR SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK[rip]
	or	edi, edx
	call	cpu_to_be32@PLT
	mov	QWORD PTR [r15], rax
	cmp	rbx, 2048
	je	.L27
.L4:
	mov	rdx, QWORD PTR 8[rsp]
	mov	esi, ebx
	mov	rdi, r12
	sal	esi, 6
	call	ni_calculate_sclk_params@PLT
	mov	r8d, eax
	test	eax, eax
	je	.L28
.L5:
	mov	rdi, rbp
	mov	DWORD PTR 8[rsp], r8d
	call	kfree@PLT
	mov	r8d, DWORD PTR 8[rsp]
	jmp	.L1
.L27:
	mov	rax, QWORD PTR 16[rsp]
	mov	ecx, 16
	mov	rdx, rbp
	mov	rdi, r12
	mov	r8d, DWORD PTR [rax]
	mov	rax, QWORD PTR 24[rsp]
	mov	rsi, QWORD PTR [rax]
	call	rv770_copy_bytes_to_smc@PLT
	mov	r8d, eax
	jmp	.L5
.L26:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	ni_init_smc_spll_table, .-ni_init_smc_spll_table
	.comm	SPLL_PDIV_A_SHIFT,4,4
	.comm	SPLL_PDIV_A_MASK,4,4
	.comm	SPLL_FB_DIV_SHIFT,4,4
	.comm	SPLL_FB_DIV_MASK,4,4
	.comm	SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT,4,4
	.comm	SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK,4,4
	.comm	SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT,4,4
	.comm	SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK,4,4
	.comm	SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT,4,4
	.comm	SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK,4,4
	.comm	SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT,4,4
	.comm	SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK,4,4
	.comm	GFP_KERNEL,4,4
	.comm	ENOMEM,4,4
	.comm	EINVAL,4,4
	.comm	CLK_V_SHIFT,4,4
	.comm	CLK_V_MASK,4,4
	.comm	CLK_S_SHIFT,4,4
	.comm	CLK_S_MASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_ni_dpm.c_ni_init_smc_spll_table.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	ni_init_smc_spll_table, %function
ni_init_smc_spll_table:
	@ args = 0, pretend = 0, frame = 40
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r3, .L31
	sub	sp, sp, #52
	str	r0, [sp, #12]
	mov	r4, r0
	ldr	r3, [r3]
	str	r3, [sp, #44]
	mov	r3,#0
	bl	rv770_get_pi
	mov	r3, r0
	mov	r0, r4
	str	r3, [sp, #16]
	bl	ni_get_pi
	ldr	r3, [r0]
	str	r0, [sp, #20]
	cmp	r3, #0
	bne	.L2
	ldr	r3, .L31+4
	ldr	r4, [r3]
	rsb	r4, r4, #0
.L1:
	ldr	r3, .L31
	ldr	r2, [r3]
	ldr	r3, [sp, #44]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L27
	mov	r0, r4
	add	sp, sp, #52
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L2:
	ldr	r3, .L31+8
	mov	r0, #8
	ldr	r1, [r3]
	bl	kzalloc
	subs	r3, r0, #0
	movne	r6, #0
	str	r3, [sp, #8]
	bne	.L4
	b	.L28
.L30:
	ldr	r3, .L31+12
	ldr	r4, [sp, #28]
	ldr	r3, [r3]
	ldr	r0, .L31+16
	ldr	r1, .L31+20
	ldr	r0, [r0]
	and	r3, r3, r4
	ldr	r4, .L31+24
	ldr	r7, [sp, #32]
	ldr	r1, [r1]
	ldr	r4, [r4]
	asr	r3, r3, r0
	ldr	r5, [sp, #40]
	ldr	r0, .L31+28
	and	r1, r1, r7
	ldr	r2, .L31+32
	ldr	r7, .L31+36
	ldr	ip, .L31+40
	and	r5, r5, r4
	ldr	lr, .L31+44
	ldr	r4, [r0]
	ldr	r0, .L31+48
	ldr	r8, [r7]
	ldr	r2, [r2]
	ldr	ip, [ip]
	ldr	r7, [sp, #36]
	ldr	r0, [r0]
	ldr	lr, [lr]
	and	r7, r7, r4
	bics	r4, r3, r2, asr ip
	asr	r7, r7, r0
	asr	r1, r1, lr
	ldrne	r0, .L31+4
	ldr	lr, .L31+52
	asr	r5, r5, r8
	ldr	r9, .L31+56
	ldr	r8, .L31+60
	ldrne	r4, [r0]
	and	r1, lr, r1, asr #1
	ldr	r0, [r9]
	ldr	lr, [r8]
	rsbne	r4, r4, #0
	bics	r0, r7, lr, asr r0
	ldrne	r0, .L31+4
	ldr	r10, .L31+64
	ldr	fp, .L31+68
	ldrne	r4, [r0]
	ldr	lr, [r10]
	ldr	r0, [fp]
	asr	r5, r5, #6
	rsbne	r4, r4, #0
	bics	r0, r5, lr, asr r0
	ldrne	r0, .L31+4
	ldrne	r4, [r0]
	rsbne	r4, r4, #0
	cmp	r4, #0
	bne	.L5
	ldr	lr, .L31+72
	ldr	r0, .L31+76
	ldr	r4, [lr]
	ldr	lr, [r0]
	and	r3, r2, r3, lsl ip
	and	r0, lr, r1, lsl r4
	orr	r0, r0, r3
	ldr	r3, [sp, #8]
	ldr	r4, [r3, #4]
	bl	cpu_to_be32
	ldr	r3, [r8]
	ldr	ip, [fp]
	ldr	r2, [r10]
	ldr	r1, [r9]
	and	r5, r2, r5, lsl ip
	and	r7, r3, r7, lsl r1
	ldr	r3, [sp, #8]
	str	r0, [r4, r6]
	orr	r0, r5, r7
	ldr	r4, [r3]
	bl	cpu_to_be32
	str	r0, [r4, r6]
	add	r6, r6, #4
	cmp	r6, #1024
	beq	.L29
.L4:
	ldr	r0, [sp, #12]
	add	r2, sp, #28
	lsl	r1, r6, #7
	bl	ni_calculate_sclk_params
	subs	r4, r0, #0
	beq	.L30
.L5:
	ldr	r0, [sp, #8]
	bl	kfree
	b	.L1
.L29:
	ldr	r3, [sp, #20]
	ldr	r0, [sp, #12]
	ldr	r1, [r3]
	ldr	r3, [sp, #16]
	ldr	r2, [sp, #8]
	ldr	r3, [r3]
	str	r3, [sp]
	mov	r3, #8
	bl	rv770_copy_bytes_to_smc
	mov	r4, r0
	ldr	r0, [sp, #8]
	bl	kfree
	b	.L1
.L28:
	ldr	r3, .L31+80
	ldr	r4, [r3]
	rsb	r4, r4, #0
	b	.L1
.L27:
	bl	__stack_chk_fail
.L32:
	.align	2
.L31:
	.word	.LC0
	.word	EINVAL
	.word	GFP_KERNEL
	.word	SPLL_PDIV_A_MASK
	.word	SPLL_PDIV_A_SHIFT
	.word	SPLL_FB_DIV_MASK
	.word	CLK_V_MASK
	.word	CLK_S_MASK
	.word	SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK
	.word	CLK_V_SHIFT
	.word	SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT
	.word	SPLL_FB_DIV_SHIFT
	.word	CLK_S_SHIFT
	.word	-4096
	.word	SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT
	.word	SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK
	.word	SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK
	.word	SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT
	.word	SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT
	.word	SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK
	.word	ENOMEM
	.size	ni_init_smc_spll_table, .-ni_init_smc_spll_table
	.comm	SPLL_PDIV_A_SHIFT,4,4
	.comm	SPLL_PDIV_A_MASK,4,4
	.comm	SPLL_FB_DIV_SHIFT,4,4
	.comm	SPLL_FB_DIV_MASK,4,4
	.comm	SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT,4,4
	.comm	SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK,4,4
	.comm	SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT,4,4
	.comm	SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK,4,4
	.comm	SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT,4,4
	.comm	SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK,4,4
	.comm	SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT,4,4
	.comm	SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK,4,4
	.comm	GFP_KERNEL,4,4
	.comm	ENOMEM,4,4
	.comm	EINVAL,4,4
	.comm	CLK_V_SHIFT,4,4
	.comm	CLK_V_MASK,4,4
	.comm	CLK_S_SHIFT,4,4
	.comm	CLK_S_MASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
