	.file	"extr_intel_pm.c_vlv_atomic_update_fifo.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	vlv_atomic_update_fifo, @function
vlv_atomic_update_fifo:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	rbx, rsi
	sub	rsp, 8
	.cfi_def_cfa_offset 64
	mov	edi, DWORD PTR 16[rsi]
	call	to_intel_crtc@PLT
	mov	edi, DWORD PTR 4[rax]
	mov	r12, rax
	call	to_i915@PLT
	mov	edx, DWORD PTR [rbx]
	test	edx, edx
	jne	.L10
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L10:
	.cfi_restore_state
	mov	rdx, QWORD PTR PLANE_PRIMARY[rip]
	mov	rbp, rax
	mov	rax, QWORD PTR 8[rbx]
	xor	edi, edi
	mov	r13d, DWORD PTR [rax+rdx*4]
	mov	rdx, QWORD PTR PLANE_SPRITE0[rip]
	mov	ebx, DWORD PTR [rax+rdx*4]
	mov	rdx, QWORD PTR PLANE_SPRITE1[rip]
	mov	r14d, DWORD PTR [rax+rdx*4]
	mov	rdx, QWORD PTR PLANE_CURSOR[rip]
	add	ebx, r13d
	add	r14d, ebx
	cmp	DWORD PTR [rax+rdx*4], 63
	setne	dil
	call	WARN_ON@PLT
	xor	edi, edi
	cmp	r14d, 511
	setne	dil
	call	WARN_ON@PLT
	mov	ecx, r14d
	mov	edx, ebx
	mov	esi, r13d
	mov	rdi, r12
	call	trace_vlv_fifo_size@PLT
	mov	rdi, rbp
	call	spin_lock@PLT
	mov	eax, DWORD PTR [r12]
	cmp	eax, 129
	je	.L3
	cmp	eax, 130
	je	.L4
	cmp	eax, 128
	je	.L11
.L6:
	mov	esi, DWORD PTR DSPARB[rip]
	mov	rdi, rbp
	call	intel_uncore_posting_read_fw@PLT
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	rdi, rbp
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	jmp	spin_unlock@PLT
	.p2align 4,,10
	.p2align 3
.L3:
	.cfi_restore_state
	mov	esi, DWORD PTR DSPARB[rip]
	mov	rdi, rbp
	call	intel_uncore_read_fw@PLT
	mov	esi, DWORD PTR DSPARB2[rip]
	mov	rdi, rbp
	mov	r12d, eax
	call	intel_uncore_read_fw@PLT
	mov	edi, DWORD PTR SPRITEC[rip]
	mov	esi, 255
	mov	r15d, eax
	call	VLV_FIFO@PLT
	mov	edi, DWORD PTR SPRITED[rip]
	mov	esi, 255
	mov	r14d, eax
	call	VLV_FIFO@PLT
	mov	edi, DWORD PTR SPRITEC[rip]
	mov	esi, r13d
	or	r14d, eax
	call	VLV_FIFO@PLT
	mov	edi, DWORD PTR SPRITED[rip]
	mov	esi, ebx
	not	r14d
	and	r14d, r12d
	mov	r12d, eax
	sar	ebx, 8
	call	VLV_FIFO@PLT
	mov	edi, DWORD PTR SPRITEC_HI[rip]
	mov	esi, 255
	or	eax, r12d
	or	r14d, eax
	call	VLV_FIFO@PLT
	mov	edi, DWORD PTR SPRITED_HI[rip]
	mov	esi, 255
	mov	r12d, eax
	call	VLV_FIFO@PLT
	mov	edi, DWORD PTR SPRITEC_HI[rip]
	mov	esi, r13d
	or	r12d, eax
	sar	esi, 8
	call	VLV_FIFO@PLT
	not	r12d
	mov	edi, DWORD PTR SPRITED_HI[rip]
	mov	esi, ebx
	and	r15d, r12d
	mov	r12d, eax
.L8:
	call	VLV_FIFO@PLT
	mov	esi, DWORD PTR DSPARB[rip]
	mov	edx, r14d
	mov	rdi, rbp
	or	r12d, eax
	call	intel_uncore_write_fw@PLT
	or	r15d, r12d
	mov	esi, DWORD PTR DSPARB2[rip]
	mov	rdi, rbp
	mov	edx, r15d
	call	intel_uncore_write_fw@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L11:
	mov	esi, DWORD PTR DSPARB3[rip]
	mov	rdi, rbp
	call	intel_uncore_read_fw@PLT
	mov	esi, DWORD PTR DSPARB2[rip]
	mov	rdi, rbp
	mov	r14d, eax
	call	intel_uncore_read_fw@PLT
	mov	edi, DWORD PTR SPRITEE[rip]
	mov	esi, 255
	mov	r12d, eax
	call	VLV_FIFO@PLT
	mov	edi, DWORD PTR SPRITEF[rip]
	mov	esi, 255
	mov	r15d, eax
	call	VLV_FIFO@PLT
	mov	edi, DWORD PTR SPRITEE[rip]
	mov	esi, r13d
	or	r15d, eax
	call	VLV_FIFO@PLT
	mov	edi, DWORD PTR SPRITEF[rip]
	mov	esi, ebx
	not	r15d
	and	r14d, r15d
	mov	r15d, eax
	sar	ebx, 8
	call	VLV_FIFO@PLT
	mov	edi, DWORD PTR SPRITEE_HI[rip]
	mov	esi, 255
	or	eax, r15d
	or	r14d, eax
	call	VLV_FIFO@PLT
	mov	edi, DWORD PTR SPRITEF_HI[rip]
	mov	esi, 255
	mov	r15d, eax
	call	VLV_FIFO@PLT
	mov	edi, DWORD PTR SPRITEE_HI[rip]
	mov	esi, r13d
	sar	esi, 8
	or	r15d, eax
	call	VLV_FIFO@PLT
	mov	edi, DWORD PTR SPRITEF_HI[rip]
	mov	esi, ebx
	not	r15d
	mov	r13d, eax
	and	r12d, r15d
	call	VLV_FIFO@PLT
	mov	esi, DWORD PTR DSPARB3[rip]
	mov	edx, r14d
	mov	rdi, rbp
	or	r13d, eax
	call	intel_uncore_write_fw@PLT
	or	r12d, r13d
	mov	esi, DWORD PTR DSPARB2[rip]
	mov	rdi, rbp
	mov	edx, r12d
	call	intel_uncore_write_fw@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L4:
	mov	esi, DWORD PTR DSPARB[rip]
	mov	rdi, rbp
	call	intel_uncore_read_fw@PLT
	mov	esi, DWORD PTR DSPARB2[rip]
	mov	rdi, rbp
	mov	r12d, eax
	call	intel_uncore_read_fw@PLT
	mov	edi, DWORD PTR SPRITEA[rip]
	mov	esi, 255
	mov	r15d, eax
	call	VLV_FIFO@PLT
	mov	edi, DWORD PTR SPRITEB[rip]
	mov	esi, 255
	mov	r14d, eax
	call	VLV_FIFO@PLT
	mov	edi, DWORD PTR SPRITEA[rip]
	mov	esi, r13d
	or	r14d, eax
	call	VLV_FIFO@PLT
	mov	edi, DWORD PTR SPRITEB[rip]
	mov	esi, ebx
	not	r14d
	and	r14d, r12d
	mov	r12d, eax
	sar	ebx, 8
	call	VLV_FIFO@PLT
	mov	edi, DWORD PTR SPRITEA_HI[rip]
	mov	esi, 1
	or	r12d, eax
	call	VLV_FIFO@PLT
	mov	edi, DWORD PTR SPRITEB_HI[rip]
	mov	esi, 1
	or	r14d, r12d
	mov	r12d, eax
	call	VLV_FIFO@PLT
	mov	edi, DWORD PTR SPRITEA_HI[rip]
	mov	esi, r13d
	or	r12d, eax
	sar	esi, 8
	call	VLV_FIFO@PLT
	not	r12d
	mov	edi, DWORD PTR SPRITEB_HI[rip]
	mov	esi, ebx
	and	r15d, r12d
	mov	r12d, eax
	jmp	.L8
	.cfi_endproc
.LFE0:
	.size	vlv_atomic_update_fifo, .-vlv_atomic_update_fifo
	.comm	SPRITEF_HI,4,4
	.comm	SPRITEF,4,4
	.comm	SPRITEE_HI,4,4
	.comm	SPRITEE,4,4
	.comm	SPRITED_HI,4,4
	.comm	SPRITED,4,4
	.comm	SPRITEC_HI,4,4
	.comm	SPRITEC,4,4
	.comm	SPRITEB_HI,4,4
	.comm	SPRITEB,4,4
	.comm	SPRITEA_HI,4,4
	.comm	SPRITEA,4,4
	.comm	PLANE_SPRITE1,8,8
	.comm	PLANE_SPRITE0,8,8
	.comm	PLANE_PRIMARY,8,8
	.comm	PLANE_CURSOR,8,8
	.comm	DSPARB3,4,4
	.comm	DSPARB2,4,4
	.comm	DSPARB,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_intel_pm.c_vlv_atomic_update_fifo.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	vlv_atomic_update_fifo, %function
vlv_atomic_update_fifo:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r0, [r1, #8]
	sub	sp, sp, #12
	mov	r5, r1
	bl	to_intel_crtc
	mov	r6, r0
	ldr	r0, [r0, #4]
	bl	to_i915
	ldr	r3, [r5]
	cmp	r3, #0
	bne	.L11
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L11:
	mov	r4, r0
	ldr	r1, .L12
	ldr	r0, .L12+4
	ldr	r3, [r5, #4]
	ldr	r1, [r1]
	ldr	r0, [r0]
	ldr	ip, .L12+8
	ldr	r2, .L12+12
	ldr	ip, [ip]
	ldr	r5, [r3, r0, lsl #2]
	ldr	r0, [r3, r1, lsl #2]
	ldr	r2, [r2]
	ldr	r8, [r3, ip, lsl #2]
	subs	r0, r0, #63
	ldr	r7, [r3, r2, lsl #2]
	movne	r0, #1
	bl	WARN_ON
	add	r5, r8, r5
	ldr	r0, .L12+16
	add	r7, r5, r7
	subs	r0, r7, r0
	movne	r0, #1
	bl	WARN_ON
	mov	r3, r7
	mov	r2, r5
	mov	r1, r8
	mov	r0, r6
	bl	trace_vlv_fifo_size
	mov	r0, r4
	bl	spin_lock
	ldr	r3, [r6]
	cmp	r3, #129
	beq	.L3
	cmp	r3, #130
	beq	.L4
	cmp	r3, #128
	beq	.L5
.L8:
	ldr	r6, .L12+20
.L6:
	mov	r0, r4
	ldr	r1, [r6]
	bl	intel_uncore_posting_read_fw
	mov	r0, r4
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	b	spin_unlock
.L3:
	ldr	r6, .L12+20
	mov	r0, r4
	ldr	r1, [r6]
	bl	intel_uncore_read_fw
	ldr	r7, .L12+24
	mov	r9, r0
	ldr	r1, [r7]
	mov	r0, r4
	bl	intel_uncore_read_fw
	mov	r3, r0
	ldr	r10, .L12+28
	mov	r1, #255
	ldr	r0, [r10]
	str	r3, [sp, #4]
	bl	VLV_FIFO
	ldr	r2, .L12+32
	mov	fp, r0
	mov	r1, #255
	ldr	r0, [r2]
	bl	VLV_FIFO
	mov	r1, r8
	orr	fp, fp, r0
	ldr	r0, [r10]
	bl	VLV_FIFO
	ldr	r2, .L12+32
	bic	fp, r9, fp
	mov	r1, r5
	mov	r9, r0
	ldr	r0, [r2]
	bl	VLV_FIFO
	ldr	r2, .L12+36
	mov	r1, #255
	orr	r9, r9, r0
	ldr	r0, [r2]
	bl	VLV_FIFO
	orr	r9, r9, fp
	ldr	fp, .L12+40
	mov	r10, r0
	mov	r1, #255
	ldr	r0, [fp]
	bl	VLV_FIFO
	ldr	r2, .L12+36
	asr	r1, r8, #8
	orr	r8, r10, r0
.L9:
	ldr	r3, [sp, #4]
	ldr	r0, [r2]
	bic	r8, r3, r8
	bl	VLV_FIFO
	mov	r3, r0
	asr	r1, r5, #8
	ldr	r0, [fp]
	mov	r5, r3
	bl	VLV_FIFO
	orr	r5, r5, r0
	mov	r2, r9
	ldr	r1, [r6]
	mov	r0, r4
	orr	r5, r5, r8
	bl	intel_uncore_write_fw
	mov	r2, r5
	mov	r0, r4
	ldr	r1, [r7]
	bl	intel_uncore_write_fw
	b	.L6
.L5:
	ldr	r7, .L12+44
	mov	r0, r4
	ldr	r1, [r7]
	bl	intel_uncore_read_fw
	ldr	r6, .L12+24
	mov	r9, r0
	ldr	r1, [r6]
	mov	r0, r4
	bl	intel_uncore_read_fw
	mov	r3, r0
	ldr	r10, .L12+48
	mov	r1, #255
	ldr	r0, [r10]
	str	r3, [sp, #4]
	bl	VLV_FIFO
	ldr	r2, .L12+52
	mov	fp, r0
	mov	r1, #255
	ldr	r0, [r2]
	bl	VLV_FIFO
	mov	r1, r8
	orr	fp, fp, r0
	ldr	r0, [r10]
	bl	VLV_FIFO
	ldr	r2, .L12+52
	mov	r1, r5
	bic	fp, r9, fp
	mov	r9, r0
	ldr	r0, [r2]
	bl	VLV_FIFO
	ldr	r2, .L12+56
	mov	r1, #255
	orr	r9, r9, r0
	ldr	r0, [r2]
	bl	VLV_FIFO
	orr	r9, r9, fp
	ldr	fp, .L12+60
	mov	r10, r0
	mov	r1, #255
	ldr	r0, [fp]
	bl	VLV_FIFO
	ldr	r2, .L12+56
	ldr	r3, [sp, #4]
	asr	r1, r8, #8
	orr	r8, r10, r0
	ldr	r0, [r2]
	bic	r8, r3, r8
	bl	VLV_FIFO
	mov	r3, r0
	asr	r1, r5, #8
	ldr	r0, [fp]
	mov	r5, r3
	bl	VLV_FIFO
	orr	r5, r5, r0
	mov	r2, r9
	ldr	r1, [r7]
	mov	r0, r4
	orr	r5, r5, r8
	bl	intel_uncore_write_fw
	mov	r2, r5
	mov	r0, r4
	ldr	r1, [r6]
	bl	intel_uncore_write_fw
	b	.L8
.L4:
	ldr	r6, .L12+20
	mov	r0, r4
	ldr	r1, [r6]
	bl	intel_uncore_read_fw
	ldr	r7, .L12+24
	mov	r9, r0
	ldr	r1, [r7]
	mov	r0, r4
	bl	intel_uncore_read_fw
	mov	r3, r0
	ldr	r10, .L12+64
	mov	r1, #255
	ldr	r0, [r10]
	str	r3, [sp, #4]
	bl	VLV_FIFO
	ldr	r2, .L12+68
	mov	fp, r0
	mov	r1, #255
	ldr	r0, [r2]
	bl	VLV_FIFO
	mov	r1, r8
	orr	fp, fp, r0
	ldr	r0, [r10]
	bl	VLV_FIFO
	ldr	r2, .L12+68
	bic	fp, r9, fp
	mov	r1, r5
	mov	r9, r0
	ldr	r0, [r2]
	bl	VLV_FIFO
	ldr	r2, .L12+72
	mov	r1, #1
	orr	r9, r9, r0
	ldr	r0, [r2]
	bl	VLV_FIFO
	orr	r9, r9, fp
	ldr	fp, .L12+76
	mov	r10, r0
	mov	r1, #1
	ldr	r0, [fp]
	bl	VLV_FIFO
	asr	r1, r8, #8
	ldr	r2, .L12+72
	orr	r8, r10, r0
	b	.L9
.L13:
	.align	2
.L12:
	.word	PLANE_CURSOR
	.word	PLANE_SPRITE0
	.word	PLANE_PRIMARY
	.word	PLANE_SPRITE1
	.word	511
	.word	DSPARB
	.word	DSPARB2
	.word	SPRITEC
	.word	SPRITED
	.word	SPRITEC_HI
	.word	SPRITED_HI
	.word	DSPARB3
	.word	SPRITEE
	.word	SPRITEF
	.word	SPRITEE_HI
	.word	SPRITEF_HI
	.word	SPRITEA
	.word	SPRITEB
	.word	SPRITEA_HI
	.word	SPRITEB_HI
	.size	vlv_atomic_update_fifo, .-vlv_atomic_update_fifo
	.comm	SPRITEF_HI,4,4
	.comm	SPRITEF,4,4
	.comm	SPRITEE_HI,4,4
	.comm	SPRITEE,4,4
	.comm	SPRITED_HI,4,4
	.comm	SPRITED,4,4
	.comm	SPRITEC_HI,4,4
	.comm	SPRITEC,4,4
	.comm	SPRITEB_HI,4,4
	.comm	SPRITEB,4,4
	.comm	SPRITEA_HI,4,4
	.comm	SPRITEA,4,4
	.comm	PLANE_SPRITE1,4,4
	.comm	PLANE_SPRITE0,4,4
	.comm	PLANE_PRIMARY,4,4
	.comm	PLANE_CURSOR,4,4
	.comm	DSPARB3,4,4
	.comm	DSPARB2,4,4
	.comm	DSPARB,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
