	.file	"extr_intel_ddi.c_icl_combo_phy_ddi_vswing_sequence.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	icl_combo_phy_ddi_vswing_sequence, @function
icl_combo_phy_ddi_vswing_sequence:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	mov	r14, rdi
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	mov	r12d, edx
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 40
	.cfi_def_cfa_offset 96
	mov	edi, DWORD PTR [rdi]
	mov	DWORD PTR 24[rsp], esi
	call	to_i915@PLT
	mov	esi, DWORD PTR 4[r14]
	mov	rdi, rax
	mov	QWORD PTR 16[rsp], rax
	call	intel_port_to_phy@PLT
	cmp	DWORD PTR INTEL_OUTPUT_HDMI[rip], r12d
	mov	ebp, eax
	jne	.L22
	mov	BYTE PTR 11[rsp], 1
	mov	ebx, 1
	mov	DWORD PTR 28[rsp], 0
	mov	DWORD PTR 12[rsp], 4
.L2:
	mov	edi, ebp
	call	ICL_PORT_PCS_DW1_LN0@PLT
	mov	edi, eax
	call	I915_READ@PLT
	mov	r14d, DWORD PTR COMMON_KEEPER_EN[rip]
	or	r14d, eax
	cmp	DWORD PTR INTEL_OUTPUT_HDMI[rip], r12d
	jne	.L4
	mov	esi, DWORD PTR COMMON_KEEPER_EN[rip]
	not	esi
	and	esi, eax
	mov	r14d, esi
.L4:
	mov	edi, ebp
	call	ICL_PORT_PCS_DW1_GRP@PLT
	mov	esi, r14d
	xor	r14d, r14d
	mov	edi, eax
	call	I915_WRITE@PLT
.L10:
	mov	esi, ebp
	mov	edi, r14d
	lea	r13d, 1[r14]
	call	ICL_PORT_TX_DW4_LN@PLT
	mov	edi, eax
	call	I915_READ@PLT
	mov	ecx, DWORD PTR LOADGEN_SELECT[rip]
	mov	r9d, ecx
	not	r9d
	mov	r15d, r9d
	and	r15d, eax
	test	bl, bl
	je	.L5
	test	r14d, r14d
	je	.L23
.L6:
	or	ecx, eax
	mov	r15d, ecx
.L8:
	mov	esi, ebp
	mov	edi, r14d
	call	ICL_PORT_TX_DW4_LN@PLT
	mov	esi, r15d
	mov	edi, eax
	call	I915_WRITE@PLT
	cmp	r13d, 4
	je	.L9
.L11:
	mov	r14d, r13d
	jmp	.L10
	.p2align 4,,10
	.p2align 3
.L5:
	cmp	DWORD PTR 12[rsp], 3
	jg	.L8
	cmp	BYTE PTR 11[rsp], 0
	je	.L8
	lea	esi, -1[r14]
	cmp	esi, 1
	ja	.L8
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L9:
	mov	edi, ebp
	call	ICL_PORT_CL_DW5@PLT
	mov	edi, eax
	call	I915_READ@PLT
	mov	edi, ebp
	or	eax, DWORD PTR SUS_CLOCK_CONFIG[rip]
	mov	r14d, eax
	call	ICL_PORT_CL_DW5@PLT
	mov	esi, r14d
	mov	edi, eax
	call	I915_WRITE@PLT
	mov	edi, ebp
	call	ICL_PORT_TX_DW5_LN0@PLT
	mov	edi, eax
	call	I915_READ@PLT
	mov	r14d, DWORD PTR TX_TRAINING_EN[rip]
	mov	edi, ebp
	not	r14d
	and	r14d, eax
	call	ICL_PORT_TX_DW5_GRP@PLT
	mov	esi, r14d
	mov	edi, eax
	call	I915_WRITE@PLT
	mov	esi, DWORD PTR 24[rsp]
	mov	r8d, DWORD PTR 28[rsp]
	mov	edx, ebp
	mov	rdi, QWORD PTR 16[rsp]
	mov	ecx, r12d
	call	icl_ddi_combo_vswing_program@PLT
	mov	edi, ebp
	call	ICL_PORT_TX_DW5_LN0@PLT
	mov	edi, eax
	call	I915_READ@PLT
	mov	edi, ebp
	or	eax, DWORD PTR TX_TRAINING_EN[rip]
	mov	r12d, eax
	call	ICL_PORT_TX_DW5_GRP@PLT
	add	rsp, 40
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	esi, r12d
	pop	rbx
	.cfi_def_cfa_offset 48
	mov	edi, eax
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	jmp	I915_WRITE@PLT
	.p2align 4,,10
	.p2align 3
.L23:
	.cfi_restore_state
	mov	esi, ebp
	xor	edi, edi
	call	ICL_PORT_TX_DW4_LN@PLT
	mov	esi, r15d
	mov	edi, eax
	call	I915_WRITE@PLT
	jmp	.L11
	.p2align 4,,10
	.p2align 3
.L22:
	mov	rdi, r14
	call	enc_to_intel_dp@PLT
	mov	ebx, DWORD PTR [rax]
	mov	eax, DWORD PTR 4[rax]
	cmp	eax, 600000
	mov	DWORD PTR 28[rsp], eax
	setle	BYTE PTR 11[rsp]
	cmp	ebx, 4
	movzx	eax, BYTE PTR 11[rsp]
	mov	DWORD PTR 12[rsp], ebx
	sete	bl
	and	ebx, eax
	jmp	.L2
	.cfi_endproc
.LFE0:
	.size	icl_combo_phy_ddi_vswing_sequence, .-icl_combo_phy_ddi_vswing_sequence
	.comm	TX_TRAINING_EN,4,4
	.comm	SUS_CLOCK_CONFIG,4,4
	.comm	LOADGEN_SELECT,4,4
	.comm	INTEL_OUTPUT_HDMI,4,4
	.comm	COMMON_KEEPER_EN,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_intel_ddi.c_icl_combo_phy_ddi_vswing_sequence.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	icl_combo_phy_ddi_vswing_sequence, %function
icl_combo_phy_ddi_vswing_sequence:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	mov	r5, r0
	sub	sp, sp, #28
	ldr	r0, [r0]
	mov	r6, r2
	str	r1, [sp, #16]
	bl	to_i915
	ldr	r1, [r5, #4]
	str	r0, [sp, #12]
	bl	intel_port_to_phy
	ldr	r8, .L21
	mov	r4, r0
	ldr	r3, [r8]
	cmp	r3, r6
	bne	.L19
	mov	r3, #0
	mov	r7, #1
	str	r3, [sp, #20]
	mov	r3, #4
	mov	r9, r7
	str	r3, [sp, #8]
.L2:
	mov	r0, r4
	bl	ICL_PORT_PCS_DW1_LN0
	bl	I915_READ
	ldr	r3, [r8]
	ldr	r8, .L21+4
	cmp	r3, r6
	ldr	r3, .L21+8
	ldr	r5, [r3]
	biceq	r5, r0, r5
	orrne	r5, r0, r5
	mov	r0, r4
	bl	ICL_PORT_PCS_DW1_GRP
	mov	r1, r5
	bl	I915_WRITE
	mov	r5, #0
.L10:
	mov	r1, r4
	mov	r0, r5
	bl	ICL_PORT_TX_DW4_LN
	bl	I915_READ
	ldr	r2, [r8]
	cmp	r7, #0
	bic	r10, r0, r2
	add	fp, r5, #1
	beq	.L5
	cmp	r5, #0
	beq	.L20
.L6:
	orr	r10, r2, r0
.L8:
	mov	r1, r4
	mov	r0, r5
	bl	ICL_PORT_TX_DW4_LN
	mov	r1, r10
	bl	I915_WRITE
	cmp	fp, #4
	beq	.L9
.L11:
	mov	r5, fp
	b	.L10
.L5:
	ldr	r3, [sp, #8]
	sub	ip, r5, #1
	cmp	r3, #3
	movgt	r1, #0
	andle	r1, r9, #1
	cmp	r1, #0
	beq	.L8
	cmp	ip, #1
	bhi	.L8
	b	.L6
.L9:
	mov	r0, r4
	bl	ICL_PORT_CL_DW5
	bl	I915_READ
	mov	r5, r0
	ldr	r3, .L21+12
	mov	r0, r4
	ldr	r1, [r3]
	ldr	r7, .L21+16
	orr	r5, r5, r1
	bl	ICL_PORT_CL_DW5
	mov	r1, r5
	bl	I915_WRITE
	mov	r0, r4
	bl	ICL_PORT_TX_DW5_LN0
	bl	I915_READ
	mov	r5, r0
	ldr	r1, [r7]
	mov	r0, r4
	bic	r5, r5, r1
	bl	ICL_PORT_TX_DW5_GRP
	mov	r1, r5
	bl	I915_WRITE
	ldr	r3, [sp, #20]
	mov	r2, r4
	ldr	r1, [sp, #16]
	str	r3, [sp]
	ldr	r0, [sp, #12]
	mov	r3, r6
	bl	icl_ddi_combo_vswing_program
	mov	r0, r4
	bl	ICL_PORT_TX_DW5_LN0
	bl	I915_READ
	mov	r1, r0
	ldr	r3, [r7]
	mov	r0, r4
	orr	r4, r1, r3
	bl	ICL_PORT_TX_DW5_GRP
	mov	r1, r4
	add	sp, sp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	b	I915_WRITE
.L20:
	mov	r1, r4
	mov	r0, r5
	bl	ICL_PORT_TX_DW4_LN
	mov	r1, r10
	bl	I915_WRITE
	b	.L11
.L19:
	mov	r0, r5
	bl	enc_to_intel_dp
	ldr	r9, .L21+20
	ldr	r3, [r0, #4]
	ldr	r2, [r0]
	cmp	r3, r9
	movgt	r9, #0
	movle	r9, #1
	str	r3, [sp, #20]
	cmp	r2, #4
	movne	r7, #0
	andeq	r7, r9, #1
	str	r2, [sp, #8]
	b	.L2
.L22:
	.align	2
.L21:
	.word	INTEL_OUTPUT_HDMI
	.word	LOADGEN_SELECT
	.word	COMMON_KEEPER_EN
	.word	SUS_CLOCK_CONFIG
	.word	TX_TRAINING_EN
	.word	600000
	.size	icl_combo_phy_ddi_vswing_sequence, .-icl_combo_phy_ddi_vswing_sequence
	.comm	TX_TRAINING_EN,4,4
	.comm	SUS_CLOCK_CONFIG,4,4
	.comm	LOADGEN_SELECT,4,4
	.comm	INTEL_OUTPUT_HDMI,4,4
	.comm	COMMON_KEEPER_EN,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
