	.file	"extr_amba-pl022.c_pl022_interrupt_handler.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC0:
	.string	"bad message state in interrupt handler"
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"FIFO overrun\n"
.LC2:
	.string	"RXFIFO is full\n"
.LC3:
	.string	"TXFIFO is full\n"
	.section	.rodata.str1.8
	.align 8
.LC4:
	.string	"read %u surplus bytes (did you request an odd number of bytes on a 16bit bus?)\n"
	.text
	.p2align 4
	.type	pl022_interrupt_handler, @function
pl022_interrupt_handler:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	xor	edi, edi
	push	rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	push	rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	mov	r12, QWORD PTR 72[rsi]
	mov	rbx, rsi
	test	r12, r12
	sete	dil
	call	unlikely@PLT
	test	rax, rax
	jne	.L23
	mov	edi, DWORD PTR 64[rbx]
	call	SSP_MIS@PLT
	mov	edi, eax
	call	readw@PLT
	xor	edi, edi
	test	eax, eax
	mov	ebp, eax
	sete	dil
	call	unlikely@PLT
	test	rax, rax
	je	.L4
	mov	eax, DWORD PTR IRQ_NONE[rip]
.L1:
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L4:
	.cfi_restore_state
	mov	edi, DWORD PTR SSP_MIS_MASK_RORMIS[rip]
	and	edi, ebp
	call	unlikely@PLT
	test	rax, rax
	jne	.L24
	mov	rdi, rbx
	call	readwriter@PLT
	mov	rax, QWORD PTR 8[rbx]
	cmp	QWORD PTR [rbx], rax
	je	.L25
.L8:
	mov	eax, DWORD PTR IRQ_HANDLED[rip]
	mov	rcx, QWORD PTR 24[rbx]
	cmp	QWORD PTR 16[rbx], rcx
	jl	.L1
	mov	edi, DWORD PTR 64[rbx]
	call	SSP_IMSC@PLT
	mov	edi, DWORD PTR DISABLE_ALL_INTERRUPTS[rip]
	mov	esi, eax
	call	writew@PLT
	mov	edi, DWORD PTR 64[rbx]
	call	SSP_ICR@PLT
	mov	edi, DWORD PTR CLEAR_ALL_INTERRUPTS[rip]
	mov	esi, eax
	call	writew@PLT
	xor	edi, edi
	mov	rax, QWORD PTR 24[rbx]
	cmp	QWORD PTR 16[rbx], rax
	setg	dil
	call	unlikely@PLT
	test	rax, rax
	jne	.L26
.L10:
	mov	rax, QWORD PTR 48[rbx]
	mov	rdx, QWORD PTR 8[rax]
	add	DWORD PTR 4[r12], edx
	cmp	QWORD PTR [rax], 0
	je	.L11
	mov	rax, QWORD PTR 40[rbx]
	mov	edi, DWORD PTR SSP_CHIP_DESELECT[rip]
	call	[QWORD PTR [rax]]
.L11:
	mov	rdi, rbx
	call	next_transfer@PLT
	lea	rdi, 32[rbx]
	mov	DWORD PTR [r12], eax
	call	tasklet_schedule@PLT
	mov	eax, DWORD PTR IRQ_HANDLED[rip]
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L23:
	mov	rdi, QWORD PTR 56[rbx]
	lea	rsi, .LC0[rip]
	call	dev_err@PLT
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	mov	eax, DWORD PTR IRQ_HANDLED[rip]
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L24:
	.cfi_restore_state
	mov	rdi, QWORD PTR 56[rbx]
	lea	rsi, .LC1[rip]
	call	dev_err@PLT
	mov	edi, DWORD PTR 64[rbx]
	call	SSP_SR@PLT
	mov	edi, eax
	call	readw@PLT
	test	DWORD PTR SSP_SR_MASK_RFF[rip], eax
	jne	.L27
.L6:
	mov	edi, DWORD PTR 64[rbx]
	call	SSP_SR@PLT
	mov	edi, eax
	call	readw@PLT
	test	DWORD PTR SSP_SR_MASK_TNF[rip], eax
	jne	.L28
.L7:
	mov	edi, DWORD PTR 64[rbx]
	call	SSP_IMSC@PLT
	mov	edi, DWORD PTR DISABLE_ALL_INTERRUPTS[rip]
	mov	esi, eax
	call	writew@PLT
	mov	edi, DWORD PTR 64[rbx]
	call	SSP_ICR@PLT
	mov	edi, DWORD PTR CLEAR_ALL_INTERRUPTS[rip]
	mov	esi, eax
	call	writew@PLT
	mov	edi, DWORD PTR 64[rbx]
	call	SSP_CR1@PLT
	mov	edi, DWORD PTR 64[rbx]
	mov	ebp, eax
	call	SSP_CR1@PLT
	mov	edi, eax
	call	readw@PLT
	mov	edi, DWORD PTR SSP_CR1_MASK_SSE[rip]
	mov	esi, ebp
	not	edi
	and	edi, eax
	call	writew@PLT
	mov	eax, DWORD PTR STATE_ERROR[rip]
	lea	rdi, 32[rbx]
	mov	DWORD PTR [r12], eax
	call	tasklet_schedule@PLT
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	mov	eax, DWORD PTR IRQ_HANDLED[rip]
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L25:
	.cfi_restore_state
	mov	edi, DWORD PTR 64[rbx]
	call	SSP_IMSC@PLT
	mov	edi, DWORD PTR 64[rbx]
	mov	ebp, eax
	call	SSP_IMSC@PLT
	mov	edi, eax
	call	readw@PLT
	mov	edi, DWORD PTR SSP_IMSC_MASK_TXIM[rip]
	mov	esi, ebp
	not	edi
	and	edi, eax
	call	writew@PLT
	jmp	.L8
	.p2align 4,,10
	.p2align 3
.L27:
	mov	rdi, QWORD PTR 56[rbx]
	lea	rsi, .LC2[rip]
	call	dev_err@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L28:
	mov	rdi, QWORD PTR 56[rbx]
	lea	rsi, .LC3[rip]
	call	dev_err@PLT
	jmp	.L7
	.p2align 4,,10
	.p2align 3
.L26:
	mov	rdi, QWORD PTR 56[rbx]
	mov	rdx, QWORD PTR 16[rbx]
	lea	rsi, .LC4[rip]
	sub	edx, DWORD PTR 24[rbx]
	call	dev_warn@PLT
	jmp	.L10
	.cfi_endproc
.LFE0:
	.size	pl022_interrupt_handler, .-pl022_interrupt_handler
	.comm	STATE_ERROR,4,4
	.comm	SSP_SR_MASK_TNF,4,4
	.comm	SSP_SR_MASK_RFF,4,4
	.comm	SSP_MIS_MASK_RORMIS,4,4
	.comm	SSP_IMSC_MASK_TXIM,4,4
	.comm	SSP_CR1_MASK_SSE,4,4
	.comm	SSP_CHIP_DESELECT,4,4
	.comm	IRQ_NONE,4,4
	.comm	IRQ_HANDLED,4,4
	.comm	DISABLE_ALL_INTERRUPTS,4,4
	.comm	CLEAR_ALL_INTERRUPTS,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_amba-pl022.c_pl022_interrupt_handler.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"bad message state in interrupt handler\000"
	.align	2
.LC1:
	.ascii	"FIFO overrun\012\000"
	.align	2
.LC2:
	.ascii	"RXFIFO is full\012\000"
	.align	2
.LC3:
	.ascii	"TXFIFO is full\012\000"
	.align	2
.LC4:
	.ascii	"read %u surplus bytes (did you request an odd numbe"
	.ascii	"r of bytes on a 16bit bus?)\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	pl022_interrupt_handler, %function
pl022_interrupt_handler:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, lr}
	ldr	r6, [r1, #36]
	mov	r4, r1
	clz	r0, r6
	lsr	r0, r0, #5
	bl	unlikely
	cmp	r0, #0
	bne	.L26
	ldr	r0, [r4, #32]
	bl	SSP_MIS
	bl	readw
	mov	r5, r0
	clz	r0, r0
	lsr	r0, r0, #5
	bl	unlikely
	cmp	r0, #0
	beq	.L4
	ldr	r3, .L33
	ldr	r0, [r3]
	pop	{r4, r5, r6, pc}
.L4:
	ldr	r3, .L33+4
	ldr	r0, [r3]
	and	r0, r0, r5
	bl	unlikely
	cmp	r0, #0
	bne	.L27
	mov	r0, r4
	bl	readwriter
	ldm	r4, {r2, r3}
	cmp	r2, r3
	beq	.L28
.L8:
	ldr	r2, [r4, #8]
	ldr	r3, [r4, #12]
	cmp	r2, r3
	bge	.L29
	ldr	r3, .L33+8
	ldr	r0, [r3]
	pop	{r4, r5, r6, pc}
.L26:
	ldr	r0, [r4, #28]
	ldr	r1, .L33+12
	bl	dev_err
	ldr	r3, .L33+8
	ldr	r0, [r3]
	pop	{r4, r5, r6, pc}
.L27:
	ldr	r1, .L33+16
	ldr	r0, [r4, #28]
	bl	dev_err
	ldr	r0, [r4, #32]
	bl	SSP_SR
	bl	readw
	ldr	r3, .L33+20
	ldr	r3, [r3]
	tst	r0, r3
	bne	.L30
.L6:
	ldr	r0, [r4, #32]
	bl	SSP_SR
	bl	readw
	ldr	r3, .L33+24
	ldr	r3, [r3]
	tst	r0, r3
	bne	.L31
.L7:
	ldr	r3, .L33+28
	ldr	r0, [r4, #32]
	ldr	r5, [r3]
	bl	SSP_IMSC
	mov	r1, r0
	mov	r0, r5
	bl	writew
	ldr	r3, .L33+32
	ldr	r0, [r4, #32]
	ldr	r5, [r3]
	bl	SSP_ICR
	mov	r1, r0
	mov	r0, r5
	bl	writew
	ldr	r0, [r4, #32]
	bl	SSP_CR1
	bl	readw
	mov	r5, r0
	ldr	r3, .L33+36
	ldr	r0, [r4, #32]
	ldr	r3, [r3]
	bic	r5, r5, r3
	bl	SSP_CR1
	mov	r1, r0
	mov	r0, r5
	bl	writew
	ldr	r3, .L33+40
	add	r0, r4, #16
	ldr	r3, [r3]
	str	r3, [r6]
	bl	tasklet_schedule
	ldr	r3, .L33+8
	ldr	r0, [r3]
	pop	{r4, r5, r6, pc}
.L29:
	ldr	r3, .L33+28
	ldr	r0, [r4, #32]
	ldr	r5, [r3]
	bl	SSP_IMSC
	mov	r1, r0
	mov	r0, r5
	bl	writew
	ldr	r3, .L33+32
	ldr	r0, [r4, #32]
	ldr	r5, [r3]
	bl	SSP_ICR
	mov	r1, r0
	mov	r0, r5
	bl	writew
	ldr	r0, [r4, #8]
	ldr	r3, [r4, #12]
	cmp	r0, r3
	movle	r0, #0
	movgt	r0, #1
	bl	unlikely
	cmp	r0, #0
	bne	.L32
.L10:
	ldr	r2, [r4, #24]
	ldr	r3, [r6, #4]
	ldr	r1, [r2, #4]
	ldr	r2, [r2]
	add	r3, r3, r1
	cmp	r2, #0
	str	r3, [r6, #4]
	beq	.L11
	ldr	r2, .L33+44
	ldr	r3, [r4, #20]
	ldr	r0, [r2]
	ldr	r3, [r3]
	blx	r3
.L11:
	mov	r0, r4
	bl	next_transfer
	mov	r3, r0
	add	r0, r4, #16
	str	r3, [r6]
	bl	tasklet_schedule
	ldr	r3, .L33+8
	ldr	r0, [r3]
	pop	{r4, r5, r6, pc}
.L28:
	ldr	r0, [r4, #32]
	bl	SSP_IMSC
	bl	readw
	mov	r5, r0
	ldr	r3, .L33+48
	ldr	r0, [r4, #32]
	ldr	r3, [r3]
	bic	r5, r5, r3
	bl	SSP_IMSC
	mov	r1, r0
	mov	r0, r5
	bl	writew
	b	.L8
.L30:
	ldr	r1, .L33+52
	ldr	r0, [r4, #28]
	bl	dev_err
	b	.L6
.L31:
	ldr	r1, .L33+56
	ldr	r0, [r4, #28]
	bl	dev_err
	b	.L7
.L32:
	ldr	r2, [r4, #8]
	ldr	r3, [r4, #12]
	ldr	r1, .L33+60
	ldr	r0, [r4, #28]
	sub	r2, r2, r3
	bl	dev_warn
	b	.L10
.L34:
	.align	2
.L33:
	.word	IRQ_NONE
	.word	SSP_MIS_MASK_RORMIS
	.word	IRQ_HANDLED
	.word	.LC0
	.word	.LC1
	.word	SSP_SR_MASK_RFF
	.word	SSP_SR_MASK_TNF
	.word	DISABLE_ALL_INTERRUPTS
	.word	CLEAR_ALL_INTERRUPTS
	.word	SSP_CR1_MASK_SSE
	.word	STATE_ERROR
	.word	SSP_CHIP_DESELECT
	.word	SSP_IMSC_MASK_TXIM
	.word	.LC2
	.word	.LC3
	.word	.LC4
	.size	pl022_interrupt_handler, .-pl022_interrupt_handler
	.comm	STATE_ERROR,4,4
	.comm	SSP_SR_MASK_TNF,4,4
	.comm	SSP_SR_MASK_RFF,4,4
	.comm	SSP_MIS_MASK_RORMIS,4,4
	.comm	SSP_IMSC_MASK_TXIM,4,4
	.comm	SSP_CR1_MASK_SSE,4,4
	.comm	SSP_CHIP_DESELECT,4,4
	.comm	IRQ_NONE,4,4
	.comm	IRQ_HANDLED,4,4
	.comm	DISABLE_ALL_INTERRUPTS,4,4
	.comm	CLEAR_ALL_INTERRUPTS,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
