	.file	"extr_mach64_accel.c_aty_init_engine.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	aty_init_engine
	.type	aty_init_engine, @function
aty_init_engine:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	sub	rsp, 8
	.cfi_def_cfa_offset 48
	mov	edi, DWORD PTR [rsi]
	mov	eax, DWORD PTR 8[rsi]
	mov	ebx, DWORD PTR 4[rsi]
	test	edi, edi
	lea	ecx, 7[rdi]
	cmovns	ecx, edi
	cdq
	sar	ecx, 3
	idiv	ecx
	mov	r13d, eax
	cmp	edi, 24
	jne	.L2
	lea	r13d, [rax+rax*2]
	lea	ebx, [rbx+rbx*2]
.L2:
	mov	edi, DWORD PTR RESET_3D[rip]
	call	M64_HAS@PLT
	test	rax, rax
	jne	.L9
.L3:
	mov	rdi, rbp
	lea	r12d, 7[r13]
	call	aty_reset_engine@PLT
	mov	edi, DWORD PTR MEM_VGA_WP_SEL[rip]
	mov	rdx, rbp
	mov	esi, 65536
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR MEM_VGA_RP_SEL[rip]
	mov	rdx, rbp
	mov	esi, 65536
	call	aty_st_le32@PLT
	mov	rsi, rbp
	mov	edi, 14
	call	wait_for_fifo@PLT
	mov	edi, DWORD PTR CONTEXT_MASK[rip]
	mov	rdx, rbp
	mov	esi, -1
	call	aty_st_le32@PLT
	test	r13d, r13d
	mov	edi, DWORD PTR DST_OFF_PITCH[rip]
	mov	rdx, rbp
	cmovns	r12d, r13d
	sar	r12d, 3
	sal	r12d, 22
	mov	esi, r12d
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR DST_Y_X[rip]
	mov	rdx, rbp
	xor	esi, esi
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR DST_HEIGHT[rip]
	mov	rdx, rbp
	xor	esi, esi
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR DST_BRES_ERR[rip]
	mov	rdx, rbp
	xor	esi, esi
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR DST_BRES_INC[rip]
	mov	rdx, rbp
	xor	esi, esi
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR DST_BRES_DEC[rip]
	mov	rdx, rbp
	xor	esi, esi
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR DST_CNTL[rip]
	mov	rdx, rbp
	mov	esi, DWORD PTR DST_LAST_PEL[rip]
	or	esi, DWORD PTR DST_Y_TOP_TO_BOTTOM[rip]
	or	esi, DWORD PTR DST_X_LEFT_TO_RIGHT[rip]
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR SRC_OFF_PITCH[rip]
	mov	rdx, rbp
	mov	esi, r12d
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR SRC_Y_X[rip]
	mov	rdx, rbp
	xor	esi, esi
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR SRC_HEIGHT1_WIDTH1[rip]
	mov	rdx, rbp
	mov	esi, 1
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR SRC_Y_X_START[rip]
	mov	rdx, rbp
	xor	esi, esi
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR SRC_HEIGHT2_WIDTH2[rip]
	mov	rdx, rbp
	mov	esi, 1
	call	aty_st_le32@PLT
	mov	esi, DWORD PTR SRC_LINE_X_LEFT_TO_RIGHT[rip]
	mov	edi, DWORD PTR SRC_CNTL[rip]
	mov	rdx, rbp
	call	aty_st_le32@PLT
	mov	rsi, rbp
	mov	edi, 13
	call	wait_for_fifo@PLT
	mov	esi, DWORD PTR HOST_BYTE_ALIGN[rip]
	mov	edi, DWORD PTR HOST_CNTL[rip]
	mov	rdx, rbp
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR PAT_REG0[rip]
	mov	rdx, rbp
	xor	esi, esi
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR PAT_REG1[rip]
	mov	rdx, rbp
	xor	esi, esi
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR PAT_CNTL[rip]
	mov	rdx, rbp
	xor	esi, esi
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR SC_LEFT[rip]
	xor	esi, esi
	mov	rdx, rbp
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR SC_TOP[rip]
	mov	rdx, rbp
	xor	esi, esi
	call	aty_st_le32@PLT
	mov	eax, DWORD PTR 0[rbp]
	mov	edi, DWORD PTR SC_BOTTOM[rip]
	mov	rdx, rbp
	lea	esi, -1[rax]
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR SC_RIGHT[rip]
	lea	esi, -1[rbx]
	mov	rdx, rbp
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR DP_BKGD_CLR[rip]
	mov	rdx, rbp
	xor	esi, esi
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR DP_FRGD_CLR[rip]
	mov	rdx, rbp
	mov	esi, -1
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR DP_WRITE_MASK[rip]
	mov	rdx, rbp
	mov	esi, -1
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR DP_MIX[rip]
	mov	rdx, rbp
	mov	esi, DWORD PTR FRGD_MIX_S[rip]
	or	esi, DWORD PTR BKGD_MIX_D[rip]
	call	aty_st_le32@PLT
	mov	esi, DWORD PTR FRGD_SRC_FRGD_CLR[rip]
	mov	edi, DWORD PTR DP_SRC[rip]
	mov	rdx, rbp
	call	aty_st_le32@PLT
	mov	rsi, rbp
	mov	edi, 3
	call	wait_for_fifo@PLT
	mov	edi, DWORD PTR CLR_CMP_CLR[rip]
	mov	rdx, rbp
	xor	esi, esi
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR CLR_CMP_MASK[rip]
	mov	rdx, rbp
	mov	esi, -1
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR CLR_CMP_CNTL[rip]
	mov	rdx, rbp
	xor	esi, esi
	call	aty_st_le32@PLT
	mov	rsi, rbp
	mov	edi, 2
	call	wait_for_fifo@PLT
	mov	esi, DWORD PTR 4[rbp]
	mov	edi, DWORD PTR DP_PIX_WIDTH[rip]
	mov	rdx, rbp
	call	aty_st_le32@PLT
	mov	esi, DWORD PTR 8[rbp]
	mov	edi, DWORD PTR DP_CHAIN_MASK[rip]
	mov	rdx, rbp
	call	aty_st_le32@PLT
	mov	rsi, rbp
	mov	edi, 5
	call	wait_for_fifo@PLT
	mov	edi, DWORD PTR SCALE_3D_CNTL[rip]
	mov	rdx, rbp
	xor	esi, esi
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR Z_CNTL[rip]
	mov	rdx, rbp
	xor	esi, esi
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR CRTC_INT_CNTL[rip]
	mov	rsi, rbp
	call	aty_ld_le32@PLT
	mov	edi, DWORD PTR CRTC_INT_CNTL[rip]
	mov	rdx, rbp
	and	eax, -33
	mov	esi, eax
	call	aty_st_le32@PLT
	mov	edi, DWORD PTR GUI_TRAJ_CNTL[rip]
	mov	rdx, rbp
	mov	esi, 1048611
	call	aty_st_le32@PLT
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	rdi, rbp
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	jmp	wait_for_idle@PLT
	.p2align 4,,10
	.p2align 3
.L9:
	.cfi_restore_state
	mov	rdi, rbp
	call	reset_GTC_3D_engine@PLT
	jmp	.L3
	.cfi_endproc
.LFE0:
	.size	aty_init_engine, .-aty_init_engine
	.comm	Z_CNTL,4,4
	.comm	SRC_Y_X_START,4,4
	.comm	SRC_Y_X,4,4
	.comm	SRC_OFF_PITCH,4,4
	.comm	SRC_LINE_X_LEFT_TO_RIGHT,4,4
	.comm	SRC_HEIGHT2_WIDTH2,4,4
	.comm	SRC_HEIGHT1_WIDTH1,4,4
	.comm	SRC_CNTL,4,4
	.comm	SC_TOP,4,4
	.comm	SC_RIGHT,4,4
	.comm	SC_LEFT,4,4
	.comm	SC_BOTTOM,4,4
	.comm	SCALE_3D_CNTL,4,4
	.comm	RESET_3D,4,4
	.comm	PAT_REG1,4,4
	.comm	PAT_REG0,4,4
	.comm	PAT_CNTL,4,4
	.comm	MEM_VGA_WP_SEL,4,4
	.comm	MEM_VGA_RP_SEL,4,4
	.comm	HOST_CNTL,4,4
	.comm	HOST_BYTE_ALIGN,4,4
	.comm	GUI_TRAJ_CNTL,4,4
	.comm	FRGD_SRC_FRGD_CLR,4,4
	.comm	FRGD_MIX_S,4,4
	.comm	DST_Y_X,4,4
	.comm	DST_Y_TOP_TO_BOTTOM,4,4
	.comm	DST_X_LEFT_TO_RIGHT,4,4
	.comm	DST_OFF_PITCH,4,4
	.comm	DST_LAST_PEL,4,4
	.comm	DST_HEIGHT,4,4
	.comm	DST_CNTL,4,4
	.comm	DST_BRES_INC,4,4
	.comm	DST_BRES_ERR,4,4
	.comm	DST_BRES_DEC,4,4
	.comm	DP_WRITE_MASK,4,4
	.comm	DP_SRC,4,4
	.comm	DP_PIX_WIDTH,4,4
	.comm	DP_MIX,4,4
	.comm	DP_FRGD_CLR,4,4
	.comm	DP_CHAIN_MASK,4,4
	.comm	DP_BKGD_CLR,4,4
	.comm	CRTC_INT_CNTL,4,4
	.comm	CONTEXT_MASK,4,4
	.comm	CLR_CMP_MASK,4,4
	.comm	CLR_CMP_CNTL,4,4
	.comm	CLR_CMP_CLR,4,4
	.comm	BKGD_MIX_D,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_mach64_accel.c_aty_init_engine.c"
	.text
	.global	__aeabi_idiv
	.align	2
	.global	aty_init_engine
	.syntax unified
	.arm
	.fpu softvfp
	.type	aty_init_engine, %function
aty_init_engine:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, lr}
	ldr	r6, [r1]
	mov	r5, r1
	cmp	r6, #0
	add	r1, r6, #7
	movge	r1, r6
	mov	r4, r0
	asr	r1, r1, #3
	ldr	r0, [r5, #8]
	bl	__aeabi_idiv
	ldr	r3, .L10
	cmp	r6, #24
	ldr	r6, [r5, #4]
	mov	r5, r0
	addeq	r5, r0, r0, lsl #1
	ldr	r0, [r3]
	addeq	r6, r6, r6, lsl #1
	bl	M64_HAS
	cmp	r0, #0
	bne	.L9
.L3:
	mov	r0, r4
	bl	aty_reset_engine
	ldr	r3, .L10+4
	mov	r2, r4
	mov	r1, #65536
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+8
	mov	r2, r4
	ldr	r0, [r3]
	mov	r1, #65536
	bl	aty_st_le32
	mov	r1, r4
	mov	r0, #14
	bl	wait_for_fifo
	ldr	r3, .L10+12
	mov	r2, r4
	mvn	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	cmp	r5, #0
	add	r0, r5, #7
	movlt	r5, r0
	ldr	r3, .L10+16
	asr	r5, r5, #3
	lsl	r5, r5, #22
	mov	r1, r5
	mov	r2, r4
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+20
	mov	r2, r4
	mov	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+24
	mov	r2, r4
	mov	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+28
	mov	r2, r4
	mov	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+32
	mov	r2, r4
	mov	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+36
	mov	r2, r4
	mov	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r1, .L10+40
	ldr	r3, .L10+44
	ldr	r2, .L10+48
	ldr	r0, [r1]
	ldr	r3, [r3]
	ldr	r1, [r2]
	ldr	r2, .L10+52
	orr	r3, r3, r0
	orr	r1, r3, r1
	ldr	r0, [r2]
	mov	r2, r4
	bl	aty_st_le32
	ldr	r3, .L10+56
	mov	r1, r5
	mov	r2, r4
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+60
	mov	r2, r4
	mov	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+64
	mov	r2, r4
	mov	r1, #1
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+68
	mov	r2, r4
	mov	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+72
	mov	r2, r4
	mov	r1, #1
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+76
	ldr	r2, .L10+80
	ldr	r0, [r3]
	ldr	r1, [r2]
	mov	r2, r4
	bl	aty_st_le32
	mov	r1, r4
	mov	r0, #13
	bl	wait_for_fifo
	ldr	r3, .L10+84
	ldr	r2, .L10+88
	ldr	r0, [r3]
	ldr	r1, [r2]
	mov	r2, r4
	bl	aty_st_le32
	ldr	r3, .L10+92
	mov	r2, r4
	mov	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+96
	mov	r2, r4
	mov	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+100
	mov	r2, r4
	mov	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+104
	mov	r2, r4
	mov	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+108
	mov	r2, r4
	mov	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r1, [r4]
	ldr	r3, .L10+112
	mov	r2, r4
	ldr	r0, [r3]
	sub	r1, r1, #1
	bl	aty_st_le32
	ldr	r3, .L10+116
	mov	r2, r4
	sub	r1, r6, #1
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+120
	mov	r2, r4
	mov	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+124
	mov	r2, r4
	mvn	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+128
	mov	r2, r4
	mvn	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r2, .L10+132
	ldr	r3, .L10+136
	ldr	r1, [r2]
	ldr	r2, [r3]
	ldr	r3, .L10+140
	orr	r1, r1, r2
	ldr	r0, [r3]
	mov	r2, r4
	bl	aty_st_le32
	ldr	r3, .L10+144
	ldr	r2, .L10+148
	ldr	r0, [r3]
	ldr	r1, [r2]
	mov	r2, r4
	bl	aty_st_le32
	mov	r1, r4
	mov	r0, #3
	bl	wait_for_fifo
	ldr	r3, .L10+152
	mov	r2, r4
	mov	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+156
	mov	r2, r4
	mvn	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+160
	mov	r2, r4
	ldr	r0, [r3]
	mov	r1, #0
	bl	aty_st_le32
	mov	r1, r4
	mov	r0, #2
	bl	wait_for_fifo
	ldr	r3, .L10+164
	mov	r2, r4
	ldr	r1, [r4, #4]
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+168
	mov	r2, r4
	ldr	r0, [r3]
	ldr	r1, [r4, #8]
	bl	aty_st_le32
	mov	r1, r4
	mov	r0, #5
	bl	wait_for_fifo
	ldr	r3, .L10+172
	mov	r2, r4
	mov	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+176
	mov	r2, r4
	mov	r1, #0
	ldr	r0, [r3]
	bl	aty_st_le32
	ldr	r3, .L10+180
	mov	r1, r4
	ldr	r5, [r3]
	mov	r0, r5
	bl	aty_ld_le32
	mov	r1, r0
	mov	r2, r4
	mov	r0, r5
	bic	r1, r1, #32
	bl	aty_st_le32
	ldr	r3, .L10+184
	mov	r2, r4
	ldr	r0, [r3]
	ldr	r1, .L10+188
	bl	aty_st_le32
	mov	r0, r4
	pop	{r4, r5, r6, lr}
	b	wait_for_idle
.L9:
	mov	r0, r4
	bl	reset_GTC_3D_engine
	b	.L3
.L11:
	.align	2
.L10:
	.word	RESET_3D
	.word	MEM_VGA_WP_SEL
	.word	MEM_VGA_RP_SEL
	.word	CONTEXT_MASK
	.word	DST_OFF_PITCH
	.word	DST_Y_X
	.word	DST_HEIGHT
	.word	DST_BRES_ERR
	.word	DST_BRES_INC
	.word	DST_BRES_DEC
	.word	DST_Y_TOP_TO_BOTTOM
	.word	DST_LAST_PEL
	.word	DST_X_LEFT_TO_RIGHT
	.word	DST_CNTL
	.word	SRC_OFF_PITCH
	.word	SRC_Y_X
	.word	SRC_HEIGHT1_WIDTH1
	.word	SRC_Y_X_START
	.word	SRC_HEIGHT2_WIDTH2
	.word	SRC_CNTL
	.word	SRC_LINE_X_LEFT_TO_RIGHT
	.word	HOST_CNTL
	.word	HOST_BYTE_ALIGN
	.word	PAT_REG0
	.word	PAT_REG1
	.word	PAT_CNTL
	.word	SC_LEFT
	.word	SC_TOP
	.word	SC_BOTTOM
	.word	SC_RIGHT
	.word	DP_BKGD_CLR
	.word	DP_FRGD_CLR
	.word	DP_WRITE_MASK
	.word	FRGD_MIX_S
	.word	BKGD_MIX_D
	.word	DP_MIX
	.word	DP_SRC
	.word	FRGD_SRC_FRGD_CLR
	.word	CLR_CMP_CLR
	.word	CLR_CMP_MASK
	.word	CLR_CMP_CNTL
	.word	DP_PIX_WIDTH
	.word	DP_CHAIN_MASK
	.word	SCALE_3D_CNTL
	.word	Z_CNTL
	.word	CRTC_INT_CNTL
	.word	GUI_TRAJ_CNTL
	.word	1048611
	.size	aty_init_engine, .-aty_init_engine
	.comm	Z_CNTL,4,4
	.comm	SRC_Y_X_START,4,4
	.comm	SRC_Y_X,4,4
	.comm	SRC_OFF_PITCH,4,4
	.comm	SRC_LINE_X_LEFT_TO_RIGHT,4,4
	.comm	SRC_HEIGHT2_WIDTH2,4,4
	.comm	SRC_HEIGHT1_WIDTH1,4,4
	.comm	SRC_CNTL,4,4
	.comm	SC_TOP,4,4
	.comm	SC_RIGHT,4,4
	.comm	SC_LEFT,4,4
	.comm	SC_BOTTOM,4,4
	.comm	SCALE_3D_CNTL,4,4
	.comm	RESET_3D,4,4
	.comm	PAT_REG1,4,4
	.comm	PAT_REG0,4,4
	.comm	PAT_CNTL,4,4
	.comm	MEM_VGA_WP_SEL,4,4
	.comm	MEM_VGA_RP_SEL,4,4
	.comm	HOST_CNTL,4,4
	.comm	HOST_BYTE_ALIGN,4,4
	.comm	GUI_TRAJ_CNTL,4,4
	.comm	FRGD_SRC_FRGD_CLR,4,4
	.comm	FRGD_MIX_S,4,4
	.comm	DST_Y_X,4,4
	.comm	DST_Y_TOP_TO_BOTTOM,4,4
	.comm	DST_X_LEFT_TO_RIGHT,4,4
	.comm	DST_OFF_PITCH,4,4
	.comm	DST_LAST_PEL,4,4
	.comm	DST_HEIGHT,4,4
	.comm	DST_CNTL,4,4
	.comm	DST_BRES_INC,4,4
	.comm	DST_BRES_ERR,4,4
	.comm	DST_BRES_DEC,4,4
	.comm	DP_WRITE_MASK,4,4
	.comm	DP_SRC,4,4
	.comm	DP_PIX_WIDTH,4,4
	.comm	DP_MIX,4,4
	.comm	DP_FRGD_CLR,4,4
	.comm	DP_CHAIN_MASK,4,4
	.comm	DP_BKGD_CLR,4,4
	.comm	CRTC_INT_CNTL,4,4
	.comm	CONTEXT_MASK,4,4
	.comm	CLR_CMP_MASK,4,4
	.comm	CLR_CMP_CNTL,4,4
	.comm	CLR_CMP_CLR,4,4
	.comm	BKGD_MIX_D,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
