	.file	"extr_clock.c_s3c2412_clkcon_enable.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	s3c2412_clkcon_enable, @function
s3c2412_clkcon_enable:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	ebp, esi
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	mov	ebx, DWORD PTR [rdi]
	mov	edi, DWORD PTR S3C2410_CLKCON[rip]
	call	__raw_readl@PLT
	mov	rdi, rax
	test	ebp, ebp
	je	.L2
	or	rdi, rbx
.L3:
	mov	esi, DWORD PTR S3C2410_CLKCON[rip]
	call	__raw_writel@PLT
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	xor	eax, eax
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L2:
	.cfi_restore_state
	not	ebx
	and	rdi, rbx
	jmp	.L3
	.cfi_endproc
.LFE0:
	.size	s3c2412_clkcon_enable, .-s3c2412_clkcon_enable
	.comm	S3C2410_CLKCON,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_clock.c_s3c2412_clkcon_enable.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	s3c2412_clkcon_enable, %function
s3c2412_clkcon_enable:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	mov	r3, r0
	push	{r4, r5, r6, lr}
	ldr	r5, .L6
	mov	r4, r1
	ldr	r0, [r5]
	ldr	r6, [r3]
	bl	__raw_readl
	cmp	r4, #0
	ldr	r1, [r5]
	orrne	r0, r6, r0
	biceq	r0, r0, r6
	bl	__raw_writel
	mov	r0, #0
	pop	{r4, r5, r6, pc}
.L7:
	.align	2
.L6:
	.word	S3C2410_CLKCON
	.size	s3c2412_clkcon_enable, .-s3c2412_clkcon_enable
	.comm	S3C2410_CLKCON,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
