	.file	"extr_gfx_v8_0.c_gfx_v8_0_init_compute_vmid.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	gfx_v8_0_init_compute_vmid, @function
gfx_v8_0_init_compute_vmid:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	mov	r13, rdi
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	sub	rsp, 8
	.cfi_def_cfa_offset 48
	mov	eax, DWORD PTR DEFAULT_SH_MEM_BASES[rip]
	mov	ecx, DWORD PTR SH_MEM_CONFIG__ADDRESS_MODE__SHIFT[rip]
	mov	ebp, DWORD PTR SH_MEM_ADDRESS_MODE_HSA64[rip]
	mov	r12d, eax
	sal	r12d, 16
	sal	ebp, cl
	mov	ecx, DWORD PTR SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT[rip]
	or	r12d, eax
	mov	eax, DWORD PTR SH_MEM_ALIGNMENT_MODE_UNALIGNED[rip]
	sal	eax, cl
	mov	ecx, DWORD PTR SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT[rip]
	or	ebp, eax
	mov	eax, DWORD PTR MTYPE_CC[rip]
	or	ebp, DWORD PTR SH_MEM_CONFIG__PRIVATE_ATC_MASK[rip]
	sal	eax, cl
	or	ebp, eax
	call	mutex_lock@PLT
	mov	ebx, DWORD PTR FIRST_COMPUTE_VMID[rip]
	cmp	ebx, DWORD PTR LAST_COMPUTE_VMID[rip]
	jge	.L2
	.p2align 4,,10
	.p2align 3
.L3:
	mov	r8d, ebx
	xor	ecx, ecx
	xor	edx, edx
	xor	esi, esi
	mov	rdi, r13
	add	ebx, 1
	call	vi_srbm_select@PLT
	mov	edi, DWORD PTR mmSH_MEM_CONFIG[rip]
	mov	esi, ebp
	call	WREG32@PLT
	mov	edi, DWORD PTR mmSH_MEM_APE1_BASE[rip]
	mov	esi, 1
	call	WREG32@PLT
	mov	edi, DWORD PTR mmSH_MEM_APE1_LIMIT[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	edi, DWORD PTR mmSH_MEM_BASES[rip]
	mov	esi, r12d
	call	WREG32@PLT
	cmp	DWORD PTR LAST_COMPUTE_VMID[rip], ebx
	jg	.L3
.L2:
	xor	r8d, r8d
	xor	ecx, ecx
	xor	edx, edx
	xor	esi, esi
	mov	rdi, r13
	call	vi_srbm_select@PLT
	mov	rdi, r13
	call	mutex_unlock@PLT
	mov	ebp, DWORD PTR FIRST_COMPUTE_VMID[rip]
	cmp	ebp, DWORD PTR LAST_COMPUTE_VMID[rip]
	jge	.L1
	movsx	rbx, ebp
	sal	rbx, 4
	.p2align 4,,10
	.p2align 3
.L5:
	mov	rax, QWORD PTR amdgpu_gds_reg_offset[rip]
	xor	esi, esi
	add	ebp, 1
	mov	edi, DWORD PTR 12[rax+rbx]
	call	WREG32@PLT
	mov	rax, QWORD PTR amdgpu_gds_reg_offset[rip]
	xor	esi, esi
	mov	edi, DWORD PTR 8[rax+rbx]
	call	WREG32@PLT
	mov	rax, QWORD PTR amdgpu_gds_reg_offset[rip]
	xor	esi, esi
	mov	edi, DWORD PTR 4[rax+rbx]
	call	WREG32@PLT
	mov	rax, QWORD PTR amdgpu_gds_reg_offset[rip]
	xor	esi, esi
	mov	edi, DWORD PTR [rax+rbx]
	add	rbx, 16
	call	WREG32@PLT
	cmp	DWORD PTR LAST_COMPUTE_VMID[rip], ebp
	jg	.L5
.L1:
	add	rsp, 8
	.cfi_def_cfa_offset 40
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE0:
	.size	gfx_v8_0_init_compute_vmid, .-gfx_v8_0_init_compute_vmid
	.comm	mmSH_MEM_CONFIG,4,4
	.comm	mmSH_MEM_BASES,4,4
	.comm	mmSH_MEM_APE1_LIMIT,4,4
	.comm	mmSH_MEM_APE1_BASE,4,4
	.comm	amdgpu_gds_reg_offset,8,8
	.comm	SH_MEM_CONFIG__PRIVATE_ATC_MASK,4,4
	.comm	SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT,4,4
	.comm	SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT,4,4
	.comm	SH_MEM_CONFIG__ADDRESS_MODE__SHIFT,4,4
	.comm	SH_MEM_ALIGNMENT_MODE_UNALIGNED,4,4
	.comm	SH_MEM_ADDRESS_MODE_HSA64,4,4
	.comm	MTYPE_CC,4,4
	.comm	LAST_COMPUTE_VMID,4,4
	.comm	FIRST_COMPUTE_VMID,4,4
	.comm	DEFAULT_SH_MEM_BASES,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_gfx_v8_0.c_gfx_v8_0_init_compute_vmid.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	gfx_v8_0_init_compute_vmid, %function
gfx_v8_0_init_compute_vmid:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	ldr	r1, .L10
	ldr	r3, .L10+4
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r3, [r3]
	ldr	r6, [r1]
	ldr	ip, .L10+8
	ldr	r2, .L10+12
	ldr	r1, .L10+16
	ldr	lr, [ip]
	lsl	r6, r6, r3
	ldr	ip, [r2]
	ldr	r3, .L10+20
	ldr	r2, .L10+24
	ldr	r1, [r1]
	ldr	r3, [r3]
	orr	r6, r6, lr, lsl ip
	ldr	r2, [r2]
	ldr	ip, .L10+28
	orr	r6, r6, r1
	sub	sp, sp, #12
	ldr	r8, [ip]
	orr	r6, r6, r2, lsl r3
	mov	r7, r0
	ldr	r5, .L10+32
	bl	mutex_lock
	ldr	r3, .L10+36
	orr	r8, r8, r8, lsl #16
	ldr	r4, [r3]
	ldr	r3, [r5]
	cmp	r4, r3
	bge	.L2
	ldr	fp, .L10+40
	ldr	r10, .L10+44
	ldr	r9, .L10+48
.L3:
	mov	r3, #0
	str	r4, [sp]
	mov	r2, r3
	mov	r1, r3
	mov	r0, r7
	bl	vi_srbm_select
	mov	r1, r6
	ldr	r0, [fp]
	bl	WREG32
	mov	r1, #1
	ldr	r0, [r10]
	bl	WREG32
	mov	r1, #0
	ldr	r0, [r9]
	bl	WREG32
	ldr	r3, .L10+52
	mov	r1, r8
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, [r5]
	add	r4, r4, #1
	cmp	r3, r4
	bgt	.L3
.L2:
	mov	r3, #0
	mov	r0, r7
	mov	r2, r3
	mov	r1, r3
	str	r3, [sp]
	bl	vi_srbm_select
	mov	r0, r7
	bl	mutex_unlock
	ldr	r3, .L10+36
	ldr	r4, [r3]
	ldr	r3, [r5]
	cmp	r4, r3
	bge	.L1
	ldr	r6, .L10+56
.L5:
	ldr	r3, [r6]
	mov	r1, #0
	add	r3, r3, r4, lsl #4
	ldr	r0, [r3, #12]
	bl	WREG32
	ldr	r2, [r6]
	lsl	r7, r4, #4
	add	r2, r2, r7
	ldr	r0, [r2, #8]
	mov	r1, #0
	bl	WREG32
	ldr	r3, [r6]
	mov	r1, #0
	add	r3, r3, r7
	ldr	r0, [r3, #4]
	bl	WREG32
	ldr	r3, [r6]
	mov	r1, #0
	ldr	r0, [r3, r4, lsl #4]
	bl	WREG32
	ldr	r3, [r5]
	add	r4, r4, #1
	cmp	r3, r4
	bgt	.L5
.L1:
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L11:
	.align	2
.L10:
	.word	SH_MEM_ALIGNMENT_MODE_UNALIGNED
	.word	SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT
	.word	SH_MEM_ADDRESS_MODE_HSA64
	.word	SH_MEM_CONFIG__ADDRESS_MODE__SHIFT
	.word	SH_MEM_CONFIG__PRIVATE_ATC_MASK
	.word	SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT
	.word	MTYPE_CC
	.word	DEFAULT_SH_MEM_BASES
	.word	LAST_COMPUTE_VMID
	.word	FIRST_COMPUTE_VMID
	.word	mmSH_MEM_CONFIG
	.word	mmSH_MEM_APE1_BASE
	.word	mmSH_MEM_APE1_LIMIT
	.word	mmSH_MEM_BASES
	.word	amdgpu_gds_reg_offset
	.size	gfx_v8_0_init_compute_vmid, .-gfx_v8_0_init_compute_vmid
	.comm	mmSH_MEM_CONFIG,4,4
	.comm	mmSH_MEM_BASES,4,4
	.comm	mmSH_MEM_APE1_LIMIT,4,4
	.comm	mmSH_MEM_APE1_BASE,4,4
	.comm	amdgpu_gds_reg_offset,4,4
	.comm	SH_MEM_CONFIG__PRIVATE_ATC_MASK,4,4
	.comm	SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT,4,4
	.comm	SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT,4,4
	.comm	SH_MEM_CONFIG__ADDRESS_MODE__SHIFT,4,4
	.comm	SH_MEM_ALIGNMENT_MODE_UNALIGNED,4,4
	.comm	SH_MEM_ADDRESS_MODE_HSA64,4,4
	.comm	MTYPE_CC,4,4
	.comm	LAST_COMPUTE_VMID,4,4
	.comm	FIRST_COMPUTE_VMID,4,4
	.comm	DEFAULT_SH_MEM_BASES,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
