	.file	"extr_ar9003_eeprom.c_ar9003_hw_internal_regulator_apply.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	ar9003_hw_internal_regulator_apply
	.type	ar9003_hw_internal_regulator_apply, @function
ar9003_hw_internal_regulator_apply:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	push	rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	mov	rbp, rdi
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	mov	r12d, DWORD PTR 8[rdi]
	mov	edi, 4
	call	BIT@PLT
	mov	rdi, rbp
	test	r12d, eax
	je	.L2
	call	AR_SREV_9330@PLT
	test	rax, rax
	je	.L3
.L6:
	mov	esi, DWORD PTR AR_PHY_PMU2[rip]
	mov	rdi, rbp
	call	REG_READ@PLT
	mov	r12d, DWORD PTR AR_PHY_PMU2_PGM[rip]
	mov	esi, DWORD PTR AR_PHY_PMU2[rip]
	mov	rdi, rbp
	not	r12d
	and	r12d, eax
	mov	edx, r12d
	call	REG_WRITE@PLT
	mov	esi, DWORD PTR AR_PHY_PMU2[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	is_pmu_set@PLT
	test	eax, eax
	je	.L1
	mov	rdi, rbp
	mov	r12d, 320635514
	call	AR_SREV_9330@PLT
	test	rax, rax
	je	.L9
	cmp	QWORD PTR 0[rbp], 1
	sbb	r12d, r12d
	and	r12d, -14
	add	r12d, 52183942
.L9:
	mov	esi, DWORD PTR AR_PHY_PMU1[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	REG_WRITE@PLT
	mov	esi, DWORD PTR AR_PHY_PMU1[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	is_pmu_set@PLT
	test	eax, eax
	jne	.L41
.L1:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L2:
	.cfi_restore_state
	call	AR_SREV_9330@PLT
	test	rax, rax
	je	.L12
.L14:
	mov	edx, DWORD PTR AR_PHY_PMU2_PGM[rip]
	mov	esi, DWORD PTR AR_PHY_PMU2[rip]
	xor	ecx, ecx
	mov	rdi, rbp
	call	REG_RMW_FIELD@PLT
	jmp	.L13
	.p2align 4,,10
	.p2align 3
.L16:
	mov	edi, 10
	call	udelay@PLT
.L13:
	mov	edx, DWORD PTR AR_PHY_PMU2_PGM[rip]
	mov	esi, DWORD PTR AR_PHY_PMU2[rip]
	mov	rdi, rbp
	call	REG_READ_FIELD@PLT
	test	rax, rax
	jne	.L16
	mov	edx, DWORD PTR AR_PHY_PMU1_PWD[rip]
	mov	esi, DWORD PTR AR_PHY_PMU1[rip]
	mov	ecx, 1
	mov	rdi, rbp
	call	REG_RMW_FIELD@PLT
	jmp	.L17
	.p2align 4,,10
	.p2align 3
.L18:
	mov	edi, 10
	call	udelay@PLT
.L17:
	mov	edx, DWORD PTR AR_PHY_PMU1_PWD[rip]
	mov	esi, DWORD PTR AR_PHY_PMU1[rip]
	mov	rdi, rbp
	call	REG_READ_FIELD@PLT
	test	rax, rax
	je	.L18
	mov	edx, DWORD PTR AR_PHY_PMU2_PGM[rip]
	mov	esi, DWORD PTR AR_PHY_PMU2[rip]
	mov	ecx, 1
	mov	rdi, rbp
	call	REG_RMW_FIELD@PLT
	jmp	.L19
	.p2align 4,,10
	.p2align 3
.L20:
	mov	edi, 10
	call	udelay@PLT
.L19:
	mov	edx, DWORD PTR AR_PHY_PMU2_PGM[rip]
	mov	esi, DWORD PTR AR_PHY_PMU2[rip]
	mov	rdi, rbp
	call	REG_READ_FIELD@PLT
	test	rax, rax
	je	.L20
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L3:
	.cfi_restore_state
	mov	rdi, rbp
	call	AR_SREV_9485@PLT
	test	rax, rax
	jne	.L6
	mov	rdi, rbp
	call	AR_SREV_9462@PLT
	test	rax, rax
	je	.L10
.L11:
	mov	edi, DWORD PTR 12[rbp]
	call	le32_to_cpu@PLT
	mov	esi, DWORD PTR AR_PHY_PMU1[rip]
	mov	edx, eax
.L39:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	mov	rdi, rbp
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	jmp	REG_WRITE@PLT
	.p2align 4,,10
	.p2align 3
.L12:
	.cfi_restore_state
	mov	rdi, rbp
	call	AR_SREV_9485@PLT
	test	rax, rax
	jne	.L14
	mov	rdi, rbp
	call	AR_SREV_9462@PLT
	test	rax, rax
	jne	.L22
	mov	rdi, rbp
	call	AR_SREV_9565@PLT
	test	rax, rax
	jne	.L22
	mov	esi, DWORD PTR AR_RTC_SLEEP_CLK[rip]
	mov	rdi, rbp
	call	REG_READ@PLT
	or	eax, DWORD PTR AR_RTC_FORCE_SWREG_PRD[rip]
	mov	esi, DWORD PTR AR_RTC_SLEEP_CLK[rip]
	mov	edx, eax
	jmp	.L39
	.p2align 4,,10
	.p2align 3
.L41:
	mov	esi, DWORD PTR AR_PHY_PMU2[rip]
	mov	rdi, rbp
	call	REG_READ@PLT
	mov	esi, DWORD PTR AR_PHY_PMU2[rip]
	mov	rdi, rbp
	and	eax, 4194303
	mov	r12d, eax
	or	r12d, 268435456
	mov	edx, r12d
	call	REG_WRITE@PLT
	mov	esi, DWORD PTR AR_PHY_PMU2[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	is_pmu_set@PLT
	test	eax, eax
	je	.L1
	mov	esi, DWORD PTR AR_PHY_PMU2[rip]
	mov	rdi, rbp
	call	REG_READ@PLT
	mov	esi, DWORD PTR AR_PHY_PMU2[rip]
	mov	rdi, rbp
	or	eax, 2097152
	mov	edx, eax
	mov	r12d, eax
	call	REG_WRITE@PLT
	mov	esi, DWORD PTR AR_PHY_PMU2[rip]
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	mov	edx, r12d
	mov	rdi, rbp
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	jmp	is_pmu_set@PLT
	.p2align 4,,10
	.p2align 3
.L22:
	.cfi_restore_state
	mov	edx, DWORD PTR AR_PHY_PMU1_PWD[rip]
	mov	esi, DWORD PTR AR_PHY_PMU1[rip]
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	mov	rdi, rbp
	mov	ecx, 1
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	jmp	REG_RMW_FIELD@PLT
	.p2align 4,,10
	.p2align 3
.L10:
	.cfi_restore_state
	mov	rdi, rbp
	call	AR_SREV_9565@PLT
	test	rax, rax
	jne	.L11
	mov	edi, DWORD PTR 12[rbp]
	call	le32_to_cpu@PLT
	mov	esi, DWORD PTR AR_RTC_REG_CONTROL1[rip]
	mov	rdi, rbp
	mov	r12d, eax
	call	REG_READ@PLT
	mov	edx, DWORD PTR AR_RTC_REG_CONTROL1_SWREG_PROGRAM[rip]
	mov	esi, DWORD PTR AR_RTC_REG_CONTROL1[rip]
	mov	rdi, rbp
	not	edx
	and	edx, eax
	call	REG_WRITE@PLT
	mov	esi, DWORD PTR AR_RTC_REG_CONTROL0[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	REG_WRITE@PLT
	mov	esi, DWORD PTR AR_RTC_REG_CONTROL1[rip]
	mov	rdi, rbp
	call	REG_READ@PLT
	or	eax, DWORD PTR AR_RTC_REG_CONTROL1_SWREG_PROGRAM[rip]
	mov	esi, DWORD PTR AR_RTC_REG_CONTROL1[rip]
	mov	edx, eax
	jmp	.L39
	.cfi_endproc
.LFE0:
	.size	ar9003_hw_internal_regulator_apply, .-ar9003_hw_internal_regulator_apply
	.comm	AR_RTC_SLEEP_CLK,4,4
	.comm	AR_RTC_REG_CONTROL1_SWREG_PROGRAM,4,4
	.comm	AR_RTC_REG_CONTROL1,4,4
	.comm	AR_RTC_REG_CONTROL0,4,4
	.comm	AR_RTC_FORCE_SWREG_PRD,4,4
	.comm	AR_PHY_PMU2_PGM,4,4
	.comm	AR_PHY_PMU2,4,4
	.comm	AR_PHY_PMU1_PWD,4,4
	.comm	AR_PHY_PMU1,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_ar9003_eeprom.c_ar9003_hw_internal_regulator_apply.c"
	.text
	.align	2
	.global	ar9003_hw_internal_regulator_apply
	.syntax unified
	.arm
	.fpu softvfp
	.type	ar9003_hw_internal_regulator_apply, %function
ar9003_hw_internal_regulator_apply:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	mov	r4, r0
	mov	r0, #4
	ldr	r5, [r4, #4]
	bl	BIT
	tst	r5, r0
	mov	r0, r4
	beq	.L2
	bl	AR_SREV_9330
	cmp	r0, #0
	beq	.L3
.L6:
	ldr	r5, .L41
	mov	r0, r4
	ldr	r1, [r5]
	bl	REG_READ
	mov	r6, r0
	ldr	r3, .L41+4
	ldr	r1, [r5]
	ldr	r2, [r3]
	mov	r0, r4
	bic	r6, r6, r2
	mov	r2, r6
	bl	REG_WRITE
	mov	r2, r6
	mov	r0, r4
	ldr	r1, [r5]
	bl	is_pmu_set
	cmp	r0, #0
	popeq	{r4, r5, r6, r7, r8, pc}
	mov	r0, r4
	bl	AR_SREV_9330
	cmp	r0, #0
	bne	.L40
	ldr	r6, .L41+8
.L9:
	ldr	r7, .L41+12
	mov	r2, r6
	ldr	r1, [r7]
	mov	r0, r4
	bl	REG_WRITE
	mov	r2, r6
	mov	r0, r4
	ldr	r1, [r7]
	bl	is_pmu_set
	cmp	r0, #0
	popeq	{r4, r5, r6, r7, r8, pc}
	ldr	r1, [r5]
	mov	r0, r4
	bl	REG_READ
	bic	r2, r0, #-16777216
	bic	r2, r2, #12582912
	orr	r6, r2, #268435456
	mov	r2, r6
	ldr	r1, [r5]
	mov	r0, r4
	bl	REG_WRITE
	mov	r2, r6
	mov	r0, r4
	ldr	r1, [r5]
	bl	is_pmu_set
	cmp	r0, #0
	popeq	{r4, r5, r6, r7, r8, pc}
	ldr	r1, [r5]
	mov	r0, r4
	bl	REG_READ
	orr	r6, r0, #2097152
	mov	r2, r6
	ldr	r1, [r5]
	mov	r0, r4
	bl	REG_WRITE
	mov	r2, r6
	mov	r0, r4
	ldr	r1, [r5]
	pop	{r4, r5, r6, r7, r8, lr}
	b	is_pmu_set
.L2:
	bl	AR_SREV_9330
	cmp	r0, #0
	beq	.L12
.L14:
	ldr	r6, .L41+4
	ldr	r5, .L41
	mov	r3, #0
	mov	r0, r4
	ldr	r2, [r6]
	ldr	r1, [r5]
	bl	REG_RMW_FIELD
	b	.L13
.L16:
	mov	r0, #10
	bl	udelay
.L13:
	mov	r0, r4
	ldr	r2, [r6]
	ldr	r1, [r5]
	bl	REG_READ_FIELD
	cmp	r0, #0
	bne	.L16
	ldr	r8, .L41+16
	ldr	r7, .L41+12
	mov	r3, #1
	mov	r0, r4
	ldr	r2, [r8]
	ldr	r1, [r7]
	bl	REG_RMW_FIELD
	b	.L17
.L18:
	mov	r0, #10
	bl	udelay
.L17:
	mov	r0, r4
	ldr	r2, [r8]
	ldr	r1, [r7]
	bl	REG_READ_FIELD
	cmp	r0, #0
	beq	.L18
	mov	r3, #1
	mov	r0, r4
	ldr	r2, [r6]
	ldr	r1, [r5]
	bl	REG_RMW_FIELD
.L19:
	mov	r0, r4
	ldr	r2, [r6]
	ldr	r1, [r5]
	bl	REG_READ_FIELD
	cmp	r0, #0
	popne	{r4, r5, r6, r7, r8, pc}
	mov	r0, #10
	bl	udelay
	b	.L19
.L3:
	mov	r0, r4
	bl	AR_SREV_9485
	cmp	r0, #0
	bne	.L6
	mov	r0, r4
	bl	AR_SREV_9462
	cmp	r0, #0
	bne	.L11
	mov	r0, r4
	bl	AR_SREV_9565
	cmp	r0, #0
	bne	.L11
	ldr	r0, [r4, #8]
	bl	le32_to_cpu
	ldr	r7, .L41+20
	mov	r5, r0
	ldr	r8, [r7]
	mov	r0, r4
	mov	r1, r8
	bl	REG_READ
	mov	r3, r0
	ldr	r6, .L41+24
	mov	r1, r8
	ldr	r2, [r6]
	mov	r0, r4
	bic	r2, r3, r2
	bl	REG_WRITE
	ldr	r3, .L41+28
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	REG_WRITE
	ldr	r5, [r7]
	mov	r0, r4
	mov	r1, r5
	bl	REG_READ
	ldr	r2, [r6]
	mov	r1, r5
	orr	r2, r0, r2
	mov	r0, r4
	pop	{r4, r5, r6, r7, r8, lr}
	b	REG_WRITE
.L12:
	mov	r0, r4
	bl	AR_SREV_9485
	cmp	r0, #0
	bne	.L14
	mov	r0, r4
	bl	AR_SREV_9462
	cmp	r0, #0
	bne	.L22
	mov	r0, r4
	bl	AR_SREV_9565
	cmp	r0, #0
	bne	.L22
	ldr	r5, .L41+32
	mov	r0, r4
	ldr	r1, [r5]
	bl	REG_READ
	mov	r2, r0
	ldr	r3, .L41+36
	mov	r0, r4
	ldr	r3, [r3]
	ldr	r1, [r5]
	orr	r2, r2, r3
	pop	{r4, r5, r6, r7, r8, lr}
	b	REG_WRITE
.L40:
	ldr	r3, [r4]
	ldr	r2, .L41+40
	cmp	r3, #0
	ldr	r6, .L41+44
	moveq	r6, r2
	b	.L9
.L11:
	ldr	r0, [r4, #8]
	bl	le32_to_cpu
	ldr	r3, .L41+12
	mov	r2, r0
	ldr	r1, [r3]
	mov	r0, r4
	pop	{r4, r5, r6, r7, r8, lr}
	b	REG_WRITE
.L22:
	ldr	r3, .L41+12
	ldr	r2, .L41+16
	mov	r0, r4
	pop	{r4, r5, r6, r7, r8, lr}
	ldr	r1, [r3]
	ldr	r2, [r2]
	mov	r3, #1
	b	REG_RMW_FIELD
.L42:
	.align	2
.L41:
	.word	AR_PHY_PMU2
	.word	AR_PHY_PMU2_PGM
	.word	320635514
	.word	AR_PHY_PMU1
	.word	AR_PHY_PMU1_PWD
	.word	AR_RTC_REG_CONTROL1
	.word	AR_RTC_REG_CONTROL1_SWREG_PROGRAM
	.word	AR_RTC_REG_CONTROL0
	.word	AR_RTC_SLEEP_CLK
	.word	AR_RTC_FORCE_SWREG_PRD
	.word	52183928
	.word	52183942
	.size	ar9003_hw_internal_regulator_apply, .-ar9003_hw_internal_regulator_apply
	.comm	AR_RTC_SLEEP_CLK,4,4
	.comm	AR_RTC_REG_CONTROL1_SWREG_PROGRAM,4,4
	.comm	AR_RTC_REG_CONTROL1,4,4
	.comm	AR_RTC_REG_CONTROL0,4,4
	.comm	AR_RTC_FORCE_SWREG_PRD,4,4
	.comm	AR_PHY_PMU2_PGM,4,4
	.comm	AR_PHY_PMU2,4,4
	.comm	AR_PHY_PMU1_PWD,4,4
	.comm	AR_PHY_PMU1,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
