	.file	"extr_snoc.c_ath10k_snoc_clk_init.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"snoc clock %s being enabled\n"
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC1:
	.string	"failed to set clock %s freq %u\n"
	.section	.rodata.str1.1
.LC2:
	.string	"failed to enable clock %s\n"
	.text
	.p2align 4
	.type	ath10k_snoc_clk_init, @function
ath10k_snoc_clk_init:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	lea	r15, .LC0[rip]
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	mov	r14, rdi
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	xor	ebp, ebp
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 24
	.cfi_def_cfa_offset 80
	call	ath10k_snoc_priv@PLT
	mov	r13, rax
	jmp	.L2
	.p2align 4,,10
	.p2align 3
.L6:
	mov	rbx, rbp
	sal	rbx, 4
	add	rbx, QWORD PTR 0[r13]
	mov	eax, DWORD PTR [rbx]
	test	eax, eax
	je	.L3
	mov	esi, DWORD PTR ATH10K_DBG_SNOC[rip]
	mov	ecx, DWORD PTR 4[rbx]
	mov	rdx, r15
	mov	rdi, r14
	call	ath10k_dbg@PLT
	mov	rsi, QWORD PTR 8[rbx]
	test	rsi, rsi
	je	.L4
	mov	edi, DWORD PTR [rbx]
	call	clk_set_rate@PLT
	test	eax, eax
	jne	.L28
.L4:
	mov	edi, DWORD PTR [rbx]
	call	clk_prepare_enable@PLT
	test	eax, eax
	jne	.L29
.L3:
	add	rbp, 1
.L2:
	mov	edi, DWORD PTR clk_cfg[rip]
	mov	r12d, ebp
	call	ARRAY_SIZE@PLT
	cmp	eax, ebp
	jg	.L6
	xor	r8d, r8d
.L1:
	add	rsp, 24
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	eax, r8d
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L29:
	.cfi_restore_state
	mov	edx, DWORD PTR 4[rbx]
	mov	DWORD PTR 12[rsp], eax
	lea	rsi, .LC2[rip]
	mov	rdi, r14
	xor	eax, eax
	call	ath10k_err@PLT
	mov	r8d, DWORD PTR 12[rsp]
.L5:
	lea	r14d, -1[r12]
	test	r12d, r12d
	je	.L1
	movsx	rbx, r12d
	lea	eax, -1[rbp]
	movsx	r14, r14d
	sub	rbx, rax
	sal	r14, 4
	sal	rbx, 4
	sub	rbx, 32
	.p2align 4,,10
	.p2align 3
.L9:
	mov	rax, QWORD PTR 0[r13]
	mov	edi, DWORD PTR [rax+r14]
	test	edi, edi
	je	.L8
	mov	DWORD PTR 12[rsp], r8d
	call	clk_disable_unprepare@PLT
	mov	r8d, DWORD PTR 12[rsp]
.L8:
	sub	r14, 16
	cmp	r14, rbx
	jne	.L9
	jmp	.L1
.L28:
	mov	rcx, QWORD PTR 8[rbx]
	mov	edx, DWORD PTR 4[rbx]
	mov	DWORD PTR 12[rsp], eax
	mov	rdi, r14
	lea	rsi, .LC1[rip]
	xor	eax, eax
	call	ath10k_err@PLT
	mov	r8d, DWORD PTR 12[rsp]
	jmp	.L5
	.cfi_endproc
.LFE0:
	.size	ath10k_snoc_clk_init, .-ath10k_snoc_clk_init
	.comm	clk_cfg,4,4
	.comm	ATH10K_DBG_SNOC,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_snoc.c_ath10k_snoc_clk_init.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"snoc clock %s being enabled\012\000"
	.align	2
.LC1:
	.ascii	"failed to set clock %s freq %u\012\000"
	.align	2
.LC2:
	.ascii	"failed to enable clock %s\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	ath10k_snoc_clk_init, %function
ath10k_snoc_clk_init:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	mov	fp, r0
	bl	ath10k_snoc_priv
	mov	r4, #0
	mov	r9, r0
	ldr	r10, .L33
	ldr	r7, .L33+4
	b	.L2
.L6:
	ldr	r6, [r9]
	ldr	r3, [r6, r5, lsl #2]
	add	r8, r6, r5, lsl #2
	cmp	r3, #0
	beq	.L3
	ldr	r1, .L33+8
	mov	r2, r7
	ldr	r1, [r1]
	mov	r0, fp
	ldr	r3, [r8, #4]
	bl	ath10k_dbg
	ldr	r1, [r8, #8]
	cmp	r1, #0
	beq	.L4
	ldr	r0, [r6, r5, lsl #2]
	bl	clk_set_rate
	cmp	r0, #0
	bne	.L31
.L4:
	ldr	r0, [r6, r5, lsl #2]
	bl	clk_prepare_enable
	cmp	r0, #0
	bne	.L32
.L3:
	add	r4, r4, #1
.L2:
	ldr	r0, [r10]
	bl	ARRAY_SIZE
	cmp	r0, r4
	add	r5, r4, r4, lsl #1
	bgt	.L6
	mov	r3, #0
	mov	r5, r3
.L1:
	mov	r0, r5
	pop	{r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L32:
	mov	r5, r0
	ldr	r2, [r8, #4]
	mov	r0, fp
	ldr	r1, .L33+12
	bl	ath10k_err
.L5:
	cmp	r4, #0
	sub	r4, r4, #1
	beq	.L1
.L9:
	ldr	r3, [r9]
	add	r2, r4, r4, lsl #1
	ldr	r0, [r3, r2, lsl #2]
	sub	r4, r4, #1
	cmp	r0, #0
	beq	.L8
	bl	clk_disable_unprepare
.L8:
	cmn	r4, #1
	bne	.L9
	mov	r0, r5
	pop	{r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L31:
	mov	r5, r0
	ldmib	r8, {r2, r3}
	mov	r0, fp
	ldr	r1, .L33+16
	bl	ath10k_err
	b	.L5
.L34:
	.align	2
.L33:
	.word	clk_cfg
	.word	.LC0
	.word	ATH10K_DBG_SNOC
	.word	.LC2
	.word	.LC1
	.size	ath10k_snoc_clk_init, .-ath10k_snoc_clk_init
	.comm	clk_cfg,4,4
	.comm	ATH10K_DBG_SNOC,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
