	.file	"extr_etnaviv_gpu.c_etnaviv_gpu_hw_init.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	etnaviv_gpu_hw_init, @function
etnaviv_gpu_hw_init:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	mov	esi, DWORD PTR GC320[rip]
	mov	edx, 20487
	push	rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	call	etnaviv_is_model_rev@PLT
	test	rax, rax
	jne	.L5
	mov	esi, DWORD PTR GC320[rip]
	mov	edx, 21024
	mov	rdi, rbp
	call	etnaviv_is_model_rev@PLT
	test	rax, rax
	jne	.L5
.L6:
	mov	rdi, rbp
	call	etnaviv_gpu_enable_mlcg@PLT
	mov	edi, 2
	call	VIVS_HI_AXI_CONFIG_AWCACHE@PLT
	mov	edi, 2
	mov	ebx, eax
	call	VIVS_HI_AXI_CONFIG_ARCACHE@PLT
	mov	esi, DWORD PTR VIVS_HI_AXI_CONFIG[rip]
	mov	rdi, rbp
	or	ebx, eax
	mov	edx, ebx
	call	gpu_write@PLT
	mov	esi, DWORD PTR GC2000[rip]
	mov	edx, 20744
	mov	rdi, rbp
	call	etnaviv_is_model_rev@PLT
	test	rax, rax
	jne	.L16
	mov	rax, QWORD PTR ETNA_SEC_KERNEL[rip]
	cmp	QWORD PTR 0[rbp], rax
	je	.L17
.L10:
	mov	rdi, rbp
	call	etnaviv_gpu_setup_pulse_eater@PLT
	mov	esi, DWORD PTR VIVS_HI_INTR_ENBL[rip]
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	mov	rdi, rbp
	mov	edx, -1
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	jmp	gpu_write@PLT
	.p2align 4,,10
	.p2align 3
.L5:
	.cfi_restore_state
	mov	esi, DWORD PTR VIVS_HI_CHIP_TIME[rip]
	mov	rdi, rbp
	call	gpu_read@PLT
	cmp	eax, 33956864
	je	.L6
	mov	esi, DWORD PTR VIVS_MC_DEBUG_MEMORY[rip]
	mov	rdi, rbp
	call	gpu_read@PLT
	xor	al, al
	mov	edx, eax
	or	edx, 8
	cmp	DWORD PTR 8[rbp], 20487
	jne	.L8
	or	eax, 12
	mov	edx, eax
.L8:
	mov	esi, DWORD PTR VIVS_MC_DEBUG_MEMORY[rip]
	mov	rdi, rbp
	call	gpu_write@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L16:
	mov	esi, DWORD PTR VIVS_MC_BUS_CONFIG[rip]
	mov	rdi, rbp
	call	gpu_read@PLT
	mov	edx, DWORD PTR VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK[rip]
	mov	edi, 1
	or	edx, DWORD PTR VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK[rip]
	not	edx
	and	edx, eax
	mov	r12d, edx
	call	VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG@PLT
	xor	edi, edi
	mov	ebx, eax
	call	VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG@PLT
	mov	esi, DWORD PTR VIVS_MC_BUS_CONFIG[rip]
	mov	rdi, rbp
	or	ebx, eax
	mov	edx, ebx
	or	edx, r12d
	call	gpu_write@PLT
	mov	rax, QWORD PTR ETNA_SEC_KERNEL[rip]
	cmp	QWORD PTR 0[rbp], rax
	jne	.L10
.L17:
	mov	esi, DWORD PTR VIVS_MMUv2_AHB_CONTROL[rip]
	mov	rdi, rbp
	call	gpu_read@PLT
	mov	esi, DWORD PTR VIVS_MMUv2_AHB_CONTROL[rip]
	or	eax, DWORD PTR VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS[rip]
	mov	rdi, rbp
	mov	edx, eax
	call	gpu_write@PLT
	jmp	.L10
	.cfi_endproc
.LFE0:
	.size	etnaviv_gpu_hw_init, .-etnaviv_gpu_hw_init
	.comm	VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS,4,4
	.comm	VIVS_MMUv2_AHB_CONTROL,4,4
	.comm	VIVS_MC_DEBUG_MEMORY,4,4
	.comm	VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK,4,4
	.comm	VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK,4,4
	.comm	VIVS_MC_BUS_CONFIG,4,4
	.comm	VIVS_HI_INTR_ENBL,4,4
	.comm	VIVS_HI_CHIP_TIME,4,4
	.comm	VIVS_HI_AXI_CONFIG,4,4
	.comm	GC320,4,4
	.comm	GC2000,4,4
	.comm	ETNA_SEC_KERNEL,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_etnaviv_gpu.c_etnaviv_gpu_hw_init.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	etnaviv_gpu_hw_init, %function
etnaviv_gpu_hw_init:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	ldr	r5, .L18
	ldr	r2, .L18+4
	ldr	r1, [r5]
	mov	r4, r0
	bl	etnaviv_is_model_rev
	cmp	r0, #0
	bne	.L5
	mov	r0, r4
	ldr	r1, [r5]
	ldr	r2, .L18+8
	bl	etnaviv_is_model_rev
	cmp	r0, #0
	bne	.L5
.L6:
	mov	r0, r4
	bl	etnaviv_gpu_enable_mlcg
	ldr	r3, .L18+12
	mov	r0, #2
	ldr	r6, [r3]
	bl	VIVS_HI_AXI_CONFIG_AWCACHE
	mov	r5, r0
	mov	r0, #2
	bl	VIVS_HI_AXI_CONFIG_ARCACHE
	mov	r1, r6
	orr	r2, r5, r0
	mov	r0, r4
	bl	gpu_write
	ldr	r3, .L18+16
	mov	r0, r4
	ldr	r2, .L18+20
	ldr	r1, [r3]
	bl	etnaviv_is_model_rev
	cmp	r0, #0
	bne	.L16
.L9:
	ldr	r3, .L18+24
	ldr	r2, [r4]
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L17
.L10:
	mov	r0, r4
	bl	etnaviv_gpu_setup_pulse_eater
	ldr	r3, .L18+28
	mov	r0, r4
	pop	{r4, r5, r6, r7, r8, lr}
	mvn	r2, #0
	ldr	r1, [r3]
	b	gpu_write
.L5:
	ldr	r3, .L18+32
	mov	r0, r4
	ldr	r1, [r3]
	bl	gpu_read
	ldr	r3, .L18+36
	cmp	r0, r3
	beq	.L6
	ldr	r5, .L18+40
	mov	r0, r4
	ldr	r1, [r5]
	bl	gpu_read
	ldr	r1, [r4, #4]
	ldr	r3, .L18+4
	bic	r2, r0, #255
	cmp	r1, r3
	mov	r0, r4
	ldr	r1, [r5]
	orreq	r2, r2, #12
	orrne	r2, r2, #8
	bl	gpu_write
	b	.L6
.L16:
	ldr	r7, .L18+44
	mov	r0, r4
	ldr	r1, [r7]
	bl	gpu_read
	mov	r6, r0
	ldr	r2, .L18+48
	ldr	r3, .L18+52
	ldr	r2, [r2]
	ldr	r3, [r3]
	mov	r0, #1
	orr	r2, r2, r3
	bic	r6, r6, r2
	bl	VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG
	mov	r5, r0
	mov	r0, #0
	bl	VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG
	orr	r5, r5, r0
	ldr	r1, [r7]
	mov	r0, r4
	orr	r2, r5, r6
	bl	gpu_write
	b	.L9
.L17:
	ldr	r5, .L18+56
	mov	r0, r4
	ldr	r1, [r5]
	bl	gpu_read
	mov	r2, r0
	ldr	r3, .L18+60
	mov	r0, r4
	ldr	r3, [r3]
	ldr	r1, [r5]
	orr	r2, r2, r3
	bl	gpu_write
	b	.L10
.L19:
	.align	2
.L18:
	.word	GC320
	.word	20487
	.word	21024
	.word	VIVS_HI_AXI_CONFIG
	.word	GC2000
	.word	20744
	.word	ETNA_SEC_KERNEL
	.word	VIVS_HI_INTR_ENBL
	.word	VIVS_HI_CHIP_TIME
	.word	33956864
	.word	VIVS_MC_DEBUG_MEMORY
	.word	VIVS_MC_BUS_CONFIG
	.word	VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK
	.word	VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK
	.word	VIVS_MMUv2_AHB_CONTROL
	.word	VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS
	.size	etnaviv_gpu_hw_init, .-etnaviv_gpu_hw_init
	.comm	VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS,4,4
	.comm	VIVS_MMUv2_AHB_CONTROL,4,4
	.comm	VIVS_MC_DEBUG_MEMORY,4,4
	.comm	VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK,4,4
	.comm	VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK,4,4
	.comm	VIVS_MC_BUS_CONFIG,4,4
	.comm	VIVS_HI_INTR_ENBL,4,4
	.comm	VIVS_HI_CHIP_TIME,4,4
	.comm	VIVS_HI_AXI_CONFIG,4,4
	.comm	GC320,4,4
	.comm	GC2000,4,4
	.comm	ETNA_SEC_KERNEL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
