	.file	"extr_wm8996.c_wm8996_set_fll.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"FLL disabled\n"
.LC1:
	.string	"Unknown FLL source %d\n"
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC2:
	.string	"FLL configured for %dHz->%dHz\n"
	.section	.rodata.str1.1
.LC3:
	.string	"Timed out waiting for FLL\n"
	.text
	.p2align 4
	.type	wm8996_set_fll, @function
wm8996_set_fll:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	mov	r14d, ecx
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	mov	r13d, edx
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	mov	r12d, r8d
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 88
	.cfi_def_cfa_offset 144
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 72[rsp], rax
	xor	eax, eax
	call	snd_soc_component_get_drvdata@PLT
	mov	edi, DWORD PTR 0[rbp]
	mov	rbx, rax
	call	to_i2c_client@PLT
	mov	QWORD PTR 24[rsp], rax
	cmp	DWORD PTR [rbx], r13d
	je	.L26
.L2:
	test	r12d, r12d
	je	.L27
	lea	rdi, 32[rsp]
	mov	edx, r12d
	mov	esi, r14d
	call	fll_factors@PLT
	mov	r8d, eax
	test	eax, eax
	jne	.L1
	lea	eax, -128[r13]
	cmp	eax, 3
	ja	.L5
	mov	ecx, DWORD PTR WM8996_FLL_REFCLK_DIV_SHIFT[rip]
	mov	edx, eax
	mov	eax, DWORD PTR 32[rsp]
	mov	rdi, rbp
	mov	esi, DWORD PTR 36[rsp]
	sal	eax, cl
	mov	ecx, DWORD PTR WM8996_FLL_REF_FREQ_SHIFT[rip]
	sal	esi, cl
	mov	ecx, esi
	mov	esi, DWORD PTR WM8996_FLL_CONTROL_5[rip]
	or	ecx, eax
	lea	rax, CSWTCH.35[rip]
	or	ecx, DWORD PTR [rax+rdx*4]
	mov	edx, DWORD PTR WM8996_FLL_REFCLK_DIV_MASK[rip]
	or	edx, DWORD PTR WM8996_FLL_REF_FREQ[rip]
	or	edx, DWORD PTR WM8996_FLL_REFCLK_SRC_MASK[rip]
	call	snd_soc_component_update_bits@PLT
	mov	eax, DWORD PTR 40[rsp]
	or	eax, DWORD PTR 44[rsp]
	je	.L28
	mov	ecx, DWORD PTR WM8996_FLL_LFSR_SEL_SHIFT[rip]
	mov	edx, 3
	sal	edx, cl
	or	edx, DWORD PTR WM8996_FLL_EFS_ENA[rip]
.L8:
	mov	esi, DWORD PTR WM8996_FLL_EFS_2[rip]
	mov	rdi, rbp
	call	snd_soc_component_write@PLT
	mov	ecx, DWORD PTR WM8996_FLL_OUTDIV_SHIFT[rip]
	mov	eax, DWORD PTR 48[rsp]
	mov	rdi, rbp
	mov	esi, DWORD PTR WM8996_FLL_CONTROL_2[rip]
	mov	edx, DWORD PTR WM8996_FLL_OUTDIV_MASK[rip]
	sal	eax, cl
	mov	ecx, DWORD PTR 52[rsp]
	or	edx, DWORD PTR WM8996_FLL_FRATIO_MASK[rip]
	or	ecx, eax
	call	snd_soc_component_update_bits@PLT
	mov	edx, DWORD PTR 40[rsp]
	mov	esi, DWORD PTR WM8996_FLL_CONTROL_3[rip]
	mov	rdi, rbp
	call	snd_soc_component_write@PLT
	mov	ecx, DWORD PTR WM8996_FLL_N_SHIFT[rip]
	mov	eax, DWORD PTR 56[rsp]
	mov	rdi, rbp
	mov	esi, DWORD PTR WM8996_FLL_CONTROL_4[rip]
	mov	edx, DWORD PTR WM8996_FLL_N_MASK[rip]
	sal	eax, cl
	mov	ecx, DWORD PTR 60[rsp]
	or	edx, DWORD PTR WM8996_FLL_LOOP_GAIN_MASK[rip]
	or	ecx, eax
	call	snd_soc_component_update_bits@PLT
	mov	esi, DWORD PTR WM8996_FLL_EFS_1[rip]
	mov	edx, DWORD PTR 44[rsp]
	mov	rdi, rbp
	call	snd_soc_component_write@PLT
	mov	esi, DWORD PTR WM8996_FLL_CONTROL_1[rip]
	mov	rdi, rbp
	call	snd_soc_component_read32@PLT
	test	DWORD PTR WM8996_FLL_ENA[rip], eax
	je	.L29
.L9:
	lea	r15, 12[rbx]
	mov	rdi, r15
	call	try_wait_for_completion@PLT
	mov	edx, DWORD PTR WM8996_FLL_ENA[rip]
	mov	esi, DWORD PTR WM8996_FLL_CONTROL_1[rip]
	mov	rdi, rbp
	mov	ecx, edx
	call	snd_soc_component_update_bits@PLT
	mov	edx, DWORD PTR WM8996_FLL_SWITCH_CLK[rip]
	mov	esi, DWORD PTR WM8996_FLL_CONTROL_6[rip]
	mov	rdi, rbp
	call	snd_soc_component_write@PLT
	cmp	r14d, 1000000
	jbe	.L10
	mov	edi, 300
	call	usecs_to_jiffies@PLT
.L11:
	mov	rsi, QWORD PTR 24[rsp]
	cmp	QWORD PTR [rsi], 0
	je	.L12
	lea	rax, [rax+rax*4]
	add	rax, rax
	mov	QWORD PTR 8[rsp], rax
.L13:
	mov	DWORD PTR 20[rsp], 10
	.p2align 4,,10
	.p2align 3
.L16:
	mov	rsi, QWORD PTR 8[rsp]
	mov	rdi, r15
	call	wait_for_completion_timeout@PLT
	test	rax, rax
	jne	.L30
	mov	esi, DWORD PTR WM8996_INTERRUPT_RAW_STATUS_2[rip]
	mov	rdi, rbp
	call	snd_soc_component_read32@PLT
	mov	r8d, eax
	test	DWORD PTR WM8996_FLL_LOCK_STS[rip], eax
	jne	.L15
	sub	DWORD PTR 20[rsp], 1
	jne	.L16
	mov	edi, DWORD PTR 0[rbp]
	lea	rsi, .LC3[rip]
	xor	eax, eax
	call	dev_err@PLT
	mov	r8d, DWORD PTR ETIMEDOUT[rip]
	neg	r8d
.L15:
	mov	edi, DWORD PTR 0[rbp]
	mov	ecx, r12d
	mov	edx, r14d
	lea	rsi, .LC2[rip]
	xor	eax, eax
	mov	DWORD PTR 8[rsp], r8d
	call	dev_dbg@PLT
	mov	DWORD PTR 4[rbx], r14d
	mov	r8d, DWORD PTR 8[rsp]
	mov	DWORD PTR 8[rbx], r12d
	mov	DWORD PTR [rbx], r13d
.L1:
	mov	rax, QWORD PTR 72[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L31
	add	rsp, 88
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	eax, r8d
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L26:
	.cfi_restore_state
	cmp	DWORD PTR 4[rbx], r14d
	jne	.L2
	xor	r8d, r8d
	cmp	DWORD PTR 8[rbx], r12d
	jne	.L2
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L27:
	mov	edi, DWORD PTR 0[rbp]
	lea	rsi, .LC0[rip]
	xor	eax, eax
	call	dev_dbg@PLT
	mov	edx, DWORD PTR WM8996_FLL_ENA[rip]
	xor	ecx, ecx
	mov	rdi, rbp
	mov	QWORD PTR 4[rbx], 0
	mov	esi, DWORD PTR WM8996_FLL_CONTROL_1[rip]
	call	snd_soc_component_update_bits@PLT
	mov	rdi, rbp
	call	wm8996_bg_disable@PLT
	xor	r8d, r8d
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L5:
	mov	edi, DWORD PTR 0[rbp]
	xor	edx, edx
	lea	rsi, .LC1[rip]
	xor	eax, eax
	call	dev_err@PLT
	mov	r8d, DWORD PTR EINVAL[rip]
	neg	r8d
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L28:
	mov	ecx, DWORD PTR WM8996_FLL_LFSR_SEL_SHIFT[rip]
	mov	edx, 1
	sal	edx, cl
	jmp	.L8
	.p2align 4,,10
	.p2align 3
.L12:
	mov	rdx, rax
	shr	rdx
	cmp	rax, 1
	mov	eax, 1
	cmova	rax, rdx
	mov	QWORD PTR 8[rsp], rax
	jmp	.L13
	.p2align 4,,10
	.p2align 3
.L10:
	mov	edi, 2
	call	msecs_to_jiffies@PLT
	jmp	.L11
	.p2align 4,,10
	.p2align 3
.L29:
	mov	rdi, rbp
	call	wm8996_bg_enable@PLT
	jmp	.L9
	.p2align 4,,10
	.p2align 3
.L30:
	mov	rax, QWORD PTR 24[rsp]
	xor	edi, edi
	cmp	QWORD PTR [rax], 0
	sete	dil
	call	WARN_ON@PLT
	mov	r8d, 1
	jmp	.L15
.L31:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	wm8996_set_fll, .-wm8996_set_fll
	.section	.rodata
	.align 16
	.type	CSWTCH.35, @object
	.size	CSWTCH.35, 16
CSWTCH.35:
	.long	1
	.long	0
	.long	2
	.long	3
	.comm	WM8996_INTERRUPT_RAW_STATUS_2,4,4
	.comm	WM8996_FLL_SWITCH_CLK,4,4
	.comm	WM8996_FLL_REF_FREQ_SHIFT,4,4
	.comm	WM8996_FLL_REF_FREQ,4,4
	.comm	WM8996_FLL_REFCLK_SRC_MASK,4,4
	.comm	WM8996_FLL_REFCLK_DIV_SHIFT,4,4
	.comm	WM8996_FLL_REFCLK_DIV_MASK,4,4
	.comm	WM8996_FLL_OUTDIV_SHIFT,4,4
	.comm	WM8996_FLL_OUTDIV_MASK,4,4
	.comm	WM8996_FLL_N_SHIFT,4,4
	.comm	WM8996_FLL_N_MASK,4,4
	.comm	WM8996_FLL_LOOP_GAIN_MASK,4,4
	.comm	WM8996_FLL_LOCK_STS,4,4
	.comm	WM8996_FLL_LFSR_SEL_SHIFT,4,4
	.comm	WM8996_FLL_FRATIO_MASK,4,4
	.comm	WM8996_FLL_ENA,4,4
	.comm	WM8996_FLL_EFS_ENA,4,4
	.comm	WM8996_FLL_EFS_2,4,4
	.comm	WM8996_FLL_EFS_1,4,4
	.comm	WM8996_FLL_CONTROL_6,4,4
	.comm	WM8996_FLL_CONTROL_5,4,4
	.comm	WM8996_FLL_CONTROL_4,4,4
	.comm	WM8996_FLL_CONTROL_3,4,4
	.comm	WM8996_FLL_CONTROL_2,4,4
	.comm	WM8996_FLL_CONTROL_1,4,4
	.comm	ETIMEDOUT,4,4
	.comm	EINVAL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_wm8996.c_wm8996_set_fll.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"FLL disabled\012\000"
	.align	2
.LC1:
	.ascii	"Unknown FLL source %d\012\000"
	.align	2
.LC2:
	.ascii	"FLL configured for %dHz->%dHz\012\000"
	.align	2
.LC3:
	.ascii	"Timed out waiting for FLL\012\000"
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC4:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	wm8996_set_fll, %function
wm8996_set_fll:
	@ args = 4, pretend = 0, frame = 48
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	mov	r8, r3
	ldr	r3, .L33
	sub	sp, sp, #52
	mov	r7, r2
	ldr	r3, [r3]
	str	r3, [sp, #44]
	mov	r3,#0
	mov	r5, r0
	ldr	r9, [sp, #88]
	bl	snd_soc_component_get_drvdata
	mov	r6, r0
	ldr	r0, [r5]
	bl	to_i2c_client
	ldr	r3, [r6]
	str	r0, [sp]
	cmp	r3, r7
	beq	.L27
.L2:
	cmp	r9, #0
	beq	.L28
	mov	r2, r9
	mov	r1, r8
	add	r0, sp, #12
	bl	fll_factors
	subs	r4, r0, #0
	bne	.L1
	sub	r1, r7, #128
	cmp	r1, #3
	bhi	.L5
	ldr	r3, .L33+4
	ldr	r0, .L33+8
	ldr	lr, [r3]
	ldr	ip, .L33+12
	ldr	r3, [sp, #16]
	ldr	r2, .L33+16
	ldr	r0, [r0]
	ldr	ip, [ip]
	ldr	r2, [r2]
	lsl	r3, r3, lr
	ldr	lr, [sp, #12]
	orr	r2, ip, r2
	orr	r3, r3, lr, lsl r0
	ldr	ip, .L33+20
	ldr	r0, .L33+24
	ldr	ip, [ip, r1, lsl #2]
	ldr	r0, [r0]
	ldr	r1, .L33+28
	orr	r2, r2, r0
	orr	r3, r3, ip
	mov	r0, r5
	ldr	r1, [r1]
	bl	snd_soc_component_update_bits
	ldr	r2, [sp, #20]
	ldr	r3, [sp, #24]
	orrs	r3, r2, r3
	beq	.L29
	mov	r1, #3
	ldr	r3, .L33+32
	ldr	r2, .L33+36
	ldr	r3, [r3]
	ldr	r2, [r2]
	orr	r2, r2, r1, lsl r3
.L8:
	ldr	r3, .L33+40
	mov	r0, r5
	ldr	r1, [r3]
	bl	snd_soc_component_write
	ldr	r3, .L33+44
	ldr	ip, [sp, #28]
	ldr	r1, [sp, #32]
	ldr	r3, [r3]
	ldr	r0, .L33+48
	ldr	r2, .L33+52
	orr	r3, r1, ip, lsl r3
	ldr	r0, [r0]
	ldr	r2, [r2]
	ldr	r1, .L33+56
	orr	r2, r0, r2
	ldr	r1, [r1]
	mov	r0, r5
	bl	snd_soc_component_update_bits
	ldr	r3, .L33+60
	ldr	r2, [sp, #20]
	ldr	r1, [r3]
	mov	r0, r5
	bl	snd_soc_component_write
	ldr	r3, .L33+64
	ldr	ip, [sp, #36]
	ldr	r1, [sp, #40]
	ldr	r3, [r3]
	ldr	r0, .L33+68
	ldr	r2, .L33+72
	orr	r3, r1, ip, lsl r3
	ldr	r0, [r0]
	ldr	r2, [r2]
	ldr	r1, .L33+76
	orr	r2, r0, r2
	ldr	r1, [r1]
	mov	r0, r5
	bl	snd_soc_component_update_bits
	ldr	r3, .L33+80
	ldr	r4, .L33+84
	ldr	r1, [r3]
	ldr	r2, [sp, #24]
	mov	r0, r5
	bl	snd_soc_component_write
	mov	r0, r5
	ldr	r1, [r4]
	bl	snd_soc_component_read32
	ldr	fp, .L33+88
	ldr	r3, [fp]
	tst	r0, r3
	beq	.L30
.L9:
	add	r10, r6, #12
	mov	r0, r10
	bl	try_wait_for_completion
	ldr	r3, [fp]
	ldr	r1, [r4]
	mov	r2, r3
	mov	r0, r5
	bl	snd_soc_component_update_bits
	ldr	r3, .L33+92
	ldr	r2, .L33+96
	ldr	r1, [r3]
	mov	r0, r5
	ldr	r2, [r2]
	bl	snd_soc_component_write
	ldr	r3, .L33+100
	cmp	r8, r3
	bls	.L10
	mov	r0, #300
	bl	usecs_to_jiffies
.L11:
	ldr	r3, [sp]
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L12
	add	r0, r0, r0, lsl #2
	lsl	r3, r0, #1
	mov	r2, r3
.L13:
	mov	r3, #10
	str	r6, [sp, #4]
	mov	r4, r2
	mov	r6, r3
	ldr	fp, .L33+104
.L16:
	mov	r1, r4
	mov	r0, r10
	bl	wait_for_completion_timeout
	cmp	r0, #0
	bne	.L31
	ldr	r3, .L33+108
	mov	r0, r5
	ldr	r1, [r3]
	bl	snd_soc_component_read32
	ldr	r3, [fp]
	tst	r0, r3
	bne	.L24
	subs	r6, r6, #1
	bne	.L16
	ldr	r1, .L33+112
	ldr	r0, [r5]
	ldr	r6, [sp, #4]
	bl	dev_err
	ldr	r3, .L33+116
	ldr	r4, [r3]
	rsb	r4, r4, #0
.L15:
	mov	r3, r9
	mov	r2, r8
	ldr	r0, [r5]
	ldr	r1, .L33+120
	bl	dev_dbg
	stm	r6, {r7, r8, r9}
.L1:
	ldr	r3, .L33
	ldr	r2, [r3]
	ldr	r3, [sp, #44]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L32
	mov	r0, r4
	add	sp, sp, #52
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L27:
	ldr	r3, [r6, #4]
	cmp	r3, r8
	bne	.L2
	ldr	r3, [r6, #8]
	cmp	r3, r9
	moveq	r4, #0
	bne	.L2
	b	.L1
.L28:
	ldr	r1, .L33+124
	ldr	r0, [r5]
	bl	dev_dbg
	ldr	r3, .L33+84
	ldr	r2, .L33+88
	ldr	r1, [r3]
	mov	r0, r5
	mov	r3, r9
	ldr	r2, [r2]
	str	r9, [r6, #4]
	str	r9, [r6, #8]
	bl	snd_soc_component_update_bits
	mov	r0, r5
	mov	r4, r9
	bl	wm8996_bg_disable
	b	.L1
.L5:
	mov	r2, r4
	ldr	r0, [r5]
	ldr	r1, .L33+128
	bl	dev_err
	ldr	r3, .L33+132
	ldr	r4, [r3]
	rsb	r4, r4, #0
	b	.L1
.L29:
	mov	r2, #1
	ldr	r3, .L33+32
	ldr	r3, [r3]
	lsl	r2, r2, r3
	b	.L8
.L12:
	cmp	r0, #1
	movls	r3, #1
	lsrhi	r3, r0, #1
	mov	r2, r3
	b	.L13
.L10:
	mov	r0, #2
	bl	msecs_to_jiffies
	b	.L11
.L30:
	mov	r0, r5
	bl	wm8996_bg_enable
	b	.L9
.L31:
	ldm	sp, {r3, r6}
	ldr	r0, [r3]
	mov	r4, #1
	clz	r0, r0
	lsr	r0, r0, #5
	bl	WARN_ON
	b	.L15
.L24:
	mov	r4, r0
	ldr	r6, [sp, #4]
	b	.L15
.L32:
	bl	__stack_chk_fail
.L34:
	.align	2
.L33:
	.word	.LC4
	.word	WM8996_FLL_REF_FREQ_SHIFT
	.word	WM8996_FLL_REFCLK_DIV_SHIFT
	.word	WM8996_FLL_REFCLK_DIV_MASK
	.word	WM8996_FLL_REF_FREQ
	.word	.LANCHOR0
	.word	WM8996_FLL_REFCLK_SRC_MASK
	.word	WM8996_FLL_CONTROL_5
	.word	WM8996_FLL_LFSR_SEL_SHIFT
	.word	WM8996_FLL_EFS_ENA
	.word	WM8996_FLL_EFS_2
	.word	WM8996_FLL_OUTDIV_SHIFT
	.word	WM8996_FLL_OUTDIV_MASK
	.word	WM8996_FLL_FRATIO_MASK
	.word	WM8996_FLL_CONTROL_2
	.word	WM8996_FLL_CONTROL_3
	.word	WM8996_FLL_N_SHIFT
	.word	WM8996_FLL_N_MASK
	.word	WM8996_FLL_LOOP_GAIN_MASK
	.word	WM8996_FLL_CONTROL_4
	.word	WM8996_FLL_EFS_1
	.word	WM8996_FLL_CONTROL_1
	.word	WM8996_FLL_ENA
	.word	WM8996_FLL_CONTROL_6
	.word	WM8996_FLL_SWITCH_CLK
	.word	1000000
	.word	WM8996_FLL_LOCK_STS
	.word	WM8996_INTERRUPT_RAW_STATUS_2
	.word	.LC3
	.word	ETIMEDOUT
	.word	.LC2
	.word	.LC0
	.word	.LC1
	.word	EINVAL
	.size	wm8996_set_fll, .-wm8996_set_fll
	.comm	WM8996_INTERRUPT_RAW_STATUS_2,4,4
	.comm	WM8996_FLL_SWITCH_CLK,4,4
	.comm	WM8996_FLL_REF_FREQ_SHIFT,4,4
	.comm	WM8996_FLL_REF_FREQ,4,4
	.comm	WM8996_FLL_REFCLK_SRC_MASK,4,4
	.comm	WM8996_FLL_REFCLK_DIV_SHIFT,4,4
	.comm	WM8996_FLL_REFCLK_DIV_MASK,4,4
	.comm	WM8996_FLL_OUTDIV_SHIFT,4,4
	.comm	WM8996_FLL_OUTDIV_MASK,4,4
	.comm	WM8996_FLL_N_SHIFT,4,4
	.comm	WM8996_FLL_N_MASK,4,4
	.comm	WM8996_FLL_LOOP_GAIN_MASK,4,4
	.comm	WM8996_FLL_LOCK_STS,4,4
	.comm	WM8996_FLL_LFSR_SEL_SHIFT,4,4
	.comm	WM8996_FLL_FRATIO_MASK,4,4
	.comm	WM8996_FLL_ENA,4,4
	.comm	WM8996_FLL_EFS_ENA,4,4
	.comm	WM8996_FLL_EFS_2,4,4
	.comm	WM8996_FLL_EFS_1,4,4
	.comm	WM8996_FLL_CONTROL_6,4,4
	.comm	WM8996_FLL_CONTROL_5,4,4
	.comm	WM8996_FLL_CONTROL_4,4,4
	.comm	WM8996_FLL_CONTROL_3,4,4
	.comm	WM8996_FLL_CONTROL_2,4,4
	.comm	WM8996_FLL_CONTROL_1,4,4
	.comm	ETIMEDOUT,4,4
	.comm	EINVAL,4,4
	.section	.rodata
	.align	2
	.set	.LANCHOR0,. + 0
	.type	CSWTCH.35, %object
	.size	CSWTCH.35, 16
CSWTCH.35:
	.word	1
	.word	0
	.word	2
	.word	3
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
