	.file	"extr_rt61pci.c_rt61pci_config_ps.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	rt61pci_config_ps, @function
rt61pci_config_ps:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	push	rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	mov	rbx, rsi
	sub	rsp, 16
	.cfi_def_cfa_offset 48
	mov	esi, DWORD PTR MAC_CSR11[rip]
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 8[rsp], rax
	xor	eax, eax
	mov	rax, QWORD PTR [rbx]
	mov	eax, DWORD PTR [rax]
	test	DWORD PTR IEEE80211_CONF_PS[rip], eax
	je	.L8
.L2:
	call	rt2x00mmio_register_read@PLT
	lea	r12, 4[rsp]
	mov	esi, DWORD PTR MAC_CSR11_DELAY_AFTER_TBCN[rip]
	mov	DWORD PTR 4[rsp], eax
	mov	eax, DWORD PTR 0[rbp]
	mov	rdi, r12
	lea	edx, -10[rax]
	call	rt2x00_set_field32@PLT
	mov	rax, QWORD PTR [rbx]
	mov	esi, DWORD PTR MAC_CSR11_TBCN_BEFORE_WAKEUP[rip]
	mov	rdi, r12
	mov	edx, DWORD PTR 4[rax]
	sub	edx, 1
	call	rt2x00_set_field32@PLT
	mov	esi, DWORD PTR MAC_CSR11_WAKEUP_LATENCY[rip]
	mov	edx, 5
	mov	rdi, r12
	call	rt2x00_set_field32@PLT
	mov	esi, DWORD PTR MAC_CSR11_AUTOWAKE[rip]
	xor	edx, edx
	mov	rdi, r12
	call	rt2x00_set_field32@PLT
	mov	edx, DWORD PTR 4[rsp]
	mov	esi, DWORD PTR MAC_CSR11[rip]
	mov	rdi, rbp
	call	rt2x00mmio_register_write@PLT
	mov	esi, DWORD PTR MAC_CSR11_AUTOWAKE[rip]
	mov	edx, 1
	mov	rdi, r12
	call	rt2x00_set_field32@PLT
	mov	edx, DWORD PTR 4[rsp]
	mov	esi, DWORD PTR MAC_CSR11[rip]
	mov	rdi, rbp
	call	rt2x00mmio_register_write@PLT
	mov	esi, DWORD PTR SOFT_RESET_CSR[rip]
	mov	edx, 5
	mov	rdi, rbp
	call	rt2x00mmio_register_write@PLT
	mov	esi, DWORD PTR IO_CNTL_CSR[rip]
	mov	edx, 28
	mov	rdi, rbp
	call	rt2x00mmio_register_write@PLT
	mov	esi, DWORD PTR PCI_USEC_CSR[rip]
	mov	edx, 96
	mov	rdi, rbp
	call	rt2x00mmio_register_write@PLT
	mov	esi, DWORD PTR MCU_SLEEP[rip]
	xor	r8d, r8d
	xor	ecx, ecx
	mov	edx, 255
	mov	rdi, rbp
	call	rt61pci_mcu_request@PLT
.L1:
	mov	rax, QWORD PTR 8[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L9
	add	rsp, 16
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	pop	rbx
	.cfi_def_cfa_offset 24
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L8:
	.cfi_restore_state
	mov	eax, DWORD PTR STATE_SLEEP[rip]
	cmp	DWORD PTR STATE_AWAKE[rip], eax
	je	.L2
	call	rt2x00mmio_register_read@PLT
	lea	r12, 4[rsp]
	mov	esi, DWORD PTR MAC_CSR11_DELAY_AFTER_TBCN[rip]
	xor	edx, edx
	mov	rdi, r12
	mov	DWORD PTR 4[rsp], eax
	call	rt2x00_set_field32@PLT
	mov	esi, DWORD PTR MAC_CSR11_TBCN_BEFORE_WAKEUP[rip]
	xor	edx, edx
	mov	rdi, r12
	call	rt2x00_set_field32@PLT
	mov	esi, DWORD PTR MAC_CSR11_AUTOWAKE[rip]
	xor	edx, edx
	mov	rdi, r12
	call	rt2x00_set_field32@PLT
	mov	esi, DWORD PTR MAC_CSR11_WAKEUP_LATENCY[rip]
	xor	edx, edx
	mov	rdi, r12
	call	rt2x00_set_field32@PLT
	mov	edx, DWORD PTR 4[rsp]
	mov	esi, DWORD PTR MAC_CSR11[rip]
	mov	rdi, rbp
	call	rt2x00mmio_register_write@PLT
	mov	esi, DWORD PTR SOFT_RESET_CSR[rip]
	mov	rdi, rbp
	mov	edx, 7
	call	rt2x00mmio_register_write@PLT
	mov	esi, DWORD PTR IO_CNTL_CSR[rip]
	mov	rdi, rbp
	mov	edx, 24
	call	rt2x00mmio_register_write@PLT
	mov	esi, DWORD PTR PCI_USEC_CSR[rip]
	mov	rdi, rbp
	mov	edx, 32
	call	rt2x00mmio_register_write@PLT
	mov	esi, DWORD PTR MCU_WAKEUP[rip]
	xor	r8d, r8d
	xor	ecx, ecx
	mov	edx, 255
	mov	rdi, rbp
	call	rt61pci_mcu_request@PLT
	jmp	.L1
.L9:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	rt61pci_config_ps, .-rt61pci_config_ps
	.comm	STATE_SLEEP,4,4
	.comm	STATE_AWAKE,4,4
	.comm	SOFT_RESET_CSR,4,4
	.comm	PCI_USEC_CSR,4,4
	.comm	MCU_WAKEUP,4,4
	.comm	MCU_SLEEP,4,4
	.comm	MAC_CSR11_WAKEUP_LATENCY,4,4
	.comm	MAC_CSR11_TBCN_BEFORE_WAKEUP,4,4
	.comm	MAC_CSR11_DELAY_AFTER_TBCN,4,4
	.comm	MAC_CSR11_AUTOWAKE,4,4
	.comm	MAC_CSR11,4,4
	.comm	IO_CNTL_CSR,4,4
	.comm	IEEE80211_CONF_PS,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_rt61pci.c_rt61pci_config_ps.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	rt61pci_config_ps, %function
rt61pci_config_ps:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, lr}
	ldr	r2, [r1]
	ldr	r3, .L10
	ldr	r2, [r2]
	ldr	r3, [r3]
	ldr	r5, .L10+4
	ands	r6, r2, r3
	ldr	r3, .L10+8
	sub	sp, sp, #20
	mov	r7, r1
	ldr	r3, [r3]
	str	r3, [sp, #12]
	mov	r3,#0
	mov	r4, r0
	ldr	r1, [r5]
	beq	.L8
.L2:
	mov	r0, r4
	bl	rt2x00mmio_register_read
	mov	r3, r0
	ldr	r2, [r4]
	ldr	r1, .L10+12
	sub	r2, r2, #10
	ldr	r1, [r1]
	add	r0, sp, #8
	str	r3, [sp, #8]
	bl	rt2x00_set_field32
	ldr	r2, [r7]
	ldr	r3, .L10+16
	ldr	r2, [r2, #4]
	ldr	r1, [r3]
	sub	r2, r2, #1
	add	r0, sp, #8
	bl	rt2x00_set_field32
	ldr	r3, .L10+20
	ldr	r6, .L10+24
	ldr	r1, [r3]
	mov	r2, #5
	add	r0, sp, #8
	bl	rt2x00_set_field32
	mov	r2, #0
	ldr	r1, [r6]
	add	r0, sp, #8
	bl	rt2x00_set_field32
	ldr	r2, [sp, #8]
	ldr	r1, [r5]
	mov	r0, r4
	bl	rt2x00mmio_register_write
	mov	r2, #1
	ldr	r1, [r6]
	add	r0, sp, #8
	bl	rt2x00_set_field32
	ldr	r1, [r5]
	ldr	r2, [sp, #8]
	mov	r0, r4
	bl	rt2x00mmio_register_write
	ldr	r3, .L10+28
	mov	r2, #5
	ldr	r1, [r3]
	mov	r0, r4
	bl	rt2x00mmio_register_write
	ldr	r3, .L10+32
	mov	r2, #28
	ldr	r1, [r3]
	mov	r0, r4
	bl	rt2x00mmio_register_write
	ldr	r3, .L10+36
	mov	r2, #96
	ldr	r1, [r3]
	mov	r0, r4
	bl	rt2x00mmio_register_write
	mov	r3, #0
	ldr	r2, .L10+40
	str	r3, [sp]
	ldr	r1, [r2]
	mov	r0, r4
	mov	r2, #255
	bl	rt61pci_mcu_request
.L1:
	ldr	r3, .L10+8
	ldr	r2, [r3]
	ldr	r3, [sp, #12]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L9
	add	sp, sp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, pc}
.L8:
	ldr	r2, .L10+44
	ldr	r3, .L10+48
	ldr	r2, [r2]
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L2
	bl	rt2x00mmio_register_read
	mov	r3, r0
	ldr	r2, .L10+12
	add	r0, sp, #8
	ldr	r1, [r2]
	mov	r2, r6
	str	r3, [sp, #8]
	bl	rt2x00_set_field32
	ldr	r3, .L10+16
	mov	r2, r6
	ldr	r1, [r3]
	add	r0, sp, #8
	bl	rt2x00_set_field32
	ldr	r3, .L10+24
	mov	r2, r6
	ldr	r1, [r3]
	add	r0, sp, #8
	bl	rt2x00_set_field32
	ldr	r3, .L10+20
	mov	r2, r6
	ldr	r1, [r3]
	add	r0, sp, #8
	bl	rt2x00_set_field32
	ldr	r1, [r5]
	ldr	r2, [sp, #8]
	mov	r0, r4
	bl	rt2x00mmio_register_write
	ldr	r3, .L10+28
	mov	r2, #7
	ldr	r1, [r3]
	mov	r0, r4
	bl	rt2x00mmio_register_write
	ldr	r3, .L10+32
	mov	r2, #24
	ldr	r1, [r3]
	mov	r0, r4
	bl	rt2x00mmio_register_write
	ldr	r3, .L10+36
	mov	r2, #32
	ldr	r1, [r3]
	mov	r0, r4
	bl	rt2x00mmio_register_write
	ldr	r2, .L10+52
	str	r6, [sp]
	ldr	r1, [r2]
	mov	r3, r6
	mov	r0, r4
	mov	r2, #255
	bl	rt61pci_mcu_request
	b	.L1
.L9:
	bl	__stack_chk_fail
.L11:
	.align	2
.L10:
	.word	IEEE80211_CONF_PS
	.word	MAC_CSR11
	.word	.LC0
	.word	MAC_CSR11_DELAY_AFTER_TBCN
	.word	MAC_CSR11_TBCN_BEFORE_WAKEUP
	.word	MAC_CSR11_WAKEUP_LATENCY
	.word	MAC_CSR11_AUTOWAKE
	.word	SOFT_RESET_CSR
	.word	IO_CNTL_CSR
	.word	PCI_USEC_CSR
	.word	MCU_SLEEP
	.word	STATE_AWAKE
	.word	STATE_SLEEP
	.word	MCU_WAKEUP
	.size	rt61pci_config_ps, .-rt61pci_config_ps
	.comm	STATE_SLEEP,4,4
	.comm	STATE_AWAKE,4,4
	.comm	SOFT_RESET_CSR,4,4
	.comm	PCI_USEC_CSR,4,4
	.comm	MCU_WAKEUP,4,4
	.comm	MCU_SLEEP,4,4
	.comm	MAC_CSR11_WAKEUP_LATENCY,4,4
	.comm	MAC_CSR11_TBCN_BEFORE_WAKEUP,4,4
	.comm	MAC_CSR11_DELAY_AFTER_TBCN,4,4
	.comm	MAC_CSR11_AUTOWAKE,4,4
	.comm	MAC_CSR11,4,4
	.comm	IO_CNTL_CSR,4,4
	.comm	IEEE80211_CONF_PS,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
