	.file	"extr_radeon_base.c_radeon_setcolreg.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	radeon_setcolreg, @function
radeon_setcolreg:
.LFB0:
	.cfi_startproc
	endbr64
	cmp	edi, 255
	ja	.L29
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	shr	ecx, 8
	mov	r15d, edi
	shr	esi, 8
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	mov	r14d, edx
	shr	edx, 8
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	mov	r13, r9
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	mov	r12d, esi
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	ebp, ecx
	lea	rcx, [r15+r15*2]
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	ebx, edi
	sub	rsp, 24
	.cfi_def_cfa_offset 80
	mov	rax, QWORD PTR 16[r9]
	lea	rax, [rax+rcx*4]
	mov	ecx, DWORD PTR 24[r9]
	mov	DWORD PTR [rax], esi
	mov	DWORD PTR 4[rax], edx
	mov	DWORD PTR 8[rax], ebp
	test	ecx, ecx
	je	.L30
	cmp	ebx, 15
	ja	.L26
.L13:
	mov	rax, QWORD PTR 8[r13]
	mov	rdx, QWORD PTR [rax]
	mov	eax, DWORD PTR 4[r13]
	cmp	eax, 24
	je	.L14
	jg	.L15
	cmp	eax, 15
	je	.L16
	cmp	eax, 16
	jne	.L26
	mov	edi, ebx
	sal	edi, 11
	jmp	.L27
	.p2align 4,,10
	.p2align 3
.L15:
	cmp	eax, 32
	jne	.L26
	mov	edi, ebx
	sal	edi, 8
	or	ebx, edi
	mov	edi, ebx
	sal	edi, 16
	or	ebx, edi
	mov	DWORD PTR [rdx+r15*4], ebx
	.p2align 4,,10
	.p2align 3
.L26:
	xor	eax, eax
.L1:
	add	rsp, 24
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L30:
	.cfi_restore_state
	mov	edi, 9
	mov	DWORD PTR 12[rsp], edx
	call	radeon_fifo_wait@PLT
	cmp	DWORD PTR 0[r13], 16
	mov	edx, DWORD PTR 12[rsp]
	mov	ecx, ebx
	je	.L31
.L6:
	cmp	DWORD PTR 4[r13], 16
	jne	.L19
	cmp	ebx, 31
	ja	.L26
.L19:
	mov	esi, ecx
.L9:
	mov	edi, DWORD PTR PALETTE_INDEX[rip]
	mov	DWORD PTR 12[rsp], edx
	call	OUTREG@PLT
	mov	edx, DWORD PTR 12[rsp]
	mov	esi, r12d
	mov	edi, DWORD PTR PALETTE_DATA[rip]
	sal	esi, 16
	mov	ecx, esi
	sal	edx, 8
	or	ecx, ebp
	mov	esi, edx
	or	esi, ecx
	call	OUTREG@PLT
	cmp	ebx, 15
	jbe	.L13
	jmp	.L26
	.p2align 4,,10
	.p2align 3
.L29:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	.cfi_restore 6
	.cfi_restore 12
	.cfi_restore 13
	.cfi_restore 14
	.cfi_restore 15
	mov	eax, DWORD PTR EINVAL[rip]
	neg	eax
	ret
	.p2align 4,,10
	.p2align 3
.L16:
	.cfi_def_cfa_offset 80
	.cfi_offset 3, -56
	.cfi_offset 6, -48
	.cfi_offset 12, -40
	.cfi_offset 13, -32
	.cfi_offset 14, -24
	.cfi_offset 15, -16
	mov	edi, ebx
	sal	edi, 10
.L27:
	mov	eax, ebx
	sal	eax, 5
	or	edi, eax
	xor	eax, eax
	or	ebx, edi
	mov	DWORD PTR [rdx+r15*4], ebx
	add	rsp, 24
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L31:
	.cfi_restore_state
	mov	eax, DWORD PTR 4[r13]
	lea	esi, 0[0+rbx*8]
	cmp	eax, 16
	je	.L32
	cmp	eax, 15
	jne	.L9
	cmp	ebx, 31
	jbe	.L9
.L10:
	mov	eax, DWORD PTR EINVAL[rip]
	neg	eax
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L14:
	mov	edi, ebx
	mov	eax, ebx
	sal	eax, 8
	sal	edi, 16
	or	edi, eax
	xor	eax, eax
	or	ebx, edi
	mov	DWORD PTR [rdx+r15*4], ebx
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L32:
	cmp	ebx, 63
	ja	.L10
	mov	edi, DWORD PTR PALETTE_INDEX[rip]
	mov	DWORD PTR 12[rsp], esi
	sar	esi
	call	OUTREG@PLT
	mov	eax, ebx
	mov	esi, r14d
	mov	edi, DWORD PTR PALETTE_DATA[rip]
	shr	eax
	xor	sil, sil
	lea	rdx, [rax+rax*2]
	mov	rax, QWORD PTR 16[r13]
	lea	rax, [rax+rdx*4]
	mov	r14d, DWORD PTR [rax]
	or	esi, DWORD PTR 8[rax]
	sal	r14d, 16
	or	esi, r14d
	call	OUTREG@PLT
	mov	rdx, QWORD PTR 16[r13]
	lea	eax, [rbx+rbx]
	mov	ecx, DWORD PTR 12[rsp]
	lea	rax, [rax+rax*2]
	lea	rax, [rdx+rax*4]
	mov	edx, DWORD PTR 4[rax]
	jmp	.L6
	.cfi_endproc
.LFE0:
	.size	radeon_setcolreg, .-radeon_setcolreg
	.comm	PALETTE_INDEX,4,4
	.comm	PALETTE_DATA,4,4
	.comm	EINVAL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_radeon_base.c_radeon_setcolreg.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	radeon_setcolreg, %function
radeon_setcolreg:
	@ args = 8, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	cmp	r0, #255
	ldr	r8, [sp, #44]
	bhi	.L10
	mov	r4, r0
	mov	r7, r2
	ldr	r0, [r8, #12]
	ldr	r2, [r8, #16]
	add	r9, r4, r4, lsl #1
	lsr	r6, r1, #8
	lsr	r5, r3, #8
	add	r1, r0, r9, lsl #2
	lsr	r10, r7, #8
	cmp	r2, #0
	str	r6, [r0, r9, lsl #2]
	str	r5, [r1, #8]
	str	r10, [r1, #4]
	beq	.L24
	cmp	r4, #15
	bhi	.L18
.L12:
	ldr	r3, [r8, #4]
	ldr	r2, [r8, #8]
	sub	r3, r3, #15
	ldr	r2, [r2]
	cmp	r3, #17
	ldrls	pc, [pc, r3, asl #2]
	b	.L18
.L14:
	.word	.L17
	.word	.L16
	.word	.L18
	.word	.L18
	.word	.L18
	.word	.L18
	.word	.L18
	.word	.L18
	.word	.L18
	.word	.L15
	.word	.L18
	.word	.L18
	.word	.L18
	.word	.L18
	.word	.L18
	.word	.L18
	.word	.L18
	.word	.L13
.L18:
	mov	r0, #0
	pop	{r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L24:
	mov	r0, #9
	bl	radeon_fifo_wait
	ldr	r3, [r8]
	cmp	r3, #16
	movne	fp, r4
	beq	.L25
.L6:
	cmp	r4, #31
	movhi	r3, #0
	movls	r3, #1
	ldr	r2, [r8, #4]
	cmp	r2, #16
	orrne	r3, r3, #1
	cmp	r3, #0
	beq	.L18
.L9:
	ldr	r3, .L27
	mov	r1, fp
	ldr	r0, [r3]
	bl	OUTREG
	ldr	r2, .L27+4
	orr	r1, r5, r6, lsl #16
	ldr	r0, [r2]
	orr	r1, r1, r10, lsl #8
	bl	OUTREG
	cmp	r4, #15
	bls	.L12
	b	.L18
.L25:
	ldr	r3, [r8, #4]
	lsl	fp, r4, #3
	cmp	r3, #16
	beq	.L26
	cmp	r3, #15
	bne	.L9
	cmp	r4, #31
	bls	.L9
.L10:
	ldr	r3, .L27+8
	ldr	r0, [r3]
	rsb	r0, r0, #0
	pop	{r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L13:
	orr	r3, r4, r4, lsl #8
	orr	r3, r3, r3, lsl #16
	mov	r0, #0
	str	r3, [r2, r4, lsl #2]
	pop	{r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L17:
	lsl	r3, r4, #5
	orr	r3, r3, r4, lsl #10
	orr	r3, r3, r4
	mov	r0, #0
	str	r3, [r2, r4, lsl #2]
	pop	{r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L15:
	lsl	r3, r4, #8
	orr	r3, r3, r4, lsl #16
	orr	r3, r3, r4
	mov	r0, #0
	str	r3, [r2, r4, lsl #2]
	pop	{r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L16:
	lsl	r3, r4, #5
	orr	r3, r3, r4, lsl #11
	orr	r3, r3, r4
	mov	r0, #0
	str	r3, [r2, r4, lsl #2]
	pop	{r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L26:
	cmp	r4, #63
	bhi	.L10
	ldr	r3, .L27
	asr	r1, fp, #1
	ldr	r0, [r3]
	bl	OUTREG
	ldr	r1, [r8, #12]
	bic	r2, r4, #1
	add	r2, r2, r4, lsr #1
	add	r3, r1, r2, lsl #2
	ldr	r0, [r3, #8]
	ldr	r1, [r1, r2, lsl #2]
	bic	r3, r7, #255
	ldr	r2, .L27+4
	orr	r3, r3, r0
	orr	r1, r3, r1, lsl #16
	ldr	r0, [r2]
	bl	OUTREG
	ldr	r3, [r8, #12]
	add	r9, r3, r9, lsl #3
	ldr	r10, [r9, #4]
	b	.L6
.L28:
	.align	2
.L27:
	.word	PALETTE_INDEX
	.word	PALETTE_DATA
	.word	EINVAL
	.size	radeon_setcolreg, .-radeon_setcolreg
	.comm	PALETTE_INDEX,4,4
	.comm	PALETTE_DATA,4,4
	.comm	EINVAL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
