	.file	"extr_vcn_v1_0.c_vcn_v1_0_start_dpg_mode.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	vcn_v1_0_start_dpg_mode, @function
vcn_v1_0_start_dpg_mode:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	mov	r15d, 3
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	mov	r14d, 4
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	mov	r13d, 2
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	mov	r12d, 8
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	rbx, rdi
	sub	rsp, 8
	.cfi_def_cfa_offset 64
	mov	rbp, QWORD PTR [rdi]
	call	vcn_1_0_enable_static_power_gating@PLT
	mov	edx, DWORD PTR mmUVD_POWER_STATUS[rip]
	mov	edi, DWORD PTR UVD[rip]
	xor	esi, esi
	call	RREG32_SOC15@PLT
	mov	edx, DWORD PTR mmUVD_POWER_STATUS[rip]
	mov	ecx, DWORD PTR UVD_POWER_STATUS__UVD_PG_MODE_MASK[rip]
	xor	esi, esi
	or	ecx, DWORD PTR UVD_POWER_STATUS__UVD_PG_EN_MASK[rip]
	mov	edi, DWORD PTR UVD[rip]
	or	ecx, eax
	call	WREG32_SOC15@PLT
	xor	esi, esi
	mov	rdi, rbx
	call	vcn_v1_0_clock_gating_dpg_mode@PLT
	mov	ecx, DWORD PTR UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT[rip]
	xor	r9d, r9d
	xor	esi, esi
	mov	eax, 255
	mov	edx, DWORD PTR mmUVD_VCPU_CNTL[rip]
	mov	edi, DWORD PTR UVD[rip]
	mov	r8d, -1
	sal	eax, cl
	mov	ecx, DWORD PTR UVD_VCPU_CNTL__CLK_EN_MASK[rip]
	or	ecx, DWORD PTR UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK[rip]
	or	ecx, eax
	call	WREG32_SOC15_DPG_MODE@PLT
	mov	r8d, DWORD PTR UVD_MASTINT_EN__VCPU_EN_MASK[rip]
	xor	ecx, ecx
	xor	esi, esi
	mov	edx, DWORD PTR mmUVD_MASTINT_EN[rip]
	mov	edi, DWORD PTR UVD[rip]
	xor	r9d, r9d
	call	WREG32_SOC15_DPG_MODE@PLT
	mov	ecx, DWORD PTR UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT[rip]
	mov	eax, r12d
	xor	esi, esi
	mov	edx, DWORD PTR UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK[rip]
	or	edx, DWORD PTR UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK[rip]
	xor	r9d, r9d
	mov	r8d, -1
	sal	eax, cl
	mov	edi, DWORD PTR UVD[rip]
	mov	ecx, eax
	or	ecx, edx
	mov	edx, DWORD PTR mmUVD_LMI_CTRL[rip]
	or	ecx, DWORD PTR UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK[rip]
	or	ecx, DWORD PTR UVD_LMI_CTRL__REQ_MODE_MASK[rip]
	or	ecx, DWORD PTR UVD_LMI_CTRL__CRC_RESET_MASK[rip]
	or	ecx, DWORD PTR UVD_LMI_CTRL__MASK_MC_URGENT_MASK[rip]
	or	ecx, 1048576
	call	WREG32_SOC15_DPG_MODE@PLT
	mov	edx, DWORD PTR mmUVD_LMI_SWAP_CNTL[rip]
	xor	r9d, r9d
	xor	ecx, ecx
	mov	edi, DWORD PTR UVD[rip]
	xor	esi, esi
	mov	r8d, -1
	call	WREG32_SOC15_DPG_MODE@PLT
	mov	ecx, DWORD PTR UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT[rip]
	mov	eax, r13d
	xor	esi, esi
	mov	edx, DWORD PTR mmUVD_MPC_CNTL[rip]
	mov	edi, DWORD PTR UVD[rip]
	xor	r9d, r9d
	mov	r8d, -1
	sal	eax, cl
	mov	ecx, eax
	call	WREG32_SOC15_DPG_MODE@PLT
	mov	ecx, DWORD PTR UVD_MPC_SET_MUXA0__VARA_2__SHIFT[rip]
	mov	eax, r13d
	xor	esi, esi
	mov	edx, DWORD PTR UVD_MPC_SET_MUXA0__VARA_1__SHIFT[rip]
	mov	edi, DWORD PTR UVD[rip]
	xor	r9d, r9d
	mov	r8d, -1
	sal	eax, cl
	mov	ecx, DWORD PTR UVD_MPC_SET_MUXA0__VARA_3__SHIFT[rip]
	bts	eax, edx
	mov	edx, r15d
	sal	edx, cl
	mov	ecx, DWORD PTR UVD_MPC_SET_MUXA0__VARA_4__SHIFT[rip]
	or	eax, edx
	mov	edx, r14d
	sal	edx, cl
	mov	ecx, edx
	mov	edx, DWORD PTR mmUVD_MPC_SET_MUXA0[rip]
	or	ecx, eax
	call	WREG32_SOC15_DPG_MODE@PLT
	mov	ecx, DWORD PTR UVD_MPC_SET_MUXB0__VARB_2__SHIFT[rip]
	mov	eax, r13d
	xor	esi, esi
	mov	edx, DWORD PTR UVD_MPC_SET_MUXB0__VARB_1__SHIFT[rip]
	mov	edi, DWORD PTR UVD[rip]
	xor	r9d, r9d
	mov	r8d, -1
	sal	eax, cl
	mov	ecx, DWORD PTR UVD_MPC_SET_MUXB0__VARB_3__SHIFT[rip]
	bts	eax, edx
	mov	edx, DWORD PTR mmUVD_MPC_SET_MUXB0[rip]
	sal	r15d, cl
	mov	ecx, DWORD PTR UVD_MPC_SET_MUXB0__VARB_4__SHIFT[rip]
	or	eax, r15d
	sal	r14d, cl
	mov	ecx, r14d
	or	ecx, eax
	call	WREG32_SOC15_DPG_MODE@PLT
	mov	ecx, DWORD PTR UVD_MPC_SET_MUX__SET_2__SHIFT[rip]
	xor	r9d, r9d
	xor	esi, esi
	mov	eax, DWORD PTR UVD_MPC_SET_MUX__SET_1__SHIFT[rip]
	mov	edx, DWORD PTR mmUVD_MPC_SET_MUX[rip]
	mov	r8d, -1
	sal	r13d, cl
	mov	edi, DWORD PTR UVD[rip]
	mov	ecx, r13d
	bts	ecx, eax
	call	WREG32_SOC15_DPG_MODE@PLT
	mov	rdi, rbx
	call	vcn_v1_0_mc_resume_dpg_mode@PLT
	mov	edx, DWORD PTR mmUVD_REG_XX_MASK[rip]
	xor	r9d, r9d
	mov	edi, DWORD PTR UVD[rip]
	xor	esi, esi
	mov	r8d, -1
	mov	ecx, 16
	call	WREG32_SOC15_DPG_MODE@PLT
	mov	edx, DWORD PTR mmUVD_RBC_XX_IB_REG_CHECK[rip]
	xor	r9d, r9d
	xor	esi, esi
	mov	edi, DWORD PTR UVD[rip]
	mov	r8d, -1
	mov	ecx, 3
	call	WREG32_SOC15_DPG_MODE@PLT
	mov	edx, DWORD PTR mmUVD_SOFT_RESET[rip]
	xor	r9d, r9d
	xor	ecx, ecx
	mov	edi, DWORD PTR UVD[rip]
	xor	esi, esi
	mov	r8d, -1
	call	WREG32_SOC15_DPG_MODE@PLT
	mov	ecx, DWORD PTR UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT[rip]
	xor	r9d, r9d
	xor	esi, esi
	mov	eax, 31
	mov	edx, DWORD PTR mmUVD_LMI_CTRL2[rip]
	mov	edi, DWORD PTR UVD[rip]
	mov	r8d, -1
	sal	eax, cl
	mov	ecx, eax
	call	WREG32_SOC15_DPG_MODE@PLT
	mov	ecx, DWORD PTR UVD_MASTINT_EN__VCPU_EN_MASK[rip]
	xor	r9d, r9d
	xor	esi, esi
	mov	edx, DWORD PTR mmUVD_MASTINT_EN[rip]
	mov	edi, DWORD PTR UVD[rip]
	mov	r8d, ecx
	call	WREG32_SOC15_DPG_MODE@PLT
	mov	rdi, rbx
	mov	esi, 1
	call	vcn_v1_0_clock_gating_dpg_mode@PLT
	mov	ecx, DWORD PTR UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT[rip]
	xor	esi, esi
	mov	eax, DWORD PTR UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK[rip]
	or	eax, DWORD PTR UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK[rip]
	mov	edx, DWORD PTR mmUVD_LMI_CTRL[rip]
	mov	r9d, 1
	mov	r8d, -1
	sal	r12d, cl
	mov	edi, DWORD PTR UVD[rip]
	mov	ecx, r12d
	or	ecx, eax
	or	ecx, DWORD PTR UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK[rip]
	or	ecx, DWORD PTR UVD_LMI_CTRL__REQ_MODE_MASK[rip]
	or	ecx, DWORD PTR UVD_LMI_CTRL__CRC_RESET_MASK[rip]
	or	ecx, DWORD PTR UVD_LMI_CTRL__MASK_MC_URGENT_MASK[rip]
	or	ecx, 1048576
	call	WREG32_SOC15_DPG_MODE@PLT
	mov	r12d, DWORD PTR 8[rbx]
	mov	edx, DWORD PTR mmUVD_JPEG_ADDR_CONFIG[rip]
	xor	esi, esi
	mov	edi, DWORD PTR UVD[rip]
	mov	r9d, 1
	mov	r8d, -1
	mov	ecx, r12d
	call	WREG32_SOC15_DPG_MODE@PLT
	mov	edx, DWORD PTR mmUVD_JPEG_UV_ADDR_CONFIG[rip]
	mov	ecx, r12d
	xor	esi, esi
	mov	edi, DWORD PTR UVD[rip]
	mov	r9d, 1
	mov	r8d, -1
	call	WREG32_SOC15_DPG_MODE@PLT
	mov	ecx, DWORD PTR UVD_SYS_INT_EN__UVD_JRBC_EN_MASK[rip]
	xor	esi, esi
	mov	edx, DWORD PTR mmUVD_SYS_INT_EN[rip]
	mov	edi, DWORD PTR UVD[rip]
	mov	r9d, 1
	mov	r8d, -1
	call	WREG32_SOC15_DPG_MODE@PLT
	mov	edi, DWORD PTR 56[rbp]
	call	order_base_2@PLT
	mov	edx, DWORD PTR RB_BUFSZ[rip]
	mov	esi, DWORD PTR UVD_RBC_RB_CNTL[rip]
	xor	edi, edi
	mov	ecx, eax
	call	REG_SET_FIELD@PLT
	mov	edx, DWORD PTR RB_BLKSZ[rip]
	mov	esi, DWORD PTR UVD_RBC_RB_CNTL[rip]
	mov	ecx, 1
	mov	edi, eax
	call	REG_SET_FIELD@PLT
	mov	edx, DWORD PTR RB_NO_FETCH[rip]
	mov	esi, DWORD PTR UVD_RBC_RB_CNTL[rip]
	mov	ecx, 1
	mov	edi, eax
	call	REG_SET_FIELD@PLT
	mov	edx, DWORD PTR RB_NO_UPDATE[rip]
	mov	esi, DWORD PTR UVD_RBC_RB_CNTL[rip]
	mov	ecx, 1
	mov	edi, eax
	call	REG_SET_FIELD@PLT
	mov	edx, DWORD PTR RB_RPTR_WR_EN[rip]
	mov	esi, DWORD PTR UVD_RBC_RB_CNTL[rip]
	mov	ecx, 1
	mov	edi, eax
	call	REG_SET_FIELD@PLT
	mov	edx, DWORD PTR mmUVD_RBC_RB_CNTL[rip]
	mov	edi, DWORD PTR UVD[rip]
	xor	esi, esi
	mov	ecx, eax
	call	WREG32_SOC15@PLT
	mov	edx, DWORD PTR mmUVD_RBC_RB_WPTR_CNTL[rip]
	xor	ecx, ecx
	xor	esi, esi
	mov	edi, DWORD PTR UVD[rip]
	call	WREG32_SOC15@PLT
	mov	rdi, QWORD PTR 48[rbp]
	call	upper_32_bits@PLT
	mov	edx, DWORD PTR mmUVD_RBC_RB_RPTR_ADDR[rip]
	mov	edi, DWORD PTR UVD[rip]
	xor	esi, esi
	sar	eax, 2
	mov	ecx, eax
	call	WREG32_SOC15@PLT
	mov	rdi, QWORD PTR 48[rbp]
	call	lower_32_bits@PLT
	mov	edx, DWORD PTR mmUVD_LMI_RBC_RB_64BIT_BAR_LOW[rip]
	mov	edi, DWORD PTR UVD[rip]
	xor	esi, esi
	mov	ecx, eax
	call	WREG32_SOC15@PLT
	mov	rdi, QWORD PTR 48[rbp]
	call	upper_32_bits@PLT
	mov	edx, DWORD PTR mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH[rip]
	mov	edi, DWORD PTR UVD[rip]
	xor	esi, esi
	mov	ecx, eax
	call	WREG32_SOC15@PLT
	mov	edx, DWORD PTR mmUVD_RBC_RB_RPTR[rip]
	xor	ecx, ecx
	xor	esi, esi
	mov	edi, DWORD PTR UVD[rip]
	call	WREG32_SOC15@PLT
	mov	edx, DWORD PTR mmUVD_SCRATCH2[rip]
	xor	ecx, ecx
	xor	esi, esi
	mov	edi, DWORD PTR UVD[rip]
	call	WREG32_SOC15@PLT
	mov	edx, DWORD PTR mmUVD_RBC_RB_RPTR[rip]
	mov	edi, DWORD PTR UVD[rip]
	xor	esi, esi
	call	RREG32_SOC15@PLT
	mov	QWORD PTR 40[rbp], rax
	mov	rdi, rax
	call	lower_32_bits@PLT
	mov	edx, DWORD PTR mmUVD_RBC_RB_WPTR[rip]
	mov	edi, DWORD PTR UVD[rip]
	xor	esi, esi
	mov	ecx, eax
	call	WREG32_SOC15@PLT
	mov	r12d, DWORD PTR UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK[rip]
	mov	edx, DWORD PTR mmUVD_RBC_RB_CNTL[rip]
	xor	esi, esi
	mov	edi, DWORD PTR UVD[rip]
	not	r12d
	call	SOC15_REG_OFFSET@PLT
	mov	edx, r12d
	xor	esi, esi
	mov	edi, eax
	call	WREG32_P@PLT
	mov	rbp, QWORD PTR [rbx]
	mov	edx, DWORD PTR mmUVD_JRBC_RB_WPTR[rip]
	xor	esi, esi
	mov	edi, DWORD PTR UVD[rip]
	call	RREG32_SOC15@PLT
	mov	esi, DWORD PTR 0[rbp]
	imul	esi, DWORD PTR amdgpu_sched_hw_submission[rip]
	mov	rdi, rbp
	mov	QWORD PTR 8[rbp], rax
	movsx	rsi, esi
	add	rsi, rax
	call	vcn_v1_0_jpeg_ring_set_patch_ring@PLT
	add	rsp, 8
	.cfi_def_cfa_offset 56
	xor	eax, eax
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE0:
	.size	vcn_v1_0_start_dpg_mode, .-vcn_v1_0_start_dpg_mode
	.comm	mmUVD_VCPU_CNTL,4,4
	.comm	mmUVD_SYS_INT_EN,4,4
	.comm	mmUVD_SOFT_RESET,4,4
	.comm	mmUVD_SCRATCH2,4,4
	.comm	mmUVD_REG_XX_MASK,4,4
	.comm	mmUVD_RBC_XX_IB_REG_CHECK,4,4
	.comm	mmUVD_RBC_RB_WPTR_CNTL,4,4
	.comm	mmUVD_RBC_RB_WPTR,4,4
	.comm	mmUVD_RBC_RB_RPTR_ADDR,4,4
	.comm	mmUVD_RBC_RB_RPTR,4,4
	.comm	mmUVD_RBC_RB_CNTL,4,4
	.comm	mmUVD_POWER_STATUS,4,4
	.comm	mmUVD_MPC_SET_MUXB0,4,4
	.comm	mmUVD_MPC_SET_MUXA0,4,4
	.comm	mmUVD_MPC_SET_MUX,4,4
	.comm	mmUVD_MPC_CNTL,4,4
	.comm	mmUVD_MASTINT_EN,4,4
	.comm	mmUVD_LMI_SWAP_CNTL,4,4
	.comm	mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,4,4
	.comm	mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,4,4
	.comm	mmUVD_LMI_CTRL2,4,4
	.comm	mmUVD_LMI_CTRL,4,4
	.comm	mmUVD_JRBC_RB_WPTR,4,4
	.comm	mmUVD_JPEG_UV_ADDR_CONFIG,4,4
	.comm	mmUVD_JPEG_ADDR_CONFIG,4,4
	.comm	amdgpu_sched_hw_submission,4,4
	.comm	UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT,4,4
	.comm	UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK,4,4
	.comm	UVD_VCPU_CNTL__CLK_EN_MASK,4,4
	.comm	UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,4,4
	.comm	UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK,4,4
	.comm	UVD_RBC_RB_CNTL,4,4
	.comm	UVD_POWER_STATUS__UVD_PG_MODE_MASK,4,4
	.comm	UVD_POWER_STATUS__UVD_PG_EN_MASK,4,4
	.comm	UVD_MPC_SET_MUX__SET_2__SHIFT,4,4
	.comm	UVD_MPC_SET_MUX__SET_1__SHIFT,4,4
	.comm	UVD_MPC_SET_MUX__SET_0__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXB0__VARB_4__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXB0__VARB_3__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXB0__VARB_2__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXB0__VARB_1__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXA0__VARA_4__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXA0__VARA_3__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXA0__VARA_2__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXA0__VARA_1__SHIFT,4,4
	.comm	UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT,4,4
	.comm	UVD_MASTINT_EN__VCPU_EN_MASK,4,4
	.comm	UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT,4,4
	.comm	UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK,4,4
	.comm	UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK,4,4
	.comm	UVD_LMI_CTRL__REQ_MODE_MASK,4,4
	.comm	UVD_LMI_CTRL__MASK_MC_URGENT_MASK,4,4
	.comm	UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK,4,4
	.comm	UVD_LMI_CTRL__CRC_RESET_MASK,4,4
	.comm	UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,4,4
	.comm	UVD,4,4
	.comm	RB_RPTR_WR_EN,4,4
	.comm	RB_NO_UPDATE,4,4
	.comm	RB_NO_FETCH,4,4
	.comm	RB_BUFSZ,4,4
	.comm	RB_BLKSZ,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_vcn_v1_0.c_vcn_v1_0_start_dpg_mode.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	vcn_v1_0_start_dpg_mode, %function
vcn_v1_0_start_dpg_mode:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r5, .L4
	ldr	r4, .L4+4
	sub	sp, sp, #12
	mov	r8, r0
	ldr	r10, [r0]
	bl	vcn_1_0_enable_static_power_gating
	ldr	r2, [r4]
	mov	r1, #0
	ldr	r0, [r5]
	bl	RREG32_SOC15
	ldr	r2, .L4+8
	ldr	r3, .L4+12
	ldr	r1, [r2]
	ldr	r3, [r3]
	ldr	r2, [r4]
	orr	r3, r1, r3
	orr	r3, r3, r0
	mov	r1, #0
	ldr	r0, [r5]
	mov	r4, #0
	mvn	r6, #0
	bl	WREG32_SOC15
	mov	r0, r8
	mov	r1, #0
	bl	vcn_v1_0_clock_gating_dpg_mode
	mov	r3, #255
	ldr	r2, .L4+16
	ldr	r0, .L4+20
	ldr	r1, .L4+24
	ldr	r0, [r0]
	ldr	r2, [r2]
	ldr	r1, [r1]
	ldr	ip, .L4+28
	orr	r2, r2, r0
	ldr	r0, [r5]
	str	r6, [sp]
	str	r4, [sp, #4]
	orr	r3, r2, r3, lsl r1
	ldr	r2, [ip]
	mov	r1, r4
	bl	WREG32_SOC15_DPG_MODE
	ldr	r3, .L4+32
	ldr	r2, .L4+36
	ldr	r3, [r3]
	mov	r1, r4
	stm	sp, {r3, r4}
	mov	r3, r4
	ldr	r0, [r5]
	ldr	r2, [r2]
	bl	WREG32_SOC15_DPG_MODE
	ldr	r1, .L4+40
	ldr	r0, .L4+44
	ldr	r3, [r1]
	ldr	r1, [r0]
	mov	r0, #8
	mov	r9, #2
	mov	r7, #1
	mov	fp, #3
	ldr	ip, .L4+48
	ldr	lr, .L4+52
	ldr	r2, [ip]
	orr	r3, r3, r1
	ldr	r1, [lr]
	orr	r3, r3, r0, lsl r2
	ldr	r2, .L4+56
	orr	r3, r3, r1
	ldr	r1, .L4+60
	ldr	r2, [r2]
	ldr	ip, .L4+64
	ldr	r1, [r1]
	orr	r3, r3, r2
	ldr	r2, [ip]
	ldr	lr, .L4+68
	orr	r3, r3, r1
	str	r6, [sp]
	str	r4, [sp, #4]
	orr	r3, r3, r2
	mov	r1, r4
	ldr	r2, [lr]
	ldr	r0, [r5]
	orr	r3, r3, #1048576
	bl	WREG32_SOC15_DPG_MODE
	ldr	r2, .L4+72
	str	r6, [sp]
	str	r4, [sp, #4]
	mov	r3, r4
	mov	r1, r4
	ldr	r0, [r5]
	ldr	r2, [r2]
	bl	WREG32_SOC15_DPG_MODE
	ldr	r3, .L4+76
	ldr	r2, .L4+80
	ldr	r3, [r3]
	str	r6, [sp]
	str	r4, [sp, #4]
	mov	r1, r4
	lsl	r3, r9, r3
	ldr	r0, [r5]
	ldr	r2, [r2]
	bl	WREG32_SOC15_DPG_MODE
	ldr	r3, .L4+84
	ldr	r2, .L4+88
	ldr	r3, [r3]
	ldr	r0, .L4+92
	ldr	r2, [r2]
	ldr	r0, [r0]
	lsl	r3, r9, r3
	orr	r2, r3, r7, lsl r2
	orr	r3, r2, fp, lsl r0
	mov	r2, #4
	ldr	r1, .L4+96
	ldr	ip, .L4+100
	ldr	r1, [r1]
	str	r6, [sp]
	str	r4, [sp, #4]
	orr	r3, r3, r2, lsl r1
	ldr	r0, [r5]
	mov	r1, r4
	ldr	r2, [ip]
	bl	WREG32_SOC15_DPG_MODE
	ldr	r3, .L4+104
	ldr	r2, .L4+108
	ldr	r3, [r3]
	ldr	r0, .L4+112
	ldr	r2, [r2]
	ldr	r0, [r0]
	lsl	r3, r9, r3
	orr	r2, r3, r7, lsl r2
	orr	r3, r2, fp, lsl r0
	mov	r2, #4
	ldr	r1, .L4+116
	ldr	ip, .L4+120
	ldr	r1, [r1]
	str	r6, [sp]
	str	r4, [sp, #4]
	orr	r3, r3, r2, lsl r1
	ldr	r0, [r5]
	ldr	r2, [ip]
	mov	r1, r4
	bl	WREG32_SOC15_DPG_MODE
	ldr	r2, .L4+124
	ldr	r3, .L4+128
	ldr	r1, [r2]
	ldr	r3, [r3]
	ldr	r2, .L4+132
	str	r6, [sp]
	str	r4, [sp, #4]
	lsl	r9, r9, r1
	orr	r3, r9, r7, lsl r3
	mov	r1, r4
	ldr	r2, [r2]
	ldr	r0, [r5]
	bl	WREG32_SOC15_DPG_MODE
	mov	r0, r8
	bl	vcn_v1_0_mc_resume_dpg_mode
	ldr	r3, .L4+136
	str	r6, [sp]
	str	r4, [sp, #4]
	mov	r1, r4
	ldr	r2, [r3]
	ldr	r0, [r5]
	mov	r3, #16
	bl	WREG32_SOC15_DPG_MODE
	ldr	r2, .L4+140
	str	r6, [sp]
	str	r4, [sp, #4]
	mov	r3, fp
	mov	r1, r4
	ldr	r0, [r5]
	ldr	r2, [r2]
	bl	WREG32_SOC15_DPG_MODE
	ldr	r2, .L4+144
	str	r6, [sp]
	str	r4, [sp, #4]
	mov	r3, r4
	mov	r1, r4
	ldr	r0, [r5]
	ldr	r2, [r2]
	bl	WREG32_SOC15_DPG_MODE
	mov	r1, #31
	ldr	r3, .L4+148
	ldr	r2, .L4+152
	ldr	r3, [r3]
	str	r6, [sp]
	str	r4, [sp, #4]
	lsl	r3, r1, r3
	ldr	r0, [r5]
	mov	r1, r4
	ldr	r2, [r2]
	bl	WREG32_SOC15_DPG_MODE
	ldr	r3, .L4+32
	ldr	r2, .L4+36
	ldr	r3, [r3]
	mov	r1, r4
	stm	sp, {r3, r4}
	ldr	r2, [r2]
	ldr	r0, [r5]
	bl	WREG32_SOC15_DPG_MODE
	mov	r1, r7
	mov	r0, r8
	bl	vcn_v1_0_clock_gating_dpg_mode
	ldr	r1, .L4+40
	ldr	r0, .L4+44
	ldr	r3, [r1]
	ldr	r1, [r0]
	mov	r0, #8
	ldr	ip, .L4+48
	ldr	lr, .L4+52
	ldr	r2, [ip]
	orr	r3, r3, r1
	ldr	r1, [lr]
	orr	r3, r3, r0, lsl r2
	ldr	r2, .L4+56
	orr	r3, r3, r1
	ldr	r1, .L4+60
	ldr	ip, .L4+64
	ldr	r2, [r2]
	ldr	r1, [r1]
	orr	r3, r3, r2
	ldr	r2, [ip]
	stm	sp, {r6, r7}
	ldr	lr, .L4+68
	orr	r3, r3, r1
	orr	r3, r3, r2
	mov	r1, r4
	ldr	r2, [lr]
	ldr	r0, [r5]
	orr	r3, r3, #1048576
	bl	WREG32_SOC15_DPG_MODE
	ldr	r9, [r8, #4]
	stm	sp, {r6, r7}
	ldr	r2, .L4+156
	mov	r3, r9
	mov	r1, r4
	ldr	r0, [r5]
	ldr	r2, [r2]
	bl	WREG32_SOC15_DPG_MODE
	stm	sp, {r6, r7}
	ldr	r2, .L4+160
	mov	r3, r9
	mov	r1, r4
	ldr	r0, [r5]
	ldr	r2, [r2]
	bl	WREG32_SOC15_DPG_MODE
	stm	sp, {r6, r7}
	ldr	r3, .L4+164
	ldr	r2, .L4+168
	mov	r1, r4
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	r0, [r5]
	bl	WREG32_SOC15_DPG_MODE
	ldr	r0, [r10, #28]
	bl	order_base_2
	ldr	r6, .L4+172
	ldr	r2, .L4+176
	mov	r3, r0
	ldr	r1, [r6]
	mov	r0, r4
	ldr	r2, [r2]
	bl	REG_SET_FIELD
	ldr	r2, .L4+180
	mov	r3, r7
	ldr	r1, [r6]
	ldr	r2, [r2]
	bl	REG_SET_FIELD
	ldr	r2, .L4+184
	mov	r3, r7
	ldr	r1, [r6]
	ldr	r2, [r2]
	bl	REG_SET_FIELD
	ldr	r2, .L4+188
	mov	r3, r7
	ldr	r1, [r6]
	ldr	r2, [r2]
	bl	REG_SET_FIELD
	ldr	r2, .L4+192
	mov	r3, r7
	ldr	r1, [r6]
	ldr	r2, [r2]
	bl	REG_SET_FIELD
	ldr	r6, .L4+196
	mov	r3, r0
	mov	r1, r4
	ldr	r2, [r6]
	ldr	r0, [r5]
	bl	WREG32_SOC15
	ldr	r2, .L4+200
	mov	r1, r4
	mov	r3, r4
	ldr	r2, [r2]
	ldr	r0, [r5]
	bl	WREG32_SOC15
	ldr	r3, .L4+204
	ldr	r0, [r10, #24]
	ldr	r7, [r5]
	ldr	r9, [r3]
	bl	upper_32_bits
	mov	r3, r0
	mov	r2, r9
	mov	r1, r4
	mov	r0, r7
	asr	r3, r3, #2
	bl	WREG32_SOC15
	ldr	r3, .L4+208
	ldr	r0, [r10, #24]
	ldr	r7, [r5]
	ldr	r9, [r3]
	bl	lower_32_bits
	mov	r2, r9
	mov	r1, r4
	mov	r3, r0
	mov	r0, r7
	bl	WREG32_SOC15
	ldr	r3, .L4+212
	ldr	r0, [r10, #24]
	ldr	r9, [r5]
	ldr	fp, [r3]
	bl	upper_32_bits
	ldr	r7, .L4+216
	mov	r3, r0
	mov	r2, fp
	mov	r1, r4
	mov	r0, r9
	bl	WREG32_SOC15
	mov	r3, r4
	mov	r1, r4
	ldr	r2, [r7]
	ldr	r0, [r5]
	bl	WREG32_SOC15
	ldr	r2, .L4+220
	mov	r3, r4
	mov	r1, r4
	ldr	r0, [r5]
	ldr	r2, [r2]
	bl	WREG32_SOC15
	mov	r1, r4
	ldr	r2, [r7]
	ldr	r0, [r5]
	bl	RREG32_SOC15
	ldr	r3, .L4+224
	str	r0, [r10, #20]
	ldr	r7, [r5]
	ldr	r9, [r3]
	bl	lower_32_bits
	mov	r2, r9
	mov	r3, r0
	mov	r1, r4
	mov	r0, r7
	bl	WREG32_SOC15
	mov	r1, r4
	ldr	r2, [r6]
	ldr	r0, [r5]
	bl	SOC15_REG_OFFSET
	ldr	r3, .L4+228
	mov	r1, r4
	ldr	r2, [r3]
	mvn	r2, r2
	bl	WREG32_P
	ldr	r3, .L4+232
	mov	r1, r4
	ldr	r2, [r3]
	ldr	r0, [r5]
	ldr	r5, [r8]
	bl	RREG32_SOC15
	mov	r3, r0
	ldr	r1, .L4+236
	ldr	r2, [r5]
	ldr	r1, [r1]
	str	r0, [r5, #4]
	mla	r1, r2, r1, r3
	mov	r0, r5
	bl	vcn_v1_0_jpeg_ring_set_patch_ring
	mov	r0, r4
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L5:
	.align	2
.L4:
	.word	UVD
	.word	mmUVD_POWER_STATUS
	.word	UVD_POWER_STATUS__UVD_PG_MODE_MASK
	.word	UVD_POWER_STATUS__UVD_PG_EN_MASK
	.word	UVD_VCPU_CNTL__CLK_EN_MASK
	.word	UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK
	.word	UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT
	.word	mmUVD_VCPU_CNTL
	.word	UVD_MASTINT_EN__VCPU_EN_MASK
	.word	mmUVD_MASTINT_EN
	.word	UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
	.word	UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
	.word	UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT
	.word	UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
	.word	UVD_LMI_CTRL__REQ_MODE_MASK
	.word	UVD_LMI_CTRL__CRC_RESET_MASK
	.word	UVD_LMI_CTRL__MASK_MC_URGENT_MASK
	.word	mmUVD_LMI_CTRL
	.word	mmUVD_LMI_SWAP_CNTL
	.word	UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT
	.word	mmUVD_MPC_CNTL
	.word	UVD_MPC_SET_MUXA0__VARA_2__SHIFT
	.word	UVD_MPC_SET_MUXA0__VARA_1__SHIFT
	.word	UVD_MPC_SET_MUXA0__VARA_3__SHIFT
	.word	UVD_MPC_SET_MUXA0__VARA_4__SHIFT
	.word	mmUVD_MPC_SET_MUXA0
	.word	UVD_MPC_SET_MUXB0__VARB_2__SHIFT
	.word	UVD_MPC_SET_MUXB0__VARB_1__SHIFT
	.word	UVD_MPC_SET_MUXB0__VARB_3__SHIFT
	.word	UVD_MPC_SET_MUXB0__VARB_4__SHIFT
	.word	mmUVD_MPC_SET_MUXB0
	.word	UVD_MPC_SET_MUX__SET_2__SHIFT
	.word	UVD_MPC_SET_MUX__SET_1__SHIFT
	.word	mmUVD_MPC_SET_MUX
	.word	mmUVD_REG_XX_MASK
	.word	mmUVD_RBC_XX_IB_REG_CHECK
	.word	mmUVD_SOFT_RESET
	.word	UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT
	.word	mmUVD_LMI_CTRL2
	.word	mmUVD_JPEG_ADDR_CONFIG
	.word	mmUVD_JPEG_UV_ADDR_CONFIG
	.word	UVD_SYS_INT_EN__UVD_JRBC_EN_MASK
	.word	mmUVD_SYS_INT_EN
	.word	UVD_RBC_RB_CNTL
	.word	RB_BUFSZ
	.word	RB_BLKSZ
	.word	RB_NO_FETCH
	.word	RB_NO_UPDATE
	.word	RB_RPTR_WR_EN
	.word	mmUVD_RBC_RB_CNTL
	.word	mmUVD_RBC_RB_WPTR_CNTL
	.word	mmUVD_RBC_RB_RPTR_ADDR
	.word	mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
	.word	mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
	.word	mmUVD_RBC_RB_RPTR
	.word	mmUVD_SCRATCH2
	.word	mmUVD_RBC_RB_WPTR
	.word	UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK
	.word	mmUVD_JRBC_RB_WPTR
	.word	amdgpu_sched_hw_submission
	.size	vcn_v1_0_start_dpg_mode, .-vcn_v1_0_start_dpg_mode
	.comm	mmUVD_VCPU_CNTL,4,4
	.comm	mmUVD_SYS_INT_EN,4,4
	.comm	mmUVD_SOFT_RESET,4,4
	.comm	mmUVD_SCRATCH2,4,4
	.comm	mmUVD_REG_XX_MASK,4,4
	.comm	mmUVD_RBC_XX_IB_REG_CHECK,4,4
	.comm	mmUVD_RBC_RB_WPTR_CNTL,4,4
	.comm	mmUVD_RBC_RB_WPTR,4,4
	.comm	mmUVD_RBC_RB_RPTR_ADDR,4,4
	.comm	mmUVD_RBC_RB_RPTR,4,4
	.comm	mmUVD_RBC_RB_CNTL,4,4
	.comm	mmUVD_POWER_STATUS,4,4
	.comm	mmUVD_MPC_SET_MUXB0,4,4
	.comm	mmUVD_MPC_SET_MUXA0,4,4
	.comm	mmUVD_MPC_SET_MUX,4,4
	.comm	mmUVD_MPC_CNTL,4,4
	.comm	mmUVD_MASTINT_EN,4,4
	.comm	mmUVD_LMI_SWAP_CNTL,4,4
	.comm	mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,4,4
	.comm	mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,4,4
	.comm	mmUVD_LMI_CTRL2,4,4
	.comm	mmUVD_LMI_CTRL,4,4
	.comm	mmUVD_JRBC_RB_WPTR,4,4
	.comm	mmUVD_JPEG_UV_ADDR_CONFIG,4,4
	.comm	mmUVD_JPEG_ADDR_CONFIG,4,4
	.comm	amdgpu_sched_hw_submission,4,4
	.comm	UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT,4,4
	.comm	UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK,4,4
	.comm	UVD_VCPU_CNTL__CLK_EN_MASK,4,4
	.comm	UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,4,4
	.comm	UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK,4,4
	.comm	UVD_RBC_RB_CNTL,4,4
	.comm	UVD_POWER_STATUS__UVD_PG_MODE_MASK,4,4
	.comm	UVD_POWER_STATUS__UVD_PG_EN_MASK,4,4
	.comm	UVD_MPC_SET_MUX__SET_2__SHIFT,4,4
	.comm	UVD_MPC_SET_MUX__SET_1__SHIFT,4,4
	.comm	UVD_MPC_SET_MUX__SET_0__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXB0__VARB_4__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXB0__VARB_3__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXB0__VARB_2__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXB0__VARB_1__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXA0__VARA_4__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXA0__VARA_3__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXA0__VARA_2__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXA0__VARA_1__SHIFT,4,4
	.comm	UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT,4,4
	.comm	UVD_MASTINT_EN__VCPU_EN_MASK,4,4
	.comm	UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT,4,4
	.comm	UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK,4,4
	.comm	UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK,4,4
	.comm	UVD_LMI_CTRL__REQ_MODE_MASK,4,4
	.comm	UVD_LMI_CTRL__MASK_MC_URGENT_MASK,4,4
	.comm	UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK,4,4
	.comm	UVD_LMI_CTRL__CRC_RESET_MASK,4,4
	.comm	UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,4,4
	.comm	UVD,4,4
	.comm	RB_RPTR_WR_EN,4,4
	.comm	RB_NO_UPDATE,4,4
	.comm	RB_NO_FETCH,4,4
	.comm	RB_BUFSZ,4,4
	.comm	RB_BLKSZ,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
