	.file	"extr_ice1724.c_snd_vt1724_pro_internal_clock_put.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	snd_vt1724_pro_internal_clock_put, @function
snd_vt1724_pro_internal_clock_put:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rsi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 8
	.cfi_def_cfa_offset 64
	call	snd_kcontrol_chip@PLT
	mov	rbx, rax
	mov	rax, QWORD PTR 0[rbp]
	mov	ebp, DWORD PTR [rax]
	mov	rax, QWORD PTR 40[rbx]
	mov	r12d, DWORD PTR [rax]
	cmp	ebp, r12d
	jbe	.L2
	mov	eax, DWORD PTR EINVAL[rip]
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	neg	eax
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L2:
	.cfi_restore_state
	lea	r13, 32[rbx]
	xor	r14d, r14d
	mov	rdi, r13
	call	spin_lock_irq@PLT
	mov	rdi, rbx
	call	[QWORD PTR 56[rbx]]
	test	rax, rax
	jne	.L4
	mov	rdi, rbx
	call	[QWORD PTR [rbx]]
	mov	r14d, eax
.L4:
	cmp	ebp, r12d
	jne	.L5
	mov	rdi, rbx
	mov	r15d, 1
	xor	ebp, ebp
	call	[QWORD PTR 48[rbx]]
.L6:
	mov	rdi, r13
	call	spin_unlock_irq@PLT
	cmp	r14d, ebp
	setne	r12b
	je	.L10
	test	r15b, r15b
	je	.L10
	mov	rax, QWORD PTR 24[rbx]
	test	rax, rax
	je	.L9
	xor	esi, esi
	mov	rdi, rbx
	call	rax
.L9:
	mov	eax, DWORD PTR 12[rbx]
	test	eax, eax
	je	.L10
	xor	ebp, ebp
	.p2align 4,,10
	.p2align 3
.L12:
	mov	rdx, QWORD PTR 16[rbx]
	mov	eax, ebp
	lea	rdi, [rdx+rax*8]
	mov	rax, QWORD PTR [rdi]
	test	rax, rax
	je	.L11
	xor	esi, esi
	call	rax
.L11:
	add	ebp, 1
	cmp	DWORD PTR 12[rbx], ebp
	ja	.L12
.L10:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movzx	eax, r12b
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L5:
	.cfi_restore_state
	mov	rax, QWORD PTR 40[rbx]
	mov	rdi, r13
	mov	rax, QWORD PTR 8[rax]
	mov	ebp, DWORD PTR [rax+rbp*4]
	mov	DWORD PTR 8[rbx], ebp
	call	spin_unlock_irq@PLT
	mov	esi, DWORD PTR 8[rbx]
	mov	edx, 1
	mov	rdi, rbx
	call	snd_vt1724_set_pro_rate@PLT
	mov	rdi, r13
	call	spin_lock_irq@PLT
	test	ebp, ebp
	sete	r15b
	jmp	.L6
	.cfi_endproc
.LFE0:
	.size	snd_vt1724_pro_internal_clock_put, .-snd_vt1724_pro_internal_clock_put
	.comm	EINVAL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_ice1724.c_snd_vt1724_pro_internal_clock_put.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	snd_vt1724_pro_internal_clock_put, %function
snd_vt1724_pro_internal_clock_put:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	mov	r5, r1
	bl	snd_kcontrol_chip
	ldr	r2, [r5]
	ldr	r3, [r0, #24]
	ldr	r5, [r2]
	ldr	r7, [r3]
	cmp	r5, r7
	bls	.L2
	ldr	r3, .L25
	ldr	r0, [r3]
	rsb	r0, r0, #0
	pop	{r4, r5, r6, r7, r8, pc}
.L2:
	mov	r4, r0
	add	r8, r0, #20
	mov	r0, r8
	bl	spin_lock_irq
	mov	r0, r4
	ldr	r3, [r4, #32]
	blx	r3
	cmp	r0, #0
	movne	r6, #0
	bne	.L4
	mov	r0, r4
	ldr	r3, [r4]
	blx	r3
	mov	r6, r0
.L4:
	cmp	r5, r7
	bne	.L5
	mov	r0, r4
	ldr	r3, [r4, #28]
	blx	r3
	mov	r5, #1
	mov	r7, #0
.L6:
	subs	r6, r6, r7
	movne	r6, #1
	mov	r0, r8
	bl	spin_unlock_irq
	tst	r6, r5
	beq	.L9
	ldr	r3, [r4, #16]
	cmp	r3, #0
	beq	.L8
	mov	r1, #0
	mov	r0, r4
	blx	r3
.L8:
	ldr	r1, [r4, #8]
	cmp	r1, #0
	beq	.L9
	mov	r5, #0
.L11:
	ldr	r3, [r4, #12]
	ldr	r2, [r3, r5, lsl #2]
	add	r0, r3, r5, lsl #2
	cmp	r2, #0
	add	r5, r5, #1
	beq	.L10
	mov	r1, #0
	blx	r2
	ldr	r1, [r4, #8]
.L10:
	cmp	r1, r5
	bhi	.L11
.L9:
	mov	r0, r6
	pop	{r4, r5, r6, r7, r8, pc}
.L5:
	ldr	r3, [r4, #24]
	mov	r0, r8
	ldr	r3, [r3, #4]
	ldr	r7, [r3, r5, lsl #2]
	clz	r5, r7
	str	r7, [r4, #4]
	bl	spin_unlock_irq
	mov	r2, #1
	ldr	r1, [r4, #4]
	mov	r0, r4
	bl	snd_vt1724_set_pro_rate
	mov	r0, r8
	bl	spin_lock_irq
	lsr	r5, r5, #5
	b	.L6
.L26:
	.align	2
.L25:
	.word	EINVAL
	.size	snd_vt1724_pro_internal_clock_put, .-snd_vt1724_pro_internal_clock_put
	.comm	EINVAL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
