	.file	"extr_bb_cfg.c_rtl88e_phy_init_bb_rf_register_definition.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	rtl88e_phy_init_bb_rf_register_definition, @function
rtl88e_phy_init_bb_rf_register_definition:
.LFB0:
	.cfi_startproc
	endbr64
	sub	rsp, 56
	.cfi_def_cfa_offset 64
	mov	rdx, QWORD PTR RF_PATH_A[rip]
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 40[rsp], rax
	xor	eax, eax
	mov	rax, QWORD PTR [rdi]
	lea	rcx, [rdx+rdx*2]
	mov	rax, QWORD PTR [rax]
	lea	rcx, [rdx+rcx*4]
	lea	rcx, [rax+rcx*8]
	mov	QWORD PTR [rsp+rdx*8], rcx
	mov	rcx, QWORD PTR RF_PATH_B[rip]
	lea	rsi, [rcx+rcx*2]
	lea	rsi, [rcx+rsi*4]
	lea	rax, [rax+rsi*8]
	mov	rsi, QWORD PTR rFPGA0_XA_RFInterfaceOE[rip]
	mov	QWORD PTR [rsp+rcx*8], rax
	mov	rcx, QWORD PTR rFPGA0_XAB_RFInterfaceSW[rip]
	mov	rdx, QWORD PTR [rsp+rdx*8]
	mov	QWORD PTR 96[rdx], rcx
	mov	QWORD PTR 96[rax], rcx
	mov	rcx, QWORD PTR rFPGA0_XAB_RFInterfaceRB[rip]
	mov	QWORD PTR 88[rdx], rcx
	mov	QWORD PTR 88[rax], rcx
	mov	rcx, QWORD PTR rFPGA0_XB_RFInterfaceOE[rip]
	mov	QWORD PTR 80[rdx], rsi
	mov	QWORD PTR 80[rax], rcx
	mov	QWORD PTR 72[rdx], rsi
	mov	QWORD PTR 72[rax], rcx
	mov	ecx, DWORD PTR rFPGA0_XA_LSSIParameter[rip]
	mov	DWORD PTR 64[rdx], ecx
	mov	ecx, DWORD PTR rFPGA0_XB_LSSIParameter[rip]
	mov	DWORD PTR 64[rax], ecx
	mov	rcx, QWORD PTR rFPGA0_XAB_RFParameter[rip]
	mov	QWORD PTR 56[rdx], rcx
	mov	QWORD PTR 56[rax], rcx
	mov	rcx, QWORD PTR rFPGA0_TxGainStage[rip]
	mov	QWORD PTR 48[rdx], rcx
	mov	QWORD PTR 48[rax], rcx
	mov	ecx, DWORD PTR rFPGA0_XA_HSSIParameter1[rip]
	mov	DWORD PTR 44[rdx], ecx
	mov	ecx, DWORD PTR rFPGA0_XB_HSSIParameter1[rip]
	mov	DWORD PTR 44[rax], ecx
	mov	ecx, DWORD PTR rFPGA0_XA_HSSIParameter2[rip]
	mov	DWORD PTR 40[rdx], ecx
	mov	ecx, DWORD PTR rFPGA0_XB_HSSIParameter2[rip]
	mov	DWORD PTR 40[rax], ecx
	mov	rcx, QWORD PTR rFPGA0_XAB_SwitchControl[rip]
	mov	QWORD PTR 32[rdx], rcx
	mov	QWORD PTR 32[rax], rcx
	mov	ecx, DWORD PTR rOFDM0_XAAGCCore1[rip]
	mov	DWORD PTR 28[rdx], ecx
	mov	ecx, DWORD PTR rOFDM0_XBAGCCore1[rip]
	mov	DWORD PTR 28[rax], ecx
	mov	ecx, DWORD PTR rOFDM0_XAAGCCore2[rip]
	mov	DWORD PTR 24[rdx], ecx
	mov	ecx, DWORD PTR rOFDM0_XBAGCCore2[rip]
	mov	DWORD PTR 24[rax], ecx
	mov	ecx, DWORD PTR rOFDM0_XARxIQImbalance[rip]
	mov	DWORD PTR 20[rdx], ecx
	mov	ecx, DWORD PTR rOFDM0_XBRxIQImbalance[rip]
	mov	DWORD PTR 20[rax], ecx
	mov	ecx, DWORD PTR rOFDM0_XARxAFE[rip]
	mov	DWORD PTR 16[rdx], ecx
	mov	ecx, DWORD PTR rOFDM0_XBRxAFE[rip]
	mov	DWORD PTR 16[rax], ecx
	mov	ecx, DWORD PTR rOFDM0_XATxIQImbalance[rip]
	mov	DWORD PTR 12[rdx], ecx
	mov	ecx, DWORD PTR rOFDM0_XBTxIQImbalance[rip]
	mov	DWORD PTR 12[rax], ecx
	mov	ecx, DWORD PTR rOFDM0_XATxAFE[rip]
	mov	DWORD PTR 8[rdx], ecx
	mov	ecx, DWORD PTR rOFDM0_XBTxAFE[rip]
	mov	DWORD PTR 8[rax], ecx
	mov	ecx, DWORD PTR rFPGA0_XA_LSSIReadBack[rip]
	mov	DWORD PTR 4[rdx], ecx
	mov	ecx, DWORD PTR rFPGA0_XB_LSSIReadBack[rip]
	mov	DWORD PTR 4[rax], ecx
	mov	ecx, DWORD PTR TransceiverA_HSPI_Readback[rip]
	mov	DWORD PTR [rdx], ecx
	mov	edx, DWORD PTR TransceiverB_HSPI_Readback[rip]
	mov	DWORD PTR [rax], edx
	mov	rax, QWORD PTR 40[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L5
	add	rsp, 56
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
.L5:
	.cfi_restore_state
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	rtl88e_phy_init_bb_rf_register_definition, .-rtl88e_phy_init_bb_rf_register_definition
	.comm	rOFDM0_XBTxIQImbalance,4,4
	.comm	rOFDM0_XBTxAFE,4,4
	.comm	rOFDM0_XBRxIQImbalance,4,4
	.comm	rOFDM0_XBRxAFE,4,4
	.comm	rOFDM0_XBAGCCore2,4,4
	.comm	rOFDM0_XBAGCCore1,4,4
	.comm	rOFDM0_XATxIQImbalance,4,4
	.comm	rOFDM0_XATxAFE,4,4
	.comm	rOFDM0_XARxIQImbalance,4,4
	.comm	rOFDM0_XARxAFE,4,4
	.comm	rOFDM0_XAAGCCore2,4,4
	.comm	rOFDM0_XAAGCCore1,4,4
	.comm	rFPGA0_XB_RFInterfaceOE,8,8
	.comm	rFPGA0_XB_LSSIReadBack,4,4
	.comm	rFPGA0_XB_LSSIParameter,4,4
	.comm	rFPGA0_XB_HSSIParameter2,4,4
	.comm	rFPGA0_XB_HSSIParameter1,4,4
	.comm	rFPGA0_XA_RFInterfaceOE,8,8
	.comm	rFPGA0_XA_LSSIReadBack,4,4
	.comm	rFPGA0_XA_LSSIParameter,4,4
	.comm	rFPGA0_XA_HSSIParameter2,4,4
	.comm	rFPGA0_XA_HSSIParameter1,4,4
	.comm	rFPGA0_XAB_SwitchControl,8,8
	.comm	rFPGA0_XAB_RFParameter,8,8
	.comm	rFPGA0_XAB_RFInterfaceSW,8,8
	.comm	rFPGA0_XAB_RFInterfaceRB,8,8
	.comm	rFPGA0_TxGainStage,8,8
	.comm	TransceiverB_HSPI_Readback,4,4
	.comm	TransceiverA_HSPI_Readback,4,4
	.comm	RF_PATH_B,8,8
	.comm	RF_PATH_A,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_bb_cfg.c_rtl88e_phy_init_bb_rf_register_definition.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	rtl88e_phy_init_bb_rf_register_definition, %function
rtl88e_phy_init_bb_rf_register_definition:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	ldr	r3, .L6
	ldr	r2, .L6+4
	ldr	r1, [r0]
	ldr	r2, [r2]
	ldr	r3, [r3]
	ldr	r0, [r1]
	sub	sp, sp, #24
	add	ip, r3, r3, lsl #3
	add	lr, r2, r2, lsl #3
	add	r1, sp, #24
	add	r3, r1, r3, lsl #2
	ldr	r7, .L6+8
	add	r1, r1, r2, lsl #2
	ldr	r6, .L6+12
	add	r2, r0, lr, lsl #3
	add	ip, r0, ip, lsl #3
	str	ip, [r3, #-20]
	str	r2, [r1, #-20]
	ldr	r3, [r3, #-20]
	ldr	ip, [r7]
	ldr	r1, [r6]
	ldr	r7, .L6+16
	ldr	r5, .L6+20
	ldr	r4, .L6+24
	ldr	r7, [r7]
	str	r7, [sp, #20]
	mov	r7,#0
	ldr	r5, [r5]
	str	ip, [r3, #68]
	ldr	r4, [r4]
	str	ip, [r2, #68]
	ldr	r6, .L6+28
	str	r1, [r3, #64]
	ldr	r7, .L6+32
	str	r1, [r2, #64]
	ldr	ip, .L6+36
	ldr	r1, .L6+40
	str	r5, [r3, #60]
	ldr	ip, [ip]
	str	r4, [r2, #60]
	ldr	r6, [r6]
	str	r5, [r3, #56]
	ldr	r1, [r1]
	str	r4, [r2, #56]
	ldr	r7, [r7]
	ldr	r4, .L6+44
	str	r6, [r3, #52]
	ldr	r5, .L6+48
	ldr	r6, [r4]
	str	r7, [r2, #52]
	ldr	r4, .L6+52
	str	ip, [r3, #48]
	str	ip, [r2, #48]
	str	r1, [r3, #44]
	ldr	ip, .L6+56
	str	r1, [r2, #44]
	ldr	r1, .L6+60
	str	r6, [r3, #40]
	ldr	r1, [r1]
	ldr	r6, [ip]
	ldr	r5, [r5]
	ldr	r4, [r4]
	ldr	ip, .L6+64
	str	r5, [r2, #40]
	str	r4, [r3, #36]
	ldr	r5, [ip]
	str	r6, [r2, #36]
	ldr	ip, .L6+68
	str	r1, [r3, #32]
	str	r1, [r2, #32]
	ldr	r1, .L6+72
	str	r5, [r3, #28]
	ldr	r4, [ip]
	ldr	r5, [r1]
	ldr	ip, .L6+76
	ldr	r1, .L6+80
	str	r4, [r2, #28]
	ldr	ip, [ip]
	ldr	r4, [r1]
	ldr	r6, .L6+84
	ldr	r1, .L6+88
	str	ip, [r3, #24]
	ldr	r6, [r6]
	ldr	ip, [r1]
	ldr	r1, .L6+92
	str	r6, [r2, #24]
	ldr	r6, [r1]
	ldr	r1, .L6+96
	str	r5, [r3, #20]
	ldr	r5, [r1]
	ldr	r1, .L6+100
	str	r4, [r2, #20]
	ldr	r4, [r1]
	ldr	r1, .L6+104
	str	ip, [r3, #16]
	ldr	ip, [r1]
	ldr	r1, .L6+108
	str	r6, [r2, #16]
	ldr	r1, [r1]
	str	r5, [r3, #12]
	str	r4, [r2, #12]
	ldr	r5, .L6+112
	str	ip, [r3, #8]
	ldr	r4, .L6+116
	ldr	ip, .L6+120
	str	r1, [r2, #8]
	ldr	r1, .L6+124
	ldr	r5, [r5]
	ldr	r4, [r4]
	ldr	ip, [ip]
	ldr	r1, [r1]
	str	r5, [r3, #4]
	str	r4, [r2, #4]
	str	ip, [r3]
	ldr	r3, .L6+16
	str	r1, [r0, lr, lsl #3]
	ldr	r2, [r3]
	ldr	r3, [sp, #20]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L5
	add	sp, sp, #24
	@ sp needed
	pop	{r4, r5, r6, r7, r8, pc}
.L5:
	bl	__stack_chk_fail
.L7:
	.align	2
.L6:
	.word	RF_PATH_A
	.word	RF_PATH_B
	.word	rFPGA0_XAB_RFInterfaceSW
	.word	rFPGA0_XAB_RFInterfaceRB
	.word	.LC0
	.word	rFPGA0_XA_RFInterfaceOE
	.word	rFPGA0_XB_RFInterfaceOE
	.word	rFPGA0_XA_LSSIParameter
	.word	rFPGA0_XB_LSSIParameter
	.word	rFPGA0_XAB_RFParameter
	.word	rFPGA0_TxGainStage
	.word	rFPGA0_XA_HSSIParameter1
	.word	rFPGA0_XB_HSSIParameter1
	.word	rFPGA0_XA_HSSIParameter2
	.word	rFPGA0_XB_HSSIParameter2
	.word	rFPGA0_XAB_SwitchControl
	.word	rOFDM0_XAAGCCore1
	.word	rOFDM0_XBAGCCore1
	.word	rOFDM0_XARxIQImbalance
	.word	rOFDM0_XAAGCCore2
	.word	rOFDM0_XBRxIQImbalance
	.word	rOFDM0_XBAGCCore2
	.word	rOFDM0_XARxAFE
	.word	rOFDM0_XBRxAFE
	.word	rOFDM0_XATxIQImbalance
	.word	rOFDM0_XBTxIQImbalance
	.word	rOFDM0_XATxAFE
	.word	rOFDM0_XBTxAFE
	.word	rFPGA0_XA_LSSIReadBack
	.word	rFPGA0_XB_LSSIReadBack
	.word	TransceiverA_HSPI_Readback
	.word	TransceiverB_HSPI_Readback
	.size	rtl88e_phy_init_bb_rf_register_definition, .-rtl88e_phy_init_bb_rf_register_definition
	.comm	rOFDM0_XBTxIQImbalance,4,4
	.comm	rOFDM0_XBTxAFE,4,4
	.comm	rOFDM0_XBRxIQImbalance,4,4
	.comm	rOFDM0_XBRxAFE,4,4
	.comm	rOFDM0_XBAGCCore2,4,4
	.comm	rOFDM0_XBAGCCore1,4,4
	.comm	rOFDM0_XATxIQImbalance,4,4
	.comm	rOFDM0_XATxAFE,4,4
	.comm	rOFDM0_XARxIQImbalance,4,4
	.comm	rOFDM0_XARxAFE,4,4
	.comm	rOFDM0_XAAGCCore2,4,4
	.comm	rOFDM0_XAAGCCore1,4,4
	.comm	rFPGA0_XB_RFInterfaceOE,4,4
	.comm	rFPGA0_XB_LSSIReadBack,4,4
	.comm	rFPGA0_XB_LSSIParameter,4,4
	.comm	rFPGA0_XB_HSSIParameter2,4,4
	.comm	rFPGA0_XB_HSSIParameter1,4,4
	.comm	rFPGA0_XA_RFInterfaceOE,4,4
	.comm	rFPGA0_XA_LSSIReadBack,4,4
	.comm	rFPGA0_XA_LSSIParameter,4,4
	.comm	rFPGA0_XA_HSSIParameter2,4,4
	.comm	rFPGA0_XA_HSSIParameter1,4,4
	.comm	rFPGA0_XAB_SwitchControl,4,4
	.comm	rFPGA0_XAB_RFParameter,4,4
	.comm	rFPGA0_XAB_RFInterfaceSW,4,4
	.comm	rFPGA0_XAB_RFInterfaceRB,4,4
	.comm	rFPGA0_TxGainStage,4,4
	.comm	TransceiverB_HSPI_Readback,4,4
	.comm	TransceiverA_HSPI_Readback,4,4
	.comm	RF_PATH_B,4,4
	.comm	RF_PATH_A,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
