	.file	"extr_si_dpm.c_si_parse_pplib_clock_info.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	si_parse_pplib_clock_info, @function
si_parse_pplib_clock_info:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	mov	r15, rsi
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	mov	r12, rdi
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rcx
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movsx	rbx, edx
	mov	r14, rbx
	sal	rbx, 5
	sub	rsp, 72
	.cfi_def_cfa_offset 128
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 56[rsp], rax
	xor	eax, eax
	call	rv770_get_pi@PLT
	mov	rdi, r12
	mov	QWORD PTR [rsp], rax
	call	evergreen_get_pi@PLT
	mov	rdi, r12
	mov	QWORD PTR 8[rsp], rax
	call	si_get_pi@PLT
	mov	rdi, r15
	mov	r13, rax
	call	ni_get_ps@PLT
	lea	edx, 1[r14]
	mov	edi, DWORD PTR 28[rbp]
	mov	DWORD PTR [rax], edx
	add	rbx, QWORD PTR 8[rax]
	call	le16_to_cpu@PLT
	mov	edi, DWORD PTR 24[rbp]
	mov	r10, rax
	mov	eax, DWORD PTR 0[rbp]
	sal	eax, 16
	or	eax, r10d
	mov	DWORD PTR [rbx], eax
	call	le16_to_cpu@PLT
	mov	edi, DWORD PTR 20[rbp]
	mov	r10, rax
	mov	eax, DWORD PTR 4[rbp]
	sal	eax, 16
	or	eax, r10d
	mov	DWORD PTR 4[rbx], eax
	call	le16_to_cpu@PLT
	mov	edi, DWORD PTR 16[rbp]
	mov	QWORD PTR 8[rbx], rax
	call	le16_to_cpu@PLT
	mov	edi, DWORD PTR 12[rbp]
	mov	QWORD PTR 16[rbx], rax
	call	le32_to_cpu@PLT
	mov	ecx, DWORD PTR 8[rbp]
	mov	edx, DWORD PTR 68[r13]
	mov	rdi, r12
	mov	DWORD PTR 28[rbx], eax
	mov	esi, DWORD PTR 72[r13]
	call	r600_get_pcie_gen_support@PLT
	mov	rsi, QWORD PTR 8[rbx]
	lea	rdx, 24[rsp]
	mov	rdi, r12
	mov	DWORD PTR 24[rbx], eax
	call	si_get_leakage_voltage_from_leakage_index@PLT
	mov	r8, QWORD PTR [rsp]
	test	eax, eax
	jne	.L2
	mov	rax, QWORD PTR 24[rsp]
	mov	QWORD PTR 8[rbx], rax
.L2:
	mov	eax, DWORD PTR [r15]
	test	DWORD PTR ATOM_PPLIB_CLASSIFICATION_ACPI[rip], eax
	je	.L3
	mov	rdx, QWORD PTR 8[rbx]
	mov	rcx, QWORD PTR 8[rsp]
	mov	QWORD PTR [r8], rdx
	mov	rdx, QWORD PTR 16[rbx]
	mov	QWORD PTR [rcx], rdx
	mov	edx, DWORD PTR 24[rbx]
	mov	DWORD PTR 64[r13], edx
.L3:
	mov	edx, DWORD PTR 4[r15]
	test	DWORD PTR ATOM_PPLIB_CLASSIFICATION2_ULV[rip], edx
	je	.L4
	test	r14d, r14d
	je	.L24
.L4:
	mov	rdx, QWORD PTR 8[rbx]
	cmp	QWORD PTR 8[r8], rdx
	jle	.L5
	mov	QWORD PTR 8[r8], rdx
.L5:
	cmp	rdx, QWORD PTR 16[r8]
	jle	.L6
	mov	QWORD PTR 16[r8], rdx
.L6:
	test	DWORD PTR ATOM_PPLIB_CLASSIFICATION_BOOT[rip], eax
	jne	.L25
.L7:
	and	eax, DWORD PTR ATOM_PPLIB_CLASSIFICATION_UI_MASK[rip]
	cmp	eax, DWORD PTR ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE[rip]
	jne	.L1
	mov	eax, DWORD PTR [rbx]
	mov	DWORD PTR [r12], eax
	mov	eax, DWORD PTR 4[rbx]
	mov	DWORD PTR 4[r12], eax
	mov	rax, QWORD PTR 8[rbx]
	mov	QWORD PTR 8[r12], rax
	mov	rax, QWORD PTR 16[rbx]
	mov	QWORD PTR 16[r12], rax
.L1:
	mov	rax, QWORD PTR 56[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L26
	add	rsp, 72
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L24:
	.cfi_restore_state
	movdqu	xmm0, XMMWORD PTR [rbx]
	mov	edx, DWORD PTR SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT[rip]
	movups	XMMWORD PTR 32[r13], xmm0
	movdqu	xmm1, XMMWORD PTR 16[rbx]
	mov	DWORD PTR 24[r13], edx
	mov	edx, DWORD PTR SISLANDS_CGULVPARAMETER_DFLT[rip]
	mov	QWORD PTR 8[r13], 0
	mov	DWORD PTR 20[r13], edx
	mov	edx, DWORD PTR SISLANDS_CGULVCONTROL_DFLT[rip]
	movups	XMMWORD PTR 48[r13], xmm1
	mov	DWORD PTR 16[r13], edx
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L25:
	lea	rcx, 48[rsp]
	lea	rdx, 40[rsp]
	mov	rdi, r12
	lea	rsi, 32[rsp]
	call	radeon_atombios_get_default_voltages@PLT
	mov	eax, DWORD PTR 24[r12]
	mov	DWORD PTR 4[rbx], eax
	mov	eax, DWORD PTR 28[r12]
	mov	DWORD PTR [rbx], eax
	mov	rax, QWORD PTR 32[rsp]
	mov	QWORD PTR 8[rbx], rax
	mov	rax, QWORD PTR 40[rsp]
	mov	QWORD PTR 16[rbx], rax
	mov	rax, QWORD PTR 48[rsp]
	mov	QWORD PTR 0[r13], rax
	mov	eax, DWORD PTR [r15]
	jmp	.L7
.L26:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	si_parse_pplib_clock_info, .-si_parse_pplib_clock_info
	.comm	SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT,4,4
	.comm	SISLANDS_CGULVPARAMETER_DFLT,4,4
	.comm	SISLANDS_CGULVCONTROL_DFLT,4,4
	.comm	ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE,4,4
	.comm	ATOM_PPLIB_CLASSIFICATION_UI_MASK,4,4
	.comm	ATOM_PPLIB_CLASSIFICATION_BOOT,4,4
	.comm	ATOM_PPLIB_CLASSIFICATION_ACPI,4,4
	.comm	ATOM_PPLIB_CLASSIFICATION2_ULV,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_si_dpm.c_si_parse_pplib_clock_info.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	si_parse_pplib_clock_info, %function
si_parse_pplib_clock_info:
	@ args = 0, pretend = 0, frame = 32
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	mov	r5, r3
	ldr	r3, .L24
	sub	sp, sp, #36
	mov	r10, r1
	mov	r8, r2
	mov	r6, r0
	ldr	r3, [r3]
	str	r3, [sp, #28]
	mov	r3,#0
	bl	rv770_get_pi
	mov	r9, r0
	mov	r0, r6
	bl	evergreen_get_pi
	mov	fp, r0
	mov	r0, r6
	str	fp, [sp, #4]
	bl	si_get_pi
	mov	r7, r0
	mov	r0, r10
	bl	ni_get_ps
	add	r3, r8, #1
	ldr	fp, [r0, #4]
	str	r3, [r0]
	add	r3, r8, r8, lsl #1
	add	r4, fp, r3, lsl #3
	ldr	r0, [r5, #28]
	lsl	r3, r3, #3
	str	r3, [sp]
	bl	le16_to_cpu
	mov	r3, r0
	ldr	r2, [r5]
	ldr	r0, [r5, #24]
	orr	r3, r3, r2, lsl #16
	ldr	r2, [sp]
	str	r3, [fp, r2]
	bl	le16_to_cpu
	mov	r3, r0
	ldr	r2, [r5, #4]
	ldr	r0, [r5, #20]
	orr	r3, r3, r2, lsl #16
	str	r3, [r4, #4]
	bl	le16_to_cpu
	mov	r3, r0
	ldr	r0, [r5, #16]
	str	r3, [r4, #8]
	bl	le16_to_cpu
	mov	r3, r0
	ldr	r0, [r5, #12]
	str	r3, [r4, #12]
	bl	le32_to_cpu
	ldr	r3, [r5, #8]
	ldr	r2, [r7, #52]
	ldr	r1, [r7, #56]
	str	r0, [r4, #20]
	mov	r0, r6
	bl	r600_get_pcie_gen_support
	ldr	r1, [r4, #8]
	str	r0, [r4, #16]
	add	r2, sp, #12
	mov	r0, r6
	bl	si_get_leakage_voltage_from_leakage_index
	cmp	r0, #0
	ldreq	r3, [sp, #12]
	ldr	ip, [r10]
	streq	r3, [r4, #8]
	ldr	r3, .L24+4
	ldr	r3, [r3]
	tst	ip, r3
	beq	.L3
	ldr	r3, [r4, #8]
	ldr	r2, [r4, #12]
	ldr	r1, [sp, #4]
	str	r3, [r9]
	ldr	r3, [r4, #16]
	str	r2, [r1]
	str	r3, [r7, #48]
.L3:
	ldr	r3, .L24+8
	ldr	r2, [r10, #4]
	ldr	r3, [r3]
	tst	r2, r3
	movne	r2, #1
	moveq	r2, #0
	cmp	r8, #0
	moveq	r8, r2
	movne	r8, #0
	cmp	r8, #0
	bne	.L21
.L4:
	ldr	r3, [r4, #8]
	ldr	r2, [r9, #4]
	cmp	r2, r3
	ldr	r2, [r9, #8]
	strgt	r3, [r9, #4]
	cmp	r3, r2
	strgt	r3, [r9, #8]
	ldr	r3, .L24+12
	ldr	r3, [r3]
	tst	ip, r3
	bne	.L22
.L7:
	ldr	r2, .L24+16
	ldr	r3, .L24+20
	ldr	r2, [r2]
	ldr	r3, [r3]
	and	ip, ip, r2
	cmp	ip, r3
	ldreq	r3, [sp]
	ldreq	r0, [fp, r3]
	ldmibeq	r4, {r1, r2, r3}
	stmeq	r6, {r0, r1, r2, r3}
	ldr	r3, .L24
	ldr	r2, [r3]
	ldr	r3, [sp, #28]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L23
	add	sp, sp, #36
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L22:
	add	r3, sp, #24
	add	r2, sp, #20
	add	r1, sp, #16
	mov	r0, r6
	bl	radeon_atombios_get_default_voltages
	ldr	lr, [r6, #16]
	ldr	r0, [r6, #20]
	ldr	ip, [r10]
	str	lr, [r4, #4]
	ldr	lr, [sp]
	add	r1, sp, #16
	ldm	r1, {r1, r2, r3}
	str	r0, [fp, lr]
	str	r1, [r4, #8]
	str	r2, [r4, #12]
	str	r3, [r7]
	b	.L7
.L21:
	mov	r8, #0
	mov	r5, r4
	add	lr, r7, #24
	ldmia	r5!, {r0, r1, r2, r3}
	str	r8, [r7, #4]
	stmia	lr!, {r0, r1, r2, r3}
	ldr	r1, .L24+24
	ldr	r2, .L24+28
	ldr	r1, [r1]
	ldr	r3, .L24+32
	str	r1, [sp, #4]
	ldr	r2, [r2]
	ldm	r5, {r0, r1}
	ldr	r3, [r3]
	stm	lr, {r0, r1}
	ldr	r1, [sp, #4]
	str	r8, [r7, #8]
	str	r2, [r7, #20]
	str	r3, [r7, #16]
	str	r1, [r7, #12]
	b	.L4
.L23:
	bl	__stack_chk_fail
.L25:
	.align	2
.L24:
	.word	.LC0
	.word	ATOM_PPLIB_CLASSIFICATION_ACPI
	.word	ATOM_PPLIB_CLASSIFICATION2_ULV
	.word	ATOM_PPLIB_CLASSIFICATION_BOOT
	.word	ATOM_PPLIB_CLASSIFICATION_UI_MASK
	.word	ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
	.word	SISLANDS_CGULVCONTROL_DFLT
	.word	SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT
	.word	SISLANDS_CGULVPARAMETER_DFLT
	.size	si_parse_pplib_clock_info, .-si_parse_pplib_clock_info
	.comm	SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT,4,4
	.comm	SISLANDS_CGULVPARAMETER_DFLT,4,4
	.comm	SISLANDS_CGULVCONTROL_DFLT,4,4
	.comm	ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE,4,4
	.comm	ATOM_PPLIB_CLASSIFICATION_UI_MASK,4,4
	.comm	ATOM_PPLIB_CLASSIFICATION_BOOT,4,4
	.comm	ATOM_PPLIB_CLASSIFICATION_ACPI,4,4
	.comm	ATOM_PPLIB_CLASSIFICATION2_ULV,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
