	.file	"extr_dm355_ccdc.c_ccdc_config_raw.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"\nStarting ccdc_config_raw..."
.LC1:
	.string	"\nWriting 0x%x to MODESET...\n"
.LC2:
	.string	"\nWriting 0x%x to GAMMAWD...\n"
.LC3:
	.string	"\nWriting %x to COLPTN...\n"
.LC4:
	.string	"\nWriting 0x%x to HSIZE...\n"
.LC5:
	.string	"\nWriting %x to SDOFST...\n"
.LC6:
	.string	"\nend of ccdc_config_raw..."
	.text
	.p2align 4
	.type	ccdc_config_raw, @function
ccdc_config_raw:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	mov	edi, DWORD PTR ccdc_cfg[rip]
	lea	rsi, .LC0[rip]
	xor	eax, eax
	call	dev_dbg@PLT
	xor	eax, eax
	call	ccdc_restore_defaults@PLT
	mov	esi, DWORD PTR CCDCFG[rip]
	mov	edi, DWORD PTR CCDC_YCINSWP_RAW[rip]
	or	edi, DWORD PTR CCDC_CCDCFG_FIDMD_LATCH_VSYNC[rip]
	or	edi, DWORD PTR CCDC_CCDCFG_WENLOG_AND[rip]
	or	edi, DWORD PTR CCDC_CCDCFG_TRGSEL_WEN[rip]
	or	edi, DWORD PTR CCDC_CCDCFG_EXTRG_DISABLE[rip]
	or	edi, DWORD PTR CCDC_LATCH_ON_VSYNC_DISABLE[rip]
	call	regw@PLT
	mov	ecx, DWORD PTR CCDC_VD_POL_SHIFT[rip]
	mov	eax, DWORD PTR ccdc_cfg[rip+8]
	and	eax, DWORD PTR CCDC_VD_POL_MASK[rip]
	mov	edx, DWORD PTR CCDC_VDHDOUT_INPUT[rip]
	sal	eax, cl
	or	edx, DWORD PTR CCDC_RAW_IP_MODE[rip]
	mov	ecx, DWORD PTR CCDC_HD_POL_SHIFT[rip]
	or	edx, DWORD PTR CCDC_DATAPOL_NORMAL[rip]
	or	edx, DWORD PTR CCDC_EXWEN_DISABLE[rip]
	or	edx, eax
	mov	eax, DWORD PTR ccdc_cfg[rip+12]
	and	eax, DWORD PTR CCDC_HD_POL_MASK[rip]
	sal	eax, cl
	mov	ecx, DWORD PTR CCDC_FID_POL_SHIFT[rip]
	or	edx, eax
	mov	eax, DWORD PTR ccdc_cfg[rip+16]
	and	eax, DWORD PTR CCDC_FID_POL_MASK[rip]
	sal	eax, cl
	mov	ecx, DWORD PTR CCDC_FRM_FMT_SHIFT[rip]
	or	edx, eax
	mov	eax, DWORD PTR ccdc_cfg[rip+20]
	and	eax, DWORD PTR CCDC_FRM_FMT_MASK[rip]
	sal	eax, cl
	mov	ecx, DWORD PTR CCDC_PIX_FMT_SHIFT[rip]
	or	edx, eax
	mov	eax, DWORD PTR ccdc_cfg[rip+24]
	and	eax, DWORD PTR CCDC_PIX_FMT_MASK[rip]
	sal	eax, cl
	or	edx, eax
	mov	rax, QWORD PTR CCDC_DATA_8BITS[rip]
	cmp	QWORD PTR ccdc_cfg[rip+48], rax
	je	.L2
	cmp	QWORD PTR ccdc_cfg[rip+88], 0
	jne	.L2
.L3:
	mov	eax, DWORD PTR ccdc_cfg[rip+56]
	test	eax, eax
	je	.L4
	mov	ecx, DWORD PTR CCDC_LPF_SHIFT[rip]
	and	eax, DWORD PTR CCDC_LPF_MASK[rip]
	sal	eax, cl
	or	edx, eax
.L4:
	mov	ecx, DWORD PTR CCDC_DATASFT_SHIFT[rip]
	mov	r12d, DWORD PTR ccdc_cfg[rip+60]
	and	r12d, DWORD PTR CCDC_DATASFT_MASK[rip]
	mov	esi, DWORD PTR MODESET[rip]
	sal	r12d, cl
	or	r12d, edx
	mov	edi, r12d
	call	regw@PLT
	mov	edi, DWORD PTR ccdc_cfg[rip]
	mov	edx, r12d
	xor	eax, eax
	lea	rsi, .LC1[rip]
	call	dev_dbg@PLT
	mov	esi, DWORD PTR MEDFILT[rip]
	mov	edi, DWORD PTR ccdc_cfg[rip+64]
	and	edi, DWORD PTR CCDC_MED_FILT_THRESH[rip]
	call	regw@PLT
	mov	ecx, DWORD PTR CCDC_GAMMAWD_INPUT_SHIFT[rip]
	mov	r12d, DWORD PTR CCDC_GAMMA_BITS_11_2[rip]
	sal	r12d, cl
	or	r12d, DWORD PTR CCDC_CFA_MOSAIC[rip]
	cmp	QWORD PTR ccdc_cfg[rip+88], 0
	je	.L5
	mov	eax, DWORD PTR ccdc_cfg[rip+80]
	and	eax, DWORD PTR CCDC_ALAW_GAMMA_WD_MASK[rip]
	sal	eax, cl
	or	r12d, eax
	or	r12d, DWORD PTR CCDC_ALAW_ENABLE[rip]
.L5:
	mov	ecx, DWORD PTR CCDC_MFILT1_SHIFT[rip]
	mov	eax, DWORD PTR ccdc_cfg[rip+68]
	mov	edx, DWORD PTR ccdc_cfg[rip+72]
	mov	esi, DWORD PTR GAMMAWD[rip]
	sal	eax, cl
	mov	ecx, DWORD PTR CCDC_MFILT2_SHIFT[rip]
	sal	edx, cl
	or	eax, edx
	or	r12d, eax
	mov	edi, r12d
	call	regw@PLT
	mov	edi, DWORD PTR ccdc_cfg[rip]
	mov	edx, r12d
	xor	eax, eax
	lea	rsi, .LC2[rip]
	call	dev_dbg@PLT
	mov	esi, DWORD PTR ccdc_cfg[rip+20]
	mov	edx, 1
	lea	rdi, ccdc_cfg[rip+40]
	call	ccdc_setwin@PLT
	lea	rdi, ccdc_cfg[rip+124]
	call	ccdc_config_black_clamp@PLT
	lea	rdi, ccdc_cfg[rip+120]
	call	ccdc_config_black_compense@PLT
	lea	rdi, ccdc_cfg[rip+116]
	call	ccdc_config_vdfc@PLT
	test	rax, rax
	js	.L22
	lea	rdi, ccdc_cfg[rip+112]
	call	ccdc_config_csc@PLT
	lea	rsi, ccdc_cfg[rip+104]
	lea	rdi, 4[rsi]
	call	ccdc_config_color_patterns@PLT
	xor	eax, eax
	call	ccdc_config_gain_offset@PLT
	mov	edi, DWORD PTR ccdc_cfg[rip]
	mov	edx, r12d
	xor	eax, eax
	lea	rsi, .LC3[rip]
	call	dev_dbg@PLT
	mov	eax, DWORD PTR CCDC_DATAOFST_MASK[rip]
	mov	edi, DWORD PTR ccdc_cfg[rip+96]
	mov	ecx, DWORD PTR CCDC_DATAOFST_H_SHIFT[rip]
	mov	esi, DWORD PTR DATAOFST[rip]
	and	edi, eax
	and	eax, DWORD PTR ccdc_cfg[rip+100]
	sal	edi, cl
	mov	ecx, DWORD PTR CCDC_DATAOFST_V_SHIFT[rip]
	sal	eax, cl
	or	edi, eax
	call	regw@PLT
	mov	ecx, DWORD PTR CCDC_HSIZE_FLIP_SHIFT[rip]
	mov	eax, DWORD PTR ccdc_cfg[rip+28]
	and	eax, DWORD PTR CCDC_HSIZE_FLIP_MASK[rip]
	mov	rsi, QWORD PTR CCDC_DATA_8BITS[rip]
	sal	eax, cl
	cmp	QWORD PTR ccdc_cfg[rip+48], rsi
	mov	ecx, DWORD PTR ccdc_cfg[rip+40]
	mov	esi, DWORD PTR CCDC_HSIZE_VAL_MASK[rip]
	mov	edi, DWORD PTR ccdc_cfg[rip]
	je	.L9
	cmp	QWORD PTR ccdc_cfg[rip+88], 0
	je	.L10
.L9:
	lea	edx, 31[rcx]
.L20:
	sar	edx, 5
	and	edx, esi
	lea	rsi, .LC4[rip]
	or	eax, edx
	mov	r12d, eax
	xor	eax, eax
	call	dev_dbg@PLT
	mov	esi, DWORD PTR HSIZE[rip]
	mov	edi, r12d
	call	regw@PLT
	mov	eax, DWORD PTR ccdc_cfg[rip+20]
	cmp	eax, DWORD PTR CCDC_FRMFMT_INTERLACED[rip]
	je	.L23
	cmp	eax, DWORD PTR CCDC_FRMFMT_PROGRESSIVE[rip]
	je	.L24
.L14:
	mov	edi, DWORD PTR ccdc_cfg[rip]
	lea	rsi, .LC6[rip]
	xor	eax, eax
	call	dev_dbg@PLT
	xor	eax, eax
	pop	r12
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L2:
	.cfi_restore_state
	or	edx, DWORD PTR CCDC_DATA_PACK_ENABLE[rip]
	jmp	.L3
	.p2align 4,,10
	.p2align 3
.L22:
	mov	eax, DWORD PTR EFAULT[rip]
	pop	r12
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	neg	eax
	ret
	.p2align 4,,10
	.p2align 3
.L23:
	.cfi_restore_state
	cmp	QWORD PTR ccdc_cfg[rip+32], 0
	mov	esi, DWORD PTR SDOFST[rip]
	je	.L13
	mov	edi, DWORD PTR CCDC_SDOFST_INTERLACE_INVERSE[rip]
	call	regw@PLT
	mov	edx, DWORD PTR CCDC_SDOFST_INTERLACE_INVERSE[rip]
	mov	edi, DWORD PTR ccdc_cfg[rip]
	xor	eax, eax
	lea	rsi, .LC5[rip]
	call	dev_dbg@PLT
	jmp	.L14
	.p2align 4,,10
	.p2align 3
.L10:
	lea	edx, 31[rcx+rcx]
	jmp	.L20
	.p2align 4,,10
	.p2align 3
.L24:
	cmp	QWORD PTR ccdc_cfg[rip+32], 0
	mov	esi, DWORD PTR SDOFST[rip]
	je	.L15
	mov	edi, DWORD PTR CCDC_SDOFST_PROGRESSIVE_INVERSE[rip]
	call	regw@PLT
	mov	edx, DWORD PTR CCDC_SDOFST_PROGRESSIVE_INVERSE[rip]
	mov	edi, DWORD PTR ccdc_cfg[rip]
	xor	eax, eax
	lea	rsi, .LC5[rip]
	call	dev_dbg@PLT
	jmp	.L14
	.p2align 4,,10
	.p2align 3
.L13:
	mov	edi, DWORD PTR CCDC_SDOFST_INTERLACE_NORMAL[rip]
	call	regw@PLT
	mov	edx, DWORD PTR CCDC_SDOFST_INTERLACE_NORMAL[rip]
	mov	edi, DWORD PTR ccdc_cfg[rip]
	xor	eax, eax
	lea	rsi, .LC5[rip]
	call	dev_dbg@PLT
	jmp	.L14
	.p2align 4,,10
	.p2align 3
.L15:
	mov	edi, DWORD PTR CCDC_SDOFST_PROGRESSIVE_NORMAL[rip]
	call	regw@PLT
	mov	edx, DWORD PTR CCDC_SDOFST_PROGRESSIVE_NORMAL[rip]
	mov	edi, DWORD PTR ccdc_cfg[rip]
	xor	eax, eax
	lea	rsi, .LC5[rip]
	call	dev_dbg@PLT
	jmp	.L14
	.cfi_endproc
.LFE0:
	.size	ccdc_config_raw, .-ccdc_config_raw
	.comm	ccdc_cfg,128,32
	.comm	SDOFST,4,4
	.comm	MODESET,4,4
	.comm	MEDFILT,4,4
	.comm	HSIZE,4,4
	.comm	GAMMAWD,4,4
	.comm	EFAULT,4,4
	.comm	DATAOFST,4,4
	.comm	CCDC_YCINSWP_RAW,4,4
	.comm	CCDC_VD_POL_SHIFT,4,4
	.comm	CCDC_VD_POL_MASK,4,4
	.comm	CCDC_VDHDOUT_INPUT,4,4
	.comm	CCDC_SDOFST_PROGRESSIVE_NORMAL,4,4
	.comm	CCDC_SDOFST_PROGRESSIVE_INVERSE,4,4
	.comm	CCDC_SDOFST_INTERLACE_NORMAL,4,4
	.comm	CCDC_SDOFST_INTERLACE_INVERSE,4,4
	.comm	CCDC_RAW_IP_MODE,4,4
	.comm	CCDC_PIX_FMT_SHIFT,4,4
	.comm	CCDC_PIX_FMT_MASK,4,4
	.comm	CCDC_MFILT2_SHIFT,4,4
	.comm	CCDC_MFILT1_SHIFT,4,4
	.comm	CCDC_MED_FILT_THRESH,4,4
	.comm	CCDC_LPF_SHIFT,4,4
	.comm	CCDC_LPF_MASK,4,4
	.comm	CCDC_LATCH_ON_VSYNC_DISABLE,4,4
	.comm	CCDC_HSIZE_VAL_MASK,4,4
	.comm	CCDC_HSIZE_FLIP_SHIFT,4,4
	.comm	CCDC_HSIZE_FLIP_MASK,4,4
	.comm	CCDC_HD_POL_SHIFT,4,4
	.comm	CCDC_HD_POL_MASK,4,4
	.comm	CCDC_GAMMA_BITS_11_2,4,4
	.comm	CCDC_GAMMAWD_INPUT_SHIFT,4,4
	.comm	CCDC_FRM_FMT_SHIFT,4,4
	.comm	CCDC_FRM_FMT_MASK,4,4
	.comm	CCDC_FRMFMT_PROGRESSIVE,4,4
	.comm	CCDC_FRMFMT_INTERLACED,4,4
	.comm	CCDC_FID_POL_SHIFT,4,4
	.comm	CCDC_FID_POL_MASK,4,4
	.comm	CCDC_EXWEN_DISABLE,4,4
	.comm	CCDC_DATA_PACK_ENABLE,4,4
	.comm	CCDC_DATA_8BITS,8,8
	.comm	CCDC_DATASFT_SHIFT,4,4
	.comm	CCDC_DATASFT_MASK,4,4
	.comm	CCDC_DATAPOL_NORMAL,4,4
	.comm	CCDC_DATAOFST_V_SHIFT,4,4
	.comm	CCDC_DATAOFST_MASK,4,4
	.comm	CCDC_DATAOFST_H_SHIFT,4,4
	.comm	CCDC_CFA_MOSAIC,4,4
	.comm	CCDC_CCDCFG_WENLOG_AND,4,4
	.comm	CCDC_CCDCFG_TRGSEL_WEN,4,4
	.comm	CCDC_CCDCFG_FIDMD_LATCH_VSYNC,4,4
	.comm	CCDC_CCDCFG_EXTRG_DISABLE,4,4
	.comm	CCDC_ALAW_GAMMA_WD_MASK,4,4
	.comm	CCDC_ALAW_ENABLE,4,4
	.comm	CCDCFG,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_dm355_ccdc.c_ccdc_config_raw.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"\012Starting ccdc_config_raw...\000"
	.align	2
.LC1:
	.ascii	"\012Writing 0x%x to MODESET...\012\000"
	.align	2
.LC2:
	.ascii	"\012Writing 0x%x to GAMMAWD...\012\000"
	.align	2
.LC3:
	.ascii	"\012Writing %x to COLPTN...\012\000"
	.align	2
.LC4:
	.ascii	"\012Writing 0x%x to HSIZE...\012\000"
	.align	2
.LC5:
	.ascii	"\012Writing %x to SDOFST...\012\000"
	.align	2
.LC6:
	.ascii	"\012end of ccdc_config_raw...\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	ccdc_config_raw, %function
ccdc_config_raw:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, lr}
	ldr	r4, .L33
	ldr	r1, .L33+4
	ldr	r0, [r4]
	bl	dev_dbg
	bl	ccdc_restore_defaults
	ldr	r2, .L33+8
	ldr	r3, .L33+12
	ldr	r1, .L33+16
	ldr	r0, [r2]
	ldr	r3, [r3]
	ldr	r2, .L33+20
	ldr	ip, [r1]
	ldr	r1, .L33+24
	orr	r3, r3, r0
	ldr	r0, [r2]
	ldr	r2, .L33+28
	ldr	r1, [r1]
	orr	r3, r3, ip
	orr	r3, r3, r0
	ldr	r0, [r2]
	ldr	r2, .L33+32
	orr	r3, r3, r1
	orr	r0, r3, r0
	ldr	r1, [r2]
	bl	regw
	ldr	r2, .L33+36
	ldr	r3, .L33+40
	ldr	ip, .L33+44
	ldr	r1, [r2]
	ldr	r0, .L33+48
	ldr	r2, [r3]
	ldr	ip, [ip]
	ldr	r0, [r0]
	orr	r1, r1, r2
	ldr	r3, .L33+52
	orr	r1, r1, ip
	ldr	r2, .L33+56
	ldr	r3, [r3]
	orr	r1, r1, r0
	ldr	r0, [r4, #4]
	ldr	ip, .L33+60
	ldr	r2, [r2]
	and	r0, r0, r3
	ldr	r5, .L33+64
	ldr	lr, [ip]
	orr	r1, r1, r0, lsl r2
	ldr	ip, .L33+68
	ldr	r2, [r4, #8]
	ldr	r3, [r5]
	and	r2, r2, lr
	ldr	r5, [ip]
	ldr	ip, .L33+72
	orr	r1, r1, r2, lsl r3
	ldr	r3, [r4, #12]
	ldr	r0, .L33+76
	ldr	lr, [ip]
	ldr	r2, .L33+80
	and	r3, r3, r5
	ldr	ip, [r0]
	orr	r3, r1, r3, lsl lr
	ldr	r1, [r4, #16]
	ldr	r2, [r2]
	ldr	r0, .L33+84
	and	r1, r1, ip
	orr	r3, r3, r1, lsl r2
	ldr	r0, [r0]
	ldr	r6, .L33+88
	ldr	r2, [r4, #20]
	ldr	ip, .L33+92
	and	r2, r2, r0
	ldr	r1, [r6]
	ldr	r0, [r4, #36]
	ldr	ip, [ip]
	cmp	r0, r1
	orr	r3, r3, r2, lsl ip
	beq	.L2
	ldr	r2, [r4, #64]
	cmp	r2, #0
	bne	.L2
.L3:
	ldr	r2, [r4, #40]
	cmp	r2, #0
	beq	.L4
	ldr	r0, .L33+96
	ldr	r1, .L33+100
	ldr	r0, [r0]
	ldr	r1, [r1]
	and	r2, r2, r0
	orr	r3, r3, r2, lsl r1
.L4:
	ldr	r1, .L33+104
	ldr	r2, .L33+108
	ldr	r1, [r1]
	ldr	r5, [r4, #44]
	ldr	r2, [r2]
	and	r5, r5, r1
	ldr	r1, .L33+112
	orr	r5, r3, r5, lsl r2
	mov	r0, r5
	ldr	r1, [r1]
	bl	regw
	mov	r2, r5
	ldr	r1, .L33+116
	ldr	r0, [r4]
	bl	dev_dbg
	ldr	r3, .L33+120
	ldr	r0, [r4, #48]
	ldr	r2, [r3]
	ldr	r3, .L33+124
	and	r0, r0, r2
	ldr	r1, [r3]
	bl	regw
	ldr	r2, .L33+128
	ldr	r3, .L33+132
	ldr	r0, .L33+136
	ldr	r1, [r4, #64]
	ldr	r2, [r2]
	ldr	r3, [r3]
	ldr	r5, [r0]
	cmp	r1, #0
	orr	r3, r5, r3, lsl r2
	beq	.L5
	ldr	r1, .L33+140
	ldr	r5, [r4, #60]
	ldr	r0, [r1]
	ldr	r1, .L33+144
	and	r5, r5, r0
	ldr	r1, [r1]
	orr	r5, r3, r5, lsl r2
	orr	r3, r5, r1
.L5:
	ldr	r1, .L33+148
	ldr	r2, .L33+152
	ldr	r0, [r1]
	ldr	r5, [r4, #56]
	ldr	r2, [r2]
	ldr	r1, [r4, #52]
	lsl	r5, r5, r0
	orr	r5, r5, r1, lsl r2
	ldr	r2, .L33+156
	orr	r5, r5, r3
	ldr	r1, [r2]
	mov	r0, r5
	bl	regw
	mov	r2, r5
	ldr	r1, .L33+160
	ldr	r0, [r4]
	bl	dev_dbg
	mov	r2, #1
	ldr	r1, [r4, #16]
	ldr	r0, .L33+164
	bl	ccdc_setwin
	ldr	r0, .L33+168
	bl	ccdc_config_black_clamp
	ldr	r0, .L33+172
	bl	ccdc_config_black_compense
	ldr	r0, .L33+176
	bl	ccdc_config_vdfc
	cmp	r0, #0
	blt	.L29
	ldr	r0, .L33+180
	bl	ccdc_config_csc
	ldr	r1, .L33+184
	add	r0, r1, #4
	bl	ccdc_config_color_patterns
	bl	ccdc_config_gain_offset
	mov	r2, r5
	ldr	r1, .L33+188
	ldr	r0, [r4]
	bl	dev_dbg
	ldr	r3, .L33+192
	ldr	r1, .L33+196
	ldr	r2, [r3]
	ldr	r3, [r4, #72]
	ldr	r1, [r1]
	ldr	r0, .L33+200
	ldr	ip, [r4, #68]
	and	r3, r3, r2
	lsl	r3, r3, r1
	ldr	r0, [r0]
	ldr	r1, .L33+204
	and	r2, r2, ip
	orr	r0, r3, r2, lsl r0
	ldr	r1, [r1]
	bl	regw
	ldr	r3, .L33+208
	ldr	ip, .L33+212
	ldr	r1, [r6]
	ldr	r0, [r4, #36]
	ldr	r3, [r3]
	ldr	r2, [r4, #24]
	ldr	r5, [ip]
	and	r2, r2, r3
	cmp	r0, r1
	lsl	r5, r2, r5
	beq	.L30
	ldr	r2, [r4, #64]
	ldr	r3, .L33+216
	cmp	r2, #0
	ldr	r2, [r3]
	ldr	r3, [r4, #32]
	ldr	r0, [r4]
	lsleq	r3, r3, #1
.L26:
	add	r3, r3, #31
	and	r2, r2, r3, asr #5
	ldr	r1, .L33+220
	orr	r5, r2, r5
	bl	dev_dbg
	ldr	r3, .L33+224
	mov	r0, r5
	ldr	r1, [r3]
	bl	regw
	ldr	r2, .L33+228
	ldr	r3, [r4, #16]
	ldr	r2, [r2]
	cmp	r3, r2
	beq	.L31
	ldr	r2, .L33+232
	ldr	r2, [r2]
	cmp	r3, r2
	beq	.L32
.L14:
	ldr	r0, [r4]
	ldr	r1, .L33+236
	bl	dev_dbg
	mov	r0, #0
	pop	{r4, r5, r6, pc}
.L2:
	ldr	r2, .L33+240
	ldr	r2, [r2]
	orr	r3, r3, r2
	b	.L3
.L29:
	ldr	r3, .L33+244
	ldr	r0, [r3]
	rsb	r0, r0, #0
	pop	{r4, r5, r6, pc}
.L30:
	ldr	r2, .L33+216
	ldr	r3, [r4, #32]
	ldr	r2, [r2]
	ldr	r0, [r4]
	b	.L26
.L31:
	ldr	r2, [r4, #28]
	ldr	r3, .L33+248
	cmp	r2, #0
	ldr	r1, [r3]
	ldrne	r5, .L33+252
	ldreq	r5, .L33+256
.L27:
	ldr	r0, [r5]
	bl	regw
	ldr	r2, [r5]
	ldr	r1, .L33+260
	ldr	r0, [r4]
	bl	dev_dbg
	b	.L14
.L32:
	ldr	r2, [r4, #28]
	ldr	r3, .L33+248
	cmp	r2, #0
	ldr	r1, [r3]
	ldrne	r5, .L33+264
	ldreq	r5, .L33+268
	b	.L27
.L34:
	.align	2
.L33:
	.word	ccdc_cfg
	.word	.LC0
	.word	CCDC_CCDCFG_FIDMD_LATCH_VSYNC
	.word	CCDC_YCINSWP_RAW
	.word	CCDC_CCDCFG_WENLOG_AND
	.word	CCDC_CCDCFG_TRGSEL_WEN
	.word	CCDC_CCDCFG_EXTRG_DISABLE
	.word	CCDC_LATCH_ON_VSYNC_DISABLE
	.word	CCDCFG
	.word	CCDC_VDHDOUT_INPUT
	.word	CCDC_RAW_IP_MODE
	.word	CCDC_DATAPOL_NORMAL
	.word	CCDC_EXWEN_DISABLE
	.word	CCDC_VD_POL_MASK
	.word	CCDC_VD_POL_SHIFT
	.word	CCDC_HD_POL_MASK
	.word	CCDC_HD_POL_SHIFT
	.word	CCDC_FID_POL_MASK
	.word	CCDC_FID_POL_SHIFT
	.word	CCDC_FRM_FMT_MASK
	.word	CCDC_FRM_FMT_SHIFT
	.word	CCDC_PIX_FMT_MASK
	.word	CCDC_DATA_8BITS
	.word	CCDC_PIX_FMT_SHIFT
	.word	CCDC_LPF_MASK
	.word	CCDC_LPF_SHIFT
	.word	CCDC_DATASFT_MASK
	.word	CCDC_DATASFT_SHIFT
	.word	MODESET
	.word	.LC1
	.word	CCDC_MED_FILT_THRESH
	.word	MEDFILT
	.word	CCDC_GAMMAWD_INPUT_SHIFT
	.word	CCDC_GAMMA_BITS_11_2
	.word	CCDC_CFA_MOSAIC
	.word	CCDC_ALAW_GAMMA_WD_MASK
	.word	CCDC_ALAW_ENABLE
	.word	CCDC_MFILT2_SHIFT
	.word	CCDC_MFILT1_SHIFT
	.word	GAMMAWD
	.word	.LC2
	.word	ccdc_cfg+32
	.word	ccdc_cfg+96
	.word	ccdc_cfg+92
	.word	ccdc_cfg+88
	.word	ccdc_cfg+84
	.word	ccdc_cfg+76
	.word	.LC3
	.word	CCDC_DATAOFST_MASK
	.word	CCDC_DATAOFST_V_SHIFT
	.word	CCDC_DATAOFST_H_SHIFT
	.word	DATAOFST
	.word	CCDC_HSIZE_FLIP_MASK
	.word	CCDC_HSIZE_FLIP_SHIFT
	.word	CCDC_HSIZE_VAL_MASK
	.word	.LC4
	.word	HSIZE
	.word	CCDC_FRMFMT_INTERLACED
	.word	CCDC_FRMFMT_PROGRESSIVE
	.word	.LC6
	.word	CCDC_DATA_PACK_ENABLE
	.word	EFAULT
	.word	SDOFST
	.word	CCDC_SDOFST_INTERLACE_INVERSE
	.word	CCDC_SDOFST_INTERLACE_NORMAL
	.word	.LC5
	.word	CCDC_SDOFST_PROGRESSIVE_INVERSE
	.word	CCDC_SDOFST_PROGRESSIVE_NORMAL
	.size	ccdc_config_raw, .-ccdc_config_raw
	.comm	ccdc_cfg,100,4
	.comm	SDOFST,4,4
	.comm	MODESET,4,4
	.comm	MEDFILT,4,4
	.comm	HSIZE,4,4
	.comm	GAMMAWD,4,4
	.comm	EFAULT,4,4
	.comm	DATAOFST,4,4
	.comm	CCDC_YCINSWP_RAW,4,4
	.comm	CCDC_VD_POL_SHIFT,4,4
	.comm	CCDC_VD_POL_MASK,4,4
	.comm	CCDC_VDHDOUT_INPUT,4,4
	.comm	CCDC_SDOFST_PROGRESSIVE_NORMAL,4,4
	.comm	CCDC_SDOFST_PROGRESSIVE_INVERSE,4,4
	.comm	CCDC_SDOFST_INTERLACE_NORMAL,4,4
	.comm	CCDC_SDOFST_INTERLACE_INVERSE,4,4
	.comm	CCDC_RAW_IP_MODE,4,4
	.comm	CCDC_PIX_FMT_SHIFT,4,4
	.comm	CCDC_PIX_FMT_MASK,4,4
	.comm	CCDC_MFILT2_SHIFT,4,4
	.comm	CCDC_MFILT1_SHIFT,4,4
	.comm	CCDC_MED_FILT_THRESH,4,4
	.comm	CCDC_LPF_SHIFT,4,4
	.comm	CCDC_LPF_MASK,4,4
	.comm	CCDC_LATCH_ON_VSYNC_DISABLE,4,4
	.comm	CCDC_HSIZE_VAL_MASK,4,4
	.comm	CCDC_HSIZE_FLIP_SHIFT,4,4
	.comm	CCDC_HSIZE_FLIP_MASK,4,4
	.comm	CCDC_HD_POL_SHIFT,4,4
	.comm	CCDC_HD_POL_MASK,4,4
	.comm	CCDC_GAMMA_BITS_11_2,4,4
	.comm	CCDC_GAMMAWD_INPUT_SHIFT,4,4
	.comm	CCDC_FRM_FMT_SHIFT,4,4
	.comm	CCDC_FRM_FMT_MASK,4,4
	.comm	CCDC_FRMFMT_PROGRESSIVE,4,4
	.comm	CCDC_FRMFMT_INTERLACED,4,4
	.comm	CCDC_FID_POL_SHIFT,4,4
	.comm	CCDC_FID_POL_MASK,4,4
	.comm	CCDC_EXWEN_DISABLE,4,4
	.comm	CCDC_DATA_PACK_ENABLE,4,4
	.comm	CCDC_DATA_8BITS,4,4
	.comm	CCDC_DATASFT_SHIFT,4,4
	.comm	CCDC_DATASFT_MASK,4,4
	.comm	CCDC_DATAPOL_NORMAL,4,4
	.comm	CCDC_DATAOFST_V_SHIFT,4,4
	.comm	CCDC_DATAOFST_MASK,4,4
	.comm	CCDC_DATAOFST_H_SHIFT,4,4
	.comm	CCDC_CFA_MOSAIC,4,4
	.comm	CCDC_CCDCFG_WENLOG_AND,4,4
	.comm	CCDC_CCDCFG_TRGSEL_WEN,4,4
	.comm	CCDC_CCDCFG_FIDMD_LATCH_VSYNC,4,4
	.comm	CCDC_CCDCFG_EXTRG_DISABLE,4,4
	.comm	CCDC_ALAW_GAMMA_WD_MASK,4,4
	.comm	CCDC_ALAW_ENABLE,4,4
	.comm	CCDCFG,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
