	.file	"extr_uncore.c_amd_uncore_event_init.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	amd_uncore_event_init, @function
amd_uncore_event_init:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	push	rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	push	rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	mov	rax, QWORD PTR 24[rdi]
	mov	rax, QWORD PTR [rax]
	cmp	QWORD PTR 8[rdi], rax
	je	.L2
	mov	r12d, DWORD PTR ENOENT[rip]
	neg	r12d
.L1:
	mov	eax, r12d
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L2:
	.cfi_restore_state
	mov	rbx, rdi
	call	is_sampling_event@PLT
	test	rax, rax
	jne	.L16
	mov	r12d, DWORD PTR [rbx]
	and	r12d, DWORD PTR PERF_ATTACH_TASK[rip]
	jne	.L16
	mov	eax, DWORD PTR 16[rbx]
	and	eax, DWORD PTR AMD64_RAW_EVENT_MASK_NB[rip]
	mov	DWORD PTR 36[rbx], -1
	mov	DWORD PTR 32[rbx], eax
	mov	eax, DWORD PTR 4[rbx]
	test	eax, eax
	js	.L16
	cmp	QWORD PTR l3_mask[rip], 0
	jne	.L18
.L8:
	mov	rdi, rbx
	call	event_to_amd_uncore@PLT
	test	rax, rax
	je	.L19
	mov	eax, DWORD PTR [rax]
	mov	DWORD PTR 4[rbx], eax
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L16:
	mov	r12d, DWORD PTR EINVAL[rip]
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbp
	.cfi_def_cfa_offset 16
	neg	r12d
	mov	eax, r12d
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L18:
	.cfi_restore_state
	mov	rdi, rbx
	call	is_llc_event@PLT
	test	rax, rax
	je	.L8
	mov	edi, DWORD PTR 4[rbx]
	call	cpu_data@PLT
	cdq
	shr	edx, 30
	lea	ebp, [rdx+rax]
	and	ebp, 3
	sub	ebp, edx
	add	ebp, ebp
	cmp	DWORD PTR smp_num_siblings[rip], 1
	jle	.L10
	mov	edi, DWORD PTR 4[rbx]
	call	cpu_data@PLT
	sar	rax, 32
	and	eax, 1
	add	ebp, eax
.L10:
	mov	ecx, DWORD PTR AMD64_L3_THREAD_SHIFT[rip]
	mov	eax, 1
	add	ecx, ebp
	sal	rax, cl
	and	eax, DWORD PTR AMD64_L3_THREAD_MASK[rip]
	or	eax, DWORD PTR 32[rbx]
	or	eax, DWORD PTR AMD64_L3_SLICE_MASK[rip]
	mov	DWORD PTR 32[rbx], eax
	jmp	.L8
	.p2align 4,,10
	.p2align 3
.L19:
	mov	r12d, DWORD PTR ENODEV[rip]
	neg	r12d
	jmp	.L1
	.cfi_endproc
.LFE0:
	.size	amd_uncore_event_init, .-amd_uncore_event_init
	.comm	smp_num_siblings,4,4
	.comm	l3_mask,8,8
	.comm	PERF_ATTACH_TASK,4,4
	.comm	ENOENT,4,4
	.comm	ENODEV,4,4
	.comm	EINVAL,4,4
	.comm	AMD64_RAW_EVENT_MASK_NB,4,4
	.comm	AMD64_L3_THREAD_SHIFT,4,4
	.comm	AMD64_L3_THREAD_MASK,4,4
	.comm	AMD64_L3_SLICE_MASK,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_uncore.c_amd_uncore_event_init.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	amd_uncore_event_init, %function
amd_uncore_event_init:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, lr}
	ldr	r3, [r0, #16]
	ldr	r2, [r0, #8]
	ldr	r3, [r3]
	ldr	r1, .L21
	sub	sp, sp, #24
	cmp	r2, r3
	ldr	r1, [r1]
	str	r1, [sp, #20]
	mov	r1,#0
	beq	.L2
	ldr	r3, .L21+4
	ldr	r5, [r3]
	rsb	r5, r5, #0
.L1:
	ldr	r3, .L21
	ldr	r2, [r3]
	ldr	r3, [sp, #20]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L19
	mov	r0, r5
	add	sp, sp, #24
	@ sp needed
	pop	{r4, r5, r6, pc}
.L2:
	mov	r4, r0
	bl	is_sampling_event
	cmp	r0, #0
	bne	.L17
	ldr	r3, .L21+8
	ldr	r5, [r4]
	ldr	r3, [r3]
	ands	r5, r5, r3
	bne	.L17
	mvn	r2, #0
	ldr	r1, .L21+12
	ldr	r3, [r4, #12]
	ldr	r0, [r1]
	ldr	r1, [r4, #4]
	and	r3, r3, r0
	cmp	r1, #0
	str	r3, [r4, #20]
	str	r2, [r4, #24]
	blt	.L17
	ldr	r3, .L21+16
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L20
.L8:
	mov	r0, r4
	bl	event_to_amd_uncore
	cmp	r0, #0
	ldreq	r3, .L21+20
	ldrne	r3, [r0]
	ldreq	r5, [r3]
	strne	r3, [r4, #4]
	rsbeq	r5, r5, #0
	b	.L1
.L17:
	ldr	r3, .L21+24
	ldr	r5, [r3]
	rsb	r5, r5, #0
	b	.L1
.L20:
	mov	r0, r4
	bl	is_llc_event
	cmp	r0, #0
	beq	.L8
	ldr	r1, [r4, #4]
	add	r0, sp, #4
	bl	cpu_data
	ldr	r3, [sp, #4]
	ldr	r1, .L21+28
	rsbs	r2, r3, #0
	ldr	r1, [r1]
	and	r2, r2, #3
	and	r3, r3, #3
	rsbpl	r3, r2, #0
	cmp	r1, #1
	lsl	r6, r3, #1
	ble	.L10
	ldr	r1, [r4, #4]
	add	r0, sp, #12
	bl	cpu_data
	ldr	r3, [sp, #16]
	and	r3, r3, #1
	add	r6, r6, r3
.L10:
	mov	r1, #1
	ldr	r2, .L21+32
	ldr	r3, .L21+36
	ldr	r0, [r2]
	ldr	r3, [r3]
	ldr	r2, .L21+40
	add	r6, r6, r0
	and	r3, r3, r1, lsl r6
	ldr	r2, [r2]
	ldr	r1, [r4, #20]
	orr	r2, r2, r1
	orr	r3, r3, r2
	str	r3, [r4, #20]
	b	.L8
.L19:
	bl	__stack_chk_fail
.L22:
	.align	2
.L21:
	.word	.LC0
	.word	ENOENT
	.word	PERF_ATTACH_TASK
	.word	AMD64_RAW_EVENT_MASK_NB
	.word	l3_mask
	.word	ENODEV
	.word	EINVAL
	.word	smp_num_siblings
	.word	AMD64_L3_THREAD_SHIFT
	.word	AMD64_L3_THREAD_MASK
	.word	AMD64_L3_SLICE_MASK
	.size	amd_uncore_event_init, .-amd_uncore_event_init
	.comm	smp_num_siblings,4,4
	.comm	l3_mask,4,4
	.comm	PERF_ATTACH_TASK,4,4
	.comm	ENOENT,4,4
	.comm	ENODEV,4,4
	.comm	EINVAL,4,4
	.comm	AMD64_RAW_EVENT_MASK_NB,4,4
	.comm	AMD64_L3_THREAD_SHIFT,4,4
	.comm	AMD64_L3_THREAD_MASK,4,4
	.comm	AMD64_L3_SLICE_MASK,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
