	.file	"extr_radeon_clocks.c_radeon_legacy_get_engine_clock.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	radeon_legacy_get_engine_clock
	.type	radeon_legacy_get_engine_clock, @function
radeon_legacy_get_engine_clock:
.LFB0:
	.cfi_startproc
	endbr64
	push	r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	push	r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	push	r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	mov	r12, rdi
	mov	edi, DWORD PTR RADEON_M_SPLL_REF_FB_DIV[rip]
	push	rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	push	rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	call	RREG32_PLL@PLT
	mov	edi, DWORD PTR RADEON_M_SPLL_REF_FB_DIV[rip]
	mov	ebp, DWORD PTR [r12]
	mov	r14d, DWORD PTR RADEON_SPLL_FB_DIV_SHIFT[rip]
	mov	r13d, DWORD PTR RADEON_SPLL_FB_DIV_MASK[rip]
	mov	ebx, eax
	call	RREG32_PLL@PLT
	and	eax, DWORD PTR RADEON_M_SPLL_REF_DIV_MASK[rip]
	mov	r12d, eax
	jne	.L10
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	eax, r12d
	pop	rbp
	.cfi_def_cfa_offset 32
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L10:
	.cfi_restore_state
	mov	ecx, r14d
	mov	edi, DWORD PTR RADEON_SCLK_CNTL[rip]
	sar	ebx, cl
	and	ebx, r13d
	lea	eax, [rbx+rbx]
	imul	eax, ebp
	cdq
	idiv	r12d
	mov	r12d, eax
	call	RREG32_PLL@PLT
	and	eax, DWORD PTR RADEON_SCLK_SRC_SEL_MASK[rip]
	cmp	eax, 2
	je	.L11
	cmp	eax, 3
	je	.L12
	mov	edx, r12d
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	pop	rbp
	.cfi_def_cfa_offset 32
	sar	edx, 3
	cmp	eax, 4
	cmove	r12d, edx
	mov	eax, r12d
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L11:
	.cfi_restore_state
	sar	r12d
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	pop	rbp
	.cfi_def_cfa_offset 32
	mov	eax, r12d
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L12:
	.cfi_restore_state
	sar	r12d, 2
	pop	rbx
	.cfi_def_cfa_offset 40
	pop	rbp
	.cfi_def_cfa_offset 32
	mov	eax, r12d
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE0:
	.size	radeon_legacy_get_engine_clock, .-radeon_legacy_get_engine_clock
	.comm	RADEON_SPLL_FB_DIV_SHIFT,4,4
	.comm	RADEON_SPLL_FB_DIV_MASK,4,4
	.comm	RADEON_SCLK_SRC_SEL_MASK,4,4
	.comm	RADEON_SCLK_CNTL,4,4
	.comm	RADEON_M_SPLL_REF_FB_DIV,4,4
	.comm	RADEON_M_SPLL_REF_DIV_MASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_radeon_clocks.c_radeon_legacy_get_engine_clock.c"
	.text
	.global	__aeabi_idiv
	.align	2
	.global	radeon_legacy_get_engine_clock
	.syntax unified
	.arm
	.fpu softvfp
	.type	radeon_legacy_get_engine_clock, %function
radeon_legacy_get_engine_clock:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	ldr	r7, .L11
	mov	r4, r0
	ldr	r0, [r7]
	bl	RREG32_PLL
	ldr	r3, .L11+4
	ldr	r2, .L11+8
	mov	r6, r0
	ldr	r0, [r7]
	ldr	r5, [r3]
	ldr	r7, [r4]
	ldr	r8, [r2]
	bl	RREG32_PLL
	ldr	r3, .L11+12
	ldr	r1, [r3]
	ands	r4, r0, r1
	bne	.L10
.L1:
	mov	r0, r4
	pop	{r4, r5, r6, r7, r8, pc}
.L10:
	and	r0, r5, r6, asr r8
	lsl	r0, r0, #1
	mov	r1, r4
	mul	r0, r7, r0
	bl	__aeabi_idiv
	ldr	r3, .L11+16
	mov	r4, r0
	ldr	r0, [r3]
	bl	RREG32_PLL
	ldr	r3, .L11+20
	ldr	r3, [r3]
	and	r0, r0, r3
	cmp	r0, #2
	asreq	r4, r4, #1
	beq	.L1
	cmp	r0, #3
	asreq	r4, r4, #2
	beq	.L1
	cmp	r0, #4
	asreq	r4, r4, #3
	mov	r0, r4
	pop	{r4, r5, r6, r7, r8, pc}
.L12:
	.align	2
.L11:
	.word	RADEON_M_SPLL_REF_FB_DIV
	.word	RADEON_SPLL_FB_DIV_MASK
	.word	RADEON_SPLL_FB_DIV_SHIFT
	.word	RADEON_M_SPLL_REF_DIV_MASK
	.word	RADEON_SCLK_CNTL
	.word	RADEON_SCLK_SRC_SEL_MASK
	.size	radeon_legacy_get_engine_clock, .-radeon_legacy_get_engine_clock
	.comm	RADEON_SPLL_FB_DIV_SHIFT,4,4
	.comm	RADEON_SPLL_FB_DIV_MASK,4,4
	.comm	RADEON_SCLK_SRC_SEL_MASK,4,4
	.comm	RADEON_SCLK_CNTL,4,4
	.comm	RADEON_M_SPLL_REF_FB_DIV,4,4
	.comm	RADEON_M_SPLL_REF_DIV_MASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
