	.file	"extr_vsc7326.c_mac_set_speed_duplex_fc.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	mac_set_speed_duplex_fc, @function
mac_set_speed_duplex_fc:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	mov	r14d, ecx
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	mov	r12d, edx
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	rbx, rdi
	sub	rsp, 40
	.cfi_def_cfa_offset 96
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 24[rsp], rax
	xor	eax, eax
	mov	rax, QWORD PTR 8[rdi]
	mov	r13d, DWORD PTR [rax]
	test	esi, esi
	js	.L2
	cmp	DWORD PTR SPEED_10[rip], esi
	mov	ebp, esi
	je	.L3
	cmp	DWORD PTR SPEED_100[rip], esi
	je	.L3
	cmp	DWORD PTR SPEED_1000[rip], esi
	jne	.L27
.L3:
	test	r12d, r12d
	jle	.L18
	cmp	DWORD PTR DUPLEX_FULL[rip], r12d
	mov	eax, -1
	je	.L18
	.p2align 4,,10
	.p2align 3
.L1:
	mov	rcx, QWORD PTR 24[rsp]
	xor	rcx, QWORD PTR fs:40
	jne	.L37
	add	rsp, 40
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L18:
	.cfi_restore_state
	mov	edi, r13d
	lea	r15, 20[rsp]
	call	REG_MODE_CFG@PLT
	mov	edi, DWORD PTR [rbx]
	mov	rdx, r15
	mov	esi, eax
	call	vsc_read@PLT
	mov	eax, DWORD PTR 20[rsp]
	and	eax, -16
	mov	edx, eax
	or	edx, 4
	cmp	DWORD PTR SPEED_1000[rip], ebp
	mov	DWORD PTR 20[rsp], edx
	jne	.L5
	or	eax, 12
	mov	DWORD PTR 20[rsp], eax
	mov	edx, eax
.L5:
	mov	edi, r13d
	mov	DWORD PTR 12[rsp], edx
	call	REG_MODE_CFG@PLT
	mov	edx, DWORD PTR 12[rsp]
	mov	edi, DWORD PTR [rbx]
	mov	esi, eax
	call	vsc_write@PLT
	cmp	DWORD PTR SPEED_1000[rip], ebp
	je	.L38
	cmp	DWORD PTR SPEED_100[rip], ebp
	je	.L39
	mov	DWORD PTR 20[rsp], 134
	mov	edx, 135
.L7:
	mov	edi, r13d
	mov	DWORD PTR 12[rsp], edx
	call	REG_DEV_SETUP@PLT
	mov	edx, DWORD PTR 12[rsp]
	mov	edi, DWORD PTR [rbx]
	mov	esi, eax
	call	vsc_write@PLT
	mov	edx, DWORD PTR 20[rsp]
	mov	edi, r13d
	mov	DWORD PTR 12[rsp], edx
	call	REG_DEV_SETUP@PLT
	mov	edx, DWORD PTR 12[rsp]
	mov	edi, DWORD PTR [rbx]
	mov	esi, eax
	call	vsc_write@PLT
	mov	edi, r13d
	call	REG_DBG@PLT
	mov	edi, DWORD PTR [rbx]
	mov	rdx, r15
	mov	esi, eax
	call	vsc_read@PLT
	mov	edx, DWORD PTR 20[rsp]
	xor	dh, dh
	cmp	DWORD PTR SPEED_1000[rip], ebp
	je	.L40
	cmp	DWORD PTR SPEED_100[rip], ebp
	je	.L41
	or	dh, -1
	mov	DWORD PTR 20[rsp], edx
.L10:
	mov	edi, r13d
	mov	DWORD PTR 12[rsp], edx
	call	REG_DBG@PLT
	mov	edx, DWORD PTR 12[rsp]
	mov	edi, DWORD PTR [rbx]
	mov	esi, eax
	call	vsc_write@PLT
	cmp	DWORD PTR SPEED_1000[rip], ebp
	mov	eax, 17
	mov	edi, r13d
	mov	edx, 5
	cmovne	edx, eax
	mov	DWORD PTR 12[rsp], edx
	call	REG_TX_IFG@PLT
	mov	edx, DWORD PTR 12[rsp]
	mov	edi, DWORD PTR [rbx]
	mov	esi, eax
	call	vsc_write@PLT
	cmp	DWORD PTR DUPLEX_HALF[rip], r12d
	mov	edx, 9619
	je	.L13
	xor	edx, edx
	cmp	DWORD PTR SPEED_1000[rip], ebp
	sete	dl
	lea	edx, 9623[0+rdx*8]
.L13:
	mov	edi, r13d
	mov	DWORD PTR 12[rsp], edx
	call	REG_MODE_CFG@PLT
	mov	edx, DWORD PTR 12[rsp]
	mov	edi, DWORD PTR [rbx]
	mov	esi, eax
	call	vsc_write@PLT
	jmp	.L20
	.p2align 4,,10
	.p2align 3
.L2:
	test	edx, edx
	jle	.L35
	cmp	edx, DWORD PTR DUPLEX_FULL[rip]
	jne	.L27
.L35:
	lea	r15, 20[rsp]
.L20:
	mov	edi, r13d
	call	REG_PAUSE_CFG@PLT
	mov	edi, DWORD PTR [rbx]
	mov	rdx, r15
	mov	esi, eax
	call	vsc_read@PLT
	mov	edx, DWORD PTR 20[rsp]
	mov	eax, DWORD PTR PAUSE_RX[rip]
	and	edx, -983041
	mov	r12d, edx
	or	r12d, 131072
	mov	DWORD PTR 20[rsp], r12d
	test	eax, r14d
	je	.L14
	or	edx, 393216
	mov	DWORD PTR 20[rsp], edx
	mov	r12d, edx
.L14:
	mov	edx, DWORD PTR PAUSE_TX[rip]
	test	edx, r14d
	je	.L15
	or	r12d, 524288
	mov	DWORD PTR 20[rsp], r12d
.L15:
	or	eax, edx
	cmp	eax, r14d
	jne	.L16
	or	r12d, 65536
	mov	DWORD PTR 20[rsp], r12d
.L16:
	mov	edi, r13d
	call	REG_PAUSE_CFG@PLT
	mov	edi, DWORD PTR [rbx]
	mov	edx, r12d
	mov	esi, eax
	call	vsc_write@PLT
	xor	eax, eax
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L39:
	mov	DWORD PTR 20[rsp], 132
	mov	edx, 133
	jmp	.L7
	.p2align 4,,10
	.p2align 3
.L38:
	mov	DWORD PTR 20[rsp], 130
	mov	edx, 131
	jmp	.L7
	.p2align 4,,10
	.p2align 3
.L40:
	or	dh, 4
	mov	DWORD PTR 20[rsp], edx
	jmp	.L10
	.p2align 4,,10
	.p2align 3
.L41:
	or	dh, 32
	mov	DWORD PTR 20[rsp], edx
	jmp	.L10
.L27:
	mov	eax, -1
	jmp	.L1
.L37:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	mac_set_speed_duplex_fc, .-mac_set_speed_duplex_fc
	.comm	SPEED_1000,4,4
	.comm	SPEED_100,4,4
	.comm	SPEED_10,4,4
	.comm	PAUSE_TX,4,4
	.comm	PAUSE_RX,4,4
	.comm	DUPLEX_HALF,4,4
	.comm	DUPLEX_FULL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_vsc7326.c_mac_set_speed_duplex_fc.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	mac_set_speed_duplex_fc, %function
mac_set_speed_duplex_fc:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	mov	r4, r0
	mov	r6, r3
	ldr	r0, [r0, #4]
	ldr	r3, .L38
	sub	sp, sp, #12
	subs	r5, r1, #0
	mov	r8, r2
	ldr	r3, [r3]
	str	r3, [sp, #4]
	mov	r3,#0
	ldr	r7, [r0]
	blt	.L2
	ldr	r3, .L38+4
	ldr	r3, [r3]
	cmp	r3, r5
	beq	.L3
	ldr	r3, .L38+8
	ldr	r3, [r3]
	cmp	r3, r5
	beq	.L3
	ldr	r3, .L38+12
	ldr	r3, [r3]
	cmp	r3, r5
	bne	.L27
.L3:
	cmp	r8, #0
	ble	.L18
	ldr	r3, .L38+16
	ldr	r3, [r3]
	cmp	r3, r8
	beq	.L18
.L27:
	mvn	r0, #0
	b	.L1
.L18:
	mov	r0, r7
	ldr	r10, [r4]
	bl	REG_MODE_CFG
	mov	r9, sp
	mov	r1, r0
	mov	r0, r10
	ldr	r10, .L38+12
	mov	r2, r9
	bl	vsc_read
	ldr	r3, [sp]
	ldr	r1, [r10]
	bic	r3, r3, #15
	cmp	r1, r5
	orr	r2, r3, #4
	mov	r0, r7
	orreq	r3, r3, #12
	str	r2, [sp]
	ldr	fp, [r4]
	streq	r3, [sp]
	bl	REG_MODE_CFG
	ldr	r2, [sp]
	mov	r1, r0
	mov	r0, fp
	bl	vsc_write
	ldr	r3, [r10]
	cmp	r3, r5
	moveq	r3, #130
	streq	r3, [sp]
	beq	.L7
	ldr	r3, .L38+8
	ldr	r3, [r3]
	cmp	r3, r5
	moveq	r3, #132
	movne	r3, #134
	str	r3, [sp]
.L7:
	mov	r0, r7
	ldr	fp, [r4]
	bl	REG_DEV_SETUP
	ldr	r2, [sp]
	mov	r1, r0
	orr	r2, r2, #1
	mov	r0, fp
	bl	vsc_write
	mov	r0, r7
	ldr	fp, [r4]
	bl	REG_DEV_SETUP
	ldr	r2, [sp]
	mov	r1, r0
	mov	r0, fp
	bl	vsc_write
	mov	r0, r7
	ldr	fp, [r4]
	bl	REG_DBG
	mov	r2, r9
	mov	r1, r0
	mov	r0, fp
	bl	vsc_read
	ldr	r3, [sp]
	ldr	r2, [r10]
	bic	r3, r3, #65280
	cmp	r2, r5
	orreq	r3, r3, #1024
	streq	r3, [sp]
	beq	.L10
	ldr	r2, .L38+8
	ldr	r2, [r2]
	cmp	r2, r5
	orreq	r3, r3, #8192
	orrne	r3, r3, #65280
	str	r3, [sp]
.L10:
	mov	r0, r7
	ldr	fp, [r4]
	bl	REG_DBG
	ldr	r2, [sp]
	mov	r1, r0
	mov	r0, fp
	bl	vsc_write
	mov	r0, r7
	ldr	fp, [r4]
	bl	REG_TX_IFG
	ldr	r2, [r10]
	mov	r1, r0
	cmp	r2, r5
	moveq	r2, #5
	movne	r2, #17
	mov	r0, fp
	bl	vsc_write
	ldr	r3, .L38+20
	ldr	r3, [r3]
	cmp	r3, r8
	beq	.L24
	ldr	r3, [r10]
	ldr	r2, .L38+24
	ldr	r1, .L38+28
	cmp	r3, r5
	moveq	r5, r2
	movne	r5, r1
.L13:
	mov	r0, r7
	ldr	r8, [r4]
	bl	REG_MODE_CFG
	mov	r2, r5
	mov	r1, r0
	mov	r0, r8
	bl	vsc_write
.L20:
	mov	r0, r7
	ldr	r5, [r4]
	bl	REG_PAUSE_CFG
	mov	r2, r9
	mov	r1, r0
	mov	r0, r5
	bl	vsc_read
	ldr	r2, [sp]
	ldr	r3, .L38+32
	bic	r2, r2, #983040
	ldr	r1, [r3]
	orr	r3, r2, #131072
	str	r3, [sp]
	ldr	r3, .L38+36
	tst	r1, r6
	ldr	r3, [r3]
	orrne	r2, r2, #393216
	strne	r2, [sp]
	tst	r3, r6
	ldrne	r2, [sp]
	orr	r1, r1, r3
	orrne	r2, r2, #524288
	strne	r2, [sp]
	cmp	r1, r6
	ldreq	r3, [sp]
	mov	r0, r7
	orreq	r3, r3, #65536
	ldr	r4, [r4]
	streq	r3, [sp]
	bl	REG_PAUSE_CFG
	ldr	r2, [sp]
	mov	r1, r0
	mov	r0, r4
	bl	vsc_write
	mov	r0, #0
.L1:
	ldr	r3, .L38
	ldr	r2, [r3]
	ldr	r3, [sp, #4]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L37
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L2:
	cmp	r2, #0
	ble	.L35
	ldr	r3, .L38+16
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L27
.L35:
	mov	r9, sp
	b	.L20
.L24:
	ldr	r5, .L38+40
	b	.L13
.L37:
	bl	__stack_chk_fail
.L39:
	.align	2
.L38:
	.word	.LC0
	.word	SPEED_10
	.word	SPEED_100
	.word	SPEED_1000
	.word	DUPLEX_FULL
	.word	DUPLEX_HALF
	.word	9631
	.word	9623
	.word	PAUSE_RX
	.word	PAUSE_TX
	.word	9619
	.size	mac_set_speed_duplex_fc, .-mac_set_speed_duplex_fc
	.comm	SPEED_1000,4,4
	.comm	SPEED_100,4,4
	.comm	SPEED_10,4,4
	.comm	PAUSE_TX,4,4
	.comm	PAUSE_RX,4,4
	.comm	DUPLEX_HALF,4,4
	.comm	DUPLEX_FULL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
