	.file	"extr_bnx2x_main.c_bnx2x_init_hw_port.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"starting port init  port %d\n"
	.text
	.p2align 4
	.type	bnx2x_init_hw_port, @function
bnx2x_init_hw_port:
.LFB0:
	.cfi_startproc
	endbr64
	push	r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	push	r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	push	r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	push	rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	push	rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	mov	rbx, rdi
	call	BP_PORT@PLT
	mov	edi, DWORD PTR NETIF_MSG_HW[rip]
	lea	rsi, .LC0[rip]
	mov	r12d, DWORD PTR PHASE_PORT1[rip]
	mov	edx, eax
	test	eax, eax
	mov	r14d, eax
	cmove	r12d, DWORD PTR PHASE_PORT0[rip]
	call	DP@PLT
	mov	esi, DWORD PTR NIG_REG_MASK_INTERRUPT_PORT0[rip]
	xor	edx, edx
	mov	rdi, rbx
	lea	ebp, 0[0+r14*4]
	add	esi, ebp
	call	REG_WR@PLT
	mov	esi, DWORD PTR BLOCK_MISC[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_PXP[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_PXP2[rip]
	mov	rdi, rbx
	mov	edx, r12d
	call	bnx2x_init_block@PLT
	mov	rdi, rbx
	call	CHIP_IS_E1x@PLT
	test	rax, rax
	je	.L97
.L4:
	mov	esi, DWORD PTR BLOCK_ATC[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_DMAE[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_PGLUE_B[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_QM[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_TCM[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_UCM[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_CCM[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_XCM[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR 24[rbx]
	mov	edx, DWORD PTR INITOP_SET[rip]
	mov	rdi, rbx
	call	bnx2x_qm_init_cid_count@PLT
	mov	rdi, rbx
	call	CNIC_SUPPORT@PLT
	test	rax, rax
	jne	.L98
.L5:
	mov	esi, DWORD PTR BLOCK_DORQ[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_BRB1[rip]
	mov	rdi, rbx
	mov	edx, r12d
	call	bnx2x_init_block@PLT
	mov	rdi, rbx
	call	CHIP_IS_E1@PLT
	test	rax, rax
	jne	.L9
	mov	rdi, rbx
	call	CHIP_IS_E1H@PLT
	test	rax, rax
	jne	.L9
	mov	rdi, rbx
	call	CHIP_MODE_IS_4_PORT@PLT
	test	rax, rax
	jne	.L99
	.p2align 4,,10
	.p2align 3
.L13:
	mov	esi, DWORD PTR BLOCK_PRS[rip]
	mov	rdi, rbx
	mov	edx, r12d
	call	bnx2x_init_block@PLT
	mov	rdi, rbx
	call	CHIP_IS_E3B0@PLT
	test	rax, rax
	jne	.L100
.L16:
	mov	esi, DWORD PTR BLOCK_TSDM[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_CSDM[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_USDM[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_XSDM[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_TSEM[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_USEM[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_CSEM[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_XSEM[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_UPB[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_XPB[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_PBF[rip]
	mov	rdi, rbx
	mov	edx, r12d
	call	bnx2x_init_block@PLT
	mov	rdi, rbx
	call	CHIP_IS_E1x@PLT
	test	rax, rax
	jne	.L101
.L27:
	mov	rdi, rbx
	call	CNIC_SUPPORT@PLT
	test	rax, rax
	jne	.L102
.L28:
	mov	esi, DWORD PTR BLOCK_CDU[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_CFC[rip]
	mov	rdi, rbx
	mov	edx, r12d
	call	bnx2x_init_block@PLT
	mov	rdi, rbx
	call	CHIP_IS_E1@PLT
	test	rax, rax
	jne	.L103
.L29:
	mov	esi, DWORD PTR BLOCK_HC[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_IGU[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_MISC_AEU[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	rdi, rbx
	call	IS_MF@PLT
	mov	rdi, rbx
	cmp	eax, 1
	sbb	r13d, r13d
	call	CHIP_IS_E1@PLT
	and	r13b, 16
	mov	esi, DWORD PTR MISC_REG_AEU_MASK_ATTN_FUNC_0[rip]
	mov	rdi, rbx
	add	r13d, 247
	mov	r8, rax
	mov	eax, r13d
	or	eax, 16
	test	r8, r8
	cmove	r13d, eax
	add	esi, ebp
	mov	edx, r13d
	call	REG_WR@PLT
	test	r14d, r14d
	je	.L32
	mov	r13d, DWORD PTR MISC_REG_AEU_ENABLE4_NIG_1[rip]
	mov	rdi, rbx
	mov	esi, r13d
	call	REG_RD@PLT
	mov	edx, DWORD PTR AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY[rip]
	mov	esi, r13d
	mov	rdi, rbx
	not	edx
	and	edx, eax
	call	REG_WR@PLT
	mov	r13d, DWORD PTR MISC_REG_AEU_ENABLE4_PXP_1[rip]
.L33:
	mov	esi, r13d
	mov	rdi, rbx
	call	REG_RD@PLT
	mov	edx, DWORD PTR AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY[rip]
	mov	esi, r13d
	mov	rdi, rbx
	not	edx
	and	edx, eax
	call	REG_WR@PLT
	mov	esi, DWORD PTR BLOCK_NIG[rip]
	mov	rdi, rbx
	mov	edx, r12d
	call	bnx2x_init_block@PLT
	mov	rdi, rbx
	call	CHIP_IS_E1x@PLT
	test	rax, rax
	je	.L104
.L35:
	mov	rdi, rbx
	call	CHIP_IS_E3@PLT
	test	rax, rax
	je	.L105
.L46:
	mov	rdi, rbx
	call	CHIP_IS_E1@PLT
	test	rax, rax
	je	.L106
.L47:
	mov	esi, DWORD PTR MISC_REG_SPIO_EVENT_EN[rip]
	mov	rdi, rbx
	call	REG_RD@PLT
	test	DWORD PTR MISC_SPIO_SPIO5[rip], eax
	je	.L53
	test	r14d, r14d
	mov	ebp, DWORD PTR MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0[rip]
	cmove	ebp, DWORD PTR MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0[rip]
	mov	rdi, rbx
	mov	esi, ebp
	call	REG_RD@PLT
	or	eax, DWORD PTR AEU_INPUTS_ATTN_BITS_SPIO5[rip]
	mov	esi, ebp
	mov	rdi, rbx
	mov	edx, eax
	call	REG_WR@PLT
.L53:
	mov	rdi, rbx
	call	CHIP_IS_E3B0@PLT
	test	rax, rax
	je	.L56
	mov	eax, DWORD PTR PTP_SUPPORTED[rip]
	or	DWORD PTR [rbx], eax
.L56:
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	xor	eax, eax
	pop	rbp
	.cfi_def_cfa_offset 32
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L9:
	.cfi_restore_state
	mov	rdi, rbx
	call	IS_MF@PLT
	test	eax, eax
	je	.L107
	mov	eax, DWORD PTR [rbx]
	and	eax, DWORD PTR ONE_PORT_FLAG[rip]
	cmp	eax, 1
	sbb	r13d, r13d
	and	r13d, 86
	add	r13d, 216
	cmp	eax, 1
	sbb	edx, edx
	and	edx, 86
	add	edx, 160
.L11:
	mov	esi, DWORD PTR BRB1_REG_PAUSE_LOW_THRESHOLD_0[rip]
	mov	rdi, rbx
	add	esi, ebp
	call	REG_WR@PLT
	mov	esi, DWORD PTR BRB1_REG_PAUSE_HIGH_THRESHOLD_0[rip]
	mov	rdi, rbx
	mov	edx, r13d
	add	esi, ebp
	call	REG_WR@PLT
	mov	rdi, rbx
	call	CHIP_MODE_IS_4_PORT@PLT
	test	rax, rax
	je	.L13
.L99:
	mov	rdi, rbx
	call	BP_PORT@PLT
	mov	esi, DWORD PTR BRB1_REG_MAC_GUARANTIED_1[rip]
	mov	edx, 40
	mov	rdi, rbx
	test	eax, eax
	cmove	esi, DWORD PTR BRB1_REG_MAC_GUARANTIED_0[rip]
	call	REG_WR@PLT
	jmp	.L13
	.p2align 4,,10
	.p2align 3
.L32:
	mov	r13d, DWORD PTR MISC_REG_AEU_ENABLE4_NIG_0[rip]
	mov	rdi, rbx
	mov	esi, r13d
	call	REG_RD@PLT
	mov	edx, DWORD PTR AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY[rip]
	mov	esi, r13d
	mov	rdi, rbx
	not	edx
	and	edx, eax
	call	REG_WR@PLT
	mov	r13d, DWORD PTR MISC_REG_AEU_ENABLE4_PXP_0[rip]
	jmp	.L33
	.p2align 4,,10
	.p2align 3
.L107:
	mov	rax, QWORD PTR 16[rbx]
	mov	edx, DWORD PTR [rax]
	mov	eax, DWORD PTR ONE_PORT_FLAG[rip]
	and	eax, DWORD PTR [rbx]
	cmp	edx, 4096
	jle	.L12
	test	eax, eax
	jne	.L58
	mov	ecx, edx
	xor	eax, eax
	sar	ecx, 6
	and	edx, 63
	setne	al
	lea	edx, 96[rcx+rax]
	lea	r13d, 56[rdx]
	jmp	.L11
	.p2align 4,,10
	.p2align 3
.L98:
	mov	esi, DWORD PTR BLOCK_TM[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR TM_REG_LIN0_SCAN_TIME[rip]
	mov	rdi, rbx
	mov	edx, 20
	add	esi, ebp
	call	REG_WR@PLT
	mov	esi, DWORD PTR TM_REG_LIN0_MAX_ACTIVE_CID[rip]
	mov	edx, 31
	mov	rdi, rbx
	add	esi, ebp
	call	REG_WR@PLT
	jmp	.L5
	.p2align 4,,10
	.p2align 3
.L97:
	mov	esi, DWORD PTR PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER[rip]
	mov	edx, 1
	mov	rdi, rbx
	call	REG_WR@PLT
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L106:
	mov	rdi, rbx
	call	IS_MF_SD@PLT
	mov	esi, DWORD PTR NIG_REG_LLH0_BRB1_DRV_MASK_MF[rip]
	xor	edx, edx
	mov	rdi, rbx
	test	rax, rax
	sete	dl
	add	esi, ebp
	add	edx, 1
	call	REG_WR@PLT
	mov	rdi, rbx
	call	CHIP_IS_E1x@PLT
	test	rax, rax
	jne	.L49
	mov	eax, DWORD PTR 4[rbx]
	mov	r12d, 1
	cmp	eax, 129
	je	.L50
	and	eax, -3
	xor	r12d, r12d
	cmp	eax, 128
	sete	r12b
	add	r12d, r12d
.L50:
	mov	rdi, rbx
	call	BP_PORT@PLT
	mov	esi, DWORD PTR NIG_REG_LLH1_CLS_TYPE[rip]
	mov	edx, r12d
	mov	rdi, rbx
	test	eax, eax
	cmove	esi, DWORD PTR NIG_REG_LLH0_CLS_TYPE[rip]
	call	REG_WR@PLT
.L49:
	mov	esi, DWORD PTR NIG_REG_LLFC_ENABLE_0[rip]
	xor	edx, edx
	mov	rdi, rbx
	add	esi, ebp
	call	REG_WR@PLT
	mov	esi, DWORD PTR NIG_REG_LLFC_OUT_EN_0[rip]
	xor	edx, edx
	mov	rdi, rbx
	add	esi, ebp
	call	REG_WR@PLT
	mov	esi, DWORD PTR NIG_REG_PAUSE_ENABLE_0[rip]
	mov	edx, 1
	mov	rdi, rbx
	add	esi, ebp
	call	REG_WR@PLT
	jmp	.L47
	.p2align 4,,10
	.p2align 3
.L105:
	mov	esi, DWORD PTR NIG_REG_XGXS_SERDES0_MODE_SEL[rip]
	mov	edx, 1
	mov	rdi, rbx
	add	esi, ebp
	call	REG_WR@PLT
	jmp	.L46
	.p2align 4,,10
	.p2align 3
.L104:
	mov	rdi, rbx
	call	IS_MF_AFEX@PLT
	mov	rdi, rbx
	test	rax, rax
	jne	.L108
	call	IS_MF_SD@PLT
	xor	r12d, r12d
	mov	rdi, rbx
	test	rax, rax
	setne	r12b
	call	BP_PORT@PLT
	add	r12d, 6
	mov	esi, DWORD PTR NIG_REG_P1_HDRS_AFTER_BASIC[rip]
	mov	rdi, rbx
	test	eax, eax
	cmove	esi, DWORD PTR NIG_REG_P0_HDRS_AFTER_BASIC[rip]
	mov	edx, r12d
	call	REG_WR@PLT
.L39:
	mov	rdi, rbx
	call	CHIP_IS_E3@PLT
	test	rax, rax
	je	.L35
	mov	rdi, rbx
	call	IS_MF@PLT
	mov	rdi, rbx
	mov	r12d, eax
	call	BP_PORT@PLT
	mov	esi, DWORD PTR NIG_REG_LLH1_MF_MODE[rip]
	mov	edx, r12d
	mov	rdi, rbx
	test	eax, eax
	cmove	esi, DWORD PTR NIG_REG_LLH_MF_MODE[rip]
	call	REG_WR@PLT
	jmp	.L35
	.p2align 4,,10
	.p2align 3
.L103:
	mov	esi, DWORD PTR HC_REG_LEADING_EDGE_0[rip]
	lea	r13d, 0[0+r14*8]
	xor	edx, edx
	mov	rdi, rbx
	add	esi, r13d
	call	REG_WR@PLT
	mov	esi, DWORD PTR HC_REG_TRAILING_EDGE_0[rip]
	xor	edx, edx
	mov	rdi, rbx
	add	esi, r13d
	call	REG_WR@PLT
	jmp	.L29
	.p2align 4,,10
	.p2align 3
.L102:
	mov	esi, DWORD PTR BLOCK_SRC[rip]
	mov	edx, r12d
	mov	rdi, rbx
	call	bnx2x_init_block@PLT
	jmp	.L28
	.p2align 4,,10
	.p2align 3
.L101:
	mov	esi, DWORD PTR PBF_REG_P0_PAUSE_ENABLE[rip]
	xor	edx, edx
	mov	rdi, rbx
	add	esi, ebp
	call	REG_WR@PLT
	mov	esi, DWORD PTR PBF_REG_P0_ARB_THRSH[rip]
	mov	rdi, rbx
	mov	edx, 565
	add	esi, ebp
	call	REG_WR@PLT
	mov	esi, DWORD PTR PBF_REG_P0_INIT_CRD[rip]
	mov	rdi, rbx
	mov	edx, 1096
	add	esi, ebp
	call	REG_WR@PLT
	mov	esi, DWORD PTR PBF_REG_INIT_P0[rip]
	mov	edx, 1
	mov	rdi, rbx
	add	esi, ebp
	call	REG_WR@PLT
	mov	edi, 50
	call	udelay@PLT
	mov	esi, DWORD PTR PBF_REG_INIT_P0[rip]
	xor	edx, edx
	mov	rdi, rbx
	add	esi, ebp
	call	REG_WR@PLT
	jmp	.L27
	.p2align 4,,10
	.p2align 3
.L100:
	mov	rdi, rbx
	call	IS_MF_AFEX@PLT
	test	rax, rax
	jne	.L109
	mov	rdi, rbx
	xor	r13d, r13d
	cmp	QWORD PTR 8[rbx], 0
	setne	r13b
	call	BP_PORT@PLT
	add	r13d, 6
	mov	esi, DWORD PTR PRS_REG_HDRS_AFTER_BASIC_PORT_1[rip]
	mov	rdi, rbx
	test	eax, eax
	cmove	esi, DWORD PTR PRS_REG_HDRS_AFTER_BASIC_PORT_0[rip]
	mov	edx, r13d
	call	REG_WR@PLT
	jmp	.L16
	.p2align 4,,10
	.p2align 3
.L12:
	cmp	eax, 1
	sbb	r13d, r13d
	and	r13d, 80
	add	r13d, 136
	cmp	eax, 1
	sbb	edx, edx
	and	edx, 80
	add	edx, 80
	jmp	.L11
	.p2align 4,,10
	.p2align 3
.L108:
	call	BP_PORT@PLT
	mov	esi, DWORD PTR NIG_REG_P1_HDRS_AFTER_BASIC[rip]
	mov	edx, 14
	mov	rdi, rbx
	test	eax, eax
	cmove	esi, DWORD PTR NIG_REG_P0_HDRS_AFTER_BASIC[rip]
	call	REG_WR@PLT
	jmp	.L39
	.p2align 4,,10
	.p2align 3
.L109:
	mov	rdi, rbx
	call	BP_PORT@PLT
	mov	esi, DWORD PTR PRS_REG_HDRS_AFTER_BASIC_PORT_1[rip]
	mov	edx, 14
	mov	rdi, rbx
	test	eax, eax
	cmove	esi, DWORD PTR PRS_REG_HDRS_AFTER_BASIC_PORT_0[rip]
	call	REG_WR@PLT
	mov	rdi, rbx
	call	BP_PORT@PLT
	mov	esi, DWORD PTR PRS_REG_HDRS_AFTER_TAG_0_PORT_1[rip]
	mov	edx, 6
	mov	rdi, rbx
	test	eax, eax
	cmove	esi, DWORD PTR PRS_REG_HDRS_AFTER_TAG_0_PORT_0[rip]
	call	REG_WR@PLT
	mov	rdi, rbx
	call	BP_PORT@PLT
	mov	esi, DWORD PTR PRS_REG_MUST_HAVE_HDRS_PORT_1[rip]
	mov	edx, 10
	mov	rdi, rbx
	test	eax, eax
	cmove	esi, DWORD PTR PRS_REG_MUST_HAVE_HDRS_PORT_0[rip]
	call	REG_WR@PLT
	jmp	.L16
	.p2align 4,,10
	.p2align 3
.L58:
	mov	r13d, 216
	mov	edx, 160
	jmp	.L11
	.cfi_endproc
.LFE0:
	.size	bnx2x_init_hw_port, .-bnx2x_init_hw_port
	.comm	TM_REG_LIN0_SCAN_TIME,4,4
	.comm	TM_REG_LIN0_MAX_ACTIVE_CID,4,4
	.comm	PTP_SUPPORTED,4,4
	.comm	PRS_REG_MUST_HAVE_HDRS_PORT_1,4,4
	.comm	PRS_REG_MUST_HAVE_HDRS_PORT_0,4,4
	.comm	PRS_REG_HDRS_AFTER_TAG_0_PORT_1,4,4
	.comm	PRS_REG_HDRS_AFTER_TAG_0_PORT_0,4,4
	.comm	PRS_REG_HDRS_AFTER_BASIC_PORT_1,4,4
	.comm	PRS_REG_HDRS_AFTER_BASIC_PORT_0,4,4
	.comm	PHASE_PORT1,4,4
	.comm	PHASE_PORT0,4,4
	.comm	PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,4,4
	.comm	PBF_REG_P0_PAUSE_ENABLE,4,4
	.comm	PBF_REG_P0_INIT_CRD,4,4
	.comm	PBF_REG_P0_ARB_THRSH,4,4
	.comm	PBF_REG_INIT_P0,4,4
	.comm	ONE_PORT_FLAG,4,4
	.comm	NIG_REG_XGXS_SERDES0_MODE_SEL,4,4
	.comm	NIG_REG_PAUSE_ENABLE_0,4,4
	.comm	NIG_REG_P1_HDRS_AFTER_BASIC,4,4
	.comm	NIG_REG_P0_HDRS_AFTER_BASIC,4,4
	.comm	NIG_REG_MASK_INTERRUPT_PORT0,4,4
	.comm	NIG_REG_LLH_MF_MODE,4,4
	.comm	NIG_REG_LLH1_MF_MODE,4,4
	.comm	NIG_REG_LLH1_CLS_TYPE,4,4
	.comm	NIG_REG_LLH0_CLS_TYPE,4,4
	.comm	NIG_REG_LLH0_BRB1_DRV_MASK_MF,4,4
	.comm	NIG_REG_LLFC_OUT_EN_0,4,4
	.comm	NIG_REG_LLFC_ENABLE_0,4,4
	.comm	NETIF_MSG_HW,4,4
	.comm	MISC_SPIO_SPIO5,4,4
	.comm	MISC_REG_SPIO_EVENT_EN,4,4
	.comm	MISC_REG_AEU_MASK_ATTN_FUNC_0,4,4
	.comm	MISC_REG_AEU_ENABLE4_PXP_1,4,4
	.comm	MISC_REG_AEU_ENABLE4_PXP_0,4,4
	.comm	MISC_REG_AEU_ENABLE4_NIG_1,4,4
	.comm	MISC_REG_AEU_ENABLE4_NIG_0,4,4
	.comm	MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0,4,4
	.comm	MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0,4,4
	.comm	INITOP_SET,4,4
	.comm	HC_REG_TRAILING_EDGE_0,4,4
	.comm	HC_REG_LEADING_EDGE_0,4,4
	.comm	BRB1_REG_PAUSE_LOW_THRESHOLD_0,4,4
	.comm	BRB1_REG_PAUSE_HIGH_THRESHOLD_0,4,4
	.comm	BRB1_REG_MAC_GUARANTIED_1,4,4
	.comm	BRB1_REG_MAC_GUARANTIED_0,4,4
	.comm	BLOCK_XSEM,4,4
	.comm	BLOCK_XSDM,4,4
	.comm	BLOCK_XPB,4,4
	.comm	BLOCK_XCM,4,4
	.comm	BLOCK_USEM,4,4
	.comm	BLOCK_USDM,4,4
	.comm	BLOCK_UPB,4,4
	.comm	BLOCK_UCM,4,4
	.comm	BLOCK_TSEM,4,4
	.comm	BLOCK_TSDM,4,4
	.comm	BLOCK_TM,4,4
	.comm	BLOCK_TCM,4,4
	.comm	BLOCK_SRC,4,4
	.comm	BLOCK_QM,4,4
	.comm	BLOCK_PXP2,4,4
	.comm	BLOCK_PXP,4,4
	.comm	BLOCK_PRS,4,4
	.comm	BLOCK_PGLUE_B,4,4
	.comm	BLOCK_PBF,4,4
	.comm	BLOCK_NIG,4,4
	.comm	BLOCK_MISC_AEU,4,4
	.comm	BLOCK_MISC,4,4
	.comm	BLOCK_IGU,4,4
	.comm	BLOCK_HC,4,4
	.comm	BLOCK_DORQ,4,4
	.comm	BLOCK_DMAE,4,4
	.comm	BLOCK_CSEM,4,4
	.comm	BLOCK_CSDM,4,4
	.comm	BLOCK_CFC,4,4
	.comm	BLOCK_CDU,4,4
	.comm	BLOCK_CCM,4,4
	.comm	BLOCK_BRB1,4,4
	.comm	BLOCK_ATC,4,4
	.comm	AEU_INPUTS_ATTN_BITS_SPIO5,4,4
	.comm	AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_bnx2x_main.c_bnx2x_init_hw_port.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"starting port init  port %d\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	bnx2x_init_hw_port, %function
bnx2x_init_hw_port:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, lr}
	mov	r4, r0
	bl	BP_PORT
	subs	r6, r0, #0
	ldrne	r3, .L107
	ldreq	r3, .L107+4
	mov	r2, r6
	ldr	r5, [r3]
	ldr	r3, .L107+8
	ldr	r1, .L107+12
	ldr	r0, [r3]
	bl	DP
	ldr	r3, .L107+16
	mov	r2, #0
	ldr	r1, [r3]
	mov	r0, r4
	add	r1, r1, r6, lsl #2
	bl	REG_WR
	ldr	r3, .L107+20
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+24
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+28
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	mov	r0, r4
	bl	CHIP_IS_E1x
	cmp	r0, #0
	lsl	r9, r6, #2
	beq	.L95
.L4:
	ldr	r3, .L107+32
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+36
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+40
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+44
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+48
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+52
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+56
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+60
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+64
	ldr	r1, [r4, #16]
	ldr	r2, [r3]
	mov	r0, r4
	bl	bnx2x_qm_init_cid_count
	mov	r0, r4
	bl	CNIC_SUPPORT
	cmp	r0, #0
	bne	.L96
.L5:
	ldr	r3, .L107+68
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+72
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	mov	r0, r4
	bl	CHIP_IS_E1
	cmp	r0, #0
	bne	.L9
	mov	r0, r4
	bl	CHIP_IS_E1H
	cmp	r0, #0
	bne	.L9
	mov	r0, r4
	bl	CHIP_MODE_IS_4_PORT
	cmp	r0, #0
	bne	.L97
.L13:
	ldr	r3, .L107+76
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	mov	r0, r4
	bl	CHIP_IS_E3B0
	cmp	r0, #0
	bne	.L98
.L16:
	ldr	r3, .L107+80
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+84
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+88
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+92
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+96
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+100
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+104
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+108
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+112
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+116
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+120
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	mov	r0, r4
	bl	CHIP_IS_E1x
	cmp	r0, #0
	bne	.L99
.L27:
	mov	r0, r4
	bl	CNIC_SUPPORT
	cmp	r0, #0
	bne	.L100
.L28:
	ldr	r3, .L107+124
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+128
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	mov	r0, r4
	bl	CHIP_IS_E1
	cmp	r0, #0
	bne	.L101
.L29:
	ldr	r3, .L107+132
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+136
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+140
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	mov	r0, r4
	bl	IS_MF
	mov	r3, r0
	mov	r0, r4
	cmp	r3, #0
	moveq	r7, #7
	movne	r7, #247
	bl	CHIP_IS_E1
	ldr	r3, .L107+144
	cmp	r0, #0
	ldr	r1, [r3]
	orreq	r7, r7, #16
	mov	r2, r7
	mov	r0, r4
	add	r1, r9, r1
	bl	REG_WR
	cmp	r6, #0
	beq	.L32
	ldr	r3, .L107+148
	mov	r0, r4
	ldr	r7, [r3]
	ldr	r8, .L107+152
	mov	r1, r7
	bl	REG_RD
	ldr	r2, [r8]
	mov	r1, r7
	bic	r2, r0, r2
	mov	r0, r4
	bl	REG_WR
	ldr	r3, .L107+156
	ldr	r7, [r3]
.L33:
	mov	r1, r7
	mov	r0, r4
	bl	REG_RD
	ldr	r2, [r8]
	mov	r1, r7
	bic	r2, r0, r2
	mov	r0, r4
	bl	REG_WR
	ldr	r3, .L107+160
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	mov	r0, r4
	bl	CHIP_IS_E1x
	cmp	r0, #0
	beq	.L102
.L35:
	mov	r0, r4
	bl	CHIP_IS_E3
	cmp	r0, #0
	beq	.L103
.L46:
	mov	r0, r4
	bl	CHIP_IS_E1
	cmp	r0, #0
	beq	.L104
.L47:
	ldr	r3, .L107+164
	mov	r0, r4
	ldr	r1, [r3]
	bl	REG_RD
	ldr	r3, .L107+168
	ldr	r3, [r3]
	tst	r0, r3
	beq	.L53
	cmp	r6, #0
	ldrne	r3, .L107+172
	ldreq	r3, .L107+176
	mov	r0, r4
	ldr	r5, [r3]
	mov	r1, r5
	bl	REG_RD
	mov	r2, r0
	ldr	r3, .L107+180
	mov	r1, r5
	ldr	r3, [r3]
	mov	r0, r4
	orr	r2, r2, r3
	bl	REG_WR
.L53:
	mov	r0, r4
	bl	CHIP_IS_E3B0
	cmp	r0, #0
	ldrne	r2, .L107+184
	ldrne	r3, [r4]
	ldrne	r2, [r2]
	mov	r0, #0
	orrne	r3, r3, r2
	strne	r3, [r4]
	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
.L9:
	mov	r0, r4
	bl	IS_MF
	cmp	r0, #0
	beq	.L105
	ldr	r2, .L107+188
	ldr	r3, [r4]
	ldr	r2, [r2]
	ldr	r7, .L107+192
	and	r3, r3, r2
	cmp	r3, #0
	movne	r7, #216
	movne	r2, #160
	moveq	r2, #246
.L11:
	ldr	r3, .L107+196
	mov	r0, r4
	ldr	r1, [r3]
	add	r1, r9, r1
	bl	REG_WR
	ldr	r3, .L107+200
	mov	r2, r7
	ldr	r1, [r3]
	mov	r0, r4
	add	r1, r9, r1
	bl	REG_WR
	mov	r0, r4
	bl	CHIP_MODE_IS_4_PORT
	cmp	r0, #0
	beq	.L13
.L97:
	mov	r0, r4
	bl	BP_PORT
	cmp	r0, #0
	ldrne	r3, .L107+204
	ldreq	r3, .L107+208
	mov	r2, #40
	mov	r0, r4
	ldr	r1, [r3]
	bl	REG_WR
	b	.L13
.L32:
	ldr	r3, .L107+212
	mov	r0, r4
	ldr	r7, [r3]
	ldr	r8, .L107+152
	mov	r1, r7
	bl	REG_RD
	ldr	r2, [r8]
	mov	r1, r7
	bic	r2, r0, r2
	mov	r0, r4
	bl	REG_WR
	ldr	r3, .L107+216
	ldr	r7, [r3]
	b	.L33
.L105:
	ldr	r3, [r4, #12]
	ldr	r2, .L107+188
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	r1, [r4]
	cmp	r3, #4096
	and	r2, r2, r1
	ble	.L12
	cmp	r2, #0
	movne	r7, #216
	movne	r2, #160
	bne	.L11
	ands	r1, r3, #63
	movne	r1, #1
	asr	r2, r3, #6
	add	r2, r2, #96
	add	r2, r2, r1
	add	r7, r2, #56
	b	.L11
.L96:
	ldr	r3, .L107+220
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L107+224
	mov	r2, #20
	ldr	r1, [r3]
	mov	r0, r4
	add	r1, r9, r1
	bl	REG_WR
	ldr	r3, .L107+228
	mov	r2, #31
	ldr	r1, [r3]
	mov	r0, r4
	add	r1, r9, r1
	bl	REG_WR
	b	.L5
.L95:
	ldr	r3, .L107+232
	mov	r2, #1
	mov	r0, r4
	ldr	r1, [r3]
	bl	REG_WR
	b	.L4
.L104:
	ldr	r3, .L107+236
	mov	r0, r4
	ldr	r5, [r3]
	bl	IS_MF_SD
	add	r5, r9, r5
	cmp	r0, #0
	mov	r1, r5
	movne	r2, #1
	moveq	r2, #2
	mov	r0, r4
	bl	REG_WR
	mov	r0, r4
	bl	CHIP_IS_E1x
	subs	r5, r0, #0
	bne	.L49
	ldr	r3, [r4, #4]
	cmp	r3, #129
	moveq	r5, #1
	beq	.L50
	bic	r3, r3, #2
	cmp	r3, #128
	moveq	r5, #2
.L50:
	mov	r0, r4
	bl	BP_PORT
	cmp	r0, #0
	ldrne	r3, .L107+240
	ldreq	r3, .L107+244
	mov	r2, r5
	mov	r0, r4
	ldr	r1, [r3]
	bl	REG_WR
.L49:
	ldr	r3, .L107+248
	mov	r2, #0
	ldr	r1, [r3]
	mov	r0, r4
	add	r1, r9, r1
	bl	REG_WR
	ldr	r3, .L107+252
	mov	r2, #0
	ldr	r1, [r3]
	mov	r0, r4
	add	r1, r9, r1
	bl	REG_WR
	ldr	r3, .L107+256
	mov	r2, #1
	ldr	r1, [r3]
	mov	r0, r4
	add	r1, r9, r1
	bl	REG_WR
	b	.L47
.L103:
	ldr	r3, .L107+260
	mov	r2, #1
	ldr	r1, [r3]
	mov	r0, r4
	add	r1, r9, r1
	bl	REG_WR
	b	.L46
.L102:
	mov	r0, r4
	bl	IS_MF_AFEX
	cmp	r0, #0
	mov	r0, r4
	bne	.L106
	bl	BP_PORT
	cmp	r0, #0
	ldrne	r3, .L107+264
	ldreq	r3, .L107+268
	mov	r0, r4
	ldr	r5, [r3]
	bl	IS_MF_SD
	cmp	r0, #0
	mov	r1, r5
	movne	r2, #7
	moveq	r2, #6
	mov	r0, r4
	bl	REG_WR
.L39:
	mov	r0, r4
	bl	CHIP_IS_E3
	cmp	r0, #0
	beq	.L35
	mov	r0, r4
	bl	BP_PORT
	cmp	r0, #0
	ldrne	r3, .L107+272
	ldreq	r3, .L107+276
	mov	r0, r4
	ldr	r5, [r3]
	bl	IS_MF
	mov	r1, r5
	mov	r2, r0
	mov	r0, r4
	bl	REG_WR
	b	.L35
.L101:
	ldr	r3, .L107+280
	mov	r2, #0
	ldr	r1, [r3]
	mov	r0, r4
	add	r1, r1, r6, lsl #3
	bl	REG_WR
	ldr	r3, .L107+284
	lsl	r1, r6, #3
	ldr	r3, [r3]
	mov	r2, #0
	mov	r0, r4
	add	r1, r1, r3
	bl	REG_WR
	b	.L29
.L100:
	ldr	r3, .L107+288
	mov	r2, r5
	mov	r0, r4
	ldr	r1, [r3]
	bl	bnx2x_init_block
	b	.L28
.L99:
	ldr	r3, .L107+292
	mov	r2, #0
	ldr	r1, [r3]
	mov	r0, r4
	add	r1, r9, r1
	bl	REG_WR
	ldr	r3, .L107+296
	mov	r0, r4
	ldr	r1, [r3]
	ldr	r2, .L107+300
	add	r1, r9, r1
	bl	REG_WR
	ldr	r3, .L107+304
	ldr	r7, .L107+308
	ldr	r1, [r3]
	mov	r0, r4
	add	r1, r9, r1
	ldr	r2, .L107+312
	bl	REG_WR
	ldr	r1, [r7]
	mov	r2, #1
	add	r1, r9, r1
	mov	r0, r4
	bl	REG_WR
	mov	r0, #50
	bl	udelay
	ldr	r1, [r7]
	mov	r2, #0
	mov	r0, r4
	add	r1, r9, r1
	bl	REG_WR
	b	.L27
.L98:
	mov	r0, r4
	bl	IS_MF_AFEX
	cmp	r0, #0
	mov	r0, r4
	beq	.L17
	bl	BP_PORT
	cmp	r0, #0
	ldrne	r3, .L107+316
	ldreq	r3, .L107+320
	mov	r2, #14
	ldr	r1, [r3]
	mov	r0, r4
	bl	REG_WR
	mov	r0, r4
	bl	BP_PORT
	cmp	r0, #0
	ldrne	r3, .L107+324
	ldreq	r3, .L107+328
	mov	r2, #6
	ldr	r1, [r3]
	mov	r0, r4
	bl	REG_WR
	mov	r0, r4
	bl	BP_PORT
	cmp	r0, #0
	ldrne	r3, .L107+332
	ldreq	r3, .L107+336
	mov	r2, #10
	mov	r0, r4
	ldr	r1, [r3]
	bl	REG_WR
	b	.L16
.L12:
	cmp	r2, #0
	moveq	r7, #216
	movne	r7, #136
	moveq	r2, #160
	movne	r2, #80
	b	.L11
.L17:
	bl	BP_PORT
	cmp	r0, #0
	ldrne	r3, .L107+316
	ldreq	r3, .L107+320
	mov	r0, r4
	ldr	r1, [r3]
	ldr	r3, [r4, #8]
	cmp	r3, #0
	movne	r2, #7
	moveq	r2, #6
	bl	REG_WR
	b	.L16
.L106:
	bl	BP_PORT
	cmp	r0, #0
	ldrne	r3, .L107+264
	ldreq	r3, .L107+268
	mov	r2, #14
	mov	r0, r4
	ldr	r1, [r3]
	bl	REG_WR
	b	.L39
.L108:
	.align	2
.L107:
	.word	PHASE_PORT1
	.word	PHASE_PORT0
	.word	NETIF_MSG_HW
	.word	.LC0
	.word	NIG_REG_MASK_INTERRUPT_PORT0
	.word	BLOCK_MISC
	.word	BLOCK_PXP
	.word	BLOCK_PXP2
	.word	BLOCK_ATC
	.word	BLOCK_DMAE
	.word	BLOCK_PGLUE_B
	.word	BLOCK_QM
	.word	BLOCK_TCM
	.word	BLOCK_UCM
	.word	BLOCK_CCM
	.word	BLOCK_XCM
	.word	INITOP_SET
	.word	BLOCK_DORQ
	.word	BLOCK_BRB1
	.word	BLOCK_PRS
	.word	BLOCK_TSDM
	.word	BLOCK_CSDM
	.word	BLOCK_USDM
	.word	BLOCK_XSDM
	.word	BLOCK_TSEM
	.word	BLOCK_USEM
	.word	BLOCK_CSEM
	.word	BLOCK_XSEM
	.word	BLOCK_UPB
	.word	BLOCK_XPB
	.word	BLOCK_PBF
	.word	BLOCK_CDU
	.word	BLOCK_CFC
	.word	BLOCK_HC
	.word	BLOCK_IGU
	.word	BLOCK_MISC_AEU
	.word	MISC_REG_AEU_MASK_ATTN_FUNC_0
	.word	MISC_REG_AEU_ENABLE4_NIG_1
	.word	AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
	.word	MISC_REG_AEU_ENABLE4_PXP_1
	.word	BLOCK_NIG
	.word	MISC_REG_SPIO_EVENT_EN
	.word	MISC_SPIO_SPIO5
	.word	MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
	.word	MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
	.word	AEU_INPUTS_ATTN_BITS_SPIO5
	.word	PTP_SUPPORTED
	.word	ONE_PORT_FLAG
	.word	302
	.word	BRB1_REG_PAUSE_LOW_THRESHOLD_0
	.word	BRB1_REG_PAUSE_HIGH_THRESHOLD_0
	.word	BRB1_REG_MAC_GUARANTIED_1
	.word	BRB1_REG_MAC_GUARANTIED_0
	.word	MISC_REG_AEU_ENABLE4_NIG_0
	.word	MISC_REG_AEU_ENABLE4_PXP_0
	.word	BLOCK_TM
	.word	TM_REG_LIN0_SCAN_TIME
	.word	TM_REG_LIN0_MAX_ACTIVE_CID
	.word	PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
	.word	NIG_REG_LLH0_BRB1_DRV_MASK_MF
	.word	NIG_REG_LLH1_CLS_TYPE
	.word	NIG_REG_LLH0_CLS_TYPE
	.word	NIG_REG_LLFC_ENABLE_0
	.word	NIG_REG_LLFC_OUT_EN_0
	.word	NIG_REG_PAUSE_ENABLE_0
	.word	NIG_REG_XGXS_SERDES0_MODE_SEL
	.word	NIG_REG_P1_HDRS_AFTER_BASIC
	.word	NIG_REG_P0_HDRS_AFTER_BASIC
	.word	NIG_REG_LLH1_MF_MODE
	.word	NIG_REG_LLH_MF_MODE
	.word	HC_REG_LEADING_EDGE_0
	.word	HC_REG_TRAILING_EDGE_0
	.word	BLOCK_SRC
	.word	PBF_REG_P0_PAUSE_ENABLE
	.word	PBF_REG_P0_ARB_THRSH
	.word	565
	.word	PBF_REG_P0_INIT_CRD
	.word	PBF_REG_INIT_P0
	.word	1096
	.word	PRS_REG_HDRS_AFTER_BASIC_PORT_1
	.word	PRS_REG_HDRS_AFTER_BASIC_PORT_0
	.word	PRS_REG_HDRS_AFTER_TAG_0_PORT_1
	.word	PRS_REG_HDRS_AFTER_TAG_0_PORT_0
	.word	PRS_REG_MUST_HAVE_HDRS_PORT_1
	.word	PRS_REG_MUST_HAVE_HDRS_PORT_0
	.size	bnx2x_init_hw_port, .-bnx2x_init_hw_port
	.comm	TM_REG_LIN0_SCAN_TIME,4,4
	.comm	TM_REG_LIN0_MAX_ACTIVE_CID,4,4
	.comm	PTP_SUPPORTED,4,4
	.comm	PRS_REG_MUST_HAVE_HDRS_PORT_1,4,4
	.comm	PRS_REG_MUST_HAVE_HDRS_PORT_0,4,4
	.comm	PRS_REG_HDRS_AFTER_TAG_0_PORT_1,4,4
	.comm	PRS_REG_HDRS_AFTER_TAG_0_PORT_0,4,4
	.comm	PRS_REG_HDRS_AFTER_BASIC_PORT_1,4,4
	.comm	PRS_REG_HDRS_AFTER_BASIC_PORT_0,4,4
	.comm	PHASE_PORT1,4,4
	.comm	PHASE_PORT0,4,4
	.comm	PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,4,4
	.comm	PBF_REG_P0_PAUSE_ENABLE,4,4
	.comm	PBF_REG_P0_INIT_CRD,4,4
	.comm	PBF_REG_P0_ARB_THRSH,4,4
	.comm	PBF_REG_INIT_P0,4,4
	.comm	ONE_PORT_FLAG,4,4
	.comm	NIG_REG_XGXS_SERDES0_MODE_SEL,4,4
	.comm	NIG_REG_PAUSE_ENABLE_0,4,4
	.comm	NIG_REG_P1_HDRS_AFTER_BASIC,4,4
	.comm	NIG_REG_P0_HDRS_AFTER_BASIC,4,4
	.comm	NIG_REG_MASK_INTERRUPT_PORT0,4,4
	.comm	NIG_REG_LLH_MF_MODE,4,4
	.comm	NIG_REG_LLH1_MF_MODE,4,4
	.comm	NIG_REG_LLH1_CLS_TYPE,4,4
	.comm	NIG_REG_LLH0_CLS_TYPE,4,4
	.comm	NIG_REG_LLH0_BRB1_DRV_MASK_MF,4,4
	.comm	NIG_REG_LLFC_OUT_EN_0,4,4
	.comm	NIG_REG_LLFC_ENABLE_0,4,4
	.comm	NETIF_MSG_HW,4,4
	.comm	MISC_SPIO_SPIO5,4,4
	.comm	MISC_REG_SPIO_EVENT_EN,4,4
	.comm	MISC_REG_AEU_MASK_ATTN_FUNC_0,4,4
	.comm	MISC_REG_AEU_ENABLE4_PXP_1,4,4
	.comm	MISC_REG_AEU_ENABLE4_PXP_0,4,4
	.comm	MISC_REG_AEU_ENABLE4_NIG_1,4,4
	.comm	MISC_REG_AEU_ENABLE4_NIG_0,4,4
	.comm	MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0,4,4
	.comm	MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0,4,4
	.comm	INITOP_SET,4,4
	.comm	HC_REG_TRAILING_EDGE_0,4,4
	.comm	HC_REG_LEADING_EDGE_0,4,4
	.comm	BRB1_REG_PAUSE_LOW_THRESHOLD_0,4,4
	.comm	BRB1_REG_PAUSE_HIGH_THRESHOLD_0,4,4
	.comm	BRB1_REG_MAC_GUARANTIED_1,4,4
	.comm	BRB1_REG_MAC_GUARANTIED_0,4,4
	.comm	BLOCK_XSEM,4,4
	.comm	BLOCK_XSDM,4,4
	.comm	BLOCK_XPB,4,4
	.comm	BLOCK_XCM,4,4
	.comm	BLOCK_USEM,4,4
	.comm	BLOCK_USDM,4,4
	.comm	BLOCK_UPB,4,4
	.comm	BLOCK_UCM,4,4
	.comm	BLOCK_TSEM,4,4
	.comm	BLOCK_TSDM,4,4
	.comm	BLOCK_TM,4,4
	.comm	BLOCK_TCM,4,4
	.comm	BLOCK_SRC,4,4
	.comm	BLOCK_QM,4,4
	.comm	BLOCK_PXP2,4,4
	.comm	BLOCK_PXP,4,4
	.comm	BLOCK_PRS,4,4
	.comm	BLOCK_PGLUE_B,4,4
	.comm	BLOCK_PBF,4,4
	.comm	BLOCK_NIG,4,4
	.comm	BLOCK_MISC_AEU,4,4
	.comm	BLOCK_MISC,4,4
	.comm	BLOCK_IGU,4,4
	.comm	BLOCK_HC,4,4
	.comm	BLOCK_DORQ,4,4
	.comm	BLOCK_DMAE,4,4
	.comm	BLOCK_CSEM,4,4
	.comm	BLOCK_CSDM,4,4
	.comm	BLOCK_CFC,4,4
	.comm	BLOCK_CDU,4,4
	.comm	BLOCK_CCM,4,4
	.comm	BLOCK_BRB1,4,4
	.comm	BLOCK_ATC,4,4
	.comm	AEU_INPUTS_ATTN_BITS_SPIO5,4,4
	.comm	AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
