	.file	"extr_dce_v11_0.c_dce_v11_0_crtc_do_set_base.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"No FB bound\n"
.LC1:
	.string	"Unsupported screen format %s\n"
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC2:
	.string	"Bypassing hardware LUT due to 10 bit fb scanout.\n"
	.text
	.p2align 4
	.type	dce_v11_0_crtc_do_set_base, @function
dce_v11_0_crtc_do_set_base:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	mov	r15d, r8d
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	mov	r14, rsi
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 88
	.cfi_def_cfa_offset 144
	mov	DWORD PTR 4[rsp], edx
	mov	DWORD PTR 8[rsp], ecx
	mov	DWORD PTR 12[rsp], r8d
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 72[rsp], rax
	xor	eax, eax
	call	to_amdgpu_crtc@PLT
	mov	ecx, DWORD PTR ENDIAN_NONE[rip]
	mov	edx, DWORD PTR GRPH_ENDIAN_SWAP[rip]
	xor	edi, edi
	mov	rbx, rax
	mov	rax, QWORD PTR 16[rbp]
	mov	esi, DWORD PTR GRPH_SWAP_CNTL[rip]
	mov	rax, QWORD PTR [rax]
	mov	QWORD PTR 16[rsp], rax
	call	REG_SET_FIELD@PLT
	mov	DWORD PTR [rsp], eax
	test	r15d, r15d
	jne	.L2
	mov	rax, QWORD PTR 0[rbp]
	mov	r12, QWORD PTR [rax]
	test	r12, r12
	je	.L38
	mov	rax, QWORD PTR 16[r12]
	mov	rdi, QWORD PTR [rax]
	call	gem_to_amdgpu_bo@PLT
	xor	esi, esi
	mov	rdi, rax
	mov	r15, rax
	call	amdgpu_bo_reserve@PLT
	xor	edi, edi
	test	eax, eax
	mov	r13d, eax
	setne	dil
	call	unlikely@PLT
	test	rax, rax
	jne	.L1
	mov	esi, DWORD PTR AMDGPU_GEM_DOMAIN_VRAM[rip]
	mov	rdi, r15
	call	amdgpu_bo_pin@PLT
	xor	edi, edi
	test	eax, eax
	setne	dil
	call	unlikely@PLT
	test	rax, rax
	jne	.L39
.L5:
	mov	rdi, r15
	call	amdgpu_bo_gpu_offset@PLT
	lea	rsi, 64[rsp]
	mov	rdi, r15
	mov	r13, rax
	call	amdgpu_bo_get_tiling_flags@PLT
	mov	rdi, r15
	call	amdgpu_bo_unreserve@PLT
	mov	rdi, QWORD PTR 64[rsp]
	mov	esi, DWORD PTR PIPE_CONFIG[rip]
	call	AMDGPU_TILING_GET@PLT
	mov	DWORD PTR 24[rsp], eax
	mov	rax, QWORD PTR 24[r12]
	mov	edi, DWORD PTR [rax]
	lea	eax, -128[rdi]
	cmp	eax, 15
	ja	.L6
	lea	rdx, .L8[rip]
	movsx	rax, DWORD PTR [rdx+rax*4]
	add	rax, rdx
	notrack jmp	rax
	.section	.rodata
	.align 4
	.align 4
.L8:
	.long	.L12-.L8
	.long	.L11-.L8
	.long	.L10-.L8
	.long	.L9-.L8
	.long	.L7-.L8
	.long	.L16-.L8
	.long	.L15-.L8
	.long	.L14-.L8
	.long	.L13-.L8
	.long	.L14-.L8
	.long	.L13-.L8
	.long	.L12-.L8
	.long	.L11-.L8
	.long	.L10-.L8
	.long	.L9-.L8
	.long	.L7-.L8
	.text
	.p2align 4,,10
	.p2align 3
.L14:
	mov	edx, DWORD PTR GRPH_DEPTH[rip]
	mov	esi, DWORD PTR GRPH_CONTROL[rip]
	mov	ecx, 1
	xor	edi, edi
	call	REG_SET_FIELD@PLT
	mov	ecx, 5
	mov	edi, eax
	.p2align 4,,10
	.p2align 3
.L34:
	mov	edx, DWORD PTR GRPH_FORMAT[rip]
	mov	esi, DWORD PTR GRPH_CONTROL[rip]
	call	REG_SET_FIELD@PLT
	mov	DWORD PTR 28[rsp], 0
	mov	r15d, eax
.L17:
	mov	esi, DWORD PTR ARRAY_MODE[rip]
	mov	rdi, QWORD PTR 64[rsp]
	call	AMDGPU_TILING_GET@PLT
	cmp	eax, DWORD PTR ARRAY_2D_TILED_THIN1[rip]
	je	.L40
	mov	esi, DWORD PTR ARRAY_MODE[rip]
	mov	rdi, QWORD PTR 64[rsp]
	call	AMDGPU_TILING_GET@PLT
	cmp	eax, DWORD PTR ARRAY_1D_TILED_THIN1[rip]
	je	.L41
.L19:
	mov	ecx, DWORD PTR 24[rsp]
	mov	edx, DWORD PTR GRPH_PIPE_CONFIG[rip]
	mov	edi, r15d
	mov	esi, DWORD PTR GRPH_CONTROL[rip]
	call	REG_SET_FIELD@PLT
	xor	esi, esi
	mov	rdi, rbp
	mov	r15d, eax
	call	dce_v11_0_vga_enable@PLT
	mov	rdi, QWORD PTR mmGRPH_FLIP_CONTROL[rip]
	add	rdi, QWORD PTR [rbx]
	call	RREG32@PLT
	mov	edx, DWORD PTR GRPH_SURFACE_UPDATE_H_RETRACE_EN[rip]
	mov	esi, DWORD PTR GRPH_FLIP_CONTROL[rip]
	xor	ecx, ecx
	mov	edi, eax
	call	REG_SET_FIELD@PLT
	mov	rdi, QWORD PTR mmGRPH_FLIP_CONTROL[rip]
	add	rdi, QWORD PTR [rbx]
	mov	esi, eax
	call	WREG32@PLT
	mov	rdi, r13
	call	upper_32_bits@PLT
	mov	rdi, QWORD PTR mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH[rip]
	add	rdi, QWORD PTR [rbx]
	mov	esi, eax
	call	WREG32@PLT
	mov	rdi, r13
	call	upper_32_bits@PLT
	mov	rdi, QWORD PTR mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH[rip]
	add	rdi, QWORD PTR [rbx]
	mov	esi, eax
	call	WREG32@PLT
	mov	esi, DWORD PTR GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK[rip]
	mov	rdi, QWORD PTR mmGRPH_PRIMARY_SURFACE_ADDRESS[rip]
	add	rdi, QWORD PTR [rbx]
	and	esi, r13d
	call	WREG32@PLT
	mov	esi, DWORD PTR GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK[rip]
	mov	rdi, QWORD PTR mmGRPH_SECONDARY_SURFACE_ADDRESS[rip]
	add	rdi, QWORD PTR [rbx]
	and	esi, r13d
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmGRPH_CONTROL[rip]
	mov	esi, r15d
	add	rdi, QWORD PTR [rbx]
	call	WREG32@PLT
	mov	esi, DWORD PTR [rsp]
	mov	rdi, QWORD PTR mmGRPH_SWAP_CNTL[rip]
	add	rdi, QWORD PTR [rbx]
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmGRPH_LUT_10BIT_BYPASS[rip]
	add	rdi, QWORD PTR [rbx]
	call	RREG32@PLT
	mov	edx, DWORD PTR 28[rsp]
	mov	edi, eax
	test	edx, edx
	je	.L20
	mov	edx, DWORD PTR GRPH_LUT_10BIT_BYPASS_EN[rip]
	mov	esi, DWORD PTR GRPH_LUT_10BIT_BYPASS[rip]
	mov	ecx, 1
	call	REG_SET_FIELD@PLT
	mov	rdi, QWORD PTR mmGRPH_LUT_10BIT_BYPASS[rip]
	add	rdi, QWORD PTR [rbx]
	mov	esi, eax
	call	WREG32@PLT
	lea	rdi, .LC2[rip]
	call	DRM_DEBUG_KMS@PLT
.L21:
	xor	esi, esi
	mov	rdi, QWORD PTR mmGRPH_SURFACE_OFFSET_X[rip]
	add	rdi, QWORD PTR [rbx]
	call	WREG32@PLT
	xor	esi, esi
	mov	rdi, QWORD PTR mmGRPH_SURFACE_OFFSET_Y[rip]
	add	rdi, QWORD PTR [rbx]
	call	WREG32@PLT
	xor	esi, esi
	mov	rdi, QWORD PTR mmGRPH_X_START[rip]
	add	rdi, QWORD PTR [rbx]
	call	WREG32@PLT
	xor	esi, esi
	mov	rdi, QWORD PTR mmGRPH_Y_START[rip]
	add	rdi, QWORD PTR [rbx]
	call	WREG32@PLT
	mov	esi, DWORD PTR [r12]
	mov	rdi, QWORD PTR mmGRPH_X_END[rip]
	add	rdi, QWORD PTR [rbx]
	call	WREG32@PLT
	mov	esi, DWORD PTR 4[r12]
	mov	rdi, QWORD PTR mmGRPH_Y_END[rip]
	add	rdi, QWORD PTR [rbx]
	call	WREG32@PLT
	mov	rax, QWORD PTR 8[r12]
	mov	rdx, QWORD PTR 24[r12]
	mov	rdi, QWORD PTR mmGRPH_PITCH[rip]
	add	rdi, QWORD PTR [rbx]
	mov	eax, DWORD PTR [rax]
	mov	rcx, QWORD PTR 8[rdx]
	cdq
	idiv	DWORD PTR [rcx]
	mov	esi, eax
	call	WREG32@PLT
	mov	esi, 1
	mov	rdi, rbp
	call	dce_v11_0_grph_enable@PLT
	mov	esi, DWORD PTR 4[r12]
	mov	rdi, QWORD PTR mmLB_DESKTOP_HEIGHT[rip]
	add	rdi, QWORD PTR [rbx]
	call	WREG32@PLT
	mov	esi, DWORD PTR 4[rsp]
	mov	ecx, DWORD PTR 8[rsp]
	mov	rdi, QWORD PTR mmVIEWPORT_START[rip]
	add	rdi, QWORD PTR [rbx]
	sal	esi, 16
	and	ecx, -2
	and	esi, -262144
	or	esi, ecx
	call	WREG32@PLT
	mov	eax, DWORD PTR 12[rbp]
	mov	rdi, QWORD PTR mmVIEWPORT_SIZE[rip]
	lea	esi, 1[rax]
	mov	eax, DWORD PTR 8[rbp]
	and	esi, -2
	sal	eax, 16
	or	esi, eax
	add	rdi, QWORD PTR [rbx]
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmCRTC_MASTER_UPDATE_MODE[rip]
	xor	esi, esi
	add	rdi, QWORD PTR [rbx]
	call	WREG32@PLT
	mov	eax, DWORD PTR 12[rsp]
	test	eax, eax
	jne	.L22
	test	r14, r14
	je	.L22
	mov	rax, QWORD PTR 0[rbp]
	cmp	QWORD PTR [rax], r14
	je	.L22
	mov	rax, QWORD PTR 16[r14]
	mov	rdi, QWORD PTR [rax]
	call	gem_to_amdgpu_bo@PLT
	mov	esi, 1
	mov	rdi, rax
	mov	rbp, rax
	call	amdgpu_bo_reserve@PLT
	xor	edi, edi
	test	eax, eax
	mov	r13d, eax
	setne	dil
	call	unlikely@PLT
	test	rax, rax
	jne	.L1
	mov	rdi, rbp
	call	amdgpu_bo_unpin@PLT
	mov	rdi, rbp
	call	amdgpu_bo_unreserve@PLT
.L22:
	mov	rdi, QWORD PTR 16[rsp]
	xor	r13d, r13d
	call	dce_v11_0_bandwidth_update@PLT
.L1:
	mov	rax, QWORD PTR 72[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L42
	add	rsp, 88
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	eax, r13d
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L2:
	.cfi_restore_state
	mov	rax, QWORD PTR 16[r14]
	mov	r12, r14
	mov	rdi, QWORD PTR [rax]
	call	gem_to_amdgpu_bo@PLT
	xor	esi, esi
	mov	rdi, rax
	mov	r15, rax
	call	amdgpu_bo_reserve@PLT
	xor	edi, edi
	test	eax, eax
	mov	r13d, eax
	setne	dil
	call	unlikely@PLT
	test	rax, rax
	je	.L5
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L7:
	mov	edx, DWORD PTR GRPH_DEPTH[rip]
	mov	esi, DWORD PTR GRPH_CONTROL[rip]
	mov	ecx, 2
	xor	edi, edi
	call	REG_SET_FIELD@PLT
	mov	edx, DWORD PTR GRPH_FORMAT[rip]
	mov	esi, DWORD PTR GRPH_CONTROL[rip]
	xor	ecx, ecx
	mov	edi, eax
	call	REG_SET_FIELD@PLT
	mov	edx, DWORD PTR GRPH_RED_CROSSBAR[rip]
	mov	esi, DWORD PTR GRPH_SWAP_CNTL[rip]
	mov	ecx, 2
	mov	edi, DWORD PTR [rsp]
	mov	r15d, eax
	call	REG_SET_FIELD@PLT
	mov	edx, DWORD PTR GRPH_BLUE_CROSSBAR[rip]
	mov	esi, DWORD PTR GRPH_SWAP_CNTL[rip]
	mov	ecx, 2
	mov	edi, eax
	call	REG_SET_FIELD@PLT
	mov	DWORD PTR 28[rsp], 0
	mov	DWORD PTR [rsp], eax
	jmp	.L17
	.p2align 4,,10
	.p2align 3
.L9:
	mov	ecx, 1
.L36:
	mov	edx, DWORD PTR GRPH_DEPTH[rip]
	mov	esi, DWORD PTR GRPH_CONTROL[rip]
	xor	edi, edi
	call	REG_SET_FIELD@PLT
	xor	ecx, ecx
	mov	edi, eax
	jmp	.L34
	.p2align 4,,10
	.p2align 3
.L10:
	mov	edx, DWORD PTR GRPH_DEPTH[rip]
	mov	esi, DWORD PTR GRPH_CONTROL[rip]
	mov	ecx, 2
	xor	edi, edi
	call	REG_SET_FIELD@PLT
	mov	ecx, 1
	mov	edi, eax
.L35:
	mov	edx, DWORD PTR GRPH_FORMAT[rip]
	mov	esi, DWORD PTR GRPH_CONTROL[rip]
	call	REG_SET_FIELD@PLT
	mov	DWORD PTR 28[rsp], 1
	mov	r15d, eax
	jmp	.L17
	.p2align 4,,10
	.p2align 3
.L11:
	mov	edx, DWORD PTR GRPH_DEPTH[rip]
	mov	esi, DWORD PTR GRPH_CONTROL[rip]
	mov	ecx, 1
	xor	edi, edi
	call	REG_SET_FIELD@PLT
	mov	ecx, 2
	mov	edi, eax
	jmp	.L34
	.p2align 4,,10
	.p2align 3
.L12:
	mov	ecx, 2
	jmp	.L36
	.p2align 4,,10
	.p2align 3
.L13:
	mov	edx, DWORD PTR GRPH_DEPTH[rip]
	mov	esi, DWORD PTR GRPH_CONTROL[rip]
	mov	ecx, 2
	xor	edi, edi
	call	REG_SET_FIELD@PLT
	mov	ecx, 4
	mov	edi, eax
	jmp	.L35
	.p2align 4,,10
	.p2align 3
.L15:
	xor	ecx, ecx
	jmp	.L36
	.p2align 4,,10
	.p2align 3
.L16:
	mov	edx, DWORD PTR GRPH_DEPTH[rip]
	mov	esi, DWORD PTR GRPH_CONTROL[rip]
	mov	ecx, 1
	xor	edi, edi
	call	REG_SET_FIELD@PLT
	mov	ecx, 1
	mov	edi, eax
	jmp	.L34
	.p2align 4,,10
	.p2align 3
.L20:
	mov	edx, DWORD PTR GRPH_LUT_10BIT_BYPASS_EN[rip]
	mov	esi, DWORD PTR GRPH_LUT_10BIT_BYPASS[rip]
	xor	ecx, ecx
	call	REG_SET_FIELD@PLT
	mov	rdi, QWORD PTR mmGRPH_LUT_10BIT_BYPASS[rip]
	add	rdi, QWORD PTR [rbx]
	mov	esi, eax
	call	WREG32@PLT
	jmp	.L21
	.p2align 4,,10
	.p2align 3
.L40:
	mov	esi, DWORD PTR BANK_WIDTH[rip]
	mov	rdi, QWORD PTR 64[rsp]
	call	AMDGPU_TILING_GET@PLT
	mov	esi, DWORD PTR BANK_HEIGHT[rip]
	mov	rdi, QWORD PTR 64[rsp]
	mov	DWORD PTR 44[rsp], eax
	call	AMDGPU_TILING_GET@PLT
	mov	esi, DWORD PTR MACRO_TILE_ASPECT[rip]
	mov	rdi, QWORD PTR 64[rsp]
	mov	DWORD PTR 40[rsp], eax
	call	AMDGPU_TILING_GET@PLT
	mov	esi, DWORD PTR TILE_SPLIT[rip]
	mov	rdi, QWORD PTR 64[rsp]
	mov	DWORD PTR 36[rsp], eax
	call	AMDGPU_TILING_GET@PLT
	mov	esi, DWORD PTR NUM_BANKS[rip]
	mov	rdi, QWORD PTR 64[rsp]
	mov	DWORD PTR 32[rsp], eax
	call	AMDGPU_TILING_GET@PLT
	mov	edx, DWORD PTR GRPH_NUM_BANKS[rip]
	mov	esi, DWORD PTR GRPH_CONTROL[rip]
	mov	edi, r15d
	mov	ecx, eax
	call	REG_SET_FIELD@PLT
	mov	ecx, DWORD PTR ARRAY_2D_TILED_THIN1[rip]
	mov	edx, DWORD PTR GRPH_ARRAY_MODE[rip]
	mov	esi, DWORD PTR GRPH_CONTROL[rip]
	mov	edi, eax
	call	REG_SET_FIELD@PLT
	mov	r11d, DWORD PTR 32[rsp]
	mov	edx, DWORD PTR GRPH_TILE_SPLIT[rip]
	mov	esi, DWORD PTR GRPH_CONTROL[rip]
	mov	edi, eax
	mov	ecx, r11d
	call	REG_SET_FIELD@PLT
	mov	r10d, DWORD PTR 44[rsp]
	mov	edx, DWORD PTR GRPH_BANK_WIDTH[rip]
	mov	esi, DWORD PTR GRPH_CONTROL[rip]
	mov	edi, eax
	mov	ecx, r10d
	call	REG_SET_FIELD@PLT
	mov	r9d, DWORD PTR 40[rsp]
	mov	edx, DWORD PTR GRPH_BANK_HEIGHT[rip]
	mov	esi, DWORD PTR GRPH_CONTROL[rip]
	mov	edi, eax
	mov	ecx, r9d
	call	REG_SET_FIELD@PLT
	mov	r8d, DWORD PTR 36[rsp]
	mov	edx, DWORD PTR GRPH_MACRO_TILE_ASPECT[rip]
	mov	esi, DWORD PTR GRPH_CONTROL[rip]
	mov	edi, eax
	mov	ecx, r8d
	call	REG_SET_FIELD@PLT
	mov	ecx, DWORD PTR ADDR_SURF_MICRO_TILING_DISPLAY[rip]
	mov	edx, DWORD PTR GRPH_MICRO_TILE_MODE[rip]
	mov	esi, DWORD PTR GRPH_CONTROL[rip]
	mov	edi, eax
	call	REG_SET_FIELD@PLT
	mov	r15d, eax
	jmp	.L19
	.p2align 4,,10
	.p2align 3
.L41:
	mov	edx, DWORD PTR GRPH_ARRAY_MODE[rip]
	mov	esi, DWORD PTR GRPH_CONTROL[rip]
	mov	edi, r15d
	mov	ecx, eax
	call	REG_SET_FIELD@PLT
	mov	r15d, eax
	jmp	.L19
	.p2align 4,,10
	.p2align 3
.L39:
	mov	rdi, r15
	call	amdgpu_bo_unreserve@PLT
	mov	r13d, DWORD PTR EINVAL[rip]
	neg	r13d
	jmp	.L1
.L6:
	lea	rsi, 60[rsp]
	call	drm_get_format_name@PLT
	lea	rdi, .LC1[rip]
	mov	esi, eax
	call	DRM_ERROR@PLT
	mov	r13d, DWORD PTR EINVAL[rip]
	neg	r13d
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L38:
	lea	rdi, .LC0[rip]
	xor	r13d, r13d
	call	DRM_DEBUG_KMS@PLT
	jmp	.L1
.L42:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	dce_v11_0_crtc_do_set_base, .-dce_v11_0_crtc_do_set_base
	.comm	mmVIEWPORT_START,8,8
	.comm	mmVIEWPORT_SIZE,8,8
	.comm	mmLB_DESKTOP_HEIGHT,8,8
	.comm	mmGRPH_Y_START,8,8
	.comm	mmGRPH_Y_END,8,8
	.comm	mmGRPH_X_START,8,8
	.comm	mmGRPH_X_END,8,8
	.comm	mmGRPH_SWAP_CNTL,8,8
	.comm	mmGRPH_SURFACE_OFFSET_Y,8,8
	.comm	mmGRPH_SURFACE_OFFSET_X,8,8
	.comm	mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH,8,8
	.comm	mmGRPH_SECONDARY_SURFACE_ADDRESS,8,8
	.comm	mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH,8,8
	.comm	mmGRPH_PRIMARY_SURFACE_ADDRESS,8,8
	.comm	mmGRPH_PITCH,8,8
	.comm	mmGRPH_LUT_10BIT_BYPASS,8,8
	.comm	mmGRPH_FLIP_CONTROL,8,8
	.comm	mmGRPH_CONTROL,8,8
	.comm	mmCRTC_MASTER_UPDATE_MODE,8,8
	.comm	TILE_SPLIT,4,4
	.comm	PIPE_CONFIG,4,4
	.comm	NUM_BANKS,4,4
	.comm	MACRO_TILE_ASPECT,4,4
	.comm	GRPH_TILE_SPLIT,4,4
	.comm	GRPH_SWAP_CNTL,4,4
	.comm	GRPH_SURFACE_UPDATE_H_RETRACE_EN,4,4
	.comm	GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK,4,4
	.comm	GRPH_RED_CROSSBAR,4,4
	.comm	GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK,4,4
	.comm	GRPH_PIPE_CONFIG,4,4
	.comm	GRPH_NUM_BANKS,4,4
	.comm	GRPH_MICRO_TILE_MODE,4,4
	.comm	GRPH_MACRO_TILE_ASPECT,4,4
	.comm	GRPH_LUT_10BIT_BYPASS_EN,4,4
	.comm	GRPH_LUT_10BIT_BYPASS,4,4
	.comm	GRPH_FORMAT,4,4
	.comm	GRPH_FLIP_CONTROL,4,4
	.comm	GRPH_ENDIAN_SWAP,4,4
	.comm	GRPH_DEPTH,4,4
	.comm	GRPH_CONTROL,4,4
	.comm	GRPH_BLUE_CROSSBAR,4,4
	.comm	GRPH_BANK_WIDTH,4,4
	.comm	GRPH_BANK_HEIGHT,4,4
	.comm	GRPH_ARRAY_MODE,4,4
	.comm	ENDIAN_NONE,4,4
	.comm	ENDIAN_8IN32,4,4
	.comm	ENDIAN_8IN16,4,4
	.comm	EINVAL,4,4
	.comm	BANK_WIDTH,4,4
	.comm	BANK_HEIGHT,4,4
	.comm	ARRAY_MODE,4,4
	.comm	ARRAY_2D_TILED_THIN1,4,4
	.comm	ARRAY_1D_TILED_THIN1,4,4
	.comm	AMDGPU_GEM_DOMAIN_VRAM,4,4
	.comm	ADDR_SURF_MICRO_TILING_DISPLAY,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_dce_v11_0.c_dce_v11_0_crtc_do_set_base.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"No FB bound\012\000"
	.align	2
.LC1:
	.ascii	"Unsupported screen format %s\012\000"
	.align	2
.LC2:
	.ascii	"Bypassing hardware LUT due to 10 bit fb scanout.\012"
	.ascii	"\000"
	.global	__aeabi_idiv
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC3:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	dce_v11_0_crtc_do_set_base, %function
dce_v11_0_crtc_do_set_base:
	@ args = 4, pretend = 0, frame = 56
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	sub	sp, sp, #60
	stmib	sp, {r2, r3}
	mov	r5, r0
	ldr	r3, .L39
	mov	fp, r1
	ldr	r3, [r3]
	str	r3, [sp, #52]
	mov	r3,#0
	bl	to_amdgpu_crtc
	ldr	ip, [r5, #12]
	ldr	r3, .L39+4
	ldr	r2, .L39+8
	ldr	r10, .L39+12
	ldr	ip, [ip]
	ldr	r3, [r3]
	mov	r4, r0
	ldr	r2, [r2]
	mov	r0, #0
	ldr	r1, [r10]
	str	ip, [sp, #12]
	bl	REG_SET_FIELD
	ldr	r3, [sp, #96]
	str	r0, [sp]
	cmp	r3, #0
	bne	.L2
	ldr	r3, [r5]
	ldr	r6, [r3]
	cmp	r6, #0
	beq	.L34
	ldr	r3, [r6, #12]
	ldr	r0, [r3]
	bl	gem_to_amdgpu_bo
	ldr	r1, [sp, #96]
	mov	r8, r0
	bl	amdgpu_bo_reserve
	mov	r7, r0
	subs	r0, r0, #0
	movne	r0, #1
	bl	unlikely
	cmp	r0, #0
	bne	.L1
	ldr	r3, .L39+16
	mov	r0, r8
	ldr	r1, [r3]
	bl	amdgpu_bo_pin
	subs	r0, r0, #0
	movne	r0, #1
	bl	unlikely
	cmp	r0, #0
	bne	.L35
.L5:
	mov	r0, r8
	bl	amdgpu_bo_gpu_offset
	add	r1, sp, #44
	mov	r7, r0
	mov	r0, r8
	bl	amdgpu_bo_get_tiling_flags
	mov	r0, r8
	bl	amdgpu_bo_unreserve
	ldr	r3, .L39+20
	ldr	r0, [sp, #44]
	ldr	r1, [r3]
	bl	AMDGPU_TILING_GET
	ldr	r3, [r6, #16]
	str	r0, [sp, #20]
	ldr	r0, [r3]
	sub	r3, r0, #128
	cmp	r3, #15
	ldrls	pc, [pc, r3, asl #2]
	b	.L6
.L8:
	.word	.L12
	.word	.L11
	.word	.L10
	.word	.L9
	.word	.L7
	.word	.L16
	.word	.L15
	.word	.L14
	.word	.L13
	.word	.L14
	.word	.L13
	.word	.L12
	.word	.L11
	.word	.L10
	.word	.L9
	.word	.L7
.L13:
	ldr	r3, .L39+24
	ldr	r8, .L39+28
	ldr	r2, [r3]
	ldr	r1, [r8]
	mov	r3, #2
	mov	r0, #0
	bl	REG_SET_FIELD
	ldr	r3, .L39+32
	ldr	r1, [r8]
	ldr	r2, [r3]
	mov	r3, #4
	bl	REG_SET_FIELD
	mov	r3, #1
	mov	r9, r0
	str	r3, [sp, #16]
.L17:
	ldr	r3, .L39+36
	ldr	r0, [sp, #44]
	ldr	r1, [r3]
	bl	AMDGPU_TILING_GET
	ldr	r10, .L39+40
	ldr	r3, .L39+36
	ldr	r2, [r10]
	cmp	r0, r2
	beq	.L36
	ldr	r1, [r3]
	ldr	r0, [sp, #44]
	bl	AMDGPU_TILING_GET
	ldr	r3, .L39+44
	ldr	r3, [r3]
	cmp	r0, r3
	beq	.L37
.L19:
	ldr	r2, .L39+48
	ldr	r3, [sp, #20]
	ldr	r2, [r2]
	ldr	r1, [r8]
	mov	r0, r9
	bl	REG_SET_FIELD
	ldr	r9, .L39+52
	mov	r1, #0
	mov	r8, r0
	mov	r0, r5
	bl	dce_v11_0_vga_enable
	ldr	r3, [r9]
	ldr	r0, [r4]
	ldr	r10, .L39+56
	add	r0, r0, r3
	bl	RREG32
	ldr	r3, .L39+60
	ldr	r2, .L39+64
	ldr	r1, [r3]
	ldr	r2, [r2]
	mov	r3, #0
	bl	REG_SET_FIELD
	ldr	r2, [r4]
	mov	r1, r0
	ldr	r0, [r9]
	add	r0, r2, r0
	bl	WREG32
	ldr	r3, .L39+68
	ldr	r9, [r4]
	ldr	r3, [r3]
	mov	r0, r7
	add	r9, r9, r3
	bl	upper_32_bits
	mov	r1, r0
	mov	r0, r9
	bl	WREG32
	ldr	r3, .L39+72
	ldr	r9, [r4]
	ldr	r3, [r3]
	mov	r0, r7
	add	r9, r9, r3
	bl	upper_32_bits
	mov	r1, r0
	mov	r0, r9
	bl	WREG32
	ldr	r2, .L39+76
	ldr	r3, .L39+80
	ldr	r1, [r2]
	ldr	r3, [r3]
	ldr	r0, [r4]
	and	r1, r1, r7
	add	r0, r0, r3
	bl	WREG32
	ldr	r2, .L39+84
	ldr	r3, .L39+88
	ldr	r1, [r2]
	ldr	r3, [r3]
	ldr	r0, [r4]
	and	r1, r1, r7
	add	r0, r0, r3
	bl	WREG32
	ldr	r3, .L39+92
	ldr	r0, [r4]
	ldr	r3, [r3]
	mov	r1, r8
	add	r0, r0, r3
	bl	WREG32
	ldr	r3, .L39+96
	ldr	r0, [r4]
	ldr	r3, [r3]
	ldr	r1, [sp]
	add	r0, r0, r3
	bl	WREG32
	ldr	r3, [r10]
	ldr	r0, [r4]
	add	r0, r0, r3
	bl	RREG32
	ldr	r3, [sp, #16]
	ldr	r2, .L39+100
	cmp	r3, #0
	beq	.L20
	ldr	r3, .L39+104
	ldr	r2, [r2]
	ldr	r1, [r3]
	mov	r3, #1
	bl	REG_SET_FIELD
	ldr	r2, [r4]
	mov	r1, r0
	ldr	r0, [r10]
	add	r0, r2, r0
	bl	WREG32
	ldr	r0, .L39+108
	bl	DRM_DEBUG_KMS
.L21:
	ldr	r3, .L39+112
	ldr	r0, [r4]
	ldr	r3, [r3]
	mov	r1, #0
	add	r0, r0, r3
	bl	WREG32
	ldr	r3, .L39+116
	ldr	r0, [r4]
	ldr	r3, [r3]
	mov	r1, #0
	add	r0, r0, r3
	bl	WREG32
	ldr	r3, .L39+120
	ldr	r0, [r4]
	ldr	r3, [r3]
	mov	r1, #0
	add	r0, r0, r3
	bl	WREG32
	ldr	r3, .L39+124
	ldr	r0, [r4]
	ldr	r3, [r3]
	mov	r1, #0
	add	r0, r0, r3
	bl	WREG32
	ldr	r3, .L39+128
	ldr	r0, [r4]
	ldr	r3, [r3]
	ldr	r1, [r6]
	add	r0, r0, r3
	bl	WREG32
	ldr	r3, .L39+132
	ldr	r0, [r4]
	ldr	r3, [r3]
	ldr	r1, [r6, #4]
	add	r0, r0, r3
	bl	WREG32
	ldr	r3, [r6, #16]
	ldr	r2, [r6, #8]
	ldr	r3, [r3, #4]
	ldr	r0, [r2]
	ldr	r1, [r3]
	bl	__aeabi_idiv
	ldr	r3, .L39+136
	ldr	r2, [r4]
	mov	r1, r0
	ldr	r0, [r3]
	add	r0, r2, r0
	bl	WREG32
	mov	r1, #1
	mov	r0, r5
	bl	dce_v11_0_grph_enable
	ldr	r3, .L39+140
	ldr	r0, [r4]
	ldr	r3, [r3]
	ldr	r1, [r6, #4]
	add	r0, r0, r3
	bl	WREG32
	ldr	r3, .L39+144
	ldr	r2, .L39+148
	ldr	r0, [r3]
	ldr	r3, [sp, #8]
	ldr	ip, [r4]
	bic	r1, r3, #1
	ldr	r3, [sp, #4]
	add	r0, ip, r0
	and	r2, r2, r3, lsl #16
	orr	r1, r2, r1
	bl	WREG32
	ldr	r3, [r5, #8]
	ldr	r2, .L39+152
	ldr	r1, [r5, #4]
	ldr	r2, [r2]
	ldr	r0, [r4]
	add	r3, r3, #1
	bic	r3, r3, #1
	orr	r1, r3, r1, lsl #16
	add	r0, r0, r2
	bl	WREG32
	ldr	r3, .L39+156
	ldr	r0, [r4]
	ldr	r3, [r3]
	mov	r1, #0
	add	r0, r0, r3
	bl	WREG32
	ldr	r2, [sp, #96]
	subs	r3, fp, #0
	movne	r3, #1
	cmp	r2, #0
	movne	r3, #0
	cmp	r3, #0
	beq	.L22
	ldr	r3, [r5]
	ldr	r3, [r3]
	cmp	r3, fp
	beq	.L22
	ldr	r3, [fp, #12]
	ldr	r0, [r3]
	bl	gem_to_amdgpu_bo
	mov	r1, #1
	mov	r4, r0
	bl	amdgpu_bo_reserve
	mov	r7, r0
	subs	r0, r0, #0
	movne	r0, #1
	bl	unlikely
	cmp	r0, #0
	bne	.L1
	mov	r0, r4
	bl	amdgpu_bo_unpin
	mov	r0, r4
	bl	amdgpu_bo_unreserve
.L22:
	ldr	r0, [sp, #12]
	bl	dce_v11_0_bandwidth_update
	mov	r7, #0
.L1:
	ldr	r3, .L39
	ldr	r2, [r3]
	ldr	r3, [sp, #52]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L38
	mov	r0, r7
	add	sp, sp, #60
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L2:
	ldr	r3, [fp, #12]
	ldr	r0, [r3]
	bl	gem_to_amdgpu_bo
	mov	r1, #0
	mov	r8, r0
	bl	amdgpu_bo_reserve
	mov	r7, r0
	subs	r0, r0, #0
	movne	r0, #1
	bl	unlikely
	cmp	r0, #0
	moveq	r6, fp
	beq	.L5
	b	.L1
.L14:
	ldr	r3, .L39+24
	ldr	r8, .L39+28
	ldr	r2, [r3]
	ldr	r1, [r8]
	mov	r3, #1
	mov	r0, #0
	bl	REG_SET_FIELD
	ldr	r3, .L39+32
	ldr	r1, [r8]
	ldr	r2, [r3]
	mov	r3, #5
	bl	REG_SET_FIELD
	mov	r3, #0
	mov	r9, r0
	str	r3, [sp, #16]
	b	.L17
.L7:
	ldr	r3, .L39+24
	ldr	r8, .L39+28
	ldr	r2, [r3]
	ldr	r1, [r8]
	mov	r3, #2
	mov	r0, #0
	bl	REG_SET_FIELD
	ldr	r3, .L39+32
	ldr	r1, [r8]
	ldr	r2, [r3]
	mov	r3, #0
	bl	REG_SET_FIELD
	ldr	r3, .L39+160
	ldr	r1, [r10]
	ldr	r2, [r3]
	mov	r9, r0
	mov	r3, #2
	ldr	r0, [sp]
	bl	REG_SET_FIELD
	ldr	r3, .L39+164
	ldr	r1, [r10]
	ldr	r2, [r3]
	mov	r3, #2
	bl	REG_SET_FIELD
	mov	r3, #0
	str	r0, [sp]
	str	r3, [sp, #16]
	b	.L17
.L9:
	ldr	r3, .L39+24
	ldr	r8, .L39+28
	ldr	r2, [r3]
	mov	r3, #1
	ldr	r1, [r8]
.L32:
	mov	r0, #0
.L31:
	bl	REG_SET_FIELD
	ldr	r3, .L39+32
	ldr	r1, [r8]
	ldr	r2, [r3]
	mov	r3, #0
	bl	REG_SET_FIELD
	mov	r3, #0
	mov	r9, r0
	str	r3, [sp, #16]
	b	.L17
.L10:
	ldr	r3, .L39+24
	ldr	r8, .L39+28
	ldr	r2, [r3]
	ldr	r1, [r8]
	mov	r3, #2
	mov	r0, #0
	bl	REG_SET_FIELD
	ldr	r3, .L39+32
	ldr	r1, [r8]
	ldr	r2, [r3]
	mov	r3, #1
	bl	REG_SET_FIELD
	mov	r3, #1
	mov	r9, r0
	str	r3, [sp, #16]
	b	.L17
.L11:
	ldr	r3, .L39+24
	ldr	r8, .L39+28
	ldr	r2, [r3]
	ldr	r1, [r8]
	mov	r3, #1
	mov	r0, #0
	bl	REG_SET_FIELD
	ldr	r3, .L39+32
	ldr	r1, [r8]
	ldr	r2, [r3]
	mov	r3, #2
	bl	REG_SET_FIELD
	mov	r3, #0
	mov	r9, r0
	str	r3, [sp, #16]
	b	.L17
.L12:
	ldr	r3, .L39+24
	ldr	r8, .L39+28
	ldr	r2, [r3]
	ldr	r1, [r8]
	mov	r3, #2
	b	.L32
.L16:
	ldr	r3, .L39+24
	ldr	r8, .L39+28
	ldr	r2, [r3]
	ldr	r1, [r8]
	mov	r3, #1
	mov	r0, #0
	bl	REG_SET_FIELD
	ldr	r3, .L39+32
	ldr	r1, [r8]
	ldr	r2, [r3]
	mov	r3, #1
	bl	REG_SET_FIELD
	mov	r3, #0
	mov	r9, r0
	str	r3, [sp, #16]
	b	.L17
.L15:
	mov	r3, #0
	ldr	r2, .L39+24
	ldr	r8, .L39+28
	mov	r0, r3
	ldr	r2, [r2]
	ldr	r1, [r8]
	b	.L31
.L20:
	ldr	r1, .L39+104
	ldr	r3, [sp, #16]
	ldr	r2, [r2]
	ldr	r1, [r1]
	bl	REG_SET_FIELD
	ldr	r2, [r4]
	mov	r1, r0
	ldr	r0, [r10]
	add	r0, r2, r0
	bl	WREG32
	b	.L21
.L36:
	ldr	r3, .L39+168
	ldr	r0, [sp, #44]
	ldr	r1, [r3]
	bl	AMDGPU_TILING_GET
	mov	r3, r0
	ldr	r2, .L39+172
	ldr	r0, [sp, #44]
	ldr	r1, [r2]
	str	r3, [sp, #24]
	bl	AMDGPU_TILING_GET
	mov	r3, r0
	ldr	r2, .L39+176
	ldr	r0, [sp, #44]
	ldr	r1, [r2]
	str	r3, [sp, #28]
	bl	AMDGPU_TILING_GET
	mov	r3, r0
	ldr	r2, .L39+180
	ldr	r0, [sp, #44]
	ldr	r1, [r2]
	str	r3, [sp, #32]
	bl	AMDGPU_TILING_GET
	mov	r2, r0
	ldr	r3, .L39+184
	ldr	r0, [sp, #44]
	ldr	r1, [r3]
	str	r2, [sp, #36]
	bl	AMDGPU_TILING_GET
	ldr	r2, .L39+188
	mov	r3, r0
	ldr	r2, [r2]
	mov	r0, r9
	ldr	r1, [r8]
	bl	REG_SET_FIELD
	ldr	r2, .L39+192
	ldr	r3, [r10]
	ldr	r2, [r2]
	ldr	r1, [r8]
	bl	REG_SET_FIELD
	ldr	r2, .L39+196
	ldr	r3, [sp, #36]
	ldr	r2, [r2]
	ldr	r1, [r8]
	bl	REG_SET_FIELD
	ldr	r2, .L39+200
	ldr	r3, [sp, #24]
	ldr	r2, [r2]
	ldr	r1, [r8]
	bl	REG_SET_FIELD
	ldr	r2, .L39+204
	ldr	r3, [sp, #28]
	ldr	r2, [r2]
	ldr	r1, [r8]
	bl	REG_SET_FIELD
	ldr	r2, .L39+208
	ldr	r3, [sp, #32]
	ldr	r2, [r2]
	ldr	r1, [r8]
	bl	REG_SET_FIELD
	ldr	r3, .L39+212
	ldr	r2, .L39+216
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	r1, [r8]
	bl	REG_SET_FIELD
	mov	r9, r0
	b	.L19
.L37:
	ldr	r2, .L39+192
	mov	r3, r0
	ldr	r2, [r2]
	mov	r0, r9
	ldr	r1, [r8]
	bl	REG_SET_FIELD
	mov	r9, r0
	b	.L19
.L35:
	mov	r0, r8
	bl	amdgpu_bo_unreserve
	ldr	r3, .L39+220
	ldr	r7, [r3]
	rsb	r7, r7, #0
	b	.L1
.L34:
	ldr	r0, .L39+224
	mov	r7, r6
	bl	DRM_DEBUG_KMS
	b	.L1
.L38:
	bl	__stack_chk_fail
.L6:
	add	r1, sp, #48
	bl	drm_get_format_name
	mov	r1, r0
	ldr	r0, .L39+228
	bl	DRM_ERROR
	ldr	r3, .L39+220
	ldr	r7, [r3]
	rsb	r7, r7, #0
	b	.L1
.L40:
	.align	2
.L39:
	.word	.LC3
	.word	ENDIAN_NONE
	.word	GRPH_ENDIAN_SWAP
	.word	GRPH_SWAP_CNTL
	.word	AMDGPU_GEM_DOMAIN_VRAM
	.word	PIPE_CONFIG
	.word	GRPH_DEPTH
	.word	GRPH_CONTROL
	.word	GRPH_FORMAT
	.word	ARRAY_MODE
	.word	ARRAY_2D_TILED_THIN1
	.word	ARRAY_1D_TILED_THIN1
	.word	GRPH_PIPE_CONFIG
	.word	mmGRPH_FLIP_CONTROL
	.word	mmGRPH_LUT_10BIT_BYPASS
	.word	GRPH_FLIP_CONTROL
	.word	GRPH_SURFACE_UPDATE_H_RETRACE_EN
	.word	mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
	.word	mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH
	.word	GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK
	.word	mmGRPH_PRIMARY_SURFACE_ADDRESS
	.word	GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK
	.word	mmGRPH_SECONDARY_SURFACE_ADDRESS
	.word	mmGRPH_CONTROL
	.word	mmGRPH_SWAP_CNTL
	.word	GRPH_LUT_10BIT_BYPASS_EN
	.word	GRPH_LUT_10BIT_BYPASS
	.word	.LC2
	.word	mmGRPH_SURFACE_OFFSET_X
	.word	mmGRPH_SURFACE_OFFSET_Y
	.word	mmGRPH_X_START
	.word	mmGRPH_Y_START
	.word	mmGRPH_X_END
	.word	mmGRPH_Y_END
	.word	mmGRPH_PITCH
	.word	mmLB_DESKTOP_HEIGHT
	.word	mmVIEWPORT_START
	.word	-262144
	.word	mmVIEWPORT_SIZE
	.word	mmCRTC_MASTER_UPDATE_MODE
	.word	GRPH_RED_CROSSBAR
	.word	GRPH_BLUE_CROSSBAR
	.word	BANK_WIDTH
	.word	BANK_HEIGHT
	.word	MACRO_TILE_ASPECT
	.word	TILE_SPLIT
	.word	NUM_BANKS
	.word	GRPH_NUM_BANKS
	.word	GRPH_ARRAY_MODE
	.word	GRPH_TILE_SPLIT
	.word	GRPH_BANK_WIDTH
	.word	GRPH_BANK_HEIGHT
	.word	GRPH_MACRO_TILE_ASPECT
	.word	ADDR_SURF_MICRO_TILING_DISPLAY
	.word	GRPH_MICRO_TILE_MODE
	.word	EINVAL
	.word	.LC0
	.word	.LC1
	.size	dce_v11_0_crtc_do_set_base, .-dce_v11_0_crtc_do_set_base
	.comm	mmVIEWPORT_START,4,4
	.comm	mmVIEWPORT_SIZE,4,4
	.comm	mmLB_DESKTOP_HEIGHT,4,4
	.comm	mmGRPH_Y_START,4,4
	.comm	mmGRPH_Y_END,4,4
	.comm	mmGRPH_X_START,4,4
	.comm	mmGRPH_X_END,4,4
	.comm	mmGRPH_SWAP_CNTL,4,4
	.comm	mmGRPH_SURFACE_OFFSET_Y,4,4
	.comm	mmGRPH_SURFACE_OFFSET_X,4,4
	.comm	mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH,4,4
	.comm	mmGRPH_SECONDARY_SURFACE_ADDRESS,4,4
	.comm	mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH,4,4
	.comm	mmGRPH_PRIMARY_SURFACE_ADDRESS,4,4
	.comm	mmGRPH_PITCH,4,4
	.comm	mmGRPH_LUT_10BIT_BYPASS,4,4
	.comm	mmGRPH_FLIP_CONTROL,4,4
	.comm	mmGRPH_CONTROL,4,4
	.comm	mmCRTC_MASTER_UPDATE_MODE,4,4
	.comm	TILE_SPLIT,4,4
	.comm	PIPE_CONFIG,4,4
	.comm	NUM_BANKS,4,4
	.comm	MACRO_TILE_ASPECT,4,4
	.comm	GRPH_TILE_SPLIT,4,4
	.comm	GRPH_SWAP_CNTL,4,4
	.comm	GRPH_SURFACE_UPDATE_H_RETRACE_EN,4,4
	.comm	GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK,4,4
	.comm	GRPH_RED_CROSSBAR,4,4
	.comm	GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK,4,4
	.comm	GRPH_PIPE_CONFIG,4,4
	.comm	GRPH_NUM_BANKS,4,4
	.comm	GRPH_MICRO_TILE_MODE,4,4
	.comm	GRPH_MACRO_TILE_ASPECT,4,4
	.comm	GRPH_LUT_10BIT_BYPASS_EN,4,4
	.comm	GRPH_LUT_10BIT_BYPASS,4,4
	.comm	GRPH_FORMAT,4,4
	.comm	GRPH_FLIP_CONTROL,4,4
	.comm	GRPH_ENDIAN_SWAP,4,4
	.comm	GRPH_DEPTH,4,4
	.comm	GRPH_CONTROL,4,4
	.comm	GRPH_BLUE_CROSSBAR,4,4
	.comm	GRPH_BANK_WIDTH,4,4
	.comm	GRPH_BANK_HEIGHT,4,4
	.comm	GRPH_ARRAY_MODE,4,4
	.comm	ENDIAN_NONE,4,4
	.comm	ENDIAN_8IN32,4,4
	.comm	ENDIAN_8IN16,4,4
	.comm	EINVAL,4,4
	.comm	BANK_WIDTH,4,4
	.comm	BANK_HEIGHT,4,4
	.comm	ARRAY_MODE,4,4
	.comm	ARRAY_2D_TILED_THIN1,4,4
	.comm	ARRAY_1D_TILED_THIN1,4,4
	.comm	AMDGPU_GEM_DOMAIN_VRAM,4,4
	.comm	ADDR_SURF_MICRO_TILING_DISPLAY,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
