	.file	"extr_intel_lrc.c_gen11_emit_flush_render.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	gen11_emit_flush_render, @function
gen11_emit_flush_render:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	ebx, esi
	sub	rsp, 40
	.cfi_def_cfa_offset 96
	mov	rax, QWORD PTR [rdi]
	mov	esi, DWORD PTR INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH[rip]
	mov	edi, DWORD PTR [rax]
	call	intel_gt_scratch_offset@PLT
	mov	r12d, eax
	test	DWORD PTR EMIT_FLUSH[rip], ebx
	jne	.L15
	test	DWORD PTR EMIT_INVALIDATE[rip], ebx
	jne	.L16
.L1:
	add	rsp, 40
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	xor	eax, eax
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L15:
	.cfi_restore_state
	mov	eax, DWORD PTR PIPE_CONTROL_DEPTH_CACHE_FLUSH[rip]
	mov	esi, 6
	mov	rdi, rbp
	mov	r14d, DWORD PTR PIPE_CONTROL_CS_STALL[rip]
	mov	r15d, DWORD PTR PIPE_CONTROL_TILE_CACHE_FLUSH[rip]
	mov	r13d, DWORD PTR PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH[rip]
	mov	DWORD PTR 8[rsp], eax
	mov	eax, DWORD PTR PIPE_CONTROL_DC_FLUSH_ENABLE[rip]
	mov	DWORD PTR 12[rsp], eax
	mov	eax, DWORD PTR PIPE_CONTROL_FLUSH_ENABLE[rip]
	mov	DWORD PTR 16[rsp], eax
	mov	eax, DWORD PTR PIPE_CONTROL_QW_WRITE[rip]
	mov	DWORD PTR 20[rsp], eax
	mov	eax, DWORD PTR PIPE_CONTROL_GLOBAL_GTT_IVB[rip]
	mov	DWORD PTR 24[rsp], eax
	call	intel_ring_begin@PLT
	mov	rdi, rax
	mov	QWORD PTR [rsp], rax
	call	IS_ERR@PLT
	mov	rdi, QWORD PTR [rsp]
	test	rax, rax
	jne	.L13
	mov	esi, r14d
	mov	edx, r12d
	or	esi, r15d
	or	esi, r13d
	or	esi, DWORD PTR 8[rsp]
	or	esi, DWORD PTR 12[rsp]
	or	esi, DWORD PTR 16[rsp]
	or	esi, DWORD PTR 20[rsp]
	or	esi, DWORD PTR 24[rsp]
	call	gen8_emit_pipe_control@PLT
	mov	rdi, rbp
	mov	rsi, rax
	call	intel_ring_advance@PLT
	test	DWORD PTR EMIT_INVALIDATE[rip], ebx
	je	.L1
.L16:
	mov	eax, DWORD PTR PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE[rip]
	mov	esi, 6
	mov	rdi, rbp
	mov	r14d, DWORD PTR PIPE_CONTROL_CS_STALL[rip]
	mov	r15d, DWORD PTR PIPE_CONTROL_COMMAND_CACHE_INVALIDATE[rip]
	mov	r13d, DWORD PTR PIPE_CONTROL_TLB_INVALIDATE[rip]
	mov	DWORD PTR 8[rsp], eax
	mov	eax, DWORD PTR PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE[rip]
	mov	ebx, DWORD PTR PIPE_CONTROL_VF_CACHE_INVALIDATE[rip]
	mov	DWORD PTR 12[rsp], eax
	mov	eax, DWORD PTR PIPE_CONTROL_CONST_CACHE_INVALIDATE[rip]
	mov	DWORD PTR 16[rsp], eax
	mov	eax, DWORD PTR PIPE_CONTROL_STATE_CACHE_INVALIDATE[rip]
	mov	DWORD PTR 20[rsp], eax
	mov	eax, DWORD PTR PIPE_CONTROL_QW_WRITE[rip]
	mov	DWORD PTR 24[rsp], eax
	mov	eax, DWORD PTR PIPE_CONTROL_GLOBAL_GTT_IVB[rip]
	mov	DWORD PTR 28[rsp], eax
	call	intel_ring_begin@PLT
	mov	rdi, rax
	mov	QWORD PTR [rsp], rax
	call	IS_ERR@PLT
	mov	rdi, QWORD PTR [rsp]
	test	rax, rax
	jne	.L13
	mov	esi, r14d
	mov	edx, r12d
	or	esi, r15d
	or	esi, r13d
	or	esi, DWORD PTR 8[rsp]
	or	esi, DWORD PTR 12[rsp]
	or	esi, ebx
	or	esi, DWORD PTR 16[rsp]
	or	esi, DWORD PTR 20[rsp]
	or	esi, DWORD PTR 24[rsp]
	or	esi, DWORD PTR 28[rsp]
	call	gen8_emit_pipe_control@PLT
	mov	rdi, rbp
	mov	rsi, rax
	call	intel_ring_advance@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L13:
	add	rsp, 40
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	jmp	PTR_ERR@PLT
	.cfi_endproc
.LFE0:
	.size	gen11_emit_flush_render, .-gen11_emit_flush_render
	.comm	PIPE_CONTROL_VF_CACHE_INVALIDATE,4,4
	.comm	PIPE_CONTROL_TLB_INVALIDATE,4,4
	.comm	PIPE_CONTROL_TILE_CACHE_FLUSH,4,4
	.comm	PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE,4,4
	.comm	PIPE_CONTROL_STATE_CACHE_INVALIDATE,4,4
	.comm	PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH,4,4
	.comm	PIPE_CONTROL_QW_WRITE,4,4
	.comm	PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE,4,4
	.comm	PIPE_CONTROL_GLOBAL_GTT_IVB,4,4
	.comm	PIPE_CONTROL_FLUSH_ENABLE,4,4
	.comm	PIPE_CONTROL_DEPTH_CACHE_FLUSH,4,4
	.comm	PIPE_CONTROL_DC_FLUSH_ENABLE,4,4
	.comm	PIPE_CONTROL_CS_STALL,4,4
	.comm	PIPE_CONTROL_CONST_CACHE_INVALIDATE,4,4
	.comm	PIPE_CONTROL_COMMAND_CACHE_INVALIDATE,4,4
	.comm	INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH,4,4
	.comm	EMIT_INVALIDATE,4,4
	.comm	EMIT_FLUSH,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_intel_lrc.c_gen11_emit_flush_render.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	gen11_emit_flush_render, %function
gen11_emit_flush_render:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r2, [r0]
	ldr	r3, .L18
	mov	r5, r1
	mov	r4, r0
	ldr	r1, [r3]
	ldr	r0, [r2]
	sub	sp, sp, #28
	bl	intel_gt_scratch_offset
	ldr	r3, .L18+4
	mov	r2, r0
	ldr	r3, [r3]
	tst	r5, r3
	bne	.L15
	ldr	r3, .L18+8
	ldr	r3, [r3]
	tst	r5, r3
	bne	.L16
.L1:
	mov	r0, #0
	add	sp, sp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L15:
	ldr	r6, .L18+12
	ldr	lr, .L18+16
	ldr	r2, [r6]
	ldr	ip, .L18+20
	str	r2, [sp, #8]
	ldr	r2, [lr]
	ldr	r3, .L18+24
	ldr	r10, .L18+28
	str	r2, [sp, #12]
	ldr	r9, .L18+32
	ldr	r2, [ip]
	ldr	r8, .L18+36
	ldr	r7, .L18+40
	mov	r1, #6
	str	r0, [sp, #4]
	mov	r0, r4
	str	r2, [sp, #16]
	ldr	fp, [r10]
	ldr	r9, [r9]
	ldr	r10, [r3]
	ldr	r8, [r8]
	ldr	r7, [r7]
	bl	intel_ring_begin
	mov	r6, r0
	bl	IS_ERR
	cmp	r0, #0
	movne	r0, r6
	ldr	r2, [sp, #4]
	bne	.L13
	orr	r1, r9, fp
	ldr	r3, [sp, #8]
	orr	r1, r8, r1
	orr	r1, r7, r1
	orr	r1, r3, r1
	ldr	r3, [sp, #12]
	mov	r0, r6
	orr	r1, r3, r1
	ldr	r3, [sp, #16]
	str	r2, [sp, #4]
	orr	r1, r3, r1
	orr	r1, r10, r1
	bl	gen8_emit_pipe_control
	mov	r1, r0
	mov	r0, r4
	bl	intel_ring_advance
	ldr	r3, .L18+8
	ldr	r2, [sp, #4]
	ldr	r3, [r3]
	tst	r5, r3
	beq	.L1
.L16:
	ldr	fp, .L18+44
	ldr	r9, .L18+48
	str	r2, [sp, #4]
	ldr	r2, [fp]
	ldr	lr, .L18+52
	str	r2, [sp, #8]
	ldr	r2, [r9]
	ldr	ip, .L18+20
	str	r2, [sp, #12]
	ldr	r2, [lr]
	ldr	r3, .L18+24
	str	r2, [sp, #16]
	ldr	r8, .L18+32
	ldr	r2, [ip]
	ldr	r10, .L18+56
	ldr	r7, .L18+60
	ldr	r6, .L18+64
	ldr	r5, .L18+68
	mov	r1, #6
	mov	r0, r4
	str	r2, [sp, #20]
	ldr	r9, [r3]
	ldr	r8, [r8]
	ldr	r10, [r10]
	ldr	r7, [r7]
	ldr	r6, [r6]
	ldr	r5, [r5]
	bl	intel_ring_begin
	mov	fp, r0
	bl	IS_ERR
	cmp	r0, #0
	ldr	r2, [sp, #4]
	bne	.L17
	orr	r1, r8, r10
	orr	r1, r7, r1
	ldr	r3, [sp, #8]
	orr	r1, r6, r1
	orr	r1, r5, r1
	orr	r1, r3, r1
	ldr	r3, [sp, #12]
	mov	r0, fp
	orr	r1, r3, r1
	ldr	r3, [sp, #16]
	orr	r1, r3, r1
	ldr	r3, [sp, #20]
	orr	r1, r3, r1
	orr	r1, r9, r1
	bl	gen8_emit_pipe_control
	mov	r1, r0
	mov	r0, r4
	bl	intel_ring_advance
	mov	r0, #0
	add	sp, sp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L17:
	mov	r0, fp
.L13:
	add	sp, sp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	b	PTR_ERR
.L19:
	.align	2
.L18:
	.word	INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH
	.word	EMIT_FLUSH
	.word	EMIT_INVALIDATE
	.word	PIPE_CONTROL_DC_FLUSH_ENABLE
	.word	PIPE_CONTROL_FLUSH_ENABLE
	.word	PIPE_CONTROL_QW_WRITE
	.word	PIPE_CONTROL_GLOBAL_GTT_IVB
	.word	PIPE_CONTROL_TILE_CACHE_FLUSH
	.word	PIPE_CONTROL_CS_STALL
	.word	PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
	.word	PIPE_CONTROL_DEPTH_CACHE_FLUSH
	.word	PIPE_CONTROL_VF_CACHE_INVALIDATE
	.word	PIPE_CONTROL_CONST_CACHE_INVALIDATE
	.word	PIPE_CONTROL_STATE_CACHE_INVALIDATE
	.word	PIPE_CONTROL_COMMAND_CACHE_INVALIDATE
	.word	PIPE_CONTROL_TLB_INVALIDATE
	.word	PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
	.word	PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
	.size	gen11_emit_flush_render, .-gen11_emit_flush_render
	.comm	PIPE_CONTROL_VF_CACHE_INVALIDATE,4,4
	.comm	PIPE_CONTROL_TLB_INVALIDATE,4,4
	.comm	PIPE_CONTROL_TILE_CACHE_FLUSH,4,4
	.comm	PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE,4,4
	.comm	PIPE_CONTROL_STATE_CACHE_INVALIDATE,4,4
	.comm	PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH,4,4
	.comm	PIPE_CONTROL_QW_WRITE,4,4
	.comm	PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE,4,4
	.comm	PIPE_CONTROL_GLOBAL_GTT_IVB,4,4
	.comm	PIPE_CONTROL_FLUSH_ENABLE,4,4
	.comm	PIPE_CONTROL_DEPTH_CACHE_FLUSH,4,4
	.comm	PIPE_CONTROL_DC_FLUSH_ENABLE,4,4
	.comm	PIPE_CONTROL_CS_STALL,4,4
	.comm	PIPE_CONTROL_CONST_CACHE_INVALIDATE,4,4
	.comm	PIPE_CONTROL_COMMAND_CACHE_INVALIDATE,4,4
	.comm	INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH,4,4
	.comm	EMIT_INVALIDATE,4,4
	.comm	EMIT_FLUSH,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
