	.file	"extr_synclink_gt.c_rx_start.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	rx_start, @function
rx_start:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	mov	rbx, rdi
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	movzx	esi, WORD PTR IRQ_RXDATA[rip]
	add	si, WORD PTR IRQ_RXOVER[rip]
	movzx	esi, si
	call	slgt_irq_off@PLT
	movzx	edx, WORD PTR IRQ_RXOVER[rip]
	mov	esi, DWORD PTR SSR[rip]
	mov	rdi, rbx
	call	wr_reg16@PLT
	mov	esi, DWORD PTR RCR[rip]
	mov	rdi, rbx
	call	rd_reg16@PLT
	movzx	ebp, WORD PTR BIT1[rip]
	movzx	edx, WORD PTR BIT2[rip]
	mov	rdi, rbx
	mov	esi, DWORD PTR RCR[rip]
	not	ebp
	and	ebp, eax
	or	edx, ebp
	movzx	edx, dx
	call	wr_reg16@PLT
	mov	esi, DWORD PTR RCR[rip]
	movzx	edx, bp
	mov	rdi, rbx
	call	wr_reg16@PLT
	mov	rdi, rbx
	call	rdma_reset@PLT
	mov	rdi, rbx
	call	reset_rbufs@PLT
	cmp	QWORD PTR 24[rbx], 0
	mov	esi, DWORD PTR SCR[rip]
	mov	rdi, rbx
	je	.L2
	call	rd_reg16@PLT
	mov	esi, DWORD PTR SCR[rip]
	mov	rdi, rbx
	mov	r8d, eax
	movzx	eax, WORD PTR BIT14[rip]
	not	eax
	and	eax, r8d
	movzx	edx, ax
	call	wr_reg16@PLT
	movzx	esi, WORD PTR IRQ_RXDATA[rip]
	mov	rdi, rbx
	call	slgt_irq_on@PLT
	mov	rax, QWORD PTR MGSL_MODE_ASYNC[rip]
	cmp	QWORD PTR 8[rbx], rax
	je	.L8
.L3:
	movzx	esi, WORD PTR IRQ_RXOVER[rip]
	mov	rdi, rbx
	call	slgt_irq_on@PLT
	mov	esi, DWORD PTR RCR[rip]
	mov	rdi, rbx
	call	rd_reg16@PLT
	mov	esi, DWORD PTR RCR[rip]
	or	ax, WORD PTR BIT1[rip]
	mov	rdi, rbx
	movzx	edx, ax
	call	wr_reg16@PLT
	movabs	rax, 4294967296
	mov	QWORD PTR [rbx], rax
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L2:
	.cfi_restore_state
	call	rd_reg16@PLT
	mov	esi, DWORD PTR SCR[rip]
	or	ax, WORD PTR BIT14[rip]
	mov	rdi, rbx
	movzx	edx, ax
	call	wr_reg16@PLT
	mov	rax, QWORD PTR 16[rbx]
	mov	esi, DWORD PTR RDDAR[rip]
	mov	rdi, rbx
	mov	rdx, QWORD PTR [rax]
	call	wr_reg32@PLT
	mov	rax, QWORD PTR MGSL_MODE_ASYNC[rip]
	movzx	edx, WORD PTR BIT2[rip]
	cmp	QWORD PTR 8[rbx], rax
	jne	.L6
	add	rdx, QWORD PTR BIT6[rip]
.L6:
	mov	esi, DWORD PTR RDCSR[rip]
	add	rdx, QWORD PTR BIT0[rip]
	mov	rdi, rbx
	call	wr_reg32@PLT
	jmp	.L3
	.p2align 4,,10
	.p2align 3
.L8:
	mov	rdx, QWORD PTR BIT6[rip]
	mov	esi, DWORD PTR RDCSR[rip]
	mov	rdi, rbx
	call	wr_reg32@PLT
	jmp	.L3
	.cfi_endproc
.LFE0:
	.size	rx_start, .-rx_start
	.comm	SSR,4,4
	.comm	SCR,4,4
	.comm	RDDAR,4,4
	.comm	RDCSR,4,4
	.comm	RCR,4,4
	.comm	MGSL_MODE_ASYNC,8,8
	.comm	IRQ_RXOVER,2,2
	.comm	IRQ_RXDATA,2,2
	.comm	BIT6,8,8
	.comm	BIT2,2,2
	.comm	BIT14,2,2
	.comm	BIT1,2,2
	.comm	BIT0,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_synclink_gt.c_rx_start.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	rx_start, %function
rx_start:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, lr}
	mov	r4, r0
	ldr	r7, .L8
	ldr	r10, .L8+4
	ldrh	r1, [r7]
	ldrh	r3, [r10]
	ldr	r6, .L8+8
	add	r1, r1, r3
	lsl	r1, r1, #16
	lsr	r1, r1, #16
	bl	slgt_irq_off
	ldr	r3, .L8+12
	ldrh	r2, [r7]
	ldr	r1, [r3]
	mov	r0, r4
	bl	wr_reg16
	ldr	r1, [r6]
	mov	r0, r4
	bl	rd_reg16
	ldr	r8, .L8+16
	ldr	r9, .L8+20
	ldrh	r5, [r8]
	ldrh	r2, [r9]
	bic	r5, r0, r5
	lsl	r5, r5, #16
	lsr	r5, r5, #16
	orr	r2, r5, r2
	ldr	r1, [r6]
	mov	r0, r4
	bl	wr_reg16
	mov	r2, r5
	ldr	r1, [r6]
	mov	r0, r4
	bl	wr_reg16
	mov	r0, r4
	bl	rdma_reset
	mov	r0, r4
	bl	reset_rbufs
	ldr	r3, [r4, #16]
	mov	r0, r4
	cmp	r3, #0
	ldr	r3, .L8+24
	ldr	r5, [r3]
	mov	r1, r5
	beq	.L2
	bl	rd_reg16
	mov	r2, r0
	ldr	r3, .L8+28
	mov	r1, r5
	ldrh	r3, [r3]
	mov	r0, r4
	bic	r2, r2, r3
	lsl	r2, r2, #16
	lsr	r2, r2, #16
	bl	wr_reg16
	mov	r0, r4
	ldrh	r1, [r10]
	bl	slgt_irq_on
	ldr	r3, .L8+32
	ldr	r2, [r4, #8]
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L7
.L3:
	ldrh	r1, [r7]
	mov	r0, r4
	bl	slgt_irq_on
	ldr	r5, [r6]
	mov	r0, r4
	mov	r1, r5
	bl	rd_reg16
	ldrh	r2, [r8]
	mov	r1, r5
	orr	r2, r0, r2
	lsl	r2, r2, #16
	lsr	r2, r2, #16
	mov	r0, r4
	bl	wr_reg16
	mov	r2, #0
	mov	r3, #1
	stm	r4, {r2, r3}
	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
.L2:
	bl	rd_reg16
	mov	r2, r0
	ldr	r3, .L8+28
	mov	r1, r5
	ldrh	r3, [r3]
	mov	r0, r4
	orr	r2, r2, r3
	lsl	r2, r2, #16
	lsr	r2, r2, #16
	bl	wr_reg16
	ldr	r3, .L8+36
	ldr	r2, [r4, #12]
	ldr	r1, [r3]
	ldr	r2, [r2]
	mov	r0, r4
	bl	wr_reg32
	ldr	r3, .L8+32
	ldr	r2, [r4, #8]
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L4
	ldr	r3, .L8+40
	ldrh	r1, [r9]
	ldr	r2, [r3]
	ldr	r3, .L8+44
	add	r2, r1, r2
	mov	r0, r4
	ldr	r1, [r3]
	bl	wr_reg32
	b	.L3
.L7:
	ldr	r3, .L8+44
	ldr	r2, .L8+48
	mov	r0, r4
	ldr	r2, [r2]
	ldr	r1, [r3]
	bl	wr_reg32
	b	.L3
.L4:
	ldr	r1, .L8+48
	ldr	r2, .L8+40
	ldr	r0, [r1]
	ldrh	r3, [r9]
	ldr	r2, [r2]
	ldr	r1, .L8+44
	add	r3, r3, r0
	ldr	r1, [r1]
	mov	r0, r4
	add	r2, r3, r2
	bl	wr_reg32
	b	.L3
.L9:
	.align	2
.L8:
	.word	IRQ_RXOVER
	.word	IRQ_RXDATA
	.word	RCR
	.word	SSR
	.word	BIT1
	.word	BIT2
	.word	SCR
	.word	BIT14
	.word	MGSL_MODE_ASYNC
	.word	RDDAR
	.word	BIT0
	.word	RDCSR
	.word	BIT6
	.size	rx_start, .-rx_start
	.comm	SSR,4,4
	.comm	SCR,4,4
	.comm	RDDAR,4,4
	.comm	RDCSR,4,4
	.comm	RCR,4,4
	.comm	MGSL_MODE_ASYNC,4,4
	.comm	IRQ_RXOVER,2,2
	.comm	IRQ_RXDATA,2,2
	.comm	BIT6,4,4
	.comm	BIT2,2,2
	.comm	BIT14,2,2
	.comm	BIT1,2,2
	.comm	BIT0,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
