	.file	"extr_pinctrl-intel.c_intel_gpio_add_pin_ranges.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	intel_gpio_add_pin_ranges, @function
intel_gpio_add_pin_ranges:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 24
	.cfi_def_cfa_offset 80
	mov	eax, DWORD PTR [rsi]
	mov	QWORD PTR 8[rsp], rdi
	test	eax, eax
	jle	.L2
	mov	r14, rsi
	xor	ebx, ebx
	lea	r13, 4[rdi]
	.p2align 4,,10
	.p2align 3
.L4:
	mov	rax, rbx
	sal	rax, 4
	add	rax, QWORD PTR 8[r14]
	mov	r12, QWORD PTR [rax]
	test	r12, r12
	js	.L6
	mov	ebp, DWORD PTR 8[rax]
	mov	r15d, DWORD PTR 12[rax]
	mov	rax, QWORD PTR 8[rsp]
	mov	edi, DWORD PTR [rax]
	call	dev_name@PLT
	mov	r8d, ebp
	mov	ecx, r15d
	mov	rdx, r12
	mov	esi, eax
	mov	rdi, r13
	call	gpiochip_add_pin_range@PLT
	test	eax, eax
	jne	.L1
.L6:
	add	rbx, 1
	cmp	DWORD PTR [r14], ebx
	jg	.L4
.L2:
	xor	eax, eax
.L1:
	add	rsp, 24
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE0:
	.size	intel_gpio_add_pin_ranges, .-intel_gpio_add_pin_ranges
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_pinctrl-intel.c_intel_gpio_add_pin_ranges.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	intel_gpio_add_pin_ranges, %function
intel_gpio_add_pin_ranges:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	ldr	r2, [r1]
	cmp	r2, #0
	ble	.L9
	push	{r4, r5, r6, r7, r8, r9, r10, lr}
	mov	r4, #0
	mov	r7, r1
	mov	r8, r0
	mov	r6, r4
	sub	sp, sp, #8
	add	r9, r0, #4
.L4:
	ldr	r5, [r7, #4]
	ldr	r3, [r5, r4]
	add	r10, r5, r4
	cmp	r3, #0
	blt	.L6
	ldr	r0, [r8]
	bl	dev_name
	ldr	ip, [r10, #4]
	mov	r1, r0
	ldr	r2, [r5, r4]
	ldr	r3, [r10, #8]
	mov	r0, r9
	str	ip, [sp]
	bl	gpiochip_add_pin_range
	cmp	r0, #0
	bne	.L1
	ldr	r2, [r7]
.L6:
	add	r6, r6, #1
	cmp	r2, r6
	add	r4, r4, #12
	bgt	.L4
	mov	r0, #0
.L1:
	add	sp, sp, #8
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
.L9:
	mov	r0, #0
	bx	lr
	.size	intel_gpio_add_pin_ranges, .-intel_gpio_add_pin_ranges
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
