	.file	"extr_hdmi_phy_8996.c_hdmi_8996_pll_set_clk_rate.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"PLL calculation failed\n"
.LC1:
	.string	"Disabling PHY"
	.text
	.p2align 4
	.type	hdmi_8996_pll_set_clk_rate, @function
hdmi_8996_pll_set_clk_rate:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	mov	r14, rdx
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	mov	r13, rsi
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 152
	.cfi_def_cfa_offset 208
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 136[rsp], rax
	xor	eax, eax
	mov	r15, rsp
	call	hw_clk_to_pll@PLT
	mov	rdi, rax
	mov	rbp, rax
	call	pll_get_phy@PLT
	mov	edx, 136
	xor	esi, esi
	mov	rdi, r15
	mov	r12, rax
	call	memset@PLT
	mov	rdi, r13
	mov	rdx, r15
	mov	rsi, r14
	call	pll_calculate@PLT
	mov	r13d, eax
	test	eax, eax
	jne	.L13
	lea	rdi, .LC1[rip]
	call	DBG@PLT
	mov	esi, DWORD PTR REG_HDMI_8996_PHY_PD_CTL[rip]
	xor	edx, edx
	mov	rdi, r12
	call	hdmi_phy_write@PLT
	mov	edi, 500
	call	udelay@PLT
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_BG_CTRL[rip]
	mov	edx, 4
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	esi, DWORD PTR REG_HDMI_8996_PHY_PD_CTL[rip]
	mov	edx, 1
	mov	rdi, r12
	call	hdmi_phy_write@PLT
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL[rip]
	mov	edx, 32
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	esi, DWORD PTR REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL[rip]
	mov	edx, 15
	mov	rdi, r12
	call	hdmi_phy_write@PLT
	mov	esi, DWORD PTR REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL[rip]
	mov	edx, 15
	mov	rdi, r12
	call	hdmi_phy_write@PLT
	mov	edx, DWORD PTR HDMI_NUM_TX_CHANNEL[rip]
	test	edx, edx
	jle	.L4
	xor	ebx, ebx
	.p2align 4,,10
	.p2align 3
.L5:
	mov	edx, DWORD PTR REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE[rip]
	mov	esi, ebx
	mov	ecx, 3
	mov	rdi, rbp
	call	hdmi_tx_chan_write@PLT
	mov	rax, QWORD PTR [rsp]
	mov	esi, ebx
	mov	rdi, rbp
	mov	edx, DWORD PTR REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND[rip]
	mov	ecx, DWORD PTR [rax+rbx*4]
	call	hdmi_tx_chan_write@PLT
	mov	edx, DWORD PTR REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN[rip]
	mov	esi, ebx
	mov	rdi, rbp
	mov	ecx, 3
	add	rbx, 1
	call	hdmi_tx_chan_write@PLT
	cmp	DWORD PTR HDMI_NUM_TX_CHANNEL[rip], ebx
	jg	.L5
.L4:
	mov	rax, QWORD PTR 8[rsp]
	mov	edx, DWORD PTR REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE[rip]
	xor	esi, esi
	mov	rdi, rbp
	mov	ecx, DWORD PTR [rax]
	call	hdmi_tx_chan_write@PLT
	mov	rax, QWORD PTR 8[rsp]
	mov	esi, 2
	mov	rdi, rbp
	mov	edx, DWORD PTR REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE[rip]
	mov	ecx, DWORD PTR 8[rax]
	call	hdmi_tx_chan_write@PLT
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE[rip]
	mov	edx, 30
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN[rip]
	mov	edx, 7
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL[rip]
	mov	edx, 55
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL[rip]
	mov	edx, 2
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1[rip]
	mov	edx, 14
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	edx, DWORD PTR 16[rsp]
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL[rip]
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_BG_TRIM[rip]
	mov	edx, 15
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_PLL_IVCO[rip]
	mov	edx, 15
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	edx, DWORD PTR 20[rsp]
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL[rip]
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_BG_CTRL[rip]
	mov	edx, 6
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_CLK_SELECT[rip]
	mov	edx, 48
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	edx, DWORD PTR 24[rsp]
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL[rip]
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	edx, DWORD PTR 28[rsp]
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN[rip]
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	edx, DWORD PTR 32[rsp]
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0[rip]
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	edx, DWORD PTR 36[rsp]
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0[rip]
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	edx, DWORD PTR 40[rsp]
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0[rip]
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	edx, DWORD PTR 44[rsp]
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0[rip]
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	edx, DWORD PTR 48[rsp]
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0[rip]
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	edx, DWORD PTR 52[rsp]
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0[rip]
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	edx, DWORD PTR 56[rsp]
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0[rip]
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	edx, DWORD PTR 60[rsp]
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0[rip]
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	edx, DWORD PTR 64[rsp]
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0[rip]
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	edx, DWORD PTR 68[rsp]
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0[rip]
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	edx, DWORD PTR 72[rsp]
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0[rip]
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	edx, DWORD PTR 76[rsp]
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0[rip]
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP[rip]
	xor	edx, edx
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	edx, DWORD PTR 80[rsp]
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN[rip]
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	edx, DWORD PTR 84[rsp]
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV[rip]
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG[rip]
	mov	edx, 2
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	esi, DWORD PTR REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM[rip]
	mov	edx, 21
	mov	rdi, rbp
	call	hdmi_pll_write@PLT
	mov	eax, DWORD PTR HDMI_NUM_TX_CHANNEL[rip]
	test	eax, eax
	jle	.L6
	xor	ebx, ebx
	.p2align 4,,10
	.p2align 3
.L7:
	mov	rax, QWORD PTR 88[rsp]
	mov	edx, DWORD PTR REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL[rip]
	mov	esi, ebx
	mov	rdi, rbp
	mov	ecx, DWORD PTR [rax+rbx*4]
	call	hdmi_tx_chan_write@PLT
	mov	rax, QWORD PTR 96[rsp]
	mov	esi, ebx
	mov	rdi, rbp
	mov	edx, DWORD PTR REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL[rip]
	mov	ecx, DWORD PTR [rax+rbx*4]
	call	hdmi_tx_chan_write@PLT
	mov	rax, QWORD PTR 104[rsp]
	mov	esi, ebx
	mov	rdi, rbp
	mov	edx, DWORD PTR REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1[rip]
	mov	ecx, DWORD PTR [rax+rbx*4]
	call	hdmi_tx_chan_write@PLT
	mov	rax, QWORD PTR 112[rsp]
	mov	esi, ebx
	mov	rdi, rbp
	mov	edx, DWORD PTR REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2[rip]
	mov	ecx, DWORD PTR [rax+rbx*4]
	call	hdmi_tx_chan_write@PLT
	mov	edx, DWORD PTR REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET[rip]
	xor	ecx, ecx
	mov	esi, ebx
	mov	rdi, rbp
	call	hdmi_tx_chan_write@PLT
	mov	edx, DWORD PTR REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET[rip]
	xor	ecx, ecx
	mov	esi, ebx
	mov	rdi, rbp
	call	hdmi_tx_chan_write@PLT
	mov	edx, DWORD PTR REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN[rip]
	mov	esi, ebx
	mov	rdi, rbp
	mov	ecx, 3
	call	hdmi_tx_chan_write@PLT
	mov	edx, DWORD PTR REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN[rip]
	mov	esi, ebx
	mov	rdi, rbp
	mov	ecx, 64
	call	hdmi_tx_chan_write@PLT
	mov	rax, QWORD PTR 120[rsp]
	mov	esi, ebx
	mov	rdi, rbp
	mov	edx, DWORD PTR REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES[rip]
	mov	ecx, DWORD PTR [rax+rbx*4]
	add	rbx, 1
	call	hdmi_tx_chan_write@PLT
	cmp	DWORD PTR HDMI_NUM_TX_CHANNEL[rip], ebx
	jg	.L7
.L6:
	mov	edx, DWORD PTR 128[rsp]
	mov	esi, DWORD PTR REG_HDMI_8996_PHY_MODE[rip]
	mov	rdi, r12
	call	hdmi_phy_write@PLT
	mov	esi, DWORD PTR REG_HDMI_8996_PHY_PD_CTL[rip]
	mov	edx, 31
	mov	rdi, r12
	call	hdmi_phy_write@PLT
	xor	eax, eax
	call	wmb@PLT
.L1:
	mov	rax, QWORD PTR 136[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L14
	add	rsp, 152
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	eax, r13d
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L13:
	.cfi_restore_state
	lea	rdi, .LC0[rip]
	call	DRM_ERROR@PLT
	jmp	.L1
.L14:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	hdmi_8996_pll_set_clk_rate, .-hdmi_8996_pll_set_clk_rate
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_PLL_IVCO,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_CLK_SELECT,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_BG_TRIM,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_BG_CTRL,4,4
	.comm	REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL,4,4
	.comm	REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL,4,4
	.comm	REG_HDMI_8996_PHY_PD_CTL,4,4
	.comm	REG_HDMI_8996_PHY_MODE,4,4
	.comm	HDMI_NUM_TX_CHANNEL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_hdmi_phy_8996.c_hdmi_8996_pll_set_clk_rate.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"PLL calculation failed\012\000"
	.align	2
.LC1:
	.ascii	"Disabling PHY\000"
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC2:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	hdmi_8996_pll_set_clk_rate, %function
hdmi_8996_pll_set_clk_rate:
	@ args = 0, pretend = 0, frame = 120
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r3, .L15
	sub	sp, sp, #124
	ldr	r3, [r3]
	str	r3, [sp, #116]
	mov	r3,#0
	mov	r5, r1
	mov	r7, r2
	bl	hw_clk_to_pll
	mov	r4, r0
	bl	pll_get_phy
	mov	r2, #104
	mov	r1, #0
	mov	r6, r0
	add	r0, sp, #12
	bl	memset
	mov	r1, r7
	mov	r0, r5
	add	r2, sp, #12
	bl	pll_calculate
	subs	r3, r0, #0
	str	r3, [sp, #4]
	bne	.L13
	ldr	r0, .L15+4
	bl	DBG
	ldr	r5, .L15+8
	ldr	fp, [sp, #4]
	ldr	r1, [r5]
	mov	r2, fp
	mov	r0, r6
	ldr	r10, .L15+12
	bl	hdmi_phy_write
	mov	r0, #500
	bl	udelay
	mov	r2, #4
	ldr	r1, [r10]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r1, [r5]
	mov	r2, #1
	mov	r0, r6
	bl	hdmi_phy_write
	ldr	r3, .L15+16
	mov	r2, #32
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+20
	mov	r2, #15
	ldr	r1, [r3]
	mov	r0, r6
	bl	hdmi_phy_write
	ldr	r3, .L15+24
	ldr	r5, .L15+28
	ldr	r1, [r3]
	mov	r2, #15
	mov	r0, r6
	bl	hdmi_phy_write
	ldr	r3, [r5]
	cmp	r3, #0
	ble	.L4
	ldr	r9, .L15+32
	ldr	r8, .L15+36
	ldr	r7, .L15+40
.L5:
	mov	r1, fp
	mov	r3, #3
	ldr	r2, [r9]
	mov	r0, r4
	bl	hdmi_tx_chan_write
	ldr	r3, [sp, #12]
	mov	r1, fp
	ldr	r3, [r3, fp, lsl #2]
	ldr	r2, [r8]
	mov	r0, r4
	bl	hdmi_tx_chan_write
	mov	r3, #3
	mov	r1, fp
	mov	r0, r4
	ldr	r2, [r7]
	bl	hdmi_tx_chan_write
	ldr	r3, [r5]
	add	fp, fp, #1
	cmp	r3, fp
	bgt	.L5
.L4:
	ldr	r3, [sp, #16]
	ldr	r7, .L15+44
	mov	r1, #0
	ldr	r3, [r3]
	ldr	r2, [r7]
	mov	r0, r4
	bl	hdmi_tx_chan_write
	ldr	r3, [sp, #16]
	mov	r1, #2
	ldr	r2, [r7]
	ldr	r3, [r3, #8]
	mov	r0, r4
	bl	hdmi_tx_chan_write
	ldr	r3, .L15+48
	mov	r2, #30
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+52
	mov	r2, #7
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+56
	mov	r2, #55
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+60
	mov	r2, #2
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+64
	mov	r2, #14
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+68
	ldr	r2, [sp, #20]
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+72
	mov	r2, #15
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+76
	mov	r2, #15
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+80
	ldr	r2, [sp, #24]
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	mov	r2, #6
	ldr	r1, [r10]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+84
	mov	r2, #48
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+88
	ldr	r2, [sp, #28]
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+92
	ldr	r2, [sp, #32]
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+96
	ldr	r2, [sp, #36]
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+100
	ldr	r2, [sp, #40]
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+104
	ldr	r2, [sp, #44]
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+108
	ldr	r2, [sp, #48]
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+112
	ldr	r2, [sp, #52]
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+116
	ldr	r2, [sp, #56]
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+120
	ldr	r2, [sp, #60]
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+124
	ldr	r2, [sp, #64]
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+128
	ldr	r2, [sp, #68]
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+132
	ldr	r2, [sp, #72]
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+136
	ldr	r2, [sp, #76]
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+140
	ldr	r2, [sp, #80]
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+144
	mov	r2, #0
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+148
	ldr	r2, [sp, #84]
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+152
	ldr	r2, [sp, #88]
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+156
	mov	r2, #2
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, .L15+160
	mov	r2, #21
	ldr	r1, [r3]
	mov	r0, r4
	bl	hdmi_pll_write
	ldr	r3, [r5]
	cmp	r3, #0
	ble	.L6
	mov	r7, #0
	ldr	fp, .L15+164
	ldr	r10, .L15+168
	ldr	r9, .L15+172
	ldr	r8, .L15+176
.L7:
	ldr	r3, [sp, #92]
	mov	r1, r7
	ldr	r3, [r3, r7, lsl #2]
	ldr	r2, [fp]
	mov	r0, r4
	bl	hdmi_tx_chan_write
	ldr	r3, [sp, #96]
	mov	r1, r7
	ldr	r3, [r3, r7, lsl #2]
	ldr	r2, [r10]
	mov	r0, r4
	bl	hdmi_tx_chan_write
	ldr	r3, [sp, #100]
	mov	r1, r7
	ldr	r3, [r3, r7, lsl #2]
	ldr	r2, [r9]
	mov	r0, r4
	bl	hdmi_tx_chan_write
	ldr	r3, [sp, #104]
	mov	r1, r7
	ldr	r3, [r3, r7, lsl #2]
	ldr	r2, [r8]
	mov	r0, r4
	bl	hdmi_tx_chan_write
	ldr	r2, .L15+180
	mov	r1, r7
	mov	r3, #0
	ldr	r2, [r2]
	mov	r0, r4
	bl	hdmi_tx_chan_write
	ldr	r2, .L15+184
	mov	r1, r7
	mov	r3, #0
	ldr	r2, [r2]
	mov	r0, r4
	bl	hdmi_tx_chan_write
	ldr	r2, .L15+188
	mov	r1, r7
	mov	r3, #3
	ldr	r2, [r2]
	mov	r0, r4
	bl	hdmi_tx_chan_write
	ldr	r2, .L15+192
	mov	r1, r7
	mov	r3, #64
	ldr	r2, [r2]
	mov	r0, r4
	bl	hdmi_tx_chan_write
	ldr	r3, [sp, #108]
	ldr	r2, .L15+196
	ldr	r3, [r3, r7, lsl #2]
	mov	r1, r7
	mov	r0, r4
	ldr	r2, [r2]
	bl	hdmi_tx_chan_write
	ldr	r3, [r5]
	add	r7, r7, #1
	cmp	r3, r7
	bgt	.L7
.L6:
	ldr	r3, .L15+200
	ldr	r2, [sp, #112]
	ldr	r1, [r3]
	mov	r0, r6
	bl	hdmi_phy_write
	ldr	r3, .L15+8
	mov	r2, #31
	ldr	r1, [r3]
	mov	r0, r6
	bl	hdmi_phy_write
	bl	wmb
.L1:
	ldr	r3, .L15
	ldr	r2, [r3]
	ldr	r3, [sp, #116]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L14
	ldr	r0, [sp, #4]
	add	sp, sp, #124
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L13:
	ldr	r0, .L15+204
	bl	DRM_ERROR
	b	.L1
.L14:
	bl	__stack_chk_fail
.L16:
	.align	2
.L15:
	.word	.LC2
	.word	.LC1
	.word	REG_HDMI_8996_PHY_PD_CTL
	.word	REG_HDMI_PHY_QSERDES_COM_BG_CTRL
	.word	REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL
	.word	REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL
	.word	REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL
	.word	HDMI_NUM_TX_CHANNEL
	.word	REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE
	.word	REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND
	.word	REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN
	.word	REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE
	.word	REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE
	.word	REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN
	.word	REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL
	.word	REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL
	.word	REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1
	.word	REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL
	.word	REG_HDMI_PHY_QSERDES_COM_BG_TRIM
	.word	REG_HDMI_PHY_QSERDES_COM_PLL_IVCO
	.word	REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL
	.word	REG_HDMI_PHY_QSERDES_COM_CLK_SELECT
	.word	REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL
	.word	REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN
	.word	REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0
	.word	REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0
	.word	REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0
	.word	REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0
	.word	REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0
	.word	REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0
	.word	REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0
	.word	REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0
	.word	REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0
	.word	REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0
	.word	REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0
	.word	REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0
	.word	REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP
	.word	REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN
	.word	REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV
	.word	REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG
	.word	REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM
	.word	REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL
	.word	REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL
	.word	REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1
	.word	REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2
	.word	REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET
	.word	REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET
	.word	REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN
	.word	REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN
	.word	REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES
	.word	REG_HDMI_8996_PHY_MODE
	.word	.LC0
	.size	hdmi_8996_pll_set_clk_rate, .-hdmi_8996_pll_set_clk_rate
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES,4,4
	.comm	REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_PLL_IVCO,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_CLK_SELECT,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_BG_TRIM,4,4
	.comm	REG_HDMI_PHY_QSERDES_COM_BG_CTRL,4,4
	.comm	REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL,4,4
	.comm	REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL,4,4
	.comm	REG_HDMI_8996_PHY_PD_CTL,4,4
	.comm	REG_HDMI_8996_PHY_MODE,4,4
	.comm	HDMI_NUM_TX_CHANNEL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
