	.file	"extr_clk-pll-s10.c_clk_pll_get_parent.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	clk_pll_get_parent, @function
clk_pll_get_parent:
.LFB0:
	.cfi_startproc
	endbr64
	sub	rsp, 8
	.cfi_def_cfa_offset 16
	call	to_socfpga_clk@PLT
	mov	edi, DWORD PTR [rax]
	call	readl@PLT
	mov	ecx, DWORD PTR CLK_MGR_PLL_CLK_SRC_SHIFT[rip]
	sar	eax, cl
	and	eax, DWORD PTR CLK_MGR_PLL_CLK_SRC_MASK[rip]
	add	rsp, 8
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE0:
	.size	clk_pll_get_parent, .-clk_pll_get_parent
	.comm	CLK_MGR_PLL_CLK_SRC_SHIFT,4,4
	.comm	CLK_MGR_PLL_CLK_SRC_MASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_clk-pll-s10.c_clk_pll_get_parent.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	clk_pll_get_parent, %function
clk_pll_get_parent:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, lr}
	bl	to_socfpga_clk
	ldr	r0, [r0]
	bl	readl
	ldr	r2, .L4
	ldr	r3, .L4+4
	ldr	r2, [r2]
	ldr	r3, [r3]
	and	r0, r3, r0, asr r2
	pop	{r4, pc}
.L5:
	.align	2
.L4:
	.word	CLK_MGR_PLL_CLK_SRC_SHIFT
	.word	CLK_MGR_PLL_CLK_SRC_MASK
	.size	clk_pll_get_parent, .-clk_pll_get_parent
	.comm	CLK_MGR_PLL_CLK_SRC_SHIFT,4,4
	.comm	CLK_MGR_PLL_CLK_SRC_MASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
