	.file	"extr_niu.c_link_status_mii.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	link_status_mii, @function
link_status_mii:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rsi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	rbx, rdi
	sub	rsp, 24
	.cfi_def_cfa_offset 80
	mov	esi, DWORD PTR [rdi]
	mov	edx, DWORD PTR MII_BMCR[rip]
	call	mii_read@PLT
	mov	edi, eax
	mov	r12d, eax
	shr	edi, 31
	call	unlikely@PLT
	test	rax, rax
	je	.L78
.L1:
	add	rsp, 24
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	eax, r12d
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L78:
	.cfi_restore_state
	mov	edx, DWORD PTR MII_BMSR[rip]
	mov	esi, DWORD PTR [rbx]
	mov	rdi, rbx
	call	mii_read@PLT
	mov	edi, eax
	mov	r13d, eax
	shr	edi, 31
	call	unlikely@PLT
	test	rax, rax
	jne	.L31
	mov	edx, DWORD PTR MII_ADVERTISE[rip]
	mov	esi, DWORD PTR [rbx]
	mov	rdi, rbx
	call	mii_read@PLT
	mov	edi, eax
	mov	r14d, eax
	shr	edi, 31
	call	unlikely@PLT
	test	rax, rax
	je	.L79
	mov	r12d, r14d
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L31:
	mov	r12d, r13d
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L79:
	mov	edx, DWORD PTR MII_LPA[rip]
	mov	esi, DWORD PTR [rbx]
	mov	rdi, rbx
	call	mii_read@PLT
	mov	edi, eax
	mov	r15d, eax
	shr	edi, 31
	call	unlikely@PLT
	test	rax, rax
	jne	.L33
	mov	edi, DWORD PTR BMSR_ESTATEN[rip]
	and	edi, r13d
	call	likely@PLT
	test	rax, rax
	jne	.L80
	xor	r8d, r8d
	xor	r9d, r9d
	xor	ecx, ecx
.L3:
	mov	eax, r13d
	and	eax, DWORD PTR BMSR_ANEGCAPABLE[rip]
	cmovne	eax, DWORD PTR SUPPORTED_Autoneg[rip]
	test	DWORD PTR BMSR_10HALF[rip], r13d
	je	.L5
	or	eax, DWORD PTR SUPPORTED_10baseT_Half[rip]
.L5:
	test	DWORD PTR BMSR_10FULL[rip], r13d
	je	.L6
	or	eax, DWORD PTR SUPPORTED_10baseT_Full[rip]
.L6:
	test	DWORD PTR BMSR_100HALF[rip], r13d
	je	.L7
	or	eax, DWORD PTR SUPPORTED_100baseT_Half[rip]
.L7:
	test	DWORD PTR BMSR_100FULL[rip], r13d
	je	.L8
	or	eax, DWORD PTR SUPPORTED_100baseT_Full[rip]
.L8:
	test	DWORD PTR ESTATUS_1000_THALF[rip], r8d
	je	.L9
	or	eax, DWORD PTR SUPPORTED_1000baseT_Half[rip]
.L9:
	test	DWORD PTR ESTATUS_1000_TFULL[rip], r8d
	je	.L10
	or	eax, DWORD PTR SUPPORTED_1000baseT_Full[rip]
.L10:
	mov	edx, r14d
	mov	DWORD PTR 4[rbx], eax
	and	edx, DWORD PTR ADVERTISE_10HALF[rip]
	cmovne	edx, DWORD PTR ADVERTISED_10baseT_Half[rip]
	test	DWORD PTR ADVERTISE_10FULL[rip], r14d
	je	.L12
	or	edx, DWORD PTR ADVERTISED_10baseT_Full[rip]
.L12:
	test	DWORD PTR ADVERTISE_100HALF[rip], r14d
	je	.L13
	or	edx, DWORD PTR ADVERTISED_100baseT_Half[rip]
.L13:
	test	DWORD PTR ADVERTISE_100FULL[rip], r14d
	je	.L14
	or	edx, DWORD PTR ADVERTISED_100baseT_Full[rip]
.L14:
	test	DWORD PTR ADVERTISE_1000HALF[rip], ecx
	je	.L15
	or	edx, DWORD PTR ADVERTISED_1000baseT_Half[rip]
.L15:
	test	DWORD PTR ADVERTISE_1000FULL[rip], ecx
	je	.L16
	or	edx, DWORD PTR ADVERTISED_1000baseT_Full[rip]
.L16:
	test	DWORD PTR BMCR_ANENABLE[rip], r12d
	je	.L17
	lea	esi, 0[0+rcx*4]
	mov	eax, DWORD PTR LPA_1000HALF[rip]
	and	r14d, r15d
	mov	DWORD PTR 8[rbx], 1
	mov	ecx, esi
	mov	esi, DWORD PTR LPA_1000FULL[rip]
	mov	edi, DWORD PTR SPEED_1000[rip]
	and	ecx, r9d
	or	edx, DWORD PTR ADVERTISED_Autoneg[rip]
	or	eax, esi
	test	eax, ecx
	jne	.L19
	mov	edi, DWORD PTR SPEED_100[rip]
	test	DWORD PTR LPA_100[rip], r14d
	jne	.L19
	mov	eax, DWORD PTR LPA_10HALF[rip]
	or	eax, DWORD PTR LPA_10FULL[rip]
	mov	edi, DWORD PTR SPEED_10[rip]
	test	eax, r14d
	jne	.L19
	and	r14d, DWORD PTR LPA_DUPLEX[rip]
	and	esi, ecx
	mov	edi, DWORD PTR SPEED_INVALID[rip]
	or	r14d, esi
	jne	.L22
.L23:
	mov	eax, DWORD PTR DUPLEX_INVALID[rip]
	.p2align 4,,10
	.p2align 3
.L25:
	mov	DWORD PTR 20[rbx], eax
	xor	eax, eax
	test	DWORD PTR BMSR_LSTATUS[rip], r13d
	setne	al
	mov	DWORD PTR 12[rbx], edx
	xor	r12d, r12d
	mov	DWORD PTR 16[rbx], edi
	mov	DWORD PTR 0[rbp], eax
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L33:
	mov	r12d, r15d
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L80:
	mov	edx, DWORD PTR MII_ESTATUS[rip]
	mov	esi, DWORD PTR [rbx]
	mov	rdi, rbx
	call	mii_read@PLT
	mov	edi, eax
	mov	DWORD PTR 4[rsp], eax
	shr	edi, 31
	call	unlikely@PLT
	mov	r8d, DWORD PTR 4[rsp]
	test	rax, rax
	jne	.L35
	mov	edx, DWORD PTR MII_CTRL1000[rip]
	mov	esi, DWORD PTR [rbx]
	mov	rdi, rbx
	mov	DWORD PTR 8[rsp], r8d
	call	mii_read@PLT
	mov	edi, eax
	mov	DWORD PTR 4[rsp], eax
	shr	edi, 31
	call	unlikely@PLT
	mov	ecx, DWORD PTR 4[rsp]
	test	rax, rax
	jne	.L36
	mov	edx, DWORD PTR MII_STAT1000[rip]
	mov	esi, DWORD PTR [rbx]
	mov	rdi, rbx
	mov	DWORD PTR 12[rsp], ecx
	call	mii_read@PLT
	mov	edi, eax
	mov	DWORD PTR 4[rsp], eax
	shr	edi, 31
	call	unlikely@PLT
	mov	r9d, DWORD PTR 4[rsp]
	mov	ecx, DWORD PTR 12[rsp]
	test	rax, rax
	mov	r8d, DWORD PTR 8[rsp]
	je	.L3
	mov	r12d, r9d
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L17:
	mov	eax, DWORD PTR BMCR_SPEED100[rip]
	mov	DWORD PTR 8[rbx], 0
	and	eax, r12d
	test	DWORD PTR BMCR_SPEED1000[rip], r12d
	je	.L26
	mov	edi, DWORD PTR SPEED_1000[rip]
	test	eax, eax
	je	.L28
.L27:
	mov	edi, DWORD PTR SPEED_100[rip]
.L28:
	mov	eax, DWORD PTR DUPLEX_FULL[rip]
	test	DWORD PTR BMCR_FULLDPLX[rip], r12d
	cmove	eax, DWORD PTR DUPLEX_HALF[rip]
	jmp	.L25
	.p2align 4,,10
	.p2align 3
.L19:
	and	r14d, DWORD PTR LPA_DUPLEX[rip]
	and	esi, ecx
	or	r14d, esi
	jne	.L22
	cmp	DWORD PTR SPEED_INVALID[rip], edi
	je	.L23
	mov	eax, DWORD PTR DUPLEX_HALF[rip]
	jmp	.L25
	.p2align 4,,10
	.p2align 3
.L22:
	mov	eax, DWORD PTR DUPLEX_FULL[rip]
	jmp	.L25
	.p2align 4,,10
	.p2align 3
.L26:
	mov	edi, DWORD PTR SPEED_10[rip]
	test	eax, eax
	je	.L28
	jmp	.L27
.L35:
	mov	r12d, r8d
	jmp	.L1
.L36:
	mov	r12d, ecx
	jmp	.L1
	.cfi_endproc
.LFE0:
	.size	link_status_mii, .-link_status_mii
	.comm	SUPPORTED_Autoneg,4,4
	.comm	SUPPORTED_10baseT_Half,4,4
	.comm	SUPPORTED_10baseT_Full,4,4
	.comm	SUPPORTED_100baseT_Half,4,4
	.comm	SUPPORTED_100baseT_Full,4,4
	.comm	SUPPORTED_1000baseT_Half,4,4
	.comm	SUPPORTED_1000baseT_Full,4,4
	.comm	SPEED_INVALID,4,4
	.comm	SPEED_1000,4,4
	.comm	SPEED_100,4,4
	.comm	SPEED_10,4,4
	.comm	MII_STAT1000,4,4
	.comm	MII_LPA,4,4
	.comm	MII_ESTATUS,4,4
	.comm	MII_CTRL1000,4,4
	.comm	MII_BMSR,4,4
	.comm	MII_BMCR,4,4
	.comm	MII_ADVERTISE,4,4
	.comm	LPA_DUPLEX,4,4
	.comm	LPA_10HALF,4,4
	.comm	LPA_10FULL,4,4
	.comm	LPA_1000HALF,4,4
	.comm	LPA_1000FULL,4,4
	.comm	LPA_100,4,4
	.comm	ESTATUS_1000_THALF,4,4
	.comm	ESTATUS_1000_TFULL,4,4
	.comm	DUPLEX_INVALID,4,4
	.comm	DUPLEX_HALF,4,4
	.comm	DUPLEX_FULL,4,4
	.comm	BMSR_LSTATUS,4,4
	.comm	BMSR_ESTATEN,4,4
	.comm	BMSR_ANEGCAPABLE,4,4
	.comm	BMSR_10HALF,4,4
	.comm	BMSR_10FULL,4,4
	.comm	BMSR_100HALF,4,4
	.comm	BMSR_100FULL,4,4
	.comm	BMCR_SPEED1000,4,4
	.comm	BMCR_SPEED100,4,4
	.comm	BMCR_FULLDPLX,4,4
	.comm	BMCR_ANENABLE,4,4
	.comm	ADVERTISE_10HALF,4,4
	.comm	ADVERTISE_10FULL,4,4
	.comm	ADVERTISE_100HALF,4,4
	.comm	ADVERTISE_100FULL,4,4
	.comm	ADVERTISE_1000HALF,4,4
	.comm	ADVERTISE_1000FULL,4,4
	.comm	ADVERTISED_Autoneg,4,4
	.comm	ADVERTISED_10baseT_Half,4,4
	.comm	ADVERTISED_10baseT_Full,4,4
	.comm	ADVERTISED_100baseT_Half,4,4
	.comm	ADVERTISED_100baseT_Full,4,4
	.comm	ADVERTISED_1000baseT_Half,4,4
	.comm	ADVERTISED_1000baseT_Full,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_niu.c_link_status_mii.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	link_status_mii, %function
link_status_mii:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r2, .L82
	sub	sp, sp, #12
	ldr	r2, [r2]
	mov	r7, r1
	ldr	r1, [r0]
	mov	r4, r0
	bl	mii_read
	mov	r5, r0
	lsr	r0, r0, #31
	bl	unlikely
	cmp	r0, #0
	beq	.L80
.L1:
	mov	r0, r5
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L80:
	ldr	r3, .L82+4
	ldr	r1, [r4]
	ldr	r2, [r3]
	mov	r0, r4
	bl	mii_read
	mov	r6, r0
	lsr	r0, r0, #31
	bl	unlikely
	cmp	r0, #0
	movne	r5, r6
	bne	.L1
	ldr	r3, .L82+8
	ldr	r1, [r4]
	ldr	r2, [r3]
	mov	r0, r4
	bl	mii_read
	mov	r8, r0
	lsr	r0, r0, #31
	bl	unlikely
	cmp	r0, #0
	movne	r5, r8
	bne	.L1
	ldr	r3, .L82+12
	ldr	r1, [r4]
	ldr	r2, [r3]
	mov	r0, r4
	bl	mii_read
	mov	r9, r0
	lsr	r0, r0, #31
	bl	unlikely
	cmp	r0, #0
	movne	r5, r9
	bne	.L1
	ldr	r3, .L82+16
	ldr	r0, [r3]
	and	r0, r0, r6
	bl	likely
	subs	r10, r0, #0
	moveq	fp, r10
	moveq	r2, r10
	bne	.L81
.L3:
	ldr	r3, .L82+20
	ldr	r1, .L82+24
	ldr	r3, [r3]
	ldr	r1, [r1]
	ands	r3, r6, r3
	ldrne	r3, .L82+28
	ldrne	r3, [r3]
	tst	r6, r1
	ldrne	r1, .L82+32
	ldrne	r1, [r1]
	orrne	r3, r3, r1
	ldr	r1, .L82+36
	ldr	r1, [r1]
	tst	r6, r1
	ldrne	r1, .L82+40
	ldrne	r1, [r1]
	orrne	r3, r3, r1
	ldr	r1, .L82+44
	ldr	r1, [r1]
	tst	r6, r1
	ldrne	r1, .L82+48
	ldrne	r1, [r1]
	orrne	r3, r3, r1
	ldr	r1, .L82+52
	ldr	r1, [r1]
	tst	r6, r1
	ldrne	r1, .L82+56
	ldrne	r1, [r1]
	orrne	r3, r3, r1
	ldr	r1, .L82+60
	ldr	r1, [r1]
	tst	fp, r1
	ldrne	r1, .L82+64
	ldrne	r1, [r1]
	orrne	r3, r3, r1
	ldr	r1, .L82+68
	ldr	r1, [r1]
	tst	fp, r1
	ldrne	r1, .L82+72
	ldrne	r1, [r1]
	orrne	r3, r3, r1
	ldr	r1, .L82+76
	str	r3, [r4, #4]
	ldr	r3, [r1]
	ldr	r1, .L82+80
	ands	r3, r8, r3
	ldrne	r3, .L82+84
	ldr	r1, [r1]
	ldrne	r3, [r3]
	tst	r8, r1
	ldrne	r1, .L82+88
	ldrne	r1, [r1]
	orrne	r3, r3, r1
	ldr	r1, .L82+92
	ldr	r1, [r1]
	tst	r8, r1
	ldrne	r1, .L82+96
	ldrne	r1, [r1]
	orrne	r3, r3, r1
	ldr	r1, .L82+100
	ldr	r1, [r1]
	tst	r8, r1
	ldrne	r1, .L82+104
	ldrne	r1, [r1]
	orrne	r3, r3, r1
	ldr	r1, .L82+108
	ldr	r1, [r1]
	tst	r10, r1
	ldrne	r1, .L82+112
	ldrne	r1, [r1]
	orrne	r3, r3, r1
	ldr	r1, .L82+116
	ldr	r1, [r1]
	tst	r10, r1
	ldrne	r1, .L82+120
	ldrne	r1, [r1]
	orrne	r3, r3, r1
	ldr	r1, .L82+124
	ldr	r1, [r1]
	ands	r1, r5, r1
	beq	.L17
	mov	r0, #1
	ldr	r1, .L82+128
	ldr	ip, .L82+132
	and	r10, r2, r10, lsl #2
	ldr	r1, [r1]
	ldr	ip, [ip]
	ldr	r2, .L82+136
	orr	ip, r1, ip
	ldr	r2, [r2]
	tst	ip, r10
	and	r8, r8, r9
	str	r0, [r4, #8]
	orr	r3, r3, r2
	beq	.L18
	ldr	r2, .L82+140
	ldr	ip, [r2]
.L19:
	ldr	r2, .L82+144
	and	r1, r1, r10
	ldr	r9, [r2]
	and	r8, r8, r9
	orrs	r2, r8, r1
	bne	.L78
	ldr	r2, .L82+148
	ldr	r2, [r2]
	cmp	r2, ip
	beq	.L23
.L30:
	ldr	r2, .L82+152
	ldr	r1, [r2]
.L25:
	ldr	r2, .L82+156
	str	r3, [r4, #12]
	ldr	r3, [r2]
	str	ip, [r4, #16]
	tst	r6, r3
	movne	r3, #1
	moveq	r3, #0
	str	r1, [r4, #20]
	mov	r5, #0
	str	r3, [r7]
	b	.L1
.L81:
	ldr	r3, .L82+160
	ldr	r1, [r4]
	ldr	r2, [r3]
	mov	r0, r4
	bl	mii_read
	mov	fp, r0
	lsr	r0, r0, #31
	bl	unlikely
	cmp	r0, #0
	movne	r5, fp
	bne	.L1
	ldr	r3, .L82+164
	ldr	r1, [r4]
	ldr	r2, [r3]
	mov	r0, r4
	bl	mii_read
	mov	r10, r0
	lsr	r0, r0, #31
	bl	unlikely
	cmp	r0, #0
	movne	r5, r10
	bne	.L1
	ldr	r3, .L82+168
	ldr	r1, [r4]
	ldr	r2, [r3]
	mov	r0, r4
	bl	mii_read
	mov	r2, r0
	lsr	r0, r0, #31
	str	r2, [sp, #4]
	bl	unlikely
	cmp	r0, #0
	ldr	r2, [sp, #4]
	beq	.L3
	mov	r5, r2
	b	.L1
.L17:
	ldr	r0, .L82+172
	ldr	r2, .L82+176
	ldr	r0, [r0]
	ldr	r2, [r2]
	tst	r5, r0
	str	r1, [r4, #8]
	and	r2, r2, r5
	beq	.L26
	cmp	r2, #0
	bne	.L27
	ldr	r2, .L82+140
	ldr	ip, [r2]
.L28:
	ldr	r2, .L82+180
	ldr	r2, [r2]
	tst	r5, r2
	beq	.L30
.L78:
	ldr	r2, .L82+184
	ldr	r1, [r2]
	b	.L25
.L18:
	ldr	r2, .L82+188
	ldr	r2, [r2]
	tst	r8, r2
	beq	.L20
	ldr	r2, .L82+192
	ldr	ip, [r2]
	b	.L19
.L26:
	cmp	r2, #0
	ldreq	r2, .L82+196
	ldreq	ip, [r2]
	beq	.L28
.L27:
	ldr	r2, .L82+192
	ldr	ip, [r2]
	b	.L28
.L20:
	ldr	r2, .L82+200
	ldr	r0, .L82+204
	ldr	r2, [r2]
	ldr	r0, [r0]
	orr	r2, r2, r0
	tst	r2, r8
	ldrne	r2, .L82+196
	ldrne	ip, [r2]
	bne	.L19
.L21:
	ldr	r2, .L82+144
	ldr	ip, .L82+148
	ldr	r0, [r2]
	and	r1, r1, r10
	and	r8, r8, r0
	orrs	r2, r8, r1
	ldr	ip, [ip]
	bne	.L78
.L23:
	ldr	r2, .L82+208
	ldr	r1, [r2]
	b	.L25
.L83:
	.align	2
.L82:
	.word	MII_BMCR
	.word	MII_BMSR
	.word	MII_ADVERTISE
	.word	MII_LPA
	.word	BMSR_ESTATEN
	.word	BMSR_ANEGCAPABLE
	.word	BMSR_10HALF
	.word	SUPPORTED_Autoneg
	.word	SUPPORTED_10baseT_Half
	.word	BMSR_10FULL
	.word	SUPPORTED_10baseT_Full
	.word	BMSR_100HALF
	.word	SUPPORTED_100baseT_Half
	.word	BMSR_100FULL
	.word	SUPPORTED_100baseT_Full
	.word	ESTATUS_1000_THALF
	.word	SUPPORTED_1000baseT_Half
	.word	ESTATUS_1000_TFULL
	.word	SUPPORTED_1000baseT_Full
	.word	ADVERTISE_10HALF
	.word	ADVERTISE_10FULL
	.word	ADVERTISED_10baseT_Half
	.word	ADVERTISED_10baseT_Full
	.word	ADVERTISE_100HALF
	.word	ADVERTISED_100baseT_Half
	.word	ADVERTISE_100FULL
	.word	ADVERTISED_100baseT_Full
	.word	ADVERTISE_1000HALF
	.word	ADVERTISED_1000baseT_Half
	.word	ADVERTISE_1000FULL
	.word	ADVERTISED_1000baseT_Full
	.word	BMCR_ANENABLE
	.word	LPA_1000FULL
	.word	LPA_1000HALF
	.word	ADVERTISED_Autoneg
	.word	SPEED_1000
	.word	LPA_DUPLEX
	.word	SPEED_INVALID
	.word	DUPLEX_HALF
	.word	BMSR_LSTATUS
	.word	MII_ESTATUS
	.word	MII_CTRL1000
	.word	MII_STAT1000
	.word	BMCR_SPEED1000
	.word	BMCR_SPEED100
	.word	BMCR_FULLDPLX
	.word	DUPLEX_FULL
	.word	LPA_100
	.word	SPEED_100
	.word	SPEED_10
	.word	LPA_10HALF
	.word	LPA_10FULL
	.word	DUPLEX_INVALID
	.size	link_status_mii, .-link_status_mii
	.comm	SUPPORTED_Autoneg,4,4
	.comm	SUPPORTED_10baseT_Half,4,4
	.comm	SUPPORTED_10baseT_Full,4,4
	.comm	SUPPORTED_100baseT_Half,4,4
	.comm	SUPPORTED_100baseT_Full,4,4
	.comm	SUPPORTED_1000baseT_Half,4,4
	.comm	SUPPORTED_1000baseT_Full,4,4
	.comm	SPEED_INVALID,4,4
	.comm	SPEED_1000,4,4
	.comm	SPEED_100,4,4
	.comm	SPEED_10,4,4
	.comm	MII_STAT1000,4,4
	.comm	MII_LPA,4,4
	.comm	MII_ESTATUS,4,4
	.comm	MII_CTRL1000,4,4
	.comm	MII_BMSR,4,4
	.comm	MII_BMCR,4,4
	.comm	MII_ADVERTISE,4,4
	.comm	LPA_DUPLEX,4,4
	.comm	LPA_10HALF,4,4
	.comm	LPA_10FULL,4,4
	.comm	LPA_1000HALF,4,4
	.comm	LPA_1000FULL,4,4
	.comm	LPA_100,4,4
	.comm	ESTATUS_1000_THALF,4,4
	.comm	ESTATUS_1000_TFULL,4,4
	.comm	DUPLEX_INVALID,4,4
	.comm	DUPLEX_HALF,4,4
	.comm	DUPLEX_FULL,4,4
	.comm	BMSR_LSTATUS,4,4
	.comm	BMSR_ESTATEN,4,4
	.comm	BMSR_ANEGCAPABLE,4,4
	.comm	BMSR_10HALF,4,4
	.comm	BMSR_10FULL,4,4
	.comm	BMSR_100HALF,4,4
	.comm	BMSR_100FULL,4,4
	.comm	BMCR_SPEED1000,4,4
	.comm	BMCR_SPEED100,4,4
	.comm	BMCR_FULLDPLX,4,4
	.comm	BMCR_ANENABLE,4,4
	.comm	ADVERTISE_10HALF,4,4
	.comm	ADVERTISE_10FULL,4,4
	.comm	ADVERTISE_100HALF,4,4
	.comm	ADVERTISE_100FULL,4,4
	.comm	ADVERTISE_1000HALF,4,4
	.comm	ADVERTISE_1000FULL,4,4
	.comm	ADVERTISED_Autoneg,4,4
	.comm	ADVERTISED_10baseT_Half,4,4
	.comm	ADVERTISED_10baseT_Full,4,4
	.comm	ADVERTISED_100baseT_Half,4,4
	.comm	ADVERTISED_100baseT_Full,4,4
	.comm	ADVERTISED_1000baseT_Half,4,4
	.comm	ADVERTISED_1000baseT_Full,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
