	.file	"extr_cik.c_cik_gpu_init.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	cik_gpu_init, @function
cik_gpu_init:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	push	rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	push	rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	mov	rbx, rdi
	mov	edi, DWORD PTR GB_ADDR_CONFIG[rip]
	call	RREG32@PLT
	mov	eax, DWORD PTR [rbx]
	cmp	eax, 131
	je	.L2
	cmp	eax, 132
	je	.L3
	cmp	eax, 129
	je	.L38
	movabs	rax, 8589934593
	movabs	rcx, 4294967298
	mov	QWORD PTR 8[rbx], rax
	mov	QWORD PTR 16[rbx], rcx
.L36:
	mov	QWORD PTR 24[rbx], rax
	movabs	rax, 68719476992
	mov	QWORD PTR 32[rbx], rax
	movabs	rax, 137438953480
.L35:
	mov	QWORD PTR 40[rbx], rax
	mov	r12d, DWORD PTR BONAIRE_GB_ADDR_CONFIG_GOLDEN[rip]
	movabs	rax, 206158430464
	mov	QWORD PTR 48[rbx], rax
	mov	DWORD PTR 56[rbx], 304
.L6:
	mov	ebp, 11284
	.p2align 4,,10
	.p2align 3
.L7:
	mov	edi, ebp
	xor	esi, esi
	call	WREG32@PLT
	lea	edi, 4[rbp]
	xor	esi, esi
	call	WREG32@PLT
	lea	edi, 8[rbp]
	xor	esi, esi
	call	WREG32@PLT
	lea	edi, 12[rbp]
	xor	esi, esi
	call	WREG32@PLT
	lea	edi, 16[rbp]
	xor	esi, esi
	add	ebp, 24
	call	WREG32@PLT
	cmp	ebp, 12052
	jne	.L7
	mov	edi, 255
	call	GRBM_READ_TIMEOUT@PLT
	mov	edi, DWORD PTR GRBM_CNTL[rip]
	mov	esi, eax
	call	WREG32@PLT
	mov	edi, DWORD PTR SRBM_INT_CNTL[rip]
	mov	esi, 1
	call	WREG32@PLT
	mov	edi, DWORD PTR SRBM_INT_ACK[rip]
	mov	esi, 1
	call	WREG32@PLT
	mov	edi, DWORD PTR BIF_FB_EN[rip]
	mov	esi, DWORD PTR FB_READ_EN[rip]
	or	esi, DWORD PTR FB_WRITE_EN[rip]
	call	WREG32@PLT
	mov	edi, DWORD PTR MC_SHARED_CHMAP[rip]
	call	RREG32@PLT
	mov	edi, DWORD PTR MC_ARB_RAMCFG[rip]
	call	RREG32@PLT
	mov	ecx, DWORD PTR NOOFCOLS_SHIFT[rip]
	mov	DWORD PTR 64[rbx], 256
	mov	ebp, eax
	mov	eax, DWORD PTR 12[rbx]
	mov	DWORD PTR 60[rbx], eax
	mov	eax, DWORD PTR NOOFCOLS_MASK[rip]
	and	eax, ebp
	sar	eax, cl
	lea	ecx, 8[rax]
	mov	eax, 4
	sal	eax, cl
	cmp	eax, 5119
	jg	.L8
	test	eax, eax
	lea	edx, 1023[rax]
	movabs	rcx, 4294967328
	mov	DWORD PTR 80[rbx], 64
	cmovs	eax, edx
	mov	edx, DWORD PTR ROW_SIZE_MASK[rip]
	mov	QWORD PTR 72[rbx], rcx
	sar	eax, 10
	not	edx
	mov	DWORD PTR 68[rbx], eax
	and	r12d, edx
	cmp	eax, 2
	jne	.L39
	mov	edi, 1
	call	ROW_SIZE@PLT
	or	r12d, eax
.L12:
	mov	eax, DWORD PTR 60[rbx]
	mov	edx, 1
	cmp	eax, 2
	je	.L13
	mov	edx, 2
	cmp	eax, 4
	je	.L13
	xor	edx, edx
	cmp	eax, 1
	setne	dl
	lea	edx, [rdx+rdx*2]
.L13:
	mov	eax, DWORD PTR PIPE_INTERLEAVE_SIZE_MASK[rip]
	mov	ecx, DWORD PTR PIPE_INTERLEAVE_SIZE_SHIFT[rip]
	mov	esi, DWORD PTR ROW_SIZE_MASK[rip]
	and	ebp, DWORD PTR NOOFBANK_MASK[rip]
	and	eax, r12d
	mov	edi, DWORD PTR GB_ADDR_CONFIG[rip]
	sar	eax, cl
	mov	ecx, DWORD PTR ROW_SIZE_SHIFT[rip]
	and	esi, r12d
	sal	eax, 8
	sar	esi, cl
	mov	ecx, DWORD PTR NOOFBANK_SHIFT[rip]
	sal	esi, 12
	sar	ebp, cl
	or	eax, esi
	mov	esi, r12d
	sal	ebp, 4
	or	eax, ebp
	mov	ebp, r12d
	or	eax, edx
	and	ebp, 112
	mov	DWORD PTR 84[rbx], eax
	call	WREG32@PLT
	mov	edi, DWORD PTR HDP_ADDR_CONFIG[rip]
	mov	esi, r12d
	call	WREG32@PLT
	mov	edi, DWORD PTR DMIF_ADDR_CALC[rip]
	mov	esi, r12d
	call	WREG32@PLT
	mov	edi, DWORD PTR SDMA0_REGISTER_OFFSET[rip]
	mov	esi, ebp
	add	edi, DWORD PTR SDMA0_TILING_CONFIG[rip]
	call	WREG32@PLT
	mov	edi, DWORD PTR SDMA1_REGISTER_OFFSET[rip]
	mov	esi, ebp
	add	edi, DWORD PTR SDMA0_TILING_CONFIG[rip]
	call	WREG32@PLT
	mov	edi, DWORD PTR UVD_UDEC_ADDR_CONFIG[rip]
	mov	esi, r12d
	call	WREG32@PLT
	mov	edi, DWORD PTR UVD_UDEC_DB_ADDR_CONFIG[rip]
	mov	esi, r12d
	call	WREG32@PLT
	mov	edi, DWORD PTR UVD_UDEC_DBW_ADDR_CONFIG[rip]
	mov	esi, r12d
	xor	r12d, r12d
	call	WREG32@PLT
	mov	rdi, rbx
	call	cik_tiling_mode_table_init@PLT
	mov	edx, DWORD PTR 20[rbx]
	mov	ecx, DWORD PTR 24[rbx]
	mov	rdi, rbx
	mov	esi, DWORD PTR 8[rbx]
	call	cik_setup_rb@PLT
	mov	edx, DWORD PTR 8[rbx]
	mov	QWORD PTR 88[rbx], 0
	test	edx, edx
	jle	.L15
	.p2align 4,,10
	.p2align 3
.L14:
	mov	eax, DWORD PTR 20[rbx]
	xor	ebp, ebp
	test	eax, eax
	jle	.L17
	.p2align 4,,10
	.p2align 3
.L16:
	mov	edx, ebp
	mov	esi, r12d
	mov	rdi, rbx
	add	ebp, 1
	call	cik_get_cu_active_bitmap@PLT
	mov	edi, eax
	call	hweight32@PLT
	add	QWORD PTR 88[rbx], rax
	cmp	DWORD PTR 20[rbx], ebp
	jg	.L16
.L17:
	add	r12d, 1
	cmp	DWORD PTR 8[rbx], r12d
	jg	.L14
.L15:
	mov	edi, 48
	call	MEQ1_START@PLT
	mov	edi, 96
	mov	ebp, eax
	call	MEQ2_START@PLT
	mov	edi, DWORD PTR CP_MEQ_THRESHOLDS[rip]
	mov	esi, ebp
	or	esi, eax
	call	WREG32@PLT
	mov	edi, DWORD PTR SX_DEBUG_1[rip]
	mov	esi, 32
	call	WREG32@PLT
	mov	edi, DWORD PTR TA_CNTL_AUX[rip]
	mov	esi, 65536
	call	WREG32@PLT
	mov	edi, DWORD PTR SPI_CONFIG_CNTL[rip]
	call	RREG32@PLT
	mov	edi, DWORD PTR SPI_CONFIG_CNTL[rip]
	or	eax, 50331648
	mov	esi, eax
	call	WREG32@PLT
	mov	edi, DWORD PTR SQ_CONFIG[rip]
	mov	esi, 1
	call	WREG32@PLT
	mov	edi, DWORD PTR DB_DEBUG[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	edi, DWORD PTR DB_DEBUG2[rip]
	call	RREG32@PLT
	mov	edi, DWORD PTR DB_DEBUG2[rip]
	and	eax, 267386880
	mov	esi, eax
	or	esi, 1024
	call	WREG32@PLT
	mov	edi, DWORD PTR DB_DEBUG3[rip]
	call	RREG32@PLT
	mov	edi, DWORD PTR DB_DEBUG3[rip]
	and	eax, -131613
	mov	esi, eax
	or	esi, 131584
	call	WREG32@PLT
	mov	edi, DWORD PTR CB_HW_CONTROL[rip]
	call	RREG32@PLT
	mov	edi, DWORD PTR CB_HW_CONTROL[rip]
	or	eax, 98824
	mov	esi, eax
	call	WREG32@PLT
	mov	edi, 4
	call	VTX_DONE_DELAY@PLT
	mov	edi, DWORD PTR SPI_CONFIG_CNTL_1[rip]
	mov	esi, eax
	call	WREG32@PLT
	mov	edi, DWORD PTR 44[rbx]
	call	SC_FRONTEND_PRIM_FIFO_SIZE@PLT
	mov	edi, DWORD PTR 48[rbx]
	mov	ebp, eax
	call	SC_BACKEND_PRIM_FIFO_SIZE@PLT
	mov	edi, DWORD PTR 52[rbx]
	or	ebp, eax
	call	SC_HIZ_TILE_FIFO_SIZE@PLT
	mov	edi, DWORD PTR 56[rbx]
	or	ebp, eax
	call	SC_EARLYZ_TILE_FIFO_SIZE@PLT
	mov	edi, DWORD PTR PA_SC_FIFO_SIZE[rip]
	mov	esi, ebp
	or	esi, eax
	call	WREG32@PLT
	mov	edi, DWORD PTR VGT_NUM_INSTANCES[rip]
	mov	esi, 1
	call	WREG32@PLT
	mov	edi, DWORD PTR CP_PERFMON_CNTL[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	edi, DWORD PTR SQ_CONFIG[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	edi, 4095
	call	FORCE_EOV_MAX_CLK_CNT@PLT
	mov	edi, 255
	mov	ebx, eax
	call	FORCE_EOV_MAX_REZ_CNT@PLT
	mov	edi, DWORD PTR PA_SC_FORCE_EOV_MAX_CNTS[rip]
	or	ebx, eax
	mov	esi, ebx
	call	WREG32@PLT
	mov	edi, DWORD PTR VC_AND_TC[rip]
	call	CACHE_INVALIDATION@PLT
	mov	edi, DWORD PTR ES_AND_GS_AUTO[rip]
	mov	ebx, eax
	call	AUTO_INVLD_EN@PLT
	mov	edi, DWORD PTR VGT_CACHE_INVALIDATION[rip]
	or	ebx, eax
	mov	esi, ebx
	call	WREG32@PLT
	mov	edi, DWORD PTR VGT_GS_VERTEX_REUSE[rip]
	mov	esi, 16
	call	WREG32@PLT
	mov	edi, DWORD PTR PA_SC_LINE_STIPPLE_STATE[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	edi, DWORD PTR HDP_MISC_CNTL[rip]
	call	RREG32@PLT
	mov	edi, DWORD PTR HDP_MISC_CNTL[rip]
	or	eax, DWORD PTR HDP_FLUSH_INVALIDATE_CACHE[rip]
	mov	esi, eax
	call	WREG32@PLT
	mov	edi, DWORD PTR HDP_HOST_PATH_CNTL[rip]
	call	RREG32@PLT
	mov	edi, DWORD PTR HDP_HOST_PATH_CNTL[rip]
	mov	esi, eax
	call	WREG32@PLT
	mov	edi, 3
	call	NUM_CLIP_SEQ@PLT
	mov	edi, DWORD PTR PA_CL_ENHANCE[rip]
	or	eax, DWORD PTR CLIP_VTX_REORDER_ENA[rip]
	mov	esi, eax
	call	WREG32@PLT
	mov	edi, DWORD PTR PA_SC_ENHANCE[rip]
	mov	esi, DWORD PTR ENABLE_PA_SC_OUT_OF_ORDER[rip]
	call	WREG32@PLT
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	mov	edi, 50
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	jmp	udelay@PLT
.L8:
	.cfi_restore_state
	movabs	rax, 137438953476
	mov	QWORD PTR 68[rbx], rax
	movabs	rax, 274877906945
	mov	QWORD PTR 76[rbx], rax
	mov	eax, DWORD PTR ROW_SIZE_MASK[rip]
	not	eax
	and	r12d, eax
.L11:
	mov	edi, 2
	call	ROW_SIZE@PLT
	or	r12d, eax
	jmp	.L12
.L39:
	cmp	eax, 4
	je	.L11
	xor	edi, edi
	call	ROW_SIZE@PLT
	or	r12d, eax
	jmp	.L12
.L38:
	movabs	rax, 17179869185
	mov	QWORD PTR 8[rbx], rax
	movabs	rax, 4294967304
	mov	QWORD PTR 16[rbx], rax
	movabs	rax, 17179869186
	jmp	.L36
.L3:
	movabs	rax, 17179869186
	movabs	rcx, 4294967303
	mov	QWORD PTR 8[rbx], rax
	mov	QWORD PTR 24[rbx], rax
	movabs	rax, 137438953728
	mov	QWORD PTR 32[rbx], rax
	sub	rax, 248
	mov	QWORD PTR 16[rbx], rcx
	jmp	.L35
.L2:
	mov	DWORD PTR 56[rbx], 304
	mov	r12d, DWORD PTR HAWAII_GB_ADDR_CONFIG_GOLDEN[rip]
	movabs	rax, 68719476740
	movabs	rcx, 4294967307
	mov	QWORD PTR 8[rbx], rax
	mov	QWORD PTR 24[rbx], rax
	movabs	rax, 137438953728
	mov	QWORD PTR 32[rbx], rax
	sub	rax, 248
	mov	QWORD PTR 40[rbx], rax
	movabs	rax, 206158430464
	mov	QWORD PTR 16[rbx], rcx
	mov	QWORD PTR 48[rbx], rax
	jmp	.L6
	.cfi_endproc
.LFE0:
	.size	cik_gpu_init, .-cik_gpu_init
	.comm	VGT_NUM_INSTANCES,4,4
	.comm	VGT_GS_VERTEX_REUSE,4,4
	.comm	VGT_CACHE_INVALIDATION,4,4
	.comm	VC_AND_TC,4,4
	.comm	UVD_UDEC_DB_ADDR_CONFIG,4,4
	.comm	UVD_UDEC_DBW_ADDR_CONFIG,4,4
	.comm	UVD_UDEC_ADDR_CONFIG,4,4
	.comm	TA_CNTL_AUX,4,4
	.comm	SX_DEBUG_1,4,4
	.comm	SRBM_INT_CNTL,4,4
	.comm	SRBM_INT_ACK,4,4
	.comm	SQ_CONFIG,4,4
	.comm	SPI_CONFIG_CNTL_1,4,4
	.comm	SPI_CONFIG_CNTL,4,4
	.comm	SDMA1_REGISTER_OFFSET,4,4
	.comm	SDMA0_TILING_CONFIG,4,4
	.comm	SDMA0_REGISTER_OFFSET,4,4
	.comm	ROW_SIZE_SHIFT,4,4
	.comm	ROW_SIZE_MASK,4,4
	.comm	PIPE_INTERLEAVE_SIZE_SHIFT,4,4
	.comm	PIPE_INTERLEAVE_SIZE_MASK,4,4
	.comm	PA_SC_LINE_STIPPLE_STATE,4,4
	.comm	PA_SC_FORCE_EOV_MAX_CNTS,4,4
	.comm	PA_SC_FIFO_SIZE,4,4
	.comm	PA_SC_ENHANCE,4,4
	.comm	PA_CL_ENHANCE,4,4
	.comm	NOOFCOLS_SHIFT,4,4
	.comm	NOOFCOLS_MASK,4,4
	.comm	NOOFBANK_SHIFT,4,4
	.comm	NOOFBANK_MASK,4,4
	.comm	MC_SHARED_CHMAP,4,4
	.comm	MC_ARB_RAMCFG,4,4
	.comm	HDP_MISC_CNTL,4,4
	.comm	HDP_HOST_PATH_CNTL,4,4
	.comm	HDP_FLUSH_INVALIDATE_CACHE,4,4
	.comm	HDP_ADDR_CONFIG,4,4
	.comm	HAWAII_GB_ADDR_CONFIG_GOLDEN,4,4
	.comm	GRBM_CNTL,4,4
	.comm	GB_ADDR_CONFIG,4,4
	.comm	FB_WRITE_EN,4,4
	.comm	FB_READ_EN,4,4
	.comm	ES_AND_GS_AUTO,4,4
	.comm	ENABLE_PA_SC_OUT_OF_ORDER,4,4
	.comm	DMIF_ADDR_CALC,4,4
	.comm	DB_DEBUG3,4,4
	.comm	DB_DEBUG2,4,4
	.comm	DB_DEBUG,4,4
	.comm	CP_PERFMON_CNTL,4,4
	.comm	CP_MEQ_THRESHOLDS,4,4
	.comm	CLIP_VTX_REORDER_ENA,4,4
	.comm	CB_HW_CONTROL,4,4
	.comm	BONAIRE_GB_ADDR_CONFIG_GOLDEN,4,4
	.comm	BIF_FB_EN,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_cik.c_cik_gpu_init.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	cik_gpu_init, %function
cik_gpu_init:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	mov	r4, r0
	ldr	r7, .L35
	ldr	r0, [r7]
	bl	RREG32
	ldr	r3, [r4]
	cmp	r3, #131
	beq	.L2
	cmp	r3, #132
	beq	.L3
	cmp	r3, #129
	beq	.L33
	mov	r3, #2
	mov	r2, #1
	mov	r1, #256
	mov	r6, #16
	mov	r5, #8
	mov	lr, #32
	mov	ip, #48
	mov	r0, #304
	str	r3, [r4, #8]
	str	r3, [r4, #12]
	str	r3, [r4, #24]
	ldr	r3, .L35+4
	str	r2, [r4, #4]
	ldr	r8, [r3]
	str	r2, [r4, #16]
	str	r2, [r4, #20]
	str	r1, [r4, #28]
	str	r1, [r4, #44]
	str	r6, [r4, #32]
	str	r5, [r4, #36]
	str	lr, [r4, #40]
	str	ip, [r4, #48]
	str	r0, [r4, #52]
.L6:
	ldr	r5, .L35+8
	ldr	r6, .L35+12
.L7:
	mov	r1, #0
	mov	r0, r5
	bl	WREG32
	mov	r1, #0
	add	r0, r5, #4
	bl	WREG32
	mov	r1, #0
	add	r0, r5, #8
	bl	WREG32
	mov	r1, #0
	add	r0, r5, #12
	bl	WREG32
	add	r0, r5, #16
	mov	r1, #0
	add	r5, r5, #24
	bl	WREG32
	cmp	r5, r6
	bne	.L7
	ldr	r3, .L35+16
	mov	r0, #255
	ldr	r5, [r3]
	bl	GRBM_READ_TIMEOUT
	mov	r1, r0
	mov	r0, r5
	bl	WREG32
	ldr	r3, .L35+20
	mov	r1, #1
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L35+24
	mov	r1, #1
	ldr	r0, [r3]
	bl	WREG32
	ldr	r2, .L35+28
	ldr	r3, .L35+32
	ldr	r1, [r2]
	ldr	r2, [r3]
	ldr	r3, .L35+36
	orr	r1, r1, r2
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L35+40
	ldr	r0, [r3]
	bl	RREG32
	ldr	r3, .L35+44
	ldr	r0, [r3]
	bl	RREG32
	mov	r5, r0
	mov	r2, #4
	mov	r0, #256
	ldr	r3, .L35+48
	ldr	r1, .L35+52
	ldr	r3, [r3]
	ldr	r1, [r1]
	and	r3, r3, r5
	asr	r3, r3, r1
	add	r3, r3, #8
	ldr	r1, [r4, #8]
	lsl	r3, r2, r3
	cmp	r3, #5120
	str	r0, [r4, #60]
	str	r1, [r4, #56]
	bge	.L8
	add	r2, r3, #1020
	cmp	r3, #0
	add	r2, r2, #3
	movlt	r3, r2
	mov	r1, #32
	mov	r0, #1
	mov	r2, #64
	ldr	r6, .L35+56
	asr	r3, r3, #10
	ldr	ip, [r6]
	cmp	r3, #2
	str	r3, [r4, #64]
	bic	r8, r8, ip
	str	r1, [r4, #68]
	str	r0, [r4, #72]
	str	r2, [r4, #76]
	bne	.L34
.L31:
	bl	ROW_SIZE
	orr	r8, r8, r0
.L12:
	ldr	r3, [r4, #56]
	cmp	r3, #2
	moveq	r0, #1
	beq	.L13
	cmp	r3, #4
	moveq	r0, #2
	beq	.L13
	cmp	r3, #1
	movne	r0, #3
	moveq	r0, #0
.L13:
	ldr	r1, .L35+60
	ldr	r3, [r6]
	ldr	r2, .L35+64
	ldr	ip, [r1]
	ldr	lr, .L35+68
	ldr	r1, [r2]
	and	r3, r3, r8
	ldr	r2, .L35+72
	asr	r3, r3, ip
	ldr	ip, .L35+76
	ldr	lr, [lr]
	ldr	r2, [r2]
	ldr	ip, [ip]
	and	r1, r1, r8
	asr	r1, r1, lr
	and	r2, r2, r5
	lsl	r3, r3, #12
	asr	r2, r2, ip
	orr	r3, r3, r1, lsl #8
	orr	r3, r3, r2, lsl #4
	orr	r3, r3, r0
	mov	r1, r8
	str	r3, [r4, #80]
	ldr	r0, [r7]
	bl	WREG32
	ldr	r3, .L35+80
	mov	r1, r8
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L35+84
	mov	r1, r8
	ldr	r0, [r3]
	bl	WREG32
	ldr	r6, .L35+88
	ldr	r3, .L35+92
	ldr	r0, [r6]
	ldr	r3, [r3]
	and	r5, r8, #112
	mov	r1, r5
	add	r0, r0, r3
	bl	WREG32
	ldr	r0, [r6]
	mov	r6, #0
	ldr	r3, .L35+96
	mov	r1, r5
	ldr	r3, [r3]
	add	r0, r0, r3
	bl	WREG32
	ldr	r3, .L35+100
	mov	r1, r8
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L35+104
	mov	r1, r8
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L35+108
	mov	r1, r8
	ldr	r0, [r3]
	bl	WREG32
	mov	r0, r4
	bl	cik_tiling_mode_table_init
	ldr	r3, [r4, #20]
	ldr	r2, [r4, #16]
	mov	r0, r4
	ldr	r1, [r4, #4]
	bl	cik_setup_rb
	ldr	r3, [r4, #4]
	str	r6, [r4, #84]
	cmp	r3, r6
	ldrgt	r2, [r4, #16]
	ble	.L15
.L14:
	cmp	r2, #0
	movgt	r5, #0
	ble	.L17
.L16:
	mov	r2, r5
	mov	r1, r6
	mov	r0, r4
	bl	cik_get_cu_active_bitmap
	bl	hweight32
	ldr	r3, [r4, #84]
	ldr	r2, [r4, #16]
	add	r5, r5, #1
	add	r3, r3, r0
	cmp	r2, r5
	str	r3, [r4, #84]
	bgt	.L16
	ldr	r3, [r4, #4]
.L17:
	add	r6, r6, #1
	cmp	r3, r6
	bgt	.L14
.L15:
	ldr	r3, .L35+112
	mov	r0, #48
	ldr	r6, [r3]
	bl	MEQ1_START
	mov	r5, r0
	mov	r0, #96
	bl	MEQ2_START
	mov	r1, r0
	mov	r0, r6
	orr	r1, r5, r1
	bl	WREG32
	ldr	r3, .L35+116
	mov	r1, #32
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L35+120
	ldr	r5, .L35+124
	ldr	r0, [r3]
	mov	r1, #65536
	bl	WREG32
	ldr	r0, [r5]
	bl	RREG32
	ldr	r6, .L35+128
	orr	r1, r0, #50331648
	ldr	r0, [r5]
	bl	WREG32
	mov	r1, #1
	ldr	r0, [r6]
	bl	WREG32
	ldr	r3, .L35+132
	ldr	r5, .L35+136
	ldr	r0, [r3]
	mov	r1, #0
	bl	WREG32
	ldr	r0, [r5]
	bl	RREG32
	ldr	r7, .L35+140
	and	r1, r0, #267386880
	orr	r1, r1, #1024
	ldr	r0, [r5]
	bl	WREG32
	ldr	r0, [r7]
	bl	RREG32
	bic	r1, r0, #131072
	bic	r1, r1, #540
	ldr	r5, .L35+144
	orr	r1, r1, #131072
	orr	r1, r1, #512
	ldr	r0, [r7]
	bl	WREG32
	ldr	r0, [r5]
	bl	RREG32
	orr	r1, r0, #98304
	orr	r1, r1, #520
	ldr	r0, [r5]
	bl	WREG32
	ldr	r3, .L35+148
	mov	r0, #4
	ldr	r5, [r3]
	bl	VTX_DONE_DELAY
	mov	r1, r0
	mov	r0, r5
	bl	WREG32
	ldr	r3, .L35+152
	ldr	r0, [r4, #40]
	ldr	r7, [r3]
	bl	SC_FRONTEND_PRIM_FIFO_SIZE
	mov	r5, r0
	ldr	r0, [r4, #44]
	bl	SC_BACKEND_PRIM_FIFO_SIZE
	mov	r3, r0
	ldr	r0, [r4, #48]
	orr	r5, r5, r3
	bl	SC_HIZ_TILE_FIFO_SIZE
	mov	r3, r0
	ldr	r0, [r4, #52]
	orr	r5, r5, r3
	bl	SC_EARLYZ_TILE_FIFO_SIZE
	mov	r1, r0
	mov	r0, r7
	orr	r1, r5, r1
	bl	WREG32
	ldr	r3, .L35+156
	mov	r1, #1
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L35+160
	mov	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	mov	r1, #0
	ldr	r0, [r6]
	bl	WREG32
	ldr	r3, .L35+164
	ldr	r0, .L35+168
	ldr	r5, [r3]
	bl	FORCE_EOV_MAX_CLK_CNT
	mov	r4, r0
	mov	r0, #255
	bl	FORCE_EOV_MAX_REZ_CNT
	mov	r1, r0
	mov	r0, r5
	orr	r1, r4, r1
	bl	WREG32
	ldr	r2, .L35+172
	ldr	r3, .L35+176
	ldr	r0, [r2]
	ldr	r5, [r3]
	bl	CACHE_INVALIDATION
	ldr	r3, .L35+180
	mov	r4, r0
	ldr	r0, [r3]
	bl	AUTO_INVLD_EN
	mov	r1, r0
	mov	r0, r5
	orr	r1, r4, r1
	bl	WREG32
	ldr	r3, .L35+184
	mov	r1, #16
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L35+188
	ldr	r5, .L35+192
	mov	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	ldr	r0, [r5]
	bl	RREG32
	mov	r1, r0
	ldr	r3, .L35+196
	ldr	r4, .L35+200
	ldr	r3, [r3]
	ldr	r0, [r5]
	orr	r1, r1, r3
	bl	WREG32
	ldr	r0, [r4]
	bl	RREG32
	mov	r1, r0
	ldr	r0, [r4]
	bl	WREG32
	ldr	r3, .L35+204
	mov	r0, #3
	ldr	r4, [r3]
	bl	NUM_CLIP_SEQ
	mov	r1, r0
	ldr	r3, .L35+208
	mov	r0, r4
	ldr	r3, [r3]
	orr	r1, r1, r3
	bl	WREG32
	ldr	r2, .L35+212
	ldr	r3, .L35+216
	ldr	r1, [r2]
	ldr	r0, [r3]
	bl	WREG32
	pop	{r4, r5, r6, r7, r8, lr}
	mov	r0, #50
	b	udelay
.L8:
	mov	r0, #32
	mov	r1, #1
	mov	r3, #64
	ldr	r6, .L35+56
	str	r2, [r4, #64]
	ldr	r2, [r6]
	str	r0, [r4, #68]
	bic	r8, r8, r2
	str	r1, [r4, #72]
	str	r3, [r4, #76]
.L11:
	mov	r0, #2
	b	.L31
.L34:
	cmp	r3, #4
	beq	.L11
	mov	r0, #0
	bl	ROW_SIZE
	orr	r8, r8, r0
	b	.L12
.L33:
	mov	r3, #256
	mov	r0, #1
	mov	r1, #4
	mov	r2, #8
	mov	r8, #2
	mov	r6, #16
	mov	r5, #32
	mov	lr, #48
	mov	ip, #304
	str	r3, [r4, #28]
	str	r3, [r4, #44]
	ldr	r3, .L35+4
	str	r0, [r4, #4]
	str	r0, [r4, #16]
	str	r1, [r4, #8]
	str	r1, [r4, #24]
	str	r2, [r4, #12]
	str	r2, [r4, #36]
	str	r8, [r4, #20]
	str	r6, [r4, #32]
	str	r5, [r4, #40]
	str	lr, [r4, #48]
	str	ip, [r4, #52]
	ldr	r8, [r3]
	b	.L6
.L3:
	mov	r3, #32
	mov	r0, #2
	mov	r1, #4
	mov	r8, #7
	mov	r2, #256
	mov	r6, #1
	mov	r5, #8
	mov	lr, #48
	mov	ip, #304
	str	r3, [r4, #32]
	str	r3, [r4, #40]
	ldr	r3, .L35+4
	str	r0, [r4, #4]
	str	r0, [r4, #20]
	str	r1, [r4, #8]
	str	r1, [r4, #24]
	str	r8, [r4, #12]
	str	r6, [r4, #16]
	str	r2, [r4, #28]
	str	r2, [r4, #44]
	str	r5, [r4, #36]
	str	lr, [r4, #48]
	str	ip, [r4, #52]
	ldr	r8, [r3]
	b	.L6
.L2:
	mov	r3, #32
	mov	r0, #4
	mov	r1, #16
	mov	r8, #11
	mov	r2, #256
	mov	r6, #1
	mov	r5, #8
	mov	lr, #48
	mov	ip, #304
	str	r3, [r4, #32]
	str	r3, [r4, #40]
	ldr	r3, .L35+220
	str	r0, [r4, #4]
	str	r0, [r4, #20]
	str	r1, [r4, #8]
	str	r1, [r4, #24]
	str	r8, [r4, #12]
	str	r6, [r4, #16]
	str	r2, [r4, #28]
	str	r2, [r4, #44]
	str	r5, [r4, #36]
	str	lr, [r4, #48]
	str	ip, [r4, #52]
	ldr	r8, [r3]
	b	.L6
.L36:
	.align	2
.L35:
	.word	GB_ADDR_CONFIG
	.word	BONAIRE_GB_ADDR_CONFIG_GOLDEN
	.word	11284
	.word	12052
	.word	GRBM_CNTL
	.word	SRBM_INT_CNTL
	.word	SRBM_INT_ACK
	.word	FB_READ_EN
	.word	FB_WRITE_EN
	.word	BIF_FB_EN
	.word	MC_SHARED_CHMAP
	.word	MC_ARB_RAMCFG
	.word	NOOFCOLS_MASK
	.word	NOOFCOLS_SHIFT
	.word	ROW_SIZE_MASK
	.word	ROW_SIZE_SHIFT
	.word	PIPE_INTERLEAVE_SIZE_MASK
	.word	PIPE_INTERLEAVE_SIZE_SHIFT
	.word	NOOFBANK_MASK
	.word	NOOFBANK_SHIFT
	.word	HDP_ADDR_CONFIG
	.word	DMIF_ADDR_CALC
	.word	SDMA0_TILING_CONFIG
	.word	SDMA0_REGISTER_OFFSET
	.word	SDMA1_REGISTER_OFFSET
	.word	UVD_UDEC_ADDR_CONFIG
	.word	UVD_UDEC_DB_ADDR_CONFIG
	.word	UVD_UDEC_DBW_ADDR_CONFIG
	.word	CP_MEQ_THRESHOLDS
	.word	SX_DEBUG_1
	.word	TA_CNTL_AUX
	.word	SPI_CONFIG_CNTL
	.word	SQ_CONFIG
	.word	DB_DEBUG
	.word	DB_DEBUG2
	.word	DB_DEBUG3
	.word	CB_HW_CONTROL
	.word	SPI_CONFIG_CNTL_1
	.word	PA_SC_FIFO_SIZE
	.word	VGT_NUM_INSTANCES
	.word	CP_PERFMON_CNTL
	.word	PA_SC_FORCE_EOV_MAX_CNTS
	.word	4095
	.word	VC_AND_TC
	.word	VGT_CACHE_INVALIDATION
	.word	ES_AND_GS_AUTO
	.word	VGT_GS_VERTEX_REUSE
	.word	PA_SC_LINE_STIPPLE_STATE
	.word	HDP_MISC_CNTL
	.word	HDP_FLUSH_INVALIDATE_CACHE
	.word	HDP_HOST_PATH_CNTL
	.word	PA_CL_ENHANCE
	.word	CLIP_VTX_REORDER_ENA
	.word	ENABLE_PA_SC_OUT_OF_ORDER
	.word	PA_SC_ENHANCE
	.word	HAWAII_GB_ADDR_CONFIG_GOLDEN
	.size	cik_gpu_init, .-cik_gpu_init
	.comm	VGT_NUM_INSTANCES,4,4
	.comm	VGT_GS_VERTEX_REUSE,4,4
	.comm	VGT_CACHE_INVALIDATION,4,4
	.comm	VC_AND_TC,4,4
	.comm	UVD_UDEC_DB_ADDR_CONFIG,4,4
	.comm	UVD_UDEC_DBW_ADDR_CONFIG,4,4
	.comm	UVD_UDEC_ADDR_CONFIG,4,4
	.comm	TA_CNTL_AUX,4,4
	.comm	SX_DEBUG_1,4,4
	.comm	SRBM_INT_CNTL,4,4
	.comm	SRBM_INT_ACK,4,4
	.comm	SQ_CONFIG,4,4
	.comm	SPI_CONFIG_CNTL_1,4,4
	.comm	SPI_CONFIG_CNTL,4,4
	.comm	SDMA1_REGISTER_OFFSET,4,4
	.comm	SDMA0_TILING_CONFIG,4,4
	.comm	SDMA0_REGISTER_OFFSET,4,4
	.comm	ROW_SIZE_SHIFT,4,4
	.comm	ROW_SIZE_MASK,4,4
	.comm	PIPE_INTERLEAVE_SIZE_SHIFT,4,4
	.comm	PIPE_INTERLEAVE_SIZE_MASK,4,4
	.comm	PA_SC_LINE_STIPPLE_STATE,4,4
	.comm	PA_SC_FORCE_EOV_MAX_CNTS,4,4
	.comm	PA_SC_FIFO_SIZE,4,4
	.comm	PA_SC_ENHANCE,4,4
	.comm	PA_CL_ENHANCE,4,4
	.comm	NOOFCOLS_SHIFT,4,4
	.comm	NOOFCOLS_MASK,4,4
	.comm	NOOFBANK_SHIFT,4,4
	.comm	NOOFBANK_MASK,4,4
	.comm	MC_SHARED_CHMAP,4,4
	.comm	MC_ARB_RAMCFG,4,4
	.comm	HDP_MISC_CNTL,4,4
	.comm	HDP_HOST_PATH_CNTL,4,4
	.comm	HDP_FLUSH_INVALIDATE_CACHE,4,4
	.comm	HDP_ADDR_CONFIG,4,4
	.comm	HAWAII_GB_ADDR_CONFIG_GOLDEN,4,4
	.comm	GRBM_CNTL,4,4
	.comm	GB_ADDR_CONFIG,4,4
	.comm	FB_WRITE_EN,4,4
	.comm	FB_READ_EN,4,4
	.comm	ES_AND_GS_AUTO,4,4
	.comm	ENABLE_PA_SC_OUT_OF_ORDER,4,4
	.comm	DMIF_ADDR_CALC,4,4
	.comm	DB_DEBUG3,4,4
	.comm	DB_DEBUG2,4,4
	.comm	DB_DEBUG,4,4
	.comm	CP_PERFMON_CNTL,4,4
	.comm	CP_MEQ_THRESHOLDS,4,4
	.comm	CLIP_VTX_REORDER_ENA,4,4
	.comm	CB_HW_CONTROL,4,4
	.comm	BONAIRE_GB_ADDR_CONFIG_GOLDEN,4,4
	.comm	BIF_FB_EN,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
