	.file	"extr_sparcv9cap.c_OPENSSL_cpuid_setup.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"OPENSSL_sparcv9cap"
	.text
	.p2align 4
	.globl	OPENSSL_cpuid_setup
	.type	OPENSSL_cpuid_setup, @function
OPENSSL_cpuid_setup:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	sub	rsp, 56
	.cfi_def_cfa_offset 80
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 40[rsp], rax
	xor	eax, eax
	mov	eax, DWORD PTR trigger.1999[rip]
	test	eax, eax
	je	.L18
.L1:
	mov	rax, QWORD PTR 40[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L19
	add	rsp, 56
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L18:
	.cfi_restore_state
	lea	rdi, .LC0[rip]
	mov	DWORD PTR trigger.1999[rip], 1
	call	getenv@PLT
	mov	rbx, QWORD PTR OPENSSL_sparcv9cap_P[rip]
	mov	rbp, rax
	test	rax, rax
	je	.L3
	xor	esi, esi
	xor	edx, edx
	mov	rdi, rax
	call	strtoul@PLT
	mov	esi, 58
	mov	rdi, rbp
	mov	DWORD PTR [rbx], eax
	call	strchr@PLT
	test	rax, rax
	je	.L1
	mov	rbx, QWORD PTR OPENSSL_sparcv9cap_P[rip]
	lea	rdi, 1[rax]
	xor	edx, edx
	xor	esi, esi
	call	strtoul@PLT
	mov	DWORD PTR 4[rbx], eax
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L3:
	mov	eax, DWORD PTR SPARCV9_PREFER_FPU[rip]
	or	eax, DWORD PTR SPARCV9_TICK_PRIVILEGED[rip]
	lea	rbp, 8[rsp]
	mov	DWORD PTR [rbx], eax
	mov	rdi, rbp
	call	sigfillset@PLT
	mov	esi, DWORD PTR SIGILL[rip]
	mov	rdi, rbp
	call	sigdelset@PLT
	mov	esi, DWORD PTR SIGTRAP[rip]
	mov	rdi, rbp
	call	sigdelset@PLT
	mov	esi, DWORD PTR SIGFPE[rip]
	mov	rdi, rbp
	call	sigdelset@PLT
	mov	esi, DWORD PTR SIGBUS[rip]
	mov	rdi, rbp
	call	sigdelset@PLT
	mov	esi, DWORD PTR SIGSEGV[rip]
	mov	rdi, rbp
	call	sigdelset@PLT
	mov	edi, DWORD PTR SIG_SETMASK[rip]
	mov	rsi, rbp
	lea	rdx, 12[rsp]
	lea	rbp, 16[rsp]
	call	sigprocmask@PLT
	mov	edx, 8
	xor	esi, esi
	mov	rdi, rbp
	call	memset@PLT
	mov	eax, DWORD PTR common_handler[rip]
	lea	rdx, 24[rsp]
	mov	rsi, rbp
	mov	edi, DWORD PTR SIGILL[rip]
	mov	DWORD PTR 20[rsp], eax
	mov	eax, DWORD PTR 8[rsp]
	mov	DWORD PTR 16[rsp], eax
	call	sigaction@PLT
	mov	edi, DWORD PTR SIGBUS[rip]
	mov	rsi, rbp
	lea	rdx, 32[rsp]
	call	sigaction@PLT
	mov	edi, DWORD PTR common_jmp[rip]
	mov	esi, 1
	call	sigsetjmp@PLT
	endbr64
	test	rax, rax
	je	.L20
.L6:
	mov	edi, DWORD PTR common_jmp[rip]
	mov	esi, 1
	call	sigsetjmp@PLT
	endbr64
	test	rax, rax
	je	.L21
.L7:
	mov	edi, DWORD PTR common_jmp[rip]
	mov	esi, 1
	call	sigsetjmp@PLT
	endbr64
	test	rax, rax
	je	.L22
.L9:
	mov	edi, DWORD PTR common_jmp[rip]
	mov	esi, 1
	call	sigsetjmp@PLT
	endbr64
	test	rax, rax
	je	.L23
.L10:
	mov	edi, DWORD PTR common_jmp[rip]
	mov	esi, 1
	call	sigsetjmp@PLT
	endbr64
	test	rax, rax
	je	.L11
	mov	rax, QWORD PTR OPENSSL_sparcv9cap_P[rip]
	mov	eax, DWORD PTR [rax]
.L12:
	test	DWORD PTR SPARCV9_VIS3[rip], eax
	je	.L13
	mov	edi, DWORD PTR common_jmp[rip]
	mov	esi, 1
	call	sigsetjmp@PLT
	endbr64
	test	rax, rax
	je	.L24
.L13:
	mov	edi, DWORD PTR SIGBUS[rip]
	lea	rsi, 32[rsp]
	xor	edx, edx
	call	sigaction@PLT
	mov	edi, DWORD PTR SIGILL[rip]
	lea	rsi, 24[rsp]
	xor	edx, edx
	call	sigaction@PLT
	mov	edi, DWORD PTR SIG_SETMASK[rip]
	xor	edx, edx
	lea	rsi, 12[rsp]
	call	sigprocmask@PLT
	mov	rax, QWORD PTR OPENSSL_sparcv9cap_P[rip]
	mov	edx, DWORD PTR SPARCV9_64BIT_STACK[rip]
	or	DWORD PTR [rax], edx
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L24:
	call	_sparcv9_rdcfr@PLT
	mov	rdx, QWORD PTR OPENSSL_sparcv9cap_P[rip]
	mov	DWORD PTR 4[rdx], eax
	jmp	.L13
	.p2align 4,,10
	.p2align 3
.L11:
	xor	eax, eax
	call	_sparcv9_fjaesx_probe@PLT
	mov	rdx, QWORD PTR OPENSSL_sparcv9cap_P[rip]
	mov	eax, DWORD PTR [rdx]
	or	eax, DWORD PTR SPARCV9_FJAESX[rip]
	mov	DWORD PTR [rdx], eax
	jmp	.L12
	.p2align 4,,10
	.p2align 3
.L23:
	call	_sparcv9_vis3_probe@PLT
	mov	rax, QWORD PTR OPENSSL_sparcv9cap_P[rip]
	mov	edx, DWORD PTR SPARCV9_VIS3[rip]
	or	DWORD PTR [rax], edx
	jmp	.L10
	.p2align 4,,10
	.p2align 3
.L22:
	call	_sparcv9_fmadd_probe@PLT
	mov	rax, QWORD PTR OPENSSL_sparcv9cap_P[rip]
	mov	edx, DWORD PTR SPARCV9_FMADD[rip]
	or	DWORD PTR [rax], edx
	jmp	.L9
	.p2align 4,,10
	.p2align 3
.L21:
	call	_sparcv9_vis1_probe@PLT
	mov	rdx, QWORD PTR OPENSSL_sparcv9cap_P[rip]
	mov	eax, DWORD PTR SPARCV9_VIS1[rip]
	or	eax, DWORD PTR SPARCV9_BLK[rip]
	or	DWORD PTR [rdx], eax
	xor	eax, eax
	call	_sparcv9_vis1_instrument@PLT
	cmp	eax, 11
	jle	.L8
	mov	rdx, QWORD PTR OPENSSL_sparcv9cap_P[rip]
	mov	eax, DWORD PTR SPARCV9_VIS1[rip]
	or	eax, DWORD PTR SPARCV9_PREFER_FPU[rip]
	not	eax
	and	DWORD PTR [rdx], eax
	jmp	.L7
	.p2align 4,,10
	.p2align 3
.L20:
	call	_sparcv9_rdtick@PLT
	mov	eax, DWORD PTR SPARCV9_TICK_PRIVILEGED[rip]
	mov	rdx, QWORD PTR OPENSSL_sparcv9cap_P[rip]
	not	eax
	and	DWORD PTR [rdx], eax
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L8:
	xor	eax, eax
	call	_sparcv9_vis2_probe@PLT
	mov	rax, QWORD PTR OPENSSL_sparcv9cap_P[rip]
	mov	edx, DWORD PTR SPARCV9_VIS2[rip]
	or	DWORD PTR [rax], edx
	jmp	.L7
.L19:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	OPENSSL_cpuid_setup, .-OPENSSL_cpuid_setup
	.local	trigger.1999
	.comm	trigger.1999,4,4
	.comm	common_jmp,4,4
	.comm	common_handler,4,4
	.comm	SPARCV9_VIS4,4,4
	.comm	SPARCV9_VIS3,4,4
	.comm	SPARCV9_VIS2,4,4
	.comm	SPARCV9_VIS1,4,4
	.comm	SPARCV9_TICK_PRIVILEGED,4,4
	.comm	SPARCV9_PREFER_FPU,4,4
	.comm	SPARCV9_IMA,4,4
	.comm	SPARCV9_FMADD,4,4
	.comm	SPARCV9_FJHPCACE,4,4
	.comm	SPARCV9_FJDESX,4,4
	.comm	SPARCV9_FJAESX,4,4
	.comm	SPARCV9_BLK,4,4
	.comm	SPARCV9_64BIT_STACK,4,4
	.comm	SIG_SETMASK,4,4
	.comm	SIGTRAP,4,4
	.comm	SIGSEGV,4,4
	.comm	SIGILL,4,4
	.comm	SIGFPE,4,4
	.comm	SIGEMT,4,4
	.comm	SIGBUS,4,4
	.comm	OPENSSL_sparcv9cap_P,8,8
	.comm	CFR_XMPMUL,4,4
	.comm	CFR_XMONTSQR,4,4
	.comm	CFR_XMONTMUL,4,4
	.comm	CFR_MONTMUL,4,4
	.comm	CFR_CRC32C,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_sparcv9cap.c_OPENSSL_cpuid_setup.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"OPENSSL_sparcv9cap\000"
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC1:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	OPENSSL_cpuid_setup
	.syntax unified
	.arm
	.fpu softvfp
	.type	OPENSSL_cpuid_setup, %function
OPENSSL_cpuid_setup:
	@ args = 0, pretend = 0, frame = 40
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	ldr	r3, .L24
	ldr	r2, .L24+4
	ldr	r4, [r3]
	sub	sp, sp, #40
	cmp	r4, #0
	ldr	r2, [r2]
	str	r2, [sp, #36]
	mov	r2,#0
	beq	.L17
.L1:
	ldr	r3, .L24+4
	ldr	r2, [r3]
	ldr	r3, [sp, #36]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L18
	add	sp, sp, #40
	@ sp needed
	pop	{r4, r5, r6, r7, r8, pc}
.L17:
	mov	r7, #1
	ldr	r0, .L24+8
	str	r7, [r3]
	bl	getenv
	ldr	r6, .L24+12
	subs	r5, r0, #0
	ldr	r8, [r6]
	beq	.L3
	mov	r2, r4
	mov	r1, r4
	bl	strtoul
	mov	r1, #58
	str	r0, [r8]
	mov	r0, r5
	bl	strchr
	cmp	r0, #0
	beq	.L1
	mov	r2, r4
	mov	r1, r4
	add	r0, r0, r7
	ldr	r4, [r6]
	bl	strtoul
	str	r0, [r4, #4]
	b	.L1
.L3:
	ldr	r3, .L24+16
	ldr	r2, .L24+20
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	r5, .L24+24
	orr	r3, r3, r2
	str	r3, [r8]
	add	r0, sp, #4
	bl	sigfillset
	ldr	r1, [r5]
	add	r0, sp, #4
	bl	sigdelset
	ldr	r3, .L24+28
	add	r0, sp, #4
	ldr	r1, [r3]
	bl	sigdelset
	ldr	r3, .L24+32
	ldr	r4, .L24+36
	ldr	r1, [r3]
	add	r0, sp, #4
	bl	sigdelset
	ldr	r1, [r4]
	add	r0, sp, #4
	bl	sigdelset
	ldr	r3, .L24+40
	add	r0, sp, #4
	ldr	r1, [r3]
	bl	sigdelset
	ldr	r3, .L24+44
	add	r1, sp, #4
	add	r2, sp, #8
	ldr	r0, [r3]
	bl	sigprocmask
	ldr	r2, .L24+48
	ldr	r3, [sp, #4]
	ldr	r2, [r2]
	add	r1, sp, #12
	str	r2, [sp, #16]
	ldr	r0, [r5]
	add	r2, sp, #20
	str	r3, [sp, #12]
	bl	sigaction
	add	r1, sp, #12
	ldr	r0, [r4]
	add	r2, sp, #28
	bl	sigaction
	ldr	r3, .L24+52
	mov	r1, r7
	ldr	r0, [r3]
	bl	sigsetjmp
	cmp	r0, #0
	beq	.L19
.L6:
	ldr	r3, .L24+52
	mov	r1, #1
	ldr	r0, [r3]
	bl	sigsetjmp
	cmp	r0, #0
	beq	.L20
.L7:
	ldr	r3, .L24+52
	mov	r1, #1
	ldr	r0, [r3]
	bl	sigsetjmp
	cmp	r0, #0
	beq	.L21
.L9:
	ldr	r3, .L24+52
	mov	r1, #1
	ldr	r0, [r3]
	bl	sigsetjmp
	cmp	r0, #0
	beq	.L22
.L10:
	ldr	r3, .L24+52
	mov	r1, #1
	ldr	r0, [r3]
	bl	sigsetjmp
	cmp	r0, #0
	beq	.L11
	ldr	r3, .L24+12
	ldr	r3, [r3]
	ldr	r3, [r3]
.L12:
	ldr	r2, .L24+56
	ldr	r2, [r2]
	tst	r3, r2
	beq	.L13
	ldr	r3, .L24+52
	mov	r1, #1
	ldr	r0, [r3]
	bl	sigsetjmp
	cmp	r0, #0
	beq	.L23
.L13:
	ldr	r3, .L24+36
	mov	r2, #0
	ldr	r0, [r3]
	add	r1, sp, #28
	bl	sigaction
	ldr	r3, .L24+24
	mov	r2, #0
	ldr	r0, [r3]
	add	r1, sp, #20
	bl	sigaction
	ldr	r3, .L24+44
	mov	r2, #0
	ldr	r0, [r3]
	add	r1, sp, #8
	bl	sigprocmask
	mov	r0, #340
	bl	syscall
	cmp	r0, #0
	blt	.L1
	tst	r0, #1
	beq	.L1
	ldr	r2, .L24+12
	ldr	r3, .L24+60
	ldr	r2, [r2]
	ldr	r1, [r3]
	ldr	r3, [r2]
	orr	r3, r3, r1
	str	r3, [r2]
	b	.L1
.L23:
	ldr	r3, .L24+12
	ldr	r4, [r3]
	bl	_sparcv9_rdcfr
	str	r0, [r4, #4]
	b	.L13
.L11:
	bl	_sparcv9_fjaesx_probe
	ldr	r2, .L24+12
	ldr	r3, .L24+64
	ldr	r2, [r2]
	ldr	r1, [r3]
	ldr	r3, [r2]
	orr	r3, r3, r1
	str	r3, [r2]
	b	.L12
.L22:
	bl	_sparcv9_vis3_probe
	ldr	r2, .L24+12
	ldr	r3, .L24+56
	ldr	r2, [r2]
	ldr	r1, [r3]
	ldr	r3, [r2]
	orr	r3, r3, r1
	str	r3, [r2]
	b	.L10
.L21:
	bl	_sparcv9_fmadd_probe
	ldr	r2, .L24+12
	ldr	r3, .L24+68
	ldr	r2, [r2]
	ldr	r1, [r3]
	ldr	r3, [r2]
	orr	r3, r3, r1
	str	r3, [r2]
	b	.L9
.L20:
	ldr	r4, .L24+12
	bl	_sparcv9_vis1_probe
	ldr	r5, .L24+72
	ldr	r3, .L24+76
	ldr	r1, [r4]
	ldr	r0, [r3]
	ldr	r2, [r5]
	ldr	r3, [r1]
	orr	r2, r2, r0
	orr	r3, r3, r2
	str	r3, [r1]
	bl	_sparcv9_vis1_instrument
	cmp	r0, #11
	ble	.L8
	ldr	r3, .L24+16
	ldr	r1, [r4]
	ldr	r0, [r3]
	ldr	r2, [r5]
	ldr	r3, [r1]
	orr	r2, r2, r0
	bic	r3, r3, r2
	str	r3, [r1]
	b	.L7
.L19:
	bl	_sparcv9_rdtick
	ldr	r2, .L24+12
	ldr	r3, .L24+20
	ldr	r2, [r2]
	ldr	r1, [r3]
	ldr	r3, [r2]
	bic	r3, r3, r1
	str	r3, [r2]
	b	.L6
.L8:
	bl	_sparcv9_vis2_probe
	ldr	r2, [r4]
	ldr	r1, .L24+80
	ldr	r3, [r2]
	ldr	r1, [r1]
	orr	r3, r3, r1
	str	r3, [r2]
	b	.L7
.L18:
	bl	__stack_chk_fail
.L25:
	.align	2
.L24:
	.word	.LANCHOR0
	.word	.LC1
	.word	.LC0
	.word	OPENSSL_sparcv9cap_P
	.word	SPARCV9_PREFER_FPU
	.word	SPARCV9_TICK_PRIVILEGED
	.word	SIGILL
	.word	SIGTRAP
	.word	SIGFPE
	.word	SIGBUS
	.word	SIGSEGV
	.word	SIG_SETMASK
	.word	common_handler
	.word	common_jmp
	.word	SPARCV9_VIS3
	.word	SPARCV9_64BIT_STACK
	.word	SPARCV9_FJAESX
	.word	SPARCV9_FMADD
	.word	SPARCV9_VIS1
	.word	SPARCV9_BLK
	.word	SPARCV9_VIS2
	.size	OPENSSL_cpuid_setup, .-OPENSSL_cpuid_setup
	.comm	common_jmp,4,4
	.comm	common_handler,4,4
	.comm	SPARCV9_VIS4,4,4
	.comm	SPARCV9_VIS3,4,4
	.comm	SPARCV9_VIS2,4,4
	.comm	SPARCV9_VIS1,4,4
	.comm	SPARCV9_TICK_PRIVILEGED,4,4
	.comm	SPARCV9_PREFER_FPU,4,4
	.comm	SPARCV9_IMA,4,4
	.comm	SPARCV9_FMADD,4,4
	.comm	SPARCV9_FJHPCACE,4,4
	.comm	SPARCV9_FJDESX,4,4
	.comm	SPARCV9_FJAESX,4,4
	.comm	SPARCV9_BLK,4,4
	.comm	SPARCV9_64BIT_STACK,4,4
	.comm	SIG_SETMASK,4,4
	.comm	SIGTRAP,4,4
	.comm	SIGSEGV,4,4
	.comm	SIGILL,4,4
	.comm	SIGFPE,4,4
	.comm	SIGEMT,4,4
	.comm	SIGBUS,4,4
	.comm	OPENSSL_sparcv9cap_P,4,4
	.comm	CFR_XMPMUL,4,4
	.comm	CFR_XMONTSQR,4,4
	.comm	CFR_XMONTMUL,4,4
	.comm	CFR_MONTMUL,4,4
	.comm	CFR_CRC32C,4,4
	.bss
	.align	2
	.set	.LANCHOR0,. + 0
	.type	trigger.4283, %object
	.size	trigger.4283, 4
trigger.4283:
	.space	4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
