	.file	"extr_m68kopdm.c_m68k_op_divl_32_i.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	m68k_op_divl_32_i
	.type	m68k_op_divl_32_i, @function
m68k_op_divl_32_i:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 40
	.cfi_def_cfa_offset 96
	mov	edi, DWORD PTR CPU_TYPE[rip]
	call	CPU_TYPE_IS_EC020_PLUS@PLT
	test	rax, rax
	mov	eax, 0
	je	.L2
	call	OPER_I_16@PLT
	mov	r12d, eax
	xor	eax, eax
	call	OPER_I_32@PLT
	mov	r14d, eax
	test	eax, eax
	je	.L3
	mov	rax, QWORD PTR REG_D[rip]
	mov	esi, r12d
	mov	edx, r12d
	mov	edi, r12d
	and	esi, 7
	sar	edx, 12
	mov	QWORD PTR 8[rsp], rsi
	mov	ebx, DWORD PTR [rax+rsi*4]
	mov	esi, edx
	and	esi, 7
	mov	QWORD PTR 16[rsp], rsi
	mov	ebp, DWORD PTR [rax+rsi*4]
	call	BIT_A@PLT
	mov	edi, r12d
	test	rax, rax
	jne	.L57
	call	BIT_B@PLT
	test	rax, rax
	je	.L16
	cmp	ebp, -2147483648
	jne	.L17
	cmp	r14d, -1
	jne	.L17
	mov	eax, DWORD PTR NFLAG_SET[rip]
	mov	rdx, QWORD PTR 16[rsp]
	mov	DWORD PTR FLAG_N[rip], eax
	mov	eax, DWORD PTR ZFLAG_CLEAR[rip]
	mov	DWORD PTR FLAG_Z[rip], eax
	mov	eax, DWORD PTR VFLAG_CLEAR[rip]
	mov	DWORD PTR FLAG_V[rip], eax
	mov	eax, DWORD PTR CFLAG_CLEAR[rip]
	mov	DWORD PTR FLAG_C[rip], eax
	mov	rax, QWORD PTR REG_D[rip]
	mov	DWORD PTR [rax+rdx*4], -2147483648
	mov	rdx, QWORD PTR 8[rsp]
	mov	DWORD PTR [rax+rdx*4], 0
.L1:
	add	rsp, 40
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L2:
	.cfi_restore_state
	add	rsp, 40
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	jmp	m68ki_exception_illegal@PLT
	.p2align 4,,10
	.p2align 3
.L3:
	.cfi_restore_state
	mov	edi, DWORD PTR EXCEPTION_ZERO_DIVIDE[rip]
	add	rsp, 40
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	jmp	m68ki_exception_trap@PLT
	.p2align 4,,10
	.p2align 3
.L57:
	.cfi_restore_state
	call	BIT_B@PLT
	test	rax, rax
	je	.L19
	test	ebx, ebx
	sete	dl
	cmp	r14d, -1
	sete	al
	test	dl, al
	je	.L6
	cmp	ebp, -2147483648
	jne	.L6
	mov	rax, QWORD PTR REG_D[rip]
	mov	rdx, QWORD PTR 8[rsp]
	mov	DWORD PTR [rax+rdx*4], 0
	mov	rdx, QWORD PTR 16[rsp]
	mov	DWORD PTR [rax+rdx*4], -2147483648
	mov	eax, DWORD PTR NFLAG_SET[rip]
	mov	DWORD PTR FLAG_N[rip], eax
	mov	eax, DWORD PTR ZFLAG_CLEAR[rip]
	mov	DWORD PTR FLAG_Z[rip], eax
	mov	eax, DWORD PTR VFLAG_CLEAR[rip]
	mov	DWORD PTR FLAG_V[rip], eax
	mov	eax, DWORD PTR CFLAG_CLEAR[rip]
	mov	DWORD PTR FLAG_C[rip], eax
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L6:
	mov	edi, ebx
	call	GET_MSB_32@PLT
	mov	DWORD PTR 28[rsp], eax
	test	eax, eax
	jne	.L58
.L8:
	mov	edi, r14d
	call	GET_MSB_32@PLT
	mov	DWORD PTR 24[rsp], eax
	test	eax, eax
	jne	.L59
.L5:
	cmp	r14d, ebx
	jg	.L20
	mov	eax, DWORD PTR VFLAG_SET[rip]
	mov	DWORD PTR FLAG_V[rip], eax
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L19:
	mov	DWORD PTR 24[rsp], 0
	mov	DWORD PTR 28[rsp], 0
	jmp	.L5
	.p2align 4,,10
	.p2align 3
.L20:
	mov	ecx, 31
	xor	r13d, r13d
	xor	r15d, r15d
	.p2align 4,,10
	.p2align 3
.L9:
	mov	eax, ebx
	add	r15d, r15d
	sar	eax, cl
	and	eax, 1
	lea	r13d, [rax+r13*2]
	cmp	r14d, r13d
	jg	.L10
	sub	r13d, r14d
	add	r15d, 1
.L10:
	sub	ecx, 1
	cmp	ecx, -1
	jne	.L9
	mov	ebx, 31
	jmp	.L13
	.p2align 4,,10
	.p2align 3
.L11:
	sub	ebx, 1
	cmp	ebx, -1
	je	.L60
.L13:
	mov	edi, r13d
	add	r15d, r15d
	call	GET_MSB_32@PLT
	mov	edi, ebp
	mov	ecx, ebx
	sar	edi, cl
	and	edi, 1
	lea	r13d, [rdi+r13*2]
	cmp	r14d, r13d
	jle	.L21
	test	eax, eax
	je	.L11
.L21:
	sub	r13d, r14d
	add	r15d, 1
	jmp	.L11
	.p2align 4,,10
	.p2align 3
.L60:
	mov	edi, r12d
	call	BIT_B@PLT
	test	rax, rax
	je	.L14
	mov	edx, DWORD PTR 28[rsp]
	test	edx, edx
	jne	.L61
.L15:
	mov	eax, DWORD PTR 24[rsp]
	test	eax, eax
	je	.L14
	mov	edi, r15d
	neg	edi
	call	MASK_OUT_ABOVE_32@PLT
	mov	r15d, eax
	.p2align 4,,10
	.p2align 3
.L14:
	mov	rax, QWORD PTR REG_D[rip]
	mov	rdx, QWORD PTR 8[rsp]
	mov	edi, r15d
	mov	DWORD PTR [rax+rdx*4], r13d
	mov	rdx, QWORD PTR 16[rsp]
	mov	DWORD PTR [rax+rdx*4], r15d
	call	NFLAG_32@PLT
	mov	DWORD PTR FLAG_Z[rip], r15d
	mov	DWORD PTR FLAG_N[rip], eax
	mov	eax, DWORD PTR VFLAG_CLEAR[rip]
	mov	DWORD PTR FLAG_V[rip], eax
	mov	eax, DWORD PTR CFLAG_CLEAR[rip]
	mov	DWORD PTR FLAG_C[rip], eax
	jmp	.L1
.L59:
	mov	edi, r14d
	neg	edi
	call	MASK_OUT_ABOVE_32@PLT
	mov	DWORD PTR 24[rsp], 1
	mov	r14d, eax
	jmp	.L5
.L58:
	neg	ebx
	xor	eax, eax
	test	ebp, ebp
	setne	al
	mov	edi, ebx
	sub	edi, eax
	call	MASK_OUT_ABOVE_32@PLT
	mov	edi, ebp
	neg	edi
	mov	ebx, eax
	call	MASK_OUT_ABOVE_32@PLT
	mov	DWORD PTR 28[rsp], 1
	mov	ebp, eax
	jmp	.L8
	.p2align 4,,10
	.p2align 3
.L17:
	mov	edi, ebp
	call	MAKE_INT_32@PLT
	mov	edi, r14d
	mov	r12d, eax
	call	MAKE_INT_32@PLT
	mov	rsi, QWORD PTR 8[rsp]
	mov	edi, ebp
	mov	r9d, eax
	mov	eax, r12d
	cdq
	idiv	r9d
	mov	rax, QWORD PTR REG_D[rip]
	mov	DWORD PTR [rax+rsi*4], edx
	call	MAKE_INT_32@PLT
	mov	edi, r14d
	mov	r12d, eax
	call	MAKE_INT_32@PLT
.L55:
	mov	r8d, eax
	mov	eax, r12d
	cdq
	idiv	r8d
	mov	rdx, QWORD PTR 16[rsp]
	mov	r12d, eax
	mov	rax, QWORD PTR REG_D[rip]
	mov	edi, r12d
	mov	DWORD PTR [rax+rdx*4], r12d
	call	NFLAG_32@PLT
	mov	DWORD PTR FLAG_Z[rip], r12d
	mov	DWORD PTR FLAG_N[rip], eax
	mov	eax, DWORD PTR VFLAG_CLEAR[rip]
	mov	DWORD PTR FLAG_V[rip], eax
	mov	eax, DWORD PTR CFLAG_CLEAR[rip]
	mov	DWORD PTR FLAG_C[rip], eax
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L16:
	mov	edi, ebp
	call	MASK_OUT_ABOVE_32@PLT
	mov	edi, r14d
	mov	r12d, eax
	call	MASK_OUT_ABOVE_32@PLT
	mov	rsi, QWORD PTR 8[rsp]
	mov	edi, ebp
	mov	r9d, eax
	mov	eax, r12d
	cdq
	idiv	r9d
	mov	rax, QWORD PTR REG_D[rip]
	mov	DWORD PTR [rax+rsi*4], edx
	call	MASK_OUT_ABOVE_32@PLT
	mov	edi, r14d
	mov	r12d, eax
	call	MASK_OUT_ABOVE_32@PLT
	jmp	.L55
.L61:
	mov	edi, r13d
	neg	edi
	call	MASK_OUT_ABOVE_32@PLT
	mov	edi, r15d
	neg	edi
	mov	r13d, eax
	call	MASK_OUT_ABOVE_32@PLT
	mov	r15d, eax
	jmp	.L15
	.cfi_endproc
.LFE0:
	.size	m68k_op_divl_32_i, .-m68k_op_divl_32_i
	.comm	ZFLAG_CLEAR,4,4
	.comm	VFLAG_SET,4,4
	.comm	VFLAG_CLEAR,4,4
	.comm	REG_D,8,8
	.comm	NFLAG_SET,4,4
	.comm	FLAG_Z,4,4
	.comm	FLAG_V,4,4
	.comm	FLAG_N,4,4
	.comm	FLAG_C,4,4
	.comm	EXCEPTION_ZERO_DIVIDE,4,4
	.comm	CPU_TYPE,4,4
	.comm	CFLAG_CLEAR,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_m68kopdm.c_m68k_op_divl_32_i.c"
	.text
	.global	__aeabi_idivmod
	.global	__aeabi_idiv
	.align	2
	.global	m68k_op_divl_32_i
	.syntax unified
	.arm
	.fpu softvfp
	.type	m68k_op_divl_32_i, %function
m68k_op_divl_32_i:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r3, .L48
	sub	sp, sp, #20
	ldr	r0, [r3]
	bl	CPU_TYPE_IS_EC020_PLUS
	cmp	r0, #0
	beq	.L2
	bl	OPER_I_16
	mov	r6, r0
	bl	OPER_I_32
	subs	fp, r0, #0
	beq	.L3
	ldr	r9, .L48+4
	asr	r7, r6, #12
	ldr	r3, [r9]
	and	r2, r6, #7
	mov	r0, r6
	and	r7, r7, #7
	ldr	r10, [r3, r2, lsl #2]
	ldr	r5, [r3, r7, lsl #2]
	str	r2, [sp, #4]
	bl	BIT_A
	subs	r4, r0, #0
	mov	r0, r6
	bne	.L43
	bl	BIT_B
	cmp	r0, #0
	beq	.L15
	cmp	r5, #-2147483648
	cmneq	fp, #1
	bne	.L16
	mov	r2, #-2147483648
	ldr	r1, .L48+8
	ldr	r0, .L48+12
	ldr	ip, [r1]
	ldr	r1, .L48+16
	ldr	r0, [r0]
	str	ip, [r1]
	ldr	r1, .L48+20
	ldr	ip, .L48+24
	str	r0, [r1]
	ldr	ip, [ip]
	ldr	r1, .L48+28
	ldr	r0, .L48+32
	str	ip, [r1]
	ldr	r0, [r0]
	ldr	r3, [r9]
	ldr	r1, .L48+36
	str	r0, [r1]
	str	r2, [r3, r7, lsl #2]
	ldr	r2, [sp, #4]
	str	r4, [r3, r2, lsl #2]
.L1:
	add	sp, sp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L2:
	add	sp, sp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	b	m68ki_exception_illegal
.L3:
	ldr	r3, .L48+40
	ldr	r0, [r3]
	add	sp, sp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	b	m68ki_exception_trap
.L43:
	bl	BIT_B
	subs	r3, r0, #0
	str	r3, [sp, #8]
	beq	.L18
	cmn	fp, #1
	movne	r3, #0
	moveq	r3, #1
	cmp	r10, #0
	movne	r3, #0
	cmp	r5, #-2147483648
	movne	r3, #0
	andeq	r3, r3, #1
	cmp	r3, #0
	bne	.L44
	mov	r0, r10
	bl	GET_MSB_32
	subs	r3, r0, #0
	str	r3, [sp, #8]
	bne	.L45
.L8:
	mov	r0, fp
	bl	GET_MSB_32
	subs	r3, r0, #0
	str	r3, [sp, #12]
	bne	.L46
.L5:
	cmp	fp, r10
	bgt	.L19
	ldr	r2, .L48+44
	ldr	r3, .L48+28
	ldr	r2, [r2]
	str	r2, [r3]
	b	.L1
.L18:
	ldr	r3, [sp, #8]
	str	r3, [sp, #12]
	b	.L5
.L19:
	mov	r4, #0
	mov	r0, #31
	mov	r8, r4
.L9:
	asr	ip, r10, r0
	and	ip, ip, #1
	add	r4, ip, r4, lsl #1
	cmp	fp, r4
	sub	r0, r0, #1
	lsl	r8, r8, #1
	suble	r4, r4, fp
	addle	r8, r8, #1
	cmn	r0, #1
	bne	.L9
	mov	r10, #31
.L12:
	mov	r0, r4
	bl	GET_MSB_32
	subs	r0, r0, #0
	movne	r0, #1
	asr	ip, r5, r10
	and	ip, ip, #1
	add	r4, ip, r4, lsl #1
	cmp	fp, r4
	orrle	r0, r0, #1
	sub	r10, r10, #1
	cmp	r0, #0
	lsl	r8, r8, #1
	subne	r4, r4, fp
	addne	r8, r8, #1
	cmn	r10, #1
	bne	.L12
	mov	r0, r6
	bl	BIT_B
	cmp	r0, #0
	beq	.L13
	ldr	r3, [sp, #8]
	cmp	r3, #0
	bne	.L47
.L14:
	ldr	r3, [sp, #12]
	cmp	r3, #0
	beq	.L13
	rsb	r0, r8, #0
	bl	MASK_OUT_ABOVE_32
	mov	r8, r0
.L13:
	ldr	r2, [r9]
	ldr	r3, [sp, #4]
	mov	r0, r8
	str	r4, [r2, r3, lsl #2]
	str	r8, [r2, r7, lsl #2]
	bl	NFLAG_32
	ldr	ip, .L48+24
	ldr	r1, .L48+32
	ldr	r2, .L48+16
	ldr	r4, [ip]
	str	r0, [r2]
	ldr	ip, [r1]
	ldr	lr, .L48+28
	ldr	r1, .L48+36
	ldr	r2, .L48+20
	str	r4, [lr]
	str	ip, [r1]
	str	r8, [r2]
	b	.L1
.L46:
	rsb	r0, fp, #0
	bl	MASK_OUT_ABOVE_32
	mov	r3, #1
	mov	fp, r0
	str	r3, [sp, #12]
	b	.L5
.L45:
	rsb	r0, r10, #0
	cmp	r5, #0
	subne	r0, r0, #1
	bl	MASK_OUT_ABOVE_32
	mov	r10, r0
	rsb	r0, r5, #0
	bl	MASK_OUT_ABOVE_32
	mov	r3, #1
	mov	r5, r0
	str	r3, [sp, #8]
	b	.L8
.L16:
	mov	r0, r5
	bl	MAKE_INT_32
	mov	r4, r0
	mov	r0, fp
	bl	MAKE_INT_32
	mov	r1, r0
	mov	r0, r4
	bl	__aeabi_idivmod
	ldr	r3, [r9]
	ldr	r2, [sp, #4]
	mov	r0, r5
	str	r1, [r3, r2, lsl #2]
	bl	MAKE_INT_32
	mov	r4, r0
	mov	r0, fp
	bl	MAKE_INT_32
.L41:
	mov	r1, r0
	mov	r0, r4
	bl	__aeabi_idiv
	ldr	r3, [r9]
	mov	r4, r0
	str	r0, [r3, r7, lsl #2]
	bl	NFLAG_32
	ldr	r1, .L48+24
	ldr	r2, .L48+32
	ldr	r3, .L48+16
	ldr	lr, [r1]
	str	r0, [r3]
	ldr	r1, [r2]
	ldr	ip, .L48+28
	ldr	r2, .L48+36
	ldr	r3, .L48+20
	str	lr, [ip]
	str	r1, [r2]
	str	r4, [r3]
	b	.L1
.L15:
	mov	r0, r5
	bl	MASK_OUT_ABOVE_32
	mov	r4, r0
	mov	r0, fp
	bl	MASK_OUT_ABOVE_32
	mov	r1, r0
	mov	r0, r4
	bl	__aeabi_idivmod
	ldr	r3, [r9]
	ldr	r2, [sp, #4]
	mov	r0, r5
	str	r1, [r3, r2, lsl #2]
	bl	MASK_OUT_ABOVE_32
	mov	r4, r0
	mov	r0, fp
	bl	MASK_OUT_ABOVE_32
	b	.L41
.L47:
	rsb	r0, r4, #0
	bl	MASK_OUT_ABOVE_32
	mov	r4, r0
	rsb	r0, r8, #0
	bl	MASK_OUT_ABOVE_32
	mov	r8, r0
	b	.L14
.L44:
	mov	r0, #0
	mov	r2, #-2147483648
	ldr	r3, [r9]
	ldr	ip, [sp, #4]
	ldr	r1, .L48+8
	str	r0, [r3, ip, lsl #2]
	str	r2, [r3, r7, lsl #2]
	ldr	r1, [r1]
	ldr	ip, .L48+12
	ldr	r3, .L48+16
	ldr	r0, .L48+24
	ldr	r2, .L48+32
	ldr	lr, [ip]
	str	r1, [r3]
	ldr	r0, [r0]
	ldr	r2, [r2]
	ldr	ip, .L48+20
	ldr	r1, .L48+28
	ldr	r3, .L48+36
	str	lr, [ip]
	str	r0, [r1]
	str	r2, [r3]
	b	.L1
.L49:
	.align	2
.L48:
	.word	CPU_TYPE
	.word	REG_D
	.word	NFLAG_SET
	.word	ZFLAG_CLEAR
	.word	FLAG_N
	.word	FLAG_Z
	.word	VFLAG_CLEAR
	.word	FLAG_V
	.word	CFLAG_CLEAR
	.word	FLAG_C
	.word	EXCEPTION_ZERO_DIVIDE
	.word	VFLAG_SET
	.size	m68k_op_divl_32_i, .-m68k_op_divl_32_i
	.comm	ZFLAG_CLEAR,4,4
	.comm	VFLAG_SET,4,4
	.comm	VFLAG_CLEAR,4,4
	.comm	REG_D,4,4
	.comm	NFLAG_SET,4,4
	.comm	FLAG_Z,4,4
	.comm	FLAG_V,4,4
	.comm	FLAG_N,4,4
	.comm	FLAG_C,4,4
	.comm	EXCEPTION_ZERO_DIVIDE,4,4
	.comm	CPU_TYPE,4,4
	.comm	CFLAG_CLEAR,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
