	.file	"extr_sunxi-mmc.c_sunxi_mmc_clk_set_phase.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Invalid clock... returning\n"
	.text
	.p2align 4
	.type	sunxi_mmc_clk_set_phase, @function
sunxi_mmc_clk_set_phase:
.LFB0:
	.cfi_startproc
	endbr64
	xor	eax, eax
	cmp	QWORD PTR 24[rdi], 0
	jne	.L12
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	mov	rbx, rdi
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	mov	rcx, QWORD PTR [rdi]
	mov	rcx, QWORD PTR [rcx]
	test	rcx, rcx
	je	.L1
	cmp	edx, 400000
	jg	.L3
	movsx	rbp, DWORD PTR SDXC_CLK_400K[rip]
.L4:
	mov	esi, DWORD PTR 4[rcx+rbp*8]
	mov	edi, DWORD PTR 12[rbx]
	call	clk_set_phase@PLT
	mov	rax, QWORD PTR [rbx]
	mov	edi, DWORD PTR 8[rbx]
	mov	rax, QWORD PTR [rax]
	mov	esi, DWORD PTR [rax+rbp*8]
	call	clk_set_phase@PLT
	xor	eax, eax
.L1:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L3:
	.cfi_restore_state
	cmp	edx, 25000000
	jle	.L16
	cmp	edx, 52000000
	jg	.L6
	mov	rax, QWORD PTR [rsi]
	cmp	rax, QWORD PTR MMC_TIMING_UHS_DDR50[rip]
	je	.L7
	cmp	rax, QWORD PTR MMC_TIMING_MMC_DDR52[rip]
	je	.L7
	movsx	rbp, DWORD PTR SDXC_CLK_50M[rip]
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L12:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	.cfi_restore 6
	ret
	.p2align 4,,10
	.p2align 3
.L16:
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -24
	.cfi_offset 6, -16
	movsx	rbp, DWORD PTR SDXC_CLK_25M[rip]
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L7:
	movsx	rbp, DWORD PTR SDXC_CLK_50M_DDR[rip]
	mov	rax, QWORD PTR MMC_BUS_WIDTH_8[rip]
	cmp	QWORD PTR 8[rsi], rax
	jne	.L4
	movsx	rbp, DWORD PTR SDXC_CLK_50M_DDR_8BIT[rip]
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L6:
	mov	edi, DWORD PTR 16[rdi]
	call	mmc_dev@PLT
	lea	rsi, .LC0[rip]
	mov	edi, eax
	call	dev_dbg@PLT
	mov	eax, DWORD PTR EINVAL[rip]
	neg	eax
	jmp	.L1
	.cfi_endproc
.LFE0:
	.size	sunxi_mmc_clk_set_phase, .-sunxi_mmc_clk_set_phase
	.comm	SDXC_CLK_50M_DDR_8BIT,4,4
	.comm	SDXC_CLK_50M_DDR,4,4
	.comm	SDXC_CLK_50M,4,4
	.comm	SDXC_CLK_400K,4,4
	.comm	SDXC_CLK_25M,4,4
	.comm	MMC_TIMING_UHS_DDR50,8,8
	.comm	MMC_TIMING_MMC_DDR52,8,8
	.comm	MMC_BUS_WIDTH_8,8,8
	.comm	EINVAL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_sunxi-mmc.c_sunxi_mmc_clk_set_phase.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"Invalid clock... returning\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	sunxi_mmc_clk_set_phase, %function
sunxi_mmc_clk_set_phase:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, lr}
	ldr	r5, [r0, #16]
	cmp	r5, #0
	movne	r5, #0
	bne	.L1
	ldr	r3, [r0]
	mov	r4, r0
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L1
	ldr	r0, .L16
	cmp	r2, r0
	bgt	.L3
	ldr	r2, .L16+4
	ldr	r6, [r2]
.L4:
	add	r3, r3, r6, lsl #3
	ldr	r1, [r3, #4]
	ldr	r0, [r4, #8]
	bl	clk_set_phase
	ldr	r3, [r4]
	ldr	r0, [r4, #4]
	ldr	r3, [r3]
	ldr	r1, [r3, r6, lsl #3]
	bl	clk_set_phase
.L1:
	mov	r0, r5
	pop	{r4, r5, r6, pc}
.L3:
	ldr	r0, .L16+8
	cmp	r2, r0
	ble	.L15
	ldr	r0, .L16+12
	cmp	r2, r0
	bgt	.L6
	ldr	r0, .L16+16
	ldr	r2, [r1]
	ldr	r0, [r0]
	cmp	r2, r0
	beq	.L7
	ldr	r0, .L16+20
	ldr	r0, [r0]
	cmp	r2, r0
	beq	.L7
	ldr	r2, .L16+24
	ldr	r6, [r2]
	b	.L4
.L15:
	ldr	r2, .L16+28
	ldr	r6, [r2]
	b	.L4
.L7:
	ldr	r2, .L16+32
	ldr	r1, [r1, #4]
	ldr	r2, [r2]
	cmp	r1, r2
	ldreq	r2, .L16+36
	ldrne	r2, .L16+40
	ldr	r6, [r2]
	b	.L4
.L6:
	ldr	r0, [r4, #12]
	bl	mmc_dev
	ldr	r1, .L16+44
	bl	dev_dbg
	ldr	r3, .L16+48
	ldr	r5, [r3]
	rsb	r5, r5, #0
	b	.L1
.L17:
	.align	2
.L16:
	.word	400000
	.word	SDXC_CLK_400K
	.word	25000000
	.word	52000000
	.word	MMC_TIMING_UHS_DDR50
	.word	MMC_TIMING_MMC_DDR52
	.word	SDXC_CLK_50M
	.word	SDXC_CLK_25M
	.word	MMC_BUS_WIDTH_8
	.word	SDXC_CLK_50M_DDR_8BIT
	.word	SDXC_CLK_50M_DDR
	.word	.LC0
	.word	EINVAL
	.size	sunxi_mmc_clk_set_phase, .-sunxi_mmc_clk_set_phase
	.comm	SDXC_CLK_50M_DDR_8BIT,4,4
	.comm	SDXC_CLK_50M_DDR,4,4
	.comm	SDXC_CLK_50M,4,4
	.comm	SDXC_CLK_400K,4,4
	.comm	SDXC_CLK_25M,4,4
	.comm	MMC_TIMING_UHS_DDR50,4,4
	.comm	MMC_TIMING_MMC_DDR52,4,4
	.comm	MMC_BUS_WIDTH_8,4,4
	.comm	EINVAL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
