	.file	"extr_intel_pm.c_intel_init_clock_gating_hooks.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	intel_init_clock_gating_hooks
	.type	intel_init_clock_gating_hooks, @function
intel_init_clock_gating_hooks:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	mov	esi, 12
	mov	rbx, rdi
	call	IS_GEN@PLT
	test	rax, rax
	je	.L2
.L26:
	mov	rax, QWORD PTR nop_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L2:
	.cfi_restore_state
	mov	esi, 11
	mov	rdi, rbx
	call	IS_GEN@PLT
	test	rax, rax
	je	.L4
	mov	rax, QWORD PTR icl_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L4:
	.cfi_restore_state
	mov	rdi, rbx
	call	IS_CANNONLAKE@PLT
	test	rax, rax
	je	.L5
	mov	rax, QWORD PTR cnl_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L5:
	.cfi_restore_state
	mov	rdi, rbx
	call	IS_COFFEELAKE@PLT
	test	rax, rax
	je	.L6
	mov	rax, QWORD PTR cfl_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L6:
	.cfi_restore_state
	mov	rdi, rbx
	call	IS_SKYLAKE@PLT
	test	rax, rax
	je	.L7
	mov	rax, QWORD PTR skl_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
.L7:
	.cfi_restore_state
	mov	rdi, rbx
	call	IS_KABYLAKE@PLT
	test	rax, rax
	je	.L8
	mov	rax, QWORD PTR kbl_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
.L8:
	.cfi_restore_state
	mov	rdi, rbx
	call	IS_BROXTON@PLT
	test	rax, rax
	je	.L9
	mov	rax, QWORD PTR bxt_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
.L9:
	.cfi_restore_state
	mov	rdi, rbx
	call	IS_GEMINILAKE@PLT
	test	rax, rax
	je	.L10
	mov	rax, QWORD PTR glk_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
.L10:
	.cfi_restore_state
	mov	rdi, rbx
	call	IS_BROADWELL@PLT
	test	rax, rax
	je	.L11
	mov	rax, QWORD PTR bdw_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
.L11:
	.cfi_restore_state
	mov	rdi, rbx
	call	IS_CHERRYVIEW@PLT
	test	rax, rax
	je	.L12
	mov	rax, QWORD PTR chv_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
.L12:
	.cfi_restore_state
	mov	rdi, rbx
	call	IS_HASWELL@PLT
	test	rax, rax
	je	.L13
	mov	rax, QWORD PTR hsw_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
.L13:
	.cfi_restore_state
	mov	rdi, rbx
	call	IS_IVYBRIDGE@PLT
	test	rax, rax
	je	.L14
	mov	rax, QWORD PTR ivb_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
.L14:
	.cfi_restore_state
	mov	rdi, rbx
	call	IS_VALLEYVIEW@PLT
	test	rax, rax
	je	.L15
	mov	rax, QWORD PTR vlv_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
.L15:
	.cfi_restore_state
	mov	esi, 6
	mov	rdi, rbx
	call	IS_GEN@PLT
	test	rax, rax
	je	.L16
	mov	rax, QWORD PTR gen6_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
.L16:
	.cfi_restore_state
	mov	esi, 5
	mov	rdi, rbx
	call	IS_GEN@PLT
	test	rax, rax
	je	.L17
	mov	rax, QWORD PTR ilk_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
.L17:
	.cfi_restore_state
	mov	rdi, rbx
	call	IS_G4X@PLT
	test	rax, rax
	je	.L18
	mov	rax, QWORD PTR g4x_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
.L18:
	.cfi_restore_state
	mov	rdi, rbx
	call	IS_I965GM@PLT
	test	rax, rax
	je	.L19
	mov	rax, QWORD PTR i965gm_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
.L19:
	.cfi_restore_state
	mov	rdi, rbx
	call	IS_I965G@PLT
	test	rax, rax
	je	.L20
	mov	rax, QWORD PTR i965g_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
.L20:
	.cfi_restore_state
	mov	esi, 3
	mov	rdi, rbx
	call	IS_GEN@PLT
	test	rax, rax
	je	.L21
	mov	rax, QWORD PTR gen3_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
.L21:
	.cfi_restore_state
	mov	rdi, rbx
	call	IS_I85X@PLT
	test	rax, rax
	je	.L22
.L23:
	mov	rax, QWORD PTR i85x_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
.L22:
	.cfi_restore_state
	mov	rdi, rbx
	call	IS_I865G@PLT
	test	rax, rax
	jne	.L23
	mov	esi, 2
	mov	rdi, rbx
	call	IS_GEN@PLT
	test	rax, rax
	je	.L24
	mov	rax, QWORD PTR i830_init_clock_gating[rip]
	mov	QWORD PTR [rbx], rax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
.L24:
	.cfi_restore_state
	mov	rdi, rbx
	call	INTEL_DEVID@PLT
	mov	edi, eax
	call	MISSING_CASE@PLT
	jmp	.L26
	.cfi_endproc
.LFE0:
	.size	intel_init_clock_gating_hooks, .-intel_init_clock_gating_hooks
	.comm	vlv_init_clock_gating,8,8
	.comm	skl_init_clock_gating,8,8
	.comm	nop_init_clock_gating,8,8
	.comm	kbl_init_clock_gating,8,8
	.comm	ivb_init_clock_gating,8,8
	.comm	ilk_init_clock_gating,8,8
	.comm	icl_init_clock_gating,8,8
	.comm	i965gm_init_clock_gating,8,8
	.comm	i965g_init_clock_gating,8,8
	.comm	i85x_init_clock_gating,8,8
	.comm	i830_init_clock_gating,8,8
	.comm	hsw_init_clock_gating,8,8
	.comm	glk_init_clock_gating,8,8
	.comm	gen6_init_clock_gating,8,8
	.comm	gen3_init_clock_gating,8,8
	.comm	g4x_init_clock_gating,8,8
	.comm	cnl_init_clock_gating,8,8
	.comm	chv_init_clock_gating,8,8
	.comm	cfl_init_clock_gating,8,8
	.comm	bxt_init_clock_gating,8,8
	.comm	bdw_init_clock_gating,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_intel_pm.c_intel_init_clock_gating_hooks.c"
	.text
	.align	2
	.global	intel_init_clock_gating_hooks
	.syntax unified
	.arm
	.fpu softvfp
	.type	intel_init_clock_gating_hooks, %function
intel_init_clock_gating_hooks:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, lr}
	mov	r1, #12
	mov	r4, r0
	bl	IS_GEN
	cmp	r0, #0
	beq	.L2
.L26:
	ldr	r3, .L28
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L2:
	mov	r1, #11
	mov	r0, r4
	bl	IS_GEN
	cmp	r0, #0
	beq	.L4
	ldr	r3, .L28+4
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L4:
	mov	r0, r4
	bl	IS_CANNONLAKE
	cmp	r0, #0
	beq	.L5
	ldr	r3, .L28+8
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L5:
	mov	r0, r4
	bl	IS_COFFEELAKE
	cmp	r0, #0
	beq	.L6
	ldr	r3, .L28+12
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L6:
	mov	r0, r4
	bl	IS_SKYLAKE
	cmp	r0, #0
	beq	.L7
	ldr	r3, .L28+16
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L7:
	mov	r0, r4
	bl	IS_KABYLAKE
	cmp	r0, #0
	beq	.L8
	ldr	r3, .L28+20
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L8:
	mov	r0, r4
	bl	IS_BROXTON
	cmp	r0, #0
	beq	.L9
	ldr	r3, .L28+24
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L9:
	mov	r0, r4
	bl	IS_GEMINILAKE
	cmp	r0, #0
	beq	.L10
	ldr	r3, .L28+28
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L10:
	mov	r0, r4
	bl	IS_BROADWELL
	cmp	r0, #0
	beq	.L11
	ldr	r3, .L28+32
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L11:
	mov	r0, r4
	bl	IS_CHERRYVIEW
	cmp	r0, #0
	beq	.L12
	ldr	r3, .L28+36
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L12:
	mov	r0, r4
	bl	IS_HASWELL
	cmp	r0, #0
	beq	.L13
	ldr	r3, .L28+40
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L13:
	mov	r0, r4
	bl	IS_IVYBRIDGE
	cmp	r0, #0
	beq	.L14
	ldr	r3, .L28+44
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L14:
	mov	r0, r4
	bl	IS_VALLEYVIEW
	cmp	r0, #0
	beq	.L15
	ldr	r3, .L28+48
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L15:
	mov	r1, #6
	mov	r0, r4
	bl	IS_GEN
	cmp	r0, #0
	beq	.L16
	ldr	r3, .L28+52
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L16:
	mov	r1, #5
	mov	r0, r4
	bl	IS_GEN
	cmp	r0, #0
	beq	.L17
	ldr	r3, .L28+56
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L17:
	mov	r0, r4
	bl	IS_G4X
	cmp	r0, #0
	beq	.L18
	ldr	r3, .L28+60
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L18:
	mov	r0, r4
	bl	IS_I965GM
	cmp	r0, #0
	beq	.L19
	ldr	r3, .L28+64
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L19:
	mov	r0, r4
	bl	IS_I965G
	cmp	r0, #0
	beq	.L20
	ldr	r3, .L28+68
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L20:
	mov	r1, #3
	mov	r0, r4
	bl	IS_GEN
	cmp	r0, #0
	beq	.L21
	ldr	r3, .L28+72
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L21:
	mov	r0, r4
	bl	IS_I85X
	cmp	r0, #0
	beq	.L22
.L23:
	ldr	r3, .L28+76
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L22:
	mov	r0, r4
	bl	IS_I865G
	cmp	r0, #0
	bne	.L23
	mov	r1, #2
	mov	r0, r4
	bl	IS_GEN
	cmp	r0, #0
	beq	.L24
	ldr	r3, .L28+80
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, pc}
.L24:
	mov	r0, r4
	bl	INTEL_DEVID
	bl	MISSING_CASE
	b	.L26
.L29:
	.align	2
.L28:
	.word	nop_init_clock_gating
	.word	icl_init_clock_gating
	.word	cnl_init_clock_gating
	.word	cfl_init_clock_gating
	.word	skl_init_clock_gating
	.word	kbl_init_clock_gating
	.word	bxt_init_clock_gating
	.word	glk_init_clock_gating
	.word	bdw_init_clock_gating
	.word	chv_init_clock_gating
	.word	hsw_init_clock_gating
	.word	ivb_init_clock_gating
	.word	vlv_init_clock_gating
	.word	gen6_init_clock_gating
	.word	ilk_init_clock_gating
	.word	g4x_init_clock_gating
	.word	i965gm_init_clock_gating
	.word	i965g_init_clock_gating
	.word	gen3_init_clock_gating
	.word	i85x_init_clock_gating
	.word	i830_init_clock_gating
	.size	intel_init_clock_gating_hooks, .-intel_init_clock_gating_hooks
	.comm	vlv_init_clock_gating,4,4
	.comm	skl_init_clock_gating,4,4
	.comm	nop_init_clock_gating,4,4
	.comm	kbl_init_clock_gating,4,4
	.comm	ivb_init_clock_gating,4,4
	.comm	ilk_init_clock_gating,4,4
	.comm	icl_init_clock_gating,4,4
	.comm	i965gm_init_clock_gating,4,4
	.comm	i965g_init_clock_gating,4,4
	.comm	i85x_init_clock_gating,4,4
	.comm	i830_init_clock_gating,4,4
	.comm	hsw_init_clock_gating,4,4
	.comm	glk_init_clock_gating,4,4
	.comm	gen6_init_clock_gating,4,4
	.comm	gen3_init_clock_gating,4,4
	.comm	g4x_init_clock_gating,4,4
	.comm	cnl_init_clock_gating,4,4
	.comm	chv_init_clock_gating,4,4
	.comm	cfl_init_clock_gating,4,4
	.comm	bxt_init_clock_gating,4,4
	.comm	bdw_init_clock_gating,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
