	.file	"extr_sparc.c_function_arg.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	function_arg
	.type	function_arg, @function
function_arg:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	mov	r15d, ecx
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	mov	r13, rdi
	mov	edi, esi
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	mov	r12, rdx
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	ebp, esi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	ebx, r8d
	sub	rsp, 40
	.cfi_def_cfa_offset 96
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 24[rsp], rax
	xor	eax, eax
	test	r8d, r8d
	mov	eax, DWORD PTR SPARC_INCOMING_INT_ARG_FIRST[rip]
	mov	DWORD PTR [rsp], esi
	cmove	eax, DWORD PTR SPARC_OUTGOING_INT_ARG_FIRST[rip]
	mov	DWORD PTR 4[rsp], eax
	call	GET_MODE_CLASS@PLT
	sub	rsp, 8
	.cfi_def_cfa_offset 104
	mov	r8d, ebx
	mov	ecx, r15d
	mov	r14d, eax
	lea	rax, 28[rsp]
	mov	rdx, r12
	mov	esi, ebp
	push	rax
	.cfi_def_cfa_offset 112
	mov	rdi, r13
	lea	r9, 32[rsp]
	call	function_arg_slotno@PLT
	pop	rdx
	.cfi_def_cfa_offset 104
	xor	r8d, r8d
	pop	rcx
	.cfi_def_cfa_offset 96
	cmp	eax, -1
	je	.L1
	test	r12, r12
	jne	.L40
	cmp	QWORD PTR TARGET_ARCH32[rip], 0
	jne	.L17
.L16:
	cmp	DWORD PTR MODE_FLOAT[rip], r14d
	je	.L11
	cmp	DWORD PTR MODE_COMPLEX_FLOAT[rip], r14d
	je	.L11
.L12:
	test	r12, r12
	jne	.L41
.L14:
	mov	esi, DWORD PTR 16[rsp]
	mov	edi, DWORD PTR [rsp]
	call	gen_rtx_REG@PLT
	mov	r8d, eax
.L1:
	mov	rax, QWORD PTR 24[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L42
	add	rsp, 40
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	eax, r8d
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L11:
	.cfi_restore_state
	mov	edi, DWORD PTR 16[rsp]
	call	SPARC_FP_REG_P@PLT
	test	rax, rax
	je	.L12
	mov	esi, DWORD PTR 16[rsp]
	mov	edi, ebp
	call	gen_rtx_REG@PLT
	cmp	QWORD PTR 8[r13], 0
	mov	r8d, eax
	jne	.L1
	cmp	QWORD PTR 0[r13], 0
	jne	.L1
	mov	ecx, DWORD PTR SPARC_INT_ARG_MAX[rip]
	mov	eax, DWORD PTR 16[rsp]
	sub	eax, DWORD PTR SPARC_FP_ARG_FIRST[rip]
	lea	edx, [rcx+rcx]
	cmp	eax, edx
	jge	.L13
	test	ebx, ebx
	jne	.L1
	mov	edx, eax
	mov	edi, DWORD PTR VOIDmode[rip]
	mov	esi, r8d
	shr	edx, 31
	add	eax, edx
	mov	edx, DWORD PTR const0_rtx[rip]
	sar	eax
	add	eax, DWORD PTR SPARC_OUTGOING_INT_ARG_FIRST[rip]
	mov	r12d, eax
	call	gen_rtx_EXPR_LIST@PLT
	mov	r14d, DWORD PTR const0_rtx[rip]
	mov	esi, r12d
	mov	edi, ebp
	mov	r13d, eax
	call	gen_rtx_REG@PLT
	mov	edi, DWORD PTR VOIDmode[rip]
	mov	edx, r14d
	mov	esi, eax
	call	gen_rtx_EXPR_LIST@PLT
	mov	esi, r13d
	mov	edx, eax
.L38:
	mov	edi, 2
	call	gen_rtvec@PLT
	mov	edi, ebp
	mov	esi, eax
	call	gen_rtx_PARALLEL@PLT
	mov	r8d, eax
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L40:
	mov	rdi, r12
	mov	DWORD PTR 8[rsp], eax
	call	TREE_CODE@PLT
	cmp	rax, QWORD PTR VECTOR_TYPE[rip]
	mov	edx, DWORD PTR 8[rsp]
	je	.L43
.L6:
	cmp	QWORD PTR TARGET_ARCH32[rip], 0
	jne	.L17
	mov	rdi, r12
	mov	DWORD PTR 8[rsp], edx
	call	TREE_CODE@PLT
	cmp	rax, QWORD PTR RECORD_TYPE[rip]
	mov	edx, DWORD PTR 8[rsp]
	je	.L44
	mov	rdi, r12
	mov	DWORD PTR 4[rsp], edx
	call	TREE_CODE@PLT
	cmp	rax, QWORD PTR UNION_TYPE[rip]
	mov	edx, DWORD PTR 4[rsp]
	jne	.L16
	mov	rdi, r12
	mov	DWORD PTR [rsp], edx
	call	int_size_in_bytes@PLT
	xor	edi, edi
	cmp	eax, 16
	mov	r12d, eax
	setle	dil
	call	gcc_assert@PLT
	mov	ecx, DWORD PTR 16[rsp]
	mov	edx, DWORD PTR [rsp]
	mov	esi, ebp
	mov	edi, r12d
	call	function_arg_union_value@PLT
	mov	r8d, eax
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L17:
	mov	esi, DWORD PTR 16[rsp]
	mov	edi, ebp
	call	gen_rtx_REG@PLT
	mov	r8d, eax
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L41:
	mov	rdi, r12
	call	AGGREGATE_TYPE_P@PLT
	test	rax, rax
	je	.L14
	mov	rdi, r12
	call	int_size_in_bytes@PLT
	xor	edi, edi
	cmp	eax, 16
	mov	ebx, eax
	setle	dil
	call	gcc_assert@PLT
	imul	ebx, DWORD PTR BITS_PER_UNIT[rip]
	mov	esi, DWORD PTR MODE_INT[rip]
	xor	edx, edx
	mov	edi, ebx
	call	mode_for_size@PLT
	mov	DWORD PTR [rsp], eax
	jmp	.L14
	.p2align 4,,10
	.p2align 3
.L43:
	mov	rdi, r12
	call	int_size_in_bytes@PLT
	cmp	QWORD PTR TARGET_ARCH32[rip], 0
	mov	edx, DWORD PTR 8[rsp]
	mov	r8d, eax
	je	.L22
	mov	edi, 1
	cmp	eax, 8
	jle	.L7
.L22:
	cmp	QWORD PTR TARGET_ARCH64[rip], 0
	setne	al
	xor	edi, edi
	cmp	r8d, 16
	setle	dil
	and	edi, eax
.L7:
	mov	DWORD PTR 12[rsp], r8d
	mov	DWORD PTR 8[rsp], edx
	call	gcc_assert@PLT
	cmp	DWORD PTR BLKmode[rip], ebp
	mov	edx, DWORD PTR 8[rsp]
	mov	r14d, DWORD PTR MODE_FLOAT[rip]
	mov	r8d, DWORD PTR 12[rsp]
	jne	.L6
	mov	eax, DWORD PTR SPARC_FP_ARG_FIRST[rip]
	mov	rdi, r12
	mov	DWORD PTR [rsp], r8d
	lea	r13d, [rax+rdx*2]
	call	TREE_TYPE@PLT
	mov	edi, eax
	call	TYPE_MODE@PLT
	mov	r8d, DWORD PTR [rsp]
	mov	edx, r13d
	mov	esi, eax
	mov	edi, r8d
	call	function_arg_vector_value@PLT
	mov	r8d, eax
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L44:
	mov	rdi, r12
	mov	DWORD PTR [rsp], edx
	call	int_size_in_bytes@PLT
	xor	edi, edi
	cmp	eax, 16
	setle	dil
	call	gcc_assert@PLT
	mov	r8d, DWORD PTR 4[rsp]
	mov	edx, DWORD PTR [rsp]
	mov	ecx, r15d
	mov	esi, ebp
	mov	rdi, r12
	call	function_arg_record_value@PLT
	mov	r8d, eax
	jmp	.L1
.L13:
	mov	edx, DWORD PTR const0_rtx[rip]
	mov	esi, DWORD PTR NULL_RTX[rip]
	mov	DWORD PTR [rsp], r8d
	mov	edi, DWORD PTR VOIDmode[rip]
	call	gen_rtx_EXPR_LIST@PLT
	mov	r8d, DWORD PTR [rsp]
	mov	edx, DWORD PTR const0_rtx[rip]
	mov	edi, DWORD PTR VOIDmode[rip]
	mov	r12d, eax
	mov	esi, r8d
	call	gen_rtx_EXPR_LIST@PLT
	mov	esi, r12d
	mov	edx, eax
	jmp	.L38
.L42:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	function_arg, .-function_arg
	.comm	const0_rtx,4,4
	.comm	VOIDmode,4,4
	.comm	VECTOR_TYPE,8,8
	.comm	UNION_TYPE,8,8
	.comm	TARGET_ARCH64,8,8
	.comm	TARGET_ARCH32,8,8
	.comm	SPARC_OUTGOING_INT_ARG_FIRST,4,4
	.comm	SPARC_INT_ARG_MAX,4,4
	.comm	SPARC_INCOMING_INT_ARG_FIRST,4,4
	.comm	SPARC_FP_ARG_FIRST,4,4
	.comm	RECORD_TYPE,8,8
	.comm	NULL_RTX,4,4
	.comm	MODE_INT,4,4
	.comm	MODE_FLOAT,4,4
	.comm	MODE_COMPLEX_FLOAT,4,4
	.comm	BLKmode,4,4
	.comm	BITS_PER_UNIT,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_sparc.c_function_arg.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	function_arg
	.syntax unified
	.arm
	.fpu softvfp
	.type	function_arg, %function
function_arg:
	@ args = 4, pretend = 0, frame = 24
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	mov	r8, r3
	ldr	r3, .L41
	sub	sp, sp, #44
	ldr	r3, [r3]
	str	r3, [sp, #36]
	mov	r3,#0
	ldr	r9, [sp, #80]
	mov	r6, r0
	cmp	r9, #0
	ldrne	r3, .L41+4
	ldreq	r3, .L41+8
	mov	r0, r1
	ldr	r3, [r3]
	mov	r5, r2
	mov	r4, r1
	str	r3, [sp, #16]
	bl	GET_MODE_CLASS
	add	r2, sp, #32
	add	r3, sp, #28
	str	r2, [sp, #8]
	str	r3, [sp, #4]
	mov	r2, r5
	mov	r7, r0
	mov	r3, r8
	mov	r1, r4
	mov	r0, r6
	str	r9, [sp]
	bl	function_arg_slotno
	cmn	r0, #1
	mov	fp, r0
	mov	r10, r4
	moveq	r5, #0
	beq	.L1
	cmp	r5, #0
	bne	.L36
	ldr	r3, .L41+12
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L16
.L15:
	ldr	r3, .L41+16
	ldr	r3, [r3]
	cmp	r3, r7
	beq	.L10
	ldr	r3, .L41+20
	ldr	r3, [r3]
	cmp	r3, r7
	beq	.L10
.L11:
	cmp	r5, #0
	bne	.L37
.L13:
	mov	r0, r10
	ldr	r1, [sp, #28]
	bl	gen_rtx_REG
	mov	r5, r0
.L1:
	ldr	r3, .L41
	ldr	r2, [r3]
	ldr	r3, [sp, #36]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L38
	mov	r0, r5
	add	sp, sp, #44
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L10:
	ldr	r0, [sp, #28]
	bl	SPARC_FP_REG_P
	cmp	r0, #0
	beq	.L11
	mov	r0, r4
	ldr	r1, [sp, #28]
	bl	gen_rtx_REG
	ldr	r3, [r6, #4]
	mov	r5, r0
	cmp	r3, #0
	bne	.L1
	ldr	r3, [r6]
	cmp	r3, #0
	bne	.L1
	ldr	r3, .L41+24
	ldr	r2, .L41+28
	ldr	r1, [r3]
	ldr	r3, [sp, #28]
	ldr	r2, [r2]
	sub	r3, r3, r1
	cmp	r3, r2, lsl #1
	bge	.L12
	cmp	r9, #0
	bne	.L1
	ldr	r2, .L41+8
	ldr	r7, .L41+32
	ldr	r8, .L41+36
	ldr	r6, [r2]
	add	r3, r3, r3, lsr #31
	mov	r1, r0
	ldr	r2, [r7]
	ldr	r0, [r8]
	add	r6, r6, r3, asr #1
	bl	gen_rtx_EXPR_LIST
	mov	r1, r6
	mov	r5, r0
	mov	r0, r4
	ldr	r6, [r8]
	bl	gen_rtx_REG
	ldr	r2, [r7]
	mov	r1, r0
	mov	r0, r6
	bl	gen_rtx_EXPR_LIST
	mov	r1, r5
	mov	r2, r0
.L34:
	mov	r0, #2
	bl	gen_rtvec
	mov	r1, r0
	mov	r0, r4
	bl	gen_rtx_PARALLEL
	mov	r5, r0
	b	.L1
.L36:
	mov	r0, r5
	bl	TREE_CODE
	ldr	r3, .L41+40
	ldr	r3, [r3]
	cmp	r0, r3
	beq	.L31
	ldr	r3, .L41+12
.L6:
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L16
	mov	r0, r5
	bl	TREE_CODE
	ldr	r3, .L41+44
	ldr	r3, [r3]
	cmp	r0, r3
	mov	r0, r5
	beq	.L39
	bl	TREE_CODE
	ldr	r3, .L41+48
	ldr	r3, [r3]
	cmp	r0, r3
	bne	.L15
	mov	r0, r5
	bl	int_size_in_bytes
	mov	r5, r0
	cmp	r0, #16
	movgt	r0, #0
	movle	r0, #1
	bl	gcc_assert
	mov	r0, r5
	mov	r2, fp
	mov	r1, r4
	ldr	r3, [sp, #28]
	bl	function_arg_union_value
	mov	r5, r0
	b	.L1
.L16:
	mov	r0, r4
	ldr	r1, [sp, #28]
	bl	gen_rtx_REG
	mov	r5, r0
	b	.L1
.L37:
	mov	r0, r5
	bl	AGGREGATE_TYPE_P
	cmp	r0, #0
	beq	.L13
	mov	r0, r5
	bl	int_size_in_bytes
	mov	r4, r0
	cmp	r0, #16
	movgt	r0, #0
	movle	r0, #1
	bl	gcc_assert
	ldr	r2, .L41+52
	ldr	r3, .L41+56
	ldr	r0, [r2]
	ldr	r1, [r3]
	mov	r2, #0
	mul	r0, r4, r0
	bl	mode_for_size
	mov	r10, r0
	b	.L13
.L31:
	mov	r0, r5
	bl	int_size_in_bytes
	ldr	r3, .L41+12
	cmp	r0, #8
	mov	r7, r0
	ldr	r0, [r3]
	movgt	r1, #0
	movle	r1, #1
	cmp	r0, #0
	moveq	r1, #0
	cmp	r1, #0
	movne	r0, #1
	bne	.L7
	ldr	r1, .L41+60
	cmp	r7, #16
	ldr	r1, [r1]
	movgt	r0, #0
	movle	r0, #1
	cmp	r1, #0
	moveq	r0, #0
.L7:
	str	r3, [sp, #20]
	bl	gcc_assert
	ldr	r1, .L41+64
	ldr	r3, [sp, #20]
	ldr	r1, [r1]
	cmp	r1, r4
	beq	.L40
	ldr	r1, .L41+16
	ldr	r7, [r1]
	b	.L6
.L39:
	bl	int_size_in_bytes
	cmp	r0, #16
	movgt	r0, #0
	movle	r0, #1
	bl	gcc_assert
	ldr	r3, [sp, #16]
	mov	r0, r5
	str	r3, [sp]
	mov	r2, fp
	mov	r3, r8
	mov	r1, r4
	bl	function_arg_record_value
	mov	r5, r0
	b	.L1
.L40:
	mov	r0, r5
	bl	TREE_TYPE
	bl	TYPE_MODE
	ldr	r3, .L41+24
	mov	r1, r0
	ldr	r2, [r3]
	mov	r0, r7
	add	r2, r2, fp, lsl #1
	bl	function_arg_vector_value
	mov	r5, r0
	b	.L1
.L12:
	ldr	r6, .L41+32
	ldr	r3, .L41+68
	ldr	r7, .L41+36
	ldr	r2, [r6]
	ldr	r1, [r3]
	ldr	r0, [r7]
	bl	gen_rtx_EXPR_LIST
	ldr	r2, [r6]
	mov	r1, r5
	mov	r6, r0
	ldr	r0, [r7]
	bl	gen_rtx_EXPR_LIST
	mov	r1, r6
	mov	r2, r0
	b	.L34
.L38:
	bl	__stack_chk_fail
.L42:
	.align	2
.L41:
	.word	.LC0
	.word	SPARC_INCOMING_INT_ARG_FIRST
	.word	SPARC_OUTGOING_INT_ARG_FIRST
	.word	TARGET_ARCH32
	.word	MODE_FLOAT
	.word	MODE_COMPLEX_FLOAT
	.word	SPARC_FP_ARG_FIRST
	.word	SPARC_INT_ARG_MAX
	.word	const0_rtx
	.word	VOIDmode
	.word	VECTOR_TYPE
	.word	RECORD_TYPE
	.word	UNION_TYPE
	.word	BITS_PER_UNIT
	.word	MODE_INT
	.word	TARGET_ARCH64
	.word	BLKmode
	.word	NULL_RTX
	.size	function_arg, .-function_arg
	.comm	const0_rtx,4,4
	.comm	VOIDmode,4,4
	.comm	VECTOR_TYPE,4,4
	.comm	UNION_TYPE,4,4
	.comm	TARGET_ARCH64,4,4
	.comm	TARGET_ARCH32,4,4
	.comm	SPARC_OUTGOING_INT_ARG_FIRST,4,4
	.comm	SPARC_INT_ARG_MAX,4,4
	.comm	SPARC_INCOMING_INT_ARG_FIRST,4,4
	.comm	SPARC_FP_ARG_FIRST,4,4
	.comm	RECORD_TYPE,4,4
	.comm	NULL_RTX,4,4
	.comm	MODE_INT,4,4
	.comm	MODE_FLOAT,4,4
	.comm	MODE_COMPLEX_FLOAT,4,4
	.comm	BLKmode,4,4
	.comm	BITS_PER_UNIT,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
