	.file	"extr_eeprom_def.c_ath9k_hw_def_set_board_values.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	ath9k_hw_def_set_board_values, @function
ath9k_hw_def_set_board_values:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	lea	rax, 8[rdi]
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	mov	r14, rsi
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 40
	.cfi_def_cfa_offset 96
	mov	rbx, QWORD PTR 24[rdi]
	mov	rdi, rsi
	mov	QWORD PTR 24[rsp], rsi
	mov	QWORD PTR 16[rsp], rax
	call	IS_CHAN_2GHZ@PLT
	mov	rdi, r14
	cdqe
	lea	rdx, [rax+rax*2]
	lea	rax, [rax+rdx*4]
	lea	rbx, [rbx+rax*8]
	call	IS_CHAN_2GHZ@PLT
	mov	edi, DWORD PTR 96[rbx]
	cmp	eax, 1
	sbb	r14d, r14d
	call	le32_to_cpu@PLT
	mov	rsi, QWORD PTR AR_PHY_SWITCH_COM[rip]
	mov	rdi, rbp
	and	r14d, 21
	movzx	edx, ax
	add	r14d, 23
	call	REG_WRITE@PLT
	mov	eax, DWORD PTR AR5416_MAX_CHAINS[rip]
	test	eax, eax
	jle	.L6
	mov	rdi, rbp
	xor	r12d, r12d
	xor	r15d, r15d
	call	AR_SREV_9280@PLT
.L30:
	cmp	DWORD PTR 0[rbp], 5
	je	.L8
	cmp	DWORD PTR 4[rbp], 5
	je	.L8
.L9:
	mov	r8d, r15d
	sal	r8d, 12
	movsx	r13, r8d
.L10:
	mov	rax, QWORD PTR 88[rbx]
	mov	DWORD PTR 12[rsp], r8d
	mov	edi, DWORD PTR [rax+r12]
	call	le32_to_cpu@PLT
	mov	rsi, QWORD PTR AR_PHY_SWITCH_CHAIN_0[rip]
	mov	rdi, rbp
	mov	edx, eax
	add	rsi, r13
	call	REG_WRITE@PLT
	xor	edi, edi
	call	AR_PHY_TIMING_CTRL4@PLT
	mov	rdi, rbp
	lea	rsi, [rax+r13]
	call	REG_READ@PLT
	mov	esi, DWORD PTR AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF[rip]
	mov	r10d, eax
	mov	eax, DWORD PTR AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF[rip]
	or	eax, esi
	not	eax
	and	eax, r10d
	mov	DWORD PTR 4[rsp], eax
	mov	rax, QWORD PTR 80[rbx]
	mov	edi, DWORD PTR [rax+r12]
	call	SM@PLT
	mov	esi, DWORD PTR AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF[rip]
	mov	DWORD PTR 8[rsp], eax
	mov	rax, QWORD PTR 72[rbx]
	mov	edi, DWORD PTR [rax+r12]
	call	SM@PLT
	mov	edx, DWORD PTR 8[rsp]
	xor	edi, edi
	or	edx, eax
	or	edx, DWORD PTR 4[rsp]
	mov	DWORD PTR 4[rsp], edx
	call	AR_PHY_TIMING_CTRL4@PLT
	mov	edx, DWORD PTR 4[rsp]
	mov	rdi, rbp
	lea	rsi, [rax+r13]
	call	REG_WRITE@PLT
	mov	r8d, DWORD PTR 12[rsp]
	mov	r9d, r15d
	mov	ecx, r14d
	mov	rdx, QWORD PTR 16[rsp]
	mov	rsi, rbx
	mov	rdi, rbp
	add	r15d, 1
	call	ath9k_hw_def_set_gain@PLT
	cmp	DWORD PTR AR5416_MAX_CHAINS[rip], r15d
	jle	.L6
	mov	rdi, rbp
	add	r12, 4
	call	AR_SREV_9280@PLT
	test	rax, rax
	je	.L30
	cmp	r15d, 1
	jle	.L30
.L6:
	mov	rdi, rbp
	call	AR_SREV_9280_20_OR_LATER@PLT
	test	rax, rax
	jne	.L44
.L5:
	mov	ecx, DWORD PTR 24[rbx]
	mov	edx, DWORD PTR AR_PHY_SETTLING_SWITCH[rip]
	mov	rdi, rbp
	mov	esi, DWORD PTR AR_PHY_SETTLING[rip]
	call	REG_RMW_FIELD@PLT
	mov	ecx, DWORD PTR 28[rbx]
	mov	edx, DWORD PTR AR_PHY_DESIRED_SZ_ADC[rip]
	mov	rdi, rbp
	mov	esi, DWORD PTR AR_PHY_DESIRED_SZ[rip]
	call	REG_RMW_FIELD@PLT
	mov	rdi, rbp
	call	AR_SREV_9280_20_OR_LATER@PLT
	test	rax, rax
	je	.L45
.L14:
	mov	edi, DWORD PTR 64[rbx]
	mov	esi, DWORD PTR AR_PHY_RF_CTL4_TX_END_XPAA_OFF[rip]
	call	SM@PLT
	mov	edi, DWORD PTR 64[rbx]
	mov	esi, DWORD PTR AR_PHY_RF_CTL4_TX_END_XPAB_OFF[rip]
	mov	r12d, eax
	call	SM@PLT
	mov	edi, DWORD PTR 60[rbx]
	mov	esi, DWORD PTR AR_PHY_RF_CTL4_FRAME_XPAA_ON[rip]
	or	r12d, eax
	call	SM@PLT
	mov	edi, DWORD PTR 60[rbx]
	mov	esi, DWORD PTR AR_PHY_RF_CTL4_FRAME_XPAB_ON[rip]
	or	r12d, eax
	call	SM@PLT
	mov	rsi, QWORD PTR AR_PHY_RF_CTL4[rip]
	mov	edx, r12d
	mov	rdi, rbp
	or	edx, eax
	call	REG_WRITE@PLT
	mov	ecx, DWORD PTR 36[rbx]
	mov	edx, DWORD PTR AR_PHY_TX_END_TO_A2_RX_ON[rip]
	mov	rdi, rbp
	mov	esi, DWORD PTR AR_PHY_RF_CTL3[rip]
	call	REG_RMW_FIELD@PLT
	mov	rdi, rbp
	call	AR_SREV_9280_20_OR_LATER@PLT
	mov	ecx, DWORD PTR 40[rbx]
	test	rax, rax
	je	.L15
	mov	edx, DWORD PTR AR9280_PHY_CCA_THRESH62[rip]
	mov	esi, DWORD PTR AR_PHY_CCA[rip]
	mov	rdi, rbp
	call	REG_RMW_FIELD@PLT
	mov	ecx, DWORD PTR 40[rbx]
	mov	edx, DWORD PTR AR_PHY_EXT_CCA0_THRESH62[rip]
	mov	rdi, rbp
	mov	esi, DWORD PTR AR_PHY_EXT_CCA0[rip]
	call	REG_RMW_FIELD@PLT
.L16:
	mov	rdi, rbp
	call	ath9k_hw_def_get_eeprom_rev@PLT
	cmp	rax, QWORD PTR AR5416_EEP_MINOR_VER_2[rip]
	jge	.L46
.L17:
	mov	rdi, rbp
	call	ath9k_hw_def_get_eeprom_rev@PLT
	cmp	rax, QWORD PTR AR5416_EEP_MINOR_VER_3[rip]
	jge	.L47
.L19:
	mov	rdi, rbp
	call	AR_SREV_9280_20_OR_LATER@PLT
	test	rax, rax
	jne	.L48
.L22:
	mov	rdi, rbp
	call	AR_SREV_9280_20@PLT
	test	rax, rax
	jne	.L49
.L1:
	add	rsp, 40
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L8:
	.cfi_restore_state
	test	r15d, r15d
	je	.L9
	cmp	r15d, 1
	mov	eax, 8192
	mov	r13d, 4096
	mov	r8d, 4096
	cmove	r13, rax
	cmove	r8d, eax
	jmp	.L10
	.p2align 4,,10
	.p2align 3
.L15:
	mov	edx, DWORD PTR AR_PHY_CCA_THRESH62[rip]
	mov	esi, DWORD PTR AR_PHY_CCA[rip]
	mov	rdi, rbp
	call	REG_RMW_FIELD@PLT
	mov	ecx, DWORD PTR 40[rbx]
	mov	edx, DWORD PTR AR_PHY_EXT_CCA_THRESH62[rip]
	mov	rdi, rbp
	mov	esi, DWORD PTR AR_PHY_EXT_CCA[rip]
	call	REG_RMW_FIELD@PLT
	jmp	.L16
	.p2align 4,,10
	.p2align 3
.L44:
	mov	rdi, QWORD PTR 24[rsp]
	call	IS_CHAN_2GHZ@PLT
	mov	r8d, DWORD PTR [rbx]
	test	eax, eax
	jne	.L50
	mov	ecx, DWORD PTR AR_AN_RF5G1_CH0_OB5_S[rip]
	mov	edx, DWORD PTR AR_AN_RF5G1_CH0_OB5[rip]
	mov	rdi, rbp
	mov	esi, DWORD PTR AR_AN_RF5G1_CH0[rip]
	call	ath9k_hw_analog_shift_rmw@PLT
	mov	r8d, DWORD PTR 4[rbx]
	mov	rdi, rbp
	mov	ecx, DWORD PTR AR_AN_RF5G1_CH0_DB5_S[rip]
	mov	edx, DWORD PTR AR_AN_RF5G1_CH0_DB5[rip]
	mov	esi, DWORD PTR AR_AN_RF5G1_CH0[rip]
	call	ath9k_hw_analog_shift_rmw@PLT
	mov	r8d, DWORD PTR 8[rbx]
	mov	rdi, rbp
	mov	ecx, DWORD PTR AR_AN_RF5G1_CH1_OB5_S[rip]
	mov	edx, DWORD PTR AR_AN_RF5G1_CH1_OB5[rip]
	mov	esi, DWORD PTR AR_AN_RF5G1_CH1[rip]
	call	ath9k_hw_analog_shift_rmw@PLT
	mov	r8d, DWORD PTR 12[rbx]
	mov	rdi, rbp
	mov	ecx, DWORD PTR AR_AN_RF5G1_CH1_DB5_S[rip]
	mov	edx, DWORD PTR AR_AN_RF5G1_CH1_DB5[rip]
	mov	esi, DWORD PTR AR_AN_RF5G1_CH1[rip]
	call	ath9k_hw_analog_shift_rmw@PLT
.L13:
	mov	r8d, DWORD PTR 16[rbx]
	mov	ecx, DWORD PTR AR_AN_TOP2_XPABIAS_LVL_S[rip]
	mov	rdi, rbp
	mov	edx, DWORD PTR AR_AN_TOP2_XPABIAS_LVL[rip]
	mov	esi, DWORD PTR AR_AN_TOP2[rip]
	call	ath9k_hw_analog_shift_rmw@PLT
	mov	eax, DWORD PTR 20[rbx]
	xor	r8d, r8d
	mov	rdi, rbp
	test	DWORD PTR LNA_CTL_LOCAL_BIAS[rip], eax
	mov	ecx, DWORD PTR AR_AN_TOP2_LOCALBIAS_S[rip]
	mov	edx, DWORD PTR AR_AN_TOP2_LOCALBIAS[rip]
	mov	esi, DWORD PTR AR_AN_TOP2[rip]
	setne	r8b
	call	ath9k_hw_analog_shift_rmw@PLT
	mov	eax, DWORD PTR 20[rbx]
	xor	ecx, ecx
	mov	edx, DWORD PTR AR_PHY_FORCE_XPA_CFG[rip]
	test	DWORD PTR LNA_CTL_FORCE_XPA[rip], eax
	mov	esi, DWORD PTR AR_PHY_XPA_CFG[rip]
	mov	rdi, rbp
	setne	cl
	call	REG_RMW_FIELD@PLT
	jmp	.L5
	.p2align 4,,10
	.p2align 3
.L49:
	mov	rdi, rbp
	call	ath9k_hw_def_get_eeprom_rev@PLT
	cmp	rax, QWORD PTR AR5416_EEP_MINOR_VER_20[rip]
	jl	.L1
	mov	rdi, QWORD PTR 24[rsp]
	call	IS_CHAN_2GHZ@PLT
	test	eax, eax
	jne	.L51
	cmp	QWORD PTR 16[rbp], 0
	mov	edx, DWORD PTR AR_AN_TOP1_DACIPMODE[rip]
	mov	esi, DWORD PTR AR_AN_TOP1[rip]
	jne	.L52
	mov	ecx, DWORD PTR 8[rbp]
	mov	rdi, rbp
	call	REG_RMW_FIELD@PLT
.L28:
	mov	edi, 100
	call	udelay@PLT
	mov	ecx, DWORD PTR 56[rbx]
	mov	edx, DWORD PTR AR_PHY_FRAME_CTL_TX_CLIP[rip]
	mov	rdi, rbp
	mov	esi, DWORD PTR AR_PHY_FRAME_CTL[rip]
	sar	ecx, 2
	call	REG_RMW_FIELD@PLT
	mov	ecx, DWORD PTR 12[rbp]
	mov	edx, DWORD PTR AR_PHY_TX_DESIRED_SCALE_CCK[rip]
	mov	rdi, rbp
	mov	esi, DWORD PTR AR_PHY_TX_PWRCTRL9[rip]
	add	rsp, 40
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	jmp	REG_RMW_FIELD@PLT
	.p2align 4,,10
	.p2align 3
.L48:
	.cfi_restore_state
	mov	rdi, rbp
	call	ath9k_hw_def_get_eeprom_rev@PLT
	cmp	rax, QWORD PTR AR5416_EEP_MINOR_VER_19[rip]
	jl	.L22
	mov	ecx, DWORD PTR 56[rbx]
	mov	edx, DWORD PTR AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK[rip]
	mov	rdi, rbp
	mov	esi, DWORD PTR AR_PHY_CCK_TX_CTRL[rip]
	call	REG_RMW_FIELD@PLT
	jmp	.L22
	.p2align 4,,10
	.p2align 3
.L47:
	mov	rdi, QWORD PTR 24[rsp]
	call	IS_CHAN_HT40@PLT
	test	rax, rax
	je	.L19
	mov	ecx, DWORD PTR 52[rbx]
	mov	edx, DWORD PTR AR_PHY_SETTLING_SWITCH[rip]
	mov	rdi, rbp
	mov	esi, DWORD PTR AR_PHY_SETTLING[rip]
	call	REG_RMW_FIELD@PLT
	jmp	.L19
	.p2align 4,,10
	.p2align 3
.L46:
	mov	ecx, DWORD PTR 44[rbx]
	mov	edx, DWORD PTR AR_PHY_TX_END_DATA_START[rip]
	mov	rdi, rbp
	mov	esi, DWORD PTR AR_PHY_RF_CTL2[rip]
	call	REG_RMW_FIELD@PLT
	mov	ecx, DWORD PTR 48[rbx]
	mov	edx, DWORD PTR AR_PHY_TX_END_PA_ON[rip]
	mov	rdi, rbp
	mov	esi, DWORD PTR AR_PHY_RF_CTL2[rip]
	call	REG_RMW_FIELD@PLT
	jmp	.L17
	.p2align 4,,10
	.p2align 3
.L45:
	mov	ecx, DWORD PTR 32[rbx]
	mov	edx, DWORD PTR AR_PHY_DESIRED_SZ_PGA[rip]
	mov	rdi, rbp
	mov	esi, DWORD PTR AR_PHY_DESIRED_SZ[rip]
	call	REG_RMW_FIELD@PLT
	jmp	.L14
	.p2align 4,,10
	.p2align 3
.L50:
	mov	ecx, DWORD PTR AR_AN_RF2G1_CH0_OB_S[rip]
	mov	edx, DWORD PTR AR_AN_RF2G1_CH0_OB[rip]
	mov	rdi, rbp
	mov	esi, DWORD PTR AR_AN_RF2G1_CH0[rip]
	call	ath9k_hw_analog_shift_rmw@PLT
	mov	r8d, DWORD PTR 4[rbx]
	mov	rdi, rbp
	mov	ecx, DWORD PTR AR_AN_RF2G1_CH0_DB_S[rip]
	mov	edx, DWORD PTR AR_AN_RF2G1_CH0_DB[rip]
	mov	esi, DWORD PTR AR_AN_RF2G1_CH0[rip]
	call	ath9k_hw_analog_shift_rmw@PLT
	mov	r8d, DWORD PTR 8[rbx]
	mov	rdi, rbp
	mov	ecx, DWORD PTR AR_AN_RF2G1_CH1_OB_S[rip]
	mov	edx, DWORD PTR AR_AN_RF2G1_CH1_OB[rip]
	mov	esi, DWORD PTR AR_AN_RF2G1_CH1[rip]
	call	ath9k_hw_analog_shift_rmw@PLT
	mov	r8d, DWORD PTR 12[rbx]
	mov	rdi, rbp
	mov	ecx, DWORD PTR AR_AN_RF2G1_CH1_DB_S[rip]
	mov	edx, DWORD PTR AR_AN_RF2G1_CH1_DB[rip]
	mov	esi, DWORD PTR AR_AN_RF2G1_CH1[rip]
	call	ath9k_hw_analog_shift_rmw@PLT
	jmp	.L13
.L52:
	xor	ecx, ecx
	mov	rdi, rbp
	call	REG_RMW_FIELD@PLT
	jmp	.L28
.L51:
	mov	ecx, DWORD PTR 8[rbp]
	mov	edx, DWORD PTR AR_AN_TOP1_DACIPMODE[rip]
	mov	rdi, rbp
	mov	esi, DWORD PTR AR_AN_TOP1[rip]
	call	REG_RMW_FIELD@PLT
	jmp	.L28
	.cfi_endproc
.LFE0:
	.size	ath9k_hw_def_set_board_values, .-ath9k_hw_def_set_board_values
	.comm	LNA_CTL_LOCAL_BIAS,4,4
	.comm	LNA_CTL_FORCE_XPA,4,4
	.comm	AR_PHY_XPA_CFG,4,4
	.comm	AR_PHY_TX_PWRCTRL9,4,4
	.comm	AR_PHY_TX_END_TO_A2_RX_ON,4,4
	.comm	AR_PHY_TX_END_PA_ON,4,4
	.comm	AR_PHY_TX_END_DATA_START,4,4
	.comm	AR_PHY_TX_DESIRED_SCALE_CCK,4,4
	.comm	AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,4,4
	.comm	AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,4,4
	.comm	AR_PHY_SWITCH_COM,8,8
	.comm	AR_PHY_SWITCH_CHAIN_0,8,8
	.comm	AR_PHY_SETTLING_SWITCH,4,4
	.comm	AR_PHY_SETTLING,4,4
	.comm	AR_PHY_RF_CTL4_TX_END_XPAB_OFF,4,4
	.comm	AR_PHY_RF_CTL4_TX_END_XPAA_OFF,4,4
	.comm	AR_PHY_RF_CTL4_FRAME_XPAB_ON,4,4
	.comm	AR_PHY_RF_CTL4_FRAME_XPAA_ON,4,4
	.comm	AR_PHY_RF_CTL4,8,8
	.comm	AR_PHY_RF_CTL3,4,4
	.comm	AR_PHY_RF_CTL2,4,4
	.comm	AR_PHY_FRAME_CTL_TX_CLIP,4,4
	.comm	AR_PHY_FRAME_CTL,4,4
	.comm	AR_PHY_FORCE_XPA_CFG,4,4
	.comm	AR_PHY_EXT_CCA_THRESH62,4,4
	.comm	AR_PHY_EXT_CCA0_THRESH62,4,4
	.comm	AR_PHY_EXT_CCA0,4,4
	.comm	AR_PHY_EXT_CCA,4,4
	.comm	AR_PHY_DESIRED_SZ_PGA,4,4
	.comm	AR_PHY_DESIRED_SZ_ADC,4,4
	.comm	AR_PHY_DESIRED_SZ,4,4
	.comm	AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,4,4
	.comm	AR_PHY_CCK_TX_CTRL,4,4
	.comm	AR_PHY_CCA_THRESH62,4,4
	.comm	AR_PHY_CCA,4,4
	.comm	AR_AN_TOP2_XPABIAS_LVL_S,4,4
	.comm	AR_AN_TOP2_XPABIAS_LVL,4,4
	.comm	AR_AN_TOP2_LOCALBIAS_S,4,4
	.comm	AR_AN_TOP2_LOCALBIAS,4,4
	.comm	AR_AN_TOP2,4,4
	.comm	AR_AN_TOP1_DACIPMODE,4,4
	.comm	AR_AN_TOP1,4,4
	.comm	AR_AN_RF5G1_CH1_OB5_S,4,4
	.comm	AR_AN_RF5G1_CH1_OB5,4,4
	.comm	AR_AN_RF5G1_CH1_DB5_S,4,4
	.comm	AR_AN_RF5G1_CH1_DB5,4,4
	.comm	AR_AN_RF5G1_CH1,4,4
	.comm	AR_AN_RF5G1_CH0_OB5_S,4,4
	.comm	AR_AN_RF5G1_CH0_OB5,4,4
	.comm	AR_AN_RF5G1_CH0_DB5_S,4,4
	.comm	AR_AN_RF5G1_CH0_DB5,4,4
	.comm	AR_AN_RF5G1_CH0,4,4
	.comm	AR_AN_RF2G1_CH1_OB_S,4,4
	.comm	AR_AN_RF2G1_CH1_OB,4,4
	.comm	AR_AN_RF2G1_CH1_DB_S,4,4
	.comm	AR_AN_RF2G1_CH1_DB,4,4
	.comm	AR_AN_RF2G1_CH1,4,4
	.comm	AR_AN_RF2G1_CH0_OB_S,4,4
	.comm	AR_AN_RF2G1_CH0_OB,4,4
	.comm	AR_AN_RF2G1_CH0_DB_S,4,4
	.comm	AR_AN_RF2G1_CH0_DB,4,4
	.comm	AR_AN_RF2G1_CH0,4,4
	.comm	AR9280_PHY_CCA_THRESH62,4,4
	.comm	AR5416_MAX_CHAINS,4,4
	.comm	AR5416_EEP_MINOR_VER_3,8,8
	.comm	AR5416_EEP_MINOR_VER_20,8,8
	.comm	AR5416_EEP_MINOR_VER_2,8,8
	.comm	AR5416_EEP_MINOR_VER_19,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_eeprom_def.c_ath9k_hw_def_set_board_values.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	ath9k_hw_def_set_board_values, %function
ath9k_hw_def_set_board_values:
	@ args = 0, pretend = 0, frame = 32
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	mov	r4, r0
	ldr	r7, [r4, #20]
	sub	sp, sp, #44
	mov	r0, r1
	mov	r6, r1
	str	r1, [sp, #28]
	str	r7, [sp, #32]
	bl	IS_CHAN_2GHZ
	add	r5, r0, r0, lsl #1
	rsb	r5, r5, r5, lsl #3
	lsl	r3, r5, #2
	mov	r0, r6
	str	r3, [sp, #36]
	bl	IS_CHAN_2GHZ
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #23
	moveq	r3, #44
	add	r5, r7, r5, lsl #2
	ldr	r0, [r5, #80]
	str	r3, [sp, #20]
	bl	le32_to_cpu
	ldr	r3, .L55
	lsl	r2, r0, #16
	ldr	r10, .L55+4
	ldr	r1, [r3]
	lsr	r2, r2, #16
	mov	r0, r4
	bl	REG_WRITE
	ldr	r3, [r10]
	add	r2, r4, #8
	cmp	r3, #0
	str	r2, [sp, #24]
	ble	.L6
	mov	r0, r4
	bl	AR_SREV_9280
	mov	r6, #0
	ldr	fp, .L55+8
	ldr	r9, .L55+12
.L29:
	ldr	r3, [r4]
	lsl	r8, r6, #12
	cmp	r3, #5
	beq	.L7
	ldr	r3, [r4, #4]
	cmp	r3, #5
	beq	.L7
.L9:
	ldr	r3, [r5, #76]
	ldr	r7, [fp]
	ldr	r0, [r3, r6, lsl #2]
	bl	le32_to_cpu
	add	r7, r8, r7
	mov	r2, r0
	mov	r1, r7
	mov	r0, r4
	bl	REG_WRITE
	mov	r0, #0
	bl	AR_PHY_TIMING_CTRL4
	mov	r3, r0
	mov	r0, #0
	add	r3, r3, r8
	str	r3, [sp, #16]
	bl	AR_PHY_TIMING_CTRL4
	mov	r1, r0
	mov	r0, r4
	add	r1, r1, r8
	bl	REG_READ
	mov	ip, r0
	ldr	r3, .L55+16
	ldr	r2, [r9]
	ldr	r1, [r3]
	ldr	r0, [r5, #72]
	orr	r2, r1, r2
	bic	r3, ip, r2
	ldr	r0, [r0, r6, lsl #2]
	str	r3, [sp, #12]
	bl	SM
	ldr	r2, [r5, #68]
	mov	r7, r0
	ldr	r1, [r9]
	ldr	r0, [r2, r6, lsl #2]
	bl	SM
	ldr	r3, [sp, #12]
	orr	r2, r7, r0
	orr	r2, r2, r3
	ldr	r3, [sp, #16]
	mov	r0, r4
	mov	r1, r3
	bl	REG_WRITE
	ldr	r3, [sp, #20]
	str	r6, [sp, #4]
	mov	r1, r5
	mov	r0, r4
	ldr	r2, [sp, #24]
	str	r8, [sp]
	bl	ath9k_hw_def_set_gain
	ldr	r3, [r10]
	add	r6, r6, #1
	cmp	r3, r6
	ble	.L6
	mov	r0, r4
	bl	AR_SREV_9280
	cmp	r0, #0
	cmpne	r6, #1
	ble	.L29
.L6:
	mov	r0, r4
	bl	AR_SREV_9280_20_OR_LATER
	cmp	r0, #0
	bne	.L47
.L5:
	ldr	r8, .L55+20
	ldr	r7, .L55+24
	ldr	r2, [r8]
	ldr	r1, [r7]
	ldr	r3, [r5, #24]
	mov	r0, r4
	bl	REG_RMW_FIELD
	ldr	r6, .L55+28
	ldr	r3, .L55+32
	ldr	r1, [r6]
	ldr	r2, [r3]
	mov	r0, r4
	ldr	r3, [r5, #28]
	bl	REG_RMW_FIELD
	mov	r0, r4
	bl	AR_SREV_9280_20_OR_LATER
	cmp	r0, #0
	beq	.L48
.L13:
	ldr	r2, .L55+36
	ldr	r3, .L55+40
	ldr	r1, [r2]
	ldr	r0, [r5, #64]
	ldr	r9, [r3]
	bl	SM
	ldr	r3, .L55+44
	mov	r6, r0
	ldr	r1, [r3]
	ldr	r0, [r5, #64]
	bl	SM
	mov	r2, r0
	ldr	r3, .L55+48
	ldr	r0, [r5, #60]
	ldr	r1, [r3]
	orr	r6, r6, r2
	bl	SM
	mov	r2, r0
	ldr	r3, .L55+52
	ldr	r0, [r5, #60]
	ldr	r1, [r3]
	orr	r6, r6, r2
	bl	SM
	mov	r1, r9
	orr	r2, r6, r0
	mov	r0, r4
	bl	REG_WRITE
	ldr	r3, .L55+56
	ldr	r2, .L55+60
	ldr	r1, [r3]
	ldr	r2, [r2]
	ldr	r3, [r5, #36]
	mov	r0, r4
	bl	REG_RMW_FIELD
	mov	r0, r4
	bl	AR_SREV_9280_20_OR_LATER
	cmp	r0, #0
	beq	.L14
	ldr	r3, .L55+64
	ldr	r2, .L55+68
	ldr	r1, [r3]
	ldr	r2, [r2]
	ldr	r3, [r5, #40]
	mov	r0, r4
	bl	REG_RMW_FIELD
	ldr	r2, .L55+72
	ldr	r3, .L55+76
.L44:
	ldr	r1, [r3]
	ldr	r2, [r2]
	ldr	r3, [r5, #40]
	mov	r0, r4
	bl	REG_RMW_FIELD
	mov	r0, r4
	bl	ath9k_hw_def_get_eeprom_rev
	ldr	r3, .L55+80
	ldr	r3, [r3]
	cmp	r0, r3
	bge	.L49
.L16:
	mov	r0, r4
	bl	ath9k_hw_def_get_eeprom_rev
	ldr	r3, .L55+84
	ldr	r3, [r3]
	cmp	r0, r3
	bge	.L50
.L18:
	mov	r0, r4
	bl	AR_SREV_9280_20_OR_LATER
	cmp	r0, #0
	bne	.L51
.L21:
	mov	r0, r4
	bl	AR_SREV_9280_20
	cmp	r0, #0
	bne	.L52
.L1:
	add	sp, sp, #44
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L7:
	cmp	r6, #0
	beq	.L9
	cmp	r6, #1
	moveq	r8, #8192
	movne	r8, #4096
	b	.L9
.L14:
	ldr	r3, .L55+64
	ldr	r2, .L55+88
	ldr	r1, [r3]
	ldr	r2, [r2]
	ldr	r3, [r5, #40]
	mov	r0, r4
	bl	REG_RMW_FIELD
	ldr	r2, .L55+92
	ldr	r3, .L55+96
	b	.L44
.L47:
	ldr	r0, [sp, #28]
	bl	IS_CHAN_2GHZ
	ldr	r3, [sp, #32]
	ldr	r2, [sp, #36]
	cmp	r0, #0
	ldr	r1, [r3, r2]
	bne	.L53
	ldr	r6, .L55+100
	ldr	r3, .L55+104
	ldr	r2, .L55+108
	str	r1, [sp]
	ldr	r1, [r6]
	ldr	r3, [r3]
	ldr	r2, [r2]
	mov	r0, r4
	bl	ath9k_hw_analog_shift_rmw
	ldr	r0, [r5, #4]
	ldr	r3, .L55+112
	ldr	r2, .L55+116
	ldr	r1, [r6]
	ldr	r3, [r3]
	ldr	r2, [r2]
	str	r0, [sp]
	mov	r0, r4
	bl	ath9k_hw_analog_shift_rmw
	ldr	r6, .L55+120
	ldr	r0, [r5, #8]
	ldr	r3, .L55+124
	ldr	r2, .L55+128
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	r1, [r6]
	str	r0, [sp]
	mov	r0, r4
	bl	ath9k_hw_analog_shift_rmw
	ldr	r3, .L55+132
	ldr	r2, .L55+136
.L43:
	ldr	r0, [r5, #12]
	ldr	r1, [r6]
	ldr	r3, [r3]
	ldr	r2, [r2]
	str	r0, [sp]
	mov	r0, r4
	bl	ath9k_hw_analog_shift_rmw
	ldr	r6, .L55+140
	ldr	r0, [r5, #16]
	ldr	r3, .L55+144
	ldr	r2, .L55+148
	ldr	r1, [r6]
	ldr	r3, [r3]
	ldr	r2, [r2]
	str	r0, [sp]
	mov	r0, r4
	bl	ath9k_hw_analog_shift_rmw
	ldr	r3, .L55+152
	ldr	r1, [r5, #20]
	ldr	r2, [r3]
	ldr	r3, .L55+156
	tst	r1, r2
	movne	r0, #1
	moveq	r0, #0
	ldr	r2, .L55+160
	ldr	r1, [r6]
	str	r0, [sp]
	ldr	r3, [r3]
	mov	r0, r4
	ldr	r2, [r2]
	bl	ath9k_hw_analog_shift_rmw
	ldr	r3, .L55+164
	ldr	r0, [r5, #20]
	ldr	r3, [r3]
	ldr	r2, .L55+168
	ldr	r1, .L55+172
	tst	r0, r3
	movne	r3, #1
	moveq	r3, #0
	mov	r0, r4
	ldr	r2, [r2]
	ldr	r1, [r1]
	bl	REG_RMW_FIELD
	b	.L5
.L52:
	mov	r0, r4
	bl	ath9k_hw_def_get_eeprom_rev
	ldr	r3, .L55+176
	ldr	r3, [r3]
	cmp	r0, r3
	blt	.L1
	ldr	r0, [sp, #28]
	bl	IS_CHAN_2GHZ
	subs	r3, r0, #0
	bne	.L54
	ldr	r0, [r4, #16]
	ldr	r1, .L55+180
	ldr	r2, .L55+184
	cmp	r0, #0
	ldr	r1, [r1]
	mov	r0, r4
	ldr	r2, [r2]
	ldreq	r3, [r4, #8]
	bl	REG_RMW_FIELD
.L27:
	mov	r0, #100
	bl	udelay
	ldr	r3, [r5, #56]
	ldr	r2, .L55+188
	ldr	r1, .L55+192
	mov	r0, r4
	ldr	r2, [r2]
	ldr	r1, [r1]
	asr	r3, r3, #2
	bl	REG_RMW_FIELD
	mov	r0, r4
	ldr	r3, .L55+196
	ldr	r2, .L55+200
	ldr	r1, [r3]
	ldr	r2, [r2]
	ldr	r3, [r4, #12]
	add	sp, sp, #44
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	b	REG_RMW_FIELD
.L51:
	mov	r0, r4
	bl	ath9k_hw_def_get_eeprom_rev
	ldr	r3, .L55+204
	ldr	r3, [r3]
	cmp	r0, r3
	blt	.L21
	ldr	r3, .L55+208
	ldr	r2, .L55+212
	ldr	r1, [r3]
	mov	r0, r4
	ldr	r2, [r2]
	ldr	r3, [r5, #56]
	bl	REG_RMW_FIELD
	b	.L21
.L50:
	ldr	r0, [sp, #28]
	bl	IS_CHAN_HT40
	cmp	r0, #0
	beq	.L18
	mov	r0, r4
	ldr	r2, [r8]
	ldr	r1, [r7]
	ldr	r3, [r5, #52]
	bl	REG_RMW_FIELD
	b	.L18
.L49:
	ldr	r6, .L55+216
	ldr	r3, .L55+220
	ldr	r1, [r6]
	ldr	r2, [r3]
	mov	r0, r4
	ldr	r3, [r5, #44]
	bl	REG_RMW_FIELD
	ldr	r3, .L55+224
	mov	r0, r4
	ldr	r2, [r3]
	ldr	r1, [r6]
	ldr	r3, [r5, #48]
	bl	REG_RMW_FIELD
	b	.L16
.L48:
	ldr	r3, .L55+228
	mov	r0, r4
	ldr	r2, [r3]
	ldr	r1, [r6]
	ldr	r3, [r5, #32]
	bl	REG_RMW_FIELD
	b	.L13
.L53:
	ldr	r6, .L55+232
	ldr	r3, .L55+236
	ldr	r2, .L55+240
	str	r1, [sp]
	ldr	r1, [r6]
	ldr	r3, [r3]
	ldr	r2, [r2]
	mov	r0, r4
	bl	ath9k_hw_analog_shift_rmw
	ldr	r0, [r5, #4]
	ldr	r3, .L55+244
	ldr	r2, .L55+248
	ldr	r1, [r6]
	ldr	r3, [r3]
	ldr	r2, [r2]
	str	r0, [sp]
	mov	r0, r4
	bl	ath9k_hw_analog_shift_rmw
	ldr	r6, .L55+252
	ldr	r0, [r5, #8]
	ldr	r3, .L55+256
	ldr	r2, .L55+260
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	r1, [r6]
	str	r0, [sp]
	mov	r0, r4
	bl	ath9k_hw_analog_shift_rmw
	ldr	r3, .L55+264
	ldr	r2, .L55+268
	b	.L43
.L54:
	ldr	r3, .L55+180
	ldr	r2, .L55+184
	ldr	r1, [r3]
	mov	r0, r4
	ldr	r2, [r2]
	ldr	r3, [r4, #8]
	bl	REG_RMW_FIELD
	b	.L27
.L56:
	.align	2
.L55:
	.word	AR_PHY_SWITCH_COM
	.word	AR5416_MAX_CHAINS
	.word	AR_PHY_SWITCH_CHAIN_0
	.word	AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF
	.word	AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF
	.word	AR_PHY_SETTLING_SWITCH
	.word	AR_PHY_SETTLING
	.word	AR_PHY_DESIRED_SZ
	.word	AR_PHY_DESIRED_SZ_ADC
	.word	AR_PHY_RF_CTL4_TX_END_XPAA_OFF
	.word	AR_PHY_RF_CTL4
	.word	AR_PHY_RF_CTL4_TX_END_XPAB_OFF
	.word	AR_PHY_RF_CTL4_FRAME_XPAA_ON
	.word	AR_PHY_RF_CTL4_FRAME_XPAB_ON
	.word	AR_PHY_RF_CTL3
	.word	AR_PHY_TX_END_TO_A2_RX_ON
	.word	AR_PHY_CCA
	.word	AR9280_PHY_CCA_THRESH62
	.word	AR_PHY_EXT_CCA0_THRESH62
	.word	AR_PHY_EXT_CCA0
	.word	AR5416_EEP_MINOR_VER_2
	.word	AR5416_EEP_MINOR_VER_3
	.word	AR_PHY_CCA_THRESH62
	.word	AR_PHY_EXT_CCA_THRESH62
	.word	AR_PHY_EXT_CCA
	.word	AR_AN_RF5G1_CH0
	.word	AR_AN_RF5G1_CH0_OB5_S
	.word	AR_AN_RF5G1_CH0_OB5
	.word	AR_AN_RF5G1_CH0_DB5_S
	.word	AR_AN_RF5G1_CH0_DB5
	.word	AR_AN_RF5G1_CH1
	.word	AR_AN_RF5G1_CH1_OB5_S
	.word	AR_AN_RF5G1_CH1_OB5
	.word	AR_AN_RF5G1_CH1_DB5_S
	.word	AR_AN_RF5G1_CH1_DB5
	.word	AR_AN_TOP2
	.word	AR_AN_TOP2_XPABIAS_LVL_S
	.word	AR_AN_TOP2_XPABIAS_LVL
	.word	LNA_CTL_LOCAL_BIAS
	.word	AR_AN_TOP2_LOCALBIAS_S
	.word	AR_AN_TOP2_LOCALBIAS
	.word	LNA_CTL_FORCE_XPA
	.word	AR_PHY_FORCE_XPA_CFG
	.word	AR_PHY_XPA_CFG
	.word	AR5416_EEP_MINOR_VER_20
	.word	AR_AN_TOP1
	.word	AR_AN_TOP1_DACIPMODE
	.word	AR_PHY_FRAME_CTL_TX_CLIP
	.word	AR_PHY_FRAME_CTL
	.word	AR_PHY_TX_PWRCTRL9
	.word	AR_PHY_TX_DESIRED_SCALE_CCK
	.word	AR5416_EEP_MINOR_VER_19
	.word	AR_PHY_CCK_TX_CTRL
	.word	AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK
	.word	AR_PHY_RF_CTL2
	.word	AR_PHY_TX_END_DATA_START
	.word	AR_PHY_TX_END_PA_ON
	.word	AR_PHY_DESIRED_SZ_PGA
	.word	AR_AN_RF2G1_CH0
	.word	AR_AN_RF2G1_CH0_OB_S
	.word	AR_AN_RF2G1_CH0_OB
	.word	AR_AN_RF2G1_CH0_DB_S
	.word	AR_AN_RF2G1_CH0_DB
	.word	AR_AN_RF2G1_CH1
	.word	AR_AN_RF2G1_CH1_OB_S
	.word	AR_AN_RF2G1_CH1_OB
	.word	AR_AN_RF2G1_CH1_DB_S
	.word	AR_AN_RF2G1_CH1_DB
	.size	ath9k_hw_def_set_board_values, .-ath9k_hw_def_set_board_values
	.comm	LNA_CTL_LOCAL_BIAS,4,4
	.comm	LNA_CTL_FORCE_XPA,4,4
	.comm	AR_PHY_XPA_CFG,4,4
	.comm	AR_PHY_TX_PWRCTRL9,4,4
	.comm	AR_PHY_TX_END_TO_A2_RX_ON,4,4
	.comm	AR_PHY_TX_END_PA_ON,4,4
	.comm	AR_PHY_TX_END_DATA_START,4,4
	.comm	AR_PHY_TX_DESIRED_SCALE_CCK,4,4
	.comm	AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,4,4
	.comm	AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,4,4
	.comm	AR_PHY_SWITCH_COM,4,4
	.comm	AR_PHY_SWITCH_CHAIN_0,4,4
	.comm	AR_PHY_SETTLING_SWITCH,4,4
	.comm	AR_PHY_SETTLING,4,4
	.comm	AR_PHY_RF_CTL4_TX_END_XPAB_OFF,4,4
	.comm	AR_PHY_RF_CTL4_TX_END_XPAA_OFF,4,4
	.comm	AR_PHY_RF_CTL4_FRAME_XPAB_ON,4,4
	.comm	AR_PHY_RF_CTL4_FRAME_XPAA_ON,4,4
	.comm	AR_PHY_RF_CTL4,4,4
	.comm	AR_PHY_RF_CTL3,4,4
	.comm	AR_PHY_RF_CTL2,4,4
	.comm	AR_PHY_FRAME_CTL_TX_CLIP,4,4
	.comm	AR_PHY_FRAME_CTL,4,4
	.comm	AR_PHY_FORCE_XPA_CFG,4,4
	.comm	AR_PHY_EXT_CCA_THRESH62,4,4
	.comm	AR_PHY_EXT_CCA0_THRESH62,4,4
	.comm	AR_PHY_EXT_CCA0,4,4
	.comm	AR_PHY_EXT_CCA,4,4
	.comm	AR_PHY_DESIRED_SZ_PGA,4,4
	.comm	AR_PHY_DESIRED_SZ_ADC,4,4
	.comm	AR_PHY_DESIRED_SZ,4,4
	.comm	AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,4,4
	.comm	AR_PHY_CCK_TX_CTRL,4,4
	.comm	AR_PHY_CCA_THRESH62,4,4
	.comm	AR_PHY_CCA,4,4
	.comm	AR_AN_TOP2_XPABIAS_LVL_S,4,4
	.comm	AR_AN_TOP2_XPABIAS_LVL,4,4
	.comm	AR_AN_TOP2_LOCALBIAS_S,4,4
	.comm	AR_AN_TOP2_LOCALBIAS,4,4
	.comm	AR_AN_TOP2,4,4
	.comm	AR_AN_TOP1_DACIPMODE,4,4
	.comm	AR_AN_TOP1,4,4
	.comm	AR_AN_RF5G1_CH1_OB5_S,4,4
	.comm	AR_AN_RF5G1_CH1_OB5,4,4
	.comm	AR_AN_RF5G1_CH1_DB5_S,4,4
	.comm	AR_AN_RF5G1_CH1_DB5,4,4
	.comm	AR_AN_RF5G1_CH1,4,4
	.comm	AR_AN_RF5G1_CH0_OB5_S,4,4
	.comm	AR_AN_RF5G1_CH0_OB5,4,4
	.comm	AR_AN_RF5G1_CH0_DB5_S,4,4
	.comm	AR_AN_RF5G1_CH0_DB5,4,4
	.comm	AR_AN_RF5G1_CH0,4,4
	.comm	AR_AN_RF2G1_CH1_OB_S,4,4
	.comm	AR_AN_RF2G1_CH1_OB,4,4
	.comm	AR_AN_RF2G1_CH1_DB_S,4,4
	.comm	AR_AN_RF2G1_CH1_DB,4,4
	.comm	AR_AN_RF2G1_CH1,4,4
	.comm	AR_AN_RF2G1_CH0_OB_S,4,4
	.comm	AR_AN_RF2G1_CH0_OB,4,4
	.comm	AR_AN_RF2G1_CH0_DB_S,4,4
	.comm	AR_AN_RF2G1_CH0_DB,4,4
	.comm	AR_AN_RF2G1_CH0,4,4
	.comm	AR9280_PHY_CCA_THRESH62,4,4
	.comm	AR5416_MAX_CHAINS,4,4
	.comm	AR5416_EEP_MINOR_VER_3,4,4
	.comm	AR5416_EEP_MINOR_VER_20,4,4
	.comm	AR5416_EEP_MINOR_VER_2,4,4
	.comm	AR5416_EEP_MINOR_VER_19,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
