	.file	"extr_ni_mio_common.c_ni_set_master_clock.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC0:
	.string	"we don't handle an unspecified clock period correctly yet, returning error\n"
	.text
	.p2align 4
	.type	ni_set_master_clock, @function
ni_set_master_clock:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	mov	r13, rdi
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	mov	ebp, esi
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	sub	rsp, 8
	.cfi_def_cfa_offset 48
	cmp	DWORD PTR NI_MIO_INTERNAL_CLOCK[rip], esi
	mov	rbx, QWORD PTR 8[rdi]
	je	.L11
	cmp	QWORD PTR 16[rbx], 0
	mov	r12d, edx
	jne	.L12
	mov	eax, DWORD PTR EINVAL[rip]
	neg	eax
	cmp	DWORD PTR NI_MIO_RTSI_CLOCK[rip], esi
	je	.L13
.L1:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L13:
	.cfi_restore_state
	mov	esi, DWORD PTR 12[rbx]
	or	esi, DWORD PTR NISTC_RTSI_TRIG_USE_CLK[rip]
	mov	DWORD PTR 12[rbx], esi
	mov	edx, DWORD PTR NISTC_RTSI_TRIG_DIR_REG[rip]
	call	ni_stc_writew@PLT
	test	r12d, r12d
	je	.L14
	mov	DWORD PTR [rbx], r12d
.L9:
	mov	DWORD PTR 8[rbx], ebp
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	eax, 3
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L14:
	.cfi_restore_state
	mov	edi, DWORD PTR 0[r13]
	lea	rsi, .LC0[rip]
	call	dev_err@PLT
	mov	eax, DWORD PTR EINVAL[rip]
	neg	eax
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L12:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	jmp	ni_mseries_set_pll_master_clock@PLT
	.p2align 4,,10
	.p2align 3
.L11:
	.cfi_restore_state
	mov	esi, DWORD PTR NISTC_RTSI_TRIG_USE_CLK[rip]
	mov	edx, DWORD PTR NISTC_RTSI_TRIG_DIR_REG[rip]
	not	esi
	and	esi, DWORD PTR 12[rbx]
	mov	DWORD PTR 12[rbx], esi
	call	ni_stc_writew@PLT
	mov	eax, DWORD PTR TIMEBASE_1_NS[rip]
	cmp	QWORD PTR 16[rbx], 0
	mov	DWORD PTR [rbx], eax
	je	.L9
	mov	esi, DWORD PTR NI_M_CLK_FOUT2_TIMEBASE1_PLL[rip]
	or	esi, DWORD PTR NI_M_CLK_FOUT2_TIMEBASE3_PLL[rip]
	mov	rdi, r13
	not	esi
	and	esi, DWORD PTR 4[rbx]
	mov	edx, DWORD PTR NI_M_CLK_FOUT2_REG[rip]
	mov	DWORD PTR 4[rbx], esi
	call	ni_writew@PLT
	mov	edx, DWORD PTR NI_M_PLL_CTRL_REG[rip]
	xor	esi, esi
	mov	rdi, r13
	call	ni_writew@PLT
	jmp	.L9
	.cfi_endproc
.LFE0:
	.size	ni_set_master_clock, .-ni_set_master_clock
	.comm	TIMEBASE_1_NS,4,4
	.comm	NI_M_PLL_CTRL_REG,4,4
	.comm	NI_M_CLK_FOUT2_TIMEBASE3_PLL,4,4
	.comm	NI_M_CLK_FOUT2_TIMEBASE1_PLL,4,4
	.comm	NI_M_CLK_FOUT2_REG,4,4
	.comm	NI_MIO_RTSI_CLOCK,4,4
	.comm	NI_MIO_INTERNAL_CLOCK,4,4
	.comm	NISTC_RTSI_TRIG_USE_CLK,4,4
	.comm	NISTC_RTSI_TRIG_DIR_REG,4,4
	.comm	EINVAL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_ni_mio_common.c_ni_set_master_clock.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"we don't handle an unspecified clock period correct"
	.ascii	"ly yet, returning error\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	ni_set_master_clock, %function
ni_set_master_clock:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	ldr	r3, .L18
	push	{r4, r5, r6, r7, r8, lr}
	ldr	r3, [r3]
	mov	r4, r1
	cmp	r3, r1
	mov	r5, r0
	ldr	r6, [r0, #4]
	beq	.L13
	ldr	r3, [r6, #16]
	cmp	r3, #0
	bne	.L14
	ldr	r3, .L18+4
	ldr	r8, [r3]
	cmp	r8, r1
	beq	.L15
	ldr	r3, .L18+8
	ldr	r0, [r3]
	rsb	r0, r0, #0
	pop	{r4, r5, r6, r7, r8, pc}
.L15:
	mov	r7, r2
	ldr	r3, .L18+12
	ldr	r1, [r6, #12]
	ldr	r2, [r3]
	ldr	r3, .L18+16
	orr	r1, r1, r2
	str	r1, [r6, #12]
	ldr	r2, [r3]
	bl	ni_stc_writew
	cmp	r7, #0
	beq	.L16
	mov	r0, #3
	str	r7, [r6]
	str	r8, [r6, #8]
	pop	{r4, r5, r6, r7, r8, pc}
.L16:
	ldr	r0, [r5]
	ldr	r1, .L18+20
	bl	dev_err
	ldr	r3, .L18+8
	ldr	r0, [r3]
	rsb	r0, r0, #0
	pop	{r4, r5, r6, r7, r8, pc}
.L14:
	pop	{r4, r5, r6, r7, r8, lr}
	b	ni_mseries_set_pll_master_clock
.L13:
	ldr	r3, .L18+12
	ldr	r1, [r6, #12]
	ldr	r2, [r3]
	ldr	r3, .L18+16
	bic	r1, r1, r2
	str	r1, [r6, #12]
	ldr	r2, [r3]
	bl	ni_stc_writew
	ldr	r3, .L18+24
	ldr	r2, [r6, #16]
	ldr	r3, [r3]
	cmp	r2, #0
	str	r3, [r6]
	bne	.L17
.L3:
	mov	r0, #3
	str	r4, [r6, #8]
	pop	{r4, r5, r6, r7, r8, pc}
.L17:
	ldr	r3, .L18+28
	ldr	r2, .L18+32
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	r1, [r6, #4]
	orr	r3, r3, r2
	ldr	r2, .L18+36
	bic	r1, r1, r3
	str	r1, [r6, #4]
	mov	r0, r5
	ldr	r2, [r2]
	bl	ni_writew
	ldr	r3, .L18+40
	mov	r0, r5
	mov	r1, #0
	ldr	r2, [r3]
	bl	ni_writew
	b	.L3
.L19:
	.align	2
.L18:
	.word	NI_MIO_INTERNAL_CLOCK
	.word	NI_MIO_RTSI_CLOCK
	.word	EINVAL
	.word	NISTC_RTSI_TRIG_USE_CLK
	.word	NISTC_RTSI_TRIG_DIR_REG
	.word	.LC0
	.word	TIMEBASE_1_NS
	.word	NI_M_CLK_FOUT2_TIMEBASE1_PLL
	.word	NI_M_CLK_FOUT2_TIMEBASE3_PLL
	.word	NI_M_CLK_FOUT2_REG
	.word	NI_M_PLL_CTRL_REG
	.size	ni_set_master_clock, .-ni_set_master_clock
	.comm	TIMEBASE_1_NS,4,4
	.comm	NI_M_PLL_CTRL_REG,4,4
	.comm	NI_M_CLK_FOUT2_TIMEBASE3_PLL,4,4
	.comm	NI_M_CLK_FOUT2_TIMEBASE1_PLL,4,4
	.comm	NI_M_CLK_FOUT2_REG,4,4
	.comm	NI_MIO_RTSI_CLOCK,4,4
	.comm	NI_MIO_INTERNAL_CLOCK,4,4
	.comm	NISTC_RTSI_TRIG_USE_CLK,4,4
	.comm	NISTC_RTSI_TRIG_DIR_REG,4,4
	.comm	EINVAL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
