	.file	"extr_pcm_native.c_snd_pcm_hw_constraints_init.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	snd_pcm_hw_constraints_init
	.type	snd_pcm_hw_constraints_init, @function
snd_pcm_hw_constraints_init:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	mov	ebx, DWORD PTR SNDRV_PCM_HW_PARAM_FIRST_MASK[rip]
	cmp	ebx, DWORD PTR SNDRV_PCM_HW_PARAM_LAST_MASK[rip]
	mov	rbp, QWORD PTR [rdi]
	jg	.L2
	.p2align 4,,10
	.p2align 3
.L3:
	mov	esi, ebx
	mov	rdi, rbp
	add	ebx, 1
	call	constrs_mask@PLT
	mov	edi, eax
	call	snd_mask_any@PLT
	cmp	DWORD PTR SNDRV_PCM_HW_PARAM_LAST_MASK[rip], ebx
	jge	.L3
.L2:
	mov	ebx, DWORD PTR SNDRV_PCM_HW_PARAM_FIRST_INTERVAL[rip]
	cmp	ebx, DWORD PTR SNDRV_PCM_HW_PARAM_LAST_INTERVAL[rip]
	jg	.L4
	.p2align 4,,10
	.p2align 3
.L5:
	mov	esi, ebx
	mov	rdi, rbp
	add	ebx, 1
	call	constrs_interval@PLT
	mov	edi, eax
	call	snd_interval_any@PLT
	cmp	DWORD PTR SNDRV_PCM_HW_PARAM_LAST_INTERVAL[rip], ebx
	jge	.L5
.L4:
	mov	esi, DWORD PTR SNDRV_PCM_HW_PARAM_CHANNELS[rip]
	mov	rdi, rbp
	call	constrs_interval@PLT
	mov	edi, eax
	call	snd_interval_setinteger@PLT
	mov	esi, DWORD PTR SNDRV_PCM_HW_PARAM_BUFFER_SIZE[rip]
	mov	rdi, rbp
	call	constrs_interval@PLT
	mov	edi, eax
	call	snd_interval_setinteger@PLT
	mov	esi, DWORD PTR SNDRV_PCM_HW_PARAM_BUFFER_BYTES[rip]
	mov	rdi, rbp
	call	constrs_interval@PLT
	mov	edi, eax
	call	snd_interval_setinteger@PLT
	mov	esi, DWORD PTR SNDRV_PCM_HW_PARAM_SAMPLE_BITS[rip]
	mov	rdi, rbp
	call	constrs_interval@PLT
	mov	edi, eax
	call	snd_interval_setinteger@PLT
	mov	esi, DWORD PTR SNDRV_PCM_HW_PARAM_FRAME_BITS[rip]
	mov	rdi, rbp
	call	constrs_interval@PLT
	mov	edi, eax
	call	snd_interval_setinteger@PLT
	sub	rsp, 8
	.cfi_def_cfa_offset 40
	xor	esi, esi
	mov	rdi, rbp
	push	-1
	.cfi_def_cfa_offset 48
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_SAMPLE_BITS[rip]
	xor	r8d, r8d
	xor	eax, eax
	mov	ecx, DWORD PTR snd_pcm_hw_rule_format[rip]
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_FORMAT[rip]
	call	snd_pcm_hw_rule_add@PLT
	pop	rsi
	.cfi_def_cfa_offset 40
	pop	rdi
	.cfi_def_cfa_offset 32
	test	eax, eax
	js	.L1
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_SAMPLE_BITS[rip]
	push	-1
	.cfi_def_cfa_offset 40
	xor	r8d, r8d
	xor	esi, esi
	mov	ecx, DWORD PTR snd_pcm_hw_rule_sample_bits[rip]
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_FORMAT[rip]
	mov	rdi, rbp
	xor	eax, eax
	push	rdx
	.cfi_def_cfa_offset 48
	call	snd_pcm_hw_rule_add@PLT
	pop	rdx
	.cfi_def_cfa_offset 40
	pop	rcx
	.cfi_def_cfa_offset 32
	test	eax, eax
	js	.L1
	mov	eax, DWORD PTR SNDRV_PCM_HW_PARAM_CHANNELS[rip]
	push	-1
	.cfi_def_cfa_offset 40
	xor	r8d, r8d
	xor	esi, esi
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_FRAME_BITS[rip]
	mov	ecx, DWORD PTR snd_pcm_hw_rule_div[rip]
	mov	rdi, rbp
	push	rax
	.cfi_def_cfa_offset 48
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_SAMPLE_BITS[rip]
	xor	eax, eax
	call	snd_pcm_hw_rule_add@PLT
	pop	r11
	.cfi_def_cfa_offset 40
	pop	rbx
	.cfi_def_cfa_offset 32
	test	eax, eax
	js	.L1
	mov	eax, DWORD PTR SNDRV_PCM_HW_PARAM_CHANNELS[rip]
	push	-1
	.cfi_def_cfa_offset 40
	xor	r8d, r8d
	xor	esi, esi
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_SAMPLE_BITS[rip]
	mov	ecx, DWORD PTR snd_pcm_hw_rule_mul[rip]
	mov	rdi, rbp
	push	rax
	.cfi_def_cfa_offset 48
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_FRAME_BITS[rip]
	xor	eax, eax
	call	snd_pcm_hw_rule_add@PLT
	pop	r9
	.cfi_def_cfa_offset 40
	pop	r10
	.cfi_def_cfa_offset 32
	test	eax, eax
	js	.L1
	mov	eax, DWORD PTR SNDRV_PCM_HW_PARAM_PERIOD_SIZE[rip]
	push	-1
	.cfi_def_cfa_offset 40
	mov	r8d, 8
	xor	esi, esi
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_PERIOD_BYTES[rip]
	mov	ecx, DWORD PTR snd_pcm_hw_rule_mulkdiv[rip]
	mov	rdi, rbp
	push	rax
	.cfi_def_cfa_offset 48
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_FRAME_BITS[rip]
	xor	eax, eax
	call	snd_pcm_hw_rule_add@PLT
	pop	rdi
	.cfi_def_cfa_offset 40
	pop	r8
	.cfi_def_cfa_offset 32
	test	eax, eax
	js	.L1
	mov	eax, DWORD PTR SNDRV_PCM_HW_PARAM_BUFFER_SIZE[rip]
	push	-1
	.cfi_def_cfa_offset 40
	xor	esi, esi
	mov	r8d, 8
	mov	ecx, DWORD PTR snd_pcm_hw_rule_mulkdiv[rip]
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_BUFFER_BYTES[rip]
	mov	rdi, rbp
	push	rax
	.cfi_def_cfa_offset 48
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_FRAME_BITS[rip]
	xor	eax, eax
	call	snd_pcm_hw_rule_add@PLT
	pop	rcx
	.cfi_def_cfa_offset 40
	pop	rsi
	.cfi_def_cfa_offset 32
	test	eax, eax
	js	.L1
	mov	eax, DWORD PTR SNDRV_PCM_HW_PARAM_SAMPLE_BITS[rip]
	push	-1
	.cfi_def_cfa_offset 40
	xor	r8d, r8d
	xor	esi, esi
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_CHANNELS[rip]
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_FRAME_BITS[rip]
	mov	rdi, rbp
	push	rax
	.cfi_def_cfa_offset 48
	mov	ecx, DWORD PTR snd_pcm_hw_rule_div[rip]
	xor	eax, eax
	call	snd_pcm_hw_rule_add@PLT
	pop	rbx
	.cfi_def_cfa_offset 40
	pop	rdx
	.cfi_def_cfa_offset 32
	test	eax, eax
	js	.L1
	mov	eax, DWORD PTR SNDRV_PCM_HW_PARAM_PERIOD_TIME[rip]
	push	-1
	.cfi_def_cfa_offset 40
	mov	r8d, 1000000
	xor	esi, esi
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_PERIOD_SIZE[rip]
	mov	ecx, DWORD PTR snd_pcm_hw_rule_mulkdiv[rip]
	mov	rdi, rbp
	push	rax
	.cfi_def_cfa_offset 48
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_RATE[rip]
	xor	eax, eax
	call	snd_pcm_hw_rule_add@PLT
	pop	r10
	.cfi_def_cfa_offset 40
	pop	r11
	.cfi_def_cfa_offset 32
	test	eax, eax
	js	.L1
	mov	eax, DWORD PTR SNDRV_PCM_HW_PARAM_BUFFER_TIME[rip]
	push	-1
	.cfi_def_cfa_offset 40
	mov	r8d, 1000000
	xor	esi, esi
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_BUFFER_SIZE[rip]
	mov	ecx, DWORD PTR snd_pcm_hw_rule_mulkdiv[rip]
	mov	rdi, rbp
	push	rax
	.cfi_def_cfa_offset 48
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_RATE[rip]
	xor	eax, eax
	call	snd_pcm_hw_rule_add@PLT
	pop	r8
	.cfi_def_cfa_offset 40
	pop	r9
	.cfi_def_cfa_offset 32
	test	eax, eax
	js	.L1
	mov	eax, DWORD PTR SNDRV_PCM_HW_PARAM_PERIOD_SIZE[rip]
	push	-1
	.cfi_def_cfa_offset 40
	xor	esi, esi
	mov	rdi, rbp
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_BUFFER_SIZE[rip]
	mov	ecx, DWORD PTR snd_pcm_hw_rule_div[rip]
	xor	r8d, r8d
	push	rax
	.cfi_def_cfa_offset 48
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_PERIODS[rip]
	xor	eax, eax
	call	snd_pcm_hw_rule_add@PLT
	pop	rsi
	.cfi_def_cfa_offset 40
	pop	rdi
	.cfi_def_cfa_offset 32
	test	eax, eax
	js	.L1
	mov	eax, DWORD PTR SNDRV_PCM_HW_PARAM_PERIODS[rip]
	push	-1
	.cfi_def_cfa_offset 40
	xor	r8d, r8d
	xor	esi, esi
	mov	ecx, DWORD PTR snd_pcm_hw_rule_div[rip]
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_PERIOD_SIZE[rip]
	mov	rdi, rbp
	push	rax
	.cfi_def_cfa_offset 48
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_BUFFER_SIZE[rip]
	xor	eax, eax
	call	snd_pcm_hw_rule_add@PLT
	pop	rdx
	.cfi_def_cfa_offset 40
	pop	rcx
	.cfi_def_cfa_offset 32
	test	eax, eax
	js	.L1
	mov	eax, DWORD PTR SNDRV_PCM_HW_PARAM_FRAME_BITS[rip]
	push	-1
	.cfi_def_cfa_offset 40
	mov	r8d, 8
	xor	esi, esi
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_PERIOD_BYTES[rip]
	mov	ecx, DWORD PTR snd_pcm_hw_rule_mulkdiv[rip]
	mov	rdi, rbp
	push	rax
	.cfi_def_cfa_offset 48
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_PERIOD_SIZE[rip]
	xor	eax, eax
	call	snd_pcm_hw_rule_add@PLT
	pop	r11
	.cfi_def_cfa_offset 40
	pop	rbx
	.cfi_def_cfa_offset 32
	test	eax, eax
	js	.L1
	mov	eax, DWORD PTR SNDRV_PCM_HW_PARAM_RATE[rip]
	push	-1
	.cfi_def_cfa_offset 40
	mov	r8d, 1000000
	xor	esi, esi
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_PERIOD_TIME[rip]
	mov	ecx, DWORD PTR snd_pcm_hw_rule_muldivk[rip]
	mov	rdi, rbp
	push	rax
	.cfi_def_cfa_offset 48
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_PERIOD_SIZE[rip]
	xor	eax, eax
	call	snd_pcm_hw_rule_add@PLT
	pop	r9
	.cfi_def_cfa_offset 40
	pop	r10
	.cfi_def_cfa_offset 32
	test	eax, eax
	js	.L1
	mov	eax, DWORD PTR SNDRV_PCM_HW_PARAM_PERIODS[rip]
	push	-1
	.cfi_def_cfa_offset 40
	xor	r8d, r8d
	mov	rdi, rbp
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_PERIOD_SIZE[rip]
	mov	ecx, DWORD PTR snd_pcm_hw_rule_mul[rip]
	xor	esi, esi
	push	rax
	.cfi_def_cfa_offset 48
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_BUFFER_SIZE[rip]
	xor	eax, eax
	call	snd_pcm_hw_rule_add@PLT
	pop	rdi
	.cfi_def_cfa_offset 40
	pop	r8
	.cfi_def_cfa_offset 32
	test	eax, eax
	js	.L1
	mov	eax, DWORD PTR SNDRV_PCM_HW_PARAM_FRAME_BITS[rip]
	push	-1
	.cfi_def_cfa_offset 40
	xor	esi, esi
	mov	r8d, 8
	mov	ecx, DWORD PTR snd_pcm_hw_rule_mulkdiv[rip]
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_BUFFER_BYTES[rip]
	mov	rdi, rbp
	push	rax
	.cfi_def_cfa_offset 48
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_BUFFER_SIZE[rip]
	xor	eax, eax
	call	snd_pcm_hw_rule_add@PLT
	pop	rcx
	.cfi_def_cfa_offset 40
	pop	rsi
	.cfi_def_cfa_offset 32
	test	eax, eax
	js	.L1
	mov	eax, DWORD PTR SNDRV_PCM_HW_PARAM_RATE[rip]
	push	-1
	.cfi_def_cfa_offset 40
	mov	r8d, 1000000
	xor	esi, esi
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_BUFFER_SIZE[rip]
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_BUFFER_TIME[rip]
	mov	rdi, rbp
	push	rax
	.cfi_def_cfa_offset 48
	mov	ecx, DWORD PTR snd_pcm_hw_rule_muldivk[rip]
	xor	eax, eax
	call	snd_pcm_hw_rule_add@PLT
	pop	rbx
	.cfi_def_cfa_offset 40
	pop	rdx
	.cfi_def_cfa_offset 32
	test	eax, eax
	js	.L1
	mov	eax, DWORD PTR SNDRV_PCM_HW_PARAM_FRAME_BITS[rip]
	push	-1
	.cfi_def_cfa_offset 40
	mov	r8d, 8
	xor	esi, esi
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_PERIOD_SIZE[rip]
	mov	ecx, DWORD PTR snd_pcm_hw_rule_muldivk[rip]
	mov	rdi, rbp
	push	rax
	.cfi_def_cfa_offset 48
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_PERIOD_BYTES[rip]
	xor	eax, eax
	call	snd_pcm_hw_rule_add@PLT
	pop	r10
	.cfi_def_cfa_offset 40
	pop	r11
	.cfi_def_cfa_offset 32
	test	eax, eax
	js	.L1
	mov	eax, DWORD PTR SNDRV_PCM_HW_PARAM_FRAME_BITS[rip]
	push	-1
	.cfi_def_cfa_offset 40
	mov	r8d, 8
	xor	esi, esi
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_BUFFER_SIZE[rip]
	mov	ecx, DWORD PTR snd_pcm_hw_rule_muldivk[rip]
	mov	rdi, rbp
	push	rax
	.cfi_def_cfa_offset 48
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_BUFFER_BYTES[rip]
	xor	eax, eax
	call	snd_pcm_hw_rule_add@PLT
	pop	r8
	.cfi_def_cfa_offset 40
	pop	r9
	.cfi_def_cfa_offset 32
	test	eax, eax
	js	.L1
	mov	eax, DWORD PTR SNDRV_PCM_HW_PARAM_RATE[rip]
	push	-1
	.cfi_def_cfa_offset 40
	xor	esi, esi
	mov	rdi, rbp
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_PERIOD_SIZE[rip]
	mov	ecx, DWORD PTR snd_pcm_hw_rule_mulkdiv[rip]
	mov	r8d, 1000000
	push	rax
	.cfi_def_cfa_offset 48
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_PERIOD_TIME[rip]
	xor	eax, eax
	call	snd_pcm_hw_rule_add@PLT
	pop	rsi
	.cfi_def_cfa_offset 40
	pop	rdi
	.cfi_def_cfa_offset 32
	test	eax, eax
	js	.L1
	mov	eax, DWORD PTR SNDRV_PCM_HW_PARAM_RATE[rip]
	push	-1
	.cfi_def_cfa_offset 40
	xor	esi, esi
	mov	r8d, 1000000
	mov	ecx, DWORD PTR snd_pcm_hw_rule_mulkdiv[rip]
	mov	edx, DWORD PTR SNDRV_PCM_HW_PARAM_BUFFER_TIME[rip]
	mov	rdi, rbp
	push	rax
	.cfi_def_cfa_offset 48
	mov	r9d, DWORD PTR SNDRV_PCM_HW_PARAM_BUFFER_SIZE[rip]
	xor	eax, eax
	call	snd_pcm_hw_rule_add@PLT
	pop	rdx
	.cfi_def_cfa_offset 40
	mov	edx, 0
	pop	rcx
	.cfi_def_cfa_offset 32
	test	eax, eax
	cmovg	eax, edx
.L1:
	add	rsp, 8
	.cfi_def_cfa_offset 24
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE0:
	.size	snd_pcm_hw_constraints_init, .-snd_pcm_hw_constraints_init
	.comm	snd_pcm_hw_rule_sample_bits,4,4
	.comm	snd_pcm_hw_rule_mulkdiv,4,4
	.comm	snd_pcm_hw_rule_muldivk,4,4
	.comm	snd_pcm_hw_rule_mul,4,4
	.comm	snd_pcm_hw_rule_format,4,4
	.comm	snd_pcm_hw_rule_div,4,4
	.comm	SNDRV_PCM_HW_PARAM_SAMPLE_BITS,4,4
	.comm	SNDRV_PCM_HW_PARAM_RATE,4,4
	.comm	SNDRV_PCM_HW_PARAM_PERIOD_TIME,4,4
	.comm	SNDRV_PCM_HW_PARAM_PERIOD_SIZE,4,4
	.comm	SNDRV_PCM_HW_PARAM_PERIOD_BYTES,4,4
	.comm	SNDRV_PCM_HW_PARAM_PERIODS,4,4
	.comm	SNDRV_PCM_HW_PARAM_LAST_MASK,4,4
	.comm	SNDRV_PCM_HW_PARAM_LAST_INTERVAL,4,4
	.comm	SNDRV_PCM_HW_PARAM_FRAME_BITS,4,4
	.comm	SNDRV_PCM_HW_PARAM_FORMAT,4,4
	.comm	SNDRV_PCM_HW_PARAM_FIRST_MASK,4,4
	.comm	SNDRV_PCM_HW_PARAM_FIRST_INTERVAL,4,4
	.comm	SNDRV_PCM_HW_PARAM_CHANNELS,4,4
	.comm	SNDRV_PCM_HW_PARAM_BUFFER_TIME,4,4
	.comm	SNDRV_PCM_HW_PARAM_BUFFER_SIZE,4,4
	.comm	SNDRV_PCM_HW_PARAM_BUFFER_BYTES,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_pcm_native.c_snd_pcm_hw_constraints_init.c"
	.text
	.align	2
	.global	snd_pcm_hw_constraints_init
	.syntax unified
	.arm
	.fpu softvfp
	.type	snd_pcm_hw_constraints_init, %function
snd_pcm_hw_constraints_init:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r3, .L11
	ldr	r6, .L11+4
	ldr	r5, [r3]
	ldr	r3, [r6]
	ldr	r4, [r0]
	cmp	r5, r3
	sub	sp, sp, #20
	bgt	.L2
.L3:
	mov	r1, r5
	mov	r0, r4
	bl	constrs_mask
	bl	snd_mask_any
	ldr	r3, [r6]
	add	r5, r5, #1
	cmp	r3, r5
	bge	.L3
.L2:
	ldr	r3, .L11+8
	ldr	r6, .L11+12
	ldr	r5, [r3]
	ldr	r3, [r6]
	cmp	r5, r3
	bgt	.L4
.L5:
	mov	r1, r5
	mov	r0, r4
	bl	constrs_interval
	bl	snd_interval_any
	ldr	r3, [r6]
	add	r5, r5, #1
	cmp	r3, r5
	bge	.L5
.L4:
	mvn	r7, #0
	mov	r5, #0
	ldr	r10, .L11+16
	mov	r0, r4
	ldr	r1, [r10]
	ldr	fp, .L11+20
	bl	constrs_interval
	bl	snd_interval_setinteger
	ldr	r9, .L11+24
	ldr	r1, [fp]
	mov	r0, r4
	bl	constrs_interval
	bl	snd_interval_setinteger
	ldr	r6, .L11+28
	ldr	r1, [r9]
	mov	r0, r4
	bl	constrs_interval
	bl	snd_interval_setinteger
	ldr	r8, .L11+32
	ldr	r1, [r6]
	mov	r0, r4
	bl	constrs_interval
	bl	snd_interval_setinteger
	ldr	r1, [r8]
	mov	r0, r4
	bl	constrs_interval
	bl	snd_interval_setinteger
	ldr	r2, [r6]
	ldr	r9, .L11+36
	stmib	sp, {r2, r7}
	ldr	r3, .L11+40
	str	r5, [sp]
	mov	r1, r5
	mov	r0, r4
	ldr	r3, [r3]
	ldr	r2, [r9]
	bl	snd_pcm_hw_rule_add
	cmp	r0, #0
	blt	.L1
	ldr	r1, [r9]
	ldr	r2, [r6]
	ldr	r3, .L11+44
	str	r1, [sp, #4]
	str	r7, [sp, #12]
	str	r5, [sp]
	str	r2, [sp, #8]
	mov	r1, r5
	mov	r0, r4
	ldr	r3, [r3]
	bl	snd_pcm_hw_rule_add
	cmp	r0, #0
	blt	.L1
	ldr	r1, [r10]
	ldr	r2, [r8]
	ldr	r9, .L11+48
	str	r7, [sp, #12]
	str	r5, [sp]
	ldr	r3, [r9]
	str	r1, [sp, #8]
	str	r2, [sp, #4]
	mov	r1, r5
	mov	r0, r4
	ldr	r2, [r6]
	bl	snd_pcm_hw_rule_add
	cmp	r0, #0
	blt	.L1
	ldr	r1, [r10]
	ldr	r2, [r6]
	ldr	r0, .L11+52
	str	r7, [sp, #12]
	str	r5, [sp]
	ldr	r3, [r0]
	str	r1, [sp, #8]
	str	r2, [sp, #4]
	mov	r1, r5
	mov	r0, r4
	ldr	r2, [r8]
	bl	snd_pcm_hw_rule_add
	cmp	r0, #0
	blt	.L1
	ldr	r1, .L11+56
	ldr	r2, .L11+60
	ldr	r3, [r1]
	mov	r1, #8
	ldr	r2, [r2]
	str	r1, [sp]
	str	r2, [sp, #8]
	ldr	r2, .L11+64
	str	r7, [sp, #12]
	str	r3, [sp, #4]
	ldr	r3, [r2]
	mov	r1, r5
	mov	r0, r4
	ldr	r2, [r8]
	bl	snd_pcm_hw_rule_add
	cmp	r0, #0
	blt	.L1
	mov	r1, #8
	ldr	r3, .L11+24
	ldr	r2, [fp]
	ldr	r3, [r3]
	str	r2, [sp, #8]
	ldr	r2, .L11+64
	str	r1, [sp]
	str	r7, [sp, #12]
	str	r3, [sp, #4]
	ldr	r3, [r2]
	mov	r1, r5
	mov	r0, r4
	ldr	r2, [r8]
	bl	snd_pcm_hw_rule_add
	cmp	r0, #0
	blt	.L1
	ldr	r2, [r6]
	ldr	r3, [r8]
	str	r2, [sp, #8]
	str	r7, [sp, #12]
	str	r5, [sp]
	ldr	r2, [r10]
	str	r3, [sp, #4]
	mov	r1, r5
	mov	r0, r4
	ldr	r3, [r9]
	bl	snd_pcm_hw_rule_add
	cmp	r0, #0
	blt	.L1
	ldr	r10, .L11+68
	ldr	ip, .L11+60
	ldr	r2, [r10]
	ldr	r3, [ip]
	ldr	lr, .L11+72
	ldr	r6, .L11+76
	str	r7, [sp, #12]
	str	r2, [sp, #8]
	ldr	r1, .L11+64
	ldr	r2, [lr]
	str	r3, [sp, #4]
	str	r6, [sp]
	ldr	r3, [r1]
	mov	r0, r4
	mov	r1, r5
	bl	snd_pcm_hw_rule_add
	cmp	r0, #0
	blt	.L1
	ldr	ip, .L11+80
	ldr	r3, [fp]
	ldr	r2, [ip]
	ldr	lr, .L11+72
	str	r2, [sp, #8]
	ldr	r2, .L11+64
	str	r7, [sp, #12]
	str	r6, [sp]
	str	r3, [sp, #4]
	ldr	r3, [r2]
	mov	r1, r5
	mov	r0, r4
	ldr	r2, [lr]
	bl	snd_pcm_hw_rule_add
	cmp	r0, #0
	blt	.L1
	ldr	r1, .L11+60
	ldr	r3, [fp]
	ldr	r0, [r1]
	str	r5, [sp]
	mov	r1, r5
	ldr	r5, .L11+84
	str	r7, [sp, #12]
	ldr	r2, [r5]
	str	r0, [sp, #8]
	str	r3, [sp, #4]
	mov	r0, r4
	ldr	r3, [r9]
	bl	snd_pcm_hw_rule_add
	cmp	r0, #0
	mov	r7, r5
	blt	.L1
	mov	r6, #0
	mvn	r5, #0
	ldr	r0, [r7]
	ldr	r2, [fp]
	ldr	ip, .L11+60
	ldr	r3, [r9]
	str	r0, [sp, #8]
	str	r5, [sp, #12]
	str	r6, [sp]
	str	r2, [sp, #4]
	mov	r1, r6
	mov	r0, r4
	ldr	r2, [ip]
	mov	r9, ip
	bl	snd_pcm_hw_rule_add
	cmp	r0, #0
	blt	.L1
	mov	r7, #8
	ldr	r1, .L11+56
	ldr	r2, [r8]
	ldr	r3, [r1]
	str	r2, [sp, #8]
	ldr	r2, .L11+64
	str	r5, [sp, #12]
	str	r7, [sp]
	str	r3, [sp, #4]
	ldr	r3, [r2]
	mov	r1, r6
	mov	r0, r4
	ldr	r2, [r9]
	bl	snd_pcm_hw_rule_add
	cmp	r0, #0
	blt	.L1
	ldr	lr, .L11+72
	ldr	r2, [r10]
	ldr	ip, .L11+88
	ldr	r0, [lr]
	str	r5, [sp, #12]
	ldr	r3, [ip]
	str	r2, [sp, #4]
	ldr	r2, .L11+76
	str	r0, [sp, #8]
	str	r2, [sp]
	mov	r1, r6
	mov	r0, r4
	ldr	r2, [r9]
	bl	snd_pcm_hw_rule_add
	cmp	r0, #0
	blt	.L1
	ldr	r2, .L11+84
	ldr	r0, .L11+52
	ldr	r3, [r2]
	ldr	r2, [r9]
	str	r3, [sp, #8]
	str	r5, [sp, #12]
	str	r6, [sp]
	ldr	r3, [r0]
	mov	r1, r6
	str	r2, [sp, #4]
	mov	r0, r4
	ldr	r2, [fp]
	bl	snd_pcm_hw_rule_add
	cmp	r0, #0
	blt	.L1
	ldr	r9, .L11+24
	ldr	r2, [r8]
	ldr	r3, [r9]
	ldr	r1, .L11+64
	str	r2, [sp, #8]
	str	r5, [sp, #12]
	str	r7, [sp]
	str	r3, [sp, #4]
	ldr	r3, [r1]
	mov	r0, r4
	mov	r1, r6
	ldr	r2, [fp]
	bl	snd_pcm_hw_rule_add
	cmp	r0, #0
	blt	.L1
	ldr	lr, .L11+72
	ldr	r3, .L11+80
	ldr	r2, [lr]
	ldr	r3, [r3]
	ldr	r0, .L11+76
	ldr	ip, .L11+88
	str	r0, [sp]
	str	r2, [sp, #8]
	str	r5, [sp, #12]
	str	r3, [sp, #4]
	mov	r1, r6
	mov	r0, r4
	ldr	r3, [ip]
	ldr	r2, [fp]
	bl	snd_pcm_hw_rule_add
	cmp	r0, #0
	blt	.L1
	ldr	r3, .L11+60
	ldr	r0, [r8]
	ldr	r3, [r3]
	ldr	r1, .L11+56
	str	r5, [sp, #12]
	str	r7, [sp]
	ldr	ip, .L11+88
	ldr	r2, [r1]
	str	r0, [sp, #8]
	str	r3, [sp, #4]
	mov	r1, r6
	mov	r0, r4
	ldr	r3, [ip]
	bl	snd_pcm_hw_rule_add
	cmp	r0, #0
	blt	.L1
	ldr	r3, [r8]
	ldr	r0, [fp]
	ldr	ip, .L11+88
	str	r3, [sp, #8]
	str	r5, [sp, #12]
	str	r7, [sp]
	ldr	r3, [ip]
	ldr	r2, [r9]
	mov	r1, r6
	str	r0, [sp, #4]
	mov	r0, r4
	bl	snd_pcm_hw_rule_add
	cmp	r0, #0
	blt	.L1
	ldr	r9, .L11+60
	ldr	lr, .L11+72
	ldr	r2, [r9]
	ldr	r9, .L11+76
	ldr	r3, [lr]
	ldr	r7, .L11+64
	str	r2, [sp, #4]
	str	r5, [sp, #12]
	str	r9, [sp]
	ldr	r2, [r10]
	str	r3, [sp, #8]
	mov	r1, r6
	mov	r0, r4
	ldr	r3, [r7]
	mov	r8, lr
	bl	snd_pcm_hw_rule_add
	cmp	r0, #0
	blt	.L1
	ldr	r2, [r8]
	ldr	r3, [fp]
	ldr	ip, .L11+80
	str	r2, [sp, #8]
	str	r3, [sp, #4]
	str	r5, [sp, #12]
	str	r9, [sp]
	mov	r1, r6
	mov	r0, r4
	ldr	r3, [r7]
	ldr	r2, [ip]
	bl	snd_pcm_hw_rule_add
	and	r0, r0, r0, asr #31
.L1:
	add	sp, sp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L12:
	.align	2
.L11:
	.word	SNDRV_PCM_HW_PARAM_FIRST_MASK
	.word	SNDRV_PCM_HW_PARAM_LAST_MASK
	.word	SNDRV_PCM_HW_PARAM_FIRST_INTERVAL
	.word	SNDRV_PCM_HW_PARAM_LAST_INTERVAL
	.word	SNDRV_PCM_HW_PARAM_CHANNELS
	.word	SNDRV_PCM_HW_PARAM_BUFFER_SIZE
	.word	SNDRV_PCM_HW_PARAM_BUFFER_BYTES
	.word	SNDRV_PCM_HW_PARAM_SAMPLE_BITS
	.word	SNDRV_PCM_HW_PARAM_FRAME_BITS
	.word	SNDRV_PCM_HW_PARAM_FORMAT
	.word	snd_pcm_hw_rule_format
	.word	snd_pcm_hw_rule_sample_bits
	.word	snd_pcm_hw_rule_div
	.word	snd_pcm_hw_rule_mul
	.word	SNDRV_PCM_HW_PARAM_PERIOD_BYTES
	.word	SNDRV_PCM_HW_PARAM_PERIOD_SIZE
	.word	snd_pcm_hw_rule_mulkdiv
	.word	SNDRV_PCM_HW_PARAM_PERIOD_TIME
	.word	SNDRV_PCM_HW_PARAM_RATE
	.word	1000000
	.word	SNDRV_PCM_HW_PARAM_BUFFER_TIME
	.word	SNDRV_PCM_HW_PARAM_PERIODS
	.word	snd_pcm_hw_rule_muldivk
	.size	snd_pcm_hw_constraints_init, .-snd_pcm_hw_constraints_init
	.comm	snd_pcm_hw_rule_sample_bits,4,4
	.comm	snd_pcm_hw_rule_mulkdiv,4,4
	.comm	snd_pcm_hw_rule_muldivk,4,4
	.comm	snd_pcm_hw_rule_mul,4,4
	.comm	snd_pcm_hw_rule_format,4,4
	.comm	snd_pcm_hw_rule_div,4,4
	.comm	SNDRV_PCM_HW_PARAM_SAMPLE_BITS,4,4
	.comm	SNDRV_PCM_HW_PARAM_RATE,4,4
	.comm	SNDRV_PCM_HW_PARAM_PERIOD_TIME,4,4
	.comm	SNDRV_PCM_HW_PARAM_PERIOD_SIZE,4,4
	.comm	SNDRV_PCM_HW_PARAM_PERIOD_BYTES,4,4
	.comm	SNDRV_PCM_HW_PARAM_PERIODS,4,4
	.comm	SNDRV_PCM_HW_PARAM_LAST_MASK,4,4
	.comm	SNDRV_PCM_HW_PARAM_LAST_INTERVAL,4,4
	.comm	SNDRV_PCM_HW_PARAM_FRAME_BITS,4,4
	.comm	SNDRV_PCM_HW_PARAM_FORMAT,4,4
	.comm	SNDRV_PCM_HW_PARAM_FIRST_MASK,4,4
	.comm	SNDRV_PCM_HW_PARAM_FIRST_INTERVAL,4,4
	.comm	SNDRV_PCM_HW_PARAM_CHANNELS,4,4
	.comm	SNDRV_PCM_HW_PARAM_BUFFER_TIME,4,4
	.comm	SNDRV_PCM_HW_PARAM_BUFFER_SIZE,4,4
	.comm	SNDRV_PCM_HW_PARAM_BUFFER_BYTES,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
