	.file	"extr_identcpu.c_parse_cpu_features_hwcap.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	parse_cpu_features_hwcap, @function
parse_cpu_features_hwcap:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	lea	rbx, [rdi+rdi*2]
	sal	rbx, 2
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	mov	rax, QWORD PTR cpu_desc[rip]
	mov	edi, DWORD PTR 8[rax+rbx]
	call	ID_AA64ISAR0_DP_VAL@PLT
	cmp	rax, QWORD PTR ID_AA64ISAR0_DP_IMPL[rip]
	mov	r12d, DWORD PTR HWCAP_ASIMDDP[rip]
	je	.L2
	xor	r12d, r12d
.L2:
	mov	rax, QWORD PTR cpu_desc[rip]
	mov	edi, DWORD PTR 8[rax+rbx]
	call	ID_AA64ISAR0_SM4_VAL@PLT
	cmp	rax, QWORD PTR ID_AA64ISAR0_SM4_IMPL[rip]
	jne	.L3
	or	r12d, DWORD PTR HWCAP_SM4[rip]
.L3:
	mov	rax, QWORD PTR cpu_desc[rip]
	mov	edi, DWORD PTR 8[rax+rbx]
	call	ID_AA64ISAR0_SM3_VAL@PLT
	cmp	rax, QWORD PTR ID_AA64ISAR0_SM3_IMPL[rip]
	jne	.L4
	or	r12d, DWORD PTR HWCAP_SM3[rip]
.L4:
	mov	rax, QWORD PTR cpu_desc[rip]
	mov	edi, DWORD PTR 8[rax+rbx]
	call	ID_AA64ISAR0_RDM_VAL@PLT
	cmp	rax, QWORD PTR ID_AA64ISAR0_RDM_IMPL[rip]
	jne	.L5
	or	r12d, DWORD PTR HWCAP_ASIMDRDM[rip]
.L5:
	mov	rax, QWORD PTR cpu_desc[rip]
	mov	edi, DWORD PTR 8[rax+rbx]
	call	ID_AA64ISAR0_Atomic_VAL@PLT
	cmp	rax, QWORD PTR ID_AA64ISAR0_Atomic_IMPL[rip]
	jne	.L6
	or	r12d, DWORD PTR HWCAP_ATOMICS[rip]
.L6:
	mov	rax, QWORD PTR cpu_desc[rip]
	mov	edi, DWORD PTR 8[rax+rbx]
	call	ID_AA64ISAR0_CRC32_VAL@PLT
	cmp	rax, QWORD PTR ID_AA64ISAR0_CRC32_BASE[rip]
	jne	.L7
	or	r12d, DWORD PTR HWCAP_CRC32[rip]
.L7:
	mov	rax, QWORD PTR cpu_desc[rip]
	mov	edi, DWORD PTR 8[rax+rbx]
	call	ID_AA64ISAR0_SHA2_VAL@PLT
	cmp	eax, 132
	je	.L8
	cmp	eax, 133
	jne	.L10
	mov	eax, DWORD PTR HWCAP_SHA2[rip]
	or	eax, DWORD PTR HWCAP_SHA512[rip]
	or	r12d, eax
.L10:
	mov	rax, QWORD PTR cpu_desc[rip]
	mov	edi, DWORD PTR 8[rax+rbx]
	call	ID_AA64ISAR0_SHA1_VAL@PLT
	test	rax, rax
	jne	.L32
.L11:
	mov	rax, QWORD PTR cpu_desc[rip]
	mov	edi, DWORD PTR 8[rax+rbx]
	call	ID_AA64ISAR0_AES_VAL@PLT
	cmp	eax, 134
	je	.L12
	cmp	eax, 135
	je	.L33
.L13:
	mov	rax, QWORD PTR cpu_desc[rip]
	mov	edi, DWORD PTR 4[rax+rbx]
	call	ID_AA64ISAR1_LRCPC_VAL@PLT
	cmp	rax, QWORD PTR ID_AA64ISAR1_LRCPC_IMPL[rip]
	jne	.L14
	or	r12d, DWORD PTR HWCAP_LRCPC[rip]
.L14:
	mov	rax, QWORD PTR cpu_desc[rip]
	mov	edi, DWORD PTR 4[rax+rbx]
	call	ID_AA64ISAR1_FCMA_VAL@PLT
	cmp	rax, QWORD PTR ID_AA64ISAR1_FCMA_IMPL[rip]
	jne	.L15
	or	r12d, DWORD PTR HWCAP_FCMA[rip]
.L15:
	mov	rax, QWORD PTR cpu_desc[rip]
	mov	edi, DWORD PTR 4[rax+rbx]
	call	ID_AA64ISAR1_JSCVT_VAL@PLT
	cmp	rax, QWORD PTR ID_AA64ISAR1_JSCVT_IMPL[rip]
	jne	.L16
	or	r12d, DWORD PTR HWCAP_JSCVT[rip]
.L16:
	mov	rax, QWORD PTR cpu_desc[rip]
	mov	edi, DWORD PTR 4[rax+rbx]
	call	ID_AA64ISAR1_DPB_VAL@PLT
	cmp	rax, QWORD PTR ID_AA64ISAR1_DPB_IMPL[rip]
	jne	.L17
	or	r12d, DWORD PTR HWCAP_DCPOP[rip]
.L17:
	mov	rax, QWORD PTR cpu_desc[rip]
	mov	edi, DWORD PTR [rax+rbx]
	call	ID_AA64PFR0_SVE_VAL@PLT
	cmp	rax, QWORD PTR ID_AA64PFR0_SVE_IMPL[rip]
	jne	.L18
	or	r12d, DWORD PTR HWCAP_SVE[rip]
.L18:
	mov	rax, QWORD PTR cpu_desc[rip]
	mov	edi, DWORD PTR [rax+rbx]
	call	ID_AA64PFR0_AdvSIMD_VAL@PLT
	cmp	eax, 130
	je	.L19
	cmp	eax, 131
	je	.L20
.L21:
	mov	rax, QWORD PTR cpu_desc[rip]
	mov	edi, DWORD PTR [rax+rbx]
	call	ID_AA64PFR0_FP_VAL@PLT
	cmp	eax, 128
	je	.L22
	cmp	eax, 129
	je	.L23
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	mov	eax, r12d
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L32:
	.cfi_restore_state
	or	r12d, DWORD PTR HWCAP_SHA1[rip]
	jmp	.L11
	.p2align 4,,10
	.p2align 3
.L33:
	or	r12d, DWORD PTR HWCAP_AES[rip]
	jmp	.L13
	.p2align 4,,10
	.p2align 3
.L23:
	mov	eax, DWORD PTR HWCAP_FP[rip]
	or	eax, DWORD PTR HWCAP_FPHP[rip]
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	or	r12d, eax
	pop	rbx
	.cfi_def_cfa_offset 16
	mov	eax, r12d
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L20:
	.cfi_restore_state
	mov	eax, DWORD PTR HWCAP_ASIMD[rip]
	or	eax, DWORD PTR HWCAP_ASIMDDP[rip]
	or	r12d, eax
	jmp	.L21
	.p2align 4,,10
	.p2align 3
.L8:
	or	r12d, DWORD PTR HWCAP_SHA2[rip]
	jmp	.L10
	.p2align 4,,10
	.p2align 3
.L12:
	mov	eax, DWORD PTR HWCAP_PMULL[rip]
	or	eax, DWORD PTR HWCAP_AES[rip]
	or	r12d, eax
	jmp	.L13
	.p2align 4,,10
	.p2align 3
.L22:
	or	r12d, DWORD PTR HWCAP_FP[rip]
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	mov	eax, r12d
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L19:
	.cfi_restore_state
	or	r12d, DWORD PTR HWCAP_ASIMD[rip]
	jmp	.L21
	.cfi_endproc
.LFE0:
	.size	parse_cpu_features_hwcap, .-parse_cpu_features_hwcap
	.comm	cpu_desc,8,8
	.comm	ID_AA64PFR0_SVE_IMPL,8,8
	.comm	ID_AA64ISAR1_LRCPC_IMPL,8,8
	.comm	ID_AA64ISAR1_JSCVT_IMPL,8,8
	.comm	ID_AA64ISAR1_FCMA_IMPL,8,8
	.comm	ID_AA64ISAR1_DPB_IMPL,8,8
	.comm	ID_AA64ISAR0_SM4_IMPL,8,8
	.comm	ID_AA64ISAR0_SM3_IMPL,8,8
	.comm	ID_AA64ISAR0_RDM_IMPL,8,8
	.comm	ID_AA64ISAR0_DP_IMPL,8,8
	.comm	ID_AA64ISAR0_CRC32_BASE,8,8
	.comm	ID_AA64ISAR0_Atomic_IMPL,8,8
	.comm	HWCAP_SVE,4,4
	.comm	HWCAP_SM4,4,4
	.comm	HWCAP_SM3,4,4
	.comm	HWCAP_SHA512,4,4
	.comm	HWCAP_SHA2,4,4
	.comm	HWCAP_SHA1,4,4
	.comm	HWCAP_PMULL,4,4
	.comm	HWCAP_LRCPC,4,4
	.comm	HWCAP_JSCVT,4,4
	.comm	HWCAP_FPHP,4,4
	.comm	HWCAP_FP,4,4
	.comm	HWCAP_FCMA,4,4
	.comm	HWCAP_DCPOP,4,4
	.comm	HWCAP_CRC32,4,4
	.comm	HWCAP_ATOMICS,4,4
	.comm	HWCAP_ASIMDRDM,4,4
	.comm	HWCAP_ASIMDDP,4,4
	.comm	HWCAP_ASIMD,4,4
	.comm	HWCAP_AES,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_identcpu.c_parse_cpu_features_hwcap.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	parse_cpu_features_hwcap, %function
parse_cpu_features_hwcap:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, lr}
	ldr	r4, .L32
	add	r0, r0, r0, lsl #1
	ldr	r3, [r4]
	lsl	r5, r0, #2
	add	r0, r3, r0, lsl #2
	ldr	r0, [r0, #8]
	bl	ID_AA64ISAR0_DP_VAL
	ldr	r3, .L32+4
	ldr	r3, [r3]
	cmp	r0, r3
	ldreq	r3, .L32+8
	movne	r6, #0
	ldreq	r6, [r3]
	ldr	r3, [r4]
	add	r3, r3, r5
	ldr	r0, [r3, #8]
	bl	ID_AA64ISAR0_SM4_VAL
	ldr	r3, .L32+12
	ldr	r3, [r3]
	cmp	r0, r3
	ldreq	r3, .L32+16
	ldreq	r3, [r3]
	orreq	r6, r6, r3
	ldr	r3, [r4]
	add	r3, r3, r5
	ldr	r0, [r3, #8]
	bl	ID_AA64ISAR0_SM3_VAL
	ldr	r3, .L32+20
	ldr	r3, [r3]
	cmp	r0, r3
	ldreq	r3, .L32+24
	ldreq	r3, [r3]
	orreq	r6, r6, r3
	ldr	r3, [r4]
	add	r3, r3, r5
	ldr	r0, [r3, #8]
	bl	ID_AA64ISAR0_RDM_VAL
	ldr	r3, .L32+28
	ldr	r3, [r3]
	cmp	r0, r3
	ldreq	r3, .L32+32
	ldreq	r3, [r3]
	orreq	r6, r6, r3
	ldr	r3, [r4]
	add	r3, r3, r5
	ldr	r0, [r3, #8]
	bl	ID_AA64ISAR0_Atomic_VAL
	ldr	r3, .L32+36
	ldr	r3, [r3]
	cmp	r0, r3
	ldreq	r3, .L32+40
	ldreq	r3, [r3]
	orreq	r6, r6, r3
	ldr	r3, [r4]
	add	r3, r3, r5
	ldr	r0, [r3, #8]
	bl	ID_AA64ISAR0_CRC32_VAL
	ldr	r3, .L32+44
	ldr	r3, [r3]
	cmp	r0, r3
	ldreq	r3, .L32+48
	ldreq	r3, [r3]
	orreq	r6, r6, r3
	ldr	r3, [r4]
	add	r3, r3, r5
	ldr	r0, [r3, #8]
	bl	ID_AA64ISAR0_SHA2_VAL
	cmp	r0, #132
	beq	.L8
	cmp	r0, #133
	bne	.L10
	ldr	r3, .L32+52
	ldr	r2, .L32+56
	ldr	r3, [r3]
	ldr	r2, [r2]
	orr	r3, r3, r2
	orr	r6, r6, r3
.L10:
	ldr	r3, [r4]
	add	r3, r3, r5
	ldr	r0, [r3, #8]
	bl	ID_AA64ISAR0_SHA1_VAL
	cmp	r0, #0
	ldrne	r3, .L32+60
	ldrne	r3, [r3]
	orrne	r6, r6, r3
	ldr	r3, [r4]
	add	r3, r3, r5
	ldr	r0, [r3, #8]
	bl	ID_AA64ISAR0_AES_VAL
	cmp	r0, #134
	beq	.L12
	cmp	r0, #135
	beq	.L31
.L13:
	ldr	r3, [r4]
	add	r3, r3, r5
	ldr	r0, [r3, #4]
	bl	ID_AA64ISAR1_LRCPC_VAL
	ldr	r3, .L32+64
	ldr	r3, [r3]
	cmp	r0, r3
	ldreq	r3, .L32+68
	ldreq	r3, [r3]
	orreq	r6, r6, r3
	ldr	r3, [r4]
	add	r3, r3, r5
	ldr	r0, [r3, #4]
	bl	ID_AA64ISAR1_FCMA_VAL
	ldr	r3, .L32+72
	ldr	r3, [r3]
	cmp	r0, r3
	ldreq	r3, .L32+76
	ldreq	r3, [r3]
	orreq	r6, r6, r3
	ldr	r3, [r4]
	add	r3, r3, r5
	ldr	r0, [r3, #4]
	bl	ID_AA64ISAR1_JSCVT_VAL
	ldr	r3, .L32+80
	ldr	r3, [r3]
	cmp	r0, r3
	ldreq	r3, .L32+84
	ldreq	r3, [r3]
	orreq	r6, r6, r3
	ldr	r3, [r4]
	add	r3, r3, r5
	ldr	r0, [r3, #4]
	bl	ID_AA64ISAR1_DPB_VAL
	ldr	r3, .L32+88
	ldr	r3, [r3]
	cmp	r0, r3
	ldreq	r3, .L32+92
	ldreq	r3, [r3]
	orreq	r6, r6, r3
	ldr	r3, [r4]
	ldr	r0, [r3, r5]
	bl	ID_AA64PFR0_SVE_VAL
	ldr	r3, .L32+96
	ldr	r3, [r3]
	cmp	r0, r3
	ldreq	r3, .L32+100
	ldreq	r3, [r3]
	orreq	r6, r6, r3
	ldr	r3, [r4]
	ldr	r0, [r3, r5]
	bl	ID_AA64PFR0_AdvSIMD_VAL
	cmp	r0, #130
	beq	.L19
	cmp	r0, #131
	beq	.L20
.L21:
	ldr	r3, [r4]
	ldr	r0, [r3, r5]
	bl	ID_AA64PFR0_FP_VAL
	cmp	r0, #128
	beq	.L22
	cmp	r0, #129
	beq	.L23
	mov	r0, r6
	pop	{r4, r5, r6, pc}
.L31:
	ldr	r3, .L32+104
	ldr	r3, [r3]
	orr	r6, r6, r3
	b	.L13
.L23:
	ldr	r3, .L32+108
	ldr	r2, .L32+112
	ldr	r3, [r3]
	ldr	r2, [r2]
	orr	r3, r3, r2
	orr	r6, r6, r3
	mov	r0, r6
	pop	{r4, r5, r6, pc}
.L20:
	ldr	r3, .L32+116
	ldr	r2, .L32+8
	ldr	r3, [r3]
	ldr	r2, [r2]
	orr	r3, r3, r2
	orr	r6, r6, r3
	b	.L21
.L12:
	ldr	r3, .L32+120
	ldr	r2, .L32+104
	ldr	r3, [r3]
	ldr	r2, [r2]
	orr	r3, r3, r2
	orr	r6, r6, r3
	b	.L13
.L8:
	ldr	r3, .L32+52
	ldr	r3, [r3]
	orr	r6, r6, r3
	b	.L10
.L22:
	ldr	r3, .L32+108
	ldr	r3, [r3]
	orr	r6, r6, r3
	mov	r0, r6
	pop	{r4, r5, r6, pc}
.L19:
	ldr	r3, .L32+116
	ldr	r3, [r3]
	orr	r6, r6, r3
	b	.L21
.L33:
	.align	2
.L32:
	.word	cpu_desc
	.word	ID_AA64ISAR0_DP_IMPL
	.word	HWCAP_ASIMDDP
	.word	ID_AA64ISAR0_SM4_IMPL
	.word	HWCAP_SM4
	.word	ID_AA64ISAR0_SM3_IMPL
	.word	HWCAP_SM3
	.word	ID_AA64ISAR0_RDM_IMPL
	.word	HWCAP_ASIMDRDM
	.word	ID_AA64ISAR0_Atomic_IMPL
	.word	HWCAP_ATOMICS
	.word	ID_AA64ISAR0_CRC32_BASE
	.word	HWCAP_CRC32
	.word	HWCAP_SHA2
	.word	HWCAP_SHA512
	.word	HWCAP_SHA1
	.word	ID_AA64ISAR1_LRCPC_IMPL
	.word	HWCAP_LRCPC
	.word	ID_AA64ISAR1_FCMA_IMPL
	.word	HWCAP_FCMA
	.word	ID_AA64ISAR1_JSCVT_IMPL
	.word	HWCAP_JSCVT
	.word	ID_AA64ISAR1_DPB_IMPL
	.word	HWCAP_DCPOP
	.word	ID_AA64PFR0_SVE_IMPL
	.word	HWCAP_SVE
	.word	HWCAP_AES
	.word	HWCAP_FP
	.word	HWCAP_FPHP
	.word	HWCAP_ASIMD
	.word	HWCAP_PMULL
	.size	parse_cpu_features_hwcap, .-parse_cpu_features_hwcap
	.comm	cpu_desc,4,4
	.comm	ID_AA64PFR0_SVE_IMPL,4,4
	.comm	ID_AA64ISAR1_LRCPC_IMPL,4,4
	.comm	ID_AA64ISAR1_JSCVT_IMPL,4,4
	.comm	ID_AA64ISAR1_FCMA_IMPL,4,4
	.comm	ID_AA64ISAR1_DPB_IMPL,4,4
	.comm	ID_AA64ISAR0_SM4_IMPL,4,4
	.comm	ID_AA64ISAR0_SM3_IMPL,4,4
	.comm	ID_AA64ISAR0_RDM_IMPL,4,4
	.comm	ID_AA64ISAR0_DP_IMPL,4,4
	.comm	ID_AA64ISAR0_CRC32_BASE,4,4
	.comm	ID_AA64ISAR0_Atomic_IMPL,4,4
	.comm	HWCAP_SVE,4,4
	.comm	HWCAP_SM4,4,4
	.comm	HWCAP_SM3,4,4
	.comm	HWCAP_SHA512,4,4
	.comm	HWCAP_SHA2,4,4
	.comm	HWCAP_SHA1,4,4
	.comm	HWCAP_PMULL,4,4
	.comm	HWCAP_LRCPC,4,4
	.comm	HWCAP_JSCVT,4,4
	.comm	HWCAP_FPHP,4,4
	.comm	HWCAP_FP,4,4
	.comm	HWCAP_FCMA,4,4
	.comm	HWCAP_DCPOP,4,4
	.comm	HWCAP_CRC32,4,4
	.comm	HWCAP_ATOMICS,4,4
	.comm	HWCAP_ASIMDRDM,4,4
	.comm	HWCAP_ASIMDDP,4,4
	.comm	HWCAP_ASIMD,4,4
	.comm	HWCAP_AES,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
