	.file	"extr_amdgpu_ucode.c_amdgpu_ucode_init_bo.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	amdgpu_ucode_init_bo
	.type	amdgpu_ucode_init_bo, @function
amdgpu_ucode_init_bo:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 8
	.cfi_def_cfa_offset 64
	call	amdgpu_sriov_vf@PLT
	test	rax, rax
	jne	.L2
	cmp	QWORD PTR 48[rbp], 0
	jne	.L11
	cmp	QWORD PTR 40[rbp], 0
	jne	.L11
.L2:
	mov	rax, QWORD PTR AMDGPU_FW_LOAD_PSP[rip]
	cmp	QWORD PTR 0[rbp], rax
	jne	.L15
	mov	rdx, QWORD PTR AMDGPU_UCODE_ID_MAXIMUM[rip]
	mov	DWORD PTR 8[rbp], edx
	mov	eax, edx
.L7:
	test	eax, eax
	jle	.L11
	xor	r12d, r12d
	xor	r13d, r13d
	jmp	.L10
	.p2align 4,,10
	.p2align 3
.L9:
	mov	esi, DWORD PTR PAGE_SIZE[rip]
	mov	edi, DWORD PTR [rbx]
	call	ALIGN@PLT
	add	r13, rax
.L8:
	add	r12, 1
	cmp	DWORD PTR 8[rbp], r12d
	jle	.L11
.L10:
	mov	rbx, r12
	sal	rbx, 4
	add	rbx, QWORD PTR 32[rbp]
	cmp	QWORD PTR 8[rbx], 0
	je	.L8
	mov	rcx, QWORD PTR 16[rbp]
	mov	rdx, QWORD PTR 24[rbp]
	mov	rsi, rbx
	mov	rdi, rbp
	add	rcx, r13
	add	rdx, r13
	call	amdgpu_ucode_init_single_fw@PLT
	cmp	DWORD PTR AMDGPU_UCODE_ID_CP_MEC1[rip], r12d
	jne	.L9
	mov	rax, QWORD PTR AMDGPU_FW_LOAD_PSP[rip]
	cmp	QWORD PTR 0[rbp], rax
	je	.L9
	mov	rax, QWORD PTR 8[rbx]
	mov	rdx, QWORD PTR 16[rbp]
	mov	rdi, rbx
	mov	rsi, QWORD PTR 24[rbp]
	mov	r15, QWORD PTR [rax]
	add	rdx, r13
	add	rsi, r13
	call	amdgpu_ucode_patch_jt@PLT
	mov	edi, DWORD PTR [r15]
	mov	r14d, DWORD PTR PAGE_SIZE[rip]
	call	le32_to_cpu@PLT
	mov	esi, r14d
	lea	edi, 0[0+rax*4]
	call	ALIGN@PLT
	add	r13, rax
	jmp	.L9
	.p2align 4,,10
	.p2align 3
.L11:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	xor	eax, eax
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L15:
	.cfi_restore_state
	mov	rdi, rbp
	call	amdgpu_sriov_vf@PLT
	test	rax, rax
	mov	rax, QWORD PTR AMDGPU_UCODE_ID_MAXIMUM[rip]
	je	.L6
	lea	rdx, -3[rax]
	mov	DWORD PTR 8[rbp], edx
	mov	eax, edx
	jmp	.L7
	.p2align 4,,10
	.p2align 3
.L6:
	lea	rdx, -4[rax]
	mov	DWORD PTR 8[rbp], edx
	mov	eax, edx
	jmp	.L7
	.cfi_endproc
.LFE0:
	.size	amdgpu_ucode_init_bo, .-amdgpu_ucode_init_bo
	.comm	PAGE_SIZE,4,4
	.comm	AMDGPU_UCODE_ID_MAXIMUM,8,8
	.comm	AMDGPU_UCODE_ID_CP_MEC1,4,4
	.comm	AMDGPU_FW_LOAD_PSP,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_amdgpu_ucode.c_amdgpu_ucode_init_bo.c"
	.text
	.align	2
	.global	amdgpu_ucode_init_bo
	.syntax unified
	.arm
	.fpu softvfp
	.type	amdgpu_ucode_init_bo, %function
amdgpu_ucode_init_bo:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	sub	sp, sp, #12
	mov	r5, r0
	bl	amdgpu_sriov_vf
	cmp	r0, #0
	bne	.L2
	ldr	r3, [r5, #24]
	cmp	r3, #0
	bne	.L15
	ldr	r3, [r5, #20]
	cmp	r3, #0
	bne	.L15
.L2:
	ldr	fp, .L21
	ldr	r2, [r5]
	ldr	r3, [fp]
	cmp	r2, r3
	bne	.L20
	ldr	r3, .L21+4
	ldr	r3, [r3]
	str	r3, [r5, #4]
.L7:
	cmp	r3, #0
	ble	.L15
	mov	r4, #0
	ldr	r10, .L21+8
	mov	r6, r4
	b	.L10
.L9:
	ldr	r3, .L21+12
	ldr	r0, [r8, r9]
	ldr	r1, [r3]
	bl	ALIGN
	add	r6, r6, r0
.L8:
	ldr	r3, [r5, #4]
	add	r4, r4, #1
	cmp	r3, r4
	ble	.L15
.L10:
	ldr	r8, [r5, #16]
	lsl	r9, r4, #3
	add	r7, r8, r4, lsl #3
	ldr	r3, [r7, #4]
	cmp	r3, #0
	beq	.L8
	ldr	r3, [r5, #8]
	ldr	r2, [r5, #12]
	add	r3, r6, r3
	mov	r1, r7
	mov	r0, r5
	add	r2, r6, r2
	bl	amdgpu_ucode_init_single_fw
	ldr	r3, [r10]
	cmp	r3, r4
	bne	.L9
	ldr	r2, [r5]
	ldr	r3, [fp]
	cmp	r2, r3
	beq	.L9
	ldr	r3, [r7, #4]
	ldr	r2, [r5, #8]
	ldr	r1, [r5, #12]
	ldr	r3, [r3]
	add	r2, r6, r2
	add	r1, r6, r1
	mov	r0, r7
	str	r3, [sp, #4]
	bl	amdgpu_ucode_patch_jt
	ldr	r3, [sp, #4]
	ldr	r0, [r3]
	bl	le32_to_cpu
	ldr	r3, .L21+12
	lsl	r0, r0, #2
	ldr	r1, [r3]
	bl	ALIGN
	add	r6, r6, r0
	b	.L9
.L15:
	mov	r0, #0
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L20:
	mov	r0, r5
	bl	amdgpu_sriov_vf
	ldr	r3, .L21+4
	cmp	r0, #0
	ldr	r3, [r3]
	subne	r3, r3, #3
	subeq	r3, r3, #4
	str	r3, [r5, #4]
	b	.L7
.L22:
	.align	2
.L21:
	.word	AMDGPU_FW_LOAD_PSP
	.word	AMDGPU_UCODE_ID_MAXIMUM
	.word	AMDGPU_UCODE_ID_CP_MEC1
	.word	PAGE_SIZE
	.size	amdgpu_ucode_init_bo, .-amdgpu_ucode_init_bo
	.comm	PAGE_SIZE,4,4
	.comm	AMDGPU_UCODE_ID_MAXIMUM,4,4
	.comm	AMDGPU_UCODE_ID_CP_MEC1,4,4
	.comm	AMDGPU_FW_LOAD_PSP,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
