	.file	"extr_radeon_base.c_radeon_calc_pll_regs.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC0:
	.string	"freq = %lu, PLL min = %u, PLL max = %u\n"
	.align 8
.LC1:
	.string	"ref_div = %d, ref_clk = %d, output_freq = %d\n"
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"post div = 0x%x\n"
.LC3:
	.string	"fb_div = 0x%x\n"
.LC4:
	.string	"ppll_div_3 = 0x%x\n"
	.text
	.p2align 4
	.type	radeon_calc_pll_regs, @function
radeon_calc_pll_regs:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	mov	r13, rsi
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	mov	r12, rdx
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 8
	.cfi_def_cfa_offset 64
	cmp	QWORD PTR 32[rdi], 0
	jne	.L2
.L4:
	xor	r14d, r14d
.L3:
	mov	rcx, QWORD PTR 8[rbp]
	mov	r8, QWORD PTR 16[rbp]
	cmp	rcx, r12
	cmovbe	r12, rcx
	lea	rax, [r12+r12*2]
	sal	rax, 2
	cmp	rax, r8
	jnb	.L10
	movabs	r12, -6148914691236517205
	mov	rax, r8
	mul	r12
	mov	r12, rdx
	shr	r12, 3
.L10:
	mov	rdx, r8
	lea	r15, post_divs.1952[rip]
	mov	esi, r12d
	xor	eax, eax
	lea	rdi, .LC0[rip]
	call	pr_debug@PLT
	xor	ecx, ecx
	mov	eax, 1
	mov	rdx, r15
	mov	QWORD PTR post_div.1951[rip], r15
	.p2align 4,,10
	.p2align 3
.L14:
	mov	ebx, r12d
	imul	ebx, eax
	test	r14d, r14d
	je	.L11
	test	al, 1
	jne	.L12
.L11:
	movsx	rax, ebx
	cmp	rax, QWORD PTR 16[rbp]
	jb	.L12
	cmp	rax, QWORD PTR 8[rbp]
	jbe	.L13
.L12:
	mov	eax, DWORD PTR 8[rdx]
	add	rdx, 8
	mov	ecx, 1
	test	eax, eax
	jne	.L14
	movsx	rax, DWORD PTR 4[rdx]
	mov	ebx, DWORD PTR [r15+rax*8]
	lea	rdx, [r15+rax*8]
	mov	QWORD PTR post_div.1951[rip], rdx
	imul	ebx, r12d
.L18:
	mov	edx, DWORD PTR 28[rbp]
	mov	esi, DWORD PTR 24[rbp]
	mov	ecx, ebx
	lea	rdi, .LC1[rip]
	xor	eax, eax
	call	pr_debug@PLT
	mov	rax, QWORD PTR post_div.1951[rip]
	mov	edx, DWORD PTR [rax]
	test	edx, edx
	jne	.L17
	movsx	rax, DWORD PTR 4[rax]
	mov	ebx, DWORD PTR [r15+rax*8]
	lea	rdx, [r15+rax*8]
	mov	QWORD PTR post_div.1951[rip], rdx
	imul	ebx, r12d
.L17:
	mov	edx, DWORD PTR 28[rbp]
	mov	esi, DWORD PTR 24[rbp]
	mov	ecx, ebx
	lea	rdi, .LC1[rip]
	xor	eax, eax
	call	pr_debug@PLT
	mov	edi, DWORD PTR 24[rbp]
	mov	esi, DWORD PTR 28[rbp]
	imul	edi, ebx
	call	round_div@PLT
	lea	rdi, .LC2[rip]
	mov	r12d, eax
	mov	eax, DWORD PTR 24[rbp]
	mov	DWORD PTR 0[r13], eax
	mov	rax, QWORD PTR post_div.1951[rip]
	mov	esi, DWORD PTR 4[rax]
	mov	eax, esi
	sal	eax, 16
	or	eax, r12d
	mov	DWORD PTR 4[r13], eax
	xor	eax, eax
	call	pr_debug@PLT
	mov	esi, r12d
	lea	rdi, .LC3[rip]
	xor	eax, eax
	call	pr_debug@PLT
	mov	esi, DWORD PTR 4[r13]
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	xor	eax, eax
	pop	rbx
	.cfi_def_cfa_offset 48
	lea	rdi, .LC4[rip]
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	jmp	pr_debug@PLT
	.p2align 4,,10
	.p2align 3
.L2:
	.cfi_restore_state
	mov	edi, DWORD PTR FP2_GEN_CNTL[rip]
	call	INREG@PLT
	mov	ebx, eax
	test	DWORD PTR FP2_ON[rip], eax
	je	.L4
	mov	rax, QWORD PTR CHIP_FAMILY_R200[rip]
	cmp	QWORD PTR 0[rbp], rax
	je	.L8
	mov	rdi, rbp
	call	IS_R300_VARIANT@PLT
	test	rax, rax
	je	.L33
.L8:
	sar	ebx, 10
	and	ebx, 3
	cmp	ebx, 3
	je	.L34
.L7:
	xor	r14d, r14d
	cmp	ebx, 1
	setne	r14b
	jmp	.L3
	.p2align 4,,10
	.p2align 3
.L13:
	test	cl, cl
	je	.L18
	mov	QWORD PTR post_div.1951[rip], rdx
	jmp	.L18
.L33:
	sar	ebx, 13
	and	ebx, 1
	jmp	.L7
.L34:
	mov	edi, DWORD PTR DISP_OUTPUT_CNTL[rip]
	call	INREG@PLT
	sar	eax, 12
	mov	ebx, eax
	and	ebx, 3
	jmp	.L7
	.cfi_endproc
.LFE0:
	.size	radeon_calc_pll_regs, .-radeon_calc_pll_regs
	.section	.rodata
	.align 32
	.type	post_divs.1952, @object
	.size	post_divs.1952, 72
post_divs.1952:
	.long	1
	.long	0
	.long	2
	.long	1
	.long	4
	.long	2
	.long	8
	.long	3
	.long	3
	.long	4
	.long	16
	.long	5
	.long	6
	.long	6
	.long	12
	.long	7
	.long	0
	.long	0
	.local	post_div.1951
	.comm	post_div.1951,8,8
	.comm	FP2_ON,4,4
	.comm	FP2_GEN_CNTL,4,4
	.comm	DISP_OUTPUT_CNTL,4,4
	.comm	CHIP_FAMILY_R200,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_radeon_base.c_radeon_calc_pll_regs.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"freq = %lu, PLL min = %u, PLL max = %u\012\000"
	.align	2
.LC1:
	.ascii	"ref_div = %d, ref_clk = %d, output_freq = %d\012\000"
	.align	2
.LC2:
	.ascii	"post div = 0x%x\012\000"
	.align	2
.LC3:
	.ascii	"fb_div = 0x%x\012\000"
	.align	2
.LC4:
	.ascii	"ppll_div_3 = 0x%x\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	radeon_calc_pll_regs, %function
radeon_calc_pll_regs:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	ldr	r3, [r0, #20]
	push	{r4, r5, r6, r7, r8, r9, r10, lr}
	cmp	r3, #0
	mov	r5, r0
	mov	r7, r1
	mov	r6, r2
	bne	.L2
.L4:
	mov	r4, #0
.L3:
	ldr	r3, [r5, #4]
	ldr	r2, [r5, #8]
	cmp	r3, r6
	movcc	r6, r3
	add	r1, r6, r6, lsl #1
	cmp	r2, r1, lsl #2
	ldrhi	r6, .L35
	ldr	r0, .L35+4
	umullhi	r1, r6, r2, r6
	lsrhi	r6, r6, #3
	mov	r1, r6
	bl	pr_debug
	ldr	r3, .L35+8
	mov	r0, #0
	mov	r9, r3
	mov	r2, #1
	mov	r1, r3
	ldr	r8, .L35+12
	str	r3, [r8]
.L14:
	cmp	r4, #0
	mul	r3, r6, r2
	beq	.L11
	tst	r2, #1
	bne	.L12
.L11:
	ldr	r2, [r5, #8]
	cmp	r3, r2
	bcc	.L12
	ldr	r2, [r5, #4]
	cmp	r3, r2
	bls	.L13
.L12:
	ldr	r2, [r1, #8]!
	mov	r0, #1
	cmp	r2, #0
	bne	.L14
	ldr	r2, [r1, #4]
	ldr	r3, [r9, r2, lsl #3]
	add	r2, r9, r2, lsl #3
	mul	r4, r3, r6
	str	r2, [r8]
.L18:
	mov	r3, r4
	ldr	r2, [r5, #16]
	ldr	r1, [r5, #12]
	ldr	r0, .L35+16
	bl	pr_debug
	ldr	r3, [r8]
	ldr	r1, [r5, #12]
	ldr	r2, [r3]
	ldr	r0, .L35+16
	cmp	r2, #0
	ldreq	r2, [r3, #4]
	ldreq	r3, [r9, r2, lsl #3]
	addeq	r9, r9, r2, lsl #3
	muleq	r4, r3, r6
	ldr	r2, [r5, #16]
	mov	r3, r4
	streq	r9, [r8]
	bl	pr_debug
	ldr	r0, [r5, #12]
	ldr	r1, [r5, #16]
	mul	r0, r4, r0
	bl	round_div
	mov	r4, r0
	ldr	r2, [r8]
	ldr	r3, [r5, #12]
	ldr	r1, [r2, #4]
	str	r3, [r7]
	orr	r3, r0, r1, lsl #16
	str	r3, [r7, #4]
	ldr	r0, .L35+20
	bl	pr_debug
	mov	r1, r4
	ldr	r0, .L35+24
	bl	pr_debug
	ldr	r1, [r7, #4]
	ldr	r0, .L35+28
	pop	{r4, r5, r6, r7, r8, r9, r10, lr}
	b	pr_debug
.L2:
	ldr	r3, .L35+32
	ldr	r0, [r3]
	bl	INREG
	ldr	r3, .L35+36
	mov	r4, r0
	ldr	r3, [r3]
	tst	r0, r3
	beq	.L4
	ldr	r3, .L35+40
	ldr	r2, [r5]
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L8
	mov	r0, r5
	bl	IS_R300_VARIANT
	cmp	r0, #0
	beq	.L33
.L8:
	asr	r4, r4, #10
	and	r4, r4, #3
	cmp	r4, #3
	beq	.L34
.L7:
	subs	r4, r4, #1
	movne	r4, #1
	b	.L3
.L13:
	cmp	r0, #0
	mov	r4, r3
	strne	r1, [r8]
	b	.L18
.L33:
	asr	r4, r4, #13
	and	r4, r4, #1
	b	.L7
.L34:
	ldr	r3, .L35+44
	ldr	r0, [r3]
	bl	INREG
	asr	r4, r0, #12
	and	r4, r4, #3
	b	.L7
.L36:
	.align	2
.L35:
	.word	-1431655765
	.word	.LC0
	.word	.LANCHOR1
	.word	.LANCHOR0
	.word	.LC1
	.word	.LC2
	.word	.LC3
	.word	.LC4
	.word	FP2_GEN_CNTL
	.word	FP2_ON
	.word	CHIP_FAMILY_R200
	.word	DISP_OUTPUT_CNTL
	.size	radeon_calc_pll_regs, .-radeon_calc_pll_regs
	.comm	FP2_ON,4,4
	.comm	FP2_GEN_CNTL,4,4
	.comm	DISP_OUTPUT_CNTL,4,4
	.comm	CHIP_FAMILY_R200,4,4
	.section	.rodata
	.align	2
	.set	.LANCHOR1,. + 0
	.type	post_divs.4236, %object
	.size	post_divs.4236, 72
post_divs.4236:
	.word	1
	.word	0
	.word	2
	.word	1
	.word	4
	.word	2
	.word	8
	.word	3
	.word	3
	.word	4
	.word	16
	.word	5
	.word	6
	.word	6
	.word	12
	.word	7
	.word	0
	.word	0
	.bss
	.align	2
	.set	.LANCHOR0,. + 0
	.type	post_div.4235, %object
	.size	post_div.4235, 4
post_div.4235:
	.space	4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
