	.file	"extr_sdma_v3_0.c_sdma_v3_0_update_sdma_medium_grain_clock_gating.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	sdma_v3_0_update_sdma_medium_grain_clock_gating, @function
sdma_v3_0_update_sdma_medium_grain_clock_gating:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	mov	rbx, rdi
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	mov	eax, DWORD PTR 4[rdi]
	test	esi, esi
	je	.L4
	mov	edx, DWORD PTR [rdi]
	test	DWORD PTR AMD_CG_SUPPORT_SDMA_MGCG[rip], edx
	je	.L4
	test	eax, eax
	jle	.L1
	xor	ebp, ebp
	.p2align 4,,10
	.p2align 3
.L7:
	mov	rax, QWORD PTR sdma_offsets[rip]
	mov	rdi, QWORD PTR mmSDMA0_CLK_CTRL[rip]
	add	rdi, QWORD PTR [rax+rbp*8]
	call	RREG32@PLT
	mov	esi, DWORD PTR SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK[rip]
	or	esi, DWORD PTR SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK[rip]
	or	esi, DWORD PTR SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK[rip]
	or	esi, DWORD PTR SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK[rip]
	or	esi, DWORD PTR SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK[rip]
	or	esi, DWORD PTR SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK[rip]
	or	esi, DWORD PTR SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK[rip]
	or	esi, DWORD PTR SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK[rip]
	not	esi
	and	esi, eax
	cmp	eax, esi
	je	.L6
	mov	rax, QWORD PTR sdma_offsets[rip]
	mov	rdi, QWORD PTR mmSDMA0_CLK_CTRL[rip]
	add	rdi, QWORD PTR [rax+rbp*8]
	call	WREG32@PLT
.L6:
	add	rbp, 1
	cmp	DWORD PTR 4[rbx], ebp
	jg	.L7
.L1:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L4:
	.cfi_restore_state
	xor	ebp, ebp
	test	eax, eax
	jle	.L1
	.p2align 4,,10
	.p2align 3
.L3:
	mov	rax, QWORD PTR sdma_offsets[rip]
	mov	rdi, QWORD PTR mmSDMA0_CLK_CTRL[rip]
	add	rdi, QWORD PTR [rax+rbp*8]
	call	RREG32@PLT
	mov	esi, DWORD PTR SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK[rip]
	or	esi, DWORD PTR SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK[rip]
	or	esi, DWORD PTR SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK[rip]
	or	esi, DWORD PTR SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK[rip]
	or	esi, DWORD PTR SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK[rip]
	or	esi, DWORD PTR SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK[rip]
	or	esi, DWORD PTR SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK[rip]
	or	esi, DWORD PTR SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK[rip]
	or	esi, eax
	cmp	eax, esi
	je	.L8
	mov	rax, QWORD PTR sdma_offsets[rip]
	mov	rdi, QWORD PTR mmSDMA0_CLK_CTRL[rip]
	add	rdi, QWORD PTR [rax+rbp*8]
	call	WREG32@PLT
.L8:
	add	rbp, 1
	cmp	DWORD PTR 4[rbx], ebp
	jg	.L3
	add	rsp, 8
	.cfi_def_cfa_offset 24
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE0:
	.size	sdma_v3_0_update_sdma_medium_grain_clock_gating, .-sdma_v3_0_update_sdma_medium_grain_clock_gating
	.comm	sdma_offsets,8,8
	.comm	mmSDMA0_CLK_CTRL,8,8
	.comm	SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK,4,4
	.comm	SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK,4,4
	.comm	SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK,4,4
	.comm	SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK,4,4
	.comm	SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK,4,4
	.comm	SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK,4,4
	.comm	SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK,4,4
	.comm	SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK,4,4
	.comm	AMD_CG_SUPPORT_SDMA_MGCG,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_sdma_v3_0.c_sdma_v3_0_update_sdma_medium_grain_clock_gating.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	sdma_v3_0_update_sdma_medium_grain_clock_gating, %function
sdma_v3_0_update_sdma_medium_grain_clock_gating:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	cmp	r1, #0
	mov	r5, r0
	ldr	r3, [r0, #4]
	sub	sp, sp, #20
	beq	.L4
	ldr	r2, .L17
	ldr	r1, [r0]
	ldr	r2, [r2]
	tst	r1, r2
	beq	.L4
	cmp	r3, #0
	ble	.L1
	ldr	r3, .L17+4
	ldr	r6, .L17+8
	str	r3, [sp, #4]
	ldr	r3, .L17+12
	ldr	r7, .L17+16
	str	r3, [sp, #8]
	ldr	r3, .L17+20
	mov	r4, #0
	str	r3, [sp, #12]
	ldr	r3, .L17+24
	ldr	fp, .L17+28
	str	r3, [sp]
	mov	r3, r6
	mov	r6, r7
	mov	r7, r3
	ldr	r10, .L17+32
	ldr	r9, .L17+36
	ldr	r8, .L17+40
.L7:
	ldr	r0, [r6]
	ldr	r1, [r7]
	ldr	r0, [r0, r4, lsl #2]
	add	r0, r0, r1
	bl	RREG32
	ldr	ip, [r10]
	ldr	r1, [fp]
	ldr	lr, [r9]
	ldr	r3, [sp, #4]
	orr	r1, r1, ip
	orr	r1, r1, lr
	ldr	ip, [r8]
	ldr	lr, [r3]
	ldr	r3, [sp, #8]
	orr	r1, r1, ip
	ldr	ip, [r3]
	ldr	r3, [sp, #12]
	orr	r1, r1, lr
	ldr	lr, [r3]
	ldr	r3, [sp]
	orr	r1, r1, ip
	ldr	ip, [r3]
	orr	r1, r1, lr
	orr	r1, r1, ip
	tst	r1, r0
	bic	r1, r0, r1
	beq	.L6
	ldr	ip, [r6]
	ldr	r0, [r7]
	ldr	ip, [ip, r4, lsl #2]
	add	r0, ip, r0
	bl	WREG32
.L6:
	ldr	r1, [r5, #4]
	add	r4, r4, #1
	cmp	r1, r4
	bgt	.L7
.L1:
	add	sp, sp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L4:
	cmp	r3, #0
	ble	.L1
	ldr	r3, .L17+4
	ldr	r6, .L17+8
	str	r3, [sp, #4]
	ldr	r3, .L17+12
	ldr	r7, .L17+16
	str	r3, [sp, #8]
	ldr	r3, .L17+20
	mov	r4, #0
	str	r3, [sp, #12]
	ldr	r3, .L17+24
	ldr	fp, .L17+28
	str	r3, [sp]
	mov	r3, r6
	mov	r6, r7
	mov	r7, r3
	ldr	r10, .L17+32
	ldr	r9, .L17+36
	ldr	r8, .L17+40
.L3:
	ldr	r0, [r6]
	ldr	r1, [r7]
	ldr	r0, [r0, r4, lsl #2]
	add	r0, r0, r1
	bl	RREG32
	ldr	ip, [r10]
	ldr	r1, [fp]
	ldr	lr, [r9]
	ldr	r3, [sp, #4]
	orr	r1, r1, ip
	orr	r1, r1, lr
	ldr	ip, [r8]
	ldr	lr, [r3]
	ldr	r3, [sp, #8]
	orr	r1, r1, ip
	ldr	ip, [r3]
	ldr	r3, [sp, #12]
	orr	r1, r1, lr
	ldr	lr, [r3]
	ldr	r3, [sp]
	orr	r1, r1, ip
	ldr	ip, [r3]
	orr	r1, r1, lr
	orr	r1, r1, ip
	bics	r3, r1, r0
	orr	r1, r1, r0
	beq	.L8
	ldr	ip, [r6]
	ldr	r0, [r7]
	ldr	ip, [ip, r4, lsl #2]
	add	r0, ip, r0
	bl	WREG32
.L8:
	ldr	r1, [r5, #4]
	add	r4, r4, #1
	cmp	r1, r4
	bgt	.L3
	add	sp, sp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L18:
	.align	2
.L17:
	.word	AMD_CG_SUPPORT_SDMA_MGCG
	.word	SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK
	.word	mmSDMA0_CLK_CTRL
	.word	SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK
	.word	sdma_offsets
	.word	SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK
	.word	SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK
	.word	SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK
	.word	SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK
	.word	SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK
	.word	SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK
	.size	sdma_v3_0_update_sdma_medium_grain_clock_gating, .-sdma_v3_0_update_sdma_medium_grain_clock_gating
	.comm	sdma_offsets,4,4
	.comm	mmSDMA0_CLK_CTRL,4,4
	.comm	SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK,4,4
	.comm	SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK,4,4
	.comm	SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK,4,4
	.comm	SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK,4,4
	.comm	SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK,4,4
	.comm	SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK,4,4
	.comm	SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK,4,4
	.comm	SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK,4,4
	.comm	AMD_CG_SUPPORT_SDMA_MGCG,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
