	.file	"extr_reload.c_combine_reloads.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	combine_reloads, @function
combine_reloads:
.LFB0:
	.cfi_startproc
	endbr64
	mov	ecx, DWORD PTR n_reloads[rip]
	test	ecx, ecx
	jle	.L87
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xor	eax, eax
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	ebx, -1
	sub	rsp, 8
	.cfi_def_cfa_offset 64
	mov	rsi, QWORD PTR rld[rip]
	mov	rdx, rsi
	.p2align 4,,10
	.p2align 3
.L6:
	cmp	QWORD PTR [rdx], 0
	je	.L4
	cmp	ebx, -1
	jne	.L1
	mov	ebx, eax
.L4:
	add	eax, 1
	add	rdx, 96
	cmp	eax, ecx
	jne	.L6
	cmp	ebx, -1
	je	.L1
	movsx	rax, ebx
	lea	r13, [rax+rax*2]
	sal	r13, 5
	add	rsi, r13
	cmp	QWORD PTR 88[rsi], 0
	jne	.L1
	cmp	QWORD PTR 8[rsi], 0
	je	.L91
.L1:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L91:
	.cfi_restore_state
	mov	rdi, QWORD PTR [rsi]
	call	earlyclobber_operand_p@PLT
	test	rax, rax
	jne	.L1
	mov	ecx, DWORD PTR n_reloads[rip]
	test	ecx, ecx
	jle	.L7
	sub	ecx, 1
	mov	rdx, QWORD PTR rld[rip]
	mov	rsi, QWORD PTR RELOAD_FOR_OUTPUT_ADDRESS[rip]
	lea	rcx, [rcx+rcx*2]
	mov	r8, QWORD PTR RELOAD_FOR_OUTADDR_ADDRESS[rip]
	sal	rcx, 5
	lea	r9, [rdx+r13]
	lea	rax, 16[rdx]
	lea	rdi, 112[rdx+rcx]
	jmp	.L10
	.p2align 4,,10
	.p2align 3
.L93:
	cmp	rcx, r8
	je	.L8
.L9:
	add	rax, 96
	cmp	rdi, rax
	je	.L92
.L10:
	mov	rcx, QWORD PTR [rax]
	cmp	rcx, rsi
	jne	.L93
.L8:
	mov	rcx, QWORD PTR 24[r9]
	cmp	QWORD PTR 8[rax], rcx
	jne	.L9
	jmp	.L1
.L92:
	xor	ebp, ebp
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L95:
	mov	rdx, QWORD PTR rld[rip]
.L24:
	lea	r12, 0[rbp+rbp*2]
	mov	r14d, ebp
	sal	r12, 5
	lea	rax, [rdx+r12]
	cmp	QWORD PTR 8[rax], 0
	je	.L11
	cmp	QWORD PTR 88[rax], 0
	jne	.L11
	mov	edx, DWORD PTR 84[rax]
	test	edx, edx
	jne	.L11
	mov	rdx, QWORD PTR 16[rax]
	cmp	rdx, QWORD PTR RELOAD_FOR_OUTPUT_ADDRESS[rip]
	je	.L11
	cmp	rdx, QWORD PTR RELOAD_FOR_OUTADDR_ADDRESS[rip]
	je	.L11
	cmp	rdx, QWORD PTR RELOAD_OTHER[rip]
	jne	.L94
	.p2align 4,,10
	.p2align 3
.L11:
	add	rbp, 1
	cmp	DWORD PTR n_reloads[rip], ebp
	jg	.L95
.L7:
	mov	edi, DWORD PTR this_insn[rip]
	call	INSN_CODE@PLT
	cmp	rax, -1
	je	.L1
	mov	ebx, 8
	mov	ebp, 1
	jmp	.L25
	.p2align 4,,10
	.p2align 3
.L26:
	mov	edi, DWORD PTR this_insn[rip]
	mov	r12, QWORD PTR insn_data[rip]
	call	INSN_CODE@PLT
	sal	rax, 4
	mov	rax, QWORD PTR 8[r12+rax]
	mov	rax, QWORD PTR [rax+rbx]
	cmp	BYTE PTR [rax], 61
	je	.L1
	mov	edi, DWORD PTR this_insn[rip]
	mov	r12, QWORD PTR insn_data[rip]
	call	INSN_CODE@PLT
	sal	rax, 4
	mov	rax, QWORD PTR 8[r12+rax]
	mov	rax, QWORD PTR [rax+rbx]
	add	rbx, 8
	cmp	BYTE PTR [rax], 43
	je	.L1
	add	ebp, 1
.L25:
	mov	edi, DWORD PTR this_insn[rip]
	mov	r12, QWORD PTR insn_data[rip]
	call	INSN_CODE@PLT
	sal	rax, 4
	cmp	DWORD PTR [r12+rax], ebp
	jg	.L26
	mov	edi, DWORD PTR this_insn[rip]
	call	REG_NOTES@PLT
	mov	rbp, rax
	test	rax, rax
	jne	.L33
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L27:
	mov	rdi, rbp
	mov	esi, 1
	call	XEXP@PLT
	mov	rbp, rax
	test	rax, rax
	je	.L1
.L33:
	mov	rdi, rbp
	call	REG_NOTE_KIND@PLT
	cmp	rax, QWORD PTR REG_DEAD[rip]
	jne	.L27
	xor	esi, esi
	mov	rdi, rbp
	call	XEXP@PLT
	mov	rdi, rax
	call	REG_P@PLT
	test	rax, rax
	je	.L27
	mov	rax, QWORD PTR rld[rip]
	xor	esi, esi
	mov	rdi, rbp
	mov	r12, QWORD PTR [rax+r13]
	call	XEXP@PLT
	mov	rdi, rax
	mov	rsi, r12
	call	reg_overlap_mentioned_for_reload_p@PLT
	test	rax, rax
	jne	.L27
	xor	esi, esi
	mov	rdi, rbp
	call	XEXP@PLT
	mov	rdi, rax
	call	REGNO@PLT
	cmp	rax, QWORD PTR FIRST_PSEUDO_REGISTER[rip]
	jnb	.L27
	mov	rax, QWORD PTR rld[rip]
	xor	esi, esi
	mov	rdi, rbp
	mov	r12, QWORD PTR 48[rax+r13]
	call	XEXP@PLT
	mov	rdi, rax
	call	REGNO@PLT
	mov	rsi, r12
	mov	rdi, rax
	call	HARD_REGNO_MODE_OK@PLT
	test	rax, rax
	je	.L27
	xor	esi, esi
	mov	rdi, rbp
	call	XEXP@PLT
	mov	rdi, rax
	call	REGNO@PLT
	mov	rsi, rax
	mov	rax, QWORD PTR rld[rip]
	movsx	rdx, DWORD PTR 32[rax+r13]
	mov	rax, QWORD PTR reg_class_contents[rip]
	mov	edi, DWORD PTR [rax+rdx*4]
	call	TEST_HARD_REG_BIT@PLT
	test	rax, rax
	je	.L27
	xor	esi, esi
	mov	rdi, rbp
	mov	rbx, QWORD PTR hard_regno_nregs[rip]
	call	XEXP@PLT
	mov	rdi, rax
	call	REGNO@PLT
	mov	rdx, QWORD PTR rld[rip]
	xor	esi, esi
	mov	rdi, rbp
	mov	rax, QWORD PTR [rbx+rax*8]
	mov	rbx, QWORD PTR hard_regno_nregs[rip]
	mov	rdx, QWORD PTR 48[rdx+r13]
	mov	r12, QWORD PTR [rax+rdx*8]
	call	XEXP@PLT
	mov	rdi, rax
	call	REGNO@PLT
	xor	esi, esi
	mov	rdi, rbp
	mov	rbx, QWORD PTR [rbx+rax*8]
	call	XEXP@PLT
	mov	rdi, rax
	call	GET_MODE@PLT
	cmp	r12, QWORD PTR [rbx+rax*8]
	jg	.L27
	mov	rax, QWORD PTR rld[rip]
	movsx	rbx, DWORD PTR 72[rax+r13]
	cmp	ebx, -1
	je	.L30
	xor	esi, esi
	imul	rbx, rbx, 96
	mov	rdi, rbp
	call	XEXP@PLT
	mov	rdi, rax
	call	REGNO@PLT
	mov	rsi, rax
	mov	rax, QWORD PTR rld[rip]
	movsx	rdx, DWORD PTR 32[rax+rbx]
	mov	rax, QWORD PTR reg_class_contents[rip]
	mov	edi, DWORD PTR [rax+rdx*4]
	call	TEST_HARD_REG_BIT@PLT
	test	rax, rax
	jne	.L27
	mov	rax, QWORD PTR rld[rip]
	mov	ebx, DWORD PTR 72[rax+rbx]
	cmp	ebx, -1
	je	.L30
	xor	esi, esi
	mov	rdi, rbp
	call	XEXP@PLT
	mov	rdi, rax
	call	REGNO@PLT
	mov	rsi, rax
	movsx	rax, ebx
	imul	rax, rax, 96
	add	rax, QWORD PTR rld[rip]
	movsx	rdx, DWORD PTR 32[rax]
	mov	rax, QWORD PTR reg_class_contents[rip]
	mov	edi, DWORD PTR [rax+rdx*4]
	call	TEST_HARD_REG_BIT@PLT
	test	rax, rax
	jne	.L27
.L30:
	xor	esi, esi
	mov	rdi, rbp
	mov	rbx, QWORD PTR fixed_regs[rip]
	call	XEXP@PLT
	mov	rdi, rax
	call	REGNO@PLT
	cmp	DWORD PTR [rbx+rax*4], 0
	jne	.L27
	xor	esi, esi
	mov	rdi, rbp
	call	XEXP@PLT
	mov	rdi, rax
	call	ORIGINAL_REGNO@PLT
	cmp	rax, QWORD PTR FIRST_PSEUDO_REGISTER[rip]
	jl	.L32
	xor	esi, esi
	mov	rdi, rbp
	call	XEXP@PLT
	mov	rdi, rax
	call	ORIGINAL_REGNO@PLT
	mov	rsi, rax
	mov	rax, QWORD PTR ENTRY_BLOCK_PTR[rip]
	mov	rax, QWORD PTR [rax]
	mov	edi, DWORD PTR [rax]
	call	bitmap_bit_p@PLT
	test	eax, eax
	jne	.L27
.L32:
	xor	esi, esi
	mov	rdi, rbp
	call	XEXP@PLT
	mov	rdi, rax
	call	REGNO@PLT
	add	r13, QWORD PTR rld[rip]
	mov	rdi, QWORD PTR 48[r13]
	mov	rsi, rax
	call	gen_rtx_REG@PLT
	mov	QWORD PTR 64[r13], rax
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L87:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	.cfi_restore 6
	.cfi_restore 12
	.cfi_restore 13
	.cfi_restore 14
	.cfi_restore 15
	ret
.L94:
	.cfi_def_cfa_offset 64
	.cfi_offset 3, -56
	.cfi_offset 6, -48
	.cfi_offset 12, -40
	.cfi_offset 13, -32
	.cfi_offset 14, -24
	.cfi_offset 15, -16
	mov	rsi, QWORD PTR 40[rax]
	mov	rdi, QWORD PTR 32[rax]
	call	CLASS_MAX_NREGS@PLT
	mov	r15, rax
	mov	rax, QWORD PTR rld[rip]
	add	rax, r13
	mov	rsi, QWORD PTR 48[rax]
	mov	rdi, QWORD PTR 32[rax]
	call	CLASS_MAX_NREGS@PLT
	cmp	r15, rax
	jne	.L11
	mov	rdx, QWORD PTR rld[rip]
	lea	rax, [rdx+r12]
	cmp	QWORD PTR 56[rax], 0
	jne	.L11
	cmp	QWORD PTR 64[rax], 0
	jne	.L11
	cmp	QWORD PTR SMALL_REGISTER_CLASSES[rip], 0
	mov	rsi, QWORD PTR 32[rdx+r13]
	mov	rdi, QWORD PTR 32[rax]
	je	.L12
	cmp	rsi, rdi
	sete	al
.L13:
	test	al, al
	je	.L11
	mov	rax, QWORD PTR rld[rip]
	mov	rsi, QWORD PTR [rax+r13]
	mov	rdi, QWORD PTR 8[rax+r12]
	call	MATCHES@PLT
	test	rax, rax
	jne	.L17
	mov	rax, QWORD PTR rld[rip]
	mov	rsi, QWORD PTR 8[rax+r12]
	mov	rdi, QWORD PTR [rax+r13]
	call	reg_overlap_mentioned_for_reload_p@PLT
	test	rax, rax
	jne	.L11
	mov	rax, QWORD PTR rld[rip]
	mov	rdi, QWORD PTR 8[rax+r12]
	call	REG_P@PLT
	test	rax, rax
	jne	.L96
.L17:
	mov	rax, QWORD PTR rld[rip]
	mov	rdi, QWORD PTR RELOAD_FOR_INPUT[rip]
	xor	edx, edx
	add	rax, r12
	cmp	QWORD PTR 16[rax], rdi
	mov	rsi, QWORD PTR 40[rax]
	mov	rdi, QWORD PTR 8[rax]
	setne	dl
	call	reload_inner_reg_of_subreg@PLT
	test	eax, eax
	jne	.L11
	mov	rax, QWORD PTR rld[rip]
	mov	rcx, QWORD PTR reg_class_size[rip]
	lea	rdx, [rax+r12]
	mov	rsi, QWORD PTR 32[rdx]
	movsx	rdi, esi
	mov	rcx, QWORD PTR [rcx+rdi*8]
	or	rcx, QWORD PTR SMALL_REGISTER_CLASSES[rip]
	je	.L11
	mov	rcx, QWORD PTR 16[rdx]
	cmp	rcx, QWORD PTR RELOAD_FOR_INPUT[rip]
	je	.L18
	cmp	rcx, QWORD PTR RELOAD_FOR_OUTPUT[rip]
	jne	.L11
.L18:
	add	rax, r13
	mov	rcx, QWORD PTR [rax]
	mov	QWORD PTR [rdx], rcx
	mov	ecx, DWORD PTR 80[rax]
	mov	DWORD PTR 80[rdx], ecx
	mov	rcx, QWORD PTR 48[rax]
	mov	QWORD PTR 48[rdx], rcx
	mov	rcx, QWORD PTR RELOAD_OTHER[rip]
	mov	QWORD PTR [rax], 0
	mov	QWORD PTR 16[rdx], rcx
	mov	ecx, DWORD PTR 72[rax]
	cmp	ecx, -1
	je	.L19
	mov	DWORD PTR 72[rdx], ecx
	mov	ecx, DWORD PTR 76[rax]
	mov	DWORD PTR 76[rdx], ecx
.L19:
	mov	rdi, QWORD PTR 32[rax]
	call	reg_class_subset_p@PLT
	test	rax, rax
	je	.L20
	mov	rax, QWORD PTR rld[rip]
	mov	rdx, QWORD PTR 32[rax+r13]
	mov	QWORD PTR 32[rax+r12], rdx
.L20:
	mov	rdx, QWORD PTR replacements[rip]
	xor	eax, eax
	jmp	.L22
.L23:
	cmp	DWORD PTR [rdx+rax*4], ebx
	jne	.L21
	mov	DWORD PTR [rdx+rax*4], r14d
.L21:
	add	rax, 1
.L22:
	cmp	DWORD PTR n_replacements[rip], eax
	jg	.L23
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L12:
	call	reg_class_subset_p@PLT
	mov	r8, rax
	mov	eax, 1
	test	r8, r8
	je	.L97
.L14:
	and	eax, 1
	jmp	.L13
.L96:
	mov	rax, QWORD PTR rld[rip]
	mov	rsi, QWORD PTR [rax+r13]
	mov	rdi, QWORD PTR 8[rax+r12]
	call	reg_overlap_mentioned_for_reload_p@PLT
	test	rax, rax
	je	.L17
	jmp	.L11
.L97:
	mov	rax, QWORD PTR rld[rip]
	mov	rsi, QWORD PTR 32[rax+r12]
	mov	rdi, QWORD PTR 32[rax+r13]
	call	reg_class_subset_p@PLT
	test	rax, rax
	setne	al
	movzx	eax, al
	jmp	.L14
	.cfi_endproc
.LFE0:
	.size	combine_reloads, .-combine_reloads
	.comm	this_insn,4,4
	.comm	secondary_memlocs_elim,8,8
	.comm	rld,8,8
	.comm	replacements,8,8
	.comm	reg_class_size,8,8
	.comm	reg_class_contents,8,8
	.comm	n_replacements,4,4
	.comm	n_reloads,4,4
	.comm	insn_data,8,8
	.comm	hard_regno_nregs,8,8
	.comm	fixed_regs,8,8
	.comm	SMALL_REGISTER_CLASSES,8,8
	.comm	RELOAD_OTHER,8,8
	.comm	RELOAD_FOR_OUTPUT_ADDRESS,8,8
	.comm	RELOAD_FOR_OUTPUT,8,8
	.comm	RELOAD_FOR_OUTADDR_ADDRESS,8,8
	.comm	RELOAD_FOR_INPUT,8,8
	.comm	REG_DEAD,8,8
	.comm	FIRST_PSEUDO_REGISTER,8,8
	.comm	ENTRY_BLOCK_PTR,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_reload.c_combine_reloads.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	combine_reloads, %function
combine_reloads:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r7, .L105
	sub	sp, sp, #12
	ldr	r0, [r7]
	cmp	r0, #0
	ble	.L1
	ldr	r6, .L105+4
	mvn	r4, #0
	ldr	ip, [r6]
	mov	r3, #0
	mov	r2, ip
.L6:
	ldr	r1, [r2]
	add	r2, r2, #56
	cmp	r1, #0
	beq	.L4
	cmn	r4, #1
	bne	.L1
	mov	r4, r3
.L4:
	add	r3, r3, #1
	cmp	r3, r0
	bne	.L6
	cmn	r4, #1
	beq	.L1
	rsb	r8, r4, r4, lsl #3
	add	r3, ip, r8, lsl #3
	ldr	r2, [r3, #52]
	lsl	r8, r8, #3
	cmp	r2, #0
	bne	.L1
	ldr	r3, [r3, #4]
	cmp	r3, #0
	beq	.L98
.L1:
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L98:
	ldr	r0, [ip, r8]
	bl	earlyclobber_operand_p
	subs	r5, r0, #0
	bne	.L1
	ldr	r0, [r7]
	cmp	r0, #0
	ble	.L7
	ldr	ip, .L105+8
	ldr	r3, [r6]
	ldr	r9, [ip]
	ldr	ip, .L105+12
	mov	r1, r5
	mov	r2, r3
	ldr	r10, [ip]
	add	fp, r3, r8
	b	.L10
.L100:
	cmp	ip, r10
	beq	.L8
.L9:
	cmp	r1, r0
	add	r2, r2, #56
	beq	.L99
.L10:
	ldr	ip, [r2, #8]
	add	r1, r1, #1
	cmp	ip, r9
	bne	.L100
.L8:
	ldr	lr, [r2, #12]
	ldr	ip, [fp, #12]
	cmp	lr, ip
	bne	.L9
	b	.L1
.L99:
	ldr	r9, .L105+16
	ldr	fp, .L105+20
	b	.L24
.L102:
	ldr	r3, [r6]
.L24:
	rsb	r2, r5, r5, lsl #3
	add	r3, r3, r2, lsl #3
	ldr	r1, [r3, #4]
	lsl	r10, r2, #3
	cmp	r1, #0
	beq	.L11
	ldr	r2, [r3, #52]
	cmp	r2, #0
	bne	.L11
	ldr	r2, [r3, #48]
	cmp	r2, #0
	bne	.L11
	ldr	r1, .L105+8
	ldr	r2, [r3, #8]
	ldr	r1, [r1]
	cmp	r2, r1
	beq	.L11
	ldr	r1, .L105+12
	ldr	r1, [r1]
	cmp	r2, r1
	beq	.L11
	ldr	r1, [r9]
	cmp	r2, r1
	bne	.L101
.L11:
	ldr	r3, [r7]
	add	r5, r5, #1
	cmp	r3, r5
	bgt	.L102
.L7:
	ldr	r7, .L105+24
	ldr	r0, [r7]
	bl	INSN_CODE
	cmn	r0, #1
	beq	.L1
	mov	r4, #1
	ldr	r9, .L105+28
	b	.L25
.L26:
	ldr	r5, [r9]
	bl	INSN_CODE
	add	r5, r5, r0, lsl #3
	ldr	r3, [r5, #4]
	ldr	r3, [r3, r4, lsl #2]
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #61
	beq	.L1
	ldr	r0, [r7]
	ldr	r5, [r9]
	bl	INSN_CODE
	add	r5, r5, r0, lsl #3
	ldr	r3, [r5, #4]
	ldr	r3, [r3, r4, lsl #2]
	add	r4, r4, #1
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #43
	beq	.L1
.L25:
	ldr	r0, [r7]
	ldr	r5, [r9]
	bl	INSN_CODE
	ldr	r3, [r5, r0, lsl #3]
	ldr	r0, [r7]
	cmp	r3, r4
	bgt	.L26
	bl	REG_NOTES
	subs	r4, r0, #0
	beq	.L1
	ldr	r5, .L105+32
	ldr	r10, .L105+36
	ldr	r7, .L105+40
	ldr	r9, .L105+44
	b	.L33
.L27:
	mov	r0, r4
	mov	r1, #1
	bl	XEXP
	subs	r4, r0, #0
	beq	.L1
.L33:
	mov	r0, r4
	bl	REG_NOTE_KIND
	ldr	r3, [r5]
	cmp	r0, r3
	bne	.L27
	mov	r1, #0
	mov	r0, r4
	bl	XEXP
	bl	REG_P
	cmp	r0, #0
	beq	.L27
	mov	r1, #0
	mov	r0, r4
	bl	XEXP
	ldr	r3, [r6]
	ldr	r1, [r3, r8]
	bl	reg_overlap_mentioned_for_reload_p
	subs	fp, r0, #0
	bne	.L27
	mov	r1, fp
	mov	r0, r4
	bl	XEXP
	bl	REGNO
	ldr	r3, [r10]
	cmp	r0, r3
	bcs	.L27
	mov	r1, fp
	mov	r0, r4
	bl	XEXP
	bl	REGNO
	ldr	r3, [r6]
	add	r3, r3, r8
	ldr	r1, [r3, #24]
	bl	HARD_REGNO_MODE_OK
	cmp	r0, #0
	beq	.L27
	ldr	r3, [r6]
	ldr	r2, [r7]
	add	r3, r3, r8
	ldr	r3, [r3, #16]
	mov	r1, fp
	ldr	r3, [r2, r3, lsl #2]
	mov	r0, r4
	str	r3, [sp]
	bl	XEXP
	bl	REGNO
	ldr	r3, [sp]
	mov	r1, r0
	mov	r0, r3
	bl	TEST_HARD_REG_BIT
	cmp	r0, #0
	beq	.L27
	ldr	r2, [r9]
	mov	r1, fp
	mov	r0, r4
	str	r2, [sp]
	bl	XEXP
	bl	REGNO
	ldr	r3, [r6]
	ldr	r2, [sp]
	add	r3, r3, r8
	ldr	r2, [r2, r0, lsl #2]
	ldr	r3, [r3, #24]
	mov	r1, fp
	ldr	r2, [r2, r3, lsl #2]
	ldr	r3, [r9]
	mov	r0, r4
	str	r2, [sp, #4]
	str	r3, [sp]
	bl	XEXP
	bl	REGNO
	mov	ip, r0
	ldr	r3, [sp]
	mov	r1, fp
	ldr	r3, [r3, ip, lsl #2]
	mov	r0, r4
	str	r3, [sp]
	bl	XEXP
	bl	GET_MODE
	ldr	r3, [sp]
	ldr	r2, [sp, #4]
	ldr	r3, [r3, r0, lsl #2]
	cmp	r2, r3
	bgt	.L27
	ldr	r2, [r6]
	add	r3, r2, r8
	ldr	r3, [r3, #36]
	cmn	r3, #1
	beq	.L30
	mov	r1, #56
	mul	r3, r1, r3
	add	r2, r2, r3
	ldr	ip, [r2, #16]
	ldr	r2, [r7]
	mov	r1, fp
	mov	r0, r4
	ldr	fp, [r2, ip, lsl #2]
	str	r3, [sp]
	bl	XEXP
	bl	REGNO
	mov	r1, r0
	mov	r0, fp
	bl	TEST_HARD_REG_BIT
	cmp	r0, #0
	bne	.L27
	ldr	r2, [r6]
	ldr	r3, [sp]
	add	r3, r2, r3
	ldr	r3, [r3, #36]
	cmn	r3, #1
	beq	.L30
	mov	r1, #56
	mla	r3, r1, r3, r2
	ldr	r2, [r7]
	ldr	r3, [r3, #16]
	mov	r1, #0
	mov	r0, r4
	ldr	fp, [r2, r3, lsl #2]
	bl	XEXP
	bl	REGNO
	mov	r1, r0
	mov	r0, fp
	bl	TEST_HARD_REG_BIT
	cmp	r0, #0
	bne	.L27
.L30:
	ldr	r3, .L105+48
	mov	r1, #0
	mov	r0, r4
	ldr	fp, [r3]
	bl	XEXP
	bl	REGNO
	ldr	fp, [fp, r0, lsl #2]
	cmp	fp, #0
	bne	.L27
	mov	r1, fp
	mov	r0, r4
	bl	XEXP
	bl	ORIGINAL_REGNO
	ldr	r3, [r10]
	cmp	r0, r3
	blt	.L32
	ldr	r3, .L105+52
	mov	r1, fp
	ldr	r3, [r3]
	mov	r0, r4
	ldr	r3, [r3]
	ldr	fp, [r3]
	bl	XEXP
	bl	ORIGINAL_REGNO
	mov	r1, r0
	mov	r0, fp
	bl	bitmap_bit_p
	cmp	r0, #0
	bne	.L27
.L32:
	ldr	r3, [r6]
	mov	r1, #0
	add	r3, r3, r8
	mov	r0, r4
	ldr	r4, [r3, #24]
	bl	XEXP
	bl	REGNO
	ldr	r3, [r6]
	mov	r1, r0
	mov	r0, r4
	add	r8, r3, r8
	bl	gen_rtx_REG
	str	r0, [r8, #32]
	b	.L1
.L101:
	ldr	r1, [r3, #20]
	ldr	r0, [r3, #16]
	bl	CLASS_MAX_NREGS
	ldr	r3, [r6]
	str	r0, [sp]
	add	r3, r3, r8
	ldr	r1, [r3, #24]
	ldr	r0, [r3, #16]
	bl	CLASS_MAX_NREGS
	ldr	r2, [sp]
	cmp	r2, r0
	bne	.L11
	ldr	r3, [r6]
	add	r2, r3, r10
	ldr	r1, [r2, #28]
	cmp	r1, #0
	bne	.L11
	ldr	r1, [r2, #32]
	cmp	r1, #0
	bne	.L11
	ldr	r1, [fp]
	add	r3, r3, r8
	cmp	r1, #0
	ldr	r0, [r2, #16]
	ldr	r1, [r3, #16]
	beq	.L12
	sub	r0, r0, r1
	clz	r0, r0
	lsr	r0, r0, #5
.L13:
	cmp	r0, #0
	beq	.L11
	ldr	r3, [r6]
	add	r2, r3, r10
	ldr	r0, [r2, #4]
	ldr	r1, [r3, r8]
	bl	MATCHES
	cmp	r0, #0
	bne	.L17
	ldr	r3, [r6]
	add	r2, r3, r10
	ldr	r1, [r2, #4]
	ldr	r0, [r3, r8]
	bl	reg_overlap_mentioned_for_reload_p
	cmp	r0, #0
	bne	.L11
	ldr	r3, [r6]
	add	r3, r3, r10
	ldr	r0, [r3, #4]
	bl	REG_P
	cmp	r0, #0
	bne	.L103
.L17:
	ldr	r3, [r6]
	ldr	r2, .L105+56
	add	r3, r3, r10
	ldr	r0, [r3, #8]
	ldr	r2, [r2]
	ldr	r1, [r3, #20]
	subs	r2, r0, r2
	movne	r2, #1
	ldr	r0, [r3, #4]
	bl	reload_inner_reg_of_subreg
	subs	r3, r0, #0
	bne	.L11
	ldr	r1, [r6]
	ldr	r0, .L105+60
	add	r2, r1, r10
	ldr	ip, [r0]
	ldr	lr, [r2, #16]
	ldr	r0, [fp]
	ldr	ip, [ip, lr, lsl #2]
	orrs	r0, ip, r0
	beq	.L11
	ldr	ip, .L105+56
	ldr	r0, [r2, #8]
	ldr	ip, [ip]
	cmp	r0, ip
	beq	.L18
	ldr	ip, .L105+64
	ldr	ip, [ip]
	cmp	r0, ip
	bne	.L11
.L18:
	ldr	r7, [r9]
	ldr	r9, [r1, r8]
	add	r0, r1, r8
	ldr	ip, [r0, #36]
	ldr	fp, [r0, #44]
	str	r9, [r2]
	ldr	r9, [r0, #24]
	cmn	ip, #1
	str	r9, [r2, #24]
	mov	r9, #0
	str	fp, [r2, #44]
	str	r9, [r1, r8]
	ldrne	r1, [r0, #40]
	str	r7, [r2, #8]
	strne	r1, [r2, #40]
	strne	ip, [r2, #36]
	mov	r1, lr
	ldr	r0, [r0, #16]
	str	r3, [sp]
	bl	reg_class_subset_p
	cmp	r0, #0
	ldr	r3, [sp]
	beq	.L20
	ldr	r2, [r6]
	add	r8, r2, r8
	ldr	r1, [r8, #16]
	add	r2, r2, r10
	str	r1, [r2, #16]
.L20:
	ldr	r2, .L105+68
	ldr	r1, .L105+72
	ldr	r2, [r2]
	b	.L22
.L23:
	ldr	r0, [r2, r3, lsl #2]
	cmp	r0, r4
	streq	r5, [r2, r3, lsl #2]
	add	r3, r3, #1
.L22:
	ldr	r0, [r1]
	cmp	r0, r3
	bgt	.L23
	b	.L1
.L12:
	bl	reg_class_subset_p
	cmp	r0, #0
	movne	r0, #1
	beq	.L104
.L14:
	and	r0, r0, #1
	b	.L13
.L103:
	ldr	r3, [r6]
	add	r2, r3, r10
	ldr	r0, [r2, #4]
	ldr	r1, [r3, r8]
	bl	reg_overlap_mentioned_for_reload_p
	cmp	r0, #0
	beq	.L17
	b	.L11
.L104:
	ldr	r3, [r6]
	add	r2, r3, r10
	add	r3, r3, r8
	ldr	r1, [r2, #16]
	ldr	r0, [r3, #16]
	bl	reg_class_subset_p
	subs	r0, r0, #0
	movne	r0, #1
	b	.L14
.L106:
	.align	2
.L105:
	.word	n_reloads
	.word	rld
	.word	RELOAD_FOR_OUTPUT_ADDRESS
	.word	RELOAD_FOR_OUTADDR_ADDRESS
	.word	RELOAD_OTHER
	.word	SMALL_REGISTER_CLASSES
	.word	this_insn
	.word	insn_data
	.word	REG_DEAD
	.word	FIRST_PSEUDO_REGISTER
	.word	reg_class_contents
	.word	hard_regno_nregs
	.word	fixed_regs
	.word	ENTRY_BLOCK_PTR
	.word	RELOAD_FOR_INPUT
	.word	reg_class_size
	.word	RELOAD_FOR_OUTPUT
	.word	replacements
	.word	n_replacements
	.size	combine_reloads, .-combine_reloads
	.comm	this_insn,4,4
	.comm	secondary_memlocs_elim,4,4
	.comm	rld,4,4
	.comm	replacements,4,4
	.comm	reg_class_size,4,4
	.comm	reg_class_contents,4,4
	.comm	n_replacements,4,4
	.comm	n_reloads,4,4
	.comm	insn_data,4,4
	.comm	hard_regno_nregs,4,4
	.comm	fixed_regs,4,4
	.comm	SMALL_REGISTER_CLASSES,4,4
	.comm	RELOAD_OTHER,4,4
	.comm	RELOAD_FOR_OUTPUT_ADDRESS,4,4
	.comm	RELOAD_FOR_OUTPUT,4,4
	.comm	RELOAD_FOR_OUTADDR_ADDRESS,4,4
	.comm	RELOAD_FOR_INPUT,4,4
	.comm	REG_DEAD,4,4
	.comm	FIRST_PSEUDO_REGISTER,4,4
	.comm	ENTRY_BLOCK_PTR,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
