	.file	"extr_atl2.c_atl2_get_regs.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	atl2_get_regs, @function
atl2_get_regs:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	mov	r12, rsi
	push	rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	push	rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	mov	rbx, rdx
	sub	rsp, 16
	.cfi_def_cfa_offset 48
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 8[rsp], rax
	xor	eax, eax
	call	netdev_priv@PLT
	xor	esi, esi
	mov	rdi, rbx
	mov	rbp, rax
	mov	eax, DWORD PTR ATL2_REGS_LEN[rip]
	lea	edx, 0[0+rax*8]
	call	memset@PLT
	mov	eax, DWORD PTR 0[rbp]
	mov	rsi, QWORD PTR REG_VPD_CAP[rip]
	mov	rdi, rbp
	sal	eax, 16
	or	eax, DWORD PTR 4[rbp]
	or	eax, 16777216
	mov	DWORD PTR [r12], eax
	lea	r12, 4[rsp]
	call	ATL2_READ_REG@PLT
	mov	rdi, rbp
	mov	QWORD PTR [rbx], rax
	mov	rsi, QWORD PTR REG_SPI_FLASH_CTRL[rip]
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_SPI_FLASH_CONFIG[rip]
	mov	rdi, rbp
	mov	QWORD PTR 8[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_TWSI_CTRL[rip]
	mov	rdi, rbp
	mov	QWORD PTR 16[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_PCIE_DEV_MISC_CTRL[rip]
	mov	rdi, rbp
	mov	QWORD PTR 24[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_MASTER_CTRL[rip]
	mov	rdi, rbp
	mov	QWORD PTR 32[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_MANUAL_TIMER_INIT[rip]
	mov	rdi, rbp
	mov	QWORD PTR 40[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_IRQ_MODU_TIMER_INIT[rip]
	mov	rdi, rbp
	mov	QWORD PTR 48[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_PHY_ENABLE[rip]
	mov	rdi, rbp
	mov	QWORD PTR 56[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_CMBDISDMA_TIMER[rip]
	mov	rdi, rbp
	mov	QWORD PTR 64[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_IDLE_STATUS[rip]
	mov	rdi, rbp
	mov	QWORD PTR 72[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_MDIO_CTRL[rip]
	mov	rdi, rbp
	mov	QWORD PTR 80[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_SERDES_LOCK[rip]
	mov	rdi, rbp
	mov	QWORD PTR 88[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_MAC_CTRL[rip]
	mov	rdi, rbp
	mov	QWORD PTR 96[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_MAC_IPG_IFG[rip]
	mov	rdi, rbp
	mov	QWORD PTR 104[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_MAC_STA_ADDR[rip]
	mov	rdi, rbp
	mov	QWORD PTR 112[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rdi, rbp
	mov	QWORD PTR 120[rbx], rax
	mov	rax, QWORD PTR REG_MAC_STA_ADDR[rip]
	lea	rsi, 4[rax]
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_RX_HASH_TABLE[rip]
	mov	rdi, rbp
	mov	QWORD PTR 128[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rdi, rbp
	mov	QWORD PTR 136[rbx], rax
	mov	rax, QWORD PTR REG_RX_HASH_TABLE[rip]
	lea	rsi, 4[rax]
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_MAC_HALF_DUPLX_CTRL[rip]
	mov	rdi, rbp
	mov	QWORD PTR 144[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_MTU[rip]
	mov	rdi, rbp
	mov	QWORD PTR 152[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_WOL_CTRL[rip]
	mov	rdi, rbp
	mov	QWORD PTR 160[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_SRAM_TXRAM_END[rip]
	mov	rdi, rbp
	mov	QWORD PTR 168[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_DESC_BASE_ADDR_HI[rip]
	mov	rdi, rbp
	mov	QWORD PTR 176[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_TXD_BASE_ADDR_LO[rip]
	mov	rdi, rbp
	mov	QWORD PTR 184[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_TXD_MEM_SIZE[rip]
	mov	rdi, rbp
	mov	QWORD PTR 192[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_TXS_BASE_ADDR_LO[rip]
	mov	rdi, rbp
	mov	QWORD PTR 200[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_TXS_MEM_SIZE[rip]
	mov	rdi, rbp
	mov	QWORD PTR 208[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_RXD_BASE_ADDR_LO[rip]
	mov	rdi, rbp
	mov	QWORD PTR 216[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_RXD_BUF_NUM[rip]
	mov	rdi, rbp
	mov	QWORD PTR 224[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_DMAR[rip]
	mov	rdi, rbp
	mov	QWORD PTR 232[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_TX_CUT_THRESH[rip]
	mov	rdi, rbp
	mov	QWORD PTR 240[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_DMAW[rip]
	mov	rdi, rbp
	mov	QWORD PTR 248[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_PAUSE_ON_TH[rip]
	mov	rdi, rbp
	mov	QWORD PTR 256[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_PAUSE_OFF_TH[rip]
	mov	rdi, rbp
	mov	QWORD PTR 264[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_MB_TXD_WR_IDX[rip]
	mov	rdi, rbp
	mov	QWORD PTR 272[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_MB_RXD_RD_IDX[rip]
	mov	rdi, rbp
	mov	QWORD PTR 280[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_ISR[rip]
	mov	rdi, rbp
	mov	QWORD PTR 288[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	rsi, QWORD PTR REG_IMR[rip]
	mov	rdi, rbp
	mov	QWORD PTR 304[rbx], rax
	call	ATL2_READ_REG@PLT
	mov	esi, DWORD PTR MII_BMCR[rip]
	mov	rdx, r12
	mov	rdi, rbp
	mov	QWORD PTR 312[rbx], rax
	call	atl2_read_phy_reg@PLT
	movsx	rax, DWORD PTR 4[rsp]
	mov	rdx, r12
	mov	rdi, rbp
	mov	esi, DWORD PTR MII_BMSR[rip]
	mov	QWORD PTR 320[rbx], rax
	call	atl2_read_phy_reg@PLT
	movsx	rax, DWORD PTR 4[rsp]
	mov	QWORD PTR 328[rbx], rax
	mov	rax, QWORD PTR 8[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L5
	add	rsp, 16
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	pop	rbx
	.cfi_def_cfa_offset 24
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
.L5:
	.cfi_restore_state
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	atl2_get_regs, .-atl2_get_regs
	.comm	REG_WOL_CTRL,8,8
	.comm	REG_VPD_CAP,8,8
	.comm	REG_TX_CUT_THRESH,8,8
	.comm	REG_TXS_MEM_SIZE,8,8
	.comm	REG_TXS_BASE_ADDR_LO,8,8
	.comm	REG_TXD_MEM_SIZE,8,8
	.comm	REG_TXD_BASE_ADDR_LO,8,8
	.comm	REG_TWSI_CTRL,8,8
	.comm	REG_SRAM_TXRAM_END,8,8
	.comm	REG_SPI_FLASH_CTRL,8,8
	.comm	REG_SPI_FLASH_CONFIG,8,8
	.comm	REG_SERDES_LOCK,8,8
	.comm	REG_RX_HASH_TABLE,8,8
	.comm	REG_RXD_BUF_NUM,8,8
	.comm	REG_RXD_BASE_ADDR_LO,8,8
	.comm	REG_PHY_ENABLE,8,8
	.comm	REG_PCIE_DEV_MISC_CTRL,8,8
	.comm	REG_PAUSE_ON_TH,8,8
	.comm	REG_PAUSE_OFF_TH,8,8
	.comm	REG_MTU,8,8
	.comm	REG_MDIO_CTRL,8,8
	.comm	REG_MB_TXD_WR_IDX,8,8
	.comm	REG_MB_RXD_RD_IDX,8,8
	.comm	REG_MASTER_CTRL,8,8
	.comm	REG_MANUAL_TIMER_INIT,8,8
	.comm	REG_MAC_STA_ADDR,8,8
	.comm	REG_MAC_IPG_IFG,8,8
	.comm	REG_MAC_HALF_DUPLX_CTRL,8,8
	.comm	REG_MAC_CTRL,8,8
	.comm	REG_ISR,8,8
	.comm	REG_IRQ_MODU_TIMER_INIT,8,8
	.comm	REG_IMR,8,8
	.comm	REG_IDLE_STATUS,8,8
	.comm	REG_DMAW,8,8
	.comm	REG_DMAR,8,8
	.comm	REG_DESC_BASE_ADDR_HI,8,8
	.comm	REG_CMBDISDMA_TIMER,8,8
	.comm	MII_BMSR,4,4
	.comm	MII_BMCR,4,4
	.comm	ATL2_REGS_LEN,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_atl2.c_atl2_get_regs.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	atl2_get_regs, %function
atl2_get_regs:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, lr}
	ldr	r3, .L6
	sub	sp, sp, #8
	mov	r5, r2
	mov	r6, r1
	ldr	r3, [r3]
	str	r3, [sp, #4]
	mov	r3,#0
	bl	netdev_priv
	mov	r4, r0
	ldr	r3, .L6+4
	mov	r1, #0
	ldr	r2, [r3]
	mov	r0, r5
	lsl	r2, r2, #2
	bl	memset
	ldm	r4, {r1, r3}
	ldr	r2, .L6+8
	orr	r3, r3, r1, lsl #16
	orr	r3, r3, #16777216
	ldr	r1, [r2]
	str	r3, [r6]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+12
	str	r0, [r5]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+16
	str	r0, [r5, #4]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+20
	str	r0, [r5, #8]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+24
	str	r0, [r5, #12]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+28
	str	r0, [r5, #16]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+32
	str	r0, [r5, #20]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+36
	str	r0, [r5, #24]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+40
	str	r0, [r5, #28]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+44
	str	r0, [r5, #32]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+48
	str	r0, [r5, #36]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+52
	str	r0, [r5, #40]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+56
	str	r0, [r5, #44]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+60
	str	r0, [r5, #48]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+64
	str	r0, [r5, #52]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r6, .L6+68
	str	r0, [r5, #56]
	ldr	r1, [r6]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r1, [r6]
	str	r0, [r5, #60]
	add	r1, r1, #4
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r6, .L6+72
	str	r0, [r5, #64]
	ldr	r1, [r6]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r1, [r6]
	str	r0, [r5, #68]
	add	r1, r1, #4
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+76
	str	r0, [r5, #72]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+80
	str	r0, [r5, #76]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+84
	str	r0, [r5, #80]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+88
	str	r0, [r5, #84]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+92
	str	r0, [r5, #88]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+96
	str	r0, [r5, #92]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+100
	str	r0, [r5, #96]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+104
	str	r0, [r5, #100]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+108
	str	r0, [r5, #104]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+112
	str	r0, [r5, #108]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+116
	str	r0, [r5, #112]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+120
	str	r0, [r5, #116]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+124
	str	r0, [r5, #120]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+128
	str	r0, [r5, #124]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+132
	str	r0, [r5, #128]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+136
	str	r0, [r5, #132]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+140
	str	r0, [r5, #136]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+144
	str	r0, [r5, #140]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+148
	str	r0, [r5, #144]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+152
	str	r0, [r5, #152]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ATL2_READ_REG
	ldr	r3, .L6+156
	mov	r2, sp
	ldr	r1, [r3]
	str	r0, [r5, #156]
	mov	r0, r4
	bl	atl2_read_phy_reg
	ldr	r1, [sp]
	ldr	r3, .L6+160
	mov	r2, sp
	str	r1, [r5, #160]
	mov	r0, r4
	ldr	r1, [r3]
	bl	atl2_read_phy_reg
	ldr	r3, [sp]
	str	r3, [r5, #164]
	ldr	r3, .L6
	ldr	r2, [r3]
	ldr	r3, [sp, #4]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L5
	add	sp, sp, #8
	@ sp needed
	pop	{r4, r5, r6, pc}
.L5:
	bl	__stack_chk_fail
.L7:
	.align	2
.L6:
	.word	.LC0
	.word	ATL2_REGS_LEN
	.word	REG_VPD_CAP
	.word	REG_SPI_FLASH_CTRL
	.word	REG_SPI_FLASH_CONFIG
	.word	REG_TWSI_CTRL
	.word	REG_PCIE_DEV_MISC_CTRL
	.word	REG_MASTER_CTRL
	.word	REG_MANUAL_TIMER_INIT
	.word	REG_IRQ_MODU_TIMER_INIT
	.word	REG_PHY_ENABLE
	.word	REG_CMBDISDMA_TIMER
	.word	REG_IDLE_STATUS
	.word	REG_MDIO_CTRL
	.word	REG_SERDES_LOCK
	.word	REG_MAC_CTRL
	.word	REG_MAC_IPG_IFG
	.word	REG_MAC_STA_ADDR
	.word	REG_RX_HASH_TABLE
	.word	REG_MAC_HALF_DUPLX_CTRL
	.word	REG_MTU
	.word	REG_WOL_CTRL
	.word	REG_SRAM_TXRAM_END
	.word	REG_DESC_BASE_ADDR_HI
	.word	REG_TXD_BASE_ADDR_LO
	.word	REG_TXD_MEM_SIZE
	.word	REG_TXS_BASE_ADDR_LO
	.word	REG_TXS_MEM_SIZE
	.word	REG_RXD_BASE_ADDR_LO
	.word	REG_RXD_BUF_NUM
	.word	REG_DMAR
	.word	REG_TX_CUT_THRESH
	.word	REG_DMAW
	.word	REG_PAUSE_ON_TH
	.word	REG_PAUSE_OFF_TH
	.word	REG_MB_TXD_WR_IDX
	.word	REG_MB_RXD_RD_IDX
	.word	REG_ISR
	.word	REG_IMR
	.word	MII_BMCR
	.word	MII_BMSR
	.size	atl2_get_regs, .-atl2_get_regs
	.comm	REG_WOL_CTRL,4,4
	.comm	REG_VPD_CAP,4,4
	.comm	REG_TX_CUT_THRESH,4,4
	.comm	REG_TXS_MEM_SIZE,4,4
	.comm	REG_TXS_BASE_ADDR_LO,4,4
	.comm	REG_TXD_MEM_SIZE,4,4
	.comm	REG_TXD_BASE_ADDR_LO,4,4
	.comm	REG_TWSI_CTRL,4,4
	.comm	REG_SRAM_TXRAM_END,4,4
	.comm	REG_SPI_FLASH_CTRL,4,4
	.comm	REG_SPI_FLASH_CONFIG,4,4
	.comm	REG_SERDES_LOCK,4,4
	.comm	REG_RX_HASH_TABLE,4,4
	.comm	REG_RXD_BUF_NUM,4,4
	.comm	REG_RXD_BASE_ADDR_LO,4,4
	.comm	REG_PHY_ENABLE,4,4
	.comm	REG_PCIE_DEV_MISC_CTRL,4,4
	.comm	REG_PAUSE_ON_TH,4,4
	.comm	REG_PAUSE_OFF_TH,4,4
	.comm	REG_MTU,4,4
	.comm	REG_MDIO_CTRL,4,4
	.comm	REG_MB_TXD_WR_IDX,4,4
	.comm	REG_MB_RXD_RD_IDX,4,4
	.comm	REG_MASTER_CTRL,4,4
	.comm	REG_MANUAL_TIMER_INIT,4,4
	.comm	REG_MAC_STA_ADDR,4,4
	.comm	REG_MAC_IPG_IFG,4,4
	.comm	REG_MAC_HALF_DUPLX_CTRL,4,4
	.comm	REG_MAC_CTRL,4,4
	.comm	REG_ISR,4,4
	.comm	REG_IRQ_MODU_TIMER_INIT,4,4
	.comm	REG_IMR,4,4
	.comm	REG_IDLE_STATUS,4,4
	.comm	REG_DMAW,4,4
	.comm	REG_DMAR,4,4
	.comm	REG_DESC_BASE_ADDR_HI,4,4
	.comm	REG_CMBDISDMA_TIMER,4,4
	.comm	MII_BMSR,4,4
	.comm	MII_BMCR,4,4
	.comm	ATL2_REGS_LEN,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
