	.file	"extr_rtl8xxxu_core.c_rtl8xxxu_gen1_disable_rf.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	rtl8xxxu_gen1_disable_rf
	.type	rtl8xxxu_gen1_disable_rf, @function
rtl8xxxu_gen1_disable_rf:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	sub	rsp, 24
	.cfi_def_cfa_offset 64
	mov	esi, DWORD PTR REG_SPS0_CTRL[rip]
	call	rtl8xxxu_read8@PLT
	mov	esi, DWORD PTR REG_FPGA0_XAB_RF_PARM[rip]
	mov	rdi, rbp
	mov	r12d, eax
	call	rtl8xxxu_read32@PLT
	mov	edi, 3
	mov	r13d, eax
	call	BIT@PLT
	mov	edi, 4
	mov	ebx, eax
	call	BIT@PLT
	mov	edi, 5
	or	ebx, eax
	call	BIT@PLT
	or	ebx, eax
	mov	edx, ebx
	not	edx
	and	edx, r13d
	cmp	DWORD PTR 0[rbp], 2
	je	.L8
.L2:
	mov	esi, DWORD PTR REG_FPGA0_XAB_RF_PARM[rip]
	mov	rdi, rbp
	call	rtl8xxxu_write32@PLT
	mov	esi, DWORD PTR REG_OFDM0_TRX_PATH_ENABLE[rip]
	mov	rdi, rbp
	call	rtl8xxxu_read32@PLT
	mov	edx, DWORD PTR OFDM_RF_PATH_TX_MASK[rip]
	mov	esi, DWORD PTR REG_OFDM0_TRX_PATH_ENABLE[rip]
	mov	rdi, rbp
	not	edx
	and	edx, eax
	call	rtl8xxxu_write32@PLT
	mov	esi, DWORD PTR REG_FPGA0_RF_MODE[rip]
	mov	rdi, rbp
	call	rtl8xxxu_read32@PLT
	mov	esi, DWORD PTR REG_FPGA0_RF_MODE[rip]
	or	eax, DWORD PTR FPGA_RF_MODE_JAPAN[rip]
	mov	rdi, rbp
	mov	edx, eax
	call	rtl8xxxu_write32@PLT
	cmp	DWORD PTR 0[rbp], 2
	je	.L9
	mov	esi, DWORD PTR REG_RX_WAIT_CCA[rip]
	mov	edx, 1779104
	mov	rdi, rbp
	call	rtl8xxxu_write32@PLT
.L4:
	mov	edx, DWORD PTR RF6052_REG_AC[rip]
	mov	esi, DWORD PTR RF_A[rip]
	xor	ecx, ecx
	mov	rdi, rbp
	call	rtl8xxxu_write_rfreg@PLT
	cmp	DWORD PTR 0[rbp], 2
	je	.L10
.L5:
	xor	edi, edi
	call	BIT@PLT
	mov	edi, 3
	mov	ebx, eax
	call	BIT@PLT
	mov	esi, DWORD PTR REG_SPS0_CTRL[rip]
	add	rsp, 24
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	rdi, rbp
	or	ebx, eax
	mov	edx, ebx
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	not	edx
	and	edx, r12d
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	jmp	rtl8xxxu_write8@PLT
	.p2align 4,,10
	.p2align 3
.L9:
	.cfi_restore_state
	mov	esi, DWORD PTR REG_RX_WAIT_CCA[rip]
	mov	edx, 14362016
	mov	rdi, rbp
	call	rtl8xxxu_write32@PLT
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L8:
	mov	edi, 19
	mov	DWORD PTR 12[rsp], edx
	call	BIT@PLT
	mov	edi, 20
	mov	ebx, eax
	call	BIT@PLT
	mov	edi, 21
	or	ebx, eax
	call	BIT@PLT
	mov	edx, DWORD PTR 12[rsp]
	or	ebx, eax
	not	ebx
	and	edx, ebx
	jmp	.L2
	.p2align 4,,10
	.p2align 3
.L10:
	mov	edx, DWORD PTR RF6052_REG_AC[rip]
	mov	esi, DWORD PTR RF_B[rip]
	xor	ecx, ecx
	mov	rdi, rbp
	call	rtl8xxxu_write_rfreg@PLT
	jmp	.L5
	.cfi_endproc
.LFE0:
	.size	rtl8xxxu_gen1_disable_rf, .-rtl8xxxu_gen1_disable_rf
	.comm	RF_B,4,4
	.comm	RF_A,4,4
	.comm	RF6052_REG_AC,4,4
	.comm	REG_SPS0_CTRL,4,4
	.comm	REG_RX_WAIT_CCA,4,4
	.comm	REG_OFDM0_TRX_PATH_ENABLE,4,4
	.comm	REG_FPGA0_XAB_RF_PARM,4,4
	.comm	REG_FPGA0_RF_MODE,4,4
	.comm	OFDM_RF_PATH_TX_MASK,4,4
	.comm	FPGA_RF_MODE_JAPAN,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_rtl8xxxu_core.c_rtl8xxxu_gen1_disable_rf.c"
	.text
	.align	2
	.global	rtl8xxxu_gen1_disable_rf
	.syntax unified
	.arm
	.fpu softvfp
	.type	rtl8xxxu_gen1_disable_rf, %function
rtl8xxxu_gen1_disable_rf:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, lr}
	ldr	r8, .L10
	mov	r4, r0
	ldr	r1, [r8]
	bl	rtl8xxxu_read8
	ldr	r9, .L10+4
	mov	r7, r0
	ldr	r1, [r9]
	mov	r0, r4
	bl	rtl8xxxu_read32
	mov	r5, r0
	mov	r0, #3
	bl	BIT
	mov	r6, r0
	mov	r0, #4
	bl	BIT
	mov	r2, r0
	mov	r0, #5
	orr	r6, r6, r2
	bl	BIT
	ldr	r3, [r4]
	orr	r6, r6, r0
	cmp	r3, #2
	bic	r5, r5, r6
	beq	.L8
.L2:
	ldr	r6, .L10+8
	mov	r2, r5
	ldr	r1, [r9]
	mov	r0, r4
	bl	rtl8xxxu_write32
	ldr	r1, [r6]
	mov	r0, r4
	bl	rtl8xxxu_read32
	ldr	r3, .L10+12
	ldr	r5, .L10+16
	ldr	r2, [r3]
	ldr	r1, [r6]
	bic	r2, r0, r2
	mov	r0, r4
	bl	rtl8xxxu_write32
	ldr	r1, [r5]
	mov	r0, r4
	bl	rtl8xxxu_read32
	mov	r2, r0
	ldr	r3, .L10+20
	ldr	r1, [r5]
	ldr	r3, [r3]
	mov	r0, r4
	orr	r2, r2, r3
	bl	rtl8xxxu_write32
	ldr	r3, [r4]
	mov	r0, r4
	cmp	r3, #2
	ldr	r3, .L10+24
	ldreq	r2, .L10+28
	ldrne	r2, .L10+32
	ldr	r1, [r3]
	bl	rtl8xxxu_write32
	ldr	r5, .L10+36
	ldr	r3, .L10+40
	mov	r0, r4
	ldr	r1, [r3]
	ldr	r2, [r5]
	mov	r3, #0
	bl	rtl8xxxu_write_rfreg
	ldr	r3, [r4]
	cmp	r3, #2
	beq	.L9
.L5:
	mov	r0, #0
	bl	BIT
	mov	r5, r0
	mov	r0, #3
	bl	BIT
	orr	r2, r5, r0
	ldr	r1, [r8]
	mov	r0, r4
	bic	r2, r7, r2
	pop	{r4, r5, r6, r7, r8, r9, r10, lr}
	b	rtl8xxxu_write8
.L8:
	mov	r0, #19
	bl	BIT
	mov	r6, r0
	mov	r0, #20
	bl	BIT
	mov	r3, r0
	mov	r0, #21
	orr	r6, r6, r3
	bl	BIT
	orr	r6, r6, r0
	bic	r5, r5, r6
	b	.L2
.L9:
	ldr	r3, .L10+44
	mov	r0, r4
	ldr	r1, [r3]
	ldr	r2, [r5]
	mov	r3, #0
	bl	rtl8xxxu_write_rfreg
	b	.L5
.L11:
	.align	2
.L10:
	.word	REG_SPS0_CTRL
	.word	REG_FPGA0_XAB_RF_PARM
	.word	REG_OFDM0_TRX_PATH_ENABLE
	.word	OFDM_RF_PATH_TX_MASK
	.word	REG_FPGA0_RF_MODE
	.word	FPGA_RF_MODE_JAPAN
	.word	REG_RX_WAIT_CCA
	.word	14362016
	.word	1779104
	.word	RF6052_REG_AC
	.word	RF_A
	.word	RF_B
	.size	rtl8xxxu_gen1_disable_rf, .-rtl8xxxu_gen1_disable_rf
	.comm	RF_B,4,4
	.comm	RF_A,4,4
	.comm	RF6052_REG_AC,4,4
	.comm	REG_SPS0_CTRL,4,4
	.comm	REG_RX_WAIT_CCA,4,4
	.comm	REG_OFDM0_TRX_PATH_ENABLE,4,4
	.comm	REG_FPGA0_XAB_RF_PARM,4,4
	.comm	REG_FPGA0_RF_MODE,4,4
	.comm	OFDM_RF_PATH_TX_MASK,4,4
	.comm	FPGA_RF_MODE_JAPAN,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
