	.file	"extr_nbio_v7_4.c_nbio_v7_4_update_medium_grain_light_sleep.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	nbio_v7_4_update_medium_grain_light_sleep, @function
nbio_v7_4_update_medium_grain_light_sleep:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	ebp, esi
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	mov	rbx, rdi
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	mov	edi, DWORD PTR smnPCIE_CNTL2[rip]
	call	RREG32_PCIE@PLT
	mov	esi, DWORD PTR PCIE_CNTL2__SLV_MEM_LS_EN_MASK[rip]
	or	esi, DWORD PTR PCIE_CNTL2__MST_MEM_LS_EN_MASK[rip]
	or	esi, DWORD PTR PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK[rip]
	test	ebp, ebp
	je	.L3
	mov	edx, DWORD PTR [rbx]
	test	DWORD PTR AMD_CG_SUPPORT_BIF_LS[rip], edx
	jne	.L11
.L3:
	not	esi
	and	esi, eax
	cmp	esi, eax
	jne	.L12
.L1:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L11:
	.cfi_restore_state
	or	esi, eax
	cmp	esi, eax
	je	.L1
.L12:
	mov	edi, DWORD PTR smnPCIE_CNTL2[rip]
	add	rsp, 8
	.cfi_def_cfa_offset 24
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	jmp	WREG32_PCIE@PLT
	.cfi_endproc
.LFE0:
	.size	nbio_v7_4_update_medium_grain_light_sleep, .-nbio_v7_4_update_medium_grain_light_sleep
	.comm	smnPCIE_CNTL2,4,4
	.comm	PCIE_CNTL2__SLV_MEM_LS_EN_MASK,4,4
	.comm	PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK,4,4
	.comm	PCIE_CNTL2__MST_MEM_LS_EN_MASK,4,4
	.comm	AMD_CG_SUPPORT_BIF_LS,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_nbio_v7_4.c_nbio_v7_4_update_medium_grain_light_sleep.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	nbio_v7_4_update_medium_grain_light_sleep, %function
nbio_v7_4_update_medium_grain_light_sleep:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, lr}
	mov	r4, r1
	ldr	r5, .L11
	mov	r6, r0
	ldr	r0, [r5]
	bl	RREG32_PCIE
	cmp	r4, #0
	beq	.L2
	ldr	r1, .L11+4
	ldr	r2, .L11+8
	ldr	r3, .L11+12
	ldr	ip, [r1]
	ldr	r1, [r2]
	ldr	r2, [r3]
	ldr	r3, .L11+16
	ldr	lr, [r6]
	ldr	r3, [r3]
	orr	r1, r1, r2
	tst	lr, ip
	orr	r1, r1, r3
	orrne	r1, r0, r1
	biceq	r1, r0, r1
.L4:
	cmp	r1, r0
	popeq	{r4, r5, r6, pc}
	ldr	r0, [r5]
	pop	{r4, r5, r6, lr}
	b	WREG32_PCIE
.L2:
	ldr	r1, .L11+8
	ldr	r2, .L11+12
	ldr	r3, .L11+16
	ldr	r1, [r1]
	ldr	r2, [r2]
	ldr	r3, [r3]
	orr	r1, r1, r2
	orr	r1, r1, r3
	bic	r1, r0, r1
	b	.L4
.L12:
	.align	2
.L11:
	.word	smnPCIE_CNTL2
	.word	AMD_CG_SUPPORT_BIF_LS
	.word	PCIE_CNTL2__SLV_MEM_LS_EN_MASK
	.word	PCIE_CNTL2__MST_MEM_LS_EN_MASK
	.word	PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK
	.size	nbio_v7_4_update_medium_grain_light_sleep, .-nbio_v7_4_update_medium_grain_light_sleep
	.comm	smnPCIE_CNTL2,4,4
	.comm	PCIE_CNTL2__SLV_MEM_LS_EN_MASK,4,4
	.comm	PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK,4,4
	.comm	PCIE_CNTL2__MST_MEM_LS_EN_MASK,4,4
	.comm	AMD_CG_SUPPORT_BIF_LS,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
