	.file	"extr_command_table.c_set_pixel_clock_v7.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	set_pixel_clock_v7, @function
set_pixel_clock_v7:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	mov	edx, 56
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	mov	rbx, rsi
	xor	esi, esi
	sub	rsp, 88
	.cfi_def_cfa_offset 128
	mov	r12d, DWORD PTR BP_RESULT_FAILURE[rip]
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 72[rsp], rax
	xor	eax, eax
	lea	rdi, 16[rsp]
	call	memset@PLT
	mov	rax, QWORD PTR 0[rbp]
	mov	edi, DWORD PTR 72[rbx]
	lea	rsi, 8[rsp]
	call	[QWORD PTR 32[rax]]
	test	rax, rax
	je	.L1
	mov	rax, QWORD PTR 0[rbp]
	mov	edi, DWORD PTR 68[rbx]
	mov	rsi, rsp
	call	[QWORD PTR 24[rax]]
	test	rax, rax
	jne	.L21
.L1:
	mov	rax, QWORD PTR 72[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L22
	add	rsp, 88
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	eax, r12d
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L21:
	.cfi_restore_state
	mov	rax, QWORD PTR [rsp]
	mov	edi, DWORD PTR 64[rbx]
	mov	QWORD PTR 64[rsp], rax
	mov	rax, QWORD PTR 8[rsp]
	mov	QWORD PTR 56[rsp], rax
	mov	rax, QWORD PTR 0[rbp]
	mov	r13, QWORD PTR 16[rax]
	call	dal_graphics_object_id_get_encoder_id@PLT
	mov	edi, eax
	call	r13
	xor	esi, esi
	mov	rdi, QWORD PTR [rbx]
	mov	DWORD PTR 48[rsp], eax
	mov	rax, QWORD PTR 0[rbp]
	call	[QWORD PTR 8[rax]]
	mov	edi, DWORD PTR 60[rbx]
	mov	QWORD PTR 40[rsp], rax
	call	cpu_to_le32@PLT
	mov	edi, DWORD PTR 56[rbx]
	mov	DWORD PTR 32[rsp], eax
	mov	rax, QWORD PTR 0[rbp]
	call	[QWORD PTR [rax]]
	cmp	QWORD PTR 48[rbx], 0
	mov	QWORD PTR 24[rsp], rax
	je	.L3
	mov	eax, DWORD PTR PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL[rip]
	or	DWORD PTR 16[rsp], eax
.L3:
	cmp	QWORD PTR 40[rbx], 0
	je	.L4
	mov	eax, DWORD PTR PIXEL_CLOCK_V7_MISC_REF_DIV_SRC[rip]
	or	DWORD PTR 16[rsp], eax
.L4:
	cmp	QWORD PTR 32[rbx], 0
	je	.L5
	mov	eax, DWORD PTR PIXEL_CLOCK_V7_MISC_PROG_PHYPLL[rip]
	or	DWORD PTR 16[rsp], eax
.L5:
	cmp	QWORD PTR 24[rbx], 0
	je	.L6
	mov	eax, DWORD PTR PIXEL_CLOCK_V7_MISC_YUV420_MODE[rip]
	or	DWORD PTR 16[rsp], eax
.L6:
	cmp	QWORD PTR 16[rbx], 0
	je	.L7
	mov	eax, DWORD PTR PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN[rip]
	or	DWORD PTR 16[rsp], eax
.L7:
	cmp	QWORD PTR 8[rbx], 0
	je	.L8
	mov	eax, DWORD PTR PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK[rip]
	or	DWORD PTR 16[rsp], eax
.L8:
	mov	rax, QWORD PTR SIGNAL_TYPE_DVI_DUAL_LINK[rip]
	cmp	QWORD PTR [rbx], rax
	jne	.L9
	mov	eax, DWORD PTR PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN[rip]
	or	DWORD PTR 16[rsp], eax
.L9:
	sub	rsp, 8
	.cfi_def_cfa_offset 136
	mov	edi, DWORD PTR SetPixelClock[rip]
	push	QWORD PTR 72[rsp]
	.cfi_def_cfa_offset 144
	push	QWORD PTR 72[rsp]
	.cfi_def_cfa_offset 152
	push	QWORD PTR 72[rsp]
	.cfi_def_cfa_offset 160
	push	QWORD PTR 72[rsp]
	.cfi_def_cfa_offset 168
	push	QWORD PTR 72[rsp]
	.cfi_def_cfa_offset 176
	push	QWORD PTR 72[rsp]
	.cfi_def_cfa_offset 184
	push	QWORD PTR 72[rsp]
	.cfi_def_cfa_offset 192
	call	EXEC_BIOS_CMD_TABLE@PLT
	add	rsp, 64
	.cfi_def_cfa_offset 128
	test	rax, rax
	cmovne	r12d, DWORD PTR BP_RESULT_OK[rip]
	jmp	.L1
.L22:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	set_pixel_clock_v7, .-set_pixel_clock_v7
	.comm	SetPixelClock,4,4
	.comm	SIGNAL_TYPE_DVI_DUAL_LINK,8,8
	.comm	PIXEL_CLOCK_V7_MISC_YUV420_MODE,4,4
	.comm	PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN,4,4
	.comm	PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK,4,4
	.comm	PIXEL_CLOCK_V7_MISC_REF_DIV_SRC,4,4
	.comm	PIXEL_CLOCK_V7_MISC_PROG_PHYPLL,4,4
	.comm	PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL,4,4
	.comm	PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN,4,4
	.comm	BP_RESULT_OK,4,4
	.comm	BP_RESULT_FAILURE,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_command_table.c_set_pixel_clock_v7.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	set_pixel_clock_v7, %function
set_pixel_clock_v7:
	@ args = 0, pretend = 0, frame = 40
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, lr}
	mov	r4, #0
	ldr	r3, [r0]
	sub	sp, sp, #60
	ldr	r2, .L42
	ldr	ip, .L42+4
	add	r5, sp, #24
	mov	r8, r0
	mov	r6, r1
	ldr	r0, [r1, #44]
	ldr	r3, [r3, #16]
	add	r1, sp, #20
	ldr	ip, [ip]
	str	ip, [sp, #52]
	mov	ip,#0
	ldr	r7, [r2]
	str	r4, [sp, #24]
	str	r4, [r5, #4]
	str	r4, [r5, #8]
	str	r4, [r5, #12]
	str	r4, [r5, #16]
	str	r4, [r5, #20]
	str	r4, [r5, #24]
	blx	r3
	cmp	r0, r4
	beq	.L1
	ldr	r3, [r8]
	ldr	r0, [r6, #40]
	ldr	r3, [r3, #12]
	add	r1, sp, #16
	blx	r3
	cmp	r0, r4
	bne	.L40
.L1:
	ldr	r3, .L42+4
	ldr	r2, [r3]
	ldr	r3, [sp, #52]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L41
	mov	r0, r7
	add	sp, sp, #60
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, pc}
.L40:
	ldr	r1, [sp, #16]
	ldr	r2, [sp, #20]
	ldr	r3, [r8]
	ldr	r0, [r6, #36]
	ldr	r9, [r3, #8]
	str	r1, [sp, #48]
	str	r2, [sp, #44]
	bl	dal_graphics_object_id_get_encoder_id
	blx	r9
	mov	r2, r0
	ldr	r3, [r8]
	mov	r1, r4
	ldr	r3, [r3, #4]
	ldr	r0, [r6]
	str	r2, [sp, #40]
	blx	r3
	mov	r3, r0
	ldr	r0, [r6, #32]
	str	r3, [sp, #36]
	bl	cpu_to_le32
	mov	r2, r0
	ldr	r3, [r8]
	ldr	r0, [r6, #28]
	ldr	r3, [r3]
	str	r2, [sp, #32]
	blx	r3
	ldr	r3, [r6, #24]
	str	r0, [sp, #28]
	cmp	r3, r4
	ldrne	r3, .L42+8
	ldr	ip, .L42+12
	ldrne	r3, [r3]
	strne	r3, [sp, #24]
	ldr	r3, [r6, #20]
	cmp	r3, #0
	ldrne	r2, .L42+16
	ldrne	r3, [sp, #24]
	ldrne	r2, [r2]
	orrne	r3, r3, r2
	strne	r3, [sp, #24]
	ldr	r3, [r6, #16]
	cmp	r3, #0
	ldrne	r2, .L42+20
	ldrne	r3, [sp, #24]
	ldrne	r2, [r2]
	orrne	r3, r3, r2
	strne	r3, [sp, #24]
	ldr	r3, [r6, #12]
	cmp	r3, #0
	ldrne	r2, .L42+24
	ldrne	r3, [sp, #24]
	ldrne	r2, [r2]
	orrne	r3, r3, r2
	strne	r3, [sp, #24]
	ldr	r3, [r6, #8]
	cmp	r3, #0
	ldrne	r2, .L42+28
	ldrne	r3, [sp, #24]
	ldrne	r2, [r2]
	orrne	r3, r3, r2
	strne	r3, [sp, #24]
	ldr	r3, [r6, #4]
	cmp	r3, #0
	ldrne	r2, .L42+32
	ldrne	r3, [sp, #24]
	ldrne	r2, [r2]
	orrne	r3, r3, r2
	strne	r3, [sp, #24]
	ldr	r3, .L42+36
	ldr	r2, [r6]
	ldr	r3, [r3]
	cmp	r2, r3
	ldreq	r2, .L42+40
	ldreq	r3, [sp, #24]
	ldreq	r2, [r2]
	orreq	r3, r3, r2
	streq	r3, [sp, #24]
	add	r3, sp, #36
	ldm	r3, {r0, r1, r2, r3}
	stm	sp, {r0, r1, r2, r3}
	ldm	r5, {r1, r2, r3}
	ldr	r0, [ip]
	bl	EXEC_BIOS_CMD_TABLE
	cmp	r0, #0
	ldrne	r3, .L42+44
	ldrne	r7, [r3]
	b	.L1
.L41:
	bl	__stack_chk_fail
.L43:
	.align	2
.L42:
	.word	BP_RESULT_FAILURE
	.word	.LC0
	.word	PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL
	.word	SetPixelClock
	.word	PIXEL_CLOCK_V7_MISC_REF_DIV_SRC
	.word	PIXEL_CLOCK_V7_MISC_PROG_PHYPLL
	.word	PIXEL_CLOCK_V7_MISC_YUV420_MODE
	.word	PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN
	.word	PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK
	.word	SIGNAL_TYPE_DVI_DUAL_LINK
	.word	PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN
	.word	BP_RESULT_OK
	.size	set_pixel_clock_v7, .-set_pixel_clock_v7
	.comm	SetPixelClock,4,4
	.comm	SIGNAL_TYPE_DVI_DUAL_LINK,4,4
	.comm	PIXEL_CLOCK_V7_MISC_YUV420_MODE,4,4
	.comm	PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN,4,4
	.comm	PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK,4,4
	.comm	PIXEL_CLOCK_V7_MISC_REF_DIV_SRC,4,4
	.comm	PIXEL_CLOCK_V7_MISC_PROG_PHYPLL,4,4
	.comm	PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL,4,4
	.comm	PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN,4,4
	.comm	BP_RESULT_OK,4,4
	.comm	BP_RESULT_FAILURE,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
