	.file	"extr_gfx_v8_0.c_gfx_v8_0_enable_gfx_static_mg_power_gating.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	gfx_v8_0_enable_gfx_static_mg_power_gating, @function
gfx_v8_0_enable_gfx_static_mg_power_gating:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	mov	rax, QWORD PTR [rdi]
	mov	ebx, esi
	cmp	rax, QWORD PTR CHIP_POLARIS11[rip]
	je	.L2
	cmp	rax, QWORD PTR CHIP_POLARIS12[rip]
	je	.L2
	cmp	rax, QWORD PTR CHIP_VEGAM[rip]
	je	.L2
.L3:
	xor	edx, edx
	mov	esi, DWORD PTR STATIC_PER_CU_PG_ENABLE[rip]
	test	ebx, ebx
	mov	edi, DWORD PTR RLC_PG_CNTL[rip]
	setne	dl
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	WREG32_FIELD@PLT
	.p2align 4,,10
	.p2align 3
.L2:
	.cfi_restore_state
	mov	rax, QWORD PTR 8[rdi]
	cmp	QWORD PTR [rax], 0
	je	.L3
	mov	esi, DWORD PTR AMD_IP_BLOCK_TYPE_GFX[rip]
	mov	edx, ebx
	call	amdgpu_dpm_set_powergating_by_smu@PLT
	jmp	.L3
	.cfi_endproc
.LFE0:
	.size	gfx_v8_0_enable_gfx_static_mg_power_gating, .-gfx_v8_0_enable_gfx_static_mg_power_gating
	.comm	STATIC_PER_CU_PG_ENABLE,4,4
	.comm	RLC_PG_CNTL,4,4
	.comm	CHIP_VEGAM,8,8
	.comm	CHIP_POLARIS12,8,8
	.comm	CHIP_POLARIS11,8,8
	.comm	AMD_IP_BLOCK_TYPE_GFX,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_gfx_v8_0.c_gfx_v8_0_enable_gfx_static_mg_power_gating.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	gfx_v8_0_enable_gfx_static_mg_power_gating, %function
gfx_v8_0_enable_gfx_static_mg_power_gating:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	ldr	r2, .L9
	ldr	r3, [r0]
	ldr	ip, [r2]
	push	{r4, lr}
	cmp	r3, ip
	mov	r4, r1
	beq	.L2
	ldr	r2, .L9+4
	ldr	r2, [r2]
	cmp	r3, r2
	beq	.L2
	ldr	r2, .L9+8
	ldr	r2, [r2]
	cmp	r3, r2
	beq	.L2
.L3:
	ldr	r1, .L9+12
	ldr	r3, .L9+16
	subs	r2, r4, #0
	movne	r2, #1
	pop	{r4, lr}
	ldr	r1, [r1]
	ldr	r0, [r3]
	b	WREG32_FIELD
.L2:
	ldr	r3, [r0, #4]
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L3
	ldr	r3, .L9+20
	mov	r2, r4
	ldr	r1, [r3]
	bl	amdgpu_dpm_set_powergating_by_smu
	b	.L3
.L10:
	.align	2
.L9:
	.word	CHIP_POLARIS11
	.word	CHIP_POLARIS12
	.word	CHIP_VEGAM
	.word	STATIC_PER_CU_PG_ENABLE
	.word	RLC_PG_CNTL
	.word	AMD_IP_BLOCK_TYPE_GFX
	.size	gfx_v8_0_enable_gfx_static_mg_power_gating, .-gfx_v8_0_enable_gfx_static_mg_power_gating
	.comm	STATIC_PER_CU_PG_ENABLE,4,4
	.comm	RLC_PG_CNTL,4,4
	.comm	CHIP_VEGAM,4,4
	.comm	CHIP_POLARIS12,4,4
	.comm	CHIP_POLARIS11,4,4
	.comm	AMD_IP_BLOCK_TYPE_GFX,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
