	.file	"extr_reset.c_ath5k_hw_set_sleep_clock.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	ath5k_hw_set_sleep_clock, @function
ath5k_hw_set_sleep_clock:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	mov	ebx, esi
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	mov	edi, DWORD PTR 24[rdi]
	call	AR5K_EEPROM_HAS32KHZCRYSTAL@PLT
	test	rax, rax
	je	.L2
	test	ebx, ebx
	jne	.L31
.L4:
	mov	edx, DWORD PTR AR5K_PCICFG_SLEEP_CLOCK_EN[rip]
	mov	esi, DWORD PTR AR5K_PCICFG[rip]
	mov	rdi, rbp
	call	AR5K_REG_DISABLE_BITS@PLT
	mov	edx, DWORD PTR AR5K_PCICFG_SLEEP_CLOCK_RATE[rip]
	xor	ecx, ecx
	mov	rdi, rbp
	mov	esi, DWORD PTR AR5K_PCICFG[rip]
	call	AR5K_REG_WRITE_BITS@PLT
	mov	edx, DWORD PTR AR5K_PHY_SCR[rip]
	mov	esi, 31
	mov	rdi, rbp
	call	ath5k_hw_reg_write@PLT
	mov	esi, DWORD PTR AR5K_PHY_SLMT_32MHZ[rip]
	mov	edx, DWORD PTR AR5K_PHY_SLMT[rip]
	mov	rdi, rbp
	call	ath5k_hw_reg_write@PLT
	mov	eax, DWORD PTR AR5K_SREV_AR2417[rip]
	mov	esi, DWORD PTR AR5K_PHY_SCAL_32MHZ_2417[rip]
	sar	eax, 4
	cmp	DWORD PTR 8[rbp], eax
	je	.L12
	cmp	QWORD PTR 16[rbp], 0
	mov	esi, DWORD PTR AR5K_PHY_SCAL_32MHZ[rip]
	je	.L12
	mov	esi, DWORD PTR AR5K_PHY_SCAL_32MHZ_HB63[rip]
.L12:
	mov	edx, DWORD PTR AR5K_PHY_SCAL[rip]
	mov	rdi, rbp
	call	ath5k_hw_reg_write@PLT
	mov	edx, DWORD PTR AR5K_PHY_SCLOCK[rip]
	mov	esi, DWORD PTR AR5K_PHY_SCLOCK_32MHZ[rip]
	mov	rdi, rbp
	call	ath5k_hw_reg_write@PLT
	mov	esi, DWORD PTR AR5K_PHY_SDELAY_32MHZ[rip]
	mov	edx, DWORD PTR AR5K_PHY_SDELAY[rip]
	mov	rdi, rbp
	call	ath5k_hw_reg_write@PLT
	mov	rax, QWORD PTR 0[rbp]
	cmp	rax, QWORD PTR AR5K_RF5112[rip]
	mov	esi, 20
	je	.L14
	cmp	rax, QWORD PTR AR5K_RF5413[rip]
	je	.L14
	cmp	rax, QWORD PTR AR5K_RF2316[rip]
	je	.L14
	mov	eax, DWORD PTR AR5K_SREV_AR2417[rip]
	xor	esi, esi
	sar	eax, 4
	cmp	DWORD PTR 8[rbp], eax
	setne	sil
	lea	esi, 20[0+rsi*4]
.L14:
	mov	edx, DWORD PTR AR5K_PHY_SPENDING[rip]
	mov	rdi, rbp
	call	ath5k_hw_reg_write@PLT
	mov	edx, DWORD PTR AR5K_TSF_PARM_INC[rip]
	mov	ecx, 1
	mov	rdi, rbp
	mov	esi, DWORD PTR AR5K_TSF_PARM[rip]
	call	AR5K_REG_WRITE_BITS@PLT
	mov	rax, QWORD PTR 0[rbp]
	cmp	rax, QWORD PTR AR5K_RF5112[rip]
	mov	ecx, 39
	je	.L15
	cmp	rax, QWORD PTR AR5K_RF5413[rip]
	je	.L15
	cmp	rax, QWORD PTR AR5K_RF2316[rip]
	je	.L15
	xor	ecx, ecx
	cmp	rax, QWORD PTR AR5K_RF2317[rip]
	sete	cl
	lea	ecx, 31[0+rcx*8]
.L15:
	mov	edx, DWORD PTR AR5K_USEC_32[rip]
	mov	esi, DWORD PTR AR5K_USEC_5211[rip]
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	mov	rdi, rbp
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	jmp	AR5K_REG_WRITE_BITS@PLT
	.p2align 4,,10
	.p2align 3
.L2:
	.cfi_restore_state
	mov	edi, DWORD PTR 24[rbp]
	call	AR5K_EEPROM_HAS32KHZCRYSTAL_OLD@PLT
	test	rax, rax
	je	.L4
	test	ebx, ebx
	je	.L4
	.p2align 4,,10
	.p2align 3
.L31:
	mov	edx, DWORD PTR AR5K_USEC_32[rip]
	mov	esi, DWORD PTR AR5K_USEC_5211[rip]
	mov	ecx, 1
	mov	rdi, rbp
	call	AR5K_REG_WRITE_BITS@PLT
	mov	edx, DWORD PTR AR5K_TSF_PARM_INC[rip]
	mov	ecx, 61
	mov	rdi, rbp
	mov	esi, DWORD PTR AR5K_TSF_PARM[rip]
	call	AR5K_REG_WRITE_BITS@PLT
	mov	edx, DWORD PTR AR5K_PHY_SCR[rip]
	mov	esi, 31
	mov	rdi, rbp
	call	ath5k_hw_reg_write@PLT
	mov	rax, QWORD PTR 0[rbp]
	cmp	rax, QWORD PTR AR5K_RF5112[rip]
	mov	esi, 20
	je	.L6
	cmp	rax, QWORD PTR AR5K_RF5413[rip]
	je	.L6
	cmp	rax, QWORD PTR AR5K_RF2316[rip]
	je	.L6
	mov	eax, DWORD PTR AR5K_SREV_AR2417[rip]
	xor	esi, esi
	sar	eax, 4
	cmp	DWORD PTR 8[rbp], eax
	setne	sil
	lea	esi, 20[0+rsi*4]
.L6:
	mov	edx, DWORD PTR AR5K_PHY_SPENDING[rip]
	mov	rdi, rbp
	call	ath5k_hw_reg_write@PLT
	mov	rax, QWORD PTR 0[rbp]
	cmp	rax, QWORD PTR AR5K_RF5112[rip]
	mov	edx, DWORD PTR AR5K_PHY_SLMT[rip]
	je	.L8
	cmp	rax, QWORD PTR AR5K_RF5413[rip]
	je	.L8
	mov	eax, DWORD PTR AR5K_SREV_AR2417[rip]
	sar	eax, 4
	cmp	DWORD PTR 8[rbp], eax
	je	.L8
	mov	rdi, rbp
	mov	esi, 10
	call	ath5k_hw_reg_write@PLT
	mov	edx, DWORD PTR AR5K_PHY_SCAL[rip]
	mov	rdi, rbp
	mov	esi, 12
	call	ath5k_hw_reg_write@PLT
	mov	edx, DWORD PTR AR5K_PHY_SCLOCK[rip]
	mov	rdi, rbp
	mov	esi, 3
	call	ath5k_hw_reg_write@PLT
	mov	edx, DWORD PTR AR5K_PHY_SDELAY[rip]
	mov	rdi, rbp
	mov	esi, 32
	call	ath5k_hw_reg_write@PLT
	mov	edx, DWORD PTR AR5K_PCICFG_SLEEP_CLOCK_RATE[rip]
	mov	ecx, 3
	mov	rdi, rbp
	mov	esi, DWORD PTR AR5K_PCICFG[rip]
	call	AR5K_REG_WRITE_BITS@PLT
	jmp	.L10
	.p2align 4,,10
	.p2align 3
.L8:
	mov	esi, 38
	mov	rdi, rbp
	call	ath5k_hw_reg_write@PLT
	mov	edx, DWORD PTR AR5K_PHY_SCAL[rip]
	mov	esi, 13
	mov	rdi, rbp
	call	ath5k_hw_reg_write@PLT
	mov	edx, DWORD PTR AR5K_PHY_SCLOCK[rip]
	mov	esi, 7
	mov	rdi, rbp
	call	ath5k_hw_reg_write@PLT
	mov	edx, DWORD PTR AR5K_PHY_SDELAY[rip]
	mov	esi, 63
	mov	rdi, rbp
	call	ath5k_hw_reg_write@PLT
	mov	edx, DWORD PTR AR5K_PCICFG_SLEEP_CLOCK_RATE[rip]
	mov	ecx, 2
	mov	rdi, rbp
	mov	esi, DWORD PTR AR5K_PCICFG[rip]
	call	AR5K_REG_WRITE_BITS@PLT
.L10:
	mov	edx, DWORD PTR AR5K_PCICFG_SLEEP_CLOCK_EN[rip]
	mov	esi, DWORD PTR AR5K_PCICFG[rip]
	add	rsp, 8
	.cfi_def_cfa_offset 24
	mov	rdi, rbp
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	jmp	AR5K_REG_ENABLE_BITS@PLT
	.cfi_endproc
.LFE0:
	.size	ath5k_hw_set_sleep_clock, .-ath5k_hw_set_sleep_clock
	.comm	AR5K_USEC_5211,4,4
	.comm	AR5K_USEC_32,4,4
	.comm	AR5K_TSF_PARM_INC,4,4
	.comm	AR5K_TSF_PARM,4,4
	.comm	AR5K_SREV_AR2417,4,4
	.comm	AR5K_RF5413,8,8
	.comm	AR5K_RF5112,8,8
	.comm	AR5K_RF2317,8,8
	.comm	AR5K_RF2316,8,8
	.comm	AR5K_PHY_SPENDING,4,4
	.comm	AR5K_PHY_SLMT_32MHZ,4,4
	.comm	AR5K_PHY_SLMT,4,4
	.comm	AR5K_PHY_SDELAY_32MHZ,4,4
	.comm	AR5K_PHY_SDELAY,4,4
	.comm	AR5K_PHY_SCR,4,4
	.comm	AR5K_PHY_SCLOCK_32MHZ,4,4
	.comm	AR5K_PHY_SCLOCK,4,4
	.comm	AR5K_PHY_SCAL_32MHZ_HB63,4,4
	.comm	AR5K_PHY_SCAL_32MHZ_2417,4,4
	.comm	AR5K_PHY_SCAL_32MHZ,4,4
	.comm	AR5K_PHY_SCAL,4,4
	.comm	AR5K_PCICFG_SLEEP_CLOCK_RATE,4,4
	.comm	AR5K_PCICFG_SLEEP_CLOCK_EN,4,4
	.comm	AR5K_PCICFG,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_reset.c_ath5k_hw_set_sleep_clock.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	ath5k_hw_set_sleep_clock, %function
ath5k_hw_set_sleep_clock:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, lr}
	mov	r4, r0
	ldr	r0, [r0, #12]
	mov	r5, r1
	bl	AR5K_EEPROM_HAS32KHZCRYSTAL
	cmp	r0, #0
	beq	.L2
	cmp	r5, #0
	bne	.L31
.L4:
	ldr	r3, .L34
	ldr	r5, .L34+4
	ldr	r2, [r3]
	ldr	r1, [r5]
	mov	r0, r4
	bl	AR5K_REG_DISABLE_BITS
	ldr	r3, .L34+8
	ldr	r1, [r5]
	ldr	r2, [r3]
	mov	r0, r4
	mov	r3, #0
	bl	AR5K_REG_WRITE_BITS
	ldr	r3, .L34+12
	mov	r1, #31
	ldr	r2, [r3]
	mov	r0, r4
	bl	ath5k_hw_reg_write
	ldr	r3, .L34+16
	ldr	r2, .L34+20
	ldr	r6, .L34+24
	ldr	r2, [r2]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ath5k_hw_reg_write
	ldr	r2, [r6]
	ldr	r3, [r4, #4]
	cmp	r3, r2, asr #4
	beq	.L32
	ldr	r3, [r4, #8]
	cmp	r3, #0
	ldrne	r3, .L34+28
	ldreq	r3, .L34+32
	ldr	r1, [r3]
.L12:
	ldr	r3, .L34+36
	mov	r0, r4
	ldr	r2, [r3]
	bl	ath5k_hw_reg_write
	ldr	r3, .L34+40
	ldr	r2, .L34+44
	ldr	r1, [r3]
	ldr	r2, [r2]
	mov	r0, r4
	bl	ath5k_hw_reg_write
	ldr	r3, .L34+48
	ldr	r2, .L34+52
	ldr	r5, .L34+56
	ldr	r2, [r2]
	ldr	r1, [r3]
	mov	r0, r4
	bl	ath5k_hw_reg_write
	ldr	r2, [r5]
	ldr	r3, [r4]
	cmp	r3, r2
	beq	.L22
	ldr	r2, .L34+60
	ldr	r2, [r2]
	cmp	r3, r2
	beq	.L22
	ldr	r2, .L34+64
	ldr	r2, [r2]
	cmp	r3, r2
	beq	.L22
	ldr	r2, [r6]
	ldr	r3, [r4, #4]
	cmp	r3, r2, asr #4
	moveq	r1, #20
	movne	r1, #24
.L14:
	ldr	r3, .L34+68
	mov	r0, r4
	ldr	r2, [r3]
	bl	ath5k_hw_reg_write
	ldr	r3, .L34+72
	ldr	r2, .L34+76
	ldr	r1, [r3]
	ldr	r2, [r2]
	mov	r3, #1
	mov	r0, r4
	bl	AR5K_REG_WRITE_BITS
	ldr	r2, [r5]
	ldr	r3, [r4]
	cmp	r3, r2
	beq	.L26
	ldr	r2, .L34+60
	ldr	r2, [r2]
	cmp	r3, r2
	beq	.L26
	ldr	r2, .L34+64
	ldr	r2, [r2]
	cmp	r3, r2
	beq	.L26
	ldr	r2, .L34+80
	ldr	r2, [r2]
	cmp	r3, r2
	moveq	r3, #39
	movne	r3, #31
.L15:
	ldr	r2, .L34+84
	ldr	r1, .L34+88
	mov	r0, r4
	pop	{r4, r5, r6, lr}
	ldr	r2, [r2]
	ldr	r1, [r1]
	b	AR5K_REG_WRITE_BITS
.L32:
	ldr	r3, .L34+92
	ldr	r1, [r3]
	b	.L12
.L26:
	mov	r3, #39
	b	.L15
.L22:
	mov	r1, #20
	b	.L14
.L2:
	ldr	r0, [r4, #12]
	bl	AR5K_EEPROM_HAS32KHZCRYSTAL_OLD
	cmp	r0, #0
	beq	.L4
	cmp	r5, #0
	beq	.L4
.L31:
	ldr	r3, .L34+88
	ldr	r2, .L34+84
	ldr	r1, [r3]
	ldr	r2, [r2]
	mov	r3, #1
	mov	r0, r4
	bl	AR5K_REG_WRITE_BITS
	ldr	r3, .L34+72
	ldr	r2, .L34+76
	ldr	r1, [r3]
	ldr	r2, [r2]
	mov	r3, #61
	mov	r0, r4
	bl	AR5K_REG_WRITE_BITS
	ldr	r3, .L34+12
	ldr	r5, .L34+56
	ldr	r2, [r3]
	mov	r1, #31
	mov	r0, r4
	bl	ath5k_hw_reg_write
	ldr	r2, [r5]
	ldr	r3, [r4]
	cmp	r3, r2
	beq	.L18
	ldr	r2, .L34+60
	ldr	r2, [r2]
	cmp	r3, r2
	beq	.L18
	ldr	r2, .L34+64
	ldr	r2, [r2]
	cmp	r3, r2
	beq	.L18
	ldr	r2, .L34+24
	ldr	r3, [r4, #4]
	ldr	r2, [r2]
	cmp	r3, r2, asr #4
	moveq	r1, #20
	movne	r1, #24
.L6:
	ldr	r3, .L34+68
	mov	r0, r4
	ldr	r2, [r3]
	bl	ath5k_hw_reg_write
	ldr	r2, [r5]
	ldr	r3, [r4]
	cmp	r3, r2
	beq	.L33
	ldr	r1, .L34+60
	ldr	r2, .L34+20
	ldr	r1, [r1]
	ldr	r2, [r2]
	cmp	r3, r1
	beq	.L8
	ldr	r1, .L34+24
	ldr	r3, [r4, #4]
	ldr	r1, [r1]
	cmp	r3, r1, asr #4
	beq	.L8
	mov	r1, #10
	mov	r0, r4
	bl	ath5k_hw_reg_write
	ldr	r3, .L34+36
	mov	r1, #12
	ldr	r2, [r3]
	mov	r0, r4
	bl	ath5k_hw_reg_write
	ldr	r3, .L34+44
	mov	r1, #3
	ldr	r2, [r3]
	mov	r0, r4
	bl	ath5k_hw_reg_write
	ldr	r3, .L34+52
	mov	r1, #32
	ldr	r2, [r3]
	mov	r0, r4
	bl	ath5k_hw_reg_write
	ldr	r5, .L34+4
	ldr	r3, .L34+8
	mov	r0, r4
	ldr	r2, [r3]
	ldr	r1, [r5]
	mov	r3, #3
	bl	AR5K_REG_WRITE_BITS
.L10:
	ldr	r3, .L34
	mov	r0, r4
	ldr	r1, [r5]
	ldr	r2, [r3]
	pop	{r4, r5, r6, lr}
	b	AR5K_REG_ENABLE_BITS
.L18:
	mov	r1, #20
	b	.L6
.L33:
	ldr	r3, .L34+20
	ldr	r2, [r3]
.L8:
	mov	r1, #38
	mov	r0, r4
	bl	ath5k_hw_reg_write
	ldr	r3, .L34+36
	mov	r1, #13
	ldr	r2, [r3]
	mov	r0, r4
	bl	ath5k_hw_reg_write
	ldr	r3, .L34+44
	mov	r1, #7
	ldr	r2, [r3]
	mov	r0, r4
	bl	ath5k_hw_reg_write
	ldr	r3, .L34+52
	mov	r1, #63
	ldr	r2, [r3]
	mov	r0, r4
	bl	ath5k_hw_reg_write
	ldr	r5, .L34+4
	ldr	r3, .L34+8
	mov	r0, r4
	ldr	r2, [r3]
	ldr	r1, [r5]
	mov	r3, #2
	bl	AR5K_REG_WRITE_BITS
	b	.L10
.L35:
	.align	2
.L34:
	.word	AR5K_PCICFG_SLEEP_CLOCK_EN
	.word	AR5K_PCICFG
	.word	AR5K_PCICFG_SLEEP_CLOCK_RATE
	.word	AR5K_PHY_SCR
	.word	AR5K_PHY_SLMT_32MHZ
	.word	AR5K_PHY_SLMT
	.word	AR5K_SREV_AR2417
	.word	AR5K_PHY_SCAL_32MHZ_HB63
	.word	AR5K_PHY_SCAL_32MHZ
	.word	AR5K_PHY_SCAL
	.word	AR5K_PHY_SCLOCK_32MHZ
	.word	AR5K_PHY_SCLOCK
	.word	AR5K_PHY_SDELAY_32MHZ
	.word	AR5K_PHY_SDELAY
	.word	AR5K_RF5112
	.word	AR5K_RF5413
	.word	AR5K_RF2316
	.word	AR5K_PHY_SPENDING
	.word	AR5K_TSF_PARM
	.word	AR5K_TSF_PARM_INC
	.word	AR5K_RF2317
	.word	AR5K_USEC_32
	.word	AR5K_USEC_5211
	.word	AR5K_PHY_SCAL_32MHZ_2417
	.size	ath5k_hw_set_sleep_clock, .-ath5k_hw_set_sleep_clock
	.comm	AR5K_USEC_5211,4,4
	.comm	AR5K_USEC_32,4,4
	.comm	AR5K_TSF_PARM_INC,4,4
	.comm	AR5K_TSF_PARM,4,4
	.comm	AR5K_SREV_AR2417,4,4
	.comm	AR5K_RF5413,4,4
	.comm	AR5K_RF5112,4,4
	.comm	AR5K_RF2317,4,4
	.comm	AR5K_RF2316,4,4
	.comm	AR5K_PHY_SPENDING,4,4
	.comm	AR5K_PHY_SLMT_32MHZ,4,4
	.comm	AR5K_PHY_SLMT,4,4
	.comm	AR5K_PHY_SDELAY_32MHZ,4,4
	.comm	AR5K_PHY_SDELAY,4,4
	.comm	AR5K_PHY_SCR,4,4
	.comm	AR5K_PHY_SCLOCK_32MHZ,4,4
	.comm	AR5K_PHY_SCLOCK,4,4
	.comm	AR5K_PHY_SCAL_32MHZ_HB63,4,4
	.comm	AR5K_PHY_SCAL_32MHZ_2417,4,4
	.comm	AR5K_PHY_SCAL_32MHZ,4,4
	.comm	AR5K_PHY_SCAL,4,4
	.comm	AR5K_PCICFG_SLEEP_CLOCK_RATE,4,4
	.comm	AR5K_PCICFG_SLEEP_CLOCK_EN,4,4
	.comm	AR5K_PCICFG,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
