	.file	"extr_perf_event.c_register_sh_pmu.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC0:
	.string	"Performance Events: %s support registered\n"
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"cpu"
.LC2:
	.string	"PERF_SUPERH"
	.text
	.p2align 4
	.globl	register_sh_pmu
	.type	register_sh_pmu, @function
register_sh_pmu:
.LFB0:
	.cfi_startproc
	endbr64
	cmp	QWORD PTR sh_pmu[rip], 0
	je	.L2
	mov	eax, DWORD PTR EBUSY[rip]
	neg	eax
	ret
	.p2align 4,,10
	.p2align 3
.L2:
	push	rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	mov	esi, DWORD PTR 8[rdi]
	mov	rbx, rdi
	mov	QWORD PTR sh_pmu[rip], rdi
	lea	rdi, .LC0[rip]
	call	pr_info@PLT
	mov	eax, DWORD PTR PERF_PMU_CAP_NO_INTERRUPT[rip]
	xor	edi, edi
	or	DWORD PTR pmu[rip], eax
	mov	rax, QWORD PTR MAX_HWEVENTS[rip]
	cmp	QWORD PTR [rbx], rax
	setg	dil
	call	WARN_ON@PLT
	mov	edx, DWORD PTR PERF_TYPE_RAW[rip]
	lea	rsi, .LC1[rip]
	lea	rdi, pmu[rip]
	call	perf_pmu_register@PLT
	mov	edx, DWORD PTR sh_pmu_prepare_cpu[rip]
	xor	ecx, ecx
	mov	edi, DWORD PTR CPUHP_PERF_SUPERH[rip]
	lea	rsi, .LC2[rip]
	call	cpuhp_setup_state@PLT
	xor	eax, eax
	pop	rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE0:
	.size	register_sh_pmu, .-register_sh_pmu
	.comm	sh_pmu_prepare_cpu,4,4
	.comm	sh_pmu,8,8
	.comm	pmu,4,4
	.comm	PERF_TYPE_RAW,4,4
	.comm	PERF_PMU_CAP_NO_INTERRUPT,4,4
	.comm	MAX_HWEVENTS,8,8
	.comm	EBUSY,4,4
	.comm	CPUHP_PERF_SUPERH,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_perf_event.c_register_sh_pmu.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"Performance Events: %s support registered\012\000"
	.align	2
.LC1:
	.ascii	"cpu\000"
	.align	2
.LC2:
	.ascii	"PERF_SUPERH\000"
	.text
	.align	2
	.global	register_sh_pmu
	.syntax unified
	.arm
	.fpu softvfp
	.type	register_sh_pmu, %function
register_sh_pmu:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	ldr	r3, .L6
	push	{r4, r5, r6, lr}
	ldr	r4, [r3]
	cmp	r4, #0
	beq	.L2
	ldr	r3, .L6+4
	ldr	r0, [r3]
	rsb	r0, r0, #0
	pop	{r4, r5, r6, pc}
.L2:
	mov	r5, r0
	ldr	r1, [r0, #4]
	ldr	r0, .L6+8
	str	r5, [r3]
	bl	pr_info
	ldr	r2, .L6+12
	ldr	r6, .L6+16
	ldr	r3, .L6+20
	ldr	r0, [r5]
	ldr	r1, [r2]
	ldr	r2, [r3]
	ldr	r3, [r6]
	cmp	r0, r1
	movle	r0, #0
	movgt	r0, #1
	orr	r3, r3, r2
	str	r3, [r6]
	bl	WARN_ON
	ldr	r3, .L6+24
	mov	r0, r6
	ldr	r2, [r3]
	ldr	r1, .L6+28
	bl	perf_pmu_register
	ldr	r3, .L6+32
	ldr	r2, .L6+36
	ldr	r0, [r3]
	ldr	r2, [r2]
	mov	r3, r4
	ldr	r1, .L6+40
	bl	cpuhp_setup_state
	mov	r0, r4
	pop	{r4, r5, r6, pc}
.L7:
	.align	2
.L6:
	.word	sh_pmu
	.word	EBUSY
	.word	.LC0
	.word	MAX_HWEVENTS
	.word	pmu
	.word	PERF_PMU_CAP_NO_INTERRUPT
	.word	PERF_TYPE_RAW
	.word	.LC1
	.word	CPUHP_PERF_SUPERH
	.word	sh_pmu_prepare_cpu
	.word	.LC2
	.size	register_sh_pmu, .-register_sh_pmu
	.comm	sh_pmu_prepare_cpu,4,4
	.comm	sh_pmu,4,4
	.comm	pmu,4,4
	.comm	PERF_TYPE_RAW,4,4
	.comm	PERF_PMU_CAP_NO_INTERRUPT,4,4
	.comm	MAX_HWEVENTS,4,4
	.comm	EBUSY,4,4
	.comm	CPUHP_PERF_SUPERH,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
