	.file	"extr_i386.c_ix86_expand_vector_init_general.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	ix86_expand_vector_init_general, @function
ix86_expand_vector_init_general:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	mov	r14d, esi
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rcx
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	ebx, edi
	mov	edi, esi
	sub	rsp, 104
	.cfi_def_cfa_offset 160
	mov	DWORD PTR 36[rsp], esi
	mov	QWORD PTR 40[rsp], rdx
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 88[rsp], rax
	xor	eax, eax
	call	GET_MODE_INNER@PLT
	mov	r12d, eax
	lea	eax, -128[r14]
	cmp	eax, 9
	ja	.L2
	lea	rdx, .L4[rip]
	movsx	rax, DWORD PTR [rdx+rax*4]
	add	rax, rdx
	notrack jmp	rax
	.section	.rodata
	.align 4
	.align 4
.L4:
	.long	.L3-.L4
	.long	.L3-.L4
	.long	.L8-.L4
	.long	.L26-.L4
	.long	.L3-.L4
	.long	.L6-.L4
	.long	.L6-.L4
	.long	.L5-.L4
	.long	.L5-.L4
	.long	.L3-.L4
	.text
.L2:
	xor	eax, eax
	call	gcc_unreachable@PLT
.L3:
	mov	r15d, DWORD PTR 36[rsp]
	mov	edi, r15d
	call	GET_MODE_INNER@PLT
	mov	edi, r15d
	mov	r12d, eax
	call	GET_MODE_NUNITS@PLT
	mov	edi, r15d
	mov	ebx, eax
	call	GET_MODE_SIZE@PLT
	mov	edi, r12d
	cdq
	idiv	DWORD PTR UNITS_PER_WORD[rip]
	mov	DWORD PTR 32[rsp], eax
	mov	eax, ebx
	mov	ebx, DWORD PTR 32[rsp]
	cdq
	idiv	ebx
	mov	DWORD PTR 16[rsp], eax
	call	GET_MODE_BITSIZE@PLT
	mov	edi, eax
	call	GEN_INT@PLT
	mov	r13, rax
	test	ebx, ebx
	jle	.L14
	lea	rax, 48[rsp]
	mov	DWORD PTR 4[rsp], -1
	mov	QWORD PTR 8[rsp], rax
	mov	eax, DWORD PTR 16[rsp]
	sub	eax, 2
	mov	DWORD PTR 20[rsp], eax
	mov	eax, DWORD PTR 32[rsp]
	sub	eax, 1
	lea	rax, 56[rsp+rax*8]
	mov	QWORD PTR 24[rsp], rax
	.p2align 4,,10
	.p2align 3
.L19:
	mov	ecx, DWORD PTR 16[rsp]
	mov	r14, QWORD PTR NULL_RTX[rip]
	test	ecx, ecx
	jle	.L17
	mov	r15d, DWORD PTR 20[rsp]
	xor	esi, esi
	mov	rdi, rbp
	lea	edx, 1[r15]
	call	XVECEXP@PLT
	mov	edi, DWORD PTR word_mode[rip]
	mov	ecx, 1
	mov	esi, r12d
	mov	rdx, rax
	call	convert_modes@PLT
	mov	r14, rax
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L18:
	mov	edx, r15d
	xor	esi, esi
	mov	rdi, rbp
	sub	r15d, 1
	call	XVECEXP@PLT
	mov	edi, DWORD PTR word_mode[rip]
	mov	ecx, 1
	mov	esi, r12d
	mov	rdx, rax
	call	convert_modes@PLT
	sub	rsp, 8
	.cfi_def_cfa_offset 168
	mov	r8, r14
	mov	rdx, r14
	mov	rbx, rax
	mov	eax, DWORD PTR OPTAB_LIB_WIDEN[rip]
	mov	rcx, r13
	mov	esi, DWORD PTR ASHIFT[rip]
	mov	edi, DWORD PTR word_mode[rip]
	mov	r9d, 1
	push	rax
	.cfi_def_cfa_offset 176
	call	expand_simple_binop@PLT
	mov	esi, DWORD PTR IOR[rip]
	mov	edi, DWORD PTR word_mode[rip]
	mov	rcx, rbx
	mov	rdx, rax
	mov	eax, DWORD PTR OPTAB_LIB_WIDEN[rip]
	mov	r9d, 1
	mov	r8, rdx
	mov	DWORD PTR [rsp], eax
	call	expand_simple_binop@PLT
	mov	r14, rax
	pop	rax
	.cfi_def_cfa_offset 168
	pop	rdx
	.cfi_def_cfa_offset 160
.L24:
	cmp	r15d, DWORD PTR 4[rsp]
	jne	.L18
.L17:
	mov	rax, QWORD PTR 8[rsp]
	mov	ecx, DWORD PTR 16[rsp]
	add	DWORD PTR 20[rsp], ecx
	mov	QWORD PTR [rax], r14
	add	rax, 8
	add	DWORD PTR 4[rsp], ecx
	mov	QWORD PTR 8[rsp], rax
	cmp	rax, QWORD PTR 24[rsp]
	jne	.L19
	cmp	DWORD PTR 32[rsp], 1
	je	.L35
.L14:
	cmp	DWORD PTR 32[rsp], 2
	je	.L36
	cmp	DWORD PTR 32[rsp], 4
	je	.L37
	xor	eax, eax
	call	gcc_unreachable@PLT
.L1:
	mov	rax, QWORD PTR 88[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L38
	add	rsp, 104
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L6:
	.cfi_restore_state
	or	ebx, DWORD PTR TARGET_SSE[rip]
	je	.L3
	.p2align 4,,10
	.p2align 3
.L5:
	xor	edx, edx
	xor	esi, esi
	mov	rdi, rbp
	call	XVECEXP@PLT
	xor	esi, esi
	mov	rdi, rbp
	mov	edx, 1
	mov	r13, rax
	call	XVECEXP@PLT
	mov	esi, r12d
	mov	rdi, r13
	mov	r14, rax
	call	register_operand@PLT
	test	eax, eax
	je	.L39
.L10:
	mov	esi, r12d
	mov	rdi, r14
	call	register_operand@PLT
	test	eax, eax
	je	.L40
.L11:
	mov	edi, DWORD PTR 36[rsp]
	mov	rdx, r14
	mov	rsi, r13
	call	gen_rtx_VEC_CONCAT@PLT
	mov	rsi, QWORD PTR 40[rsp]
	mov	edi, DWORD PTR VOIDmode[rip]
	mov	edx, eax
	call	gen_rtx_SET@PLT
	mov	edi, eax
	call	emit_insn@PLT
	jmp	.L1
.L8:
	mov	r12d, 133
.L7:
	mov	edi, r12d
	call	gen_reg_rtx@PLT
	xor	esi, esi
	mov	edx, 1
	mov	rdi, rbp
	mov	r13, rax
	call	XVECEXP@PLT
	xor	edx, edx
	xor	esi, esi
	mov	rdi, rbp
	mov	r14, rax
	call	XVECEXP@PLT
	mov	rdx, r14
	mov	edi, 2
	mov	rsi, rax
	call	gen_rtvec@PLT
	mov	edi, r12d
	mov	esi, eax
	call	gen_rtx_PARALLEL@PLT
	mov	rsi, r13
	xor	edi, edi
	mov	rdx, rax
	call	ix86_expand_vector_init@PLT
	mov	edi, r12d
	call	gen_reg_rtx@PLT
	xor	esi, esi
	mov	edx, 3
	mov	rdi, rbp
	mov	r14, rax
	call	XVECEXP@PLT
	xor	esi, esi
	mov	edx, 2
	mov	rdi, rbp
	mov	rbx, rax
	call	XVECEXP@PLT
	mov	rdx, rbx
	mov	edi, 2
	mov	rsi, rax
	call	gen_rtvec@PLT
	mov	edi, r12d
	mov	esi, eax
	call	gen_rtx_PARALLEL@PLT
	xor	edi, edi
	mov	rsi, r14
	mov	rdx, rax
	call	ix86_expand_vector_init@PLT
	mov	esi, r12d
	mov	rdi, r13
	call	register_operand@PLT
	test	eax, eax
	jne	.L10
.L39:
	mov	rsi, r13
	mov	edi, r12d
	call	force_reg@PLT
	mov	esi, r12d
	mov	rdi, r14
	mov	r13, rax
	call	register_operand@PLT
	test	eax, eax
	jne	.L11
.L40:
	mov	rsi, r14
	mov	edi, r12d
	call	force_reg@PLT
	mov	r14, rax
	jmp	.L11
.L26:
	mov	r12d, 134
	jmp	.L7
.L37:
	mov	edi, 130
	call	gen_reg_rtx@PLT
	lea	rsi, 48[rsp]
	mov	edi, 4
	mov	rbp, rax
	call	gen_rtvec_v@PLT
	mov	edi, 130
	mov	esi, eax
	call	gen_rtx_PARALLEL@PLT
	mov	esi, 130
	mov	rdx, rbp
	xor	edi, edi
	mov	rcx, rax
	call	ix86_expand_vector_init_general
	mov	rsi, rbp
.L33:
	mov	edi, DWORD PTR 36[rsp]
	call	gen_lowpart@PLT
	mov	rdi, QWORD PTR 40[rsp]
	mov	rsi, rax
	call	emit_move_insn@PLT
	jmp	.L1
.L35:
	mov	rsi, QWORD PTR 48[rsp]
	jmp	.L33
.L36:
	mov	edi, DWORD PTR 36[rsp]
	call	gen_reg_rtx@PLT
	mov	edi, DWORD PTR VOIDmode[rip]
	mov	rsi, rax
	mov	rbp, rax
	call	gen_rtx_CLOBBER@PLT
	mov	edi, eax
	call	emit_insn@PLT
	mov	edi, DWORD PTR word_mode[rip]
	mov	r12, QWORD PTR 48[rsp]
	mov	rsi, rbp
	call	gen_lowpart@PLT
	mov	rsi, r12
	mov	rdi, rax
	call	emit_move_insn@PLT
	mov	edi, DWORD PTR word_mode[rip]
	mov	r12, QWORD PTR 56[rsp]
	mov	rsi, rbp
	call	gen_highpart@PLT
	mov	rsi, r12
	mov	rdi, rax
	call	emit_move_insn@PLT
	mov	rdi, QWORD PTR 40[rsp]
	mov	rsi, rbp
	call	emit_move_insn@PLT
	jmp	.L1
.L38:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	ix86_expand_vector_init_general, .-ix86_expand_vector_init_general
	.comm	word_mode,4,4
	.comm	VOIDmode,4,4
	.comm	UNITS_PER_WORD,4,4
	.comm	TARGET_SSE,4,4
	.comm	OPTAB_LIB_WIDEN,4,4
	.comm	NULL_RTX,8,8
	.comm	IOR,4,4
	.comm	ASHIFT,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_i386.c_ix86_expand_vector_init_general.c"
	.text
	.global	__aeabi_idiv
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	ix86_expand_vector_init_general, %function
ix86_expand_vector_init_general:
	@ args = 0, pretend = 0, frame = 56
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	mov	r9, r3
	sub	sp, sp, #76
	ldr	r3, .L41
	mov	r4, r1
	str	r1, [sp, #36]
	str	r2, [sp, #44]
	mov	r5, r0
	mov	r0, r1
	ldr	r3, [r3]
	str	r3, [sp, #68]
	mov	r3,#0
	bl	GET_MODE_INNER
	sub	r3, r4, #128
	mov	r4, r0
	cmp	r3, #9
	ldrls	pc, [pc, r3, asl #2]
	b	.L2
.L4:
	.word	.L3
	.word	.L3
	.word	.L8
	.word	.L26
	.word	.L3
	.word	.L6
	.word	.L6
	.word	.L5
	.word	.L5
	.word	.L3
.L2:
	bl	gcc_unreachable
.L3:
	ldr	r5, [sp, #36]
	mov	r0, r5
	bl	GET_MODE_INNER
	mov	r10, r0
	mov	r0, r5
	bl	GET_MODE_NUNITS
	mov	r4, r0
	mov	r0, r5
	bl	GET_MODE_SIZE
	ldr	r3, .L41+4
	ldr	r1, [r3]
	bl	__aeabi_idiv
	mov	r3, r0
	str	r0, [sp, #40]
	mov	r1, r3
	mov	r0, r4
	mov	r4, r3
	bl	__aeabi_idiv
	mov	r3, r0
	mov	r0, r10
	str	r3, [sp, #24]
	bl	GET_MODE_BITSIZE
	bl	GEN_INT
	cmp	r4, #0
	mov	fp, r0
	ble	.L14
	mvn	r3, #0
	ldr	r2, [sp, #40]
	str	r3, [sp, #16]
	add	r3, sp, #52
	str	r3, [sp, #28]
	add	r3, r3, r2, lsl #2
	str	r3, [sp, #32]
	ldr	r3, [sp, #24]
	ldr	r6, .L41+8
	sub	r3, r3, #2
	ldr	r8, .L41+12
	str	r3, [sp, #20]
.L19:
	ldr	r3, [sp, #24]
	cmp	r3, #0
	ble	.L34
	ldr	r5, [sp, #20]
	mov	r1, #0
	add	r2, r5, #1
	mov	r0, r9
	bl	XVECEXP
	mov	r3, #1
	mov	r2, r0
	mov	r1, r10
	ldr	r0, [r6]
	bl	convert_modes
	mov	r4, r0
	b	.L24
.L18:
	mov	r2, r5
	mov	r1, #0
	mov	r0, r9
	bl	XVECEXP
	mov	r3, #1
	mov	r2, r0
	mov	r1, r10
	ldr	r0, [r6]
	mov	r7, r3
	bl	convert_modes
	mov	ip, r0
	ldr	r3, [r8]
	ldr	r1, .L41+16
	str	r4, [sp]
	str	r3, [sp, #8]
	str	r7, [sp, #4]
	mov	r2, r4
	mov	r3, fp
	ldr	r1, [r1]
	ldr	r0, [r6]
	mov	r4, ip
	bl	expand_simple_binop
	mov	r2, r0
	ldr	r1, [r8]
	stm	sp, {r2, r7}
	str	r1, [sp, #8]
	ldr	r1, .L41+20
	mov	r3, r4
	ldr	r1, [r1]
	ldr	r0, [r6]
	bl	expand_simple_binop
	mov	r4, r0
	sub	r5, r5, #1
.L24:
	ldr	r3, [sp, #16]
	cmp	r5, r3
	bne	.L18
.L17:
	ldr	r3, [sp, #28]
	ldr	r2, [sp, #32]
	str	r4, [r3], #4
	cmp	r3, r2
	str	r3, [sp, #28]
	ldr	r2, [sp, #20]
	ldr	r3, [sp, #24]
	add	r2, r2, r3
	str	r2, [sp, #20]
	ldr	r2, [sp, #16]
	add	r3, r2, r3
	str	r3, [sp, #16]
	bne	.L19
	ldr	r3, [sp, #40]
	cmp	r3, #1
	beq	.L35
.L14:
	ldr	r3, [sp, #40]
	cmp	r3, #2
	beq	.L36
	ldr	r3, [sp, #40]
	cmp	r3, #4
	beq	.L37
	bl	gcc_unreachable
.L1:
	ldr	r3, .L41
	ldr	r2, [r3]
	ldr	r3, [sp, #68]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L38
	add	sp, sp, #76
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L6:
	ldr	r3, .L41+24
	ldr	r3, [r3]
	orrs	r3, r5, r3
	beq	.L3
.L5:
	mov	r2, #0
	mov	r0, r9
	mov	r1, r2
	bl	XVECEXP
	mov	r2, #1
	mov	r5, r0
	mov	r1, #0
	mov	r0, r9
	bl	XVECEXP
	mov	r6, r0
.L9:
	mov	r1, r4
	mov	r0, r5
	bl	register_operand
	cmp	r0, #0
	beq	.L39
.L10:
	mov	r1, r4
	mov	r0, r6
	bl	register_operand
	cmp	r0, #0
	beq	.L40
.L11:
	ldr	r3, .L41+28
	mov	r2, r6
	mov	r1, r5
	ldr	r0, [sp, #36]
	ldr	r4, [r3]
	bl	gen_rtx_VEC_CONCAT
	ldr	r1, [sp, #44]
	mov	r2, r0
	mov	r0, r4
	bl	gen_rtx_SET
	bl	emit_insn
	b	.L1
.L34:
	ldr	r3, .L41+32
	ldr	r4, [r3]
	b	.L17
.L8:
	mov	r4, #133
.L7:
	mov	r0, r4
	bl	gen_reg_rtx
	mov	r2, #0
	mov	r5, r0
	mov	r1, r2
	mov	r0, r9
	bl	XVECEXP
	mov	r2, #1
	mov	r6, r0
	mov	r1, #0
	mov	r0, r9
	bl	XVECEXP
	mov	r1, r6
	mov	r2, r0
	mov	r0, #2
	bl	gen_rtvec
	mov	r1, r0
	mov	r0, r4
	bl	gen_rtx_PARALLEL
	mov	r1, r5
	mov	r2, r0
	mov	r0, #0
	bl	ix86_expand_vector_init
	mov	r0, r4
	bl	gen_reg_rtx
	mov	r2, #2
	mov	r6, r0
	mov	r1, #0
	mov	r0, r9
	bl	XVECEXP
	mov	r2, #3
	mov	r7, r0
	mov	r1, #0
	mov	r0, r9
	bl	XVECEXP
	mov	r1, r7
	mov	r2, r0
	mov	r0, #2
	bl	gen_rtvec
	mov	r1, r0
	mov	r0, r4
	bl	gen_rtx_PARALLEL
	mov	r1, r6
	mov	r2, r0
	mov	r0, #0
	bl	ix86_expand_vector_init
	b	.L9
.L26:
	mov	r4, #134
	b	.L7
.L40:
	mov	r1, r6
	mov	r0, r4
	bl	force_reg
	mov	r6, r0
	b	.L11
.L39:
	mov	r1, r5
	mov	r0, r4
	bl	force_reg
	mov	r5, r0
	b	.L10
.L37:
	mov	r0, #130
	bl	gen_reg_rtx
	add	r1, sp, #52
	mov	r4, r0
	ldr	r0, [sp, #40]
	bl	gen_rtvec_v
	mov	r1, r0
	mov	r0, #130
	bl	gen_rtx_PARALLEL
	mov	r2, r4
	mov	r3, r0
	mov	r1, #130
	mov	r0, #0
	bl	ix86_expand_vector_init_general
	mov	r1, r4
	ldr	r0, [sp, #36]
	bl	gen_lowpart
	mov	r1, r0
	ldr	r0, [sp, #44]
	bl	emit_move_insn
	b	.L1
.L35:
	ldr	r1, [sp, #52]
	ldr	r0, [sp, #36]
	bl	gen_lowpart
	mov	r1, r0
	ldr	r0, [sp, #44]
	bl	emit_move_insn
	b	.L1
.L36:
	ldr	r0, [sp, #36]
	bl	gen_reg_rtx
	mov	r4, r0
	ldr	r3, .L41+28
	mov	r1, r0
	ldr	r5, .L41+8
	ldr	r0, [r3]
	bl	gen_rtx_CLOBBER
	bl	emit_insn
	mov	r1, r4
	ldr	r0, [r5]
	bl	gen_lowpart
	ldr	r1, [sp, #52]
	bl	emit_move_insn
	mov	r1, r4
	ldr	r0, [r5]
	bl	gen_highpart
	ldr	r1, [sp, #56]
	bl	emit_move_insn
	mov	r1, r4
	ldr	r0, [sp, #44]
	bl	emit_move_insn
	b	.L1
.L38:
	bl	__stack_chk_fail
.L42:
	.align	2
.L41:
	.word	.LC0
	.word	UNITS_PER_WORD
	.word	word_mode
	.word	OPTAB_LIB_WIDEN
	.word	ASHIFT
	.word	IOR
	.word	TARGET_SSE
	.word	VOIDmode
	.word	NULL_RTX
	.size	ix86_expand_vector_init_general, .-ix86_expand_vector_init_general
	.comm	word_mode,4,4
	.comm	VOIDmode,4,4
	.comm	UNITS_PER_WORD,4,4
	.comm	TARGET_SSE,4,4
	.comm	OPTAB_LIB_WIDEN,4,4
	.comm	NULL_RTX,4,4
	.comm	IOR,4,4
	.comm	ASHIFT,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
