	.file	"extr_tegra_xhci.c_enable_fdt_resources.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC0:
	.string	"Cannot reset 'xusb_host' reset\n"
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Cannot reset 'xusb_ss' reset\n"
	.section	.rodata.str1.8
	.align 8
.LC2:
	.string	"Cannot enable 'avddio_pex' regulator\n"
	.align 8
.LC3:
	.string	"Cannot enable 'dvddio_pex' regulator\n"
	.align 8
.LC4:
	.string	"Cannot enable 'avdd_usb' regulator\n"
	.align 8
.LC5:
	.string	"Cannot enable 'avdd_pll_utmip-5v' regulator\n"
	.align 8
.LC6:
	.string	"Cannot enable 'avdd_pll_erefe' regulator\n"
	.align 8
.LC7:
	.string	"Cannot enable 'avdd_usb_ss_pll' regulator\n"
	.align 8
.LC8:
	.string	"Cannot enable 'hvdd_usb_ss' regulator\n"
	.align 8
.LC9:
	.string	"Cannot enable 'hvdd_usb_ss_pll_e' regulator\n"
	.align 8
.LC10:
	.string	"Cannot powerdown  'xusba' domain\n"
	.align 8
.LC11:
	.string	"Cannot powerdown  'xusbc' domain\n"
	.align 8
.LC12:
	.string	"Cannot enable 'xusb_gate' clock\n"
	.align 8
.LC13:
	.string	"Cannot powerup 'xusbc' domain\n"
	.align 8
.LC14:
	.string	"Cannot powerup 'xusba' domain\n"
	.align 8
.LC15:
	.string	"Cannot enable 'xusb_falcon_src' clock\n"
	.align 8
.LC16:
	.string	"Cannot enable 'xusb_fs_src' clock\n"
	.align 8
.LC17:
	.string	"Cannot enable 'xusb_hs_src' clock\n"
	.section	.rodata.str1.1
.LC18:
	.string	"Cannot enable USB2_0 phy\n"
.LC19:
	.string	"Cannot enable USB2_1 phy\n"
.LC20:
	.string	"Cannot enable USB2_2 phy\n"
.LC21:
	.string	"Cannot enable USB3_0 phy\n"
	.text
	.p2align 4
	.type	enable_fdt_resources, @function
enable_fdt_resources:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	mov	rbx, rdi
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	mov	edi, DWORD PTR 40[rdi]
	call	hwreset_assert@PLT
	test	eax, eax
	jne	.L29
	mov	edi, DWORD PTR 32[rbx]
	call	hwreset_assert@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L30
	mov	edi, DWORD PTR 80[rbx]
	call	regulator_enable@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L31
	mov	edi, DWORD PTR 76[rbx]
	call	regulator_enable@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L32
	mov	edi, DWORD PTR 72[rbx]
	call	regulator_enable@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L33
	mov	edi, DWORD PTR 68[rbx]
	call	regulator_enable@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L34
	mov	edi, DWORD PTR 64[rbx]
	call	regulator_enable@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L35
	mov	edi, DWORD PTR 60[rbx]
	call	regulator_enable@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L36
	mov	edi, DWORD PTR 56[rbx]
	call	regulator_enable@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L37
	mov	edi, DWORD PTR 52[rbx]
	call	regulator_enable@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L38
	mov	edi, DWORD PTR TEGRA_POWERGATE_XUSBA[rip]
	call	tegra_powergate_power_off@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L39
	mov	edi, DWORD PTR TEGRA_POWERGATE_XUSBC[rip]
	call	tegra_powergate_power_off@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L40
	mov	edi, DWORD PTR 36[rbx]
	mov	esi, DWORD PTR TEGRA_XHCI_SS_HIGH_SPEED[rip]
	xor	edx, edx
	call	clk_set_freq@PLT
	mov	edi, DWORD PTR 48[rbx]
	call	clk_enable@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L41
	mov	edx, DWORD PTR 40[rbx]
	mov	esi, DWORD PTR 44[rbx]
	mov	edi, DWORD PTR TEGRA_POWERGATE_XUSBC[rip]
	call	tegra_powergate_sequence_power_up@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L42
	mov	edx, DWORD PTR 32[rbx]
	mov	esi, DWORD PTR 36[rbx]
	mov	edi, DWORD PTR TEGRA_POWERGATE_XUSBA[rip]
	call	tegra_powergate_sequence_power_up@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L43
	mov	edi, DWORD PTR 28[rbx]
	call	clk_enable@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L44
	mov	edi, DWORD PTR 24[rbx]
	call	clk_enable@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L45
	mov	edi, DWORD PTR 20[rbx]
	call	clk_enable@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L46
	mov	edi, DWORD PTR 16[rbx]
	call	phy_enable@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L47
	mov	edi, DWORD PTR 12[rbx]
	call	phy_enable@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L48
	mov	edi, DWORD PTR 8[rbx]
	call	phy_enable@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L49
	mov	edi, DWORD PTR 4[rbx]
	call	phy_enable@PLT
	mov	r12d, eax
	test	eax, eax
	je	.L1
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC21[rip]
	call	device_printf@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L30:
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC1[rip]
	call	device_printf@PLT
.L1:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	mov	eax, r12d
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L29:
	.cfi_restore_state
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC0[rip]
	mov	r12d, eax
	call	device_printf@PLT
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	mov	eax, r12d
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L32:
	.cfi_restore_state
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC3[rip]
	call	device_printf@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L31:
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC2[rip]
	call	device_printf@PLT
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	mov	eax, r12d
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L33:
	.cfi_restore_state
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC4[rip]
	call	device_printf@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L36:
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC7[rip]
	call	device_printf@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L34:
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC5[rip]
	call	device_printf@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L35:
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC6[rip]
	call	device_printf@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L37:
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC8[rip]
	call	device_printf@PLT
	jmp	.L1
.L38:
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC9[rip]
	call	device_printf@PLT
	jmp	.L1
.L39:
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC10[rip]
	call	device_printf@PLT
	jmp	.L1
.L40:
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC11[rip]
	call	device_printf@PLT
	jmp	.L1
.L41:
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC12[rip]
	call	device_printf@PLT
	jmp	.L1
.L42:
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC13[rip]
	call	device_printf@PLT
	jmp	.L1
.L43:
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC14[rip]
	call	device_printf@PLT
	jmp	.L1
.L44:
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC15[rip]
	call	device_printf@PLT
	jmp	.L1
.L45:
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC16[rip]
	call	device_printf@PLT
	jmp	.L1
.L46:
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC17[rip]
	call	device_printf@PLT
	jmp	.L1
.L47:
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC18[rip]
	call	device_printf@PLT
	jmp	.L1
.L49:
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC20[rip]
	call	device_printf@PLT
	jmp	.L1
.L48:
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC19[rip]
	call	device_printf@PLT
	jmp	.L1
	.cfi_endproc
.LFE0:
	.size	enable_fdt_resources, .-enable_fdt_resources
	.comm	TEGRA_XHCI_SS_HIGH_SPEED,4,4
	.comm	TEGRA_POWERGATE_XUSBC,4,4
	.comm	TEGRA_POWERGATE_XUSBA,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_tegra_xhci.c_enable_fdt_resources.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"Cannot reset 'xusb_host' reset\012\000"
	.align	2
.LC1:
	.ascii	"Cannot reset 'xusb_ss' reset\012\000"
	.align	2
.LC2:
	.ascii	"Cannot enable 'avddio_pex' regulator\012\000"
	.align	2
.LC3:
	.ascii	"Cannot enable 'dvddio_pex' regulator\012\000"
	.align	2
.LC4:
	.ascii	"Cannot enable 'avdd_usb' regulator\012\000"
	.align	2
.LC5:
	.ascii	"Cannot enable 'avdd_pll_utmip-5v' regulator\012\000"
	.align	2
.LC6:
	.ascii	"Cannot enable 'avdd_pll_erefe' regulator\012\000"
	.align	2
.LC7:
	.ascii	"Cannot enable 'avdd_usb_ss_pll' regulator\012\000"
	.align	2
.LC8:
	.ascii	"Cannot enable 'hvdd_usb_ss' regulator\012\000"
	.align	2
.LC9:
	.ascii	"Cannot enable 'hvdd_usb_ss_pll_e' regulator\012\000"
	.align	2
.LC10:
	.ascii	"Cannot powerdown  'xusba' domain\012\000"
	.align	2
.LC11:
	.ascii	"Cannot powerdown  'xusbc' domain\012\000"
	.align	2
.LC12:
	.ascii	"Cannot enable 'xusb_gate' clock\012\000"
	.align	2
.LC13:
	.ascii	"Cannot powerup 'xusbc' domain\012\000"
	.align	2
.LC14:
	.ascii	"Cannot powerup 'xusba' domain\012\000"
	.align	2
.LC15:
	.ascii	"Cannot enable 'xusb_falcon_src' clock\012\000"
	.align	2
.LC16:
	.ascii	"Cannot enable 'xusb_fs_src' clock\012\000"
	.align	2
.LC17:
	.ascii	"Cannot enable 'xusb_hs_src' clock\012\000"
	.align	2
.LC18:
	.ascii	"Cannot enable USB2_0 phy\012\000"
	.align	2
.LC19:
	.ascii	"Cannot enable USB2_1 phy\012\000"
	.align	2
.LC20:
	.ascii	"Cannot enable USB2_2 phy\012\000"
	.align	2
.LC21:
	.ascii	"Cannot enable USB3_0 phy\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	enable_fdt_resources, %function
enable_fdt_resources:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	mov	r5, r0
	ldr	r0, [r0, #40]
	bl	hwreset_assert
	subs	r4, r0, #0
	bne	.L29
	ldr	r0, [r5, #32]
	bl	hwreset_assert
	subs	r4, r0, #0
	bne	.L30
	ldr	r0, [r5, #80]
	bl	regulator_enable
	subs	r4, r0, #0
	bne	.L31
	ldr	r0, [r5, #76]
	bl	regulator_enable
	subs	r4, r0, #0
	bne	.L32
	ldr	r0, [r5, #72]
	bl	regulator_enable
	subs	r4, r0, #0
	bne	.L33
	ldr	r0, [r5, #68]
	bl	regulator_enable
	subs	r4, r0, #0
	bne	.L34
	ldr	r0, [r5, #64]
	bl	regulator_enable
	subs	r4, r0, #0
	bne	.L35
	ldr	r0, [r5, #60]
	bl	regulator_enable
	subs	r4, r0, #0
	bne	.L36
	ldr	r0, [r5, #56]
	bl	regulator_enable
	subs	r4, r0, #0
	bne	.L37
	ldr	r0, [r5, #52]
	bl	regulator_enable
	subs	r4, r0, #0
	bne	.L38
	ldr	r6, .L50
	ldr	r0, [r6]
	bl	tegra_powergate_power_off
	subs	r4, r0, #0
	bne	.L39
	ldr	r7, .L50+4
	ldr	r0, [r7]
	bl	tegra_powergate_power_off
	subs	r4, r0, #0
	bne	.L40
	ldr	r3, .L50+8
	mov	r2, r4
	ldr	r1, [r3]
	ldr	r0, [r5, #36]
	bl	clk_set_freq
	ldr	r0, [r5, #48]
	bl	clk_enable
	subs	r4, r0, #0
	bne	.L41
	ldr	r0, [r7]
	ldr	r2, [r5, #40]
	ldr	r1, [r5, #44]
	bl	tegra_powergate_sequence_power_up
	subs	r4, r0, #0
	bne	.L42
	ldr	r0, [r6]
	ldr	r2, [r5, #32]
	ldr	r1, [r5, #36]
	bl	tegra_powergate_sequence_power_up
	subs	r4, r0, #0
	bne	.L43
	ldr	r0, [r5, #28]
	bl	clk_enable
	subs	r4, r0, #0
	bne	.L44
	ldr	r0, [r5, #24]
	bl	clk_enable
	subs	r4, r0, #0
	bne	.L45
	ldr	r0, [r5, #20]
	bl	clk_enable
	subs	r4, r0, #0
	bne	.L46
	ldr	r0, [r5, #16]
	bl	phy_enable
	subs	r4, r0, #0
	bne	.L47
	ldr	r0, [r5, #12]
	bl	phy_enable
	subs	r4, r0, #0
	bne	.L48
	ldr	r0, [r5, #8]
	bl	phy_enable
	subs	r4, r0, #0
	bne	.L49
	ldr	r0, [r5, #4]
	bl	phy_enable
	subs	r4, r0, #0
	beq	.L1
	ldr	r0, [r5]
	ldr	r1, .L50+12
	bl	device_printf
	b	.L1
.L30:
	ldr	r0, [r5]
	ldr	r1, .L50+16
	bl	device_printf
.L1:
	mov	r0, r4
	pop	{r4, r5, r6, r7, r8, pc}
.L29:
	ldr	r0, [r5]
	ldr	r1, .L50+20
	bl	device_printf
	mov	r0, r4
	pop	{r4, r5, r6, r7, r8, pc}
.L32:
	ldr	r0, [r5]
	ldr	r1, .L50+24
	bl	device_printf
	b	.L1
.L31:
	ldr	r0, [r5]
	ldr	r1, .L50+28
	bl	device_printf
	mov	r0, r4
	pop	{r4, r5, r6, r7, r8, pc}
.L33:
	ldr	r0, [r5]
	ldr	r1, .L50+32
	bl	device_printf
	b	.L1
.L36:
	ldr	r0, [r5]
	ldr	r1, .L50+36
	bl	device_printf
	b	.L1
.L34:
	ldr	r0, [r5]
	ldr	r1, .L50+40
	bl	device_printf
	b	.L1
.L35:
	ldr	r0, [r5]
	ldr	r1, .L50+44
	bl	device_printf
	b	.L1
.L37:
	ldr	r0, [r5]
	ldr	r1, .L50+48
	bl	device_printf
	b	.L1
.L38:
	ldr	r0, [r5]
	ldr	r1, .L50+52
	bl	device_printf
	b	.L1
.L39:
	ldr	r0, [r5]
	ldr	r1, .L50+56
	bl	device_printf
	b	.L1
.L40:
	ldr	r0, [r5]
	ldr	r1, .L50+60
	bl	device_printf
	b	.L1
.L41:
	ldr	r0, [r5]
	ldr	r1, .L50+64
	bl	device_printf
	b	.L1
.L42:
	ldr	r0, [r5]
	ldr	r1, .L50+68
	bl	device_printf
	b	.L1
.L43:
	ldr	r0, [r5]
	ldr	r1, .L50+72
	bl	device_printf
	b	.L1
.L44:
	ldr	r0, [r5]
	ldr	r1, .L50+76
	bl	device_printf
	b	.L1
.L45:
	ldr	r0, [r5]
	ldr	r1, .L50+80
	bl	device_printf
	b	.L1
.L46:
	ldr	r0, [r5]
	ldr	r1, .L50+84
	bl	device_printf
	b	.L1
.L47:
	ldr	r0, [r5]
	ldr	r1, .L50+88
	bl	device_printf
	b	.L1
.L49:
	ldr	r0, [r5]
	ldr	r1, .L50+92
	bl	device_printf
	b	.L1
.L48:
	ldr	r0, [r5]
	ldr	r1, .L50+96
	bl	device_printf
	b	.L1
.L51:
	.align	2
.L50:
	.word	TEGRA_POWERGATE_XUSBA
	.word	TEGRA_POWERGATE_XUSBC
	.word	TEGRA_XHCI_SS_HIGH_SPEED
	.word	.LC21
	.word	.LC1
	.word	.LC0
	.word	.LC3
	.word	.LC2
	.word	.LC4
	.word	.LC7
	.word	.LC5
	.word	.LC6
	.word	.LC8
	.word	.LC9
	.word	.LC10
	.word	.LC11
	.word	.LC12
	.word	.LC13
	.word	.LC14
	.word	.LC15
	.word	.LC16
	.word	.LC17
	.word	.LC18
	.word	.LC20
	.word	.LC19
	.size	enable_fdt_resources, .-enable_fdt_resources
	.comm	TEGRA_XHCI_SS_HIGH_SPEED,4,4
	.comm	TEGRA_POWERGATE_XUSBC,4,4
	.comm	TEGRA_POWERGATE_XUSBA,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
