	.file	"extr_clk-stm32h7.c_register_core_and_bus_clocks.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"sys_ck"
.LC1:
	.string	"d1cpre"
.LC2:
	.string	"hclk"
.LC3:
	.string	"systick"
.LC4:
	.string	"pclk3"
.LC5:
	.string	"pclk1"
.LC6:
	.string	"tim1_ker"
.LC7:
	.string	"pclk2"
.LC8:
	.string	"tim2_ker"
.LC9:
	.string	"pclk4"
	.text
	.p2align 4
	.type	register_core_and_bus_clocks, @function
register_core_and_bus_clocks:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	xor	edi, edi
	mov	r9d, 8
	lea	rsi, .LC1[rip]
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	lea	rbx, stm32rcc_lock[rip]
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	mov	rdx, QWORD PTR SYS_D1CPRE[rip]
	mov	rax, QWORD PTR hws[rip]
	mov	ecx, DWORD PTR CLK_IGNORE_UNUSED[rip]
	mov	r8, QWORD PTR RCC_D1CFGR[rip]
	push	rbx
	.cfi_def_cfa_offset 40
	lea	rbp, [rax+rdx*4]
	mov	eax, DWORD PTR d1cpre_div_table[rip]
	add	r8, QWORD PTR base[rip]
	lea	rdx, .LC0[rip]
	push	rax
	.cfi_def_cfa_offset 48
	push	0
	.cfi_def_cfa_offset 56
	push	4
	.cfi_def_cfa_offset 64
	call	clk_hw_register_divider_table@PLT
	add	rsp, 32
	.cfi_def_cfa_offset 32
	xor	r9d, r9d
	xor	edi, edi
	mov	DWORD PTR 0[rbp], eax
	mov	rdx, QWORD PTR HCLK[rip]
	lea	rsi, .LC2[rip]
	mov	rax, QWORD PTR hws[rip]
	mov	ecx, DWORD PTR CLK_IGNORE_UNUSED[rip]
	push	rbx
	.cfi_def_cfa_offset 40
	mov	r8, QWORD PTR RCC_D1CFGR[rip]
	add	r8, QWORD PTR base[rip]
	lea	rbp, [rax+rdx*4]
	mov	eax, DWORD PTR d1cpre_div_table[rip]
	lea	rdx, .LC1[rip]
	push	rax
	.cfi_def_cfa_offset 48
	push	0
	.cfi_def_cfa_offset 56
	push	4
	.cfi_def_cfa_offset 64
	call	clk_hw_register_divider_table@PLT
	mov	rdx, QWORD PTR CPU_SYSTICK[rip]
	xor	ecx, ecx
	xor	edi, edi
	mov	DWORD PTR 0[rbp], eax
	add	rsp, 32
	.cfi_def_cfa_offset 32
	mov	rax, QWORD PTR hws[rip]
	mov	r9d, 8
	mov	r8d, 1
	lea	rsi, .LC3[rip]
	lea	rbp, [rax+rdx*4]
	lea	rdx, .LC1[rip]
	call	clk_hw_register_fixed_factor@PLT
	mov	rdx, QWORD PTR PCLK3[rip]
	xor	ecx, ecx
	xor	edi, edi
	mov	DWORD PTR 0[rbp], eax
	mov	rax, QWORD PTR hws[rip]
	mov	r9d, 4
	lea	rsi, .LC4[rip]
	push	rbx
	.cfi_def_cfa_offset 40
	mov	r8, QWORD PTR RCC_D1CFGR[rip]
	lea	rbp, [rax+rdx*4]
	mov	eax, DWORD PTR ppre_div_table[rip]
	add	r8, QWORD PTR base[rip]
	lea	rdx, .LC2[rip]
	push	rax
	.cfi_def_cfa_offset 48
	push	0
	.cfi_def_cfa_offset 56
	push	3
	.cfi_def_cfa_offset 64
	call	clk_hw_register_divider_table@PLT
	mov	rdx, QWORD PTR PCLK1[rip]
	xor	ecx, ecx
	xor	edi, edi
	mov	DWORD PTR 0[rbp], eax
	add	rsp, 32
	.cfi_def_cfa_offset 32
	mov	rax, QWORD PTR hws[rip]
	mov	r9d, 4
	push	rbx
	.cfi_def_cfa_offset 40
	mov	r8, QWORD PTR RCC_D2CFGR[rip]
	lea	rsi, .LC5[rip]
	lea	rbp, [rax+rdx*4]
	mov	eax, DWORD PTR ppre_div_table[rip]
	add	r8, QWORD PTR base[rip]
	lea	rdx, .LC2[rip]
	push	rax
	.cfi_def_cfa_offset 48
	push	0
	.cfi_def_cfa_offset 56
	push	3
	.cfi_def_cfa_offset 64
	call	clk_hw_register_divider_table@PLT
	add	rsp, 32
	.cfi_def_cfa_offset 32
	mov	r9, rbx
	xor	ecx, ecx
	mov	DWORD PTR 0[rbp], eax
	xor	edi, edi
	mov	r8d, 4
	lea	rdx, .LC5[rip]
	lea	rsi, .LC6[rip]
	call	clk_register_stm32_timer_ker@PLT
	mov	rdx, QWORD PTR PCLK2[rip]
	push	rbx
	.cfi_def_cfa_offset 40
	xor	ecx, ecx
	mov	rax, QWORD PTR hws[rip]
	mov	r8, QWORD PTR RCC_D2CFGR[rip]
	mov	r9d, 8
	xor	edi, edi
	add	r8, QWORD PTR base[rip]
	lea	rsi, .LC7[rip]
	lea	rbp, [rax+rdx*4]
	mov	eax, DWORD PTR ppre_div_table[rip]
	lea	rdx, .LC2[rip]
	push	rax
	.cfi_def_cfa_offset 48
	push	0
	.cfi_def_cfa_offset 56
	push	3
	.cfi_def_cfa_offset 64
	call	clk_hw_register_divider_table@PLT
	add	rsp, 32
	.cfi_def_cfa_offset 32
	mov	r9, rbx
	xor	ecx, ecx
	mov	DWORD PTR 0[rbp], eax
	xor	edi, edi
	mov	r8d, 8
	lea	rdx, .LC7[rip]
	lea	rsi, .LC8[rip]
	call	clk_register_stm32_timer_ker@PLT
	mov	rdx, QWORD PTR PCLK4[rip]
	push	rbx
	.cfi_def_cfa_offset 40
	xor	ecx, ecx
	mov	rax, QWORD PTR hws[rip]
	mov	r8, QWORD PTR RCC_D3CFGR[rip]
	mov	r9d, 4
	xor	edi, edi
	add	r8, QWORD PTR base[rip]
	lea	rsi, .LC9[rip]
	lea	rbp, [rax+rdx*4]
	mov	eax, DWORD PTR ppre_div_table[rip]
	lea	rdx, .LC2[rip]
	push	rax
	.cfi_def_cfa_offset 48
	push	0
	.cfi_def_cfa_offset 56
	push	3
	.cfi_def_cfa_offset 64
	call	clk_hw_register_divider_table@PLT
	mov	DWORD PTR 0[rbp], eax
	add	rsp, 40
	.cfi_def_cfa_offset 24
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE0:
	.size	register_core_and_bus_clocks, .-register_core_and_bus_clocks
	.comm	stm32rcc_lock,4,4
	.comm	ppre_div_table,4,4
	.comm	hws,8,8
	.comm	d1cpre_div_table,4,4
	.comm	base,8,8
	.comm	SYS_D1CPRE,8,8
	.comm	RCC_D3CFGR,8,8
	.comm	RCC_D2CFGR,8,8
	.comm	RCC_D1CFGR,8,8
	.comm	PCLK4,8,8
	.comm	PCLK3,8,8
	.comm	PCLK2,8,8
	.comm	PCLK1,8,8
	.comm	HCLK,8,8
	.comm	CPU_SYSTICK,8,8
	.comm	CLK_IGNORE_UNUSED,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_clk-stm32h7.c_register_core_and_bus_clocks.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"sys_ck\000"
	.align	2
.LC1:
	.ascii	"d1cpre\000"
	.align	2
.LC2:
	.ascii	"hclk\000"
	.align	2
.LC3:
	.ascii	"systick\000"
	.align	2
.LC4:
	.ascii	"pclk3\000"
	.align	2
.LC5:
	.ascii	"pclk1\000"
	.align	2
.LC6:
	.ascii	"tim1_ker\000"
	.align	2
.LC7:
	.ascii	"pclk2\000"
	.align	2
.LC8:
	.ascii	"tim2_ker\000"
	.align	2
.LC9:
	.ascii	"pclk4\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	register_core_and_bus_clocks, %function
register_core_and_bus_clocks:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r5, .L4
	ldr	r6, .L4+4
	ldr	r9, .L4+8
	ldr	r1, [r6]
	ldr	r3, [r5]
	ldr	r2, [r9]
	sub	sp, sp, #36
	add	r3, r3, r1
	str	r3, [sp]
	str	r2, [sp, #16]
	mov	r3, #4
	mov	r2, #8
	mov	r4, #0
	stmib	sp, {r2, r3}
	ldr	fp, .L4+12
	ldr	r8, .L4+16
	str	r4, [sp, #12]
	ldr	ip, .L4+20
	ldr	r7, .L4+24
	ldr	r3, [r8]
	str	fp, [sp, #20]
	ldr	lr, .L4+28
	ldr	ip, [ip]
	mov	r1, r7
	mov	r0, r4
	ldr	r2, .L4+32
	ldr	r10, [lr]
	str	ip, [sp, #28]
	bl	clk_hw_register_divider_table
	ldr	r2, [r5]
	ldr	r1, [r6]
	ldr	ip, [sp, #28]
	add	r2, r2, r1
	mov	r1, #4
	str	r0, [r10, ip, lsl #2]
	ldr	r3, [r9]
	ldr	r9, .L4+36
	str	r3, [sp, #16]
	ldr	r3, [r8]
	stm	sp, {r2, r4}
	ldr	ip, .L4+40
	ldr	lr, .L4+28
	str	r4, [sp, #12]
	str	r1, [sp, #8]
	str	fp, [sp, #20]
	mov	r2, r7
	mov	r1, r9
	mov	r0, r4
	ldr	r8, [lr]
	ldr	r10, [ip]
	bl	clk_hw_register_divider_table
	mov	r1, #1
	str	r0, [r8, r10, lsl #2]
	mov	r0, #8
	ldr	ip, .L4+44
	ldr	lr, .L4+28
	str	r0, [sp, #4]
	str	r1, [sp]
	mov	r2, r7
	mov	r3, r4
	mov	r0, r4
	ldr	r1, .L4+48
	ldr	r8, [lr]
	ldr	r10, [ip]
	bl	clk_hw_register_fixed_factor
	ldr	r1, [r6]
	ldr	r3, [r5]
	str	r0, [r8, r10, lsl #2]
	add	r3, r3, r1
	mov	r8, #3
	mov	r1, #4
	ldr	r7, .L4+52
	ldr	ip, .L4+56
	ldr	r2, [r7]
	ldr	lr, .L4+28
	str	r4, [sp, #12]
	str	r1, [sp, #4]
	str	r3, [sp]
	str	r2, [sp, #16]
	str	fp, [sp, #20]
	str	r8, [sp, #8]
	mov	r3, r4
	mov	r2, r9
	mov	r0, r4
	ldr	r1, .L4+60
	ldr	r8, [lr]
	ldr	r10, [ip]
	bl	clk_hw_register_divider_table
	ldr	r6, .L4+64
	str	r0, [r8, r10, lsl #2]
	ldr	r3, [r5]
	ldr	r0, [r6]
	mov	r8, #3
	add	r3, r3, r0
	mov	r0, #4
	ldr	r2, [r7]
	stmib	sp, {r0, r8}
	ldr	ip, .L4+68
	ldr	lr, .L4+28
	str	r4, [sp, #12]
	str	r2, [sp, #16]
	str	r3, [sp]
	str	fp, [sp, #20]
	mov	r3, r4
	mov	r2, r9
	mov	r0, r4
	ldr	r1, .L4+72
	ldr	r8, [lr]
	ldr	r10, [ip]
	bl	clk_hw_register_divider_table
	str	r0, [r8, r10, lsl #2]
	mov	r0, #4
	ldr	r1, .L4+72
	mov	r3, r4
	mov	r2, r1
	str	r0, [sp]
	ldr	r1, .L4+76
	mov	r0, r4
	str	fp, [sp, #4]
	bl	clk_register_stm32_timer_ker
	mov	r8, #3
	ldr	r1, [r6]
	mov	r6, #8
	ldr	r3, [r5]
	ldr	r2, [r7]
	ldr	r10, .L4+80
	stmib	sp, {r6, r8}
	ldr	ip, .L4+84
	ldr	lr, .L4+28
	add	r3, r3, r1
	str	r4, [sp, #12]
	str	r3, [sp]
	str	r2, [sp, #16]
	str	fp, [sp, #20]
	mov	r3, r4
	mov	r2, r9
	mov	r1, r10
	mov	r0, r4
	ldr	r6, [lr]
	ldr	r8, [ip]
	bl	clk_hw_register_divider_table
	str	r0, [r6, r8, lsl #2]
	mov	r6, #8
	mov	r2, r10
	mov	r3, r4
	mov	r0, r4
	ldr	r1, .L4+88
	str	fp, [sp, #4]
	str	r6, [sp]
	bl	clk_register_stm32_timer_ker
	mov	r8, #3
	mov	r0, #4
	ldr	r2, .L4+92
	ldr	r3, [r5]
	ldr	r1, [r2]
	ldr	r2, [r7]
	stmib	sp, {r0, r8}
	ldr	ip, .L4+96
	ldr	lr, .L4+28
	add	r3, r3, r1
	str	r2, [sp, #16]
	str	r3, [sp]
	str	fp, [sp, #20]
	str	r4, [sp, #12]
	mov	r3, r4
	mov	r2, r9
	mov	r0, r4
	ldr	r1, .L4+100
	ldr	r4, [lr]
	ldr	r5, [ip]
	bl	clk_hw_register_divider_table
	str	r0, [r4, r5, lsl #2]
	add	sp, sp, #36
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L5:
	.align	2
.L4:
	.word	base
	.word	RCC_D1CFGR
	.word	d1cpre_div_table
	.word	stm32rcc_lock
	.word	CLK_IGNORE_UNUSED
	.word	SYS_D1CPRE
	.word	.LC1
	.word	hws
	.word	.LC0
	.word	.LC2
	.word	HCLK
	.word	CPU_SYSTICK
	.word	.LC3
	.word	ppre_div_table
	.word	PCLK3
	.word	.LC4
	.word	RCC_D2CFGR
	.word	PCLK1
	.word	.LC5
	.word	.LC6
	.word	.LC7
	.word	PCLK2
	.word	.LC8
	.word	RCC_D3CFGR
	.word	PCLK4
	.word	.LC9
	.size	register_core_and_bus_clocks, .-register_core_and_bus_clocks
	.comm	stm32rcc_lock,4,4
	.comm	ppre_div_table,4,4
	.comm	hws,4,4
	.comm	d1cpre_div_table,4,4
	.comm	base,4,4
	.comm	SYS_D1CPRE,4,4
	.comm	RCC_D3CFGR,4,4
	.comm	RCC_D2CFGR,4,4
	.comm	RCC_D1CFGR,4,4
	.comm	PCLK4,4,4
	.comm	PCLK3,4,4
	.comm	PCLK2,4,4
	.comm	PCLK1,4,4
	.comm	HCLK,4,4
	.comm	CPU_SYSTICK,4,4
	.comm	CLK_IGNORE_UNUSED,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
