	.file	"extr_gpio-tegra.c_tegra_gpio_irq_set_type.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC0:
	.string	"unable to lock Tegra GPIO %u as IRQ\n"
	.text
	.p2align 4
	.type	tegra_gpio_irq_set_type, @function
tegra_gpio_irq_set_type:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	mov	r14d, esi
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	mov	r13, rdi
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 40
	.cfi_def_cfa_offset 96
	mov	ebp, DWORD PTR [rdi]
	mov	edi, ebp
	call	GPIO_PORT@PLT
	mov	rdi, r13
	mov	ebx, eax
	call	irq_data_get_irq_chip_data@PLT
	mov	r12, QWORD PTR 8[rax]
	mov	r9, rax
	mov	eax, DWORD PTR IRQ_TYPE_SENSE_MASK[rip]
	and	eax, r14d
	add	eax, -128
	cmp	eax, 4
	ja	.L2
	lea	rdx, .L4[rip]
	movsx	rax, DWORD PTR [rdx+rax*4]
	add	rax, rdx
	notrack jmp	rax
	.section	.rodata
	.align 4
	.align 4
.L4:
	.long	.L8-.L4
	.long	.L7-.L4
	.long	.L6-.L4
	.long	.L5-.L4
	.long	.L3-.L4
	.text
	.p2align 4,,10
	.p2align 3
.L5:
	mov	eax, DWORD PTR GPIO_INT_LVL_EDGE_FALLING[rip]
	mov	DWORD PTR 28[rsp], eax
.L9:
	mov	r8d, ebx
	xor	r10d, r10d
	mov	QWORD PTR 8[rsp], r9
	sal	r8, 2
	mov	rsi, r10
	mov	rdi, r8
	add	rdi, QWORD PTR [r9]
	mov	QWORD PTR 16[rsp], r8
	call	spin_lock_irqsave@PLT
	mov	esi, ebp
	mov	rdi, r12
	call	GPIO_INT_LVL@PLT
	mov	rdi, r12
	mov	esi, eax
	call	tegra_gpio_readl@PLT
	mov	edi, ebp
	mov	ebx, DWORD PTR GPIO_INT_LVL_MASK[rip]
	mov	r15d, eax
	call	GPIO_BIT@PLT
	mov	edi, ebp
	mov	ecx, eax
	sal	ebx, cl
	call	GPIO_BIT@PLT
	not	ebx
	mov	esi, ebp
	mov	rdi, r12
	and	r15d, ebx
	mov	ebx, DWORD PTR 28[rsp]
	mov	ecx, eax
	sal	ebx, cl
	call	GPIO_INT_LVL@PLT
	or	r15d, ebx
	mov	rdi, r12
	mov	edx, eax
	mov	esi, r15d
	call	tegra_gpio_writel@PLT
	mov	r8, QWORD PTR 16[rsp]
	mov	r9, QWORD PTR 8[rsp]
	xor	r10d, r10d
	mov	rsi, r10
	mov	rdi, r8
	add	rdi, QWORD PTR [r9]
	call	spin_unlock_irqrestore@PLT
	mov	esi, ebp
	mov	rdi, r12
	call	GPIO_MSK_OE@PLT
	xor	ecx, ecx
	mov	edx, ebp
	mov	rdi, r12
	mov	esi, eax
	call	tegra_gpio_mask_write@PLT
	mov	esi, ebp
	mov	rdi, r12
	call	tegra_gpio_enable@PLT
	lea	rdi, 4[r12]
	mov	esi, ebp
	call	gpiochip_lock_as_irq@PLT
	mov	r15d, eax
	test	eax, eax
	jne	.L18
	test	r14b, -127
	jne	.L19
	and	r14d, 131
	jne	.L20
.L1:
	add	rsp, 40
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	eax, r15d
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L3:
	.cfi_restore_state
	mov	eax, DWORD PTR GPIO_INT_LVL_EDGE_BOTH[rip]
	mov	DWORD PTR 28[rsp], eax
	jmp	.L9
	.p2align 4,,10
	.p2align 3
.L7:
	mov	eax, DWORD PTR GPIO_INT_LVL_LEVEL_HIGH[rip]
	mov	DWORD PTR 28[rsp], eax
	jmp	.L9
	.p2align 4,,10
	.p2align 3
.L6:
	mov	eax, DWORD PTR GPIO_INT_LVL_EDGE_RISING[rip]
	mov	DWORD PTR 28[rsp], eax
	jmp	.L9
	.p2align 4,,10
	.p2align 3
.L8:
	mov	eax, DWORD PTR GPIO_INT_LVL_LEVEL_LOW[rip]
	mov	DWORD PTR 28[rsp], eax
	jmp	.L9
	.p2align 4,,10
	.p2align 3
.L19:
	mov	esi, DWORD PTR handle_level_irq[rip]
	mov	rdi, r13
	call	irq_set_handler_locked@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L18:
	mov	edi, DWORD PTR [r12]
	mov	edx, ebp
	lea	rsi, .LC0[rip]
	call	dev_err@PLT
	mov	esi, ebp
	mov	rdi, r12
	call	tegra_gpio_disable@PLT
	jmp	.L1
.L2:
	mov	r15d, DWORD PTR EINVAL[rip]
	neg	r15d
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L20:
	mov	esi, DWORD PTR handle_edge_irq[rip]
	mov	rdi, r13
	call	irq_set_handler_locked@PLT
	jmp	.L1
	.cfi_endproc
.LFE0:
	.size	tegra_gpio_irq_set_type, .-tegra_gpio_irq_set_type
	.comm	handle_level_irq,4,4
	.comm	handle_edge_irq,4,4
	.comm	IRQ_TYPE_SENSE_MASK,4,4
	.comm	GPIO_INT_LVL_MASK,4,4
	.comm	GPIO_INT_LVL_LEVEL_LOW,4,4
	.comm	GPIO_INT_LVL_LEVEL_HIGH,4,4
	.comm	GPIO_INT_LVL_EDGE_RISING,4,4
	.comm	GPIO_INT_LVL_EDGE_FALLING,4,4
	.comm	GPIO_INT_LVL_EDGE_BOTH,4,4
	.comm	EINVAL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_gpio-tegra.c_tegra_gpio_irq_set_type.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"unable to lock Tegra GPIO %u as IRQ\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	tegra_gpio_irq_set_type, %function
tegra_gpio_irq_set_type:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r4, [r0]
	mov	r7, r0
	sub	sp, sp, #12
	mov	r0, r4
	mov	r8, r1
	bl	GPIO_PORT
	mov	r6, r0
	mov	r0, r7
	bl	irq_data_get_irq_chip_data
	ldr	r3, .L21
	mov	r9, r0
	ldr	r3, [r3]
	ldr	r5, [r0, #4]
	and	r3, r3, r8
	sub	r3, r3, #128
	cmp	r3, #4
	ldrls	pc, [pc, r3, asl #2]
	b	.L2
.L4:
	.word	.L8
	.word	.L7
	.word	.L6
	.word	.L5
	.word	.L3
.L3:
	ldr	r3, .L21+4
	ldr	r10, [r3]
.L9:
	mov	fp, #0
	ldr	r0, [r9]
	mov	r1, fp
	add	r0, r0, r6, lsl #2
	bl	spin_lock_irqsave
	mov	r1, r4
	mov	r0, r5
	bl	GPIO_INT_LVL
	mov	r1, r0
	mov	r0, r5
	bl	tegra_gpio_readl
	mov	r3, r0
	ldr	r2, .L21+8
	mov	r0, r4
	ldr	r1, [r2]
	str	r3, [sp, #4]
	str	r1, [sp]
	bl	GPIO_BIT
	ldm	sp, {r1, r3}
	mov	r2, r0
	mov	r0, r4
	bic	r3, r3, r1, lsl r2
	str	r3, [sp]
	bl	GPIO_BIT
	ldr	r3, [sp]
	mov	r1, r4
	orr	r10, r3, r10, lsl r0
	mov	r0, r5
	bl	GPIO_INT_LVL
	mov	r1, r10
	mov	r2, r0
	mov	r0, r5
	bl	tegra_gpio_writel
	ldr	r0, [r9]
	lsl	r6, r6, #2
	mov	r1, fp
	add	r0, r0, r6
	bl	spin_unlock_irqrestore
	mov	r1, r4
	mov	r0, r5
	bl	GPIO_MSK_OE
	mov	r3, fp
	mov	r1, r0
	mov	r2, r4
	mov	r0, r5
	bl	tegra_gpio_mask_write
	mov	r1, r4
	mov	r0, r5
	bl	tegra_gpio_enable
	mov	r1, r4
	add	r0, r5, #4
	bl	gpiochip_lock_as_irq
	subs	r6, r0, #0
	bne	.L18
	tst	r8, #129
	bne	.L19
	tst	r8, #131
	bne	.L20
.L1:
	mov	r0, r6
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L8:
	ldr	r3, .L21+12
	ldr	r10, [r3]
	b	.L9
.L6:
	ldr	r3, .L21+16
	ldr	r10, [r3]
	b	.L9
.L5:
	ldr	r3, .L21+20
	ldr	r10, [r3]
	b	.L9
.L7:
	ldr	r3, .L21+24
	ldr	r10, [r3]
	b	.L9
.L19:
	ldr	r3, .L21+28
	mov	r0, r7
	ldr	r1, [r3]
	bl	irq_set_handler_locked
	mov	r0, r6
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L18:
	mov	r2, r4
	ldr	r1, .L21+32
	ldr	r0, [r5]
	bl	dev_err
	mov	r1, r4
	mov	r0, r5
	bl	tegra_gpio_disable
	mov	r0, r6
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L20:
	ldr	r3, .L21+36
	mov	r0, r7
	ldr	r1, [r3]
	bl	irq_set_handler_locked
	mov	r0, r6
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L2:
	ldr	r3, .L21+40
	ldr	r0, [r3]
	rsb	r6, r0, #0
	b	.L1
.L22:
	.align	2
.L21:
	.word	IRQ_TYPE_SENSE_MASK
	.word	GPIO_INT_LVL_EDGE_BOTH
	.word	GPIO_INT_LVL_MASK
	.word	GPIO_INT_LVL_LEVEL_LOW
	.word	GPIO_INT_LVL_EDGE_RISING
	.word	GPIO_INT_LVL_EDGE_FALLING
	.word	GPIO_INT_LVL_LEVEL_HIGH
	.word	handle_level_irq
	.word	.LC0
	.word	handle_edge_irq
	.word	EINVAL
	.size	tegra_gpio_irq_set_type, .-tegra_gpio_irq_set_type
	.comm	handle_level_irq,4,4
	.comm	handle_edge_irq,4,4
	.comm	IRQ_TYPE_SENSE_MASK,4,4
	.comm	GPIO_INT_LVL_MASK,4,4
	.comm	GPIO_INT_LVL_LEVEL_LOW,4,4
	.comm	GPIO_INT_LVL_LEVEL_HIGH,4,4
	.comm	GPIO_INT_LVL_EDGE_RISING,4,4
	.comm	GPIO_INT_LVL_EDGE_FALLING,4,4
	.comm	GPIO_INT_LVL_EDGE_BOTH,4,4
	.comm	EINVAL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
