	.file	"extr_ar71xx_serial.c_ar71xx_sys_frequency.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	ar71xx_sys_frequency
	.type	ar71xx_sys_frequency, @function
ar71xx_sys_frequency:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	mov	r12, rdi
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	mov	rbp, rsi
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	mov	rbx, rdx
	sub	rsp, 8
	.cfi_def_cfa_offset 48
	mov	rdi, QWORD PTR AR71XX_PLL_BASE[rip]
	add	rdi, QWORD PTR AR71XX_PLL_REG_CPU_CONFIG[rip]
	call	KSEG1ADDR@PLT
	mov	edi, eax
	call	readl@PLT
	mov	r11d, DWORD PTR AR71XX_CPU_DIV_MASK[rip]
	mov	ecx, DWORD PTR AR71XX_CPU_DIV_SHIFT[rip]
	mov	edi, DWORD PTR AR71XX_PLL_DIV_MASK[rip]
	mov	r8d, DWORD PTR AR71XX_DDR_DIV_MASK[rip]
	mov	r9d, eax
	and	r11d, eax
	mov	r13d, DWORD PTR AR71XX_DDR_DIV_SHIFT[rip]
	mov	esi, DWORD PTR AR71XX_AHB_DIV_MASK[rip]
	sar	r11d, cl
	mov	ecx, DWORD PTR AR71XX_PLL_DIV_SHIFT[rip]
	and	edi, eax
	mov	r10d, DWORD PTR AR71XX_AHB_DIV_SHIFT[rip]
	add	r11d, 1
	sar	edi, cl
	add	edi, 1
	imul	edi, edi, 40000000
	test	r12, r12
	je	.L2
	mov	eax, edi
	cdq
	idiv	r11d
	mov	DWORD PTR [r12], eax
.L2:
	test	rbp, rbp
	je	.L3
	mov	ecx, r13d
	and	r8d, r9d
	mov	eax, edi
	sar	r8d, cl
	cdq
	lea	ecx, 1[r8]
	idiv	ecx
	mov	DWORD PTR 0[rbp], eax
.L3:
	test	rbx, rbx
	je	.L1
	mov	eax, edi
	mov	ecx, r10d
	and	r9d, esi
	cdq
	sar	r9d, cl
	idiv	r11d
	lea	ecx, 2[r9+r9]
	cdq
	idiv	ecx
	mov	DWORD PTR [rbx], eax
.L1:
	add	rsp, 8
	.cfi_def_cfa_offset 40
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE0:
	.size	ar71xx_sys_frequency, .-ar71xx_sys_frequency
	.comm	AR91XX_PLL_REG_CPU_CONFIG,8,8
	.comm	AR91XX_PLL_DIV_SHIFT,4,4
	.comm	AR91XX_PLL_DIV_MASK,4,4
	.comm	AR91XX_DDR_DIV_SHIFT,4,4
	.comm	AR91XX_DDR_DIV_MASK,4,4
	.comm	AR91XX_AHB_DIV_SHIFT,4,4
	.comm	AR91XX_AHB_DIV_MASK,4,4
	.comm	AR71XX_PLL_REG_CPU_CONFIG,8,8
	.comm	AR71XX_PLL_DIV_SHIFT,4,4
	.comm	AR71XX_PLL_DIV_MASK,4,4
	.comm	AR71XX_PLL_BASE,8,8
	.comm	AR71XX_DDR_DIV_SHIFT,4,4
	.comm	AR71XX_DDR_DIV_MASK,4,4
	.comm	AR71XX_CPU_DIV_SHIFT,4,4
	.comm	AR71XX_CPU_DIV_MASK,4,4
	.comm	AR71XX_AHB_DIV_SHIFT,4,4
	.comm	AR71XX_AHB_DIV_MASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_ar71xx_serial.c_ar71xx_sys_frequency.c"
	.text
	.global	__aeabi_idiv
	.align	2
	.global	ar71xx_sys_frequency
	.syntax unified
	.arm
	.fpu softvfp
	.type	ar71xx_sys_frequency, %function
ar71xx_sys_frequency:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	ip, .L16
	ldr	r3, .L16+4
	ldr	ip, [ip]
	ldr	r3, [r3]
	mov	r7, r0
	sub	sp, sp, #12
	add	r0, ip, r3
	mov	r6, r1
	mov	r5, r2
	bl	KSEG1ADDR
	bl	readl
	ldr	r3, .L16+8
	ldr	r2, .L16+12
	ldr	r3, [r3]
	ldr	r2, [r2]
	and	r3, r3, r0
	ldr	r1, .L16+16
	asr	r3, r3, r2
	add	r3, r3, #1
	ldr	r2, .L16+20
	ldr	r9, [r1]
	rsb	r4, r3, r3, lsl #5
	ldr	lr, [r2]
	rsb	r4, r4, r4, lsl #6
	add	r3, r3, r4, lsl #3
	and	r9, r9, r0
	mov	r8, r0
	ldr	ip, .L16+24
	ldr	r2, .L16+28
	ldr	r0, .L16+32
	ldr	r1, .L16+36
	add	r3, r3, r3, lsl #2
	asr	r9, r9, lr
	cmp	r7, #0
	lsl	r4, r3, #9
	ldr	r2, [r2]
	ldr	r3, [ip]
	ldr	r10, [r0]
	ldr	fp, [r1]
	add	r9, r9, #1
	beq	.L2
	mov	r1, r9
	mov	r0, r4
	str	r2, [sp, #4]
	str	r3, [sp]
	bl	__aeabi_idiv
	ldr	r2, [sp, #4]
	ldr	r3, [sp]
	str	r0, [r7]
.L2:
	cmp	r6, #0
	beq	.L3
	and	r1, r3, r8
	asr	r1, r1, r2
	mov	r0, r4
	add	r1, r1, #1
	bl	__aeabi_idiv
	str	r0, [r6]
.L3:
	cmp	r5, #0
	beq	.L1
	mov	r1, r9
	mov	r0, r4
	bl	__aeabi_idiv
	and	r1, r10, r8
	asr	r1, r1, fp
	add	r1, r1, #1
	lsl	r1, r1, #1
	bl	__aeabi_idiv
	str	r0, [r5]
.L1:
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L17:
	.align	2
.L16:
	.word	AR71XX_PLL_REG_CPU_CONFIG
	.word	AR71XX_PLL_BASE
	.word	AR71XX_PLL_DIV_MASK
	.word	AR71XX_PLL_DIV_SHIFT
	.word	AR71XX_CPU_DIV_MASK
	.word	AR71XX_CPU_DIV_SHIFT
	.word	AR71XX_DDR_DIV_MASK
	.word	AR71XX_DDR_DIV_SHIFT
	.word	AR71XX_AHB_DIV_MASK
	.word	AR71XX_AHB_DIV_SHIFT
	.size	ar71xx_sys_frequency, .-ar71xx_sys_frequency
	.comm	AR91XX_PLL_REG_CPU_CONFIG,4,4
	.comm	AR91XX_PLL_DIV_SHIFT,4,4
	.comm	AR91XX_PLL_DIV_MASK,4,4
	.comm	AR91XX_DDR_DIV_SHIFT,4,4
	.comm	AR91XX_DDR_DIV_MASK,4,4
	.comm	AR91XX_AHB_DIV_SHIFT,4,4
	.comm	AR91XX_AHB_DIV_MASK,4,4
	.comm	AR71XX_PLL_REG_CPU_CONFIG,4,4
	.comm	AR71XX_PLL_DIV_SHIFT,4,4
	.comm	AR71XX_PLL_DIV_MASK,4,4
	.comm	AR71XX_PLL_BASE,4,4
	.comm	AR71XX_DDR_DIV_SHIFT,4,4
	.comm	AR71XX_DDR_DIV_MASK,4,4
	.comm	AR71XX_CPU_DIV_SHIFT,4,4
	.comm	AR71XX_CPU_DIV_MASK,4,4
	.comm	AR71XX_AHB_DIV_SHIFT,4,4
	.comm	AR71XX_AHB_DIV_MASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
