	.file	"extr_intel.c_intel_ppin_init.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	intel_ppin_init, @function
intel_ppin_init:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	push	rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	sub	rsp, 24
	.cfi_def_cfa_offset 48
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 8[rsp], rax
	xor	eax, eax
	mov	eax, DWORD PTR [rdi]
	add	eax, -128
	cmp	eax, 6
	jbe	.L14
.L1:
	mov	rax, QWORD PTR 8[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L15
	add	rsp, 24
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L14:
	.cfi_restore_state
	mov	rbp, rdi
	mov	r12, rsp
	mov	edi, DWORD PTR MSR_PPIN_CTL[rip]
	mov	rsi, r12
	call	rdmsrl_safe@PLT
	test	eax, eax
	jne	.L1
	mov	rsi, QWORD PTR [rsp]
	mov	rax, rsi
	and	eax, 3
	cmp	rax, 1
	je	.L1
	test	rax, rax
	je	.L16
.L5:
	cmp	rax, 2
	jne	.L1
	mov	esi, DWORD PTR X86_FEATURE_INTEL_PPIN[rip]
	mov	rdi, rbp
	call	set_cpu_cap@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L16:
	mov	edi, DWORD PTR MSR_PPIN_CTL[rip]
	or	rsi, 2
	call	wrmsrl_safe@PLT
	mov	edi, DWORD PTR MSR_PPIN_CTL[rip]
	mov	rsi, r12
	call	rdmsrl_safe@PLT
	mov	rax, QWORD PTR [rsp]
	and	eax, 3
	jmp	.L5
.L15:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	intel_ppin_init, .-intel_ppin_init
	.comm	X86_FEATURE_INTEL_PPIN,4,4
	.comm	MSR_PPIN_CTL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_intel.c_intel_ppin_init.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	intel_ppin_init, %function
intel_ppin_init:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	ldr	r3, [r0]
	ldr	r2, .L17
	sub	r3, r3, #128
	sub	sp, sp, #16
	cmp	r3, #6
	ldr	r2, [r2]
	str	r2, [sp, #12]
	mov	r2,#0
	bls	.L14
.L1:
	ldr	r3, .L17
	ldr	r2, [r3]
	ldr	r3, [sp, #12]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L15
	add	sp, sp, #16
	@ sp needed
	pop	{r4, r5, r6, r7, r8, pc}
.L14:
	ldr	r8, .L17+4
	mov	r4, r0
	mov	r1, sp
	ldr	r0, [r8]
	bl	rdmsrl_safe
	subs	r5, r0, #0
	bne	.L1
	ldm	sp, {r2, r3}
	cmp	r5, #0
	and	r6, r2, #3
	cmpeq	r6, #1
	mov	r7, r5
	beq	.L1
	orrs	r1, r6, r7
	beq	.L16
.L5:
	cmp	r7, #0
	cmpeq	r6, #2
	bne	.L1
	ldr	r3, .L17+8
	mov	r0, r4
	ldr	r1, [r3]
	bl	set_cpu_cap
	b	.L1
.L16:
	orr	r2, r2, #2
	ldr	r0, [r8]
	bl	wrmsrl_safe
	mov	r1, sp
	ldr	r0, [r8]
	bl	rdmsrl_safe
	ldr	r3, [sp]
	and	r6, r3, #3
	b	.L5
.L15:
	bl	__stack_chk_fail
.L18:
	.align	2
.L17:
	.word	.LC0
	.word	MSR_PPIN_CTL
	.word	X86_FEATURE_INTEL_PPIN
	.size	intel_ppin_init, .-intel_ppin_init
	.comm	X86_FEATURE_INTEL_PPIN,4,4
	.comm	MSR_PPIN_CTL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
