	.file	"extr_ecp_nistp521.c_felem_reduce.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	felem_reduce, @function
felem_reduce:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	mov	ecx, 58
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	r9d, DWORD PTR [rsi]
	and	r9d, DWORD PTR bottom58bits[rip]
	mov	DWORD PTR [rdi], r9d
	mov	r8d, DWORD PTR 4[rsi]
	mov	edx, DWORD PTR bottom58bits[rip]
	and	r8d, edx
	mov	DWORD PTR 4[rdi], r8d
	mov	r11d, DWORD PTR 8[rsi]
	and	r11d, edx
	mov	DWORD PTR 8[rdi], r11d
	mov	r14d, DWORD PTR 12[rsi]
	and	r14d, edx
	mov	DWORD PTR 12[rdi], r14d
	mov	r13d, DWORD PTR 16[rsi]
	and	r13d, edx
	mov	DWORD PTR 16[rdi], r13d
	mov	r12d, DWORD PTR 20[rsi]
	and	r12d, edx
	mov	DWORD PTR 20[rdi], r12d
	mov	ebp, DWORD PTR 24[rsi]
	and	ebp, edx
	mov	DWORD PTR 24[rdi], ebp
	mov	ebx, DWORD PTR 28[rsi]
	and	ebx, edx
	mov	DWORD PTR 28[rdi], ebx
	and	edx, DWORD PTR 32[rsi]
	mov	DWORD PTR 32[rdi], edx
	mov	eax, DWORD PTR [rsi]
	sar	eax, cl
	mov	ecx, 64
	add	r8d, eax
	mov	eax, DWORD PTR bottom52bits[rip]
	mov	DWORD PTR 4[rdi], r8d
	mov	r10d, DWORD PTR [rsi]
	sar	r10d, cl
	mov	ecx, r10d
	and	ecx, eax
	sal	ecx, 6
	lea	r15d, [rcx+r8]
	mov	ecx, 64
	mov	DWORD PTR 4[rdi], r15d
	mov	r8d, DWORD PTR [rsi]
	sar	r8d, cl
	mov	ecx, 52
	sar	r8d, cl
	mov	ecx, 58
	add	r8d, r11d
	mov	DWORD PTR 8[rdi], r8d
	mov	r11d, DWORD PTR 4[rsi]
	sar	r11d, cl
	mov	ecx, 64
	add	r8d, r11d
	mov	DWORD PTR 8[rdi], r8d
	mov	r11d, DWORD PTR 4[rsi]
	sar	r11d, cl
	and	r11d, eax
	sal	r11d, 6
	add	r11d, r8d
	mov	DWORD PTR 8[rdi], r11d
	mov	r8d, DWORD PTR 4[rsi]
	sar	r8d, cl
	mov	ecx, 52
	sar	r8d, cl
	mov	ecx, 58
	add	r8d, r14d
	mov	DWORD PTR 12[rdi], r8d
	mov	r10d, DWORD PTR 8[rsi]
	sar	r10d, cl
	mov	ecx, 64
	add	r8d, r10d
	mov	DWORD PTR 12[rdi], r8d
	mov	r10d, DWORD PTR 8[rsi]
	sar	r10d, cl
	and	r10d, eax
	sal	r10d, 6
	add	r10d, r8d
	mov	DWORD PTR 12[rdi], r10d
	mov	r8d, DWORD PTR 8[rsi]
	sar	r8d, cl
	mov	ecx, 52
	sar	r8d, cl
	mov	ecx, 58
	add	r13d, r8d
	mov	DWORD PTR 16[rdi], r13d
	mov	r8d, DWORD PTR 12[rsi]
	sar	r8d, cl
	mov	ecx, 64
	add	r13d, r8d
	mov	DWORD PTR 16[rdi], r13d
	mov	r8d, DWORD PTR 12[rsi]
	sar	r8d, cl
	and	r8d, eax
	sal	r8d, 6
	add	r8d, r13d
	mov	DWORD PTR 16[rdi], r8d
	mov	r11d, DWORD PTR 12[rsi]
	sar	r11d, cl
	mov	ecx, 52
	sar	r11d, cl
	mov	ecx, 58
	add	r12d, r11d
	mov	DWORD PTR 20[rdi], r12d
	mov	r11d, DWORD PTR 16[rsi]
	sar	r11d, cl
	mov	ecx, 64
	add	r12d, r11d
	mov	DWORD PTR 20[rdi], r12d
	mov	r11d, DWORD PTR 16[rsi]
	sar	r11d, cl
	and	r11d, eax
	sal	r11d, 6
	add	r11d, r12d
	mov	DWORD PTR 20[rdi], r11d
	mov	r10d, DWORD PTR 16[rsi]
	sar	r10d, cl
	mov	ecx, 52
	sar	r10d, cl
	mov	ecx, 58
	add	ebp, r10d
	mov	DWORD PTR 24[rdi], ebp
	mov	r10d, DWORD PTR 20[rsi]
	sar	r10d, cl
	mov	ecx, 64
	add	ebp, r10d
	mov	DWORD PTR 24[rdi], ebp
	mov	r10d, DWORD PTR 20[rsi]
	sar	r10d, cl
	and	r10d, eax
	sal	r10d, 6
	add	r10d, ebp
	mov	DWORD PTR 24[rdi], r10d
	mov	r8d, DWORD PTR 20[rsi]
	sar	r8d, cl
	mov	ecx, 52
	sar	r8d, cl
	mov	ecx, 58
	add	ebx, r8d
	mov	DWORD PTR 28[rdi], ebx
	mov	r8d, DWORD PTR 24[rsi]
	sar	r8d, cl
	mov	ecx, 64
	add	ebx, r8d
	mov	DWORD PTR 28[rdi], ebx
	mov	r8d, DWORD PTR 24[rsi]
	sar	r8d, cl
	and	r8d, eax
	sal	r8d, 6
	add	r8d, ebx
	mov	DWORD PTR 28[rdi], r8d
	mov	r8d, DWORD PTR 24[rsi]
	sar	r8d, cl
	mov	ecx, 52
	sar	r8d, cl
	mov	ecx, 58
	add	edx, r8d
	mov	DWORD PTR 32[rdi], edx
	mov	r8d, DWORD PTR 28[rsi]
	sar	r8d, cl
	mov	ecx, 64
	add	r8d, edx
	mov	DWORD PTR 32[rdi], r8d
	mov	edx, DWORD PTR 28[rsi]
	sar	edx, cl
	and	edx, eax
	sal	edx, 6
	add	edx, r8d
	mov	DWORD PTR 32[rdi], edx
	mov	r8d, DWORD PTR 28[rsi]
	mov	edx, DWORD PTR 32[rsi]
	sar	r8d, cl
	mov	ecx, 52
	sar	r8d, cl
	mov	esi, edx
	mov	ecx, 58
	sar	esi, cl
	mov	ecx, 64
	sar	edx, cl
	add	r8d, esi
	mov	ecx, 52
	and	eax, edx
	sar	edx, cl
	mov	ecx, 58
	sal	eax, 6
	lea	edx, [r15+rdx*2]
	add	eax, r8d
	lea	eax, [r9+rax*2]
	mov	ebx, eax
	mov	DWORD PTR [rdi], eax
	and	eax, DWORD PTR bottom58bits[rip]
	sar	ebx, cl
	mov	DWORD PTR [rdi], eax
	add	edx, ebx
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	mov	DWORD PTR 4[rdi], edx
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE0:
	.size	felem_reduce, .-felem_reduce
	.comm	bottom58bits,4,4
	.comm	bottom52bits,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_ecp_nistp521.c_felem_reduce.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	felem_reduce, %function
felem_reduce:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r10, .L4
	ldr	r5, [r1]
	ldr	r3, [r10]
	sub	sp, sp, #20
	and	r3, r5, r3
	str	r3, [r0]
	ldr	ip, [r10]
	str	r3, [sp, #4]
	ldr	r3, [r1, #4]
	mov	r6, #58
	and	r3, r3, ip
	str	r3, [r0, #4]
	ldr	fp, [r1, #8]
	mov	lr, #64
	and	fp, fp, ip
	str	fp, [r0, #8]
	ldr	r9, [r1, #12]
	mov	r7, #52
	and	r9, r9, ip
	str	r9, [r0, #12]
	ldr	r8, [r1, #16]
	ldr	r2, .L4+4
	and	r8, r8, ip
	str	r8, [r0, #16]
	ldr	r5, [r2]
	ldr	r2, [r1, #20]
	and	r4, ip, r2
	str	r4, [r0, #20]
	ldr	r2, [r1, #24]
	str	r4, [sp, #8]
	and	r2, ip, r2
	str	r2, [r0, #24]
	ldr	r4, [r1, #28]
	str	r2, [sp, #12]
	and	r4, r4, ip
	str	r4, [r0, #28]
	ldr	r2, [r1, #32]
	and	ip, ip, r2
	str	ip, [r0, #32]
	ldr	r2, [r1]
	add	r3, r3, r2, asr r6
	str	r3, [r0, #4]
	ldr	r2, [r1]
	and	r2, r5, r2, asr lr
	add	r3, r3, r2, lsl #6
	str	r3, [r0, #4]
	ldr	r2, [r1]
	asr	r2, r2, lr
	add	r2, fp, r2, asr r7
	str	r2, [r0, #8]
	ldr	fp, [r1, #4]
	add	r2, r2, fp, asr r6
	str	r2, [r0, #8]
	ldr	fp, [r1, #4]
	and	fp, r5, fp, asr lr
	add	r2, r2, fp, lsl #6
	str	r2, [r0, #8]
	ldr	r2, [r1, #4]
	asr	r2, r2, lr
	add	r9, r9, r2, asr r7
	str	r9, [r0, #12]
	ldr	r2, [r1, #8]
	add	r9, r9, r2, asr r6
	str	r9, [r0, #12]
	ldr	r2, [r1, #8]
	and	r2, r5, r2, asr lr
	add	r9, r9, r2, lsl #6
	str	r9, [r0, #12]
	ldr	r2, [r1, #8]
	asr	r2, r2, lr
	add	r8, r8, r2, asr r7
	str	r8, [r0, #16]
	ldr	r2, [r1, #12]
	add	r8, r8, r2, asr r6
	str	r8, [r0, #16]
	ldr	r2, [r1, #12]
	and	r2, r5, r2, asr lr
	add	r8, r8, r2, lsl #6
	str	r8, [r0, #16]
	ldr	r2, [r1, #12]
	ldr	r8, [sp, #8]
	asr	r2, r2, lr
	add	r2, r8, r2, asr r7
	str	r2, [r0, #20]
	ldr	r8, [r1, #16]
	add	r2, r2, r8, asr r6
	str	r2, [r0, #20]
	ldr	r8, [r1, #16]
	and	r8, r5, r8, asr lr
	add	r2, r2, r8, lsl #6
	str	r2, [r0, #20]
	ldr	r2, [r1, #16]
	ldr	r8, [sp, #12]
	asr	r2, r2, lr
	add	r2, r8, r2, asr r7
	str	r2, [r0, #24]
	ldr	r8, [r1, #20]
	add	r2, r2, r8, asr r6
	str	r2, [r0, #24]
	ldr	r8, [r1, #20]
	and	r8, r5, r8, asr lr
	add	r2, r2, r8, lsl #6
	str	r2, [r0, #24]
	ldr	r2, [r1, #20]
	asr	r2, r2, lr
	add	r4, r4, r2, asr r7
	str	r4, [r0, #28]
	ldr	r2, [r1, #24]
	add	r4, r4, r2, asr r6
	str	r4, [r0, #28]
	ldr	r2, [r1, #24]
	and	r2, r5, r2, asr lr
	add	r4, r4, r2, lsl #6
	str	r4, [r0, #28]
	ldr	r2, [r1, #24]
	asr	r2, r2, lr
	add	ip, ip, r2, asr r7
	str	ip, [r0, #32]
	ldr	r2, [r1, #28]
	add	ip, ip, r2, asr r6
	str	ip, [r0, #32]
	ldr	r2, [r1, #28]
	and	r2, r5, r2, asr lr
	add	ip, ip, r2, lsl #6
	str	ip, [r0, #32]
	ldr	r2, [r1, #32]
	ldr	ip, [r1, #28]
	asr	r1, r2, lr
	asr	lr, ip, lr
	asr	r2, r2, r6
	add	r2, r2, lr, asr r7
	and	r5, r5, r1
	add	r5, r2, r5, lsl #6
	ldr	r2, [sp, #4]
	asr	r7, r1, r7
	add	r5, r2, r5, lsl #1
	str	r5, [r0]
	ldr	r2, [r10]
	add	r3, r3, r7, lsl #1
	and	r2, r2, r5
	add	r6, r3, r5, asr r6
	stm	r0, {r2, r6}
	add	sp, sp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L5:
	.align	2
.L4:
	.word	bottom58bits
	.word	bottom52bits
	.size	felem_reduce, .-felem_reduce
	.comm	bottom58bits,4,4
	.comm	bottom52bits,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
