	.file	"extr_synclinkmp.c_async_mode.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	async_mode, @function
async_mode:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rdi
	call	tx_stop@PLT
	mov	rdi, rbp
	call	rx_stop@PLT
	xor	edx, edx
	cmp	DWORD PTR 16[rbp], 1
	je	.L2
	movzx	edx, BYTE PTR BIT1[rip]
.L2:
	mov	esi, DWORD PTR MD0[rip]
	mov	rdi, rbp
	call	write_reg@PLT
	mov	eax, DWORD PTR 20[rbp]
	cmp	eax, 6
	je	.L3
	cmp	eax, 7
	je	.L4
	mov	edx, 64
	cmp	eax, 5
	je	.L16
.L6:
	mov	rax, QWORD PTR 24[rbp]
	cmp	rax, QWORD PTR ASYNC_PARITY_NONE[rip]
	je	.L7
	or	dl, BYTE PTR BIT1[rip]
	cmp	rax, QWORD PTR ASYNC_PARITY_ODD[rip]
	je	.L17
.L7:
	mov	esi, DWORD PTR MD1[rip]
	movzx	edx, dl
	mov	rdi, rbp
	call	write_reg@PLT
	xor	edx, edx
	cmp	QWORD PTR 40[rbp], 0
	je	.L8
	movzx	edx, BYTE PTR BIT0[rip]
	add	dl, BYTE PTR BIT1[rip]
	movzx	edx, dl
.L8:
	mov	esi, DWORD PTR MD2[rip]
	mov	rdi, rbp
	call	write_reg@PLT
	movzx	edx, BYTE PTR BIT6[rip]
	mov	esi, DWORD PTR RXS[rip]
	mov	rdi, rbp
	call	write_reg@PLT
	mov	esi, DWORD PTR TXS[rip]
	movzx	edx, BYTE PTR BIT6[rip]
	mov	rdi, rbp
	call	write_reg@PLT
	mov	rax, QWORD PTR 48[rbp]
	mov	ecx, DWORD PTR 0[rbp]
	mov	rdi, rbp
	mov	rdx, QWORD PTR [rax]
	movzx	eax, BYTE PTR BIT0[rip]
	add	ecx, ecx
	sal	eax, cl
	or	BYTE PTR [rdx], al
	call	write_control_reg@PLT
	mov	rdi, rbp
	call	tx_set_idle@PLT
	mov	esi, DWORD PTR RRC[rip]
	xor	edx, edx
	mov	rdi, rbp
	call	write_reg@PLT
	mov	esi, DWORD PTR TRC0[rip]
	mov	rdi, rbp
	mov	edx, 16
	call	write_reg@PLT
	mov	esi, DWORD PTR TRC1[rip]
	mov	rdi, rbp
	mov	edx, 30
	call	write_reg@PLT
	mov	eax, DWORD PTR 4[rbp]
	xor	edx, edx
	test	DWORD PTR SerialSignal_RTS[rip], eax
	sete	dl
	mov	esi, DWORD PTR CTL[rip]
	mov	rdi, rbp
	add	edx, 16
	call	write_reg@PLT
	movzx	edx, BYTE PTR RXINTE[rip]
	add	dl, BYTE PTR TXINTE[rip]
	mov	rdi, rbp
	or	dl, BYTE PTR 8[rbp]
	mov	esi, DWORD PTR IE0[rip]
	mov	BYTE PTR 8[rbp], dl
	movzx	edx, dl
	call	write_reg@PLT
	movzx	edx, BYTE PTR BRKD[rip]
	mov	esi, DWORD PTR IE1[rip]
	mov	rdi, rbp
	mov	BYTE PTR 9[rbp], dl
	call	write_reg@PLT
	movzx	edx, BYTE PTR OVRN[rip]
	mov	esi, DWORD PTR IE2[rip]
	mov	rdi, rbp
	mov	BYTE PTR 10[rbp], dl
	call	write_reg@PLT
	mov	esi, DWORD PTR 32[rbp]
	mov	rdi, rbp
	pop	rbp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	sal	esi, 4
	jmp	set_rate@PLT
	.p2align 4,,10
	.p2align 3
.L17:
	.cfi_restore_state
	or	dl, BYTE PTR BIT0[rip]
	jmp	.L7
	.p2align 4,,10
	.p2align 3
.L16:
	movzx	edx, BYTE PTR BIT4[rip]
	add	dl, BYTE PTR BIT5[rip]
	add	dl, BYTE PTR BIT3[rip]
	add	dl, BYTE PTR BIT2[rip]
	or	edx, 64
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L4:
	movzx	edx, BYTE PTR BIT2[rip]
	add	dl, BYTE PTR BIT4[rip]
	or	edx, 64
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L3:
	movzx	edx, BYTE PTR BIT3[rip]
	add	dl, BYTE PTR BIT5[rip]
	or	edx, 64
	jmp	.L6
	.cfi_endproc
.LFE0:
	.size	async_mode, .-async_mode
	.comm	TXS,4,4
	.comm	TXINTE,1,1
	.comm	TRC1,4,4
	.comm	TRC0,4,4
	.comm	SerialSignal_RTS,4,4
	.comm	RXS,4,4
	.comm	RXINTE,1,1
	.comm	RRC,4,4
	.comm	OVRN,1,1
	.comm	MD2,4,4
	.comm	MD1,4,4
	.comm	MD0,4,4
	.comm	IE2,4,4
	.comm	IE1,4,4
	.comm	IE0,4,4
	.comm	CTL,4,4
	.comm	BRKD,1,1
	.comm	BIT6,1,1
	.comm	BIT5,1,1
	.comm	BIT4,1,1
	.comm	BIT3,1,1
	.comm	BIT2,1,1
	.comm	BIT1,1,1
	.comm	BIT0,1,1
	.comm	ASYNC_PARITY_ODD,8,8
	.comm	ASYNC_PARITY_NONE,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_synclinkmp.c_async_mode.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	async_mode, %function
async_mode:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, lr}
	mov	r4, r0
	bl	tx_stop
	mov	r0, r4
	bl	rx_stop
	ldr	r3, [r4, #12]
	mov	r0, r4
	cmp	r3, #1
	ldrne	r3, .L21
	moveq	r2, #0
	ldrbne	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L21+4
	ldr	r1, [r3]
	bl	write_reg
	ldr	r3, [r4, #16]
	cmp	r3, #6
	beq	.L3
	cmp	r3, #7
	beq	.L4
	cmp	r3, #5
	movne	r2, #64
	beq	.L20
.L6:
	ldr	r1, .L21+8
	ldr	r3, [r4, #20]
	ldr	r1, [r1]
	cmp	r3, r1
	ldreq	r5, .L21+12
	beq	.L7
	ldr	r0, .L21+16
	ldr	r1, .L21
	ldr	r0, [r0]
	ldr	r5, .L21+12
	cmp	r3, r0
	ldrb	r1, [r1]	@ zero_extendqisi2
	ldrbeq	r3, [r5]	@ zero_extendqisi2
	orr	r2, r2, r1
	orreq	r2, r2, r3
.L7:
	ldr	r3, .L21+20
	mov	r0, r4
	ldr	r1, [r3]
	bl	write_reg
	ldr	r2, [r4, #28]
	mov	r0, r4
	cmp	r2, #0
	ldrne	r2, .L21
	ldrbne	r3, [r5]	@ zero_extendqisi2
	ldrbne	r2, [r2]	@ zero_extendqisi2
	ldr	r6, .L21+24
	addne	r2, r2, r3
	ldr	r3, .L21+28
	andne	r2, r2, #255
	ldr	r1, [r3]
	bl	write_reg
	ldr	r3, .L21+32
	ldrb	r2, [r6]	@ zero_extendqisi2
	ldr	r1, [r3]
	mov	r0, r4
	bl	write_reg
	ldr	r3, .L21+36
	ldrb	r2, [r6]	@ zero_extendqisi2
	ldr	r1, [r3]
	mov	r0, r4
	bl	write_reg
	ldr	r3, [r4, #32]
	ldr	r2, [r4]
	ldr	r1, [r3]
	ldrb	r0, [r5]	@ zero_extendqisi2
	ldrb	r3, [r1]	@ zero_extendqisi2
	lsl	r2, r2, #1
	orr	r3, r3, r0, lsl r2
	strb	r3, [r1]
	mov	r0, r4
	bl	write_control_reg
	mov	r0, r4
	bl	tx_set_idle
	ldr	r3, .L21+40
	mov	r2, #0
	ldr	r1, [r3]
	mov	r0, r4
	bl	write_reg
	ldr	r3, .L21+44
	mov	r2, #16
	ldr	r1, [r3]
	mov	r0, r4
	bl	write_reg
	ldr	r3, .L21+48
	mov	r2, #30
	ldr	r1, [r3]
	mov	r0, r4
	bl	write_reg
	ldr	r3, .L21+52
	ldr	r1, [r4, #4]
	ldr	r2, [r3]
	ldr	r3, .L21+56
	tst	r1, r2
	movne	r2, #16
	moveq	r2, #17
	ldr	r1, [r3]
	mov	r0, r4
	bl	write_reg
	ldr	r3, .L21+60
	ldr	r2, .L21+64
	ldrb	r1, [r3]	@ zero_extendqisi2
	ldrb	r2, [r2]	@ zero_extendqisi2
	ldrb	r3, [r4, #8]	@ zero_extendqisi2
	add	r2, r2, r1
	orr	r2, r2, r3
	ldr	r3, .L21+68
	and	r2, r2, #255
	ldr	r1, [r3]
	strb	r2, [r4, #8]
	mov	r0, r4
	bl	write_reg
	ldr	r2, .L21+72
	ldr	r3, .L21+76
	ldrb	r2, [r2]	@ zero_extendqisi2
	ldr	r1, [r3]
	strb	r2, [r4, #9]
	mov	r0, r4
	bl	write_reg
	ldr	r2, .L21+80
	ldr	r3, .L21+84
	ldrb	r2, [r2]	@ zero_extendqisi2
	mov	r0, r4
	ldr	r1, [r3]
	strb	r2, [r4, #10]
	bl	write_reg
	ldr	r1, [r4, #24]
	mov	r0, r4
	pop	{r4, r5, r6, lr}
	lsl	r1, r1, #4
	b	set_rate
.L3:
	ldr	r2, .L21+88
	ldr	r3, .L21+92
.L18:
	ldrb	r2, [r2]	@ zero_extendqisi2
	ldrb	r3, [r3]	@ zero_extendqisi2
	add	r2, r2, r3
	orr	r2, r2, #64
	and	r2, r2, #255
	b	.L6
.L20:
	ldr	r3, .L21+96
	ldr	r2, .L21+88
	ldr	r1, .L21+92
	ldrb	r0, [r3]	@ zero_extendqisi2
	ldrb	r2, [r2]	@ zero_extendqisi2
	ldr	r3, .L21+100
	ldrb	r1, [r1]	@ zero_extendqisi2
	ldrb	r3, [r3]	@ zero_extendqisi2
	add	r2, r2, r0
	add	r2, r2, r1
	add	r2, r2, r3
	orr	r2, r2, #64
	and	r2, r2, #255
	b	.L6
.L4:
	ldr	r2, .L21+96
	ldr	r3, .L21+100
	b	.L18
.L22:
	.align	2
.L21:
	.word	BIT1
	.word	MD0
	.word	ASYNC_PARITY_NONE
	.word	BIT0
	.word	ASYNC_PARITY_ODD
	.word	MD1
	.word	BIT6
	.word	MD2
	.word	RXS
	.word	TXS
	.word	RRC
	.word	TRC0
	.word	TRC1
	.word	SerialSignal_RTS
	.word	CTL
	.word	RXINTE
	.word	TXINTE
	.word	IE0
	.word	BRKD
	.word	IE1
	.word	OVRN
	.word	IE2
	.word	BIT5
	.word	BIT3
	.word	BIT4
	.word	BIT2
	.size	async_mode, .-async_mode
	.comm	TXS,4,4
	.comm	TXINTE,1,1
	.comm	TRC1,4,4
	.comm	TRC0,4,4
	.comm	SerialSignal_RTS,4,4
	.comm	RXS,4,4
	.comm	RXINTE,1,1
	.comm	RRC,4,4
	.comm	OVRN,1,1
	.comm	MD2,4,4
	.comm	MD1,4,4
	.comm	MD0,4,4
	.comm	IE2,4,4
	.comm	IE1,4,4
	.comm	IE0,4,4
	.comm	CTL,4,4
	.comm	BRKD,1,1
	.comm	BIT6,1,1
	.comm	BIT5,1,1
	.comm	BIT4,1,1
	.comm	BIT3,1,1
	.comm	BIT2,1,1
	.comm	BIT1,1,1
	.comm	BIT0,1,1
	.comm	ASYNC_PARITY_ODD,4,4
	.comm	ASYNC_PARITY_NONE,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
