	.file	"extr_intel_sdvo.c_intel_sdvo_pre_enable.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC0:
	.string	"Setting output timings on %s failed\n"
	.align 8
.LC1:
	.string	"Setting input timings on %s failed\n"
	.align 8
.LC2:
	.string	"unknown pixel multiplier specified\n"
	.text
	.p2align 4
	.type	intel_sdvo_pre_enable, @function
intel_sdvo_pre_enable:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	mov	r12, rdx
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	rbx, rsi
	sub	rsp, 72
	.cfi_def_cfa_offset 128
	mov	edi, DWORD PTR [rdi]
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 56[rsp], rax
	xor	eax, eax
	call	to_i915@PLT
	mov	edi, DWORD PTR 32[rbx]
	mov	r14, rax
	call	to_intel_crtc@PLT
	mov	rdi, r12
	mov	QWORD PTR [rsp], rax
	call	to_intel_sdvo_connector_state@PLT
	mov	edi, DWORD PTR [r12]
	mov	r15, rax
	call	to_intel_sdvo_connector@PLT
	mov	rdi, rbp
	mov	r13, rax
	call	to_sdvo@PLT
	mov	rsi, r15
	mov	rbp, rax
	mov	rdi, rax
	call	intel_sdvo_update_props@PLT
	mov	eax, DWORD PTR 20[rbp]
	mov	rdi, rbp
	lea	rdx, 32[rsp]
	mov	esi, DWORD PTR SDVO_CMD_SET_IN_OUT_MAP[rip]
	mov	ecx, 16
	mov	QWORD PTR 32[rsp], 0
	mov	DWORD PTR 40[rsp], eax
	call	intel_sdvo_set_value@PLT
	mov	esi, DWORD PTR 20[rbp]
	mov	rdi, rbp
	call	intel_sdvo_set_target_output@PLT
	test	eax, eax
	jne	.L51
.L1:
	mov	rax, QWORD PTR 56[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L52
	add	rsp, 72
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L51:
	.cfi_restore_state
	mov	rdi, r13
	call	IS_LVDS@PLT
	test	rax, rax
	je	.L3
	lea	r8, 28[rsp]
	mov	rsi, QWORD PTR 0[r13]
	mov	rdi, r8
	mov	QWORD PTR 8[rsp], r8
	call	intel_sdvo_get_dtd_from_mode@PLT
	mov	r8, QWORD PTR 8[rsp]
	mov	rdi, rbp
	mov	rsi, r8
	call	intel_sdvo_set_output_timing@PLT
	test	eax, eax
	je	.L53
.L5:
	mov	rdi, rbp
	call	intel_sdvo_set_target_input@PLT
	test	eax, eax
	je	.L1
	cmp	QWORD PTR 16[rbx], 0
	jne	.L54
	mov	esi, DWORD PTR SDVO_ENCODE_DVI[rip]
	mov	rdi, rbp
	call	intel_sdvo_set_encode@PLT
.L7:
	mov	rdi, r13
	call	IS_TV@PLT
	test	rax, rax
	je	.L11
	mov	rsi, r12
	mov	rdi, rbp
	call	intel_sdvo_set_tv_format@PLT
	test	eax, eax
	je	.L1
.L11:
	lea	r12, 24[rsp]
	lea	rsi, 28[rbx]
	mov	rdi, r12
	call	intel_sdvo_get_dtd_from_mode@PLT
	mov	rdi, r13
	call	IS_TV@PLT
	test	rax, rax
	je	.L55
.L9:
	mov	eax, DWORD PTR 0[rbp]
	mov	DWORD PTR 24[rsp], eax
.L12:
	mov	rsi, r12
	mov	rdi, rbp
	call	intel_sdvo_set_input_timing@PLT
	test	eax, eax
	je	.L56
.L13:
	mov	eax, DWORD PTR [rbx]
	cmp	eax, 2
	je	.L14
	mov	esi, DWORD PTR SDVO_CLOCK_RATE_MULT_4X[rip]
	cmp	eax, 4
	je	.L17
	cmp	eax, 1
	je	.L16
	lea	rsi, .LC2[rip]
	mov	edi, 1
	call	WARN@PLT
.L16:
	mov	esi, DWORD PTR SDVO_CLOCK_RATE_MULT_1X[rip]
.L17:
	mov	rdi, rbp
	call	intel_sdvo_set_clock_rate_mult@PLT
	test	eax, eax
	je	.L1
	mov	rdi, r14
	call	INTEL_GEN@PLT
	cmp	eax, 3
	jle	.L18
	mov	rdi, r14
	mov	r12d, DWORD PTR SDVO_VSYNC_ACTIVE_HIGH[rip]
	or	r12d, DWORD PTR SDVO_HSYNC_ACTIVE_HIGH[rip]
	call	HAS_PCH_SPLIT@PLT
	test	eax, eax
	jne	.L19
	cmp	QWORD PTR 8[rbx], 0
	je	.L19
	or	r12d, DWORD PTR HDMI_COLOR_RANGE_16_235[rip]
.L19:
	mov	rdi, r14
	call	INTEL_GEN@PLT
	cmp	eax, 4
	jle	.L57
.L20:
	mov	rdi, r14
	call	HAS_PCH_CPT@PLT
	test	rax, rax
	mov	rax, QWORD PTR [rsp]
	mov	edi, DWORD PTR [rax]
	je	.L23
	call	SDVO_PIPE_SEL_CPT@PLT
	or	r12d, eax
.L24:
	mov	rdi, r14
	call	INTEL_GEN@PLT
	cmp	eax, 3
	jle	.L58
.L25:
	mov	eax, DWORD PTR 24[rsp]
	test	DWORD PTR SDVO_NEED_TO_STALL[rip], eax
	jne	.L59
.L26:
	mov	esi, r12d
	mov	rdi, rbp
	call	intel_sdvo_write_sdvox@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L3:
	lea	r8, 28[rsp]
	lea	rsi, 24[rbx]
	mov	rdi, r8
	mov	QWORD PTR 8[rsp], r8
	call	intel_sdvo_get_dtd_from_mode@PLT
	mov	r8, QWORD PTR 8[rsp]
	mov	rdi, rbp
	mov	rsi, r8
	call	intel_sdvo_set_output_timing@PLT
	test	eax, eax
	jne	.L5
.L53:
	mov	rdi, rbp
	call	SDVO_NAME@PLT
	lea	rdi, .LC0[rip]
	mov	esi, eax
	call	DRM_INFO@PLT
	jmp	.L5
	.p2align 4,,10
	.p2align 3
.L54:
	mov	esi, DWORD PTR SDVO_ENCODE_HDMI[rip]
	mov	rdi, rbp
	call	intel_sdvo_set_encode@PLT
	mov	esi, DWORD PTR SDVO_COLORIMETRY_RGB256[rip]
	mov	rdi, rbp
	call	intel_sdvo_set_colorimetry@PLT
	mov	rsi, rbx
	mov	rdi, rbp
	call	intel_sdvo_set_avi_infoframe@PLT
	jmp	.L7
	.p2align 4,,10
	.p2align 3
.L56:
	mov	rdi, rbp
	call	SDVO_NAME@PLT
	lea	rdi, .LC1[rip]
	mov	esi, eax
	call	DRM_INFO@PLT
	jmp	.L13
	.p2align 4,,10
	.p2align 3
.L55:
	mov	rdi, r13
	call	IS_LVDS@PLT
	test	rax, rax
	jne	.L9
	jmp	.L12
	.p2align 4,,10
	.p2align 3
.L14:
	mov	esi, DWORD PTR SDVO_CLOCK_RATE_MULT_2X[rip]
	jmp	.L17
	.p2align 4,,10
	.p2align 3
.L18:
	mov	edi, DWORD PTR 16[rbp]
	call	I915_READ@PLT
	mov	r12d, DWORD PTR SDVOC_PRESERVE_MASK[rip]
	mov	rcx, QWORD PTR PORT_B[rip]
	and	r12d, eax
	cmp	QWORD PTR 8[rbp], rcx
	je	.L60
.L22:
	or	r12d, DWORD PTR SDVO_BORDER_ENABLE[rip]
	or	r12d, 4718592
	jmp	.L20
	.p2align 4,,10
	.p2align 3
.L23:
	call	SDVO_PIPE_SEL@PLT
	or	r12d, eax
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L57:
	or	r12d, DWORD PTR SDVO_BORDER_ENABLE[rip]
	jmp	.L20
	.p2align 4,,10
	.p2align 3
.L60:
	and	eax, DWORD PTR SDVOB_PRESERVE_MASK[rip]
	mov	r12d, eax
	jmp	.L22
	.p2align 4,,10
	.p2align 3
.L59:
	mov	rdi, r14
	call	INTEL_GEN@PLT
	cmp	eax, 4
	jg	.L26
	or	r12d, DWORD PTR SDVO_STALL_SELECT[rip]
	jmp	.L26
	.p2align 4,,10
	.p2align 3
.L58:
	mov	rdi, r14
	call	IS_I945G@PLT
	test	rax, rax
	jne	.L25
	mov	rdi, r14
	call	IS_I945GM@PLT
	test	rax, rax
	jne	.L25
	mov	rdi, r14
	call	IS_G33@PLT
	test	rax, rax
	jne	.L25
	mov	rdi, r14
	call	IS_PINEVIEW@PLT
	test	rax, rax
	jne	.L25
	mov	eax, DWORD PTR [rbx]
	mov	ecx, DWORD PTR SDVO_PORT_MULTIPLY_SHIFT[rip]
	sub	eax, 1
	sal	eax, cl
	or	r12d, eax
	jmp	.L25
.L52:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	intel_sdvo_pre_enable, .-intel_sdvo_pre_enable
	.comm	SDVO_VSYNC_ACTIVE_HIGH,4,4
	.comm	SDVO_STALL_SELECT,4,4
	.comm	SDVO_PORT_MULTIPLY_SHIFT,4,4
	.comm	SDVO_NEED_TO_STALL,4,4
	.comm	SDVO_HSYNC_ACTIVE_HIGH,4,4
	.comm	SDVO_ENCODE_HDMI,4,4
	.comm	SDVO_ENCODE_DVI,4,4
	.comm	SDVO_COLORIMETRY_RGB256,4,4
	.comm	SDVO_CMD_SET_IN_OUT_MAP,4,4
	.comm	SDVO_CLOCK_RATE_MULT_4X,4,4
	.comm	SDVO_CLOCK_RATE_MULT_2X,4,4
	.comm	SDVO_CLOCK_RATE_MULT_1X,4,4
	.comm	SDVO_BORDER_ENABLE,4,4
	.comm	SDVOC_PRESERVE_MASK,4,4
	.comm	SDVOB_PRESERVE_MASK,4,4
	.comm	PORT_B,8,8
	.comm	HDMI_COLOR_RANGE_16_235,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_intel_sdvo.c_intel_sdvo_pre_enable.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"Setting output timings on %s failed\012\000"
	.align	2
.LC1:
	.ascii	"Setting input timings on %s failed\012\000"
	.align	2
.LC2:
	.ascii	"unknown pixel multiplier specified\012\000"
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC3:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	intel_sdvo_pre_enable, %function
intel_sdvo_pre_enable:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, lr}
	ldr	r3, .L62
	sub	sp, sp, #24
	mov	r4, r0
	ldr	r0, [r0]
	mov	r6, r2
	mov	r5, r1
	ldr	r3, [r3]
	str	r3, [sp, #20]
	mov	r3,#0
	bl	to_i915
	mov	r9, r0
	ldr	r0, [r5, #20]
	bl	to_intel_crtc
	mov	r10, r0
	mov	r0, r6
	bl	to_intel_sdvo_connector_state
	mov	r8, r0
	ldr	r0, [r6]
	bl	to_intel_sdvo_connector
	mov	r7, r0
	mov	r0, r4
	bl	to_sdvo
	mov	r4, r0
	mov	r1, r8
	bl	intel_sdvo_update_props
	mov	ip, #0
	ldr	r2, [r4, #12]
	ldr	r3, .L62+4
	str	r2, [sp, #16]
	ldr	r1, [r3]
	add	r2, sp, #12
	mov	r3, #8
	mov	r0, r4
	str	ip, [sp, #12]
	bl	intel_sdvo_set_value
	mov	r0, r4
	ldr	r1, [r4, #12]
	bl	intel_sdvo_set_target_output
	cmp	r0, #0
	bne	.L53
.L1:
	ldr	r3, .L62
	ldr	r2, [r3]
	ldr	r3, [sp, #20]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L54
	add	sp, sp, #24
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
.L53:
	mov	r0, r7
	bl	IS_LVDS
	add	r8, sp, #8
	cmp	r0, #0
	ldrne	r1, [r7]
	addeq	r1, r5, #12
	mov	r0, r8
	bl	intel_sdvo_get_dtd_from_mode
	mov	r1, r8
	mov	r0, r4
	bl	intel_sdvo_set_output_timing
	cmp	r0, #0
	beq	.L55
.L5:
	mov	r0, r4
	bl	intel_sdvo_set_target_input
	cmp	r0, #0
	beq	.L1
	ldr	r3, [r5, #8]
	cmp	r3, #0
	bne	.L56
	ldr	r3, .L62+8
	mov	r0, r4
	ldr	r1, [r3]
	bl	intel_sdvo_set_encode
.L7:
	mov	r0, r7
	bl	IS_TV
	cmp	r0, #0
	beq	.L11
	mov	r1, r6
	mov	r0, r4
	bl	intel_sdvo_set_tv_format
	cmp	r0, #0
	beq	.L1
.L11:
	add	r1, r5, #16
	add	r0, sp, #4
	bl	intel_sdvo_get_dtd_from_mode
	mov	r0, r7
	bl	IS_TV
	cmp	r0, #0
	beq	.L57
.L9:
	ldr	r3, [r4]
	str	r3, [sp, #4]
.L12:
	mov	r0, r4
	add	r1, sp, #4
	bl	intel_sdvo_set_input_timing
	cmp	r0, #0
	beq	.L58
.L13:
	ldr	r3, [r5]
	cmp	r3, #2
	beq	.L14
	cmp	r3, #4
	beq	.L15
	cmp	r3, #1
	beq	.L16
	mov	r0, #1
	ldr	r1, .L62+12
	bl	WARN
.L16:
	ldr	r3, .L62+16
	ldr	r1, [r3]
.L17:
	mov	r0, r4
	bl	intel_sdvo_set_clock_rate_mult
	cmp	r0, #0
	beq	.L1
	mov	r0, r9
	bl	INTEL_GEN
	cmp	r0, #3
	ble	.L18
	ldr	r2, .L62+20
	ldr	r3, .L62+24
	ldr	r6, [r2]
	ldr	r3, [r3]
	mov	r0, r9
	orr	r6, r6, r3
	bl	HAS_PCH_SPLIT
	cmp	r0, #0
	bne	.L19
	ldr	r3, [r5, #4]
	cmp	r3, #0
	ldrne	r3, .L62+28
	ldrne	r3, [r3]
	orrne	r6, r6, r3
.L19:
	mov	r0, r9
	bl	INTEL_GEN
	cmp	r0, #4
	ble	.L59
.L20:
	mov	r0, r9
	bl	HAS_PCH_CPT
	cmp	r0, #0
	ldr	r0, [r10]
	beq	.L23
	bl	SDVO_PIPE_SEL_CPT
	orr	r6, r6, r0
.L24:
	mov	r0, r9
	bl	INTEL_GEN
	cmp	r0, #3
	ble	.L60
.L25:
	ldr	r3, .L62+32
	ldr	r2, [sp, #4]
	ldr	r3, [r3]
	tst	r2, r3
	bne	.L61
.L26:
	mov	r1, r6
	mov	r0, r4
	bl	intel_sdvo_write_sdvox
	b	.L1
.L56:
	ldr	r3, .L62+36
	mov	r0, r4
	ldr	r1, [r3]
	bl	intel_sdvo_set_encode
	ldr	r3, .L62+40
	mov	r0, r4
	ldr	r1, [r3]
	bl	intel_sdvo_set_colorimetry
	mov	r1, r5
	mov	r0, r4
	bl	intel_sdvo_set_avi_infoframe
	b	.L7
.L55:
	mov	r0, r4
	bl	SDVO_NAME
	mov	r1, r0
	ldr	r0, .L62+44
	bl	DRM_INFO
	b	.L5
.L58:
	mov	r0, r4
	bl	SDVO_NAME
	mov	r1, r0
	ldr	r0, .L62+48
	bl	DRM_INFO
	b	.L13
.L57:
	mov	r0, r7
	bl	IS_LVDS
	cmp	r0, #0
	bne	.L9
	b	.L12
.L15:
	ldr	r3, .L62+52
	ldr	r1, [r3]
	b	.L17
.L14:
	ldr	r3, .L62+56
	ldr	r1, [r3]
	b	.L17
.L18:
	ldr	r0, [r4, #8]
	bl	I915_READ
	ldr	r3, .L62+60
	ldr	r2, [r4, #4]
	ldr	r3, [r3]
	cmp	r2, r3
	ldreq	r3, .L62+64
	ldrne	r3, .L62+68
	ldr	r6, [r3]
	ldr	r3, .L62+72
	and	r6, r6, r0
	ldr	r3, [r3]
	orr	r6, r6, r3
	orr	r6, r6, #4718592
	b	.L20
.L23:
	bl	SDVO_PIPE_SEL
	orr	r6, r6, r0
	b	.L24
.L59:
	ldr	r3, .L62+72
	ldr	r3, [r3]
	orr	r6, r6, r3
	b	.L20
.L61:
	mov	r0, r9
	bl	INTEL_GEN
	cmp	r0, #4
	ldrle	r3, .L62+76
	ldrle	r3, [r3]
	orrle	r6, r6, r3
	b	.L26
.L60:
	mov	r0, r9
	bl	IS_I945G
	cmp	r0, #0
	bne	.L25
	mov	r0, r9
	bl	IS_I945GM
	cmp	r0, #0
	bne	.L25
	mov	r0, r9
	bl	IS_G33
	cmp	r0, #0
	bne	.L25
	mov	r0, r9
	bl	IS_PINEVIEW
	cmp	r0, #0
	ldreq	r2, .L62+80
	ldreq	r3, [r5]
	ldreq	r2, [r2]
	subeq	r3, r3, #1
	orreq	r6, r6, r3, lsl r2
	b	.L25
.L54:
	bl	__stack_chk_fail
.L63:
	.align	2
.L62:
	.word	.LC3
	.word	SDVO_CMD_SET_IN_OUT_MAP
	.word	SDVO_ENCODE_DVI
	.word	.LC2
	.word	SDVO_CLOCK_RATE_MULT_1X
	.word	SDVO_VSYNC_ACTIVE_HIGH
	.word	SDVO_HSYNC_ACTIVE_HIGH
	.word	HDMI_COLOR_RANGE_16_235
	.word	SDVO_NEED_TO_STALL
	.word	SDVO_ENCODE_HDMI
	.word	SDVO_COLORIMETRY_RGB256
	.word	.LC0
	.word	.LC1
	.word	SDVO_CLOCK_RATE_MULT_4X
	.word	SDVO_CLOCK_RATE_MULT_2X
	.word	PORT_B
	.word	SDVOB_PRESERVE_MASK
	.word	SDVOC_PRESERVE_MASK
	.word	SDVO_BORDER_ENABLE
	.word	SDVO_STALL_SELECT
	.word	SDVO_PORT_MULTIPLY_SHIFT
	.size	intel_sdvo_pre_enable, .-intel_sdvo_pre_enable
	.comm	SDVO_VSYNC_ACTIVE_HIGH,4,4
	.comm	SDVO_STALL_SELECT,4,4
	.comm	SDVO_PORT_MULTIPLY_SHIFT,4,4
	.comm	SDVO_NEED_TO_STALL,4,4
	.comm	SDVO_HSYNC_ACTIVE_HIGH,4,4
	.comm	SDVO_ENCODE_HDMI,4,4
	.comm	SDVO_ENCODE_DVI,4,4
	.comm	SDVO_COLORIMETRY_RGB256,4,4
	.comm	SDVO_CMD_SET_IN_OUT_MAP,4,4
	.comm	SDVO_CLOCK_RATE_MULT_4X,4,4
	.comm	SDVO_CLOCK_RATE_MULT_2X,4,4
	.comm	SDVO_CLOCK_RATE_MULT_1X,4,4
	.comm	SDVO_BORDER_ENABLE,4,4
	.comm	SDVOC_PRESERVE_MASK,4,4
	.comm	SDVOB_PRESERVE_MASK,4,4
	.comm	PORT_B,4,4
	.comm	HDMI_COLOR_RANGE_16_235,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
