	.file	"extr_if_alc.c_alc_phy_reset_813x.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	alc_phy_reset_813x, @function
alc_phy_reset_813x:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	mov	rbx, rdi
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	mov	edx, DWORD PTR GPHY_CFG_SEL_ANA_RESET[rip]
	mov	esi, DWORD PTR ALC_GPHY_CFG[rip]
	call	CSR_WRITE_2@PLT
	mov	esi, DWORD PTR ALC_GPHY_CFG[rip]
	mov	rdi, rbx
	call	CSR_READ_2@PLT
	mov	edi, 10000
	call	DELAY@PLT
	mov	esi, DWORD PTR ALC_GPHY_CFG[rip]
	mov	edx, DWORD PTR GPHY_CFG_EXT_RESET[rip]
	mov	rdi, rbx
	or	edx, DWORD PTR GPHY_CFG_SEL_ANA_RESET[rip]
	call	CSR_WRITE_2@PLT
	mov	esi, DWORD PTR ALC_GPHY_CFG[rip]
	mov	rdi, rbx
	call	CSR_READ_2@PLT
	mov	edi, 10000
	call	DELAY@PLT
	mov	rax, QWORD PTR 8[rbx]
	mov	rax, QWORD PTR [rax]
	cmp	rax, QWORD PTR DEVICEID_ATHEROS_AR8152_B[rip]
	je	.L9
.L2:
	cmp	QWORD PTR DEVICEID_ATHEROS_AR8151[rip], rax
	je	.L3
	cmp	QWORD PTR DEVICEID_ATHEROS_AR8151_V2[rip], rax
	je	.L3
	cmp	QWORD PTR DEVICEID_ATHEROS_AR8152_B[rip], rax
	je	.L3
	cmp	QWORD PTR DEVICEID_ATHEROS_AR8152_B2[rip], rax
	jne	.L4
	.p2align 4,,10
	.p2align 3
.L3:
	mov	edi, DWORD PTR 4[rbx]
	mov	edx, DWORD PTR ALC_MII_DBG_ADDR[rip]
	mov	ecx, 59
	mov	esi, DWORD PTR [rbx]
	call	alc_miibus_writereg@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	edx, DWORD PTR ALC_MII_DBG_DATA[rip]
	mov	esi, DWORD PTR [rbx]
	call	alc_miibus_readreg@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	edx, DWORD PTR ALC_MII_DBG_DATA[rip]
	and	eax, 65527
	mov	esi, DWORD PTR [rbx]
	mov	ecx, eax
	call	alc_miibus_writereg@PLT
	mov	edi, 20000
	call	DELAY@PLT
	mov	rax, QWORD PTR 8[rbx]
	mov	rax, QWORD PTR [rax]
	cmp	rax, QWORD PTR DEVICEID_ATHEROS_AR8151[rip]
	je	.L10
.L4:
	cmp	QWORD PTR DEVICEID_ATHEROS_AR8131[rip], rax
	je	.L5
	cmp	QWORD PTR DEVICEID_ATHEROS_AR8132[rip], rax
	je	.L5
	cmp	QWORD PTR DEVICEID_ATHEROS_AR8151_V2[rip], rax
	je	.L5
	cmp	QWORD PTR DEVICEID_ATHEROS_AR8152_B2[rip], rax
	jne	.L6
	.p2align 4,,10
	.p2align 3
.L5:
	mov	edi, DWORD PTR 4[rbx]
	mov	edx, DWORD PTR ALC_MII_DBG_ADDR[rip]
	mov	ecx, 41
	mov	esi, DWORD PTR [rbx]
	call	alc_miibus_writereg@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR [rbx]
	mov	ecx, 46813
	mov	edx, DWORD PTR ALC_MII_DBG_DATA[rip]
	call	alc_miibus_writereg@PLT
.L6:
	mov	ecx, DWORD PTR ANA_INTERVAL_SEL_TIMER_SHIFT[rip]
	mov	eax, 1
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR [rbx]
	mov	edx, DWORD PTR ALC_MII_DBG_ADDR[rip]
	sal	eax, cl
	mov	ecx, DWORD PTR MII_ANA_CFG18[rip]
	and	eax, DWORD PTR ANA_INTERVAL_SEL_TIMER_MASK[rip]
	mov	r12d, DWORD PTR ANA_LOOP_SEL_10BT[rip]
	or	r12d, DWORD PTR ANA_EN_MASK_TB[rip]
	or	r12d, DWORD PTR ANA_EN_10BT_IDLE[rip]
	or	r12d, eax
	call	alc_miibus_writereg@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR [rbx]
	mov	ecx, r12d
	mov	edx, DWORD PTR ALC_MII_DBG_DATA[rip]
	call	alc_miibus_writereg@PLT
	mov	eax, 2
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR [rbx]
	mov	ecx, DWORD PTR ANA_SERDES_CDR_BW_SHIFT[rip]
	mov	edx, DWORD PTR ALC_MII_DBG_ADDR[rip]
	mov	r12d, DWORD PTR ANA_SERDES_EN_DEEM[rip]
	or	r12d, DWORD PTR ANA_SERDES_SEL_HSP[rip]
	sal	eax, cl
	mov	ecx, DWORD PTR MII_ANA_CFG5[rip]
	or	r12d, DWORD PTR ANA_SERDES_EN_PLL[rip]
	and	eax, DWORD PTR ANA_SERDES_CDR_BW_MASK[rip]
	or	r12d, DWORD PTR ANA_SERDES_EN_LCKDT[rip]
	or	r12d, eax
	call	alc_miibus_writereg@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR [rbx]
	mov	ecx, r12d
	mov	edx, DWORD PTR ALC_MII_DBG_DATA[rip]
	mov	r12d, 44
	call	alc_miibus_writereg@PLT
	mov	esi, DWORD PTR ANA_SHORT_CABLE_TH_100_SHIFT[rip]
	mov	eax, 33
	mov	ecx, DWORD PTR ANA_LONG_CABLE_TH_100_SHIFT[rip]
	mov	edx, DWORD PTR ANA_BP_BAD_LINK_ACCUM[rip]
	or	edx, DWORD PTR ANA_BP_SMALL_BW[rip]
	sal	r12d, cl
	mov	ecx, esi
	and	r12d, DWORD PTR ANA_LONG_CABLE_TH_100_MASK[rip]
	mov	edi, DWORD PTR 4[rbx]
	sal	eax, cl
	or	r12d, edx
	mov	ecx, DWORD PTR MII_ANA_CFG54[rip]
	mov	edx, DWORD PTR ALC_MII_DBG_ADDR[rip]
	and	eax, esi
	mov	esi, DWORD PTR [rbx]
	or	r12d, eax
	call	alc_miibus_writereg@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR [rbx]
	mov	ecx, r12d
	mov	edx, DWORD PTR ALC_MII_DBG_DATA[rip]
	call	alc_miibus_writereg@PLT
	mov	eax, 11
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR [rbx]
	mov	ecx, DWORD PTR ANA_IECHO_ADJ_3_SHIFT[rip]
	mov	r12d, eax
	sal	r12d, cl
	mov	ecx, DWORD PTR ANA_IECHO_ADJ_2_SHIFT[rip]
	and	r12d, DWORD PTR ANA_IECHO_ADJ_3_MASK[rip]
	sal	eax, cl
	and	eax, DWORD PTR ANA_IECHO_ADJ_2_MASK[rip]
	mov	ecx, DWORD PTR ANA_IECHO_ADJ_1_SHIFT[rip]
	or	r12d, eax
	mov	eax, 8
	mov	edx, eax
	sal	edx, cl
	mov	ecx, DWORD PTR ANA_IECHO_ADJ_0_SHIFT[rip]
	and	edx, DWORD PTR ANA_IECHO_ADJ_1_MASK[rip]
	or	r12d, edx
	mov	edx, DWORD PTR ALC_MII_DBG_ADDR[rip]
	sal	eax, cl
	mov	ecx, DWORD PTR MII_ANA_CFG4[rip]
	and	eax, DWORD PTR ANA_IECHO_ADJ_0_MASK[rip]
	or	r12d, eax
	call	alc_miibus_writereg@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR [rbx]
	mov	ecx, r12d
	mov	edx, DWORD PTR ALC_MII_DBG_DATA[rip]
	call	alc_miibus_writereg@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR [rbx]
	mov	eax, DWORD PTR ANA_MANUL_SWICH_ON_SHIFT[rip]
	mov	ecx, DWORD PTR MII_ANA_CFG0[rip]
	mov	edx, DWORD PTR ALC_MII_DBG_ADDR[rip]
	and	eax, DWORD PTR ANA_MANUL_SWICH_ON_MASK[rip]
	mov	r12d, DWORD PTR ANA_RESTART_CAL[rip]
	and	eax, 7
	or	r12d, DWORD PTR ANA_MAN_ENABLE[rip]
	or	r12d, DWORD PTR ANA_SEL_HSP[rip]
	or	r12d, DWORD PTR ANA_EN_HB[rip]
	or	r12d, DWORD PTR ANA_OEN_125M[rip]
	or	r12d, eax
	call	alc_miibus_writereg@PLT
	mov	esi, DWORD PTR [rbx]
	mov	edi, DWORD PTR 4[rbx]
	mov	ecx, r12d
	mov	edx, DWORD PTR ALC_MII_DBG_DATA[rip]
	call	alc_miibus_writereg@PLT
	mov	edi, 1000
	call	DELAY@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR [rbx]
	mov	ecx, 41
	mov	edx, DWORD PTR ALC_MII_DBG_ADDR[rip]
	call	alc_miibus_writereg@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR [rbx]
	mov	edx, DWORD PTR ALC_MII_DBG_DATA[rip]
	call	alc_miibus_readreg@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR [rbx]
	mov	edx, DWORD PTR ALC_MII_DBG_DATA[rip]
	and	ah, 127
	mov	ecx, eax
	call	alc_miibus_writereg@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR [rbx]
	mov	ecx, 11
	mov	edx, DWORD PTR ALC_MII_DBG_ADDR[rip]
	call	alc_miibus_writereg@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR [rbx]
	mov	edx, DWORD PTR ALC_MII_DBG_DATA[rip]
	call	alc_miibus_readreg@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR [rbx]
	mov	edx, DWORD PTR ALC_MII_DBG_DATA[rip]
	and	ah, 127
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbx
	.cfi_def_cfa_offset 16
	mov	ecx, eax
	pop	r12
	.cfi_def_cfa_offset 8
	jmp	alc_miibus_writereg@PLT
	.p2align 4,,10
	.p2align 3
.L10:
	.cfi_restore_state
	mov	edi, DWORD PTR 4[rbx]
	mov	edx, DWORD PTR ALC_MII_DBG_ADDR[rip]
	mov	ecx, 41
	mov	esi, DWORD PTR [rbx]
	call	alc_miibus_writereg@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR [rbx]
	mov	ecx, 37533
	mov	edx, DWORD PTR ALC_MII_DBG_DATA[rip]
	call	alc_miibus_writereg@PLT
	mov	rax, QWORD PTR 8[rbx]
	mov	rax, QWORD PTR [rax]
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L9:
	mov	edi, DWORD PTR 4[rbx]
	mov	edx, DWORD PTR ALC_MII_DBG_ADDR[rip]
	mov	ecx, 10
	mov	esi, DWORD PTR [rbx]
	call	alc_miibus_writereg@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	edx, DWORD PTR ALC_MII_DBG_DATA[rip]
	mov	esi, DWORD PTR [rbx]
	call	alc_miibus_readreg@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	edx, DWORD PTR ALC_MII_DBG_DATA[rip]
	and	eax, 57343
	mov	esi, DWORD PTR [rbx]
	mov	ecx, eax
	call	alc_miibus_writereg@PLT
	mov	rax, QWORD PTR 8[rbx]
	mov	rax, QWORD PTR [rax]
	jmp	.L2
	.cfi_endproc
.LFE0:
	.size	alc_phy_reset_813x, .-alc_phy_reset_813x
	.comm	MII_ANA_CFG54,4,4
	.comm	MII_ANA_CFG5,4,4
	.comm	MII_ANA_CFG4,4,4
	.comm	MII_ANA_CFG18,4,4
	.comm	MII_ANA_CFG0,4,4
	.comm	GPHY_CFG_SEL_ANA_RESET,4,4
	.comm	GPHY_CFG_EXT_RESET,4,4
	.comm	DEVICEID_ATHEROS_AR8152_B2,8,8
	.comm	DEVICEID_ATHEROS_AR8152_B,8,8
	.comm	DEVICEID_ATHEROS_AR8151_V2,8,8
	.comm	DEVICEID_ATHEROS_AR8151,8,8
	.comm	DEVICEID_ATHEROS_AR8132,8,8
	.comm	DEVICEID_ATHEROS_AR8131,8,8
	.comm	ANA_SHORT_CABLE_TH_100_SHIFT,4,4
	.comm	ANA_SERDES_SEL_HSP,4,4
	.comm	ANA_SERDES_EN_PLL,4,4
	.comm	ANA_SERDES_EN_LCKDT,4,4
	.comm	ANA_SERDES_EN_DEEM,4,4
	.comm	ANA_SERDES_CDR_BW_SHIFT,4,4
	.comm	ANA_SERDES_CDR_BW_MASK,4,4
	.comm	ANA_SEL_HSP,4,4
	.comm	ANA_RESTART_CAL,4,4
	.comm	ANA_OEN_125M,4,4
	.comm	ANA_MAN_ENABLE,4,4
	.comm	ANA_MANUL_SWICH_ON_SHIFT,4,4
	.comm	ANA_MANUL_SWICH_ON_MASK,4,4
	.comm	ANA_LOOP_SEL_10BT,4,4
	.comm	ANA_LONG_CABLE_TH_100_SHIFT,4,4
	.comm	ANA_LONG_CABLE_TH_100_MASK,4,4
	.comm	ANA_INTERVAL_SEL_TIMER_SHIFT,4,4
	.comm	ANA_INTERVAL_SEL_TIMER_MASK,4,4
	.comm	ANA_IECHO_ADJ_3_SHIFT,4,4
	.comm	ANA_IECHO_ADJ_3_MASK,4,4
	.comm	ANA_IECHO_ADJ_2_SHIFT,4,4
	.comm	ANA_IECHO_ADJ_2_MASK,4,4
	.comm	ANA_IECHO_ADJ_1_SHIFT,4,4
	.comm	ANA_IECHO_ADJ_1_MASK,4,4
	.comm	ANA_IECHO_ADJ_0_SHIFT,4,4
	.comm	ANA_IECHO_ADJ_0_MASK,4,4
	.comm	ANA_EN_MASK_TB,4,4
	.comm	ANA_EN_HB,4,4
	.comm	ANA_EN_10BT_IDLE,4,4
	.comm	ANA_BP_SMALL_BW,4,4
	.comm	ANA_BP_BAD_LINK_ACCUM,4,4
	.comm	ALC_MII_DBG_DATA,4,4
	.comm	ALC_MII_DBG_ADDR,4,4
	.comm	ALC_GPHY_CFG,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_if_alc.c_alc_phy_reset_813x.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	alc_phy_reset_813x, %function
alc_phy_reset_813x:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	mov	r4, r0
	ldr	r5, .L12
	ldr	r6, .L12+4
	ldr	r1, [r5]
	ldr	r2, [r6]
	bl	CSR_WRITE_2
	ldr	r1, [r5]
	mov	r0, r4
	bl	CSR_READ_2
	ldr	r0, .L12+8
	bl	DELAY
	ldr	r2, .L12+12
	ldr	r3, [r6]
	ldr	r2, [r2]
	ldr	r1, [r5]
	orr	r2, r2, r3
	mov	r0, r4
	bl	CSR_WRITE_2
	ldr	r1, [r5]
	mov	r0, r4
	bl	CSR_READ_2
	ldr	r0, .L12+8
	bl	DELAY
	ldr	r8, .L12+16
	ldr	r3, [r4, #8]
	ldr	r2, [r8]
	ldr	r3, [r3]
	ldr	r7, .L12+20
	cmp	r3, r2
	ldr	r5, .L12+24
	beq	.L8
.L2:
	ldr	r6, .L12+28
	ldr	r2, [r6]
	cmp	r2, r3
	beq	.L3
	ldr	r2, .L12+32
	ldr	r2, [r2]
	cmp	r2, r3
	beq	.L3
	ldr	r2, [r8]
	cmp	r2, r3
	beq	.L3
	ldr	r2, .L12+36
	ldr	r2, [r2]
	cmp	r2, r3
	bne	.L4
.L3:
	mov	r3, #59
	ldr	r2, [r7]
	ldr	r1, [r4]
	ldr	r0, [r4, #4]
	bl	alc_miibus_writereg
	ldr	r2, [r5]
	ldr	r1, [r4]
	ldr	r0, [r4, #4]
	bl	alc_miibus_readreg
	ldr	r3, .L12+40
	ldr	r2, [r5]
	and	r3, r3, r0
	ldr	r1, [r4]
	ldr	r0, [r4, #4]
	bl	alc_miibus_writereg
	ldr	r0, .L12+44
	bl	DELAY
	ldr	r3, [r4, #8]
	ldr	r2, [r6]
	ldr	r3, [r3]
	cmp	r3, r2
	beq	.L11
.L4:
	ldr	r2, .L12+48
	ldr	r2, [r2]
	cmp	r2, r3
	beq	.L5
	ldr	r2, .L12+52
	ldr	r2, [r2]
	cmp	r2, r3
	beq	.L5
	ldr	r2, .L12+32
	ldr	r2, [r2]
	cmp	r2, r3
	beq	.L5
	ldr	r2, .L12+36
	ldr	r2, [r2]
	cmp	r2, r3
	bne	.L6
.L5:
	mov	r3, #41
	ldr	r2, [r7]
	ldr	r1, [r4]
	ldr	r0, [r4, #4]
	bl	alc_miibus_writereg
	ldr	r3, .L12+56
	ldr	r2, [r5]
	ldr	r1, [r4]
	ldr	r0, [r4, #4]
	bl	alc_miibus_writereg
.L6:
	mov	r0, #1
	ldr	lr, .L12+60
	ldr	r2, .L12+64
	ldr	ip, .L12+68
	ldr	r1, .L12+72
	ldr	r3, .L12+76
	ldr	r6, [lr]
	ldr	r2, [r2]
	ldr	ip, [ip]
	ldr	r1, [r1]
	ldr	r3, [r3]
	orr	r6, r6, r2
	ldr	r2, .L12+80
	orr	r6, r6, ip
	and	r3, r3, r0, lsl r1
	orr	r6, r6, r3
	ldr	r1, [r4]
	ldr	r3, [r2]
	ldr	r0, [r4, #4]
	ldr	r2, [r7]
	bl	alc_miibus_writereg
	mov	r3, r6
	ldr	r2, [r5]
	ldr	r1, [r4]
	ldr	r0, [r4, #4]
	bl	alc_miibus_writereg
	mov	r0, #2
	ldr	r1, .L12+84
	ldr	r3, .L12+88
	ldr	r2, .L12+92
	ldr	lr, [r3]
	ldr	r6, [r1]
	ldr	ip, .L12+96
	ldr	r1, .L12+100
	ldr	r3, .L12+104
	ldr	r2, [r2]
	ldr	ip, [ip]
	orr	r6, r6, lr
	ldr	r1, [r1]
	ldr	r3, [r3]
	orr	r6, r6, r2
	ldr	r2, .L12+108
	orr	r6, r6, ip
	and	r3, r3, r0, lsl r1
	orr	r6, r6, r3
	ldr	r1, [r4]
	ldr	r3, [r2]
	ldr	r0, [r4, #4]
	ldr	r2, [r7]
	bl	alc_miibus_writereg
	mov	r3, r6
	ldr	r2, [r5]
	ldr	r1, [r4]
	ldr	r0, [r4, #4]
	bl	alc_miibus_writereg
	mov	lr, #44
	mov	r0, #33
	ldr	ip, .L12+112
	ldr	r6, .L12+116
	ldr	r2, .L12+120
	ldr	r1, .L12+124
	ldr	r3, .L12+128
	ldr	ip, [ip]
	ldr	r1, [r1]
	ldr	r6, [r6]
	ldr	r2, [r2]
	ldr	r3, [r3]
	and	r6, r6, lr, lsl ip
	orr	r2, r2, r1
	ldr	r1, .L12+132
	mov	r8, #11
	and	r3, r3, r0, lsl r3
	orr	r6, r6, r2
	orr	r6, r6, r3
	ldr	r2, [r7]
	ldr	r3, [r1]
	ldr	r0, [r4, #4]
	ldr	r1, [r4]
	bl	alc_miibus_writereg
	mov	r3, r6
	ldr	r2, [r5]
	ldr	r1, [r4]
	ldr	r0, [r4, #4]
	bl	alc_miibus_writereg
	mov	r0, #8
	ldr	r1, .L12+136
	ldr	r2, .L12+140
	ldr	ip, .L12+144
	ldr	r3, .L12+148
	ldr	ip, [ip]
	ldr	r6, [r1]
	ldr	r3, [r3]
	ldr	r1, [r2]
	ldr	lr, .L12+152
	ldr	r2, .L12+156
	and	r1, r1, r8, lsl r3
	and	r6, r6, r8, lsl ip
	ldr	r3, .L12+160
	ldr	ip, .L12+164
	ldr	lr, [lr]
	ldr	r2, [r2]
	ldr	ip, [ip]
	ldr	r3, [r3]
	and	r2, r2, r0, lsl lr
	orr	r6, r6, r1
	ldr	r1, .L12+168
	and	r3, r3, r0, lsl ip
	orr	r6, r6, r2
	orr	r6, r6, r3
	ldr	r2, [r7]
	ldr	r3, [r1]
	ldr	r0, [r4, #4]
	ldr	r1, [r4]
	bl	alc_miibus_writereg
	mov	r3, r6
	ldr	r2, [r5]
	ldr	r1, [r4]
	ldr	r0, [r4, #4]
	bl	alc_miibus_writereg
	ldr	r2, .L12+172
	ldr	r3, .L12+176
	ldr	r6, [r2]
	ldr	r1, [r3]
	ldr	ip, .L12+180
	ldr	r0, .L12+184
	ldr	r3, .L12+188
	ldr	r2, .L12+192
	ldr	ip, [ip]
	orr	r6, r6, r1
	ldr	r1, .L12+196
	ldr	r0, [r0]
	ldr	r2, [r2]
	ldr	r3, [r3]
	orr	r6, r6, ip
	ldr	r1, [r1]
	orr	r6, r6, r0
	and	r3, r3, r2
	ldr	r2, .L12+200
	orr	r6, r6, r1
	and	r3, r3, #7
	ldr	r1, [r4]
	orr	r6, r6, r3
	ldr	r0, [r4, #4]
	ldr	r3, [r2]
	ldr	r2, [r7]
	bl	alc_miibus_writereg
	mov	r3, r6
	ldr	r2, [r5]
	ldr	r1, [r4]
	ldr	r0, [r4, #4]
	bl	alc_miibus_writereg
	mov	r0, #1000
	bl	DELAY
	mov	r3, #41
	ldr	r2, [r7]
	ldr	r1, [r4]
	ldr	r0, [r4, #4]
	bl	alc_miibus_writereg
	ldr	r2, [r5]
	ldr	r1, [r4]
	ldr	r0, [r4, #4]
	bl	alc_miibus_readreg
	ldr	r2, [r5]
	ldr	r1, [r4]
	bic	r3, r0, #32768
	ldr	r0, [r4, #4]
	bl	alc_miibus_writereg
	mov	r3, r8
	ldr	r2, [r7]
	ldr	r1, [r4]
	ldr	r0, [r4, #4]
	bl	alc_miibus_writereg
	ldr	r2, [r5]
	ldr	r1, [r4]
	ldr	r0, [r4, #4]
	bl	alc_miibus_readreg
	ldr	r2, [r5]
	ldr	r1, [r4]
	bic	r3, r0, #32768
	ldr	r0, [r4, #4]
	pop	{r4, r5, r6, r7, r8, lr}
	b	alc_miibus_writereg
.L11:
	mov	r3, #41
	ldr	r2, [r7]
	ldr	r1, [r4]
	ldr	r0, [r4, #4]
	bl	alc_miibus_writereg
	ldr	r3, .L12+204
	ldr	r2, [r5]
	ldr	r1, [r4]
	ldr	r0, [r4, #4]
	bl	alc_miibus_writereg
	ldr	r3, [r4, #8]
	ldr	r3, [r3]
	b	.L4
.L8:
	mov	r3, #10
	ldr	r2, [r7]
	ldr	r1, [r4]
	ldr	r0, [r4, #4]
	bl	alc_miibus_writereg
	ldr	r2, [r5]
	ldr	r1, [r4]
	ldr	r0, [r4, #4]
	bl	alc_miibus_readreg
	ldr	r3, .L12+208
	ldr	r2, [r5]
	and	r3, r3, r0
	ldr	r1, [r4]
	ldr	r0, [r4, #4]
	bl	alc_miibus_writereg
	ldr	r3, [r4, #8]
	ldr	r3, [r3]
	b	.L2
.L13:
	.align	2
.L12:
	.word	ALC_GPHY_CFG
	.word	GPHY_CFG_SEL_ANA_RESET
	.word	10000
	.word	GPHY_CFG_EXT_RESET
	.word	DEVICEID_ATHEROS_AR8152_B
	.word	ALC_MII_DBG_ADDR
	.word	ALC_MII_DBG_DATA
	.word	DEVICEID_ATHEROS_AR8151
	.word	DEVICEID_ATHEROS_AR8151_V2
	.word	DEVICEID_ATHEROS_AR8152_B2
	.word	65527
	.word	20000
	.word	DEVICEID_ATHEROS_AR8131
	.word	DEVICEID_ATHEROS_AR8132
	.word	46813
	.word	ANA_LOOP_SEL_10BT
	.word	ANA_EN_MASK_TB
	.word	ANA_EN_10BT_IDLE
	.word	ANA_INTERVAL_SEL_TIMER_SHIFT
	.word	ANA_INTERVAL_SEL_TIMER_MASK
	.word	MII_ANA_CFG18
	.word	ANA_SERDES_EN_DEEM
	.word	ANA_SERDES_SEL_HSP
	.word	ANA_SERDES_EN_PLL
	.word	ANA_SERDES_EN_LCKDT
	.word	ANA_SERDES_CDR_BW_SHIFT
	.word	ANA_SERDES_CDR_BW_MASK
	.word	MII_ANA_CFG5
	.word	ANA_LONG_CABLE_TH_100_SHIFT
	.word	ANA_LONG_CABLE_TH_100_MASK
	.word	ANA_BP_BAD_LINK_ACCUM
	.word	ANA_BP_SMALL_BW
	.word	ANA_SHORT_CABLE_TH_100_SHIFT
	.word	MII_ANA_CFG54
	.word	ANA_IECHO_ADJ_3_MASK
	.word	ANA_IECHO_ADJ_2_MASK
	.word	ANA_IECHO_ADJ_3_SHIFT
	.word	ANA_IECHO_ADJ_2_SHIFT
	.word	ANA_IECHO_ADJ_1_SHIFT
	.word	ANA_IECHO_ADJ_1_MASK
	.word	ANA_IECHO_ADJ_0_MASK
	.word	ANA_IECHO_ADJ_0_SHIFT
	.word	MII_ANA_CFG4
	.word	ANA_RESTART_CAL
	.word	ANA_MAN_ENABLE
	.word	ANA_SEL_HSP
	.word	ANA_EN_HB
	.word	ANA_MANUL_SWICH_ON_SHIFT
	.word	ANA_MANUL_SWICH_ON_MASK
	.word	ANA_OEN_125M
	.word	MII_ANA_CFG0
	.word	37533
	.word	57343
	.size	alc_phy_reset_813x, .-alc_phy_reset_813x
	.comm	MII_ANA_CFG54,4,4
	.comm	MII_ANA_CFG5,4,4
	.comm	MII_ANA_CFG4,4,4
	.comm	MII_ANA_CFG18,4,4
	.comm	MII_ANA_CFG0,4,4
	.comm	GPHY_CFG_SEL_ANA_RESET,4,4
	.comm	GPHY_CFG_EXT_RESET,4,4
	.comm	DEVICEID_ATHEROS_AR8152_B2,4,4
	.comm	DEVICEID_ATHEROS_AR8152_B,4,4
	.comm	DEVICEID_ATHEROS_AR8151_V2,4,4
	.comm	DEVICEID_ATHEROS_AR8151,4,4
	.comm	DEVICEID_ATHEROS_AR8132,4,4
	.comm	DEVICEID_ATHEROS_AR8131,4,4
	.comm	ANA_SHORT_CABLE_TH_100_SHIFT,4,4
	.comm	ANA_SERDES_SEL_HSP,4,4
	.comm	ANA_SERDES_EN_PLL,4,4
	.comm	ANA_SERDES_EN_LCKDT,4,4
	.comm	ANA_SERDES_EN_DEEM,4,4
	.comm	ANA_SERDES_CDR_BW_SHIFT,4,4
	.comm	ANA_SERDES_CDR_BW_MASK,4,4
	.comm	ANA_SEL_HSP,4,4
	.comm	ANA_RESTART_CAL,4,4
	.comm	ANA_OEN_125M,4,4
	.comm	ANA_MAN_ENABLE,4,4
	.comm	ANA_MANUL_SWICH_ON_SHIFT,4,4
	.comm	ANA_MANUL_SWICH_ON_MASK,4,4
	.comm	ANA_LOOP_SEL_10BT,4,4
	.comm	ANA_LONG_CABLE_TH_100_SHIFT,4,4
	.comm	ANA_LONG_CABLE_TH_100_MASK,4,4
	.comm	ANA_INTERVAL_SEL_TIMER_SHIFT,4,4
	.comm	ANA_INTERVAL_SEL_TIMER_MASK,4,4
	.comm	ANA_IECHO_ADJ_3_SHIFT,4,4
	.comm	ANA_IECHO_ADJ_3_MASK,4,4
	.comm	ANA_IECHO_ADJ_2_SHIFT,4,4
	.comm	ANA_IECHO_ADJ_2_MASK,4,4
	.comm	ANA_IECHO_ADJ_1_SHIFT,4,4
	.comm	ANA_IECHO_ADJ_1_MASK,4,4
	.comm	ANA_IECHO_ADJ_0_SHIFT,4,4
	.comm	ANA_IECHO_ADJ_0_MASK,4,4
	.comm	ANA_EN_MASK_TB,4,4
	.comm	ANA_EN_HB,4,4
	.comm	ANA_EN_10BT_IDLE,4,4
	.comm	ANA_BP_SMALL_BW,4,4
	.comm	ANA_BP_BAD_LINK_ACCUM,4,4
	.comm	ALC_MII_DBG_DATA,4,4
	.comm	ALC_MII_DBG_ADDR,4,4
	.comm	ALC_GPHY_CFG,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
