	.file	"extr_al_hal_eth_main.c_al_eth_eee_config.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"[%s]: config eee.\n"
.LC1:
	.string	"[%s]: disable eee.\n"
	.text
	.p2align 4
	.globl	al_eth_eee_config
	.type	al_eth_eee_config, @function
al_eth_eee_config:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsi
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	mov	rbx, rdi
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	mov	esi, DWORD PTR 24[rdi]
	lea	rdi, .LC0[rip]
	call	al_dbg@PLT
	cmp	QWORD PTR 0[rbp], 0
	je	.L16
	mov	rdi, QWORD PTR [rbx]
	call	AL_ETH_IS_10G_MAC@PLT
	test	rax, rax
	je	.L4
.L7:
	mov	rdi, QWORD PTR [rbx]
	call	AL_ETH_IS_10G_MAC@PLT
	mov	edx, DWORD PTR ETH_MAC_KR_25_PCS_CFG_EEE_TIMER_VAL[rip]
	mov	ecx, DWORD PTR ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_SHIFT[rip]
	test	rax, rax
	mov	rax, QWORD PTR 16[rbx]
	cmovne	edx, DWORD PTR ETH_MAC_KR_10_PCS_CFG_EEE_TIMER_VAL[rip]
	mov	esi, DWORD PTR ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_MASK[rip]
	sal	edx, cl
	lea	rdi, 4[rax]
	call	al_reg_write32_masked@PLT
	mov	rax, QWORD PTR [rbx]
	cmp	rax, QWORD PTR AL_ETH_MAC_MODE_XLG_LL_40G[rip]
	je	.L10
.L18:
	cmp	rax, QWORD PTR AL_ETH_MAC_MODE_XLG_LL_50G[rip]
	je	.L17
.L12:
	mov	rax, QWORD PTR 8[rbx]
	mov	esi, DWORD PTR 8[rbp]
	lea	rdi, 12[rax]
	call	al_reg_write32@PLT
	mov	rax, QWORD PTR 8[rbx]
	mov	esi, DWORD PTR 12[rbp]
	lea	rdi, 8[rax]
	call	al_reg_write32@PLT
	mov	rax, QWORD PTR 8[rbx]
	mov	esi, DWORD PTR 16[rbp]
	lea	rdi, 4[rax]
	call	al_reg_write32@PLT
	mov	rdi, QWORD PTR 8[rbx]
	mov	esi, DWORD PTR EC_EEE_CFG_E_MASK_EC_TMI_STOP[rip]
	or	esi, DWORD PTR EC_EEE_CFG_E_MASK_MAC_EEE[rip]
	or	esi, DWORD PTR EC_EEE_CFG_E_ENABLE[rip]
	or	esi, DWORD PTR EC_EEE_CFG_E_USE_EC_TX_FIFO[rip]
	or	esi, DWORD PTR EC_EEE_CFG_E_USE_EC_RX_FIFO[rip]
	call	al_reg_write32@PLT
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	xor	eax, eax
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L4:
	.cfi_restore_state
	mov	rdi, QWORD PTR [rbx]
	call	AL_ETH_IS_25G_MAC@PLT
	test	rax, rax
	jne	.L7
	mov	rax, QWORD PTR [rbx]
	cmp	rax, QWORD PTR AL_ETH_MAC_MODE_XLG_LL_40G[rip]
	jne	.L18
.L10:
	mov	edx, DWORD PTR ETH_MAC_XLG_40_PCS_CFG_EEE_TIMER_VAL[rip]
	jmp	.L13
	.p2align 4,,10
	.p2align 3
.L16:
	mov	esi, DWORD PTR 24[rbx]
	lea	rdi, .LC1[rip]
	call	al_dbg@PLT
	mov	rdi, QWORD PTR 8[rbx]
	xor	esi, esi
	call	al_reg_write32@PLT
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	xor	eax, eax
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L17:
	.cfi_restore_state
	mov	edx, DWORD PTR ETH_MAC_XLG_50_PCS_CFG_EEE_TIMER_VAL[rip]
.L13:
	mov	ecx, DWORD PTR ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_SHIFT[rip]
	mov	rdi, QWORD PTR 16[rbx]
	mov	esi, DWORD PTR ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_MASK[rip]
	sal	edx, cl
	call	al_reg_write32_masked@PLT
	xor	edx, edx
	mov	esi, DWORD PTR ETH_MAC_GEN_V3_PCS_40G_EEE_CONTROL_ADDR[rip]
	mov	rdi, rbx
	cmp	QWORD PTR 24[rbp], 0
	setne	dl
	call	al_eth_40g_pcs_reg_write@PLT
	jmp	.L12
	.cfi_endproc
.LFE0:
	.size	al_eth_eee_config, .-al_eth_eee_config
	.comm	ETH_MAC_XLG_50_PCS_CFG_EEE_TIMER_VAL,4,4
	.comm	ETH_MAC_XLG_40_PCS_CFG_EEE_TIMER_VAL,4,4
	.comm	ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_SHIFT,4,4
	.comm	ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_MASK,4,4
	.comm	ETH_MAC_KR_25_PCS_CFG_EEE_TIMER_VAL,4,4
	.comm	ETH_MAC_KR_10_PCS_CFG_EEE_TIMER_VAL,4,4
	.comm	ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_SHIFT,4,4
	.comm	ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_MASK,4,4
	.comm	ETH_MAC_GEN_V3_PCS_40G_EEE_CONTROL_ADDR,4,4
	.comm	EC_EEE_CFG_E_USE_EC_TX_FIFO,4,4
	.comm	EC_EEE_CFG_E_USE_EC_RX_FIFO,4,4
	.comm	EC_EEE_CFG_E_MASK_MAC_EEE,4,4
	.comm	EC_EEE_CFG_E_MASK_EC_TMI_STOP,4,4
	.comm	EC_EEE_CFG_E_ENABLE,4,4
	.comm	AL_ETH_MAC_MODE_XLG_LL_50G,8,8
	.comm	AL_ETH_MAC_MODE_XLG_LL_40G,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_al_hal_eth_main.c_al_eth_eee_config.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"[%s]: config eee.\012\000"
	.align	2
.LC1:
	.ascii	"[%s]: disable eee.\012\000"
	.text
	.align	2
	.global	al_eth_eee_config
	.syntax unified
	.arm
	.fpu softvfp
	.type	al_eth_eee_config, %function
al_eth_eee_config:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	mov	r5, r1
	mov	r4, r0
	ldr	r1, [r0, #12]
	ldr	r0, .L21
	bl	al_dbg
	ldr	r6, [r5]
	cmp	r6, #0
	beq	.L18
	ldr	r0, [r4]
	bl	AL_ETH_IS_10G_MAC
	cmp	r0, #0
	beq	.L4
.L7:
	ldr	r3, .L21+4
	ldr	r0, [r4]
	ldr	r6, [r4, #8]
	ldr	r7, [r3]
	bl	AL_ETH_IS_10G_MAC
	cmp	r0, #0
	add	r6, r6, #4
	beq	.L19
	ldr	r3, .L21+8
	ldr	r2, [r3]
.L9:
	ldr	r3, .L21+12
	mov	r1, r7
	ldr	r3, [r3]
	mov	r0, r6
	lsl	r2, r2, r3
	bl	al_reg_write32_masked
.L8:
	ldr	r2, .L21+16
	ldr	r3, [r4]
	ldr	r2, [r2]
	cmp	r3, r2
	beq	.L10
	ldr	r2, .L21+20
	ldr	r2, [r2]
	cmp	r3, r2
	beq	.L20
.L12:
	ldr	r0, [r4, #4]
	ldr	r1, [r5, #4]
	add	r0, r0, #12
	bl	al_reg_write32
	ldr	r0, [r4, #4]
	ldr	r1, [r5, #8]
	add	r0, r0, #8
	bl	al_reg_write32
	ldr	r0, [r4, #4]
	ldr	r1, [r5, #12]
	add	r0, r0, #4
	bl	al_reg_write32
	ldr	r2, .L21+24
	ldr	r3, .L21+28
	ldr	r1, .L21+32
	ldr	ip, [r2]
	ldr	r3, [r3]
	ldr	r2, .L21+36
	ldr	r1, [r1]
	ldr	r0, .L21+40
	ldr	r2, [r2]
	orr	r3, r3, ip
	orr	r3, r3, r1
	ldr	r1, [r0]
	orr	r3, r3, r2
	ldr	r0, [r4, #4]
	orr	r1, r3, r1
	bl	al_reg_write32
	mov	r0, #0
	pop	{r4, r5, r6, r7, r8, pc}
.L4:
	ldr	r0, [r4]
	bl	AL_ETH_IS_25G_MAC
	cmp	r0, #0
	bne	.L7
	b	.L8
.L18:
	ldr	r1, [r4, #12]
	ldr	r0, .L21+44
	bl	al_dbg
	mov	r1, r6
	ldr	r0, [r4, #4]
	bl	al_reg_write32
	mov	r0, #0
	pop	{r4, r5, r6, r7, r8, pc}
.L19:
	ldr	r3, .L21+48
	ldr	r2, [r3]
	b	.L9
.L20:
	ldr	r2, .L21+52
	ldr	r3, .L21+56
	ldr	r1, [r2]
	ldr	r0, [r4, #8]
	ldr	r2, [r3]
.L13:
	ldr	r3, .L21+60
	ldr	r3, [r3]
	lsl	r2, r2, r3
	bl	al_reg_write32_masked
	ldr	r2, [r5, #16]
	ldr	r3, .L21+64
	subs	r2, r2, #0
	movne	r2, #1
	mov	r0, r4
	ldr	r1, [r3]
	bl	al_eth_40g_pcs_reg_write
	b	.L12
.L10:
	ldr	r2, .L21+52
	ldr	r3, .L21+68
	ldr	r1, [r2]
	ldr	r0, [r4, #8]
	ldr	r2, [r3]
	b	.L13
.L22:
	.align	2
.L21:
	.word	.LC0
	.word	ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_MASK
	.word	ETH_MAC_KR_10_PCS_CFG_EEE_TIMER_VAL
	.word	ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_SHIFT
	.word	AL_ETH_MAC_MODE_XLG_LL_40G
	.word	AL_ETH_MAC_MODE_XLG_LL_50G
	.word	EC_EEE_CFG_E_MASK_MAC_EEE
	.word	EC_EEE_CFG_E_MASK_EC_TMI_STOP
	.word	EC_EEE_CFG_E_ENABLE
	.word	EC_EEE_CFG_E_USE_EC_TX_FIFO
	.word	EC_EEE_CFG_E_USE_EC_RX_FIFO
	.word	.LC1
	.word	ETH_MAC_KR_25_PCS_CFG_EEE_TIMER_VAL
	.word	ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_MASK
	.word	ETH_MAC_XLG_50_PCS_CFG_EEE_TIMER_VAL
	.word	ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_SHIFT
	.word	ETH_MAC_GEN_V3_PCS_40G_EEE_CONTROL_ADDR
	.word	ETH_MAC_XLG_40_PCS_CFG_EEE_TIMER_VAL
	.size	al_eth_eee_config, .-al_eth_eee_config
	.comm	ETH_MAC_XLG_50_PCS_CFG_EEE_TIMER_VAL,4,4
	.comm	ETH_MAC_XLG_40_PCS_CFG_EEE_TIMER_VAL,4,4
	.comm	ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_SHIFT,4,4
	.comm	ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_MASK,4,4
	.comm	ETH_MAC_KR_25_PCS_CFG_EEE_TIMER_VAL,4,4
	.comm	ETH_MAC_KR_10_PCS_CFG_EEE_TIMER_VAL,4,4
	.comm	ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_SHIFT,4,4
	.comm	ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_MASK,4,4
	.comm	ETH_MAC_GEN_V3_PCS_40G_EEE_CONTROL_ADDR,4,4
	.comm	EC_EEE_CFG_E_USE_EC_TX_FIFO,4,4
	.comm	EC_EEE_CFG_E_USE_EC_RX_FIFO,4,4
	.comm	EC_EEE_CFG_E_MASK_MAC_EEE,4,4
	.comm	EC_EEE_CFG_E_MASK_EC_TMI_STOP,4,4
	.comm	EC_EEE_CFG_E_ENABLE,4,4
	.comm	AL_ETH_MAC_MODE_XLG_LL_50G,4,4
	.comm	AL_ETH_MAC_MODE_XLG_LL_40G,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
