	.file	"extr_intel_display.c_ironlake_get_pipe_config.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	ironlake_get_pipe_config, @function
ironlake_get_pipe_config:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	mov	r12, rdi
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rsi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 8
	.cfi_def_cfa_offset 64
	mov	rdi, QWORD PTR 8[rdi]
	call	to_i915@PLT
	mov	rdi, QWORD PTR [r12]
	mov	r14, rax
	call	POWER_DOMAIN_PIPE@PLT
	mov	rdi, r14
	mov	esi, eax
	mov	r15d, eax
	call	intel_display_power_get_if_enabled@PLT
	mov	r13d, eax
	test	eax, eax
	jne	.L27
.L1:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	eax, r13d
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L27:
	.cfi_restore_state
	mov	rdi, QWORD PTR [r12]
	mov	eax, DWORD PTR INTEL_OUTPUT_FORMAT_RGB[rip]
	mov	QWORD PTR 40[rbp], 0
	mov	DWORD PTR 0[rbp], edi
	mov	DWORD PTR 48[rbp], eax
	call	PIPECONF@PLT
	mov	edi, eax
	call	I915_READ@PLT
	mov	ebx, eax
	and	ebx, DWORD PTR PIPECONF_ENABLE[rip]
	je	.L3
	mov	edx, DWORD PTR PIPECONF_BPC_MASK[rip]
	and	edx, eax
	cmp	edx, 130
	je	.L4
	jg	.L5
	cmp	edx, 128
	je	.L6
	cmp	edx, 129
	jne	.L8
	mov	DWORD PTR 4[rbp], 18
	.p2align 4,,10
	.p2align 3
.L8:
	test	DWORD PTR PIPECONF_COLOR_RANGE_SELECT[rip], eax
	jne	.L28
.L10:
	mov	ecx, DWORD PTR PIPECONF_GAMMA_MODE_SHIFT[rip]
	and	eax, DWORD PTR PIPECONF_GAMMA_MODE_MASK_ILK[rip]
	mov	rdi, QWORD PTR [r12]
	sar	eax, cl
	mov	DWORD PTR 12[rbp], eax
	call	PIPE_CSC_MODE@PLT
	mov	edi, eax
	call	I915_READ@PLT
	mov	rdi, rbp
	mov	DWORD PTR 16[rbp], eax
	call	i9xx_get_pipe_color_config@PLT
	mov	rdi, rbp
	call	intel_color_get_config@PLT
	mov	rdi, QWORD PTR [r12]
	call	PCH_TRANSCONF@PLT
	mov	edi, eax
	call	I915_READ@PLT
	test	DWORD PTR TRANS_ENABLE[rip], eax
	jne	.L29
	mov	DWORD PTR 28[rbp], 1
.L15:
	mov	rsi, rbp
	mov	rdi, r12
	mov	ebx, 1
	call	intel_get_pipe_timings@PLT
	mov	rsi, rbp
	mov	rdi, r12
	call	intel_get_pipe_src_size@PLT
	mov	rsi, rbp
	mov	rdi, r12
	call	ironlake_get_pfit_config@PLT
.L3:
	mov	edx, r13d
	mov	esi, r15d
	mov	rdi, r14
	mov	r13d, ebx
	call	intel_display_power_put@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L5:
	cmp	edx, 131
	jne	.L8
	mov	DWORD PTR 4[rbp], 30
	jmp	.L8
	.p2align 4,,10
	.p2align 3
.L28:
	mov	DWORD PTR 8[rbp], 1
	jmp	.L10
	.p2align 4,,10
	.p2align 3
.L6:
	mov	DWORD PTR 4[rbp], 24
	jmp	.L8
	.p2align 4,,10
	.p2align 3
.L29:
	mov	DWORD PTR 20[rbp], 1
	mov	rdi, QWORD PTR [r12]
	call	FDI_RX_CTL@PLT
	mov	edi, eax
	call	I915_READ@PLT
	mov	ecx, DWORD PTR FDI_DP_PORT_WIDTH_SHIFT[rip]
	mov	rdi, r12
	mov	rsi, rbp
	and	eax, DWORD PTR FDI_DP_PORT_WIDTH_MASK[rip]
	sar	eax, cl
	add	eax, 1
	mov	DWORD PTR 24[rbp], eax
	call	ironlake_get_fdi_m_n_config@PLT
	mov	rdi, r14
	call	HAS_PCH_IBX@PLT
	test	rax, rax
	je	.L12
	mov	esi, DWORD PTR [r12]
.L13:
	mov	rdi, r14
	call	intel_get_shared_dpll_by_id@PLT
	lea	rdx, 32[rbp]
	mov	rdi, r14
	mov	rsi, rax
	mov	QWORD PTR 40[rbp], rax
	mov	rax, QWORD PTR [rax]
	mov	rax, QWORD PTR [rax]
	call	[QWORD PTR [rax]]
	xor	edi, edi
	test	eax, eax
	sete	dil
	call	WARN_ON@PLT
	mov	ecx, DWORD PTR PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT[rip]
	mov	rsi, rbp
	mov	rdi, r12
	mov	eax, DWORD PTR PLL_REF_SDVO_HDMI_MULTIPLIER_MASK[rip]
	and	eax, DWORD PTR 32[rbp]
	sar	eax, cl
	add	eax, 1
	mov	DWORD PTR 28[rbp], eax
	call	ironlake_pch_clock_get@PLT
	jmp	.L15
	.p2align 4,,10
	.p2align 3
.L4:
	mov	DWORD PTR 4[rbp], 36
	jmp	.L8
	.p2align 4,,10
	.p2align 3
.L12:
	mov	edi, DWORD PTR PCH_DPLL_SEL[rip]
	call	I915_READ@PLT
	mov	rdi, QWORD PTR [r12]
	mov	ebx, eax
	call	TRANS_DPLLB_SEL@PLT
	mov	esi, DWORD PTR DPLL_ID_PCH_PLL_B[rip]
	test	eax, ebx
	cmove	esi, DWORD PTR DPLL_ID_PCH_PLL_A[rip]
	jmp	.L13
	.cfi_endproc
.LFE0:
	.size	ironlake_get_pipe_config, .-ironlake_get_pipe_config
	.comm	TRANS_ENABLE,4,4
	.comm	PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT,4,4
	.comm	PLL_REF_SDVO_HDMI_MULTIPLIER_MASK,4,4
	.comm	PIPECONF_GAMMA_MODE_SHIFT,4,4
	.comm	PIPECONF_GAMMA_MODE_MASK_ILK,4,4
	.comm	PIPECONF_ENABLE,4,4
	.comm	PIPECONF_COLOR_RANGE_SELECT,4,4
	.comm	PIPECONF_BPC_MASK,4,4
	.comm	PCH_DPLL_SEL,4,4
	.comm	INTEL_OUTPUT_FORMAT_RGB,4,4
	.comm	FDI_DP_PORT_WIDTH_SHIFT,4,4
	.comm	FDI_DP_PORT_WIDTH_MASK,4,4
	.comm	DPLL_ID_PCH_PLL_B,4,4
	.comm	DPLL_ID_PCH_PLL_A,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_intel_display.c_ironlake_get_pipe_config.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	ironlake_get_pipe_config, %function
ironlake_get_pipe_config:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, lr}
	mov	r5, r0
	ldr	r0, [r0, #4]
	mov	r4, r1
	bl	to_i915
	mov	r6, r0
	ldr	r0, [r5]
	bl	POWER_DOMAIN_PIPE
	mov	r7, r0
	mov	r0, r6
	mov	r1, r7
	bl	intel_display_power_get_if_enabled
	subs	r8, r0, #0
	bne	.L27
	mov	r0, r8
	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
.L27:
	mov	r2, #0
	ldr	r3, .L29
	ldr	r0, [r5]
	ldr	r3, [r3]
	str	r2, [r4, #36]
	str	r3, [r4, #40]
	str	r0, [r4]
	bl	PIPECONF
	bl	I915_READ
	ldr	r2, .L29+4
	mov	r3, r0
	ldr	r2, [r2]
	ands	r9, r0, r2
	beq	.L3
	ldr	r2, .L29+8
	ldr	r2, [r2]
	and	r2, r2, r0
	sub	r2, r2, #128
	cmp	r2, #3
	ldrls	pc, [pc, r2, asl #2]
	b	.L4
.L6:
	.word	.L9
	.word	.L8
	.word	.L7
	.word	.L5
.L8:
	mov	r2, #18
	str	r2, [r4, #4]
.L4:
	ldr	r2, .L29+12
	ldr	r1, .L29+16
	ldr	r2, [r2]
	ldr	r0, [r1]
	tst	r3, r2
	movne	r2, #1
	strne	r2, [r4, #8]
	ldr	r2, .L29+20
	and	r3, r3, r0
	ldr	r2, [r2]
	ldr	r0, [r5]
	asr	r3, r3, r2
	str	r3, [r4, #12]
	bl	PIPE_CSC_MODE
	bl	I915_READ
	mov	r3, r0
	mov	r0, r4
	str	r3, [r4, #16]
	bl	i9xx_get_pipe_color_config
	mov	r0, r4
	bl	intel_color_get_config
	ldr	r0, [r5]
	bl	PCH_TRANSCONF
	bl	I915_READ
	ldr	r3, .L29+24
	ldr	r3, [r3]
	tst	r0, r3
	mov	r3, #1
	streq	r3, [r4, #28]
	bne	.L28
.L15:
	mov	r1, r4
	mov	r0, r5
	bl	intel_get_pipe_timings
	mov	r1, r4
	mov	r0, r5
	bl	intel_get_pipe_src_size
	mov	r1, r4
	mov	r0, r5
	bl	ironlake_get_pfit_config
	mov	r9, #1
.L3:
	mov	r2, r8
	mov	r8, r9
	mov	r1, r7
	mov	r0, r6
	bl	intel_display_power_put
	mov	r0, r8
	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
.L5:
	mov	r2, #30
	str	r2, [r4, #4]
	b	.L4
.L7:
	mov	r2, #36
	str	r2, [r4, #4]
	b	.L4
.L9:
	mov	r2, #24
	str	r2, [r4, #4]
	b	.L4
.L28:
	ldr	r0, [r5]
	str	r3, [r4, #20]
	bl	FDI_RX_CTL
	bl	I915_READ
	ldr	r3, .L29+28
	ldr	r2, .L29+32
	ldr	r3, [r3]
	ldr	r2, [r2]
	and	r3, r3, r0
	asr	r3, r3, r2
	add	r3, r3, #1
	mov	r1, r4
	str	r3, [r4, #24]
	mov	r0, r5
	bl	ironlake_get_fdi_m_n_config
	mov	r0, r6
	bl	HAS_PCH_IBX
	cmp	r0, #0
	beq	.L12
	ldr	r1, [r5]
.L13:
	mov	r0, r6
	bl	intel_get_shared_dpll_by_id
	ldr	r3, [r0]
	mov	r1, r0
	ldr	r3, [r3]
	add	r2, r4, #32
	ldr	r3, [r3]
	str	r0, [r4, #36]
	mov	r0, r6
	blx	r3
	clz	r0, r0
	lsr	r0, r0, #5
	bl	WARN_ON
	ldr	r3, .L29+36
	ldr	r2, .L29+40
	ldr	r1, [r4, #32]
	ldr	r3, [r3]
	ldr	r2, [r2]
	and	r3, r3, r1
	asr	r3, r3, r2
	add	r3, r3, #1
	mov	r1, r4
	mov	r0, r5
	str	r3, [r4, #28]
	bl	ironlake_pch_clock_get
	b	.L15
.L12:
	ldr	r3, .L29+44
	ldr	r0, [r3]
	bl	I915_READ
	mov	r9, r0
	ldr	r0, [r5]
	bl	TRANS_DPLLB_SEL
	tst	r0, r9
	ldrne	r3, .L29+48
	ldreq	r3, .L29+52
	ldr	r1, [r3]
	b	.L13
.L30:
	.align	2
.L29:
	.word	INTEL_OUTPUT_FORMAT_RGB
	.word	PIPECONF_ENABLE
	.word	PIPECONF_BPC_MASK
	.word	PIPECONF_COLOR_RANGE_SELECT
	.word	PIPECONF_GAMMA_MODE_MASK_ILK
	.word	PIPECONF_GAMMA_MODE_SHIFT
	.word	TRANS_ENABLE
	.word	FDI_DP_PORT_WIDTH_MASK
	.word	FDI_DP_PORT_WIDTH_SHIFT
	.word	PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
	.word	PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
	.word	PCH_DPLL_SEL
	.word	DPLL_ID_PCH_PLL_B
	.word	DPLL_ID_PCH_PLL_A
	.size	ironlake_get_pipe_config, .-ironlake_get_pipe_config
	.comm	TRANS_ENABLE,4,4
	.comm	PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT,4,4
	.comm	PLL_REF_SDVO_HDMI_MULTIPLIER_MASK,4,4
	.comm	PIPECONF_GAMMA_MODE_SHIFT,4,4
	.comm	PIPECONF_GAMMA_MODE_MASK_ILK,4,4
	.comm	PIPECONF_ENABLE,4,4
	.comm	PIPECONF_COLOR_RANGE_SELECT,4,4
	.comm	PIPECONF_BPC_MASK,4,4
	.comm	PCH_DPLL_SEL,4,4
	.comm	INTEL_OUTPUT_FORMAT_RGB,4,4
	.comm	FDI_DP_PORT_WIDTH_SHIFT,4,4
	.comm	FDI_DP_PORT_WIDTH_MASK,4,4
	.comm	DPLL_ID_PCH_PLL_B,4,4
	.comm	DPLL_ID_PCH_PLL_A,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
