	.file	"extr_intel_gmbus.c_get_gmbus_pin.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	get_gmbus_pin, @function
get_gmbus_pin:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	mov	ebx, esi
	sal	rbx, 2
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	call	INTEL_PCH_TYPE@PLT
	cmp	rax, QWORD PTR PCH_ICP[rip]
	jl	.L2
	mov	rax, QWORD PTR gmbus_pins_icp[rip]
	add	rax, rbx
.L1:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L2:
	.cfi_restore_state
	mov	rdi, rbp
	call	HAS_PCH_CNP@PLT
	test	rax, rax
	je	.L4
	mov	rax, QWORD PTR gmbus_pins_cnp[rip]
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	add	rax, rbx
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L4:
	.cfi_restore_state
	mov	rdi, rbp
	call	IS_GEN9_LP@PLT
	test	rax, rax
	je	.L5
	mov	rax, QWORD PTR gmbus_pins_bxt[rip]
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	add	rax, rbx
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L5:
	.cfi_restore_state
	mov	rdi, rbp
	call	IS_GEN9_BC@PLT
	test	rax, rax
	je	.L6
	mov	rax, QWORD PTR gmbus_pins_skl[rip]
	add	rax, rbx
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L6:
	mov	rdi, rbp
	call	IS_BROADWELL@PLT
	test	rax, rax
	mov	rax, rbx
	je	.L7
	add	rax, QWORD PTR gmbus_pins_bdw[rip]
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L7:
	add	rax, QWORD PTR gmbus_pins[rip]
	jmp	.L1
	.cfi_endproc
.LFE0:
	.size	get_gmbus_pin, .-get_gmbus_pin
	.comm	gmbus_pins_skl,8,8
	.comm	gmbus_pins_icp,8,8
	.comm	gmbus_pins_cnp,8,8
	.comm	gmbus_pins_bxt,8,8
	.comm	gmbus_pins_bdw,8,8
	.comm	gmbus_pins,8,8
	.comm	PCH_ICP,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_intel_gmbus.c_get_gmbus_pin.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_gmbus_pin, %function
get_gmbus_pin:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, lr}
	mov	r4, r1
	mov	r5, r0
	bl	INTEL_PCH_TYPE
	ldr	r3, .L10
	lsl	r4, r4, #2
	ldr	r3, [r3]
	cmp	r0, r3
	blt	.L2
	ldr	r3, .L10+4
	ldr	r0, [r3]
	add	r0, r0, r4
	pop	{r4, r5, r6, pc}
.L2:
	mov	r0, r5
	bl	HAS_PCH_CNP
	cmp	r0, #0
	beq	.L4
	ldr	r3, .L10+8
	ldr	r0, [r3]
	add	r0, r0, r4
	pop	{r4, r5, r6, pc}
.L4:
	mov	r0, r5
	bl	IS_GEN9_LP
	cmp	r0, #0
	beq	.L5
	ldr	r3, .L10+12
	ldr	r0, [r3]
	add	r0, r0, r4
	pop	{r4, r5, r6, pc}
.L5:
	mov	r0, r5
	bl	IS_GEN9_BC
	cmp	r0, #0
	beq	.L6
	ldr	r3, .L10+16
	ldr	r0, [r3]
	add	r0, r0, r4
	pop	{r4, r5, r6, pc}
.L6:
	mov	r0, r5
	bl	IS_BROADWELL
	cmp	r0, #0
	ldrne	r3, .L10+20
	ldreq	r3, .L10+24
	ldr	r0, [r3]
	add	r0, r0, r4
	pop	{r4, r5, r6, pc}
.L11:
	.align	2
.L10:
	.word	PCH_ICP
	.word	gmbus_pins_icp
	.word	gmbus_pins_cnp
	.word	gmbus_pins_bxt
	.word	gmbus_pins_skl
	.word	gmbus_pins_bdw
	.word	gmbus_pins
	.size	get_gmbus_pin, .-get_gmbus_pin
	.comm	gmbus_pins_skl,4,4
	.comm	gmbus_pins_icp,4,4
	.comm	gmbus_pins_cnp,4,4
	.comm	gmbus_pins_bxt,4,4
	.comm	gmbus_pins_bdw,4,4
	.comm	gmbus_pins,4,4
	.comm	PCH_ICP,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
