	.file	"extr_r600_cp.c_r700_vm_init.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	r700_vm_init, @function
r700_vm_init:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	mov	r13, rdi
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	sub	rsp, 8
	.cfi_def_cfa_offset 48
	mov	r12, QWORD PTR [rdi]
	mov	rdi, QWORD PTR R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR[rip]
	mov	esi, DWORD PTR [r12]
	sar	esi, 12
	call	RADEON_WRITE@PLT
	mov	esi, DWORD PTR 4[r12]
	add	esi, DWORD PTR [r12]
	mov	rdi, QWORD PTR R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR[rip]
	sub	esi, 1
	sar	esi, 12
	call	RADEON_WRITE@PLT
	mov	rdi, QWORD PTR R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[rip]
	xor	esi, esi
	call	RADEON_WRITE@PLT
	mov	edi, 5
	mov	ebp, DWORD PTR R700_ENABLE_L1_TLB[rip]
	or	ebp, DWORD PTR R700_ENABLE_L1_FRAGMENT_PROCESSING[rip]
	or	ebp, DWORD PTR R700_SYSTEM_ACCESS_MODE_IN_SYS[rip]
	or	ebp, DWORD PTR R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU[rip]
	call	R700_EFFECTIVE_L1_TLB_SIZE@PLT
	mov	edi, 5
	or	ebp, eax
	call	R700_EFFECTIVE_L1_QUEUE_SIZE@PLT
	mov	rdi, QWORD PTR R700_MC_VM_MD_L1_TLB0_CNTL[rip]
	or	ebp, eax
	mov	esi, ebp
	call	RADEON_WRITE@PLT
	mov	rdi, QWORD PTR R700_MC_VM_MD_L1_TLB1_CNTL[rip]
	mov	esi, ebp
	call	RADEON_WRITE@PLT
	mov	rdi, QWORD PTR R700_MC_VM_MD_L1_TLB2_CNTL[rip]
	mov	esi, ebp
	call	RADEON_WRITE@PLT
	mov	rdi, QWORD PTR R700_MC_VM_MB_L1_TLB0_CNTL[rip]
	mov	esi, ebp
	call	RADEON_WRITE@PLT
	mov	rdi, QWORD PTR R700_MC_VM_MB_L1_TLB1_CNTL[rip]
	mov	esi, ebp
	call	RADEON_WRITE@PLT
	mov	rdi, QWORD PTR R700_MC_VM_MB_L1_TLB2_CNTL[rip]
	mov	esi, ebp
	call	RADEON_WRITE@PLT
	mov	rdi, QWORD PTR R700_MC_VM_MB_L1_TLB3_CNTL[rip]
	mov	esi, ebp
	call	RADEON_WRITE@PLT
	mov	edi, 7
	mov	ebx, DWORD PTR R600_VM_L2_CACHE_EN[rip]
	or	ebx, DWORD PTR R600_VM_L2_FRAG_PROC[rip]
	or	ebx, DWORD PTR R600_VM_ENABLE_PTE_CACHE_LRU_W[rip]
	call	R700_VM_L2_CNTL_QUEUE_SIZE@PLT
	mov	rdi, QWORD PTR R600_VM_L2_CNTL[rip]
	or	ebx, eax
	mov	esi, ebx
	call	RADEON_WRITE@PLT
	mov	rdi, QWORD PTR R600_VM_L2_CNTL2[rip]
	xor	esi, esi
	call	RADEON_WRITE@PLT
	xor	edi, edi
	call	R700_VM_L2_CNTL3_BANK_SELECT@PLT
	mov	edi, 2
	mov	ebx, eax
	call	R700_VM_L2_CNTL3_CACHE_UPDATE_MODE@PLT
	mov	rdi, QWORD PTR R600_VM_L2_CNTL3[rip]
	or	ebx, eax
	mov	esi, ebx
	call	RADEON_WRITE@PLT
	mov	ebp, DWORD PTR R600_VM_ENABLE_CONTEXT[rip]
	mov	ebx, DWORD PTR R600_VM_PAGE_TABLE_DEPTH_FLAT[rip]
	mov	rdi, QWORD PTR R600_VM_CONTEXT0_CNTL[rip]
	or	ebx, ebp
	mov	esi, ebx
	call	RADEON_WRITE@PLT
	mov	ebp, DWORD PTR R600_VM_ENABLE_CONTEXT[rip]
	not	ebp
	and	ebp, ebx
	mov	ebx, 4
	.p2align 4,,10
	.p2align 3
.L2:
	mov	rdi, QWORD PTR R600_VM_CONTEXT0_CNTL[rip]
	mov	esi, ebp
	add	rdi, rbx
	add	rbx, 4
	call	RADEON_WRITE@PLT
	cmp	rbx, 32
	jne	.L2
	mov	esi, DWORD PTR 8[r12]
	mov	rdi, QWORD PTR R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR[rip]
	sar	esi, 12
	call	RADEON_WRITE@PLT
	mov	esi, DWORD PTR [r12]
	mov	rdi, QWORD PTR R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR[rip]
	sar	esi, 12
	call	RADEON_WRITE@PLT
	mov	esi, DWORD PTR 4[r12]
	add	esi, DWORD PTR [r12]
	mov	rdi, QWORD PTR R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR[rip]
	sub	esi, 1
	sar	esi, 12
	call	RADEON_WRITE@PLT
	add	rsp, 8
	.cfi_def_cfa_offset 40
	mov	rdi, r13
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	jmp	r600_vm_flush_gart_range@PLT
	.cfi_endproc
.LFE0:
	.size	r700_vm_init, .-r700_vm_init
	.comm	R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR,8,8
	.comm	R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR,8,8
	.comm	R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR,8,8
	.comm	R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU,4,4
	.comm	R700_SYSTEM_ACCESS_MODE_IN_SYS,4,4
	.comm	R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR,8,8
	.comm	R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,8,8
	.comm	R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,8,8
	.comm	R700_MC_VM_MD_L1_TLB2_CNTL,8,8
	.comm	R700_MC_VM_MD_L1_TLB1_CNTL,8,8
	.comm	R700_MC_VM_MD_L1_TLB0_CNTL,8,8
	.comm	R700_MC_VM_MB_L1_TLB3_CNTL,8,8
	.comm	R700_MC_VM_MB_L1_TLB2_CNTL,8,8
	.comm	R700_MC_VM_MB_L1_TLB1_CNTL,8,8
	.comm	R700_MC_VM_MB_L1_TLB0_CNTL,8,8
	.comm	R700_ENABLE_L1_TLB,4,4
	.comm	R700_ENABLE_L1_FRAGMENT_PROCESSING,4,4
	.comm	R600_VM_PAGE_TABLE_DEPTH_FLAT,4,4
	.comm	R600_VM_L2_FRAG_PROC,4,4
	.comm	R600_VM_L2_CNTL3,8,8
	.comm	R600_VM_L2_CNTL2,8,8
	.comm	R600_VM_L2_CNTL,8,8
	.comm	R600_VM_L2_CACHE_EN,4,4
	.comm	R600_VM_ENABLE_PTE_CACHE_LRU_W,4,4
	.comm	R600_VM_ENABLE_CONTEXT,4,4
	.comm	R600_VM_CONTEXT0_CNTL,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_r600_cp.c_r700_vm_init.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	r700_vm_init, %function
r700_vm_init:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, lr}
	ldr	r5, [r0]
	ldr	r3, .L6
	ldr	r1, [r5]
	mov	r6, r0
	asr	r1, r1, #12
	ldr	r0, [r3]
	bl	RADEON_WRITE
	ldm	r5, {r1, r2}
	ldr	r3, .L6+4
	add	r1, r1, r2
	sub	r1, r1, #1
	ldr	r0, [r3]
	asr	r1, r1, #12
	bl	RADEON_WRITE
	ldr	r3, .L6+8
	mov	r1, #0
	ldr	r0, [r3]
	bl	RADEON_WRITE
	ldr	r1, .L6+12
	ldr	r2, .L6+16
	ldr	r3, .L6+20
	ldr	r4, [r1]
	ldr	r1, [r2]
	ldr	r2, .L6+24
	ldr	r3, [r3]
	orr	r4, r4, r1
	ldr	r1, [r2]
	orr	r4, r4, r3
	mov	r0, #5
	orr	r4, r4, r1
	bl	R700_EFFECTIVE_L1_TLB_SIZE
	mov	r1, r0
	mov	r0, #5
	orr	r4, r4, r1
	bl	R700_EFFECTIVE_L1_QUEUE_SIZE
	ldr	r3, .L6+28
	orr	r4, r4, r0
	mov	r1, r4
	ldr	r0, [r3]
	bl	RADEON_WRITE
	ldr	r3, .L6+32
	mov	r1, r4
	ldr	r0, [r3]
	bl	RADEON_WRITE
	ldr	r3, .L6+36
	mov	r1, r4
	ldr	r0, [r3]
	bl	RADEON_WRITE
	ldr	r3, .L6+40
	mov	r1, r4
	ldr	r0, [r3]
	bl	RADEON_WRITE
	ldr	r3, .L6+44
	mov	r1, r4
	ldr	r0, [r3]
	bl	RADEON_WRITE
	ldr	r3, .L6+48
	mov	r1, r4
	ldr	r0, [r3]
	bl	RADEON_WRITE
	ldr	r3, .L6+52
	mov	r1, r4
	ldr	r0, [r3]
	bl	RADEON_WRITE
	ldr	r1, .L6+56
	ldr	r3, .L6+60
	ldr	r2, .L6+64
	ldr	r4, [r1]
	ldr	r3, [r3]
	ldr	r1, [r2]
	orr	r4, r4, r3
	mov	r0, #7
	orr	r4, r4, r1
	bl	R700_VM_L2_CNTL_QUEUE_SIZE
	ldr	r3, .L6+68
	orr	r1, r4, r0
	ldr	r0, [r3]
	bl	RADEON_WRITE
	ldr	r3, .L6+72
	mov	r1, #0
	ldr	r0, [r3]
	bl	RADEON_WRITE
	mov	r0, #0
	bl	R700_VM_L2_CNTL3_BANK_SELECT
	mov	r7, r0
	mov	r0, #2
	bl	R700_VM_L2_CNTL3_CACHE_UPDATE_MODE
	mov	r4, #4
	ldr	r3, .L6+76
	orr	r1, r7, r0
	ldr	r0, [r3]
	bl	RADEON_WRITE
	ldr	r9, .L6+80
	ldr	r3, .L6+84
	ldr	r7, [r9]
	ldr	r1, [r3]
	ldr	r8, .L6+88
	orr	r7, r7, r1
	mov	r1, r7
	ldr	r0, [r8]
	bl	RADEON_WRITE
	ldr	r1, [r9]
	bic	r7, r7, r1
.L2:
	ldr	r0, [r8]
	mov	r1, r7
	add	r0, r4, r0
	add	r4, r4, #4
	bl	RADEON_WRITE
	cmp	r4, #32
	bne	.L2
	ldr	r1, [r5, #8]
	ldr	r3, .L6+92
	asr	r1, r1, #12
	ldr	r0, [r3]
	bl	RADEON_WRITE
	ldr	r1, [r5]
	ldr	r3, .L6+96
	asr	r1, r1, #12
	ldr	r0, [r3]
	bl	RADEON_WRITE
	ldm	r5, {r1, r2}
	ldr	r3, .L6+100
	add	r1, r1, r2
	sub	r1, r1, #1
	ldr	r0, [r3]
	asr	r1, r1, #12
	bl	RADEON_WRITE
	mov	r0, r6
	pop	{r4, r5, r6, r7, r8, r9, r10, lr}
	b	r600_vm_flush_gart_range
.L7:
	.align	2
.L6:
	.word	R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR
	.word	R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR
	.word	R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
	.word	R700_ENABLE_L1_TLB
	.word	R700_ENABLE_L1_FRAGMENT_PROCESSING
	.word	R700_SYSTEM_ACCESS_MODE_IN_SYS
	.word	R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
	.word	R700_MC_VM_MD_L1_TLB0_CNTL
	.word	R700_MC_VM_MD_L1_TLB1_CNTL
	.word	R700_MC_VM_MD_L1_TLB2_CNTL
	.word	R700_MC_VM_MB_L1_TLB0_CNTL
	.word	R700_MC_VM_MB_L1_TLB1_CNTL
	.word	R700_MC_VM_MB_L1_TLB2_CNTL
	.word	R700_MC_VM_MB_L1_TLB3_CNTL
	.word	R600_VM_L2_CACHE_EN
	.word	R600_VM_L2_FRAG_PROC
	.word	R600_VM_ENABLE_PTE_CACHE_LRU_W
	.word	R600_VM_L2_CNTL
	.word	R600_VM_L2_CNTL2
	.word	R600_VM_L2_CNTL3
	.word	R600_VM_ENABLE_CONTEXT
	.word	R600_VM_PAGE_TABLE_DEPTH_FLAT
	.word	R600_VM_CONTEXT0_CNTL
	.word	R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
	.word	R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR
	.word	R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR
	.size	r700_vm_init, .-r700_vm_init
	.comm	R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR,4,4
	.comm	R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR,4,4
	.comm	R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR,4,4
	.comm	R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU,4,4
	.comm	R700_SYSTEM_ACCESS_MODE_IN_SYS,4,4
	.comm	R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR,4,4
	.comm	R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,4,4
	.comm	R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,4,4
	.comm	R700_MC_VM_MD_L1_TLB2_CNTL,4,4
	.comm	R700_MC_VM_MD_L1_TLB1_CNTL,4,4
	.comm	R700_MC_VM_MD_L1_TLB0_CNTL,4,4
	.comm	R700_MC_VM_MB_L1_TLB3_CNTL,4,4
	.comm	R700_MC_VM_MB_L1_TLB2_CNTL,4,4
	.comm	R700_MC_VM_MB_L1_TLB1_CNTL,4,4
	.comm	R700_MC_VM_MB_L1_TLB0_CNTL,4,4
	.comm	R700_ENABLE_L1_TLB,4,4
	.comm	R700_ENABLE_L1_FRAGMENT_PROCESSING,4,4
	.comm	R600_VM_PAGE_TABLE_DEPTH_FLAT,4,4
	.comm	R600_VM_L2_FRAG_PROC,4,4
	.comm	R600_VM_L2_CNTL3,4,4
	.comm	R600_VM_L2_CNTL2,4,4
	.comm	R600_VM_L2_CNTL,4,4
	.comm	R600_VM_L2_CACHE_EN,4,4
	.comm	R600_VM_ENABLE_PTE_CACHE_LRU_W,4,4
	.comm	R600_VM_ENABLE_CONTEXT,4,4
	.comm	R600_VM_CONTEXT0_CNTL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
