	.file	"extr_clk-tegra20.c_tegra20_pll_init.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"pll_ref"
.LC1:
	.string	"pll_c"
.LC2:
	.string	"pll_c_out1_div"
.LC3:
	.string	"pll_c_out1"
.LC4:
	.string	"pll_m"
.LC5:
	.string	"pll_m_out1_div"
.LC6:
	.string	"pll_m_out1"
.LC7:
	.string	"pll_x"
.LC8:
	.string	"pll_u"
.LC9:
	.string	"pll_d"
.LC10:
	.string	"pll_d_out0"
.LC11:
	.string	"pll_p_out1"
.LC12:
	.string	"pll_a"
.LC13:
	.string	"pll_a_out0_div"
.LC14:
	.string	"pll_a_out0"
.LC15:
	.string	"pll_e"
	.text
	.p2align 4
	.type	tegra20_pll_init, @function
tegra20_pll_init:
.LFB0:
	.cfi_startproc
	endbr64
	sub	rsp, 16
	.cfi_def_cfa_offset 24
	mov	rdx, QWORD PTR clk_base[rip]
	xor	r8d, r8d
	xor	ecx, ecx
	push	0
	.cfi_def_cfa_offset 32
	lea	r9, pll_c_params[rip]
	lea	rsi, .LC0[rip]
	lea	rdi, .LC1[rip]
	call	tegra_clk_register_pll@PLT
	mov	rdx, QWORD PTR TEGRA20_CLK_PLL_C[rip]
	mov	rcx, QWORD PTR clks[rip]
	mov	r9d, 8
	mov	r8d, DWORD PTR TEGRA_DIVIDER_ROUND_UP[rip]
	lea	rsi, .LC1[rip]
	lea	rdi, .LC2[rip]
	mov	QWORD PTR [rcx+rdx*8], rax
	xor	ecx, ecx
	mov	rdx, QWORD PTR PLLC_OUT[rip]
	mov	QWORD PTR [rsp], 0
	add	rdx, QWORD PTR clk_base[rip]
	push	1
	.cfi_def_cfa_offset 40
	push	8
	.cfi_def_cfa_offset 48
	call	tegra_clk_register_divider@PLT
	add	rsp, 32
	.cfi_def_cfa_offset 16
	xor	r8d, r8d
	mov	r9d, DWORD PTR CLK_SET_RATE_PARENT[rip]
	push	0
	.cfi_def_cfa_offset 24
	mov	rdx, QWORD PTR PLLC_OUT[rip]
	mov	ecx, 1
	lea	rsi, .LC2[rip]
	push	0
	.cfi_def_cfa_offset 32
	add	rdx, QWORD PTR clk_base[rip]
	lea	rdi, .LC3[rip]
	call	tegra_clk_register_pll_out@PLT
	mov	rdx, QWORD PTR TEGRA20_CLK_PLL_C_OUT1[rip]
	mov	rcx, QWORD PTR clks[rip]
	lea	r9, pll_m_params[rip]
	mov	r8d, DWORD PTR CLK_SET_RATE_GATE[rip]
	lea	rsi, .LC0[rip]
	lea	rdi, .LC4[rip]
	mov	QWORD PTR [rcx+rdx*8], rax
	mov	rdx, QWORD PTR clk_base[rip]
	xor	ecx, ecx
	mov	QWORD PTR [rsp], 0
	call	tegra_clk_register_pll@PLT
	mov	rdx, QWORD PTR TEGRA20_CLK_PLL_M[rip]
	mov	rcx, QWORD PTR clks[rip]
	mov	r9d, 8
	mov	r8d, DWORD PTR TEGRA_DIVIDER_ROUND_UP[rip]
	lea	rsi, .LC4[rip]
	lea	rdi, .LC5[rip]
	mov	QWORD PTR [rcx+rdx*8], rax
	xor	ecx, ecx
	mov	rdx, QWORD PTR PLLM_OUT[rip]
	mov	QWORD PTR [rsp], 0
	add	rdx, QWORD PTR clk_base[rip]
	push	1
	.cfi_def_cfa_offset 40
	push	8
	.cfi_def_cfa_offset 48
	call	tegra_clk_register_divider@PLT
	add	rsp, 32
	.cfi_def_cfa_offset 16
	xor	r8d, r8d
	mov	r9d, DWORD PTR CLK_SET_RATE_PARENT[rip]
	push	0
	.cfi_def_cfa_offset 24
	mov	rdx, QWORD PTR PLLM_OUT[rip]
	mov	ecx, 1
	lea	rsi, .LC5[rip]
	push	0
	.cfi_def_cfa_offset 32
	add	rdx, QWORD PTR clk_base[rip]
	lea	rdi, .LC6[rip]
	call	tegra_clk_register_pll_out@PLT
	mov	rdx, QWORD PTR TEGRA20_CLK_PLL_M_OUT1[rip]
	xor	r8d, r8d
	mov	rcx, QWORD PTR clks[rip]
	lea	r9, pll_x_params[rip]
	lea	rsi, .LC0[rip]
	mov	QWORD PTR [rcx+rdx*8], rax
	mov	rdx, QWORD PTR clk_base[rip]
	xor	ecx, ecx
	lea	rdi, .LC7[rip]
	mov	QWORD PTR [rsp], 0
	call	tegra_clk_register_pll@PLT
	mov	rdx, QWORD PTR TEGRA20_CLK_PLL_X[rip]
	xor	r8d, r8d
	mov	rcx, QWORD PTR clks[rip]
	lea	r9, pll_u_params[rip]
	lea	rsi, .LC0[rip]
	mov	QWORD PTR [rcx+rdx*8], rax
	mov	rdx, QWORD PTR clk_base[rip]
	xor	ecx, ecx
	lea	rdi, .LC8[rip]
	mov	QWORD PTR [rsp], 0
	call	tegra_clk_register_pll@PLT
	mov	rdx, QWORD PTR TEGRA20_CLK_PLL_U[rip]
	xor	r8d, r8d
	mov	rcx, QWORD PTR clks[rip]
	lea	r9, pll_d_params[rip]
	lea	rsi, .LC0[rip]
	mov	QWORD PTR [rcx+rdx*8], rax
	mov	rdx, QWORD PTR clk_base[rip]
	xor	ecx, ecx
	lea	rdi, .LC9[rip]
	mov	QWORD PTR [rsp], 0
	call	tegra_clk_register_pll@PLT
	mov	rdx, QWORD PTR TEGRA20_CLK_PLL_D[rip]
	xor	edi, edi
	mov	rcx, QWORD PTR clks[rip]
	mov	r9d, 2
	mov	r8d, 1
	lea	rsi, .LC10[rip]
	mov	QWORD PTR [rcx+rdx*8], rax
	mov	ecx, DWORD PTR CLK_SET_RATE_PARENT[rip]
	lea	rdx, .LC9[rip]
	call	clk_register_fixed_factor@PLT
	mov	rdx, QWORD PTR TEGRA20_CLK_PLL_D_OUT0[rip]
	xor	r8d, r8d
	mov	rcx, QWORD PTR clks[rip]
	lea	r9, pll_a_params[rip]
	lea	rsi, .LC11[rip]
	mov	QWORD PTR [rcx+rdx*8], rax
	mov	rdx, QWORD PTR clk_base[rip]
	xor	ecx, ecx
	lea	rdi, .LC12[rip]
	mov	QWORD PTR [rsp], 0
	call	tegra_clk_register_pll@PLT
	mov	rdx, QWORD PTR TEGRA20_CLK_PLL_A[rip]
	mov	rcx, QWORD PTR clks[rip]
	mov	r9d, 8
	mov	r8d, DWORD PTR TEGRA_DIVIDER_ROUND_UP[rip]
	lea	rsi, .LC12[rip]
	lea	rdi, .LC13[rip]
	mov	QWORD PTR [rcx+rdx*8], rax
	mov	rdx, QWORD PTR PLLA_OUT[rip]
	xor	ecx, ecx
	mov	QWORD PTR [rsp], 0
	add	rdx, QWORD PTR clk_base[rip]
	push	1
	.cfi_def_cfa_offset 40
	push	8
	.cfi_def_cfa_offset 48
	call	tegra_clk_register_divider@PLT
	add	rsp, 32
	.cfi_def_cfa_offset 16
	xor	r8d, r8d
	mov	ecx, 1
	push	0
	.cfi_def_cfa_offset 24
	mov	rdx, QWORD PTR PLLA_OUT[rip]
	lea	rsi, .LC13[rip]
	lea	rdi, .LC14[rip]
	mov	r9d, DWORD PTR CLK_IGNORE_UNUSED[rip]
	add	rdx, QWORD PTR clk_base[rip]
	push	0
	.cfi_def_cfa_offset 32
	or	r9d, DWORD PTR CLK_SET_RATE_PARENT[rip]
	call	tegra_clk_register_pll_out@PLT
	mov	rdx, QWORD PTR TEGRA20_CLK_PLL_A_OUT0[rip]
	mov	rcx, QWORD PTR clks[rip]
	lea	r9, pll_e_params[rip]
	xor	r8d, r8d
	lea	rsi, .LC0[rip]
	lea	rdi, .LC15[rip]
	mov	QWORD PTR [rcx+rdx*8], rax
	mov	ecx, DWORD PTR pmc_base[rip]
	mov	rdx, QWORD PTR clk_base[rip]
	mov	QWORD PTR [rsp], 0
	call	tegra_clk_register_plle@PLT
	mov	rdx, QWORD PTR TEGRA20_CLK_PLL_E[rip]
	mov	rcx, QWORD PTR clks[rip]
	mov	QWORD PTR [rcx+rdx*8], rax
	add	rsp, 24
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE0:
	.size	tegra20_pll_init, .-tegra20_pll_init
	.comm	pmc_base,4,4
	.comm	pll_x_params,4,4
	.comm	pll_u_params,4,4
	.comm	pll_m_params,4,4
	.comm	pll_e_params,4,4
	.comm	pll_d_params,4,4
	.comm	pll_c_params,4,4
	.comm	pll_a_params,4,4
	.comm	clks,8,8
	.comm	clk_base,8,8
	.comm	TEGRA_DIVIDER_ROUND_UP,4,4
	.comm	TEGRA20_CLK_PLL_X,8,8
	.comm	TEGRA20_CLK_PLL_U,8,8
	.comm	TEGRA20_CLK_PLL_M_OUT1,8,8
	.comm	TEGRA20_CLK_PLL_M,8,8
	.comm	TEGRA20_CLK_PLL_E,8,8
	.comm	TEGRA20_CLK_PLL_D_OUT0,8,8
	.comm	TEGRA20_CLK_PLL_D,8,8
	.comm	TEGRA20_CLK_PLL_C_OUT1,8,8
	.comm	TEGRA20_CLK_PLL_C,8,8
	.comm	TEGRA20_CLK_PLL_A_OUT0,8,8
	.comm	TEGRA20_CLK_PLL_A,8,8
	.comm	PLLM_OUT,8,8
	.comm	PLLC_OUT,8,8
	.comm	PLLA_OUT,8,8
	.comm	CLK_SET_RATE_PARENT,4,4
	.comm	CLK_SET_RATE_GATE,4,4
	.comm	CLK_IGNORE_UNUSED,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_clk-tegra20.c_tegra20_pll_init.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"pll_ref\000"
	.align	2
.LC1:
	.ascii	"pll_c\000"
	.align	2
.LC2:
	.ascii	"pll_c_out1_div\000"
	.align	2
.LC3:
	.ascii	"pll_c_out1\000"
	.align	2
.LC4:
	.ascii	"pll_m\000"
	.align	2
.LC5:
	.ascii	"pll_m_out1_div\000"
	.align	2
.LC6:
	.ascii	"pll_m_out1\000"
	.align	2
.LC7:
	.ascii	"pll_x\000"
	.align	2
.LC8:
	.ascii	"pll_u\000"
	.align	2
.LC9:
	.ascii	"pll_d\000"
	.align	2
.LC10:
	.ascii	"pll_d_out0\000"
	.align	2
.LC11:
	.ascii	"pll_p_out1\000"
	.align	2
.LC12:
	.ascii	"pll_a\000"
	.align	2
.LC13:
	.ascii	"pll_a_out0_div\000"
	.align	2
.LC14:
	.ascii	"pll_a_out0\000"
	.align	2
.LC15:
	.ascii	"pll_e\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	tegra20_pll_init, %function
tegra20_pll_init:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	mov	r4, #0
	ldr	r5, .L4
	ldr	r8, .L4+4
	ldr	r9, .L4+8
	ldr	ip, .L4+12
	sub	sp, sp, #28
	mov	r3, r4
	mov	r1, r8
	ldr	r2, [r5]
	str	ip, [sp, #4]
	mov	r0, r9
	str	r4, [sp, #8]
	str	r4, [sp]
	bl	tegra_clk_register_pll
	ldr	r6, .L4+16
	ldr	r3, .L4+20
	ldr	lr, [r6]
	ldr	r10, [r3]
	ldr	fp, .L4+24
	ldr	r3, .L4+28
	ldr	r2, [fp]
	mov	r7, #1
	ldr	r3, [r3]
	ldr	ip, [r5]
	str	r0, [lr, r10, lsl #2]
	mov	r0, #8
	ldr	r10, .L4+32
	mov	r1, r9
	ldr	r9, .L4+36
	add	r2, ip, r2
	str	r3, [sp]
	str	r7, [sp, #12]
	mov	r3, r4
	str	r0, [sp, #8]
	str	r0, [sp, #4]
	str	r4, [sp, #16]
	mov	r0, r10
	bl	tegra_clk_register_divider
	ldr	r2, [fp]
	ldr	r3, [r9]
	ldr	r0, [r5]
	mov	r1, r10
	add	r2, r0, r2
	str	r3, [sp, #4]
	str	r4, [sp, #12]
	mov	r3, r7
	str	r4, [sp, #8]
	str	r4, [sp]
	ldr	r0, .L4+40
	bl	tegra_clk_register_pll_out
	ldr	r1, .L4+44
	ldr	r2, .L4+48
	ldr	r1, [r1]
	ldr	r2, [r2]
	ldr	r3, [r6]
	ldr	r10, .L4+52
	ldr	ip, .L4+56
	str	r0, [r3, r1, lsl #2]
	mov	r3, r4
	mov	r1, r8
	str	r2, [sp]
	str	ip, [sp, #4]
	ldr	r2, [r5]
	mov	r0, r10
	str	r4, [sp, #8]
	bl	tegra_clk_register_pll
	ldr	r2, .L4+60
	ldr	r3, [r6]
	ldr	lr, [r2]
	ldr	fp, .L4+64
	ldr	ip, [r5]
	ldr	r2, [fp]
	str	r0, [r3, lr, lsl #2]
	mov	r0, #8
	ldr	r3, .L4+28
	mov	r1, r10
	ldr	r3, [r3]
	ldr	r10, .L4+68
	add	r2, ip, r2
	str	r7, [sp, #12]
	str	r0, [sp, #8]
	str	r0, [sp, #4]
	str	r3, [sp]
	mov	r0, r10
	mov	r3, r4
	str	r4, [sp, #16]
	bl	tegra_clk_register_divider
	ldr	r2, [fp]
	ldr	r3, [r9]
	ldr	r0, [r5]
	mov	r1, r10
	add	r2, r0, r2
	str	r3, [sp, #4]
	str	r4, [sp, #12]
	mov	r3, r7
	str	r4, [sp, #8]
	str	r4, [sp]
	ldr	r0, .L4+72
	bl	tegra_clk_register_pll_out
	ldr	r2, .L4+76
	ldr	r3, [r6]
	ldr	r2, [r2]
	ldr	ip, .L4+80
	str	r0, [r3, r2, lsl #2]
	mov	r1, r8
	mov	r3, r4
	ldr	r2, [r5]
	str	ip, [sp, #4]
	str	r4, [sp, #8]
	str	r4, [sp]
	ldr	r0, .L4+84
	bl	tegra_clk_register_pll
	ldr	r2, .L4+88
	ldr	r3, [r6]
	ldr	r2, [r2]
	ldr	ip, .L4+92
	str	r0, [r3, r2, lsl #2]
	mov	r1, r8
	mov	r3, r4
	ldr	r2, [r5]
	str	ip, [sp, #4]
	str	r4, [sp, #8]
	str	r4, [sp]
	ldr	r0, .L4+96
	bl	tegra_clk_register_pll
	ldr	r2, .L4+100
	ldr	r3, [r6]
	ldr	r2, [r2]
	ldr	r10, .L4+104
	ldr	ip, .L4+108
	str	r0, [r3, r2, lsl #2]
	mov	r1, r8
	mov	r3, r4
	ldr	r2, [r5]
	str	ip, [sp, #4]
	mov	r0, r10
	str	r4, [sp, #8]
	str	r4, [sp]
	bl	tegra_clk_register_pll
	mov	r1, #2
	ldr	r2, .L4+112
	ldr	r3, [r6]
	ldr	ip, [r2]
	mov	r2, r10
	str	r0, [r3, ip, lsl #2]
	ldr	r3, [r9]
	mov	r0, r4
	str	r7, [sp]
	str	r1, [sp, #4]
	ldr	r1, .L4+116
	bl	clk_register_fixed_factor
	ldr	r2, .L4+120
	ldr	r3, [r6]
	ldr	r2, [r2]
	ldr	r10, .L4+124
	ldr	r1, .L4+128
	str	r0, [r3, r2, lsl #2]
	mov	r3, r4
	ldr	r2, [r5]
	str	r1, [sp, #4]
	mov	r0, r10
	ldr	r1, .L4+132
	str	r4, [sp, #8]
	str	r4, [sp]
	bl	tegra_clk_register_pll
	ldr	r3, .L4+136
	mov	r1, r10
	ldr	lr, [r3]
	ldr	r10, [r6]
	ldr	fp, .L4+140
	ldr	r2, .L4+28
	ldr	r3, [fp]
	ldr	ip, [r2]
	ldr	r2, [r5]
	str	r0, [r10, lr, lsl #2]
	mov	r0, #8
	ldr	r10, .L4+144
	str	ip, [sp]
	str	r7, [sp, #12]
	str	r0, [sp, #8]
	str	r0, [sp, #4]
	add	r2, r2, r3
	mov	r0, r10
	mov	r3, r4
	str	r4, [sp, #16]
	bl	tegra_clk_register_divider
	ldr	r2, .L4+148
	ldr	r3, [r9]
	ldr	r0, [r2]
	ldr	ip, [r5]
	ldr	r2, [fp]
	orr	r0, r0, r3
	mov	r1, r10
	mov	r3, r7
	str	r0, [sp, #4]
	add	r2, ip, r2
	str	r4, [sp, #12]
	str	r4, [sp, #8]
	str	r4, [sp]
	ldr	r0, .L4+152
	bl	tegra_clk_register_pll_out
	ldr	r3, .L4+156
	ldr	lr, [r6]
	ldr	r7, [r3]
	ldr	ip, .L4+160
	ldr	r3, .L4+164
	ldr	r2, [r5]
	ldr	r3, [r3]
	str	r0, [lr, r7, lsl #2]
	mov	r1, r8
	stm	sp, {r4, ip}
	str	r4, [sp, #8]
	ldr	r0, .L4+168
	bl	tegra_clk_register_plle
	ldr	r2, .L4+172
	ldr	r3, [r6]
	ldr	r2, [r2]
	str	r0, [r3, r2, lsl #2]
	add	sp, sp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L5:
	.align	2
.L4:
	.word	clk_base
	.word	.LC0
	.word	.LC1
	.word	pll_c_params
	.word	clks
	.word	TEGRA20_CLK_PLL_C
	.word	PLLC_OUT
	.word	TEGRA_DIVIDER_ROUND_UP
	.word	.LC2
	.word	CLK_SET_RATE_PARENT
	.word	.LC3
	.word	TEGRA20_CLK_PLL_C_OUT1
	.word	CLK_SET_RATE_GATE
	.word	.LC4
	.word	pll_m_params
	.word	TEGRA20_CLK_PLL_M
	.word	PLLM_OUT
	.word	.LC5
	.word	.LC6
	.word	TEGRA20_CLK_PLL_M_OUT1
	.word	pll_x_params
	.word	.LC7
	.word	TEGRA20_CLK_PLL_X
	.word	pll_u_params
	.word	.LC8
	.word	TEGRA20_CLK_PLL_U
	.word	.LC9
	.word	pll_d_params
	.word	TEGRA20_CLK_PLL_D
	.word	.LC10
	.word	TEGRA20_CLK_PLL_D_OUT0
	.word	.LC12
	.word	pll_a_params
	.word	.LC11
	.word	TEGRA20_CLK_PLL_A
	.word	PLLA_OUT
	.word	.LC13
	.word	CLK_IGNORE_UNUSED
	.word	.LC14
	.word	TEGRA20_CLK_PLL_A_OUT0
	.word	pll_e_params
	.word	pmc_base
	.word	.LC15
	.word	TEGRA20_CLK_PLL_E
	.size	tegra20_pll_init, .-tegra20_pll_init
	.comm	pmc_base,4,4
	.comm	pll_x_params,4,4
	.comm	pll_u_params,4,4
	.comm	pll_m_params,4,4
	.comm	pll_e_params,4,4
	.comm	pll_d_params,4,4
	.comm	pll_c_params,4,4
	.comm	pll_a_params,4,4
	.comm	clks,4,4
	.comm	clk_base,4,4
	.comm	TEGRA_DIVIDER_ROUND_UP,4,4
	.comm	TEGRA20_CLK_PLL_X,4,4
	.comm	TEGRA20_CLK_PLL_U,4,4
	.comm	TEGRA20_CLK_PLL_M_OUT1,4,4
	.comm	TEGRA20_CLK_PLL_M,4,4
	.comm	TEGRA20_CLK_PLL_E,4,4
	.comm	TEGRA20_CLK_PLL_D_OUT0,4,4
	.comm	TEGRA20_CLK_PLL_D,4,4
	.comm	TEGRA20_CLK_PLL_C_OUT1,4,4
	.comm	TEGRA20_CLK_PLL_C,4,4
	.comm	TEGRA20_CLK_PLL_A_OUT0,4,4
	.comm	TEGRA20_CLK_PLL_A,4,4
	.comm	PLLM_OUT,4,4
	.comm	PLLC_OUT,4,4
	.comm	PLLA_OUT,4,4
	.comm	CLK_SET_RATE_PARENT,4,4
	.comm	CLK_SET_RATE_GATE,4,4
	.comm	CLK_IGNORE_UNUSED,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
