	.file	"extr_cdv_intel_display.c_cdv_update_wm.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	cdv_update_wm
	.type	cdv_update_wm, @function
cdv_update_wm:
.LFB0:
	.cfi_startproc
	endbr64
	push	r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	push	r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	push	r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	mov	r12, rsi
	push	rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	mov	r14, QWORD PTR [rdi]
	mov	rdi, rsi
	call	to_gma_crtc@PLT
	xor	esi, esi
	mov	rdi, rbp
	mov	r13, rax
	call	cdv_intel_pipe_enabled@PLT
	mov	esi, 1
	mov	rdi, rbp
	mov	ebx, eax
	call	cdv_intel_pipe_enabled@PLT
	cmp	ebx, eax
	je	.L2
	mov	edi, DWORD PTR DSPFW1[rip]
	call	REG_READ@PLT
	mov	edx, 126
	mov	ecx, DWORD PTR DSP_FIFO_SR_WM_SHIFT[rip]
	mov	edi, DWORD PTR DSPFW1[rip]
	mov	esi, eax
	mov	eax, DWORD PTR DSP_FIFO_SR_WM_MASK[rip]
	not	eax
	and	esi, eax
	mov	eax, edx
	sal	eax, cl
	mov	ecx, DWORD PTR CURSOR_B_FIFO_WM_SHIFT[rip]
	or	eax, esi
	mov	esi, DWORD PTR CURSOR_B_FIFO_WM_MASK[rip]
	not	esi
	and	eax, esi
	mov	esi, 4
	sal	esi, cl
	or	esi, eax
	call	REG_WRITE@PLT
	mov	edi, DWORD PTR DSPFW2[rip]
	call	REG_READ@PLT
	mov	ecx, DWORD PTR CURSOR_A_FIFO_WM_SHIFT[rip]
	mov	edx, 6
	mov	edi, DWORD PTR DSPFW2[rip]
	mov	esi, eax
	mov	eax, DWORD PTR CURSOR_A_FIFO_WM_MASK[rip]
	not	eax
	and	esi, eax
	mov	eax, edx
	sal	eax, cl
	mov	ecx, DWORD PTR DSP_PLANE_C_FIFO_WM_SHIFT[rip]
	or	eax, esi
	mov	esi, DWORD PTR DSP_PLANE_C_FIFO_WM_MASK[rip]
	not	esi
	and	eax, esi
	mov	esi, 8
	sal	esi, cl
	or	esi, eax
	call	REG_WRITE@PLT
	mov	edi, DWORD PTR DSPFW3[rip]
	mov	esi, 905969664
	call	REG_WRITE@PLT
	cmp	DWORD PTR 0[r13], 1
	je	.L10
.L3:
	mov	ecx, DWORD PTR DSP_PLANE_B_FIFO_WM1_SHIFT[rip]
	mov	edx, 3
	mov	eax, 4
	mov	edi, DWORD PTR DSPFW5[rip]
	mov	esi, edx
	mov	ebx, eax
	sal	esi, cl
	mov	ecx, DWORD PTR DSP_PLANE_A_FIFO_WM1_SHIFT[rip]
	sal	ebx, cl
	mov	ecx, DWORD PTR CURSOR_B_FIFO_WM1_SHIFT[rip]
	or	esi, ebx
	sal	edx, cl
	mov	ecx, DWORD PTR CURSOR_FIFO_SR_WM1_SHIFT[rip]
	or	esi, edx
	sal	eax, cl
	or	esi, eax
	call	REG_WRITE@PLT
.L4:
	mov	edi, DWORD PTR DSPFW6[rip]
	mov	esi, 16
	call	REG_WRITE@PLT
	mov	rdi, rbp
	call	gma_wait_for_vblank@PLT
	mov	esi, DWORD PTR FW_BLC_SELF_EN[rip]
	mov	edi, DWORD PTR FW_BLC_SELF[rip]
	call	REG_WRITE@PLT
	mov	edi, DWORD PTR FW_BLC_SELF[rip]
	call	REG_READ@PLT
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	rdi, rbp
	pop	rbp
	.cfi_def_cfa_offset 32
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	jmp	gma_wait_for_vblank@PLT
	.p2align 4,,10
	.p2align 3
.L10:
	.cfi_restore_state
	mov	esi, DWORD PTR INTEL_OUTPUT_LVDS[rip]
	mov	rdi, r12
	call	gma_pipe_has_type@PLT
	test	rax, rax
	je	.L3
	mov	edi, DWORD PTR DSPFW5[rip]
	mov	esi, 262960
	call	REG_WRITE@PLT
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L2:
	mov	edi, DWORD PTR DSPFW1[rip]
	mov	esi, 1065879560
	call	REG_WRITE@PLT
	mov	edi, DWORD PTR DSPFW2[rip]
	mov	esi, 184680962
	call	REG_WRITE@PLT
	mov	edi, DWORD PTR DSPFW3[rip]
	mov	esi, 603979776
	call	REG_WRITE@PLT
	mov	edi, DWORD PTR DSPFW4[rip]
	mov	esi, 134414850
	call	REG_WRITE@PLT
	mov	edi, DWORD PTR DSPFW5[rip]
	mov	esi, 16843009
	call	REG_WRITE@PLT
	mov	edi, DWORD PTR DSPFW6[rip]
	mov	esi, 464
	call	REG_WRITE@PLT
	mov	rdi, rbp
	call	gma_wait_for_vblank@PLT
	mov	rax, QWORD PTR [r14]
	pop	rbx
	.cfi_def_cfa_offset 40
	mov	rdi, rbp
	pop	rbp
	.cfi_def_cfa_offset 32
	pop	r12
	.cfi_def_cfa_offset 24
	mov	rax, QWORD PTR [rax]
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	jmp	rax
	.cfi_endproc
.LFE0:
	.size	cdv_update_wm, .-cdv_update_wm
	.comm	INTEL_OUTPUT_LVDS,4,4
	.comm	FW_BLC_SELF_EN,4,4
	.comm	FW_BLC_SELF,4,4
	.comm	DSP_PLANE_C_FIFO_WM_SHIFT,4,4
	.comm	DSP_PLANE_C_FIFO_WM_MASK,4,4
	.comm	DSP_PLANE_B_FIFO_WM1_SHIFT,4,4
	.comm	DSP_PLANE_A_FIFO_WM1_SHIFT,4,4
	.comm	DSP_FIFO_SR_WM_SHIFT,4,4
	.comm	DSP_FIFO_SR_WM_MASK,4,4
	.comm	DSPFW6,4,4
	.comm	DSPFW5,4,4
	.comm	DSPFW4,4,4
	.comm	DSPFW3,4,4
	.comm	DSPFW2,4,4
	.comm	DSPFW1,4,4
	.comm	CURSOR_FIFO_SR_WM1_SHIFT,4,4
	.comm	CURSOR_B_FIFO_WM_SHIFT,4,4
	.comm	CURSOR_B_FIFO_WM_MASK,4,4
	.comm	CURSOR_B_FIFO_WM1_SHIFT,4,4
	.comm	CURSOR_A_FIFO_WM_SHIFT,4,4
	.comm	CURSOR_A_FIFO_WM_MASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_cdv_intel_display.c_cdv_update_wm.c"
	.text
	.align	2
	.global	cdv_update_wm
	.syntax unified
	.arm
	.fpu softvfp
	.type	cdv_update_wm, %function
cdv_update_wm:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	mov	r4, r0
	mov	r0, r1
	mov	r5, r1
	ldr	r8, [r4]
	bl	to_gma_crtc
	mov	r1, #0
	mov	r6, r0
	mov	r0, r4
	bl	cdv_intel_pipe_enabled
	mov	r1, #1
	mov	r7, r0
	mov	r0, r4
	bl	cdv_intel_pipe_enabled
	cmp	r7, r0
	beq	.L2
	ldr	r8, .L11
	ldr	r7, .L11+4
	ldr	r0, [r8]
	bl	REG_READ
	mov	r3, r0
	mov	lr, #126
	mov	r1, #4
	ldr	r2, .L11+8
	ldr	r0, [r8]
	ldr	ip, [r2]
	ldr	r2, .L11+12
	bic	r3, r3, ip
	ldr	ip, [r2]
	ldr	r2, .L11+16
	orr	r3, r3, lr, lsl ip
	ldr	ip, [r2]
	ldr	r2, .L11+20
	bic	r3, r3, ip
	ldr	r2, [r2]
	orr	r1, r3, r1, lsl r2
	bl	REG_WRITE
	ldr	r0, [r7]
	bl	REG_READ
	mov	lr, #6
	mov	r1, #8
	ldr	r3, .L11+24
	ldr	r2, .L11+28
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	ip, .L11+32
	bic	r3, r0, r3
	orr	r3, r3, lr, lsl r2
	ldr	r2, .L11+36
	ldr	r0, [ip]
	ldr	r2, [r2]
	bic	r3, r3, r0
	orr	r1, r3, r1, lsl r2
	ldr	r0, [r7]
	bl	REG_WRITE
	ldr	r3, .L11+40
	mov	r1, #905969664
	ldr	r0, [r3]
	bl	REG_WRITE
	ldr	r3, [r6]
	cmp	r3, #1
	beq	.L10
.L3:
	mov	r2, #4
	mov	r1, #3
	ldr	r3, .L11+44
	ldr	r0, .L11+48
	ldr	r3, [r3]
	ldr	r0, [r0]
	ldr	ip, .L11+52
	lsl	r3, r2, r3
	orr	r3, r3, r1, lsl r0
	ldr	ip, [ip]
	ldr	r0, .L11+56
	orr	r3, r3, r1, lsl ip
	ldr	r1, [r0]
	ldr	r0, .L11+60
	orr	r1, r3, r2, lsl r1
	ldr	r0, [r0]
	bl	REG_WRITE
.L4:
	ldr	r3, .L11+64
	mov	r1, #16
	ldr	r0, [r3]
	bl	REG_WRITE
	mov	r0, r4
	bl	gma_wait_for_vblank
	ldr	r5, .L11+68
	ldr	r3, .L11+72
	ldr	r0, [r5]
	ldr	r1, [r3]
	bl	REG_WRITE
	ldr	r0, [r5]
	bl	REG_READ
	mov	r0, r4
	pop	{r4, r5, r6, r7, r8, lr}
	b	gma_wait_for_vblank
.L10:
	ldr	r3, .L11+76
	mov	r0, r5
	ldr	r1, [r3]
	bl	gma_pipe_has_type
	cmp	r0, #0
	beq	.L3
	ldr	r3, .L11+60
	ldr	r1, .L11+80
	ldr	r0, [r3]
	bl	REG_WRITE
	b	.L4
.L2:
	ldr	r3, .L11
	ldr	r1, .L11+84
	ldr	r0, [r3]
	bl	REG_WRITE
	ldr	r3, .L11+4
	ldr	r1, .L11+88
	ldr	r0, [r3]
	bl	REG_WRITE
	ldr	r3, .L11+40
	mov	r1, #603979776
	ldr	r0, [r3]
	bl	REG_WRITE
	ldr	r3, .L11+92
	ldr	r1, .L11+96
	ldr	r0, [r3]
	bl	REG_WRITE
	ldr	r3, .L11+60
	ldr	r1, .L11+100
	ldr	r0, [r3]
	bl	REG_WRITE
	ldr	r3, .L11+64
	mov	r1, #464
	ldr	r0, [r3]
	bl	REG_WRITE
	mov	r0, r4
	bl	gma_wait_for_vblank
	ldr	r3, [r8]
	mov	r0, r4
	pop	{r4, r5, r6, r7, r8, lr}
	ldr	r3, [r3]
	bx	r3
.L12:
	.align	2
.L11:
	.word	DSPFW1
	.word	DSPFW2
	.word	DSP_FIFO_SR_WM_MASK
	.word	DSP_FIFO_SR_WM_SHIFT
	.word	CURSOR_B_FIFO_WM_MASK
	.word	CURSOR_B_FIFO_WM_SHIFT
	.word	CURSOR_A_FIFO_WM_MASK
	.word	CURSOR_A_FIFO_WM_SHIFT
	.word	DSP_PLANE_C_FIFO_WM_MASK
	.word	DSP_PLANE_C_FIFO_WM_SHIFT
	.word	DSPFW3
	.word	DSP_PLANE_A_FIFO_WM1_SHIFT
	.word	DSP_PLANE_B_FIFO_WM1_SHIFT
	.word	CURSOR_B_FIFO_WM1_SHIFT
	.word	CURSOR_FIFO_SR_WM1_SHIFT
	.word	DSPFW5
	.word	DSPFW6
	.word	FW_BLC_SELF
	.word	FW_BLC_SELF_EN
	.word	INTEL_OUTPUT_LVDS
	.word	262960
	.word	1065879560
	.word	184680962
	.word	DSPFW4
	.word	134414850
	.word	16843009
	.size	cdv_update_wm, .-cdv_update_wm
	.comm	INTEL_OUTPUT_LVDS,4,4
	.comm	FW_BLC_SELF_EN,4,4
	.comm	FW_BLC_SELF,4,4
	.comm	DSP_PLANE_C_FIFO_WM_SHIFT,4,4
	.comm	DSP_PLANE_C_FIFO_WM_MASK,4,4
	.comm	DSP_PLANE_B_FIFO_WM1_SHIFT,4,4
	.comm	DSP_PLANE_A_FIFO_WM1_SHIFT,4,4
	.comm	DSP_FIFO_SR_WM_SHIFT,4,4
	.comm	DSP_FIFO_SR_WM_MASK,4,4
	.comm	DSPFW6,4,4
	.comm	DSPFW5,4,4
	.comm	DSPFW4,4,4
	.comm	DSPFW3,4,4
	.comm	DSPFW2,4,4
	.comm	DSPFW1,4,4
	.comm	CURSOR_FIFO_SR_WM1_SHIFT,4,4
	.comm	CURSOR_B_FIFO_WM_SHIFT,4,4
	.comm	CURSOR_B_FIFO_WM_MASK,4,4
	.comm	CURSOR_B_FIFO_WM1_SHIFT,4,4
	.comm	CURSOR_A_FIFO_WM_SHIFT,4,4
	.comm	CURSOR_A_FIFO_WM_MASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
