	.file	"extr_vt_vga.c_vga_initialize.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Timeout initializing vt_vga\n"
	.text
	.p2align 4
	.type	vga_initialize, @function
vga_initialize:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	mov	r13, rdi
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	mov	r12d, esi
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	mov	ebp, 10000
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	sub	rsp, 8
	.cfi_def_cfa_offset 48
	mov	rbx, QWORD PTR [rdi]
	mov	esi, DWORD PTR VGA_GEN_MISC_OUTPUT_R[rip]
	mov	rdi, rbx
	call	REG_READ1@PLT
	mov	esi, DWORD PTR VGA_GEN_MISC_OUTPUT_W[rip]
	or	eax, DWORD PTR VGA_GEN_MO_IOA[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_CRTC_VERT_RETRACE_END[rip]
	mov	esi, DWORD PTR VGA_CRTC_ADDRESS[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_CRTC_DATA[rip]
	mov	rdi, rbx
	call	REG_READ1@PLT
	mov	edx, DWORD PTR VGA_CRTC_VRE_PR[rip]
	mov	esi, DWORD PTR VGA_CRTC_DATA[rip]
	mov	rdi, rbx
	not	edx
	and	edx, eax
	call	REG_WRITE1@PLT
	jmp	.L3
	.p2align 4,,10
	.p2align 3
.L20:
	sub	ebp, 1
	je	.L19
.L3:
	mov	edi, 10
	call	DELAY@PLT
	mov	esi, DWORD PTR VGA_GEN_INPUT_STAT_1[rip]
	mov	rdi, rbx
	call	REG_READ1@PLT
	mov	edx, DWORD PTR VGA_GEN_IS1_VR[rip]
	or	edx, DWORD PTR VGA_GEN_IS1_DE[rip]
	and	eax, edx
	cmp	edx, eax
	jne	.L20
	mov	edx, DWORD PTR VGA_CRTC_MODE_CONTROL[rip]
	mov	esi, DWORD PTR VGA_CRTC_ADDRESS[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_CRTC_DATA[rip]
	mov	rdi, rbx
	call	REG_READ1@PLT
	mov	edx, DWORD PTR VGA_CRTC_MC_HR[rip]
	mov	esi, DWORD PTR VGA_CRTC_DATA[rip]
	mov	rdi, rbx
	not	edx
	and	edx, eax
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_SEQ_RESET[rip]
	mov	esi, DWORD PTR VGA_SEQ_ADDRESS[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_SEQ_RST_SR[rip]
	mov	esi, DWORD PTR VGA_SEQ_DATA[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	test	r12d, r12d
	je	.L21
.L11:
	mov	edx, DWORD PTR VGA_CRTC_PRESET_ROW_SCAN[rip]
	mov	esi, DWORD PTR VGA_CRTC_ADDRESS[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_CRTC_DATA[rip]
	xor	edx, edx
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_CRTC_CURSOR_START[rip]
	mov	esi, DWORD PTR VGA_CRTC_ADDRESS[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_CRTC_CS_COO[rip]
	mov	esi, DWORD PTR VGA_CRTC_DATA[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_CRTC_CURSOR_END[rip]
	mov	esi, DWORD PTR VGA_CRTC_ADDRESS[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_CRTC_DATA[rip]
	xor	edx, edx
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_CRTC_START_ADDR_HIGH[rip]
	mov	esi, DWORD PTR VGA_CRTC_ADDRESS[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_CRTC_DATA[rip]
	xor	edx, edx
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_CRTC_START_ADDR_LOW[rip]
	mov	esi, DWORD PTR VGA_CRTC_ADDRESS[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_CRTC_DATA[rip]
	xor	edx, edx
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_CRTC_CURSOR_LOC_HIGH[rip]
	mov	esi, DWORD PTR VGA_CRTC_ADDRESS[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_CRTC_DATA[rip]
	xor	edx, edx
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_CRTC_CURSOR_LOC_LOW[rip]
	mov	esi, DWORD PTR VGA_CRTC_ADDRESS[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_CRTC_DATA[rip]
	mov	edx, 89
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_CRTC_UNDERLINE_LOC[rip]
	mov	esi, DWORD PTR VGA_CRTC_ADDRESS[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_CRTC_UL_UL[rip]
	mov	esi, DWORD PTR VGA_CRTC_DATA[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_AC_MODE_CONTROL[rip]
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	test	r12d, r12d
	je	.L5
.L17:
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	xor	edx, edx
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	xor	edi, edi
	call	VGA_AC_PALETTE@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	xor	edx, edx
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	edi, 1
	call	VGA_AC_PALETTE@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_AC_PAL_B[rip]
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	edi, 2
	call	VGA_AC_PALETTE@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_AC_PAL_G[rip]
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	edi, 3
	call	VGA_AC_PALETTE@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	edx, DWORD PTR VGA_AC_PAL_G[rip]
	mov	rdi, rbx
	or	edx, DWORD PTR VGA_AC_PAL_B[rip]
	call	REG_WRITE1@PLT
	mov	edi, 4
	call	VGA_AC_PALETTE@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_AC_PAL_R[rip]
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	edi, 5
	call	VGA_AC_PALETTE@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	edx, DWORD PTR VGA_AC_PAL_R[rip]
	mov	rdi, rbx
	or	edx, DWORD PTR VGA_AC_PAL_B[rip]
	call	REG_WRITE1@PLT
	mov	edi, 6
	call	VGA_AC_PALETTE@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	edx, DWORD PTR VGA_AC_PAL_SG[rip]
	mov	rdi, rbx
	or	edx, DWORD PTR VGA_AC_PAL_R[rip]
	call	REG_WRITE1@PLT
	mov	edi, 7
	call	VGA_AC_PALETTE@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	edx, DWORD PTR VGA_AC_PAL_R[rip]
	mov	rdi, rbx
	or	edx, DWORD PTR VGA_AC_PAL_G[rip]
	or	edx, DWORD PTR VGA_AC_PAL_B[rip]
	call	REG_WRITE1@PLT
	mov	edi, 8
	call	VGA_AC_PALETTE@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	edx, DWORD PTR VGA_AC_PAL_SR[rip]
	mov	rdi, rbx
	or	edx, DWORD PTR VGA_AC_PAL_SG[rip]
	or	edx, DWORD PTR VGA_AC_PAL_SB[rip]
	call	REG_WRITE1@PLT
	mov	edi, 9
	call	VGA_AC_PALETTE@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	edx, DWORD PTR VGA_AC_PAL_SR[rip]
	mov	rdi, rbx
	or	edx, DWORD PTR VGA_AC_PAL_SG[rip]
	or	edx, DWORD PTR VGA_AC_PAL_SB[rip]
	or	edx, DWORD PTR VGA_AC_PAL_B[rip]
	call	REG_WRITE1@PLT
	mov	edi, 10
	call	VGA_AC_PALETTE@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	edx, DWORD PTR VGA_AC_PAL_SR[rip]
	mov	rdi, rbx
	or	edx, DWORD PTR VGA_AC_PAL_SG[rip]
	or	edx, DWORD PTR VGA_AC_PAL_SB[rip]
	or	edx, DWORD PTR VGA_AC_PAL_G[rip]
	call	REG_WRITE1@PLT
	mov	edi, 11
	call	VGA_AC_PALETTE@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	edx, DWORD PTR VGA_AC_PAL_SR[rip]
	mov	rdi, rbx
	or	edx, DWORD PTR VGA_AC_PAL_SG[rip]
	or	edx, DWORD PTR VGA_AC_PAL_SB[rip]
	or	edx, DWORD PTR VGA_AC_PAL_G[rip]
	or	edx, DWORD PTR VGA_AC_PAL_B[rip]
	call	REG_WRITE1@PLT
	mov	edi, 12
	call	VGA_AC_PALETTE@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	edx, DWORD PTR VGA_AC_PAL_SR[rip]
	mov	rdi, rbx
	or	edx, DWORD PTR VGA_AC_PAL_SG[rip]
	or	edx, DWORD PTR VGA_AC_PAL_SB[rip]
	or	edx, DWORD PTR VGA_AC_PAL_R[rip]
	call	REG_WRITE1@PLT
	mov	edi, 13
	call	VGA_AC_PALETTE@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	edx, DWORD PTR VGA_AC_PAL_SR[rip]
	mov	rdi, rbx
	or	edx, DWORD PTR VGA_AC_PAL_SG[rip]
	or	edx, DWORD PTR VGA_AC_PAL_SB[rip]
	or	edx, DWORD PTR VGA_AC_PAL_R[rip]
	or	edx, DWORD PTR VGA_AC_PAL_B[rip]
	call	REG_WRITE1@PLT
	mov	edi, 14
	call	VGA_AC_PALETTE@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	edx, DWORD PTR VGA_AC_PAL_SR[rip]
	mov	rdi, rbx
	or	edx, DWORD PTR VGA_AC_PAL_SG[rip]
	or	edx, DWORD PTR VGA_AC_PAL_SB[rip]
	or	edx, DWORD PTR VGA_AC_PAL_R[rip]
	or	edx, DWORD PTR VGA_AC_PAL_G[rip]
	call	REG_WRITE1@PLT
	mov	edi, 15
	call	VGA_AC_PALETTE@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	edx, DWORD PTR VGA_AC_PAL_SR[rip]
	mov	rdi, rbx
	or	edx, DWORD PTR VGA_AC_PAL_SG[rip]
	or	edx, DWORD PTR VGA_AC_PAL_SB[rip]
	or	edx, DWORD PTR VGA_AC_PAL_R[rip]
	or	edx, DWORD PTR VGA_AC_PAL_G[rip]
	or	edx, DWORD PTR VGA_AC_PAL_B[rip]
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_AC_OVERSCAN_COLOR[rip]
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	xor	edx, edx
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_AC_COLOR_PLANE_ENABLE[rip]
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	edx, 15
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_AC_COLOR_SELECT[rip]
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	xor	edx, edx
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	test	r12d, r12d
	jne	.L7
	cmp	QWORD PTR VT_VGA_MEMSIZE[rip], 0
	jle	.L7
	xor	ebp, ebp
	.p2align 4,,10
	.p2align 3
.L8:
	xor	edx, edx
	mov	rsi, rbp
	mov	rdi, rbx
	add	rbp, 1
	call	MEM_WRITE1@PLT
	cmp	QWORD PTR VT_VGA_MEMSIZE[rip], rbp
	jg	.L8
.L7:
	mov	edx, DWORD PTR VGA_SEQ_RESET[rip]
	mov	esi, DWORD PTR VGA_SEQ_ADDRESS[rip]
	mov	rdi, rbx
	xor	r13d, r13d
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_SEQ_DATA[rip]
	mov	edx, DWORD PTR VGA_SEQ_RST_SR[rip]
	mov	rdi, rbx
	or	edx, DWORD PTR VGA_SEQ_RST_NAR[rip]
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_CRTC_MODE_CONTROL[rip]
	mov	esi, DWORD PTR VGA_CRTC_ADDRESS[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_CRTC_DATA[rip]
	mov	rdi, rbx
	call	REG_READ1@PLT
	mov	esi, DWORD PTR VGA_CRTC_DATA[rip]
	or	eax, DWORD PTR VGA_CRTC_MC_HR[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_WRITE1@PLT
	test	r12d, r12d
	je	.L22
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	eax, r13d
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L5:
	.cfi_restore_state
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_AC_MC_GA[rip]
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	edx, DWORD PTR VGA_AC_HORIZ_PIXEL_PANNING[rip]
	mov	esi, DWORD PTR VGA_AC_WRITE[rip]
	mov	rdi, rbx
	jmp	.L17
	.p2align 4,,10
	.p2align 3
.L21:
	mov	rdi, r13
	call	vga_initialize_graphics@PLT
	jmp	.L11
	.p2align 4,,10
	.p2align 3
.L22:
	mov	edx, DWORD PTR VGA_GC_MODE[rip]
	mov	esi, DWORD PTR VGA_GC_ADDRESS[rip]
	mov	rdi, rbx
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_GC_DATA[rip]
	mov	rdi, rbx
	mov	edx, 3
	call	REG_WRITE1@PLT
	mov	DWORD PTR [rbx], 3
	mov	edx, DWORD PTR VGA_GC_ENABLE_SET_RESET[rip]
	mov	rdi, rbx
	mov	esi, DWORD PTR VGA_GC_ADDRESS[rip]
	call	REG_WRITE1@PLT
	mov	esi, DWORD PTR VGA_GC_DATA[rip]
	mov	rdi, rbx
	xor	edx, edx
	call	REG_WRITE1@PLT
	movabs	rax, 1095216660735
	mov	QWORD PTR 4[rbx], rax
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	eax, r13d
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
.L19:
	.cfi_restore_state
	lea	rdi, .LC0[rip]
	call	printf@PLT
	mov	r13d, DWORD PTR ENXIO[rip]
	add	rsp, 8
	.cfi_def_cfa_offset 40
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	mov	eax, r13d
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE0:
	.size	vga_initialize, .-vga_initialize
	.comm	VT_VGA_MEMSIZE,8,8
	.comm	VGA_SEQ_RST_SR,4,4
	.comm	VGA_SEQ_RST_NAR,4,4
	.comm	VGA_SEQ_RESET,4,4
	.comm	VGA_SEQ_DATA,4,4
	.comm	VGA_SEQ_ADDRESS,4,4
	.comm	VGA_GEN_MO_IOA,4,4
	.comm	VGA_GEN_MISC_OUTPUT_W,4,4
	.comm	VGA_GEN_MISC_OUTPUT_R,4,4
	.comm	VGA_GEN_IS1_VR,4,4
	.comm	VGA_GEN_IS1_DE,4,4
	.comm	VGA_GEN_INPUT_STAT_1,4,4
	.comm	VGA_GC_MODE,4,4
	.comm	VGA_GC_ENABLE_SET_RESET,4,4
	.comm	VGA_GC_DATA,4,4
	.comm	VGA_GC_ADDRESS,4,4
	.comm	VGA_CRTC_VRE_PR,4,4
	.comm	VGA_CRTC_VERT_RETRACE_END,4,4
	.comm	VGA_CRTC_UNDERLINE_LOC,4,4
	.comm	VGA_CRTC_UL_UL,4,4
	.comm	VGA_CRTC_START_ADDR_LOW,4,4
	.comm	VGA_CRTC_START_ADDR_HIGH,4,4
	.comm	VGA_CRTC_PRESET_ROW_SCAN,4,4
	.comm	VGA_CRTC_MODE_CONTROL,4,4
	.comm	VGA_CRTC_MC_HR,4,4
	.comm	VGA_CRTC_DATA,4,4
	.comm	VGA_CRTC_CURSOR_START,4,4
	.comm	VGA_CRTC_CURSOR_LOC_LOW,4,4
	.comm	VGA_CRTC_CURSOR_LOC_HIGH,4,4
	.comm	VGA_CRTC_CURSOR_END,4,4
	.comm	VGA_CRTC_CS_COO,4,4
	.comm	VGA_CRTC_ADDRESS,4,4
	.comm	VGA_AC_WRITE,4,4
	.comm	VGA_AC_PAL_SR,4,4
	.comm	VGA_AC_PAL_SG,4,4
	.comm	VGA_AC_PAL_SB,4,4
	.comm	VGA_AC_PAL_R,4,4
	.comm	VGA_AC_PAL_G,4,4
	.comm	VGA_AC_PAL_B,4,4
	.comm	VGA_AC_OVERSCAN_COLOR,4,4
	.comm	VGA_AC_MODE_CONTROL,4,4
	.comm	VGA_AC_MC_GA,4,4
	.comm	VGA_AC_HORIZ_PIXEL_PANNING,4,4
	.comm	VGA_AC_COLOR_SELECT,4,4
	.comm	VGA_AC_COLOR_PLANE_ENABLE,4,4
	.comm	ENXIO,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_vt_vga.c_vga_initialize.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"Timeout initializing vt_vga\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	vga_initialize, %function
vga_initialize:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	mov	r3, r1
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r2, .L23
	ldr	r4, [r0]
	sub	sp, sp, #12
	ldr	r1, [r2]
	mov	r5, r0
	mov	r0, r4
	str	r3, [sp]
	bl	REG_READ1
	mov	r1, r0
	ldr	r2, .L23+4
	ldr	r3, .L23+8
	ldr	r2, [r2]
	mov	r0, r4
	orr	r2, r1, r2
	ldr	r1, [r3]
	bl	REG_WRITE1
	ldr	r3, .L23+12
	ldr	r6, .L23+16
	ldr	r2, [r3]
	ldr	r3, .L23+20
	mov	r0, r4
	ldr	r1, [r3]
	bl	REG_WRITE1
	ldr	r1, [r6]
	mov	r0, r4
	bl	REG_READ1
	mov	r3, r0
	ldr	r2, .L23+24
	mov	r0, r4
	ldr	r2, [r2]
	ldr	r1, [r6]
	bic	r2, r3, r2
	bl	REG_WRITE1
	ldr	r7, .L23+28
	ldr	r8, .L23+32
	ldr	r10, .L23+36
	ldr	r9, .L23+40
	b	.L3
.L19:
	subs	r7, r7, #1
	beq	.L18
.L3:
	mov	r0, #10
	bl	DELAY
	mov	r0, r4
	ldr	r1, [r8]
	bl	REG_READ1
	ldr	r3, [r10]
	ldr	r2, [r9]
	orr	r3, r3, r2
	bics	r3, r3, r0
	bne	.L19
	ldr	r3, .L23+20
	mov	r0, r4
	ldr	r1, [r3]
	ldr	r3, .L23+44
	ldr	r2, [r3]
	bl	REG_WRITE1
	ldr	r1, [r6]
	mov	r0, r4
	bl	REG_READ1
	ldr	r3, .L23+48
	ldr	r1, [r6]
	ldr	r2, [r3]
	bic	r2, r0, r2
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, .L23+52
	mov	r0, r4
	ldr	r2, [r3]
	ldr	r3, .L23+56
	ldr	r1, [r3]
	bl	REG_WRITE1
	ldr	r3, .L23+60
	mov	r0, r4
	ldr	r2, [r3]
	ldr	r3, .L23+64
	ldr	r1, [r3]
	bl	REG_WRITE1
	ldr	r3, [sp]
	cmp	r3, #0
	beq	.L20
.L11:
	ldr	r5, .L23+20
	ldr	r3, .L23+68
	ldr	r1, [r5]
	ldr	r2, [r3]
	mov	r0, r4
	bl	REG_WRITE1
	mov	r2, #0
	ldr	r1, [r6]
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, .L23+72
	ldr	r1, [r5]
	ldr	r2, [r3]
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, .L23+76
	ldr	r1, [r6]
	ldr	r2, [r3]
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, .L23+80
	ldr	r1, [r5]
	ldr	r2, [r3]
	mov	r0, r4
	bl	REG_WRITE1
	mov	r2, #0
	ldr	r1, [r6]
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, .L23+84
	ldr	r1, [r5]
	ldr	r2, [r3]
	mov	r0, r4
	bl	REG_WRITE1
	mov	r2, #0
	ldr	r1, [r6]
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, .L23+88
	ldr	r1, [r5]
	ldr	r2, [r3]
	mov	r0, r4
	bl	REG_WRITE1
	mov	r2, #0
	ldr	r1, [r6]
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, .L23+92
	ldr	r1, [r5]
	ldr	r2, [r3]
	mov	r0, r4
	bl	REG_WRITE1
	mov	r2, #0
	ldr	r1, [r6]
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, .L23+96
	ldr	r1, [r5]
	ldr	r2, [r3]
	mov	r0, r4
	bl	REG_WRITE1
	mov	r2, #89
	ldr	r1, [r6]
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, .L23+100
	ldr	r1, [r5]
	ldr	r2, [r3]
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, .L23+104
	ldr	r1, [r6]
	ldr	r2, [r3]
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, [sp]
	ldr	r5, .L23+108
	cmp	r3, #0
	ldr	r3, .L23+112
	mov	r0, r4
	ldr	r2, [r3]
	ldr	r1, [r5]
	bne	.L21
	bl	REG_WRITE1
	ldr	r3, .L23+116
	ldr	r1, [r5]
	ldr	r2, [r3]
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, .L23+120
	ldr	r1, [r5]
	ldr	r2, [r3]
	mov	r0, r4
	bl	REG_WRITE1
	mov	r0, r4
	ldr	r2, [sp]
	ldr	r1, [r5]
	bl	REG_WRITE1
.L6:
	mov	r0, #0
	ldr	r7, [r5]
	bl	VGA_AC_PALETTE
	mov	r1, r7
	mov	r2, r0
	mov	r0, r4
	bl	REG_WRITE1
	mov	r2, #0
	ldr	r1, [r5]
	mov	r0, r4
	bl	REG_WRITE1
	mov	r0, #1
	ldr	r7, [r5]
	bl	VGA_AC_PALETTE
	ldr	r8, .L23+124
	mov	r2, r0
	mov	r1, r7
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r2, [r8]
	ldr	r1, [r5]
	mov	r0, r4
	bl	REG_WRITE1
	mov	r0, #2
	ldr	r7, [r5]
	bl	VGA_AC_PALETTE
	ldr	fp, .L23+128
	mov	r2, r0
	mov	r1, r7
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r2, [fp]
	ldr	r1, [r5]
	mov	r0, r4
	bl	REG_WRITE1
	mov	r0, #3
	ldr	r7, [r5]
	bl	VGA_AC_PALETTE
	mov	r1, r7
	mov	r2, r0
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, [r8]
	ldr	r2, [fp]
	ldr	r1, [r5]
	orr	r2, r2, r3
	mov	r0, r4
	bl	REG_WRITE1
	mov	r0, #4
	ldr	r7, [r5]
	bl	VGA_AC_PALETTE
	ldr	r9, .L23+132
	mov	r2, r0
	mov	r1, r7
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r2, [r9]
	ldr	r1, [r5]
	mov	r0, r4
	bl	REG_WRITE1
	mov	r0, #5
	ldr	r7, [r5]
	bl	VGA_AC_PALETTE
	mov	r1, r7
	mov	r2, r0
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, [r8]
	ldr	r2, [r9]
	ldr	r1, [r5]
	orr	r2, r2, r3
	mov	r0, r4
	bl	REG_WRITE1
	mov	r0, #6
	ldr	r10, [r5]
	bl	VGA_AC_PALETTE
	ldr	r7, .L23+136
	mov	r2, r0
	mov	r1, r10
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, [r9]
	ldr	r2, [r7]
	ldr	r1, [r5]
	orr	r2, r2, r3
	mov	r0, r4
	bl	REG_WRITE1
	mov	r0, #7
	ldr	r10, [r5]
	bl	VGA_AC_PALETTE
	mov	r1, r10
	mov	r2, r0
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r1, [fp]
	ldr	r3, [r9]
	ldr	r2, [r8]
	orr	r3, r3, r1
	orr	r2, r3, r2
	ldr	r1, [r5]
	mov	r0, r4
	bl	REG_WRITE1
	mov	r0, #8
	ldr	r10, [r5]
	bl	VGA_AC_PALETTE
	ldr	fp, .L23+140
	mov	r2, r0
	mov	r1, r10
	mov	r0, r4
	ldr	r10, .L23+144
	bl	REG_WRITE1
	ldr	r0, [r7]
	ldr	r2, [fp]
	ldr	r1, [r10]
	orr	r2, r2, r0
	orr	r2, r2, r1
	mov	r0, r4
	ldr	r1, [r5]
	bl	REG_WRITE1
	ldr	r1, [r5]
	mov	r0, #9
	str	r1, [sp, #4]
	bl	VGA_AC_PALETTE
	ldr	r1, [sp, #4]
	mov	r2, r0
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r1, [r7]
	ldr	r2, [fp]
	ldr	r0, [r10]
	orr	r2, r2, r1
	ldr	r1, [r8]
	orr	r2, r2, r0
	orr	r2, r2, r1
	mov	r0, r4
	ldr	r1, [r5]
	bl	REG_WRITE1
	ldr	r1, [r5]
	mov	r0, #10
	str	r1, [sp, #4]
	bl	VGA_AC_PALETTE
	ldr	r1, [sp, #4]
	mov	r2, r0
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, .L23+128
	ldr	r1, [r7]
	ldr	r2, [fp]
	ldr	r0, [r10]
	orr	r2, r2, r1
	ldr	r1, [r3]
	orr	r2, r2, r0
	orr	r2, r2, r1
	mov	r0, r4
	ldr	r1, [r5]
	bl	REG_WRITE1
	ldr	r1, [r5]
	mov	r0, #11
	str	r1, [sp, #4]
	bl	VGA_AC_PALETTE
	ldr	r1, [sp, #4]
	mov	r2, r0
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, .L23+128
	ldr	r0, [r7]
	ldr	r2, [fp]
	ldr	r1, [r10]
	orr	r2, r2, r0
	ldr	r0, [r3]
	orr	r2, r2, r1
	ldr	r1, [r8]
	orr	r2, r2, r0
	orr	r2, r2, r1
	mov	r0, r4
	ldr	r1, [r5]
	bl	REG_WRITE1
	ldr	r1, [r5]
	mov	r0, #12
	str	r1, [sp, #4]
	bl	VGA_AC_PALETTE
	ldr	r1, [sp, #4]
	mov	r2, r0
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r1, [r7]
	ldr	r2, [fp]
	ldr	r0, [r10]
	orr	r2, r2, r1
	ldr	r1, [r9]
	orr	r2, r2, r0
	orr	r2, r2, r1
	mov	r0, r4
	ldr	r1, [r5]
	bl	REG_WRITE1
	ldr	r1, [r5]
	mov	r0, #13
	str	r1, [sp, #4]
	bl	VGA_AC_PALETTE
	ldr	r1, [sp, #4]
	mov	r2, r0
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r0, [r7]
	ldr	r2, [fp]
	ldr	r1, [r10]
	orr	r2, r2, r0
	ldr	r0, [r9]
	orr	r2, r2, r1
	ldr	r1, [r8]
	orr	r2, r2, r0
	orr	r2, r2, r1
	mov	r0, r4
	ldr	r1, [r5]
	bl	REG_WRITE1
	ldr	r1, [r5]
	mov	r0, #14
	str	r1, [sp, #4]
	bl	VGA_AC_PALETTE
	ldr	r1, [sp, #4]
	mov	r2, r0
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r0, [r7]
	ldr	r2, [fp]
	ldr	r3, .L23+128
	ldr	r1, [r10]
	orr	r2, r2, r0
	ldr	r0, [r9]
	orr	r2, r2, r1
	ldr	r1, [r3]
	orr	r2, r2, r0
	orr	r2, r2, r1
	mov	r0, r4
	ldr	r1, [r5]
	bl	REG_WRITE1
	ldr	r1, [r5]
	mov	r0, #15
	str	r1, [sp, #4]
	bl	VGA_AC_PALETTE
	ldr	r1, [sp, #4]
	mov	r2, r0
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r2, [r7]
	ldr	r3, [fp]
	ldr	r1, [r10]
	orr	r3, r3, r2
	orr	r3, r3, r1
	ldr	r1, .L23+128
	ldr	r2, [r9]
	ldr	r1, [r1]
	orr	r3, r3, r2
	ldr	r2, [r8]
	orr	r3, r3, r1
	orr	r2, r3, r2
	ldr	r1, [r5]
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, .L23+148
	ldr	r1, [r5]
	ldr	r2, [r3]
	mov	r0, r4
	bl	REG_WRITE1
	mov	r2, #0
	ldr	r1, [r5]
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, .L23+152
	ldr	r1, [r5]
	ldr	r2, [r3]
	mov	r0, r4
	bl	REG_WRITE1
	mov	r2, #15
	ldr	r1, [r5]
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, .L23+156
	ldr	r1, [r5]
	ldr	r2, [r3]
	mov	r0, r4
	bl	REG_WRITE1
	mov	r2, #0
	mov	r0, r4
	ldr	r1, [r5]
	bl	REG_WRITE1
	ldr	r7, [sp]
	cmp	r7, #0
	bne	.L7
	ldr	r5, .L23+160
	ldr	r3, [r5]
	cmp	r3, #0
	ble	.L7
.L8:
	mov	r1, r7
	mov	r2, #0
	mov	r0, r4
	bl	MEM_WRITE1
	ldr	r3, [r5]
	add	r7, r7, #1
	cmp	r3, r7
	bgt	.L8
.L7:
	ldr	r3, .L23+52
	mov	r0, r4
	ldr	r2, [r3]
	ldr	r3, .L23+56
	ldr	r1, [r3]
	bl	REG_WRITE1
	ldr	r3, .L23+164
	ldr	r2, .L23+60
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	r1, .L23+64
	orr	r2, r2, r3
	ldr	r1, [r1]
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, .L23+44
	mov	r0, r4
	ldr	r2, [r3]
	ldr	r3, .L23+20
	ldr	r1, [r3]
	bl	REG_WRITE1
	ldr	r1, [r6]
	mov	r0, r4
	bl	REG_READ1
	ldr	r3, .L23+48
	ldr	r1, [r6]
	ldr	r2, [r3]
	orr	r2, r0, r2
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r3, [sp]
	cmp	r3, #0
	movne	r0, #0
	beq	.L22
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L21:
	bl	REG_WRITE1
	mov	r2, #0
	mov	r0, r4
	ldr	r1, [r5]
	bl	REG_WRITE1
	b	.L6
.L20:
	mov	r0, r5
	bl	vga_initialize_graphics
	b	.L11
.L18:
	ldr	r0, .L23+168
	bl	printf
	ldr	r3, .L23+172
	ldr	r0, [r3]
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L22:
	ldr	r3, .L23+176
	ldr	r6, .L23+180
	ldr	r5, .L23+184
	ldr	r2, [r3]
	ldr	r1, [r6]
	mov	r0, r4
	bl	REG_WRITE1
	ldr	r1, [r5]
	mov	r2, #3
	mov	r0, r4
	bl	REG_WRITE1
	mov	r2, #3
	ldr	r3, .L23+188
	ldr	r1, [r6]
	mov	r0, r4
	str	r2, [r4]
	ldr	r2, [r3]
	bl	REG_WRITE1
	ldr	r6, [sp]
	mov	r0, r4
	mov	r2, r6
	ldr	r1, [r5]
	bl	REG_WRITE1
	mov	r3, #255
	mov	r0, r6
	str	r3, [r4, #8]
	str	r3, [r4, #4]
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L24:
	.align	2
.L23:
	.word	VGA_GEN_MISC_OUTPUT_R
	.word	VGA_GEN_MO_IOA
	.word	VGA_GEN_MISC_OUTPUT_W
	.word	VGA_CRTC_VERT_RETRACE_END
	.word	VGA_CRTC_DATA
	.word	VGA_CRTC_ADDRESS
	.word	VGA_CRTC_VRE_PR
	.word	10000
	.word	VGA_GEN_INPUT_STAT_1
	.word	VGA_GEN_IS1_VR
	.word	VGA_GEN_IS1_DE
	.word	VGA_CRTC_MODE_CONTROL
	.word	VGA_CRTC_MC_HR
	.word	VGA_SEQ_RESET
	.word	VGA_SEQ_ADDRESS
	.word	VGA_SEQ_RST_SR
	.word	VGA_SEQ_DATA
	.word	VGA_CRTC_PRESET_ROW_SCAN
	.word	VGA_CRTC_CURSOR_START
	.word	VGA_CRTC_CS_COO
	.word	VGA_CRTC_CURSOR_END
	.word	VGA_CRTC_START_ADDR_HIGH
	.word	VGA_CRTC_START_ADDR_LOW
	.word	VGA_CRTC_CURSOR_LOC_HIGH
	.word	VGA_CRTC_CURSOR_LOC_LOW
	.word	VGA_CRTC_UNDERLINE_LOC
	.word	VGA_CRTC_UL_UL
	.word	VGA_AC_WRITE
	.word	VGA_AC_MODE_CONTROL
	.word	VGA_AC_MC_GA
	.word	VGA_AC_HORIZ_PIXEL_PANNING
	.word	VGA_AC_PAL_B
	.word	VGA_AC_PAL_G
	.word	VGA_AC_PAL_R
	.word	VGA_AC_PAL_SG
	.word	VGA_AC_PAL_SR
	.word	VGA_AC_PAL_SB
	.word	VGA_AC_OVERSCAN_COLOR
	.word	VGA_AC_COLOR_PLANE_ENABLE
	.word	VGA_AC_COLOR_SELECT
	.word	VT_VGA_MEMSIZE
	.word	VGA_SEQ_RST_NAR
	.word	.LC0
	.word	ENXIO
	.word	VGA_GC_MODE
	.word	VGA_GC_ADDRESS
	.word	VGA_GC_DATA
	.word	VGA_GC_ENABLE_SET_RESET
	.size	vga_initialize, .-vga_initialize
	.comm	VT_VGA_MEMSIZE,4,4
	.comm	VGA_SEQ_RST_SR,4,4
	.comm	VGA_SEQ_RST_NAR,4,4
	.comm	VGA_SEQ_RESET,4,4
	.comm	VGA_SEQ_DATA,4,4
	.comm	VGA_SEQ_ADDRESS,4,4
	.comm	VGA_GEN_MO_IOA,4,4
	.comm	VGA_GEN_MISC_OUTPUT_W,4,4
	.comm	VGA_GEN_MISC_OUTPUT_R,4,4
	.comm	VGA_GEN_IS1_VR,4,4
	.comm	VGA_GEN_IS1_DE,4,4
	.comm	VGA_GEN_INPUT_STAT_1,4,4
	.comm	VGA_GC_MODE,4,4
	.comm	VGA_GC_ENABLE_SET_RESET,4,4
	.comm	VGA_GC_DATA,4,4
	.comm	VGA_GC_ADDRESS,4,4
	.comm	VGA_CRTC_VRE_PR,4,4
	.comm	VGA_CRTC_VERT_RETRACE_END,4,4
	.comm	VGA_CRTC_UNDERLINE_LOC,4,4
	.comm	VGA_CRTC_UL_UL,4,4
	.comm	VGA_CRTC_START_ADDR_LOW,4,4
	.comm	VGA_CRTC_START_ADDR_HIGH,4,4
	.comm	VGA_CRTC_PRESET_ROW_SCAN,4,4
	.comm	VGA_CRTC_MODE_CONTROL,4,4
	.comm	VGA_CRTC_MC_HR,4,4
	.comm	VGA_CRTC_DATA,4,4
	.comm	VGA_CRTC_CURSOR_START,4,4
	.comm	VGA_CRTC_CURSOR_LOC_LOW,4,4
	.comm	VGA_CRTC_CURSOR_LOC_HIGH,4,4
	.comm	VGA_CRTC_CURSOR_END,4,4
	.comm	VGA_CRTC_CS_COO,4,4
	.comm	VGA_CRTC_ADDRESS,4,4
	.comm	VGA_AC_WRITE,4,4
	.comm	VGA_AC_PAL_SR,4,4
	.comm	VGA_AC_PAL_SG,4,4
	.comm	VGA_AC_PAL_SB,4,4
	.comm	VGA_AC_PAL_R,4,4
	.comm	VGA_AC_PAL_G,4,4
	.comm	VGA_AC_PAL_B,4,4
	.comm	VGA_AC_OVERSCAN_COLOR,4,4
	.comm	VGA_AC_MODE_CONTROL,4,4
	.comm	VGA_AC_MC_GA,4,4
	.comm	VGA_AC_HORIZ_PIXEL_PANNING,4,4
	.comm	VGA_AC_COLOR_SELECT,4,4
	.comm	VGA_AC_COLOR_PLANE_ENABLE,4,4
	.comm	ENXIO,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
