	.file	"extr_radeon_vm.c_radeon_vm_frag_ptes.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	radeon_vm_frag_ptes, @function
radeon_vm_frag_ptes:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	mov	r15, rsi
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	mov	r13, rdi
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	mov	r12d, edx
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	ebp, r9d
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	ebx, ecx
	mov	ecx, r8d
	sub	rsp, 24
	.cfi_def_cfa_offset 80
	mov	rax, QWORD PTR [rdi]
	cmp	rax, QWORD PTR CHIP_CAYMAN[rip]
	je	.L2
	cmp	rax, QWORD PTR CHIP_ARUBA[rip]
	je	.L2
	mov	eax, DWORD PTR R600_PTE_FRAG_64KB[rip]
	mov	r14d, -128
	mov	esi, 128
	mov	DWORD PTR 4[rsp], eax
	jmp	.L9
	.p2align 4,,10
	.p2align 3
.L2:
	mov	eax, DWORD PTR R600_PTE_FRAG_256KB[rip]
	mov	r14d, -512
	mov	esi, 512
	mov	DWORD PTR 4[rsp], eax
.L9:
	mov	edi, r12d
	mov	DWORD PTR [rsp], ecx
	and	r14d, ebx
	call	ALIGN@PLT
	test	DWORD PTR R600_PTE_SYSTEM[rip], ebp
	mov	r9d, DWORD PTR RADEON_GPU_PAGE_SIZE[rip]
	mov	ecx, DWORD PTR [rsp]
	mov	r10d, eax
	jne	.L4
	test	DWORD PTR R600_PTE_VALID[rip], ebp
	je	.L4
	cmp	eax, r14d
	jge	.L4
	cmp	r12d, eax
	jne	.L12
.L8:
	sub	rsp, 8
	.cfi_def_cfa_offset 88
	mov	r12d, r14d
	mov	rsi, r15
	mov	edx, r10d
	mov	eax, DWORD PTR 12[rsp]
	sub	r12d, r10d
	mov	rdi, r13
	sar	r12d, 3
	or	eax, ebp
	mov	r8d, r12d
	push	rax
	.cfi_def_cfa_offset 96
	mov	DWORD PTR 16[rsp], ecx
	call	radeon_vm_set_pages@PLT
	pop	rcx
	.cfi_def_cfa_offset 88
	pop	rsi
	.cfi_def_cfa_offset 80
	cmp	ebx, r14d
	je	.L1
	mov	r9d, DWORD PTR RADEON_GPU_PAGE_SIZE[rip]
	mov	ecx, DWORD PTR [rsp]
	mov	edx, r14d
	mov	rsi, r15
	mov	rdi, r13
	imul	r12d, r9d
	add	ecx, r12d
	sub	ebx, r14d
	lea	eax, 7[rbx]
	cmovs	ebx, eax
	sub	rsp, 8
	.cfi_def_cfa_offset 88
	push	rbp
	.cfi_def_cfa_offset 96
	mov	r8d, ebx
	sar	r8d, 3
	call	radeon_vm_set_pages@PLT
	pop	rax
	.cfi_def_cfa_offset 88
	pop	rdx
	.cfi_def_cfa_offset 80
	add	rsp, 24
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L4:
	.cfi_restore_state
	sub	ebx, r12d
	mov	edx, r12d
	mov	rsi, r15
	mov	rdi, r13
	lea	eax, 7[rbx]
	cmovs	ebx, eax
	sub	rsp, 8
	.cfi_def_cfa_offset 88
	push	rbp
	.cfi_def_cfa_offset 96
	mov	r8d, ebx
	sar	r8d, 3
	call	radeon_vm_set_pages@PLT
	pop	r9
	.cfi_def_cfa_offset 88
	pop	r10
	.cfi_def_cfa_offset 80
.L1:
	add	rsp, 24
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L12:
	.cfi_restore_state
	mov	DWORD PTR 12[rsp], eax
	sub	eax, r12d
	mov	rdi, r13
	mov	edx, r12d
	lea	r8d, 7[rax]
	mov	rsi, r15
	cmovns	r8d, eax
	sub	rsp, 8
	.cfi_def_cfa_offset 88
	push	rbp
	.cfi_def_cfa_offset 96
	sar	r8d, 3
	mov	DWORD PTR 24[rsp], r8d
	mov	DWORD PTR 16[rsp], ecx
	call	radeon_vm_set_pages@PLT
	mov	r8d, DWORD PTR 24[rsp]
	mov	r9d, DWORD PTR RADEON_GPU_PAGE_SIZE[rip]
	mov	ecx, DWORD PTR 16[rsp]
	pop	rdi
	.cfi_def_cfa_offset 88
	imul	r8d, r9d
	add	ecx, r8d
	pop	r8
	.cfi_def_cfa_offset 80
	mov	r10d, DWORD PTR 12[rsp]
	jmp	.L8
	.cfi_endproc
.LFE0:
	.size	radeon_vm_frag_ptes, .-radeon_vm_frag_ptes
	.comm	RADEON_GPU_PAGE_SIZE,4,4
	.comm	R600_PTE_VALID,4,4
	.comm	R600_PTE_SYSTEM,4,4
	.comm	R600_PTE_FRAG_64KB,4,4
	.comm	R600_PTE_FRAG_256KB,4,4
	.comm	CHIP_CAYMAN,8,8
	.comm	CHIP_ARUBA,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_radeon_vm.c_radeon_vm_frag_ptes.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	radeon_vm_frag_ptes, %function
radeon_vm_frag_ptes:
	@ args = 8, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	ip, .L13
	mov	r5, r0
	ldr	ip, [ip]
	ldr	r0, [r0]
	sub	sp, sp, #28
	cmp	r0, ip
	mov	r8, r1
	mov	r4, r3
	ldr	r9, [sp, #68]
	beq	.L2
	ldr	r3, .L13+4
	ldr	r3, [r3]
	cmp	r0, r3
	beq	.L2
	ldr	r3, .L13+8
	mvn	r7, #127
	ldr	r3, [r3]
	mov	r1, #128
	str	r3, [sp, #20]
	b	.L8
.L2:
	mov	r1, #512
	ldr	r3, .L13+12
	ldr	r7, .L13+16
	ldr	r3, [r3]
	str	r3, [sp, #20]
.L8:
	mov	r0, r2
	str	r2, [sp, #16]
	bl	ALIGN
	ldr	r3, .L13+20
	mov	r6, r0
	ldr	r3, [r3]
	ldr	r2, [sp, #16]
	tst	r9, r3
	and	r7, r7, r4
	bne	.L11
	ldr	r3, .L13+24
	ldr	r10, .L13+28
	ldr	r3, [r3]
	ldr	r1, [r10]
	and	r3, r3, r9
	cmp	r3, #0
	cmpne	r0, r7
	blt	.L5
.L4:
	sub	r4, r4, r2
	add	r3, r4, #7
	cmp	r4, #0
	movlt	r4, r3
	asr	r4, r4, #3
	stmib	sp, {r1, r9}
	mov	r0, r5
	mov	r1, r8
	ldr	r3, [sp, #64]
	str	r4, [sp]
	bl	radeon_vm_set_pages
.L1:
	add	sp, sp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L5:
	cmp	r2, r0
	bne	.L12
.L7:
	ldr	r3, [sp, #20]
	sub	fp, r7, r6
	orr	r3, r9, r3
	asr	fp, fp, #3
	stmib	sp, {r1, r3}
	mov	r2, r6
	mov	r1, r8
	mov	r0, r5
	ldr	r3, [sp, #64]
	str	fp, [sp]
	bl	radeon_vm_set_pages
	cmp	r4, r7
	beq	.L1
	sub	r4, r4, r7
	cmp	r4, #0
	add	r3, r4, #7
	movlt	r4, r3
	ldr	r2, [sp, #64]
	ldr	r3, [r10]
	asr	r4, r4, #3
	mla	r2, fp, r3, r2
	str	r3, [sp, #4]
	mov	r1, r8
	mov	r3, r2
	mov	r0, r5
	mov	r2, r7
	str	r9, [sp, #8]
	str	r4, [sp]
	bl	radeon_vm_set_pages
	add	sp, sp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L11:
	ldr	r3, .L13+28
	ldr	r1, [r3]
	b	.L4
.L12:
	sub	fp, r0, r2
	add	r3, fp, #7
	cmp	fp, #0
	movlt	fp, r3
	asr	fp, fp, #3
	stmib	sp, {r1, r9}
	ldr	r3, [sp, #64]
	mov	r1, r8
	mov	r0, r5
	str	fp, [sp]
	bl	radeon_vm_set_pages
	ldr	r2, [sp, #64]
	ldr	r1, [r10]
	mla	r3, fp, r1, r2
	str	r3, [sp, #64]
	b	.L7
.L14:
	.align	2
.L13:
	.word	CHIP_CAYMAN
	.word	CHIP_ARUBA
	.word	R600_PTE_FRAG_64KB
	.word	R600_PTE_FRAG_256KB
	.word	-512
	.word	R600_PTE_SYSTEM
	.word	R600_PTE_VALID
	.word	RADEON_GPU_PAGE_SIZE
	.size	radeon_vm_frag_ptes, .-radeon_vm_frag_ptes
	.comm	RADEON_GPU_PAGE_SIZE,4,4
	.comm	R600_PTE_VALID,4,4
	.comm	R600_PTE_SYSTEM,4,4
	.comm	R600_PTE_FRAG_64KB,4,4
	.comm	R600_PTE_FRAG_256KB,4,4
	.comm	CHIP_CAYMAN,4,4
	.comm	CHIP_ARUBA,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
