	.file	"extr_wow.c_ath9k_hw_wow_enable.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	ath9k_hw_wow_enable
	.type	ath9k_hw_wow_enable, @function
ath9k_hw_wow_enable:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	mov	ebp, esi
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	mov	rbx, rdi
	sub	rsp, 8
	.cfi_def_cfa_offset 48
	cmp	QWORD PTR 8[rdi], 0
	mov	r13d, DWORD PTR [rdi]
	jne	.L44
.L3:
	mov	esi, DWORD PTR AR_PCIE_PM_CTRL[rip]
	mov	edx, DWORD PTR AR_PMCTRL_HOST_PME_EN[rip]
	mov	rdi, rbx
	or	edx, DWORD PTR AR_PMCTRL_PWR_PM_CTRL_ENA[rip]
	or	edx, DWORD PTR AR_PMCTRL_AUX_PWR_DET[rip]
	or	edx, DWORD PTR AR_PMCTRL_WOW_PME_CLR[rip]
	call	REG_SET_BIT@PLT
	mov	edx, DWORD PTR AR_PMCTRL_WOW_PME_CLR[rip]
	mov	esi, DWORD PTR AR_PCIE_PM_CTRL[rip]
	mov	rdi, rbx
	call	REG_CLR_BIT@PLT
	mov	edi, DWORD PTR AR_WOW_PAT_BACKOFF[rip]
	call	AR_WOW_BACK_OFF_SHIFT@PLT
	mov	esi, DWORD PTR AR_WOW_PATTERN[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_SET_BIT@PLT
	mov	edi, DWORD PTR AR_WOW_CNT_AIFS_CNT[rip]
	call	AR_WOW_AIFS_CNT@PLT
	mov	edi, DWORD PTR AR_WOW_CNT_SLOT_CNT[rip]
	mov	r12d, eax
	call	AR_WOW_SLOT_CNT@PLT
	mov	edi, DWORD PTR AR_WOW_CNT_KA_CNT[rip]
	or	r12d, eax
	call	AR_WOW_KEEP_ALIVE_CNT@PLT
	mov	edx, r12d
	mov	esi, DWORD PTR AR_WOW_COUNT[rip]
	mov	rdi, rbx
	or	edx, eax
	call	REG_SET_BIT@PLT
	test	DWORD PTR AH_WOW_BEACON_MISS[rip], ebp
	je	.L10
	mov	edx, DWORD PTR AR_WOW_BEACON_TIMO[rip]
	mov	esi, DWORD PTR AR_WOW_BCN_TIMO[rip]
	mov	rdi, rbx
	call	REG_WRITE@PLT
.L11:
	mov	rdi, rbx
	call	AR_SREV_9280@PLT
	test	rax, rax
	je	.L45
	.p2align 4,,10
	.p2align 3
.L13:
	mov	edx, DWORD PTR AR_WOW_KEEP_ALIVE_NEVER[rip]
.L12:
	mov	esi, DWORD PTR AR_WOW_KEEP_ALIVE_TIMO[rip]
	mov	rdi, rbx
	call	REG_WRITE@PLT
	mov	esi, DWORD PTR AR_WOW_KEEP_ALIVE_DELAY[rip]
	mov	rdi, rbx
	imul	edx, DWORD PTR KAL_DELAY[rip], 1000
	call	REG_WRITE@PLT
	mov	rdi, rbx
	call	ath9k_wow_create_keep_alive_pattern@PLT
	mov	ecx, DWORD PTR AR_WOW_KEEP_ALIVE_AUTO_DIS[rip]
	test	DWORD PTR AH_WOW_LINK_CHANGE[rip], ebp
	je	.L14
	or	r13d, DWORD PTR AR_WOW_KEEP_ALIVE_FAIL[rip]
.L14:
	mov	edx, DWORD PTR AR_WOW_KEEP_ALIVE_FAIL_DIS[rip]
	mov	esi, DWORD PTR AR_WOW_KEEP_ALIVE[rip]
	mov	rdi, rbx
	call	REG_RMW@PLT
	mov	ecx, DWORD PTR AR_WOW_BMISSTHRESHOLD[rip]
	mov	edx, DWORD PTR AR_RSSI_THR_BM_THR[rip]
	mov	rdi, rbx
	mov	esi, DWORD PTR AR_RSSI_THR[rip]
	call	REG_RMW_FIELD@PLT
	mov	ecx, DWORD PTR AR_WOW_BEACON_FAIL_EN[rip]
	mov	edx, ebp
	and	edx, DWORD PTR AH_WOW_BEACON_MISS[rip]
	je	.L16
	mov	edx, ecx
	or	r13d, DWORD PTR AR_WOW_BEACON_FAIL[rip]
	xor	ecx, ecx
.L16:
	mov	esi, DWORD PTR AR_WOW_BCN_EN[rip]
	mov	rdi, rbx
	call	REG_RMW@PLT
	mov	ecx, DWORD PTR AR_WOW_MAGIC_EN[rip]
	and	ebp, DWORD PTR AH_WOW_MAGIC_PATTERN_EN[rip]
	je	.L18
	mov	ebp, ecx
	or	r13d, DWORD PTR AR_WOW_MAGIC_PAT_FOUND[rip]
	xor	ecx, ecx
.L18:
	mov	edx, DWORD PTR AR_WOW_MAC_INTR_EN[rip]
	mov	esi, DWORD PTR AR_WOW_PATTERN[rip]
	mov	rdi, rbx
	or	edx, ebp
	call	REG_RMW@PLT
	mov	rdi, rbx
	call	AR_SREV_9285_12_OR_LATER@PLT
	test	rax, rax
	jne	.L46
.L19:
	mov	rdi, rbx
	mov	r12d, DWORD PTR AR_PMCTRL_PWR_STATE_D1D3[rip]
	or	r12d, DWORD PTR AR_PMCTRL_HOST_PME_EN[rip]
	or	r12d, DWORD PTR AR_PMCTRL_PWR_PM_CTRL_ENA[rip]
	call	AR_SREV_9300_20_OR_LATER@PLT
	mov	ecx, 0
	mov	rdi, rbx
	mov	edx, r12d
	test	rax, rax
	mov	esi, DWORD PTR AR_PCIE_PM_CTRL[rip]
	cmovne	ecx, DWORD PTR AR_PCIE_PM_CTRL_ENA[rip]
	call	REG_RMW@PLT
	mov	rdi, rbx
	call	AR_SREV_9462@PLT
	test	rax, rax
	jne	.L23
	mov	rdi, rbx
	call	AR_SREV_9565@PLT
	test	rax, rax
	jne	.L23
.L22:
	mov	edx, DWORD PTR AR_STA_ID1_PRESERVE_SEQNUM[rip]
	mov	esi, DWORD PTR AR_STA_ID1[rip]
	mov	rdi, rbx
	call	REG_CLR_BIT@PLT
	mov	rdi, rbx
	call	AR_SREV_9300_20_OR_LATER@PLT
	test	rax, rax
	jne	.L47
.L24:
	mov	rdi, rbx
	call	ath9k_hw_set_powermode_wow_sleep@PLT
	mov	DWORD PTR [rbx], r13d
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L23:
	.cfi_restore_state
	mov	edx, DWORD PTR AR_PMCTRL_PWR_STATE_D1D3[rip]
	mov	esi, DWORD PTR AR_PCIE_PM_CTRL[rip]
	mov	rdi, rbx
	call	REG_CLR_BIT@PLT
	mov	edx, DWORD PTR AR_PMCTRL_PWR_STATE_D1D3_REAL[rip]
	mov	esi, DWORD PTR AR_PCIE_PM_CTRL[rip]
	mov	rdi, rbx
	call	REG_SET_BIT@PLT
	jmp	.L22
	.p2align 4,,10
	.p2align 3
.L10:
	mov	edx, DWORD PTR AR_WOW_BEACON_TIMO_MAX[rip]
	mov	esi, DWORD PTR AR_WOW_BCN_TIMO[rip]
	mov	rdi, rbx
	call	REG_WRITE@PLT
	test	ebp, ebp
	je	.L13
	jmp	.L11
	.p2align 4,,10
	.p2align 3
.L44:
	call	AR_SREV_9300_20_OR_LATER@PLT
	test	rax, rax
	jne	.L48
	mov	rdi, rbx
	call	AR_SREV_9285@PLT
	test	rax, rax
	je	.L5
.L7:
	mov	eax, DWORD PTR AR9285_WA_DEFAULT[rip]
.L6:
	mov	edx, DWORD PTR AR_WA_D3_L1_DISABLE[rip]
	mov	ecx, eax
	mov	esi, DWORD PTR AR_WA[rip]
	mov	rdi, rbx
	or	ecx, edx
	test	DWORD PTR 4[rbx], edx
	mov	edx, DWORD PTR AR_WA_RESET_EN[rip]
	cmovne	eax, ecx
	or	edx, DWORD PTR AR_WA_POR_SHORT[rip]
	mov	ecx, DWORD PTR AR_WA_UNTIE_RESET_EN[rip]
	or	edx, eax
	call	REG_RMW@PLT
	mov	rdi, rbx
	call	AR_SREV_9285_12_OR_LATER@PLT
	test	rax, rax
	je	.L3
	mov	rdi, rbx
	call	ath9k_hw_config_serdes_wow_sleep@PLT
	jmp	.L3
	.p2align 4,,10
	.p2align 3
.L47:
	mov	edi, 13
	call	BIT@PLT
	mov	esi, DWORD PTR AR_PCIE_PHY_REG3[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_SET_BIT@PLT
	mov	edi, 5
	call	BIT@PLT
	mov	esi, DWORD PTR AR_PCU_MISC_MODE3[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	REG_CLR_BIT@PLT
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L46:
	mov	edx, DWORD PTR AR_WOW_PATTERN_SUPPORTED[rip]
	mov	esi, DWORD PTR AR_WOW_PATTERN_MATCH_LT_256B[rip]
	mov	rdi, rbx
	call	REG_WRITE@PLT
	jmp	.L19
	.p2align 4,,10
	.p2align 3
.L48:
	mov	esi, DWORD PTR AR_WA[rip]
	mov	ecx, DWORD PTR AR_WA_UNTIE_RESET_EN[rip]
	mov	rdi, rbx
	mov	edx, DWORD PTR AR_WA_RESET_EN[rip]
	or	ecx, DWORD PTR AR_WA_D3_L1_DISABLE[rip]
	or	edx, DWORD PTR AR_WA_POR_SHORT[rip]
	call	REG_RMW@PLT
	jmp	.L3
	.p2align 4,,10
	.p2align 3
.L45:
	mov	edx, DWORD PTR KAL_TIMEOUT[rip]
	sal	edx, 5
	jmp	.L12
	.p2align 4,,10
	.p2align 3
.L5:
	mov	rdi, rbx
	call	AR_SREV_9287@PLT
	test	rax, rax
	jne	.L7
	mov	eax, DWORD PTR AR9280_WA_DEFAULT[rip]
	jmp	.L6
	.cfi_endproc
.LFE0:
	.size	ath9k_hw_wow_enable, .-ath9k_hw_wow_enable
	.comm	KAL_TIMEOUT,4,4
	.comm	KAL_DELAY,4,4
	.comm	AR_WOW_PAT_BACKOFF,4,4
	.comm	AR_WOW_PATTERN_SUPPORTED,4,4
	.comm	AR_WOW_PATTERN_MATCH_LT_256B,4,4
	.comm	AR_WOW_PATTERN,4,4
	.comm	AR_WOW_MAGIC_PAT_FOUND,4,4
	.comm	AR_WOW_MAGIC_EN,4,4
	.comm	AR_WOW_MAC_INTR_EN,4,4
	.comm	AR_WOW_KEEP_ALIVE_TIMO,4,4
	.comm	AR_WOW_KEEP_ALIVE_NEVER,4,4
	.comm	AR_WOW_KEEP_ALIVE_FAIL_DIS,4,4
	.comm	AR_WOW_KEEP_ALIVE_FAIL,4,4
	.comm	AR_WOW_KEEP_ALIVE_DELAY,4,4
	.comm	AR_WOW_KEEP_ALIVE_AUTO_DIS,4,4
	.comm	AR_WOW_KEEP_ALIVE,4,4
	.comm	AR_WOW_COUNT,4,4
	.comm	AR_WOW_CNT_SLOT_CNT,4,4
	.comm	AR_WOW_CNT_KA_CNT,4,4
	.comm	AR_WOW_CNT_AIFS_CNT,4,4
	.comm	AR_WOW_BMISSTHRESHOLD,4,4
	.comm	AR_WOW_BEACON_TIMO_MAX,4,4
	.comm	AR_WOW_BEACON_TIMO,4,4
	.comm	AR_WOW_BEACON_FAIL_EN,4,4
	.comm	AR_WOW_BEACON_FAIL,4,4
	.comm	AR_WOW_BCN_TIMO,4,4
	.comm	AR_WOW_BCN_EN,4,4
	.comm	AR_WA_UNTIE_RESET_EN,4,4
	.comm	AR_WA_RESET_EN,4,4
	.comm	AR_WA_POR_SHORT,4,4
	.comm	AR_WA_D3_L1_DISABLE,4,4
	.comm	AR_WA,4,4
	.comm	AR_STA_ID1_PRESERVE_SEQNUM,4,4
	.comm	AR_STA_ID1,4,4
	.comm	AR_RSSI_THR_BM_THR,4,4
	.comm	AR_RSSI_THR,4,4
	.comm	AR_PMCTRL_WOW_PME_CLR,4,4
	.comm	AR_PMCTRL_PWR_STATE_D1D3_REAL,4,4
	.comm	AR_PMCTRL_PWR_STATE_D1D3,4,4
	.comm	AR_PMCTRL_PWR_PM_CTRL_ENA,4,4
	.comm	AR_PMCTRL_HOST_PME_EN,4,4
	.comm	AR_PMCTRL_AUX_PWR_DET,4,4
	.comm	AR_PCU_MISC_MODE3,4,4
	.comm	AR_PCIE_PM_CTRL_ENA,4,4
	.comm	AR_PCIE_PM_CTRL,4,4
	.comm	AR_PCIE_PHY_REG3,4,4
	.comm	AR9285_WA_DEFAULT,4,4
	.comm	AR9280_WA_DEFAULT,4,4
	.comm	AH_WOW_MAGIC_PATTERN_EN,4,4
	.comm	AH_WOW_LINK_CHANGE,4,4
	.comm	AH_WOW_BEACON_MISS,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_wow.c_ath9k_hw_wow_enable.c"
	.text
	.align	2
	.global	ath9k_hw_wow_enable
	.syntax unified
	.arm
	.fpu softvfp
	.type	ath9k_hw_wow_enable, %function
ath9k_hw_wow_enable:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r3, [r0, #8]
	mov	r4, r0
	cmp	r3, #0
	mov	r5, r1
	ldr	r7, [r0]
	sub	sp, sp, #12
	bne	.L45
.L3:
	ldr	r10, .L50
	ldr	r8, .L50+4
	ldr	r1, .L50+8
	ldr	r2, [r8]
	ldr	r9, .L50+12
	ldr	r3, [r10]
	ldr	r1, [r1]
	ldr	r6, .L50+16
	orr	r3, r3, r2
	ldr	r2, [r9]
	orr	r3, r3, r1
	orr	r2, r3, r2
	ldr	r1, [r6]
	mov	r0, r4
	bl	REG_SET_BIT
	ldr	r2, [r9]
	ldr	r1, [r6]
	mov	r0, r4
	bl	REG_CLR_BIT
	ldr	r3, .L50+20
	ldr	r9, .L50+24
	ldr	r0, [r3]
	bl	AR_WOW_BACK_OFF_SHIFT
	ldr	r1, [r9]
	mov	r2, r0
	mov	r0, r4
	bl	REG_SET_BIT
	ldr	r3, .L50+28
	ldr	fp, .L50+32
	ldr	r0, [r3]
	bl	AR_WOW_AIFS_CNT
	ldr	r1, .L50+36
	str	r0, [sp, #4]
	ldr	r0, [r1]
	bl	AR_WOW_SLOT_CNT
	ldr	r1, .L50+40
	ldr	r3, [sp, #4]
	orr	r3, r3, r0
	ldr	r0, [r1]
	str	r3, [sp, #4]
	bl	AR_WOW_KEEP_ALIVE_CNT
	ldr	r3, [sp, #4]
	ldr	r1, .L50+44
	orr	r2, r3, r0
	ldr	r1, [r1]
	mov	r0, r4
	bl	REG_SET_BIT
	ldr	r3, [fp]
	tst	r5, r3
	beq	.L10
	ldr	r2, .L50+48
	ldr	r3, .L50+52
	mov	r0, r4
	ldr	r2, [r2]
	ldr	r1, [r3]
	bl	REG_WRITE
.L11:
	mov	r0, r4
	bl	AR_SREV_9280
	cmp	r0, #0
	beq	.L46
.L13:
	ldr	r3, .L50+56
	ldr	r2, [r3]
.L12:
	ldr	r3, .L50+60
	mov	r0, r4
	ldr	r1, [r3]
	bl	REG_WRITE
	ldr	r2, .L50+64
	ldr	r3, .L50+68
	ldr	r2, [r2]
	ldr	r1, [r3]
	rsb	r3, r2, r2, lsl #5
	add	r2, r2, r3, lsl #2
	lsl	r2, r2, #3
	mov	r0, r4
	bl	REG_WRITE
	mov	r0, r4
	bl	ath9k_wow_create_keep_alive_pattern
	ldr	r2, .L50+72
	ldr	r3, .L50+76
	ldr	r2, [r2]
	ldr	r1, .L50+80
	tst	r5, r2
	ldrne	r2, .L50+84
	ldr	r3, [r3]
	ldrne	r2, [r2]
	ldr	r1, [r1]
	orrne	r7, r7, r2
	ldr	r2, .L50+88
	mov	r0, r4
	ldr	r2, [r2]
	bl	REG_RMW
	ldr	r3, .L50+92
	ldr	r2, .L50+96
	ldr	r1, .L50+100
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	r1, [r1]
	mov	r0, r4
	bl	REG_RMW_FIELD
	ldr	r2, [fp]
	ldr	r1, .L50+104
	ands	r2, r5, r2
	ldrne	r3, .L50+108
	ldrne	r2, .L50+112
	ldrne	r3, [r3]
	ldreq	r3, .L50+112
	orrne	r7, r7, r3
	ldrne	r2, [r2]
	movne	r3, #0
	ldreq	r3, [r3]
	ldr	r1, [r1]
	mov	r0, r4
	bl	REG_RMW
	ldr	r3, .L50+116
	ldr	r1, [r9]
	ldr	r2, [r3]
	mov	r0, r4
	ands	r5, r5, r2
	ldrne	r2, .L50+120
	ldrne	r3, .L50+124
	ldrne	r5, [r2]
	ldr	r2, .L50+128
	ldrne	r3, [r3]
	ldreq	r3, .L50+120
	ldr	r2, [r2]
	orrne	r7, r7, r3
	ldreq	r3, [r3]
	movne	r3, #0
	orr	r2, r5, r2
	bl	REG_RMW
	mov	r0, r4
	bl	AR_SREV_9285_12_OR_LATER
	cmp	r0, #0
	bne	.L47
.L19:
	ldr	r9, .L50+132
	ldr	r3, [r10]
	ldr	r5, [r9]
	ldr	r2, [r8]
	orr	r5, r5, r3
	mov	r0, r4
	orr	r5, r5, r2
	bl	AR_SREV_9300_20_OR_LATER
	subs	r3, r0, #0
	ldrne	r3, .L50+136
	mov	r2, r5
	ldrne	r3, [r3]
	ldr	r1, [r6]
	mov	r0, r4
	bl	REG_RMW
	mov	r0, r4
	bl	AR_SREV_9462
	cmp	r0, #0
	bne	.L23
	mov	r0, r4
	bl	AR_SREV_9565
	cmp	r0, #0
	bne	.L23
.L22:
	ldr	r3, .L50+140
	ldr	r2, .L50+144
	ldr	r1, [r3]
	ldr	r2, [r2]
	mov	r0, r4
	bl	REG_CLR_BIT
	mov	r0, r4
	bl	AR_SREV_9300_20_OR_LATER
	cmp	r0, #0
	bne	.L48
.L24:
	mov	r0, r4
	bl	ath9k_hw_set_powermode_wow_sleep
	str	r7, [r4]
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L23:
	ldr	r2, [r9]
	ldr	r1, [r6]
	mov	r0, r4
	bl	REG_CLR_BIT
	ldr	r3, .L50+148
	mov	r0, r4
	ldr	r1, [r6]
	ldr	r2, [r3]
	bl	REG_SET_BIT
	b	.L22
.L10:
	ldr	r3, .L50+52
	ldr	r2, .L50+152
	mov	r0, r4
	ldr	r2, [r2]
	ldr	r1, [r3]
	bl	REG_WRITE
	cmp	r5, #0
	beq	.L13
	b	.L11
.L45:
	bl	AR_SREV_9300_20_OR_LATER
	cmp	r0, #0
	bne	.L49
	mov	r0, r4
	bl	AR_SREV_9285
	cmp	r0, #0
	beq	.L5
.L7:
	ldr	r3, .L50+156
	ldr	r2, [r3]
.L6:
	ldr	r3, .L50+160
	ldr	r1, [r4, #4]
	ldr	r3, [r3]
	ldr	r0, .L50+164
	tst	r3, r1
	orrne	r2, r2, r3
	ldr	r1, .L50+168
	ldr	r3, .L50+172
	ldr	ip, [r1]
	ldr	r3, [r3]
	ldr	r1, .L50+176
	orr	r3, r3, ip
	orr	r2, r3, r2
	ldr	r1, [r1]
	ldr	r3, [r0]
	mov	r0, r4
	bl	REG_RMW
	mov	r0, r4
	bl	AR_SREV_9285_12_OR_LATER
	cmp	r0, #0
	beq	.L3
	mov	r0, r4
	bl	ath9k_hw_config_serdes_wow_sleep
	b	.L3
.L48:
	mov	r0, #13
	bl	BIT
	ldr	r3, .L50+180
	mov	r2, r0
	ldr	r1, [r3]
	mov	r0, r4
	bl	REG_SET_BIT
	mov	r0, #5
	bl	BIT
	ldr	r3, .L50+184
	mov	r2, r0
	ldr	r1, [r3]
	mov	r0, r4
	bl	REG_CLR_BIT
	b	.L24
.L47:
	ldr	r3, .L50+188
	ldr	r2, .L50+192
	mov	r0, r4
	ldr	r2, [r2]
	ldr	r1, [r3]
	bl	REG_WRITE
	b	.L19
.L49:
	ldr	r0, .L50+164
	ldr	r1, .L50+172
	ldr	r3, .L50+160
	ldr	r2, .L50+168
	ldr	ip, [r0]
	ldr	r3, [r3]
	ldr	r0, [r1]
	ldr	r2, [r2]
	ldr	r1, .L50+176
	orr	r2, r0, r2
	ldr	r1, [r1]
	mov	r0, r4
	orr	r3, ip, r3
	bl	REG_RMW
	b	.L3
.L46:
	ldr	r3, .L50+196
	ldr	r2, [r3]
	lsl	r2, r2, #5
	b	.L12
.L5:
	mov	r0, r4
	bl	AR_SREV_9287
	cmp	r0, #0
	bne	.L7
	ldr	r3, .L50+200
	ldr	r2, [r3]
	b	.L6
.L51:
	.align	2
.L50:
	.word	AR_PMCTRL_HOST_PME_EN
	.word	AR_PMCTRL_PWR_PM_CTRL_ENA
	.word	AR_PMCTRL_AUX_PWR_DET
	.word	AR_PMCTRL_WOW_PME_CLR
	.word	AR_PCIE_PM_CTRL
	.word	AR_WOW_PAT_BACKOFF
	.word	AR_WOW_PATTERN
	.word	AR_WOW_CNT_AIFS_CNT
	.word	AH_WOW_BEACON_MISS
	.word	AR_WOW_CNT_SLOT_CNT
	.word	AR_WOW_CNT_KA_CNT
	.word	AR_WOW_COUNT
	.word	AR_WOW_BEACON_TIMO
	.word	AR_WOW_BCN_TIMO
	.word	AR_WOW_KEEP_ALIVE_NEVER
	.word	AR_WOW_KEEP_ALIVE_TIMO
	.word	KAL_DELAY
	.word	AR_WOW_KEEP_ALIVE_DELAY
	.word	AH_WOW_LINK_CHANGE
	.word	AR_WOW_KEEP_ALIVE_AUTO_DIS
	.word	AR_WOW_KEEP_ALIVE
	.word	AR_WOW_KEEP_ALIVE_FAIL
	.word	AR_WOW_KEEP_ALIVE_FAIL_DIS
	.word	AR_WOW_BMISSTHRESHOLD
	.word	AR_RSSI_THR_BM_THR
	.word	AR_RSSI_THR
	.word	AR_WOW_BCN_EN
	.word	AR_WOW_BEACON_FAIL
	.word	AR_WOW_BEACON_FAIL_EN
	.word	AH_WOW_MAGIC_PATTERN_EN
	.word	AR_WOW_MAGIC_EN
	.word	AR_WOW_MAGIC_PAT_FOUND
	.word	AR_WOW_MAC_INTR_EN
	.word	AR_PMCTRL_PWR_STATE_D1D3
	.word	AR_PCIE_PM_CTRL_ENA
	.word	AR_STA_ID1
	.word	AR_STA_ID1_PRESERVE_SEQNUM
	.word	AR_PMCTRL_PWR_STATE_D1D3_REAL
	.word	AR_WOW_BEACON_TIMO_MAX
	.word	AR9285_WA_DEFAULT
	.word	AR_WA_D3_L1_DISABLE
	.word	AR_WA_UNTIE_RESET_EN
	.word	AR_WA_POR_SHORT
	.word	AR_WA_RESET_EN
	.word	AR_WA
	.word	AR_PCIE_PHY_REG3
	.word	AR_PCU_MISC_MODE3
	.word	AR_WOW_PATTERN_MATCH_LT_256B
	.word	AR_WOW_PATTERN_SUPPORTED
	.word	KAL_TIMEOUT
	.word	AR9280_WA_DEFAULT
	.size	ath9k_hw_wow_enable, .-ath9k_hw_wow_enable
	.comm	KAL_TIMEOUT,4,4
	.comm	KAL_DELAY,4,4
	.comm	AR_WOW_PAT_BACKOFF,4,4
	.comm	AR_WOW_PATTERN_SUPPORTED,4,4
	.comm	AR_WOW_PATTERN_MATCH_LT_256B,4,4
	.comm	AR_WOW_PATTERN,4,4
	.comm	AR_WOW_MAGIC_PAT_FOUND,4,4
	.comm	AR_WOW_MAGIC_EN,4,4
	.comm	AR_WOW_MAC_INTR_EN,4,4
	.comm	AR_WOW_KEEP_ALIVE_TIMO,4,4
	.comm	AR_WOW_KEEP_ALIVE_NEVER,4,4
	.comm	AR_WOW_KEEP_ALIVE_FAIL_DIS,4,4
	.comm	AR_WOW_KEEP_ALIVE_FAIL,4,4
	.comm	AR_WOW_KEEP_ALIVE_DELAY,4,4
	.comm	AR_WOW_KEEP_ALIVE_AUTO_DIS,4,4
	.comm	AR_WOW_KEEP_ALIVE,4,4
	.comm	AR_WOW_COUNT,4,4
	.comm	AR_WOW_CNT_SLOT_CNT,4,4
	.comm	AR_WOW_CNT_KA_CNT,4,4
	.comm	AR_WOW_CNT_AIFS_CNT,4,4
	.comm	AR_WOW_BMISSTHRESHOLD,4,4
	.comm	AR_WOW_BEACON_TIMO_MAX,4,4
	.comm	AR_WOW_BEACON_TIMO,4,4
	.comm	AR_WOW_BEACON_FAIL_EN,4,4
	.comm	AR_WOW_BEACON_FAIL,4,4
	.comm	AR_WOW_BCN_TIMO,4,4
	.comm	AR_WOW_BCN_EN,4,4
	.comm	AR_WA_UNTIE_RESET_EN,4,4
	.comm	AR_WA_RESET_EN,4,4
	.comm	AR_WA_POR_SHORT,4,4
	.comm	AR_WA_D3_L1_DISABLE,4,4
	.comm	AR_WA,4,4
	.comm	AR_STA_ID1_PRESERVE_SEQNUM,4,4
	.comm	AR_STA_ID1,4,4
	.comm	AR_RSSI_THR_BM_THR,4,4
	.comm	AR_RSSI_THR,4,4
	.comm	AR_PMCTRL_WOW_PME_CLR,4,4
	.comm	AR_PMCTRL_PWR_STATE_D1D3_REAL,4,4
	.comm	AR_PMCTRL_PWR_STATE_D1D3,4,4
	.comm	AR_PMCTRL_PWR_PM_CTRL_ENA,4,4
	.comm	AR_PMCTRL_HOST_PME_EN,4,4
	.comm	AR_PMCTRL_AUX_PWR_DET,4,4
	.comm	AR_PCU_MISC_MODE3,4,4
	.comm	AR_PCIE_PM_CTRL_ENA,4,4
	.comm	AR_PCIE_PM_CTRL,4,4
	.comm	AR_PCIE_PHY_REG3,4,4
	.comm	AR9285_WA_DEFAULT,4,4
	.comm	AR9280_WA_DEFAULT,4,4
	.comm	AH_WOW_MAGIC_PATTERN_EN,4,4
	.comm	AH_WOW_LINK_CHANGE,4,4
	.comm	AH_WOW_BEACON_MISS,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
