	.file	"extr_sh2_dynarec.c_ds_assemble_entry.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Assemble delay slot at %x\n"
.LC1:
	.string	"<->\n"
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC2:
	.string	"Jump in the delay slot.  This is probably a bug.\n"
	.section	.rodata.str1.1
.LC3:
	.string	"branch: internal\n"
.LC4:
	.string	"branch: external\n"
	.text
	.p2align 4
	.globl	ds_assemble_entry
	.type	ds_assemble_entry, @function
ds_assemble_entry:
.LFB0:
	.cfi_startproc
	endbr64
	mov	rax, QWORD PTR ba[rip]
	push	r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	push	r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	push	r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	push	rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movsx	rbp, edi
	push	rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	mov	esi, DWORD PTR [rax+rbp*4]
	mov	r13, rbp
	mov	rax, QWORD PTR instr_addr[rip]
	mov	r12d, esi
	sub	r12d, DWORD PTR start[rip]
	sar	r12d
	movsx	r14, r12d
	lea	rax, [rax+r14*8]
	cmp	QWORD PTR [rax], 0
	jne	.L2
	mov	rdx, QWORD PTR out[rip]
	mov	QWORD PTR [rax], rdx
.L2:
	lea	rdi, .LC0[rip]
	xor	eax, eax
	lea	rbx, [r14+r14*2]
	call	assem_debug@PLT
	lea	rdi, .LC1[rip]
	xor	eax, eax
	sal	rbx, 3
	call	assem_debug@PLT
	mov	rax, QWORD PTR regs[rip]
	mov	rdx, QWORD PTR HOST_CCREG[rip]
	mov	r8, QWORD PTR CCREG[rip]
	add	rax, rbx
	mov	rdi, QWORD PTR [rax]
	mov	rsi, QWORD PTR 8[rax]
	cmp	QWORD PTR [rdi+rdx*8], r8
	je	.L3
.L4:
	mov	rax, QWORD PTR rs2[rip]
	mov	ecx, DWORD PTR [rax+r14*4]
	mov	rax, QWORD PTR rs1[rip]
	mov	edx, DWORD PTR [rax+r14*4]
	mov	rax, QWORD PTR rs3[rip]
	mov	r8d, DWORD PTR [rax+r14*4]
	call	load_regs@PLT
	mov	rsi, QWORD PTR regs[rip]
	mov	edi, r12d
	add	rsi, rbx
	mov	rdx, QWORD PTR [rsi]
	call	address_generation@PLT
	mov	rax, QWORD PTR itype[rip]
	mov	eax, DWORD PTR [rax+r14*4]
	mov	edx, eax
	and	edx, -9
	cmp	edx, 131
	je	.L25
.L5:
	mov	QWORD PTR is_delayslot[rip], 0
	add	eax, -128
	cmp	eax, 17
	ja	.L6
	lea	rdx, .L8[rip]
	movsx	rax, DWORD PTR [rdx+rax*4]
	add	rax, rdx
	notrack jmp	rax
	.section	.rodata
	.align 4
	.align 4
.L8:
	.long	.L9-.L8
	.long	.L9-.L8
	.long	.L9-.L8
	.long	.L20-.L8
	.long	.L9-.L8
	.long	.L19-.L8
	.long	.L18-.L8
	.long	.L9-.L8
	.long	.L17-.L8
	.long	.L16-.L8
	.long	.L15-.L8
	.long	.L14-.L8
	.long	.L13-.L8
	.long	.L12-.L8
	.long	.L11-.L8
	.long	.L10-.L8
	.long	.L9-.L8
	.long	.L7-.L8
	.text
	.p2align 4,,10
	.p2align 3
.L9:
	lea	rdi, .LC2[rip]
	call	printf@PLT
	.p2align 4,,10
	.p2align 3
.L6:
	mov	rax, QWORD PTR regs[rip]
	mov	rdx, QWORD PTR ba[rip]
	add	rax, rbx
	mov	edx, DWORD PTR [rdx+rbp*4]
	mov	esi, DWORD PTR 16[rax]
	mov	rdi, QWORD PTR 8[rax]
	add	edx, 2
	call	store_regs_bt@PLT
	mov	rax, QWORD PTR ba[rip]
	add	rbx, QWORD PTR regs[rip]
	mov	rdi, QWORD PTR 8[rbx]
	mov	esi, DWORD PTR 16[rbx]
	mov	edx, DWORD PTR [rax+rbp*4]
	add	edx, 2
	call	load_regs_bt@PLT
	mov	rax, QWORD PTR ba[rip]
	mov	edi, DWORD PTR [rax+rbp*4]
	add	edi, 2
	call	internal_branch@PLT
	test	rax, rax
	jne	.L26
	lea	rdi, .LC4[rip]
	xor	eax, eax
	call	assem_debug@PLT
.L22:
	mov	rax, QWORD PTR ba[rip]
	mov	edi, DWORD PTR [rax+rbp*4]
	add	edi, 2
	call	internal_branch@PLT
	mov	rdi, rax
	call	assert@PLT
	mov	rax, QWORD PTR ba[rip]
	mov	edi, DWORD PTR [rax+rbp*4]
	add	edi, 2
	call	internal_branch@PLT
	mov	edi, DWORD PTR out[rip]
	mov	rdx, rax
	mov	rax, QWORD PTR ba[rip]
	mov	esi, DWORD PTR [rax+rbp*4]
	add	esi, 2
	call	add_to_linker@PLT
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	xor	edi, edi
	pop	rbp
	.cfi_def_cfa_offset 32
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	jmp	emit_jmp@PLT
	.p2align 4,,10
	.p2align 3
.L26:
	.cfi_restore_state
	lea	rdi, .LC3[rip]
	xor	eax, eax
	call	assem_debug@PLT
	jmp	.L22
	.p2align 4,,10
	.p2align 3
.L3:
	cmp	r8, QWORD PTR [rsi+rdx*8]
	je	.L4
	mov	edx, DWORD PTR 20[rax]
	mov	rsi, rdi
	mov	rdi, r8
	call	wb_register@PLT
	mov	rax, QWORD PTR regs[rip]
	add	rax, rbx
	mov	rsi, QWORD PTR 8[rax]
	mov	rdi, QWORD PTR [rax]
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L25:
	mov	rax, QWORD PTR regs[rip]
	mov	edx, DWORD PTR MMREG[rip]
	add	rax, rbx
	mov	r8d, edx
	mov	ecx, edx
	mov	rsi, QWORD PTR 8[rax]
	mov	rdi, QWORD PTR [rax]
	call	load_regs@PLT
	mov	rax, QWORD PTR itype[rip]
	mov	eax, DWORD PTR [rax+r14*4]
	jmp	.L5
	.p2align 4,,10
	.p2align 3
.L20:
	mov	rsi, QWORD PTR regs[rip]
	mov	edi, r12d
	add	rsi, rbx
	call	store_assemble@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L19:
	mov	rsi, QWORD PTR regs[rip]
	mov	edi, r12d
	add	rsi, rbx
	call	shiftimm_assemble@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L18:
	mov	rsi, QWORD PTR regs[rip]
	mov	edi, r12d
	add	rsi, rbx
	call	rmw_assemble@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L17:
	mov	rsi, QWORD PTR regs[rip]
	mov	edi, r12d
	add	rsi, rbx
	call	pcrel_assemble@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L7:
	mov	rsi, QWORD PTR regs[rip]
	mov	edi, r12d
	add	rsi, rbx
	call	alu_assemble@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L10:
	mov	rsi, QWORD PTR regs[rip]
	mov	edi, r13d
	add	rsi, rbx
	call	complex_assemble@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L16:
	mov	rsi, QWORD PTR regs[rip]
	mov	edi, r12d
	add	rsi, rbx
	call	multdiv_assemble@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L15:
	mov	rsi, QWORD PTR regs[rip]
	mov	edi, r12d
	add	rsi, rbx
	call	mov_assemble@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L14:
	mov	rsi, QWORD PTR regs[rip]
	mov	edi, r12d
	add	rsi, rbx
	call	load_assemble@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L13:
	mov	rsi, QWORD PTR regs[rip]
	mov	edi, r12d
	add	rsi, rbx
	call	imm8_assemble@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L12:
	mov	rsi, QWORD PTR regs[rip]
	mov	edi, r13d
	add	rsi, rbx
	call	flags_assemble@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L11:
	mov	rsi, QWORD PTR regs[rip]
	mov	edi, r13d
	add	rsi, rbx
	call	ext_assemble@PLT
	jmp	.L6
	.cfi_endproc
.LFE0:
	.size	ds_assemble_entry, .-ds_assemble_entry
	.comm	start,4,4
	.comm	rs3,8,8
	.comm	rs2,8,8
	.comm	rs1,8,8
	.comm	regs,8,8
	.comm	out,8,8
	.comm	itype,8,8
	.comm	is_delayslot,8,8
	.comm	instr_addr,8,8
	.comm	ba,8,8
	.comm	MMREG,4,4
	.comm	HOST_CCREG,8,8
	.comm	CCREG,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_sh2_dynarec.c_ds_assemble_entry.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"Assemble delay slot at %x\012\000"
	.align	2
.LC1:
	.ascii	"<->\012\000"
	.align	2
.LC2:
	.ascii	"Jump in the delay slot.  This is probably a bug.\012"
	.ascii	"\000"
	.align	2
.LC3:
	.ascii	"branch: internal\012\000"
	.align	2
.LC4:
	.ascii	"branch: external\012\000"
	.text
	.align	2
	.global	ds_assemble_entry
	.syntax unified
	.arm
	.fpu softvfp
	.type	ds_assemble_entry, %function
ds_assemble_entry:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, lr}
	ldr	r6, .L28
	ldr	r2, .L28+4
	ldr	r3, [r6]
	ldr	r4, [r2]
	ldr	r1, [r3, r0, lsl #2]
	ldr	r3, .L28+8
	sub	r4, r1, r4
	ldr	r3, [r3]
	asr	r4, r4, #1
	ldr	r2, [r3, r4, lsl #2]
	ldr	r9, .L28+12
	cmp	r2, #0
	ldreq	r2, [r9]
	sub	sp, sp, #8
	streq	r2, [r3, r4, lsl #2]
	mov	r5, r0
	ldr	r7, .L28+16
	ldr	r0, .L28+20
	bl	assem_debug
	ldr	r0, .L28+24
	bl	assem_debug
	ldr	r3, [r7]
	ldr	r2, .L28+28
	ldr	r0, [r3, r4, lsl #4]
	ldr	r2, [r2]
	ldr	r1, .L28+32
	ldr	ip, [r0, r2, lsl #2]
	ldr	r1, [r1]
	add	r3, r3, r4, lsl #4
	cmp	ip, r1
	lsl	r8, r4, #4
	ldr	r1, [r3, #4]
	beq	.L3
.L4:
	ldr	ip, .L28+36
	ldr	r3, .L28+40
	ldr	ip, [ip]
	ldr	r2, .L28+44
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	ip, [ip, r4, lsl #2]
	ldr	r3, [r3, r4, lsl #2]
	ldr	r2, [r2, r4, lsl #2]
	str	ip, [sp]
	bl	load_regs
	ldr	r1, [r7]
	ldr	r10, .L28+48
	ldr	r2, [r1, r4, lsl #4]
	mov	r0, r4
	add	r1, r1, r8
	bl	address_generation
	ldr	r3, [r10]
	ldr	r3, [r3, r4, lsl #2]
	bic	r2, r3, #8
	cmp	r2, #131
	beq	.L27
.L5:
	mov	r1, #0
	ldr	r2, .L28+52
	sub	r3, r3, #128
	str	r1, [r2]
	cmp	r3, #17
	ldrls	pc, [pc, r3, asl #2]
	b	.L6
.L8:
	.word	.L9
	.word	.L9
	.word	.L9
	.word	.L20
	.word	.L9
	.word	.L19
	.word	.L18
	.word	.L9
	.word	.L17
	.word	.L16
	.word	.L15
	.word	.L14
	.word	.L13
	.word	.L12
	.word	.L11
	.word	.L10
	.word	.L9
	.word	.L7
.L9:
	ldr	r0, .L28+56
	bl	printf
.L6:
	ldr	r2, [r6]
	ldr	r3, [r7]
	ldr	r2, [r2, r5, lsl #2]
	add	r3, r3, r8
	ldmib	r3, {r0, r1}
	add	r2, r2, #2
	bl	store_regs_bt
	ldr	r2, [r6]
	ldr	r3, [r7]
	ldr	r2, [r2, r5, lsl #2]
	add	r8, r3, r8
	ldmib	r8, {r0, r1}
	add	r2, r2, #2
	bl	load_regs_bt
	ldr	r3, [r6]
	ldr	r0, [r3, r5, lsl #2]
	add	r0, r0, #2
	bl	internal_branch
	cmp	r0, #0
	ldrne	r0, .L28+60
	ldreq	r0, .L28+64
	bl	assem_debug
	ldr	r3, [r6]
	ldr	r0, [r3, r5, lsl #2]
	add	r0, r0, #2
	bl	internal_branch
	bl	assert
	ldr	r3, [r6]
	ldr	r6, [r9]
	ldr	r4, [r3, r5, lsl #2]
	add	r4, r4, #2
	mov	r0, r4
	bl	internal_branch
	mov	r1, r4
	mov	r2, r0
	mov	r0, r6
	bl	add_to_linker
	mov	r0, #0
	add	sp, sp, #8
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, lr}
	b	emit_jmp
.L3:
	ldr	r2, [r1, r2, lsl #2]
	cmp	ip, r2
	beq	.L4
	mov	r1, r0
	ldr	r2, [r3, #12]
	mov	r0, ip
	bl	wb_register
	ldr	r3, [r7]
	add	r2, r3, r8
	ldr	r1, [r2, #4]
	ldr	r0, [r3, r4, lsl #4]
	b	.L4
.L27:
	ldr	r3, [r7]
	ldr	r2, .L28+68
	ldr	r0, [r3, r4, lsl #4]
	add	r1, r3, r8
	ldr	r3, [r2]
	ldr	r1, [r1, #4]
	mov	r2, r3
	str	r3, [sp]
	bl	load_regs
	ldr	r3, [r10]
	ldr	r3, [r3, r4, lsl #2]
	b	.L5
.L20:
	ldr	r1, [r7]
	mov	r0, r4
	add	r1, r1, r8
	bl	store_assemble
	b	.L6
.L19:
	ldr	r1, [r7]
	mov	r0, r4
	add	r1, r1, r8
	bl	shiftimm_assemble
	b	.L6
.L18:
	ldr	r1, [r7]
	mov	r0, r4
	add	r1, r1, r8
	bl	rmw_assemble
	b	.L6
.L17:
	ldr	r1, [r7]
	mov	r0, r4
	add	r1, r1, r8
	bl	pcrel_assemble
	b	.L6
.L16:
	ldr	r1, [r7]
	mov	r0, r4
	add	r1, r1, r8
	bl	multdiv_assemble
	b	.L6
.L15:
	ldr	r1, [r7]
	mov	r0, r4
	add	r1, r1, r8
	bl	mov_assemble
	b	.L6
.L14:
	ldr	r1, [r7]
	mov	r0, r4
	add	r1, r1, r8
	bl	load_assemble
	b	.L6
.L13:
	ldr	r1, [r7]
	mov	r0, r4
	add	r1, r1, r8
	bl	imm8_assemble
	b	.L6
.L12:
	ldr	r1, [r7]
	mov	r0, r5
	add	r1, r1, r8
	bl	flags_assemble
	b	.L6
.L11:
	ldr	r1, [r7]
	mov	r0, r5
	add	r1, r1, r8
	bl	ext_assemble
	b	.L6
.L10:
	ldr	r1, [r7]
	mov	r0, r5
	add	r1, r1, r8
	bl	complex_assemble
	b	.L6
.L7:
	ldr	r1, [r7]
	mov	r0, r4
	add	r1, r1, r8
	bl	alu_assemble
	b	.L6
.L29:
	.align	2
.L28:
	.word	ba
	.word	start
	.word	instr_addr
	.word	out
	.word	regs
	.word	.LC0
	.word	.LC1
	.word	HOST_CCREG
	.word	CCREG
	.word	rs3
	.word	rs2
	.word	rs1
	.word	itype
	.word	is_delayslot
	.word	.LC2
	.word	.LC3
	.word	.LC4
	.word	MMREG
	.size	ds_assemble_entry, .-ds_assemble_entry
	.comm	start,4,4
	.comm	rs3,4,4
	.comm	rs2,4,4
	.comm	rs1,4,4
	.comm	regs,4,4
	.comm	out,4,4
	.comm	itype,4,4
	.comm	is_delayslot,4,4
	.comm	instr_addr,4,4
	.comm	ba,4,4
	.comm	MMREG,4,4
	.comm	HOST_CCREG,4,4
	.comm	CCREG,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
