	.file	"extr_i386.c_ix86_expand_vector_init_one_nonzero.c"
	.intel_syntax noprefix
	.text
	.section	.text.unlikely,"ax",@progbits
.LCOLDB0:
	.text
.LHOTB0:
	.p2align 4
	.type	ix86_expand_vector_init_one_nonzero, @function
ix86_expand_vector_init_one_nonzero:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	lea	eax, -128[rsi]
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 24
	.cfi_def_cfa_offset 80
	cmp	eax, 9
	ja	.L22
	mov	r12d, edx
	lea	rdx, .L4[rip]
	mov	r13d, edi
	mov	ebp, esi
	movsx	rax, DWORD PTR [rdx+rax*4]
	mov	r14d, ecx
	mov	ebx, r8d
	add	rax, rdx
	notrack jmp	rax
	.section	.rodata
	.align 4
	.align 4
.L4:
	.long	.L7-.L4
	.long	.L23-.L4
	.long	.L8-.L4
	.long	.L8-.L4
	.long	.L7-.L4
	.long	.L6-.L4
	.long	.L6-.L4
	.long	.L5-.L4
	.long	.L5-.L4
	.long	.L23-.L4
	.text
	.p2align 4,,10
	.p2align 3
.L6:
	xor	eax, eax
	test	edi, edi
	je	.L1
.L5:
	xor	eax, eax
	test	ebx, ebx
	je	.L41
.L1:
	add	rsp, 24
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L23:
	.cfi_restore_state
	mov	r15d, 130
.L3:
	xor	eax, eax
	test	ebx, ebx
	jne	.L1
	mov	edi, ebp
	call	GET_MODE_INNER@PLT
	mov	edi, DWORD PTR SImode[rip]
	mov	edx, r14d
	mov	ecx, 1
	mov	esi, eax
	call	convert_modes@PLT
	mov	edi, r15d
	mov	ebx, eax
	call	gen_reg_rtx@PLT
	xor	r8d, r8d
	mov	ecx, ebx
	mov	esi, r15d
	mov	edx, eax
	mov	edi, r13d
	mov	r14d, eax
	call	ix86_expand_vector_init_one_nonzero
	test	eax, eax
	je	.L42
.L21:
	mov	esi, r14d
	mov	edi, ebp
.L39:
	call	gen_lowpart@PLT
	mov	edi, r12d
	mov	esi, eax
	call	emit_move_insn@PLT
	add	rsp, 24
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	eax, 1
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L7:
	.cfi_restore_state
	xor	eax, eax
	mov	r15d, 133
	test	edi, edi
	jne	.L3
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L8:
	mov	edi, r12d
	call	REG_P@PLT
	test	eax, eax
	je	.L12
	mov	edi, r12d
	call	REGNO@PLT
	cmp	eax, DWORD PTR FIRST_PSEUDO_REGISTER[rip]
	jge	.L43
.L12:
	mov	edi, ebp
	call	gen_reg_rtx@PLT
	mov	edi, ebp
	mov	r13d, eax
	call	GET_MODE_INNER@PLT
	mov	esi, r14d
	mov	edi, eax
	call	force_reg@PLT
	mov	edi, ebp
	mov	esi, eax
	call	gen_rtx_VEC_DUPLICATE@PLT
	mov	r15d, DWORD PTR const1_rtx[rip]
	mov	edi, ebp
	mov	r14d, eax
	call	CONST0_RTX@PLT
	mov	ecx, r15d
	mov	esi, r14d
	mov	edi, ebp
	mov	edx, eax
	call	gen_rtx_VEC_MERGE@PLT
	mov	edi, DWORD PTR VOIDmode[rip]
	mov	esi, r13d
	mov	edx, eax
	call	gen_rtx_SET@PLT
	mov	edi, eax
	call	emit_insn@PLT
	test	ebx, ebx
	jne	.L10
	cmp	r12d, r13d
	je	.L38
.L16:
	mov	esi, r13d
	mov	edi, r12d
	call	emit_move_insn@PLT
.L38:
	add	rsp, 24
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	eax, 1
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L41:
	.cfi_restore_state
	mov	edi, ebp
	call	GET_MODE_INNER@PLT
	mov	esi, r14d
	mov	edi, eax
	call	force_reg@PLT
	mov	edi, ebp
	mov	r13d, eax
	call	GET_MODE_INNER@PLT
	mov	edi, eax
	call	CONST0_RTX@PLT
	mov	esi, r13d
	mov	edi, ebp
	mov	edx, eax
	call	gen_rtx_VEC_CONCAT@PLT
	mov	edi, DWORD PTR VOIDmode[rip]
	mov	esi, r12d
	mov	edx, eax
	call	gen_rtx_SET@PLT
	mov	edi, eax
	call	emit_insn@PLT
	add	rsp, 24
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	eax, 1
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L43:
	.cfi_restore_state
	mov	edi, ebp
	call	GET_MODE_INNER@PLT
	mov	esi, r14d
	mov	edi, eax
	call	force_reg@PLT
	mov	edi, ebp
	mov	esi, eax
	call	gen_rtx_VEC_DUPLICATE@PLT
	mov	r14d, DWORD PTR const1_rtx[rip]
	mov	edi, ebp
	mov	r13d, eax
	call	CONST0_RTX@PLT
	mov	ecx, r14d
	mov	esi, r13d
	mov	edi, ebp
	mov	edx, eax
	call	gen_rtx_VEC_MERGE@PLT
	mov	edi, DWORD PTR VOIDmode[rip]
	mov	esi, r12d
	mov	edx, eax
	call	gen_rtx_SET@PLT
	mov	edi, eax
	call	emit_insn@PLT
	test	ebx, ebx
	je	.L38
	mov	r13d, r12d
.L10:
	xor	r15d, r15d
	cmp	ebx, 1
	setne	r15b
	cmp	ebp, 131
	je	.L14
	mov	ecx, DWORD PTR TARGET_SSE2[rip]
	test	ecx, ecx
	jne	.L44
	mov	edi, 131
	call	gen_reg_rtx@PLT
	mov	esi, r13d
	mov	edi, 131
	mov	r14d, eax
	call	gen_lowpart@PLT
	mov	edi, r14d
	mov	r13d, r14d
	mov	esi, eax
	call	emit_move_insn@PLT
.L14:
	cmp	ebx, 3
	je	.L17
	mov	edi, 5
	call	GEN_INT@PLT
	xor	edi, edi
	cmp	ebx, 2
	setne	dil
	mov	r14d, eax
	add	edi, 4
.L18:
	call	GEN_INT@PLT
	mov	edi, r15d
	mov	DWORD PTR 12[rsp], eax
	call	GEN_INT@PLT
	mov	edi, 1
	mov	ebx, eax
	call	GEN_INT@PLT
	sub	rsp, 8
	.cfi_def_cfa_offset 88
	mov	edx, r13d
	mov	r8d, ebx
	push	r14
	.cfi_def_cfa_offset 96
	mov	r9d, DWORD PTR 28[rsp]
	mov	ecx, eax
	mov	esi, r13d
	mov	edi, r13d
	call	gen_sse_shufps_1@PLT
	mov	edi, eax
	call	emit_insn@PLT
	pop	rax
	.cfi_def_cfa_offset 88
	pop	rdx
	.cfi_def_cfa_offset 80
	cmp	ebp, 131
	je	.L19
	mov	esi, r13d
	mov	edi, 130
	jmp	.L39
	.p2align 4,,10
	.p2align 3
.L17:
	mov	edi, 4
	call	GEN_INT@PLT
	mov	edi, 5
	mov	r14d, eax
	jmp	.L18
	.p2align 4,,10
	.p2align 3
.L44:
	xor	edi, edi
	cmp	ebx, 3
	setne	dil
	call	GEN_INT@PLT
	xor	edi, edi
	cmp	ebx, 2
	setne	dil
	mov	ebp, eax
	call	GEN_INT@PLT
	mov	edi, r15d
	mov	ebx, eax
	call	GEN_INT@PLT
	mov	edi, 1
	mov	r14d, eax
	call	GEN_INT@PLT
	mov	edi, r13d
	mov	r9d, ebp
	mov	r8d, ebx
	mov	edx, eax
	mov	ecx, r14d
	mov	esi, r13d
	call	gen_sse2_pshufd_1@PLT
	mov	edi, eax
	call	emit_insn@PLT
	cmp	r12d, r13d
	je	.L38
	jmp	.L16
	.p2align 4,,10
	.p2align 3
.L42:
	call	gcc_unreachable@PLT
	jmp	.L21
	.p2align 4,,10
	.p2align 3
.L19:
	cmp	r13d, r12d
	je	.L38
	jmp	.L16
	.cfi_endproc
	.section	.text.unlikely
	.cfi_startproc
	.type	ix86_expand_vector_init_one_nonzero.cold, @function
ix86_expand_vector_init_one_nonzero.cold:
.LFSB0:
.L22:
	.cfi_def_cfa_offset 80
	.cfi_offset 3, -56
	.cfi_offset 6, -48
	.cfi_offset 12, -40
	.cfi_offset 13, -32
	.cfi_offset 14, -24
	.cfi_offset 15, -16
	xor	eax, eax
	jmp	.L1
	.cfi_endproc
.LFE0:
	.text
	.size	ix86_expand_vector_init_one_nonzero, .-ix86_expand_vector_init_one_nonzero
	.section	.text.unlikely
	.size	ix86_expand_vector_init_one_nonzero.cold, .-ix86_expand_vector_init_one_nonzero.cold
.LCOLDE0:
	.text
.LHOTE0:
	.comm	const1_rtx,4,4
	.comm	VOIDmode,4,4
	.comm	TARGET_SSE2,4,4
	.comm	SImode,4,4
	.comm	FIRST_PSEUDO_REGISTER,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_i386.c_ix86_expand_vector_init_one_nonzero.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	ix86_expand_vector_init_one_nonzero, %function
ix86_expand_vector_init_one_nonzero:
	@ args = 4, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, lr}
	sub	ip, r1, #128
	sub	sp, sp, #16
	mov	r4, r1
	mov	r7, r0
	mov	r8, r2
	mov	r5, r3
	ldr	r6, [sp, #48]
	cmp	ip, #9
	ldrls	pc, [pc, ip, asl #2]
	b	.L28
.L4:
	.word	.L7
	.word	.L23
	.word	.L8
	.word	.L8
	.word	.L7
	.word	.L6
	.word	.L6
	.word	.L5
	.word	.L5
	.word	.L23
.L6:
	cmp	r0, #0
	beq	.L28
.L5:
	cmp	r6, #0
	beq	.L40
.L28:
	mov	r0, #0
.L1:
	add	sp, sp, #16
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
.L23:
	mov	r9, #130
.L3:
	cmp	r6, #0
	bne	.L28
	ldr	r3, .L44
	mov	r0, r4
	ldr	r10, [r3]
	bl	GET_MODE_INNER
	mov	r2, r5
	mov	r1, r0
	mov	r3, #1
	mov	r0, r10
	bl	convert_modes
	mov	r10, r0
	mov	r0, r9
	bl	gen_reg_rtx
	mov	r5, r0
	mov	r3, r10
	mov	r1, r9
	mov	r0, r7
	mov	r2, r5
	str	r6, [sp]
	bl	ix86_expand_vector_init_one_nonzero
	cmp	r0, #0
	beq	.L41
.L21:
	mov	r1, r5
	mov	r0, r4
.L38:
	bl	gen_lowpart
	mov	r1, r0
	mov	r0, r8
	bl	emit_move_insn
.L36:
	mov	r0, #1
	add	sp, sp, #16
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
.L7:
	cmp	r0, #0
	movne	r9, #133
	bne	.L3
	b	.L28
.L8:
	mov	r0, r2
	bl	REG_P
	cmp	r0, #0
	beq	.L12
	mov	r0, r8
	bl	REGNO
	ldr	r3, .L44+4
	ldr	r3, [r3]
	cmp	r0, r3
	bge	.L42
.L12:
	mov	r0, r4
	bl	gen_reg_rtx
	mov	r7, r0
	mov	r0, r4
	bl	GET_MODE_INNER
	mov	r1, r5
	bl	force_reg
	mov	r1, r0
	mov	r0, r4
	bl	gen_rtx_VEC_DUPLICATE
	mov	r5, r0
	mov	r0, r4
	bl	CONST0_RTX
	ldr	r3, .L44+8
	mov	r2, r0
	mov	r1, r5
	ldr	r3, [r3]
	mov	r0, r4
	bl	gen_rtx_VEC_MERGE
	ldr	r3, .L44+12
	mov	r2, r0
	mov	r1, r7
	ldr	r0, [r3]
	bl	gen_rtx_SET
	bl	emit_insn
	cmp	r6, #0
	bne	.L10
	cmp	r8, r7
	beq	.L36
.L37:
	mov	r1, r7
	mov	r0, r8
	bl	emit_move_insn
	mov	r0, #1
	b	.L1
.L40:
	mov	r0, r4
	bl	GET_MODE_INNER
	mov	r1, r5
	bl	force_reg
	mov	r5, r0
	mov	r0, r4
	bl	GET_MODE_INNER
	bl	CONST0_RTX
	mov	r1, r5
	mov	r2, r0
	mov	r0, r4
	bl	gen_rtx_VEC_CONCAT
	ldr	r3, .L44+12
	mov	r2, r0
	mov	r1, r8
	ldr	r0, [r3]
	bl	gen_rtx_SET
	bl	emit_insn
	mov	r0, #1
	add	sp, sp, #16
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
.L42:
	mov	r0, r4
	bl	GET_MODE_INNER
	mov	r1, r5
	bl	force_reg
	mov	r1, r0
	mov	r0, r4
	bl	gen_rtx_VEC_DUPLICATE
	mov	r5, r0
	mov	r0, r4
	bl	CONST0_RTX
	ldr	r3, .L44+8
	mov	r2, r0
	mov	r1, r5
	ldr	r3, [r3]
	mov	r0, r4
	bl	gen_rtx_VEC_MERGE
	ldr	r3, .L44+12
	mov	r2, r0
	mov	r1, r8
	ldr	r0, [r3]
	bl	gen_rtx_SET
	bl	emit_insn
	cmp	r6, #0
	beq	.L36
	mov	r7, r8
.L10:
	subs	r9, r6, #1
	movne	r9, #1
	cmp	r4, #131
	beq	.L14
	ldr	r3, .L44+16
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L43
	mov	r0, #131
	bl	gen_reg_rtx
	mov	r1, r7
	mov	r5, r0
	mov	r0, #131
	bl	gen_lowpart
	mov	r1, r0
	mov	r0, r5
	bl	emit_move_insn
	mov	r7, r5
.L14:
	mov	r0, #1
	bl	GEN_INT
	mov	r5, r0
	mov	r0, r9
	bl	GEN_INT
	cmp	r6, #2
	mov	r9, r0
	beq	.L17
	mov	r0, #5
	bl	GEN_INT
	cmp	r6, #3
	mov	r6, r0
	moveq	r0, #4
	movne	r0, #5
.L18:
	bl	GEN_INT
	mov	r1, r7
	mov	r3, r5
	mov	r2, r7
	str	r0, [sp, #8]
	str	r6, [sp, #4]
	mov	r0, r7
	str	r9, [sp]
	bl	gen_sse_shufps_1
	bl	emit_insn
	cmp	r4, #131
	movne	r1, r7
	movne	r0, #130
	bne	.L38
	cmp	r7, r8
	beq	.L36
	b	.L37
.L17:
	mov	r0, #4
	bl	GEN_INT
	mov	r6, r0
	mov	r0, #5
	b	.L18
.L43:
	mov	r0, #1
	bl	GEN_INT
	mov	r4, r0
	mov	r0, r9
	bl	GEN_INT
	mov	r5, r0
	subs	r0, r6, #2
	movne	r0, #1
	bl	GEN_INT
	mov	r3, r0
	subs	r0, r6, #3
	movne	r0, #1
	mov	r6, r3
	bl	GEN_INT
	mov	r3, r5
	mov	r2, r4
	mov	r1, r7
	str	r0, [sp, #4]
	str	r6, [sp]
	mov	r0, r7
	bl	gen_sse2_pshufd_1
	bl	emit_insn
	cmp	r8, r7
	beq	.L36
	b	.L37
.L41:
	bl	gcc_unreachable
	b	.L21
.L45:
	.align	2
.L44:
	.word	SImode
	.word	FIRST_PSEUDO_REGISTER
	.word	const1_rtx
	.word	VOIDmode
	.word	TARGET_SSE2
	.size	ix86_expand_vector_init_one_nonzero, .-ix86_expand_vector_init_one_nonzero
	.comm	const1_rtx,4,4
	.comm	VOIDmode,4,4
	.comm	TARGET_SSE2,4,4
	.comm	SImode,4,4
	.comm	FIRST_PSEUDO_REGISTER,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
