	.file	"extr_flash_qio_mode.c_bootloader_enable_qio_mode.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC0:
	.string	"Probing for QIO mode enable..."
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Raw SPI flash chip id 0x%x"
	.section	.rodata.str1.8
	.align 8
.LC2:
	.string	"Manufacturer ID 0x%02x chip ID 0x%04x"
	.align 8
.LC3:
	.string	"Enabling QIO for flash chip %s"
	.align 8
.LC4:
	.string	"Enabling default flash chip QIO"
	.text
	.p2align 4
	.globl	bootloader_enable_qio_mode
	.type	bootloader_enable_qio_mode, @function
bootloader_enable_qio_mode:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	lea	rsi, .LC0[rip]
	xor	eax, eax
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	sub	rsp, 8
	.cfi_def_cfa_offset 48
	mov	edi, DWORD PTR TAG[rip]
	call	ESP_LOGD@PLT
	lea	rdi, g_rom_flashchip[rip]
	call	esp_rom_spiflash_wait_idle@PLT
	mov	r13d, DWORD PTR g_rom_flashchip[rip]
	mov	edi, DWORD PTR TAG[rip]
	xor	eax, eax
	lea	rsi, .LC1[rip]
	mov	r12d, r13d
	mov	edx, r13d
	movzx	r13d, r13w
	call	ESP_LOGD@PLT
	sar	r12d, 16
	mov	ecx, r13d
	xor	eax, eax
	mov	edi, DWORD PTR TAG[rip]
	movzx	r12d, r12b
	lea	rsi, .LC2[rip]
	mov	rdx, r12
	call	ESP_LOGD@PLT
	mov	eax, DWORD PTR NUM_CHIPS[rip]
	lea	edx, -1[rax]
	test	edx, edx
	jle	.L6
	mov	rax, QWORD PTR chip_data[rip]
	mov	esi, edx
	xor	ebp, ebp
	xor	ebx, ebx
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L3:
	add	ebx, 1
	add	rax, 32
	add	rbp, 32
	cmp	ebx, edx
	je	.L10
.L4:
	cmp	QWORD PTR [rax], r12
	jne	.L3
	mov	ecx, DWORD PTR 12[rax]
	xor	ecx, r13d
	test	DWORD PTR 8[rax], ecx
	jne	.L3
	mov	edx, DWORD PTR 28[rax]
	mov	edi, DWORD PTR TAG[rip]
	lea	rsi, .LC3[rip]
	xor	eax, eax
	call	ESP_LOGI@PLT
	mov	eax, DWORD PTR NUM_CHIPS[rip]
	mov	esi, ebx
	lea	edx, -1[rax]
	cmp	esi, edx
	jne	.L5
.L11:
	mov	edi, DWORD PTR TAG[rip]
	lea	rsi, .LC4[rip]
	xor	eax, eax
	call	ESP_LOGI@PLT
	jmp	.L5
	.p2align 4,,10
	.p2align 3
.L10:
	movsx	rbp, edx
	sal	rbp, 5
.L2:
	cmp	esi, edx
	je	.L11
.L5:
	add	rbp, QWORD PTR chip_data[rip]
	mov	edx, DWORD PTR 16[rbp]
	mov	esi, DWORD PTR 20[rbp]
	mov	edi, DWORD PTR 24[rbp]
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	jmp	enable_qio_mode@PLT
.L6:
	.cfi_restore_state
	xor	ebp, ebp
	xor	esi, esi
	jmp	.L2
	.cfi_endproc
.LFE0:
	.size	bootloader_enable_qio_mode, .-bootloader_enable_qio_mode
	.comm	g_rom_flashchip,4,4
	.comm	chip_data,8,8
	.comm	TAG,4,4
	.comm	NUM_CHIPS,4,4
	.comm	FLASH_WRAP_MODE_DISABLE,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_flash_qio_mode.c_bootloader_enable_qio_mode.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"Probing for QIO mode enable...\000"
	.align	2
.LC1:
	.ascii	"Raw SPI flash chip id 0x%x\000"
	.align	2
.LC2:
	.ascii	"Manufacturer ID 0x%02x chip ID 0x%04x\000"
	.align	2
.LC3:
	.ascii	"Enabling QIO for flash chip %s\000"
	.align	2
.LC4:
	.ascii	"Enabling default flash chip QIO\000"
	.text
	.align	2
	.global	bootloader_enable_qio_mode
	.syntax unified
	.arm
	.fpu softvfp
	.type	bootloader_enable_qio_mode, %function
bootloader_enable_qio_mode:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, lr}
	ldr	r8, .L12
	ldr	r4, .L12+4
	ldr	r1, .L12+8
	ldr	r0, [r8]
	bl	ESP_LOGD
	mov	r0, r4
	bl	esp_rom_spiflash_wait_idle
	ldr	r6, [r4]
	ldr	r1, .L12+12
	mov	r2, r6
	lsl	r7, r6, #16
	asr	r6, r6, #16
	ldr	r0, [r8]
	ldr	r9, .L12+16
	and	r6, r6, #255
	lsr	r7, r7, #16
	bl	ESP_LOGD
	mov	r3, r7
	mov	r2, r6
	ldr	r0, [r8]
	ldr	r1, .L12+20
	bl	ESP_LOGD
	ldr	r3, [r9]
	mov	r5, #0
	sub	r3, r3, #1
	cmp	r3, #0
	ble	.L6
	ldr	r10, .L12+24
	mov	ip, r3
	mov	r4, r5
	ldr	r1, [r10]
	b	.L4
.L3:
	add	r4, r4, #1
	cmp	r4, r3
	add	r1, r1, #28
	add	r5, r5, #28
	beq	.L10
.L4:
	ldr	r0, [r1]
	cmp	r0, r6
	bne	.L3
	ldmib	r1, {r0, r2}
	eor	r2, r2, r7
	tst	r2, r0
	bne	.L3
	ldr	r2, [r1, #24]
	ldr	r0, [r8]
	ldr	r1, .L12+28
	bl	ESP_LOGI
	mov	ip, r4
	ldr	r3, [r9]
	sub	r3, r3, #1
	cmp	ip, r3
	bne	.L5
.L11:
	ldr	r0, [r8]
	ldr	r1, .L12+32
	bl	ESP_LOGI
	b	.L5
.L10:
	rsb	r5, r3, r3, lsl #3
	lsl	r5, r5, #2
.L2:
	cmp	ip, r3
	beq	.L11
.L5:
	ldr	r3, [r10]
	add	r5, r3, r5
	ldr	r2, [r5, #12]
	ldr	r1, [r5, #16]
	ldr	r0, [r5, #20]
	pop	{r4, r5, r6, r7, r8, r9, r10, lr}
	b	enable_qio_mode
.L6:
	mov	ip, r5
	ldr	r10, .L12+24
	b	.L2
.L13:
	.align	2
.L12:
	.word	TAG
	.word	g_rom_flashchip
	.word	.LC0
	.word	.LC1
	.word	NUM_CHIPS
	.word	.LC2
	.word	chip_data
	.word	.LC3
	.word	.LC4
	.size	bootloader_enable_qio_mode, .-bootloader_enable_qio_mode
	.comm	g_rom_flashchip,4,4
	.comm	chip_data,4,4
	.comm	TAG,4,4
	.comm	NUM_CHIPS,4,4
	.comm	FLASH_WRAP_MODE_DISABLE,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
