	.file	"extr_cik.c_cik_program_aspm.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	cik_program_aspm, @function
cik_program_aspm:
.LFB0:
	.cfi_startproc
	endbr64
	push	r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	push	r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	push	r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	push	rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	push	rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	sub	rsp, 16
	.cfi_def_cfa_offset 64
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 8[rsp], rax
	xor	eax, eax
	cmp	QWORD PTR radeon_aspm[rip], 0
	je	.L1
	mov	eax, DWORD PTR [rdi]
	mov	rbp, rdi
	test	DWORD PTR RADEON_IS_IGP[rip], eax
	jne	.L1
	test	DWORD PTR RADEON_IS_PCIE[rip], eax
	je	.L1
	mov	edi, DWORD PTR PCIE_LC_N_FTS_CNTL[rip]
	call	RREG32_PCIE_PORT@PLT
	mov	esi, DWORD PTR LC_XMIT_N_FTS_MASK[rip]
	mov	edi, 36
	mov	r12d, eax
	not	esi
	mov	ebx, esi
	and	ebx, eax
	call	LC_XMIT_N_FTS@PLT
	or	eax, DWORD PTR LC_XMIT_N_FTS_OVERRIDE_EN[rip]
	mov	esi, eax
	or	esi, ebx
	cmp	r12d, esi
	jne	.L36
.L5:
	mov	edi, DWORD PTR PCIE_LC_CNTL3[rip]
	call	RREG32_PCIE_PORT@PLT
	mov	esi, DWORD PTR LC_GO_TO_RECOVERY[rip]
	or	esi, eax
	cmp	eax, esi
	jne	.L37
.L6:
	mov	edi, DWORD PTR PCIE_P_CNTL[rip]
	call	RREG32_PCIE_PORT@PLT
	mov	esi, DWORD PTR P_IGNORE_EDB_ERR[rip]
	or	esi, eax
	cmp	eax, esi
	jne	.L38
.L7:
	mov	edi, DWORD PTR PCIE_LC_CNTL[rip]
	call	RREG32_PCIE_PORT@PLT
	mov	esi, DWORD PTR LC_L0S_INACTIVITY_MASK[rip]
	or	esi, DWORD PTR LC_L1_INACTIVITY_MASK[rip]
	mov	edi, 7
	not	esi
	mov	r13d, DWORD PTR LC_PMI_TO_L1_DIS[rip]
	mov	r14d, eax
	and	esi, eax
	mov	r12d, esi
	call	LC_L0S_INACTIVITY@PLT
	mov	edi, 7
	mov	ebx, eax
	call	LC_L1_INACTIVITY@PLT
	or	ebx, eax
	mov	esi, ebx
	mov	ebx, DWORD PTR LC_PMI_TO_L1_DIS[rip]
	or	esi, r13d
	or	esi, r12d
	not	ebx
	and	esi, ebx
	cmp	r14d, esi
	jne	.L39
.L8:
	mov	edi, DWORD PTR PB0_PIF_PWRDOWN_0[rip]
	call	RREG32_PCIE_PORT@PLT
	mov	esi, DWORD PTR PLL_POWER_STATE_IN_OFF_0_MASK[rip]
	mov	edi, 7
	or	esi, DWORD PTR PLL_POWER_STATE_IN_TXS2_0_MASK[rip]
	not	esi
	mov	r13d, eax
	and	esi, eax
	mov	r12d, esi
	call	PLL_POWER_STATE_IN_OFF_0@PLT
	mov	edi, 7
	mov	ebx, eax
	call	PLL_POWER_STATE_IN_TXS2_0@PLT
	or	ebx, eax
	mov	esi, ebx
	or	esi, r12d
	cmp	r13d, esi
	jne	.L40
.L9:
	mov	edi, DWORD PTR PB0_PIF_PWRDOWN_1[rip]
	call	RREG32_PCIE_PORT@PLT
	mov	esi, DWORD PTR PLL_POWER_STATE_IN_OFF_1_MASK[rip]
	mov	edi, 7
	or	esi, DWORD PTR PLL_POWER_STATE_IN_TXS2_1_MASK[rip]
	not	esi
	mov	r13d, eax
	and	esi, eax
	mov	r12d, esi
	call	PLL_POWER_STATE_IN_OFF_1@PLT
	mov	edi, 7
	mov	ebx, eax
	call	PLL_POWER_STATE_IN_TXS2_1@PLT
	or	ebx, eax
	mov	esi, ebx
	or	esi, r12d
	cmp	r13d, esi
	jne	.L41
.L10:
	mov	edi, DWORD PTR PB1_PIF_PWRDOWN_0[rip]
	call	RREG32_PCIE_PORT@PLT
	mov	esi, DWORD PTR PLL_POWER_STATE_IN_OFF_0_MASK[rip]
	mov	edi, 7
	or	esi, DWORD PTR PLL_POWER_STATE_IN_TXS2_0_MASK[rip]
	not	esi
	mov	r13d, eax
	and	esi, eax
	mov	r12d, esi
	call	PLL_POWER_STATE_IN_OFF_0@PLT
	mov	edi, 7
	mov	ebx, eax
	call	PLL_POWER_STATE_IN_TXS2_0@PLT
	or	ebx, eax
	mov	esi, ebx
	or	esi, r12d
	cmp	r13d, esi
	jne	.L42
.L11:
	mov	edi, DWORD PTR PB1_PIF_PWRDOWN_1[rip]
	call	RREG32_PCIE_PORT@PLT
	mov	esi, DWORD PTR PLL_POWER_STATE_IN_OFF_1_MASK[rip]
	mov	edi, 7
	or	esi, DWORD PTR PLL_POWER_STATE_IN_TXS2_1_MASK[rip]
	not	esi
	mov	r13d, eax
	and	esi, eax
	mov	r12d, esi
	call	PLL_POWER_STATE_IN_OFF_1@PLT
	mov	edi, 7
	mov	ebx, eax
	call	PLL_POWER_STATE_IN_TXS2_1@PLT
	or	ebx, eax
	mov	esi, ebx
	or	esi, r12d
	cmp	r13d, esi
	jne	.L43
.L12:
	mov	edi, DWORD PTR PCIE_LC_LINK_WIDTH_CNTL[rip]
	call	RREG32_PCIE_PORT@PLT
	mov	esi, DWORD PTR LC_DYN_LANES_PWR_STATE_MASK[rip]
	mov	edi, 3
	mov	r12d, eax
	not	esi
	mov	ebx, esi
	and	ebx, eax
	call	LC_DYN_LANES_PWR_STATE@PLT
	or	ebx, eax
	mov	esi, ebx
	cmp	r12d, ebx
	jne	.L44
	mov	rax, QWORD PTR 8[rbp]
	mov	rdi, QWORD PTR [rax]
	call	pci_is_root_bus@PLT
	test	eax, eax
	je	.L45
.L15:
	mov	edi, DWORD PTR PCIE_CNTL2[rip]
	call	RREG32_PCIE_PORT@PLT
	mov	esi, DWORD PTR SLV_MEM_LS_EN[rip]
	or	esi, DWORD PTR MST_MEM_LS_EN[rip]
	or	esi, DWORD PTR REPLAY_MEM_LS_EN[rip]
	or	esi, eax
	cmp	eax, esi
	jne	.L46
.L23:
	mov	edi, DWORD PTR PCIE_LC_N_FTS_CNTL[rip]
	call	RREG32_PCIE_PORT@PLT
	mov	edx, DWORD PTR LC_N_FTS_MASK[rip]
	and	eax, edx
	cmp	edx, eax
	je	.L47
	.p2align 4,,10
	.p2align 3
.L1:
	mov	rax, QWORD PTR 8[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L48
	add	rsp, 16
	.cfi_remember_state
	.cfi_def_cfa_offset 48
	pop	rbx
	.cfi_def_cfa_offset 40
	pop	rbp
	.cfi_def_cfa_offset 32
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L46:
	.cfi_restore_state
	mov	edi, DWORD PTR PCIE_CNTL2[rip]
	call	WREG32_PCIE_PORT@PLT
	jmp	.L23
	.p2align 4,,10
	.p2align 3
.L44:
	mov	edi, DWORD PTR PCIE_LC_LINK_WIDTH_CNTL[rip]
	call	WREG32_PCIE_PORT@PLT
	mov	rax, QWORD PTR 8[rbp]
	mov	rdi, QWORD PTR [rax]
	call	pci_is_root_bus@PLT
	test	eax, eax
	jne	.L15
	jmp	.L45
	.p2align 4,,10
	.p2align 3
.L43:
	mov	edi, DWORD PTR PB1_PIF_PWRDOWN_1[rip]
	call	WREG32_PCIE_PORT@PLT
	jmp	.L12
	.p2align 4,,10
	.p2align 3
.L42:
	mov	edi, DWORD PTR PB1_PIF_PWRDOWN_0[rip]
	call	WREG32_PCIE_PORT@PLT
	jmp	.L11
	.p2align 4,,10
	.p2align 3
.L41:
	mov	edi, DWORD PTR PB0_PIF_PWRDOWN_1[rip]
	call	WREG32_PCIE_PORT@PLT
	jmp	.L10
	.p2align 4,,10
	.p2align 3
.L40:
	mov	edi, DWORD PTR PB0_PIF_PWRDOWN_0[rip]
	call	WREG32_PCIE_PORT@PLT
	jmp	.L9
	.p2align 4,,10
	.p2align 3
.L39:
	mov	edi, DWORD PTR PCIE_LC_CNTL[rip]
	call	WREG32_PCIE_PORT@PLT
	jmp	.L8
	.p2align 4,,10
	.p2align 3
.L38:
	mov	edi, DWORD PTR PCIE_P_CNTL[rip]
	call	WREG32_PCIE_PORT@PLT
	jmp	.L7
	.p2align 4,,10
	.p2align 3
.L37:
	mov	edi, DWORD PTR PCIE_LC_CNTL3[rip]
	call	WREG32_PCIE_PORT@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L36:
	mov	edi, DWORD PTR PCIE_LC_N_FTS_CNTL[rip]
	call	WREG32_PCIE_PORT@PLT
	jmp	.L5
	.p2align 4,,10
	.p2align 3
.L45:
	mov	rax, QWORD PTR 8[rbp]
	mov	esi, DWORD PTR PCI_EXP_LNKCAP[rip]
	lea	rdx, 4[rsp]
	mov	rax, QWORD PTR [rax]
	mov	rdi, QWORD PTR [rax]
	call	pcie_capability_read_dword@PLT
	mov	eax, DWORD PTR 4[rsp]
	test	DWORD PTR PCI_EXP_LNKCAP_CLKPM[rip], eax
	je	.L15
	mov	edi, DWORD PTR PCIE_LC_CNTL2[rip]
	call	RREG32_PCIE_PORT@PLT
	mov	esi, DWORD PTR LC_ALLOW_PDWN_IN_L1[rip]
	or	esi, DWORD PTR LC_ALLOW_PDWN_IN_L23[rip]
	or	esi, eax
	cmp	eax, esi
	je	.L17
	mov	edi, DWORD PTR PCIE_LC_CNTL2[rip]
	call	WREG32_PCIE_PORT@PLT
.L17:
	mov	edi, DWORD PTR THM_CLK_CNTL[rip]
	call	RREG32_SMC@PLT
	mov	esi, DWORD PTR CMON_CLK_SEL_MASK[rip]
	mov	edi, 1
	or	esi, DWORD PTR TMON_CLK_SEL_MASK[rip]
	not	esi
	mov	r12d, eax
	and	esi, eax
	mov	ebp, esi
	call	CMON_CLK_SEL@PLT
	mov	edi, 1
	mov	ebx, eax
	call	TMON_CLK_SEL@PLT
	or	ebx, eax
	mov	esi, ebx
	or	esi, ebp
	cmp	r12d, esi
	je	.L18
	mov	edi, DWORD PTR THM_CLK_CNTL[rip]
	call	WREG32_SMC@PLT
.L18:
	mov	edi, DWORD PTR MISC_CLK_CTRL[rip]
	call	RREG32_SMC@PLT
	mov	esi, DWORD PTR DEEP_SLEEP_CLK_SEL_MASK[rip]
	mov	edi, 1
	or	esi, DWORD PTR ZCLK_SEL_MASK[rip]
	not	esi
	mov	r12d, eax
	and	esi, eax
	mov	ebp, esi
	call	DEEP_SLEEP_CLK_SEL@PLT
	mov	edi, 1
	mov	ebx, eax
	call	ZCLK_SEL@PLT
	or	ebx, eax
	mov	esi, ebx
	or	esi, ebp
	cmp	r12d, esi
	je	.L19
	mov	edi, DWORD PTR MISC_CLK_CTRL[rip]
	call	WREG32_SMC@PLT
.L19:
	mov	edi, DWORD PTR CG_CLKPIN_CNTL[rip]
	call	RREG32_SMC@PLT
	mov	esi, DWORD PTR BCLK_AS_XCLK[rip]
	not	esi
	and	esi, eax
	cmp	eax, esi
	je	.L20
	mov	edi, DWORD PTR CG_CLKPIN_CNTL[rip]
	call	WREG32_SMC@PLT
.L20:
	mov	edi, DWORD PTR CG_CLKPIN_CNTL_2[rip]
	call	RREG32_SMC@PLT
	mov	esi, DWORD PTR FORCE_BIF_REFCLK_EN[rip]
	not	esi
	and	esi, eax
	cmp	eax, esi
	je	.L21
	mov	edi, DWORD PTR CG_CLKPIN_CNTL_2[rip]
	call	WREG32_SMC@PLT
.L21:
	mov	edi, DWORD PTR MPLL_BYPASSCLK_SEL[rip]
	call	RREG32_SMC@PLT
	mov	esi, DWORD PTR MPLL_CLKOUT_SEL_MASK[rip]
	mov	edi, 4
	mov	ebp, eax
	not	esi
	mov	ebx, esi
	and	ebx, eax
	call	MPLL_CLKOUT_SEL@PLT
	or	ebx, eax
	mov	esi, ebx
	cmp	ebp, ebx
	je	.L15
	mov	edi, DWORD PTR MPLL_BYPASSCLK_SEL[rip]
	call	WREG32_SMC@PLT
	jmp	.L15
	.p2align 4,,10
	.p2align 3
.L47:
	mov	edi, DWORD PTR PCIE_LC_STATUS1[rip]
	call	RREG32_PCIE_PORT@PLT
	test	DWORD PTR LC_REVERSE_XMIT[rip], eax
	je	.L1
	test	DWORD PTR LC_REVERSE_RCVR[rip], eax
	je	.L1
	mov	edi, DWORD PTR PCIE_LC_CNTL[rip]
	call	RREG32_PCIE_PORT@PLT
	mov	esi, DWORD PTR LC_L0S_INACTIVITY_MASK[rip]
	not	esi
	and	esi, eax
	cmp	eax, esi
	je	.L1
	mov	edi, DWORD PTR PCIE_LC_CNTL[rip]
	call	WREG32_PCIE_PORT@PLT
	jmp	.L1
.L48:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	cik_program_aspm, .-cik_program_aspm
	.comm	radeon_aspm,8,8
	.comm	ZCLK_SEL_MASK,4,4
	.comm	TMON_CLK_SEL_MASK,4,4
	.comm	THM_CLK_CNTL,4,4
	.comm	SLV_MEM_LS_EN,4,4
	.comm	REPLAY_MEM_LS_EN,4,4
	.comm	RADEON_IS_PCIE,4,4
	.comm	RADEON_IS_IGP,4,4
	.comm	P_IGNORE_EDB_ERR,4,4
	.comm	PLL_POWER_STATE_IN_TXS2_1_MASK,4,4
	.comm	PLL_POWER_STATE_IN_TXS2_0_MASK,4,4
	.comm	PLL_POWER_STATE_IN_OFF_1_MASK,4,4
	.comm	PLL_POWER_STATE_IN_OFF_0_MASK,4,4
	.comm	PCI_EXP_LNKCAP_CLKPM,4,4
	.comm	PCI_EXP_LNKCAP,4,4
	.comm	PCIE_P_CNTL,4,4
	.comm	PCIE_LC_STATUS1,4,4
	.comm	PCIE_LC_N_FTS_CNTL,4,4
	.comm	PCIE_LC_LINK_WIDTH_CNTL,4,4
	.comm	PCIE_LC_CNTL3,4,4
	.comm	PCIE_LC_CNTL2,4,4
	.comm	PCIE_LC_CNTL,4,4
	.comm	PCIE_CNTL2,4,4
	.comm	PB1_PIF_PWRDOWN_1,4,4
	.comm	PB1_PIF_PWRDOWN_0,4,4
	.comm	PB0_PIF_PWRDOWN_1,4,4
	.comm	PB0_PIF_PWRDOWN_0,4,4
	.comm	MST_MEM_LS_EN,4,4
	.comm	MPLL_CLKOUT_SEL_MASK,4,4
	.comm	MPLL_BYPASSCLK_SEL,4,4
	.comm	MISC_CLK_CTRL,4,4
	.comm	LC_XMIT_N_FTS_OVERRIDE_EN,4,4
	.comm	LC_XMIT_N_FTS_MASK,4,4
	.comm	LC_REVERSE_XMIT,4,4
	.comm	LC_REVERSE_RCVR,4,4
	.comm	LC_PMI_TO_L1_DIS,4,4
	.comm	LC_N_FTS_MASK,4,4
	.comm	LC_L1_INACTIVITY_MASK,4,4
	.comm	LC_L0S_INACTIVITY_MASK,4,4
	.comm	LC_GO_TO_RECOVERY,4,4
	.comm	LC_DYN_LANES_PWR_STATE_MASK,4,4
	.comm	LC_ALLOW_PDWN_IN_L23,4,4
	.comm	LC_ALLOW_PDWN_IN_L1,4,4
	.comm	FORCE_BIF_REFCLK_EN,4,4
	.comm	DEEP_SLEEP_CLK_SEL_MASK,4,4
	.comm	CMON_CLK_SEL_MASK,4,4
	.comm	CG_CLKPIN_CNTL_2,4,4
	.comm	CG_CLKPIN_CNTL,4,4
	.comm	BCLK_AS_XCLK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_cik.c_cik_program_aspm.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	cik_program_aspm, %function
cik_program_aspm:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r3, .L49
	ldr	r2, .L49+4
	ldr	r3, [r3]
	sub	sp, sp, #28
	cmp	r3, #0
	ldr	r2, [r2]
	str	r2, [sp, #20]
	mov	r2,#0
	beq	.L1
	ldr	r2, .L49+8
	ldr	r3, [r0]
	ldr	r2, [r2]
	mov	r4, r0
	tst	r3, r2
	bne	.L1
	ldr	r2, .L49+12
	ldr	r2, [r2]
	tst	r3, r2
	beq	.L1
	ldr	r5, .L49+16
	ldr	r0, [r5]
	bl	RREG32_PCIE_PORT
	mov	r6, r0
	ldr	r3, .L49+20
	mov	r0, #36
	ldr	r1, [r3]
	bic	r7, r6, r1
	bl	LC_XMIT_N_FTS
	ldr	r3, .L49+24
	ldr	r1, [r3]
	orr	r1, r0, r1
	orr	r1, r1, r7
	cmp	r6, r1
	bne	.L36
.L5:
	ldr	r6, .L49+28
	ldr	r0, [r6]
	bl	RREG32_PCIE_PORT
	ldr	r3, .L49+32
	ldr	r1, [r3]
	bics	r3, r1, r0
	orr	r1, r0, r1
	bne	.L37
.L6:
	ldr	r6, .L49+36
	ldr	r0, [r6]
	bl	RREG32_PCIE_PORT
	ldr	r3, .L49+40
	ldr	r1, [r3]
	bics	r3, r1, r0
	orr	r1, r0, r1
	bne	.L38
.L7:
	ldr	r10, .L49+44
	ldr	fp, .L49+48
	ldr	r0, [r10]
	bl	RREG32_PCIE_PORT
	mov	r7, r0
	ldr	r3, .L49+52
	ldr	r9, .L49+56
	ldr	r8, [r3]
	ldr	r1, [fp]
	ldr	r3, [r9]
	orr	r1, r1, r8
	mov	r0, #7
	bic	r8, r7, r1
	str	r3, [sp, #4]
	bl	LC_L0S_INACTIVITY
	mov	r6, r0
	mov	r0, #7
	bl	LC_L1_INACTIVITY
	ldr	r3, [sp, #4]
	orr	r1, r6, r0
	orr	r1, r1, r3
	ldr	r3, [r9]
	orr	r1, r1, r8
	bic	r1, r1, r3
	cmp	r7, r1
	bne	.L39
.L8:
	ldr	r7, .L49+60
	ldr	r9, .L49+64
	ldr	r0, [r7]
	bl	RREG32_PCIE_PORT
	mov	r3, r0
	ldr	r8, .L49+68
	ldr	r1, [r9]
	ldr	r2, [r8]
	mov	r0, #7
	orr	r1, r1, r2
	bic	r2, r3, r1
	stmib	sp, {r2, r3}
	bl	PLL_POWER_STATE_IN_OFF_0
	mov	r6, r0
	mov	r0, #7
	bl	PLL_POWER_STATE_IN_TXS2_0
	ldr	r2, [sp, #4]
	ldr	r3, [sp, #8]
	orr	r1, r6, r0
	orr	r1, r1, r2
	cmp	r3, r1
	bne	.L40
.L9:
	ldr	r3, .L49+72
	ldr	r7, .L49+76
	ldr	r0, [r3]
	bl	RREG32_PCIE_PORT
	mov	r2, r0
	ldr	r6, .L49+80
	ldr	r1, [r7]
	ldr	ip, [r6]
	mov	r0, #7
	orr	r1, r1, ip
	bic	r3, r2, r1
	str	r2, [sp, #12]
	str	r3, [sp, #4]
	bl	PLL_POWER_STATE_IN_OFF_1
	mov	r1, r0
	mov	r0, #7
	str	r1, [sp, #8]
	bl	PLL_POWER_STATE_IN_TXS2_1
	ldr	r1, [sp, #8]
	ldr	r3, [sp, #4]
	ldr	r2, [sp, #12]
	orr	r1, r1, r0
	orr	r1, r1, r3
	cmp	r2, r1
	bne	.L41
.L10:
	ldr	r3, .L49+84
	ldr	r0, [r3]
	bl	RREG32_PCIE_PORT
	mov	r2, r0
	ldr	r1, [r9]
	ldr	r9, [r8]
	mov	r0, #7
	orr	r1, r1, r9
	bic	r9, r2, r1
	str	r2, [sp, #4]
	bl	PLL_POWER_STATE_IN_OFF_0
	mov	r8, r0
	mov	r0, #7
	bl	PLL_POWER_STATE_IN_TXS2_0
	ldr	r2, [sp, #4]
	orr	r1, r8, r0
	orr	r1, r1, r9
	cmp	r2, r1
	bne	.L42
.L11:
	ldr	r8, .L49+88
	ldr	r0, [r8]
	bl	RREG32_PCIE_PORT
	mov	r9, r0
	ldr	r1, [r7]
	ldr	r7, [r6]
	mov	r0, #7
	orr	r1, r1, r7
	bic	r7, r9, r1
	bl	PLL_POWER_STATE_IN_OFF_1
	mov	r6, r0
	mov	r0, #7
	bl	PLL_POWER_STATE_IN_TXS2_1
	orr	r1, r6, r0
	orr	r1, r1, r7
	cmp	r9, r1
	bne	.L43
.L12:
	ldr	r8, .L49+92
	ldr	r0, [r8]
	bl	RREG32_PCIE_PORT
	mov	r7, r0
	ldr	r3, .L49+96
	mov	r0, #3
	ldr	r1, [r3]
	bic	r6, r7, r1
	bl	LC_DYN_LANES_PWR_STATE
	orr	r1, r6, r0
	cmp	r7, r1
	bne	.L44
.L13:
	ldr	r3, [r4, #4]
	ldr	r0, [r3]
	bl	pci_is_root_bus
	cmp	r0, #0
	beq	.L45
.L15:
	ldr	r4, .L49+100
	ldr	r0, [r4]
	bl	RREG32_PCIE_PORT
	ldr	r1, .L49+104
	ldr	r2, .L49+108
	ldr	r3, .L49+112
	ldr	r1, [r1]
	ldr	r2, [r2]
	ldr	r3, [r3]
	orr	r1, r1, r2
	orr	r1, r1, r3
	bics	r3, r1, r0
	orr	r1, r1, r0
	bne	.L46
.L23:
	ldr	r0, [r5]
	bl	RREG32_PCIE_PORT
	ldr	r3, .L49+116
	ldr	r3, [r3]
	bics	r3, r3, r0
	beq	.L47
.L1:
	ldr	r3, .L49+4
	ldr	r2, [r3]
	ldr	r3, [sp, #20]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L48
	add	sp, sp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L46:
	ldr	r0, [r4]
	bl	WREG32_PCIE_PORT
	b	.L23
.L44:
	ldr	r0, [r8]
	bl	WREG32_PCIE_PORT
	b	.L13
.L43:
	ldr	r0, [r8]
	bl	WREG32_PCIE_PORT
	b	.L12
.L42:
	ldr	r3, .L49+84
	ldr	r0, [r3]
	bl	WREG32_PCIE_PORT
	b	.L11
.L41:
	ldr	r3, .L49+72
	ldr	r0, [r3]
	bl	WREG32_PCIE_PORT
	b	.L10
.L40:
	ldr	r0, [r7]
	bl	WREG32_PCIE_PORT
	b	.L9
.L39:
	ldr	r0, [r10]
	bl	WREG32_PCIE_PORT
	b	.L8
.L38:
	ldr	r0, [r6]
	bl	WREG32_PCIE_PORT
	b	.L7
.L37:
	ldr	r0, [r6]
	bl	WREG32_PCIE_PORT
	b	.L6
.L36:
	ldr	r0, [r5]
	bl	WREG32_PCIE_PORT
	b	.L5
.L45:
	ldr	r3, [r4, #4]
	ldr	r2, .L49+120
	ldr	r3, [r3]
	ldr	r1, [r2]
	ldr	r0, [r3]
	add	r2, sp, #16
	bl	pcie_capability_read_dword
	ldr	r3, .L49+124
	ldr	r2, [sp, #16]
	ldr	r3, [r3]
	tst	r2, r3
	beq	.L15
	ldr	r4, .L49+128
	ldr	r0, [r4]
	bl	RREG32_PCIE_PORT
	ldr	r2, .L49+132
	ldr	r3, .L49+136
	ldr	r1, [r2]
	ldr	r3, [r3]
	orr	r1, r1, r3
	bics	r3, r1, r0
	orr	r1, r1, r0
	beq	.L17
	ldr	r0, [r4]
	bl	WREG32_PCIE_PORT
.L17:
	ldr	r7, .L49+140
	ldr	r0, [r7]
	bl	RREG32_SMC
	mov	r8, r0
	ldr	r2, .L49+144
	ldr	r3, .L49+148
	ldr	r1, [r2]
	ldr	r6, [r3]
	mov	r0, #1
	orr	r1, r1, r6
	bic	r6, r8, r1
	bl	CMON_CLK_SEL
	mov	r4, r0
	mov	r0, #1
	bl	TMON_CLK_SEL
	orr	r1, r4, r0
	orr	r1, r1, r6
	cmp	r8, r1
	beq	.L18
	ldr	r0, [r7]
	bl	WREG32_SMC
.L18:
	ldr	r7, .L49+152
	ldr	r0, [r7]
	bl	RREG32_SMC
	mov	r8, r0
	ldr	r2, .L49+156
	ldr	r3, .L49+160
	ldr	r1, [r2]
	ldr	r6, [r3]
	mov	r0, #1
	orr	r1, r1, r6
	bic	r6, r8, r1
	bl	DEEP_SLEEP_CLK_SEL
	mov	r4, r0
	mov	r0, #1
	bl	ZCLK_SEL
	orr	r1, r4, r0
	orr	r1, r1, r6
	cmp	r8, r1
	beq	.L19
	ldr	r0, [r7]
	bl	WREG32_SMC
.L19:
	ldr	r4, .L49+164
	ldr	r0, [r4]
	bl	RREG32_SMC
	ldr	r3, .L49+168
	ldr	r1, [r3]
	tst	r1, r0
	bic	r1, r0, r1
	beq	.L20
	ldr	r0, [r4]
	bl	WREG32_SMC
.L20:
	ldr	r4, .L49+172
	ldr	r0, [r4]
	bl	RREG32_SMC
	ldr	r3, .L49+176
	ldr	r1, [r3]
	tst	r1, r0
	bic	r1, r0, r1
	beq	.L21
	ldr	r0, [r4]
	bl	WREG32_SMC
.L21:
	ldr	r7, .L49+180
	ldr	r0, [r7]
	bl	RREG32_SMC
	mov	r6, r0
	ldr	r3, .L49+184
	mov	r0, #4
	ldr	r1, [r3]
	bic	r4, r6, r1
	bl	MPLL_CLKOUT_SEL
	orr	r1, r4, r0
	cmp	r6, r1
	beq	.L15
	ldr	r0, [r7]
	bl	WREG32_SMC
	b	.L15
.L47:
	ldr	r3, .L49+188
	ldr	r0, [r3]
	bl	RREG32_PCIE_PORT
	ldr	r3, .L49+192
	ldr	r3, [r3]
	tst	r0, r3
	beq	.L1
	ldr	r3, .L49+196
	ldr	r3, [r3]
	tst	r0, r3
	beq	.L1
	ldr	r0, [r10]
	bl	RREG32_PCIE_PORT
	ldr	r1, [fp]
	tst	r1, r0
	bic	r1, r0, r1
	beq	.L1
	ldr	r0, [r10]
	bl	WREG32_PCIE_PORT
	b	.L1
.L48:
	bl	__stack_chk_fail
.L50:
	.align	2
.L49:
	.word	radeon_aspm
	.word	.LC0
	.word	RADEON_IS_IGP
	.word	RADEON_IS_PCIE
	.word	PCIE_LC_N_FTS_CNTL
	.word	LC_XMIT_N_FTS_MASK
	.word	LC_XMIT_N_FTS_OVERRIDE_EN
	.word	PCIE_LC_CNTL3
	.word	LC_GO_TO_RECOVERY
	.word	PCIE_P_CNTL
	.word	P_IGNORE_EDB_ERR
	.word	PCIE_LC_CNTL
	.word	LC_L0S_INACTIVITY_MASK
	.word	LC_L1_INACTIVITY_MASK
	.word	LC_PMI_TO_L1_DIS
	.word	PB0_PIF_PWRDOWN_0
	.word	PLL_POWER_STATE_IN_OFF_0_MASK
	.word	PLL_POWER_STATE_IN_TXS2_0_MASK
	.word	PB0_PIF_PWRDOWN_1
	.word	PLL_POWER_STATE_IN_OFF_1_MASK
	.word	PLL_POWER_STATE_IN_TXS2_1_MASK
	.word	PB1_PIF_PWRDOWN_0
	.word	PB1_PIF_PWRDOWN_1
	.word	PCIE_LC_LINK_WIDTH_CNTL
	.word	LC_DYN_LANES_PWR_STATE_MASK
	.word	PCIE_CNTL2
	.word	SLV_MEM_LS_EN
	.word	MST_MEM_LS_EN
	.word	REPLAY_MEM_LS_EN
	.word	LC_N_FTS_MASK
	.word	PCI_EXP_LNKCAP
	.word	PCI_EXP_LNKCAP_CLKPM
	.word	PCIE_LC_CNTL2
	.word	LC_ALLOW_PDWN_IN_L1
	.word	LC_ALLOW_PDWN_IN_L23
	.word	THM_CLK_CNTL
	.word	CMON_CLK_SEL_MASK
	.word	TMON_CLK_SEL_MASK
	.word	MISC_CLK_CTRL
	.word	DEEP_SLEEP_CLK_SEL_MASK
	.word	ZCLK_SEL_MASK
	.word	CG_CLKPIN_CNTL
	.word	BCLK_AS_XCLK
	.word	CG_CLKPIN_CNTL_2
	.word	FORCE_BIF_REFCLK_EN
	.word	MPLL_BYPASSCLK_SEL
	.word	MPLL_CLKOUT_SEL_MASK
	.word	PCIE_LC_STATUS1
	.word	LC_REVERSE_XMIT
	.word	LC_REVERSE_RCVR
	.size	cik_program_aspm, .-cik_program_aspm
	.comm	radeon_aspm,4,4
	.comm	ZCLK_SEL_MASK,4,4
	.comm	TMON_CLK_SEL_MASK,4,4
	.comm	THM_CLK_CNTL,4,4
	.comm	SLV_MEM_LS_EN,4,4
	.comm	REPLAY_MEM_LS_EN,4,4
	.comm	RADEON_IS_PCIE,4,4
	.comm	RADEON_IS_IGP,4,4
	.comm	P_IGNORE_EDB_ERR,4,4
	.comm	PLL_POWER_STATE_IN_TXS2_1_MASK,4,4
	.comm	PLL_POWER_STATE_IN_TXS2_0_MASK,4,4
	.comm	PLL_POWER_STATE_IN_OFF_1_MASK,4,4
	.comm	PLL_POWER_STATE_IN_OFF_0_MASK,4,4
	.comm	PCI_EXP_LNKCAP_CLKPM,4,4
	.comm	PCI_EXP_LNKCAP,4,4
	.comm	PCIE_P_CNTL,4,4
	.comm	PCIE_LC_STATUS1,4,4
	.comm	PCIE_LC_N_FTS_CNTL,4,4
	.comm	PCIE_LC_LINK_WIDTH_CNTL,4,4
	.comm	PCIE_LC_CNTL3,4,4
	.comm	PCIE_LC_CNTL2,4,4
	.comm	PCIE_LC_CNTL,4,4
	.comm	PCIE_CNTL2,4,4
	.comm	PB1_PIF_PWRDOWN_1,4,4
	.comm	PB1_PIF_PWRDOWN_0,4,4
	.comm	PB0_PIF_PWRDOWN_1,4,4
	.comm	PB0_PIF_PWRDOWN_0,4,4
	.comm	MST_MEM_LS_EN,4,4
	.comm	MPLL_CLKOUT_SEL_MASK,4,4
	.comm	MPLL_BYPASSCLK_SEL,4,4
	.comm	MISC_CLK_CTRL,4,4
	.comm	LC_XMIT_N_FTS_OVERRIDE_EN,4,4
	.comm	LC_XMIT_N_FTS_MASK,4,4
	.comm	LC_REVERSE_XMIT,4,4
	.comm	LC_REVERSE_RCVR,4,4
	.comm	LC_PMI_TO_L1_DIS,4,4
	.comm	LC_N_FTS_MASK,4,4
	.comm	LC_L1_INACTIVITY_MASK,4,4
	.comm	LC_L0S_INACTIVITY_MASK,4,4
	.comm	LC_GO_TO_RECOVERY,4,4
	.comm	LC_DYN_LANES_PWR_STATE_MASK,4,4
	.comm	LC_ALLOW_PDWN_IN_L23,4,4
	.comm	LC_ALLOW_PDWN_IN_L1,4,4
	.comm	FORCE_BIF_REFCLK_EN,4,4
	.comm	DEEP_SLEEP_CLK_SEL_MASK,4,4
	.comm	CMON_CLK_SEL_MASK,4,4
	.comm	CG_CLKPIN_CNTL_2,4,4
	.comm	CG_CLKPIN_CNTL,4,4
	.comm	BCLK_AS_XCLK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
