	.file	"extr_trigger.c_ExecIRUpdateTriggers.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	ExecIRUpdateTriggers
	.type	ExecIRUpdateTriggers, @function
ExecIRUpdateTriggers:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	mov	r15, rdi
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	mov	r14, rdx
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rsi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 152
	.cfi_def_cfa_offset 208
	mov	rbx, QWORD PTR 16[rsi]
	mov	QWORD PTR 32[rsp], rdx
	mov	QWORD PTR 16[rsp], rcx
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 136[rsp], rax
	xor	eax, eax
	call	ExecGetTriggerOldSlot@PLT
	xor	edx, edx
	mov	rdi, r14
	mov	QWORD PTR 120[rsp], 0
	mov	rsi, rax
	mov	QWORD PTR 24[rsp], rax
	mov	eax, DWORD PTR T_TriggerData[rip]
	mov	QWORD PTR 112[rsp], 0
	mov	DWORD PTR 132[rsp], eax
	mov	eax, DWORD PTR TRIGGER_EVENT_UPDATE[rip]
	or	eax, DWORD PTR TRIGGER_EVENT_ROW[rip]
	or	eax, DWORD PTR TRIGGER_EVENT_INSTEAD[rip]
	mov	DWORD PTR 64[rsp], eax
	mov	eax, DWORD PTR 8[rbp]
	mov	DWORD PTR 128[rsp], eax
	call	ExecForceStoreHeapTuple@PLT
	mov	esi, DWORD PTR [rbx]
	test	esi, esi
	jle	.L2
	lea	rax, 64[rsp]
	xor	r12d, r12d
	mov	QWORD PTR 8[rsp], 0
	mov	QWORD PTR 40[rsp], rax
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L4:
	mov	rax, QWORD PTR 24[rsp]
	mov	rdi, r15
	mov	QWORD PTR 72[rsp], r13
	mov	QWORD PTR 104[rsp], rax
	mov	rax, QWORD PTR 32[rsp]
	mov	QWORD PTR 96[rsp], rax
	mov	rax, QWORD PTR 16[rsp]
	mov	QWORD PTR 88[rsp], rax
	mov	rax, QWORD PTR 8[rsp]
	mov	QWORD PTR 80[rsp], rax
	call	GetPerTupleMemoryContext@PLT
	mov	rdi, QWORD PTR 40[rsp]
	mov	edx, DWORD PTR 4[rbp]
	mov	esi, r14d
	mov	ecx, DWORD PTR 0[rbp]
	mov	r8d, eax
	call	ExecCallTriggerFunc@PLT
	mov	rdi, rax
	test	rax, rax
	je	.L8
	cmp	QWORD PTR 8[rsp], rax
	je	.L3
	mov	rsi, QWORD PTR 16[rsp]
	xor	edx, edx
	call	ExecForceStoreHeapTuple@PLT
	mov	eax, DWORD PTR 60[rsp]
	test	eax, eax
	jne	.L20
	mov	QWORD PTR 8[rsp], 0
	.p2align 4,,10
	.p2align 3
.L3:
	add	r12, 1
	cmp	DWORD PTR [rbx], r12d
	jle	.L2
.L6:
	mov	rax, QWORD PTR 8[rbx]
	mov	ecx, DWORD PTR TRIGGER_TYPE_UPDATE[rip]
	mov	r14d, r12d
	mov	edx, DWORD PTR TRIGGER_TYPE_INSTEAD[rip]
	mov	esi, DWORD PTR TRIGGER_TYPE_ROW[rip]
	lea	r13, [rax+r12*4]
	mov	edi, DWORD PTR 0[r13]
	call	TRIGGER_TYPE_MATCHES@PLT
	test	eax, eax
	je	.L3
	sub	rsp, 8
	.cfi_def_cfa_offset 216
	mov	rdx, r13
	xor	r8d, r8d
	mov	rsi, rbp
	push	QWORD PTR 24[rsp]
	.cfi_def_cfa_offset 224
	mov	r9, QWORD PTR 40[rsp]
	mov	rdi, r15
	mov	ecx, DWORD PTR 80[rsp]
	call	TriggerEnabled@PLT
	pop	rdx
	.cfi_def_cfa_offset 216
	pop	rcx
	.cfi_def_cfa_offset 208
	test	eax, eax
	je	.L3
	cmp	QWORD PTR 8[rsp], 0
	jne	.L4
	mov	rdi, QWORD PTR 16[rsp]
	lea	rdx, 60[rsp]
	mov	esi, 1
	call	ExecFetchSlotHeapTuple@PLT
	mov	QWORD PTR 8[rsp], rax
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L2:
	mov	eax, 1
.L1:
	mov	rcx, QWORD PTR 136[rsp]
	xor	rcx, QWORD PTR fs:40
	jne	.L21
	add	rsp, 152
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L20:
	.cfi_restore_state
	mov	rdi, QWORD PTR 8[rsp]
	call	heap_freetuple@PLT
	mov	QWORD PTR 8[rsp], 0
	jmp	.L3
	.p2align 4,,10
	.p2align 3
.L8:
	xor	eax, eax
	jmp	.L1
.L21:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	ExecIRUpdateTriggers, .-ExecIRUpdateTriggers
	.comm	T_TriggerData,4,4
	.comm	TRIGGER_TYPE_UPDATE,4,4
	.comm	TRIGGER_TYPE_ROW,4,4
	.comm	TRIGGER_TYPE_INSTEAD,4,4
	.comm	TRIGGER_EVENT_UPDATE,4,4
	.comm	TRIGGER_EVENT_ROW,4,4
	.comm	TRIGGER_EVENT_INSTEAD,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_trigger.c_ExecIRUpdateTriggers.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	ExecIRUpdateTriggers
	.syntax unified
	.arm
	.fpu softvfp
	.type	ExecIRUpdateTriggers, %function
ExecIRUpdateTriggers:
	@ args = 0, pretend = 0, frame = 64
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	mov	r9, r3
	sub	sp, sp, #84
	ldr	r3, .L22
	str	r2, [sp, #28]
	mov	r7, r1
	mov	r5, r2
	ldr	r6, [r1, #12]
	ldr	r3, [r3]
	str	r3, [sp, #76]
	mov	r3,#0
	mov	fp, r0
	bl	ExecGetTriggerOldSlot
	mov	r4, #0
	mov	lr, r0
	ldr	r2, .L22+4
	ldr	r3, .L22+8
	str	r0, [sp, #20]
	ldr	r1, .L22+12
	ldr	r0, [r2]
	ldr	r2, .L22+16
	ldr	r3, [r3]
	ldr	r1, [r1]
	ldr	ip, [r2]
	ldr	r2, [r7, #8]
	orr	r3, r3, r0
	orr	r3, r3, r1
	str	r2, [sp, #68]
	mov	r1, lr
	mov	r0, r5
	mov	r2, r4
	str	r3, [sp, #36]
	str	ip, [sp, #72]
	str	r4, [sp, #64]
	str	r4, [sp, #60]
	bl	ExecForceStoreHeapTuple
	ldr	r3, [r6]
	cmp	r3, r4
	ble	.L2
	mov	r8, r4
	ldr	r10, .L22+20
	b	.L6
.L4:
	ldr	r3, [sp, #20]
	mov	r0, fp
	str	r3, [sp, #56]
	ldr	r3, [sp, #28]
	str	r5, [sp, #40]
	str	r3, [sp, #52]
	str	r9, [sp, #48]
	ldm	r7, {r3, r5}
	str	r8, [sp, #44]
	str	r3, [sp, #24]
	bl	GetPerTupleMemoryContext
	ldr	r3, [sp, #24]
	str	r0, [sp]
	mov	r2, r5
	mov	r1, r4
	add	r0, sp, #36
	bl	ExecCallTriggerFunc
	subs	r3, r0, #0
	beq	.L8
	cmp	r8, r3
	beq	.L3
	mov	r2, #0
	mov	r1, r9
	bl	ExecForceStoreHeapTuple
	ldr	r3, [sp, #32]
	cmp	r3, #0
	moveq	r8, r3
	bne	.L20
.L3:
	ldr	r3, [r6]
	add	r4, r4, #1
	cmp	r3, r4
	ble	.L2
.L6:
	ldr	r5, [r6, #4]
	ldr	r2, .L22+24
	ldr	r1, .L22+28
	ldr	r0, [r5, r4, lsl #2]
	ldr	r3, [r10]
	ldr	r2, [r2]
	ldr	r1, [r1]
	bl	TRIGGER_TYPE_MATCHES
	cmp	r0, #0
	add	r5, r5, r4, lsl #2
	beq	.L3
	ldr	r3, [sp, #20]
	mov	r2, r5
	str	r3, [sp, #4]
	mov	r3, #0
	mov	r1, r7
	str	r3, [sp]
	mov	r0, fp
	ldr	r3, [sp, #36]
	str	r9, [sp, #8]
	bl	TriggerEnabled
	cmp	r0, #0
	beq	.L3
	cmp	r8, #0
	bne	.L4
	mov	r1, #1
	mov	r0, r9
	add	r2, sp, #32
	bl	ExecFetchSlotHeapTuple
	mov	r8, r0
	b	.L4
.L2:
	mov	r0, #1
.L1:
	ldr	r3, .L22
	ldr	r2, [r3]
	ldr	r3, [sp, #76]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L21
	add	sp, sp, #84
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L20:
	mov	r0, r8
	bl	heap_freetuple
	mov	r8, #0
	b	.L3
.L8:
	mov	r0, r3
	b	.L1
.L21:
	bl	__stack_chk_fail
.L23:
	.align	2
.L22:
	.word	.LC0
	.word	TRIGGER_EVENT_ROW
	.word	TRIGGER_EVENT_UPDATE
	.word	TRIGGER_EVENT_INSTEAD
	.word	T_TriggerData
	.word	TRIGGER_TYPE_UPDATE
	.word	TRIGGER_TYPE_INSTEAD
	.word	TRIGGER_TYPE_ROW
	.size	ExecIRUpdateTriggers, .-ExecIRUpdateTriggers
	.comm	T_TriggerData,4,4
	.comm	TRIGGER_TYPE_UPDATE,4,4
	.comm	TRIGGER_TYPE_ROW,4,4
	.comm	TRIGGER_TYPE_INSTEAD,4,4
	.comm	TRIGGER_EVENT_UPDATE,4,4
	.comm	TRIGGER_EVENT_ROW,4,4
	.comm	TRIGGER_EVENT_INSTEAD,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
