	.file	"extr_ci_dpm.c_ci_setup_default_pcie_tables.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	ci_setup_default_pcie_tables, @function
ci_setup_default_pcie_tables:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	call	ci_get_pi@PLT
	cmp	QWORD PTR 48[rax], 0
	mov	rbx, rax
	je	.L10
	cmp	QWORD PTR 40[rax], 0
	je	.L11
.L5:
	mov	edx, DWORD PTR SMU7_MAX_LEVELS_LINK[rip]
	mov	rsi, rbx
	mov	rdi, rbp
	call	ci_reset_single_dpm_table@PLT
	mov	rax, QWORD PTR CHIP_BONAIRE[rip]
	cmp	QWORD PTR 0[rbp], rax
	je	.L12
	mov	ecx, DWORD PTR 24[rbx]
	mov	edx, DWORD PTR 32[rbx]
	xor	esi, esi
	mov	rdi, rbx
	call	ci_setup_pcie_table_entry@PLT
.L7:
	mov	ecx, DWORD PTR 8[rbx]
	mov	edx, DWORD PTR 16[rbx]
	mov	esi, 1
	mov	rdi, rbx
	call	ci_setup_pcie_table_entry@PLT
	mov	ecx, DWORD PTR 20[rbx]
	mov	edx, DWORD PTR 32[rbx]
	mov	esi, 2
	mov	rdi, rbx
	call	ci_setup_pcie_table_entry@PLT
	mov	ecx, DWORD PTR 4[rbx]
	mov	edx, DWORD PTR 16[rbx]
	mov	esi, 3
	mov	rdi, rbx
	call	ci_setup_pcie_table_entry@PLT
	mov	ecx, DWORD PTR 20[rbx]
	mov	edx, DWORD PTR 28[rbx]
	mov	esi, 4
	mov	rdi, rbx
	call	ci_setup_pcie_table_entry@PLT
	mov	ecx, DWORD PTR 4[rbx]
	mov	edx, DWORD PTR 12[rbx]
	mov	esi, 5
	mov	rdi, rbx
	call	ci_setup_pcie_table_entry@PLT
	mov	DWORD PTR [rbx], 6
	xor	eax, eax
.L1:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L11:
	.cfi_restore_state
	mov	rax, QWORD PTR 12[rax]
	mov	QWORD PTR 28[rbx], rax
	mov	rax, QWORD PTR 4[rbx]
	mov	QWORD PTR 20[rbx], rax
	jmp	.L5
	.p2align 4,,10
	.p2align 3
.L10:
	mov	eax, DWORD PTR EINVAL[rip]
	neg	eax
	cmp	QWORD PTR 40[rbx], 0
	je	.L1
	mov	rax, QWORD PTR 28[rbx]
	mov	QWORD PTR 12[rbx], rax
	mov	rax, QWORD PTR 20[rbx]
	mov	QWORD PTR 4[rbx], rax
	jmp	.L5
	.p2align 4,,10
	.p2align 3
.L12:
	mov	ecx, DWORD PTR 20[rbx]
	mov	edx, DWORD PTR 32[rbx]
	xor	esi, esi
	mov	rdi, rbx
	call	ci_setup_pcie_table_entry@PLT
	jmp	.L7
	.cfi_endproc
.LFE0:
	.size	ci_setup_default_pcie_tables, .-ci_setup_default_pcie_tables
	.comm	SMU7_MAX_LEVELS_LINK,4,4
	.comm	EINVAL,4,4
	.comm	CHIP_BONAIRE,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_ci_dpm.c_ci_setup_default_pcie_tables.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	ci_setup_default_pcie_tables, %function
ci_setup_default_pcie_tables:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, lr}
	mov	r5, r0
	bl	ci_get_pi
	ldr	r3, [r0, #40]
	mov	r4, r0
	cmp	r3, #0
	ldr	r3, [r0, #36]
	beq	.L10
	cmp	r3, #0
	bne	.L5
	ldr	r1, [r0, #16]
	ldr	r0, [r0, #12]
	add	r2, r4, #28
	add	r3, r4, #20
	stm	r2, {r0, r1}
	ldmib	r4, {r0, r1}
	stm	r3, {r0, r1}
.L5:
	ldr	r3, .L12
	mov	r1, r4
	ldr	r2, [r3]
	mov	r0, r5
	bl	ci_reset_single_dpm_table
	ldr	r3, .L12+4
	ldr	r2, [r5]
	ldr	r3, [r3]
	mov	r1, #0
	cmp	r2, r3
	ldreq	r3, [r4, #20]
	ldrne	r3, [r4, #24]
	ldr	r2, [r4, #32]
	mov	r0, r4
	bl	ci_setup_pcie_table_entry
	ldr	r3, [r4, #8]
	ldr	r2, [r4, #16]
	mov	r1, #1
	mov	r0, r4
	bl	ci_setup_pcie_table_entry
	ldr	r3, [r4, #20]
	ldr	r2, [r4, #32]
	mov	r1, #2
	mov	r0, r4
	bl	ci_setup_pcie_table_entry
	ldr	r3, [r4, #4]
	ldr	r2, [r4, #16]
	mov	r1, #3
	mov	r0, r4
	bl	ci_setup_pcie_table_entry
	ldr	r3, [r4, #20]
	ldr	r2, [r4, #28]
	mov	r1, #4
	mov	r0, r4
	bl	ci_setup_pcie_table_entry
	ldr	r3, [r4, #4]
	mov	r1, #5
	mov	r0, r4
	ldr	r2, [r4, #12]
	bl	ci_setup_pcie_table_entry
	mov	r3, #6
	mov	r0, #0
	str	r3, [r4]
	pop	{r4, r5, r6, pc}
.L10:
	cmp	r3, #0
	beq	.L11
	ldr	r1, [r0, #32]
	ldr	r0, [r0, #28]
	add	r3, r4, #12
	stm	r3, {r0, r1}
	ldr	r1, [r4, #24]
	ldr	r0, [r4, #20]
	stmib	r4, {r0, r1}
	b	.L5
.L11:
	ldr	r3, .L12+8
	ldr	r0, [r3]
	rsb	r0, r0, #0
	pop	{r4, r5, r6, pc}
.L13:
	.align	2
.L12:
	.word	SMU7_MAX_LEVELS_LINK
	.word	CHIP_BONAIRE
	.word	EINVAL
	.size	ci_setup_default_pcie_tables, .-ci_setup_default_pcie_tables
	.comm	SMU7_MAX_LEVELS_LINK,4,4
	.comm	EINVAL,4,4
	.comm	CHIP_BONAIRE,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
