	.file	"extr_display_gx1.c_gx1_set_mode.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	gx1_set_mode, @function
gx1_set_mode:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 40
	.cfi_def_cfa_offset 96
	mov	rbx, QWORD PTR 40[rdi]
	mov	rdi, QWORD PTR DC_UNLOCK[rip]
	add	rdi, QWORD PTR [rbx]
	call	readl@PLT
	mov	edi, DWORD PTR DC_UNLOCK_CODE[rip]
	mov	rsi, QWORD PTR DC_UNLOCK[rip]
	add	rsi, QWORD PTR [rbx]
	call	writel@PLT
	mov	rdi, QWORD PTR DC_GENERAL_CFG[rip]
	add	rdi, QWORD PTR [rbx]
	call	readl@PLT
	mov	rdi, QWORD PTR DC_TIMING_CFG[rip]
	add	rdi, QWORD PTR [rbx]
	mov	r13d, eax
	call	readl@PLT
	mov	edi, DWORD PTR DC_TCFG_BLKE[rip]
	or	edi, DWORD PTR DC_TCFG_TGEN[rip]
	not	edi
	mov	rsi, QWORD PTR DC_TIMING_CFG[rip]
	add	rsi, QWORD PTR [rbx]
	and	edi, eax
	call	writel@PLT
	mov	edi, 100
	call	udelay@PLT
	mov	r12d, DWORD PTR DC_GCFG_DFLE[rip]
	or	r12d, DWORD PTR DC_GCFG_CMPE[rip]
	or	r12d, DWORD PTR DC_GCFG_DECE[rip]
	mov	rsi, QWORD PTR DC_GENERAL_CFG[rip]
	not	r12d
	add	rsi, QWORD PTR [rbx]
	and	r12d, r13d
	mov	edi, r12d
	call	writel@PLT
	mov	edi, DWORD PTR DC_GCFG_DCLK_MASK[rip]
	mov	rsi, QWORD PTR DC_GENERAL_CFG[rip]
	add	rsi, QWORD PTR [rbx]
	not	edi
	and	r12d, edi
	mov	edi, r12d
	call	writel@PLT
	mov	rax, QWORD PTR 8[rbx]
	mov	rdi, rbp
	call	[QWORD PTR 8[rax]]
	mov	r13d, DWORD PTR DC_GCFG_DCLK_DIV_1[rip]
	mov	edi, r12d
	mov	rsi, QWORD PTR DC_GENERAL_CFG[rip]
	add	rsi, QWORD PTR [rbx]
	or	edi, r13d
	call	writel@PLT
	mov	edi, 1000
	call	udelay@PLT
	mov	ecx, DWORD PTR DC_GCFG_DFHPEL_POS[rip]
	mov	eax, 5
	mov	r12d, DWORD PTR DC_GCFG_DFLE[rip]
	or	r13d, DWORD PTR DC_GCFG_VRDY[rip]
	mov	rsi, QWORD PTR DC_FB_ST_OFFSET[rip]
	or	r12d, r13d
	mov	r13d, 6
	sal	r13d, cl
	mov	ecx, DWORD PTR DC_GCFG_DFHPSL_POS[rip]
	or	r12d, r13d
	sal	eax, cl
	or	r12d, eax
	add	rsi, QWORD PTR [rbx]
	xor	edi, edi
	call	writel@PLT
	mov	edi, DWORD PTR 36[rbp]
	mov	rsi, QWORD PTR DC_LINE_DELTA[rip]
	add	rsi, QWORD PTR [rbx]
	sar	edi, 2
	call	writel@PLT
	mov	edi, DWORD PTR 0[rbp]
	mov	eax, DWORD PTR 4[rbp]
	mov	rsi, QWORD PTR DC_BUF_SIZE[rip]
	add	rsi, QWORD PTR [rbx]
	imul	eax, edi
	test	eax, eax
	lea	edi, 7[rax]
	cmovns	edi, eax
	sar	edi, 6
	add	edi, 2
	call	writel@PLT
	mov	r9d, DWORD PTR DC_OCFG_PCKE[rip]
	or	r9d, DWORD PTR DC_OCFG_PDEL[rip]
	or	r9d, DWORD PTR DC_OCFG_PDEH[rip]
	cmp	DWORD PTR 4[rbp], 8
	jne	.L2
	or	r9d, DWORD PTR DC_OCFG_8BPP[rip]
.L2:
	mov	eax, DWORD PTR 0[rbp]
	mov	r14d, DWORD PTR 8[rbp]
	mov	DWORD PTR 28[rsp], r9d
	mov	edx, DWORD PTR 12[rbp]
	mov	ecx, DWORD PTR 20[rbp]
	add	r14d, eax
	mov	r13d, DWORD PTR 28[rbp]
	sub	eax, 1
	mov	r8d, DWORD PTR DC_TCFG_FPPE[rip]
	add	edx, r14d
	mov	DWORD PTR 20[rsp], ecx
	mov	r15d, ecx
	mov	ecx, DWORD PTR 32[rbp]
	mov	edi, edx
	add	edi, DWORD PTR 16[rbp]
	add	r15d, DWORD PTR 24[rbp]
	mov	DWORD PTR 16[rsp], edx
	sub	edi, 1
	add	r13d, r15d
	or	r8d, DWORD PTR DC_TCFG_HSYE[rip]
	mov	rsi, QWORD PTR DC_H_TIMING_1[rip]
	sal	edi, 16
	add	ecx, r13d
	add	rsi, QWORD PTR [rbx]
	or	r8d, DWORD PTR DC_TCFG_VSYE[rip]
	or	edi, eax
	or	r8d, DWORD PTR DC_TCFG_BLKE[rip]
	or	r8d, DWORD PTR DC_TCFG_TGEN[rip]
	mov	DWORD PTR 8[rsp], ecx
	mov	DWORD PTR 24[rsp], r8d
	mov	DWORD PTR 12[rsp], edi
	call	writel@PLT
	mov	edi, DWORD PTR 12[rsp]
	mov	rsi, QWORD PTR DC_H_TIMING_2[rip]
	add	rsi, QWORD PTR [rbx]
	call	writel@PLT
	mov	edx, DWORD PTR 16[rsp]
	lea	r10d, -1[r14]
	mov	rsi, QWORD PTR DC_H_TIMING_3[rip]
	add	rsi, QWORD PTR [rbx]
	lea	edi, -1[rdx]
	sal	edi, 16
	or	edi, r10d
	mov	DWORD PTR 12[rsp], edi
	call	writel@PLT
	mov	edi, DWORD PTR 12[rsp]
	mov	rsi, QWORD PTR DC_FP_H_TIMING[rip]
	add	rsi, QWORD PTR [rbx]
	call	writel@PLT
	mov	ecx, DWORD PTR 8[rsp]
	mov	rsi, QWORD PTR DC_V_TIMING_1[rip]
	add	rsi, QWORD PTR [rbx]
	lea	r14d, -1[rcx]
	mov	ecx, DWORD PTR 20[rsp]
	sal	r14d, 16
	lea	edi, -1[rcx]
	or	r14d, edi
	mov	edi, r14d
	call	writel@PLT
	mov	edi, r14d
	mov	rsi, QWORD PTR DC_V_TIMING_2[rip]
	add	rsi, QWORD PTR [rbx]
	call	writel@PLT
	lea	edi, -1[r13]
	lea	eax, -1[r15]
	mov	rsi, QWORD PTR DC_V_TIMING_3[rip]
	sal	edi, 16
	add	rsi, QWORD PTR [rbx]
	or	edi, eax
	sub	r15d, 2
	call	writel@PLT
	lea	edi, -2[r13]
	mov	rsi, QWORD PTR DC_FP_V_TIMING[rip]
	add	rsi, QWORD PTR [rbx]
	sal	edi, 16
	or	edi, r15d
	call	writel@PLT
	mov	r9d, DWORD PTR 28[rsp]
	mov	rsi, QWORD PTR DC_OUTPUT_CFG[rip]
	add	rsi, QWORD PTR [rbx]
	mov	edi, r9d
	call	writel@PLT
	mov	r8d, DWORD PTR 24[rsp]
	mov	rsi, QWORD PTR DC_TIMING_CFG[rip]
	add	rsi, QWORD PTR [rbx]
	mov	edi, r8d
	call	writel@PLT
	mov	edi, 1000
	call	udelay@PLT
	mov	edi, r12d
	mov	rsi, QWORD PTR DC_GENERAL_CFG[rip]
	add	rsi, QWORD PTR [rbx]
	call	writel@PLT
	mov	rax, QWORD PTR 8[rbx]
	mov	rdi, rbp
	call	[QWORD PTR [rax]]
	mov	rsi, QWORD PTR DC_UNLOCK[rip]
	add	rsi, QWORD PTR [rbx]
	add	rsp, 40
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	xor	edi, edi
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	jmp	writel@PLT
	.cfi_endproc
.LFE0:
	.size	gx1_set_mode, .-gx1_set_mode
	.comm	DC_V_TIMING_3,8,8
	.comm	DC_V_TIMING_2,8,8
	.comm	DC_V_TIMING_1,8,8
	.comm	DC_UNLOCK_CODE,4,4
	.comm	DC_UNLOCK,8,8
	.comm	DC_TIMING_CFG,8,8
	.comm	DC_TCFG_VSYE,4,4
	.comm	DC_TCFG_TGEN,4,4
	.comm	DC_TCFG_HSYE,4,4
	.comm	DC_TCFG_FPPE,4,4
	.comm	DC_TCFG_BLKE,4,4
	.comm	DC_OUTPUT_CFG,8,8
	.comm	DC_OCFG_PDEL,4,4
	.comm	DC_OCFG_PDEH,4,4
	.comm	DC_OCFG_PCKE,4,4
	.comm	DC_OCFG_8BPP,4,4
	.comm	DC_LINE_DELTA,8,8
	.comm	DC_H_TIMING_3,8,8
	.comm	DC_H_TIMING_2,8,8
	.comm	DC_H_TIMING_1,8,8
	.comm	DC_GENERAL_CFG,8,8
	.comm	DC_GCFG_VRDY,4,4
	.comm	DC_GCFG_DFLE,4,4
	.comm	DC_GCFG_DFHPSL_POS,4,4
	.comm	DC_GCFG_DFHPEL_POS,4,4
	.comm	DC_GCFG_DECE,4,4
	.comm	DC_GCFG_DCLK_MASK,4,4
	.comm	DC_GCFG_DCLK_DIV_1,4,4
	.comm	DC_GCFG_CMPE,4,4
	.comm	DC_FP_V_TIMING,8,8
	.comm	DC_FP_H_TIMING,8,8
	.comm	DC_FB_ST_OFFSET,8,8
	.comm	DC_BUF_SIZE,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_display_gx1.c_gx1_set_mode.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	gx1_set_mode, %function
gx1_set_mode:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r4, [r0, #40]
	ldr	r6, .L5
	mov	r5, r0
	ldr	r3, [r6]
	ldr	r0, [r4]
	sub	sp, sp, #28
	add	r0, r0, r3
	bl	readl
	ldr	r0, [r4]
	ldr	r1, [r6]
	ldr	r3, .L5+4
	ldr	r9, .L5+8
	add	r1, r0, r1
	ldr	r0, [r3]
	bl	writel
	ldr	r3, [r9]
	ldr	r0, [r4]
	ldr	fp, .L5+12
	add	r0, r0, r3
	bl	readl
	ldr	ip, [r4]
	ldr	r1, [fp]
	str	r0, [sp]
	add	r0, ip, r1
	bl	readl
	ldr	r10, .L5+16
	ldr	r7, .L5+20
	ldr	ip, [r10]
	ldr	r6, [r7]
	ldr	lr, [r4]
	ldr	r1, [fp]
	orr	ip, ip, r6
	add	r1, lr, r1
	bic	r0, r0, ip
	bl	writel
	mov	r0, #100
	bl	udelay
	ldr	r8, .L5+24
	ldr	r1, .L5+28
	ldr	r0, .L5+32
	ldr	r6, [r8]
	ldr	r1, [r1]
	ldr	r0, [r0]
	ldr	r3, [sp]
	orr	r6, r6, r1
	ldr	ip, [r4]
	ldr	r1, [r9]
	orr	r6, r6, r0
	bic	r6, r3, r6
	add	r1, ip, r1
	mov	r0, r6
	bl	writel
	ldr	r3, .L5+36
	ldr	r1, [r4]
	ldr	r0, [r3]
	ldr	r3, [r9]
	bic	r6, r6, r0
	add	r1, r1, r3
	mov	r0, r6
	bl	writel
	ldr	r3, [r4, #4]
	mov	r0, r5
	ldr	r3, [r3, #4]
	blx	r3
	ldr	r3, .L5+40
	ldr	ip, [r4]
	ldr	r3, [r3]
	ldr	r1, [r9]
	orr	r0, r6, r3
	add	r1, ip, r1
	str	r3, [sp]
	bl	writel
	mov	r0, #1000
	bl	udelay
	mov	r0, #6
	mov	ip, #5
	ldr	lr, .L5+44
	ldr	r3, [sp]
	ldr	r6, [lr]
	ldr	r1, .L5+48
	ldr	lr, [r8]
	orr	r3, r3, r6
	ldr	r8, .L5+52
	ldr	r6, [r1]
	orr	r3, r3, lr
	ldr	lr, .L5+56
	ldr	r1, [r8]
	ldr	lr, [lr]
	orr	r3, r3, r0, lsl r6
	ldr	r0, [r4]
	orr	r3, r3, ip, lsl lr
	add	r1, r0, r1
	mov	r0, #0
	str	r3, [sp]
	bl	writel
	ldr	r3, .L5+60
	ldr	r1, [r4]
	ldr	r3, [r3]
	ldr	r0, [r5, #36]
	add	r1, r1, r3
	asr	r0, r0, #2
	bl	writel
	ldm	r5, {r0, r1}
	mul	r0, r1, r0
	cmp	r0, #0
	add	r1, r0, #7
	movlt	r0, r1
	ldr	r3, .L5+64
	ldr	r1, [r4]
	ldr	r3, [r3]
	asr	r0, r0, #6
	add	r1, r1, r3
	add	r0, r0, #2
	bl	writel
	ldr	r3, .L5+68
	ldr	r0, .L5+72
	ldr	r1, .L5+76
	ldr	ip, [r5, #4]
	ldr	r0, [r0]
	ldr	r3, [r3]
	ldr	r1, [r1]
	cmp	ip, #8
	orr	r3, r3, r0
	orr	r2, r3, r1
	ldreq	r3, .L5+80
	ldr	lr, [r5]
	ldreq	r3, [r3]
	ldr	ip, [r5, #8]
	orreq	r2, r2, r3
	ldr	r8, [r5, #12]
	ldr	r0, .L5+84
	ldr	r1, .L5+88
	ldr	r3, .L5+92
	str	r2, [sp, #20]
	add	r2, lr, ip
	ldr	r6, [r0]
	ldr	ip, [r1]
	add	r0, r2, r8
	ldr	r8, [r3]
	ldr	r3, [r5, #16]
	ldr	r1, .L5+96
	str	r2, [sp, #4]
	add	r3, r0, r3
	ldr	r2, [r5, #20]
	orr	r6, r6, ip
	ldr	ip, [r7]
	ldr	r7, [r5, #24]
	str	r0, [sp, #8]
	ldr	r1, [r1]
	ldr	r0, [r10]
	sub	lr, lr, #1
	ldr	r10, [r4]
	orr	r6, r6, r8
	sub	r3, r3, #1
	ldr	r8, [r5, #28]
	add	r7, r2, r7
	orr	r3, lr, r3, lsl #16
	ldr	lr, [r5, #32]
	add	r8, r7, r8
	add	r1, r10, r1
	orr	r6, r6, r0
	mov	r0, r3
	add	r10, r8, lr
	str	r2, [sp, #12]
	orr	r6, r6, ip
	str	r3, [sp, #16]
	bl	writel
	ldr	r1, .L5+100
	ldr	ip, [r4]
	ldr	r3, [sp, #16]
	ldr	r1, [r1]
	mov	r0, r3
	add	r1, ip, r1
	bl	writel
	ldr	r2, [sp, #4]
	ldr	r0, [sp, #8]
	ldr	r1, .L5+104
	ldr	ip, [r4]
	sub	r3, r2, #1
	ldr	r1, [r1]
	sub	r0, r0, #1
	orr	r3, r3, r0, lsl #16
	add	r1, ip, r1
	mov	r0, r3
	str	r3, [sp, #4]
	bl	writel
	ldr	r1, .L5+108
	ldr	ip, [r4]
	ldr	r3, [sp, #4]
	ldr	r1, [r1]
	mov	r0, r3
	add	r1, ip, r1
	bl	writel
	ldr	r2, [sp, #12]
	ldr	r3, .L5+112
	ldr	r1, [r4]
	ldr	r3, [r3]
	sub	r0, r10, #1
	sub	r10, r2, #1
	orr	r10, r10, r0, lsl #16
	add	r1, r1, r3
	mov	r0, r10
	bl	writel
	ldr	r3, .L5+116
	ldr	r1, [r4]
	ldr	r3, [r3]
	mov	r0, r10
	add	r1, r1, r3
	bl	writel
	ldr	r3, .L5+120
	ldr	r1, [r4]
	ldr	r3, [r3]
	sub	ip, r8, #1
	sub	r0, r7, #1
	orr	r0, r0, ip, lsl #16
	add	r1, r1, r3
	bl	writel
	ldr	r3, .L5+124
	ldr	r1, [r4]
	ldr	r3, [r3]
	sub	r0, r8, #2
	sub	r7, r7, #2
	add	r1, r1, r3
	orr	r0, r7, r0, lsl #16
	bl	writel
	ldr	r3, .L5+128
	ldr	r2, [sp, #20]
	ldr	r1, [r4]
	ldr	r3, [r3]
	mov	r0, r2
	add	r1, r1, r3
	bl	writel
	ldr	r3, [fp]
	ldr	r1, [r4]
	mov	r0, r6
	add	r1, r1, r3
	bl	writel
	mov	r0, #1000
	bl	udelay
	ldr	r3, [r9]
	ldr	r1, [r4]
	ldr	r0, [sp]
	add	r1, r1, r3
	bl	writel
	ldr	r3, [r4, #4]
	mov	r0, r5
	ldr	r3, [r3]
	blx	r3
	mov	r0, #0
	ldr	r3, .L5
	ldr	r1, [r4]
	ldr	r3, [r3]
	add	r1, r1, r3
	add	sp, sp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	b	writel
.L6:
	.align	2
.L5:
	.word	DC_UNLOCK
	.word	DC_UNLOCK_CODE
	.word	DC_GENERAL_CFG
	.word	DC_TIMING_CFG
	.word	DC_TCFG_BLKE
	.word	DC_TCFG_TGEN
	.word	DC_GCFG_DFLE
	.word	DC_GCFG_CMPE
	.word	DC_GCFG_DECE
	.word	DC_GCFG_DCLK_MASK
	.word	DC_GCFG_DCLK_DIV_1
	.word	DC_GCFG_VRDY
	.word	DC_GCFG_DFHPEL_POS
	.word	DC_FB_ST_OFFSET
	.word	DC_GCFG_DFHPSL_POS
	.word	DC_LINE_DELTA
	.word	DC_BUF_SIZE
	.word	DC_OCFG_PCKE
	.word	DC_OCFG_PDEL
	.word	DC_OCFG_PDEH
	.word	DC_OCFG_8BPP
	.word	DC_TCFG_FPPE
	.word	DC_TCFG_HSYE
	.word	DC_TCFG_VSYE
	.word	DC_H_TIMING_1
	.word	DC_H_TIMING_2
	.word	DC_H_TIMING_3
	.word	DC_FP_H_TIMING
	.word	DC_V_TIMING_1
	.word	DC_V_TIMING_2
	.word	DC_V_TIMING_3
	.word	DC_FP_V_TIMING
	.word	DC_OUTPUT_CFG
	.size	gx1_set_mode, .-gx1_set_mode
	.comm	DC_V_TIMING_3,4,4
	.comm	DC_V_TIMING_2,4,4
	.comm	DC_V_TIMING_1,4,4
	.comm	DC_UNLOCK_CODE,4,4
	.comm	DC_UNLOCK,4,4
	.comm	DC_TIMING_CFG,4,4
	.comm	DC_TCFG_VSYE,4,4
	.comm	DC_TCFG_TGEN,4,4
	.comm	DC_TCFG_HSYE,4,4
	.comm	DC_TCFG_FPPE,4,4
	.comm	DC_TCFG_BLKE,4,4
	.comm	DC_OUTPUT_CFG,4,4
	.comm	DC_OCFG_PDEL,4,4
	.comm	DC_OCFG_PDEH,4,4
	.comm	DC_OCFG_PCKE,4,4
	.comm	DC_OCFG_8BPP,4,4
	.comm	DC_LINE_DELTA,4,4
	.comm	DC_H_TIMING_3,4,4
	.comm	DC_H_TIMING_2,4,4
	.comm	DC_H_TIMING_1,4,4
	.comm	DC_GENERAL_CFG,4,4
	.comm	DC_GCFG_VRDY,4,4
	.comm	DC_GCFG_DFLE,4,4
	.comm	DC_GCFG_DFHPSL_POS,4,4
	.comm	DC_GCFG_DFHPEL_POS,4,4
	.comm	DC_GCFG_DECE,4,4
	.comm	DC_GCFG_DCLK_MASK,4,4
	.comm	DC_GCFG_DCLK_DIV_1,4,4
	.comm	DC_GCFG_CMPE,4,4
	.comm	DC_FP_V_TIMING,4,4
	.comm	DC_FP_H_TIMING,4,4
	.comm	DC_FB_ST_OFFSET,4,4
	.comm	DC_BUF_SIZE,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
