	.file	"extr_ni.c_cayman_gpu_check_soft_reset.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"MC busy: 0x%08X, clearing.\n"
	.text
	.p2align 4
	.type	cayman_gpu_check_soft_reset, @function
cayman_gpu_check_soft_reset:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	push	rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	mov	rbp, rdi
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	mov	rdi, QWORD PTR GRBM_STATUS[rip]
	call	RREG32@PLT
	mov	r12d, DWORD PTR PA_BUSY[rip]
	or	r12d, DWORD PTR SC_BUSY[rip]
	or	r12d, DWORD PTR SH_BUSY[rip]
	or	r12d, DWORD PTR SX_BUSY[rip]
	or	r12d, DWORD PTR TA_BUSY[rip]
	or	r12d, DWORD PTR VGT_BUSY[rip]
	or	r12d, DWORD PTR DB_BUSY[rip]
	or	r12d, DWORD PTR CB_BUSY[rip]
	or	r12d, DWORD PTR GDS_BUSY[rip]
	or	r12d, DWORD PTR SPI_BUSY[rip]
	or	r12d, DWORD PTR IA_BUSY[rip]
	or	r12d, DWORD PTR IA_BUSY_NO_DMA[rip]
	and	r12d, eax
	mov	edx, DWORD PTR CF_RQ_PENDING[rip]
	cmovne	r12d, DWORD PTR RADEON_RESET_GFX[rip]
	or	edx, DWORD PTR PF_RQ_PENDING[rip]
	or	edx, DWORD PTR CP_BUSY[rip]
	or	edx, DWORD PTR CP_COHERENCY_BUSY[rip]
	test	edx, eax
	je	.L3
	or	r12d, DWORD PTR RADEON_RESET_CP[rip]
.L3:
	test	DWORD PTR GRBM_EE_BUSY[rip], eax
	je	.L4
	mov	eax, DWORD PTR RADEON_RESET_GRBM[rip]
	or	eax, DWORD PTR RADEON_RESET_GFX[rip]
	or	eax, DWORD PTR RADEON_RESET_CP[rip]
	or	r12d, eax
.L4:
	mov	rdi, QWORD PTR DMA0_REGISTER_OFFSET[rip]
	add	rdi, QWORD PTR DMA_STATUS_REG[rip]
	call	RREG32@PLT
	test	DWORD PTR DMA_IDLE[rip], eax
	jne	.L5
	or	r12d, DWORD PTR RADEON_RESET_DMA[rip]
.L5:
	mov	rdi, QWORD PTR DMA1_REGISTER_OFFSET[rip]
	add	rdi, QWORD PTR DMA_STATUS_REG[rip]
	call	RREG32@PLT
	test	DWORD PTR DMA_IDLE[rip], eax
	jne	.L6
	or	r12d, DWORD PTR RADEON_RESET_DMA1[rip]
.L6:
	mov	rdi, QWORD PTR SRBM_STATUS2[rip]
	call	RREG32@PLT
	test	DWORD PTR DMA_BUSY[rip], eax
	je	.L7
	or	r12d, DWORD PTR RADEON_RESET_DMA[rip]
.L7:
	test	DWORD PTR DMA1_BUSY[rip], eax
	je	.L8
	or	r12d, DWORD PTR RADEON_RESET_DMA1[rip]
.L8:
	mov	rdi, QWORD PTR SRBM_STATUS[rip]
	call	RREG32@PLT
	mov	edx, DWORD PTR RLC_RQ_PENDING[rip]
	or	edx, DWORD PTR RLC_BUSY[rip]
	test	edx, eax
	je	.L9
	or	r12d, DWORD PTR RADEON_RESET_RLC[rip]
.L9:
	test	DWORD PTR IH_BUSY[rip], eax
	je	.L10
	or	r12d, DWORD PTR RADEON_RESET_IH[rip]
.L10:
	test	DWORD PTR SEM_BUSY[rip], eax
	je	.L11
	or	r12d, DWORD PTR RADEON_RESET_SEM[rip]
.L11:
	test	DWORD PTR GRBM_RQ_PENDING[rip], eax
	je	.L12
	or	r12d, DWORD PTR RADEON_RESET_GRBM[rip]
.L12:
	test	DWORD PTR VMC_BUSY[rip], eax
	je	.L13
	or	r12d, DWORD PTR RADEON_RESET_VMC[rip]
.L13:
	mov	edx, DWORD PTR MCB_BUSY[rip]
	or	edx, DWORD PTR MCB_NON_DISPLAY_BUSY[rip]
	or	edx, DWORD PTR MCC_BUSY[rip]
	or	edx, DWORD PTR MCD_BUSY[rip]
	test	edx, eax
	je	.L14
	or	r12d, DWORD PTR RADEON_RESET_MC[rip]
.L14:
	mov	rdi, rbp
	call	evergreen_is_display_hung@PLT
	test	rax, rax
	je	.L15
	or	r12d, DWORD PTR RADEON_RESET_DISPLAY[rip]
.L15:
	mov	rdi, QWORD PTR VM_L2_STATUS[rip]
	call	RREG32@PLT
	test	DWORD PTR L2_BUSY[rip], eax
	je	.L16
	or	r12d, DWORD PTR RADEON_RESET_VMC[rip]
.L16:
	test	DWORD PTR RADEON_RESET_MC[rip], r12d
	jne	.L61
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	mov	eax, r12d
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L61:
	.cfi_restore_state
	mov	esi, r12d
	lea	rdi, .LC0[rip]
	call	DRM_DEBUG@PLT
	mov	eax, DWORD PTR RADEON_RESET_MC[rip]
	add	rsp, 8
	.cfi_def_cfa_offset 24
	pop	rbp
	.cfi_def_cfa_offset 16
	not	eax
	and	r12d, eax
	mov	eax, r12d
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE0:
	.size	cayman_gpu_check_soft_reset, .-cayman_gpu_check_soft_reset
	.comm	VM_L2_STATUS,8,8
	.comm	VMC_BUSY,4,4
	.comm	VGT_BUSY,4,4
	.comm	TA_BUSY,4,4
	.comm	SX_BUSY,4,4
	.comm	SRBM_STATUS2,8,8
	.comm	SRBM_STATUS,8,8
	.comm	SPI_BUSY,4,4
	.comm	SH_BUSY,4,4
	.comm	SEM_BUSY,4,4
	.comm	SC_BUSY,4,4
	.comm	RLC_RQ_PENDING,4,4
	.comm	RLC_BUSY,4,4
	.comm	RADEON_RESET_VMC,4,4
	.comm	RADEON_RESET_SEM,4,4
	.comm	RADEON_RESET_RLC,4,4
	.comm	RADEON_RESET_MC,4,4
	.comm	RADEON_RESET_IH,4,4
	.comm	RADEON_RESET_GRBM,4,4
	.comm	RADEON_RESET_GFX,4,4
	.comm	RADEON_RESET_DMA1,4,4
	.comm	RADEON_RESET_DMA,4,4
	.comm	RADEON_RESET_DISPLAY,4,4
	.comm	RADEON_RESET_CP,4,4
	.comm	PF_RQ_PENDING,4,4
	.comm	PA_BUSY,4,4
	.comm	MCD_BUSY,4,4
	.comm	MCC_BUSY,4,4
	.comm	MCB_NON_DISPLAY_BUSY,4,4
	.comm	MCB_BUSY,4,4
	.comm	L2_BUSY,4,4
	.comm	IH_BUSY,4,4
	.comm	IA_BUSY_NO_DMA,4,4
	.comm	IA_BUSY,4,4
	.comm	GRBM_STATUS,8,8
	.comm	GRBM_RQ_PENDING,4,4
	.comm	GRBM_EE_BUSY,4,4
	.comm	GDS_BUSY,4,4
	.comm	DMA_STATUS_REG,8,8
	.comm	DMA_IDLE,4,4
	.comm	DMA_BUSY,4,4
	.comm	DMA1_REGISTER_OFFSET,8,8
	.comm	DMA1_BUSY,4,4
	.comm	DMA0_REGISTER_OFFSET,8,8
	.comm	DB_BUSY,4,4
	.comm	CP_COHERENCY_BUSY,4,4
	.comm	CP_BUSY,4,4
	.comm	CF_RQ_PENDING,4,4
	.comm	CB_BUSY,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_ni.c_cayman_gpu_check_soft_reset.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"MC busy: 0x%08X, clearing.\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	cayman_gpu_check_soft_reset, %function
cayman_gpu_check_soft_reset:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	ldr	r3, .L63
	push	{r4, r5, r6, r7, r8, lr}
	mov	r5, r0
	ldr	r0, [r3]
	bl	RREG32
	ldr	r1, .L63+4
	ldr	r3, .L63+8
	ldr	r2, .L63+12
	ldr	r4, [r1]
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	r1, .L63+16
	orr	r4, r4, r3
	ldr	r3, .L63+20
	ldr	r1, [r1]
	orr	r4, r4, r2
	ldr	r2, .L63+24
	ldr	r3, [r3]
	ldr	r2, [r2]
	orr	r4, r4, r1
	ldr	r1, .L63+28
	orr	r4, r4, r3
	ldr	r3, .L63+32
	ldr	r1, [r1]
	orr	r4, r4, r2
	ldr	r2, .L63+36
	ldr	r3, [r3]
	ldr	r2, [r2]
	orr	r4, r4, r1
	ldr	r1, .L63+40
	orr	r4, r4, r3
	ldr	r3, .L63+44
	ldr	r1, [r1]
	orr	r4, r4, r2
	ldr	r2, .L63+48
	ldr	r3, [r3]
	orr	r4, r4, r1
	ldr	r1, [r2]
	orr	r4, r4, r3
	orr	r4, r4, r1
	ands	r4, r4, r0
	ldrne	r3, .L63+52
	ldr	r2, .L63+56
	ldrne	r4, [r3]
	ldr	r3, .L63+60
	ldr	r2, [r2]
	ldr	r3, [r3]
	ldr	r1, .L63+64
	orr	r3, r3, r2
	ldr	r2, .L63+68
	ldr	r1, [r1]
	ldr	r2, [r2]
	orr	r3, r3, r1
	orr	r3, r3, r2
	tst	r3, r0
	ldrne	r3, .L63+72
	ldrne	r3, [r3]
	orrne	r4, r4, r3
	ldr	r3, .L63+76
	ldr	r3, [r3]
	tst	r0, r3
	beq	.L4
	ldr	r3, .L63+80
	ldr	r1, .L63+52
	ldr	r2, .L63+72
	ldr	r3, [r3]
	ldr	r1, [r1]
	ldr	r2, [r2]
	orr	r3, r3, r1
	orr	r3, r3, r2
	orr	r4, r4, r3
.L4:
	ldr	r7, .L63+84
	ldr	r3, .L63+88
	ldr	r0, [r7]
	ldr	r3, [r3]
	ldr	r6, .L63+92
	add	r0, r0, r3
	bl	RREG32
	ldr	r3, [r6]
	tst	r0, r3
	ldreq	r3, .L63+96
	ldr	r0, [r7]
	ldreq	r3, [r3]
	orreq	r4, r4, r3
	ldr	r3, .L63+100
	ldr	r3, [r3]
	add	r0, r0, r3
	bl	RREG32
	ldr	r3, [r6]
	ldr	r6, .L63+104
	tst	r0, r3
	ldreq	r3, .L63+108
	ldreq	r3, [r3]
	orreq	r4, r4, r3
	ldr	r3, .L63+112
	ldr	r0, [r3]
	bl	RREG32
	ldr	r3, .L63+116
	ldr	r3, [r3]
	tst	r0, r3
	ldrne	r3, .L63+96
	ldrne	r3, [r3]
	orrne	r4, r4, r3
	ldr	r3, .L63+120
	ldr	r3, [r3]
	tst	r0, r3
	ldrne	r3, .L63+108
	ldrne	r3, [r3]
	orrne	r4, r4, r3
	ldr	r3, .L63+124
	ldr	r0, [r3]
	bl	RREG32
	ldr	r3, .L63+128
	ldr	r2, .L63+132
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	r1, .L63+136
	orr	r3, r3, r2
	tst	r3, r0
	ldrne	r3, .L63+140
	ldr	r2, .L63+144
	ldrne	r3, [r3]
	ldr	r2, [r2]
	orrne	r4, r4, r3
	ldr	r3, .L63+148
	ldr	r1, [r1]
	ldr	r3, [r3]
	tst	r0, r3
	ldrne	r3, .L63+152
	ldrne	r3, [r3]
	orrne	r4, r4, r3
	ldr	r3, .L63+156
	ldr	r3, [r3]
	tst	r0, r3
	ldrne	r3, .L63+160
	ldrne	r3, [r3]
	orrne	r4, r4, r3
	ldr	r3, .L63+164
	ldr	r3, [r3]
	tst	r0, r3
	ldrne	r3, .L63+80
	ldrne	r3, [r3]
	orrne	r4, r4, r3
	ldr	r3, .L63+168
	ldr	r3, [r3]
	tst	r0, r3
	ldrne	r3, .L63+172
	ldrne	r3, [r3]
	orrne	r4, r4, r3
	ldr	r3, .L63+176
	ldr	r3, [r3]
	orr	r3, r3, r2
	ldr	r2, .L63+180
	orr	r3, r3, r1
	ldr	r2, [r2]
	orr	r3, r3, r2
	tst	r3, r0
	ldrne	r3, [r6]
	mov	r0, r5
	orrne	r4, r4, r3
	bl	evergreen_is_display_hung
	cmp	r0, #0
	ldrne	r3, .L63+184
	ldrne	r3, [r3]
	orrne	r4, r4, r3
	ldr	r3, .L63+188
	ldr	r0, [r3]
	bl	RREG32
	ldr	r3, .L63+192
	ldr	r3, [r3]
	tst	r0, r3
	ldrne	r3, .L63+172
	ldrne	r3, [r3]
	orrne	r4, r4, r3
	ldr	r3, [r6]
	tst	r4, r3
	bne	.L62
	mov	r0, r4
	pop	{r4, r5, r6, r7, r8, pc}
.L62:
	mov	r1, r4
	ldr	r0, .L63+196
	bl	DRM_DEBUG
	ldr	r3, [r6]
	bic	r4, r4, r3
	mov	r0, r4
	pop	{r4, r5, r6, r7, r8, pc}
.L64:
	.align	2
.L63:
	.word	GRBM_STATUS
	.word	PA_BUSY
	.word	SC_BUSY
	.word	SH_BUSY
	.word	SX_BUSY
	.word	TA_BUSY
	.word	VGT_BUSY
	.word	DB_BUSY
	.word	CB_BUSY
	.word	GDS_BUSY
	.word	SPI_BUSY
	.word	IA_BUSY
	.word	IA_BUSY_NO_DMA
	.word	RADEON_RESET_GFX
	.word	PF_RQ_PENDING
	.word	CF_RQ_PENDING
	.word	CP_BUSY
	.word	CP_COHERENCY_BUSY
	.word	RADEON_RESET_CP
	.word	GRBM_EE_BUSY
	.word	RADEON_RESET_GRBM
	.word	DMA_STATUS_REG
	.word	DMA0_REGISTER_OFFSET
	.word	DMA_IDLE
	.word	RADEON_RESET_DMA
	.word	DMA1_REGISTER_OFFSET
	.word	RADEON_RESET_MC
	.word	RADEON_RESET_DMA1
	.word	SRBM_STATUS2
	.word	DMA_BUSY
	.word	DMA1_BUSY
	.word	SRBM_STATUS
	.word	RLC_RQ_PENDING
	.word	RLC_BUSY
	.word	MCC_BUSY
	.word	RADEON_RESET_RLC
	.word	MCB_NON_DISPLAY_BUSY
	.word	IH_BUSY
	.word	RADEON_RESET_IH
	.word	SEM_BUSY
	.word	RADEON_RESET_SEM
	.word	GRBM_RQ_PENDING
	.word	VMC_BUSY
	.word	RADEON_RESET_VMC
	.word	MCB_BUSY
	.word	MCD_BUSY
	.word	RADEON_RESET_DISPLAY
	.word	VM_L2_STATUS
	.word	L2_BUSY
	.word	.LC0
	.size	cayman_gpu_check_soft_reset, .-cayman_gpu_check_soft_reset
	.comm	VM_L2_STATUS,4,4
	.comm	VMC_BUSY,4,4
	.comm	VGT_BUSY,4,4
	.comm	TA_BUSY,4,4
	.comm	SX_BUSY,4,4
	.comm	SRBM_STATUS2,4,4
	.comm	SRBM_STATUS,4,4
	.comm	SPI_BUSY,4,4
	.comm	SH_BUSY,4,4
	.comm	SEM_BUSY,4,4
	.comm	SC_BUSY,4,4
	.comm	RLC_RQ_PENDING,4,4
	.comm	RLC_BUSY,4,4
	.comm	RADEON_RESET_VMC,4,4
	.comm	RADEON_RESET_SEM,4,4
	.comm	RADEON_RESET_RLC,4,4
	.comm	RADEON_RESET_MC,4,4
	.comm	RADEON_RESET_IH,4,4
	.comm	RADEON_RESET_GRBM,4,4
	.comm	RADEON_RESET_GFX,4,4
	.comm	RADEON_RESET_DMA1,4,4
	.comm	RADEON_RESET_DMA,4,4
	.comm	RADEON_RESET_DISPLAY,4,4
	.comm	RADEON_RESET_CP,4,4
	.comm	PF_RQ_PENDING,4,4
	.comm	PA_BUSY,4,4
	.comm	MCD_BUSY,4,4
	.comm	MCC_BUSY,4,4
	.comm	MCB_NON_DISPLAY_BUSY,4,4
	.comm	MCB_BUSY,4,4
	.comm	L2_BUSY,4,4
	.comm	IH_BUSY,4,4
	.comm	IA_BUSY_NO_DMA,4,4
	.comm	IA_BUSY,4,4
	.comm	GRBM_STATUS,4,4
	.comm	GRBM_RQ_PENDING,4,4
	.comm	GRBM_EE_BUSY,4,4
	.comm	GDS_BUSY,4,4
	.comm	DMA_STATUS_REG,4,4
	.comm	DMA_IDLE,4,4
	.comm	DMA_BUSY,4,4
	.comm	DMA1_REGISTER_OFFSET,4,4
	.comm	DMA1_BUSY,4,4
	.comm	DMA0_REGISTER_OFFSET,4,4
	.comm	DB_BUSY,4,4
	.comm	CP_COHERENCY_BUSY,4,4
	.comm	CP_BUSY,4,4
	.comm	CF_RQ_PENDING,4,4
	.comm	CB_BUSY,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
