	.file	"extr_asic3.c_asic3_mmc_enable.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	asic3_mmc_enable, @function
asic3_mmc_enable:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	mov	edi, DWORD PTR [rdi]
	call	dev_get_drvdata@PLT
	mov	esi, DWORD PTR SDCONF[rip]
	mov	edi, DWORD PTR SDHWCTRL[rip]
	mov	r12d, DWORD PTR ASIC3_SDHWCTRL_LEVCD[rip]
	mov	rbx, rax
	call	ASIC3_OFFSET@PLT
	mov	ecx, 1
	mov	rdi, rbx
	mov	edx, r12d
	mov	esi, eax
	call	asic3_set_register@PLT
	mov	esi, DWORD PTR SDCONF[rip]
	mov	edi, DWORD PTR SDHWCTRL[rip]
	mov	r12d, DWORD PTR ASIC3_SDHWCTRL_LEVWP[rip]
	call	ASIC3_OFFSET@PLT
	mov	ecx, 1
	mov	rdi, rbx
	mov	edx, r12d
	mov	esi, eax
	call	asic3_set_register@PLT
	mov	esi, DWORD PTR SDCONF[rip]
	mov	edi, DWORD PTR SDHWCTRL[rip]
	mov	r12d, DWORD PTR ASIC3_SDHWCTRL_SUSPEND[rip]
	call	ASIC3_OFFSET@PLT
	xor	ecx, ecx
	mov	rdi, rbx
	mov	edx, r12d
	mov	esi, eax
	call	asic3_set_register@PLT
	mov	esi, DWORD PTR SDCONF[rip]
	mov	edi, DWORD PTR SDHWCTRL[rip]
	mov	r12d, DWORD PTR ASIC3_SDHWCTRL_PCLR[rip]
	call	ASIC3_OFFSET@PLT
	xor	ecx, ecx
	mov	rdi, rbx
	mov	edx, r12d
	mov	esi, eax
	call	asic3_set_register@PLT
	mov	rax, QWORD PTR 16[rbx]
	mov	rdx, QWORD PTR ASIC3_CLOCK_EX0[rip]
	mov	rdi, rbx
	lea	rsi, [rax+rdx*4]
	call	asic3_clk_enable@PLT
	mov	rdx, QWORD PTR ASIC3_CLOCK_EX1[rip]
	mov	rax, QWORD PTR 16[rbx]
	mov	rdi, rbx
	lea	rsi, [rax+rdx*4]
	call	asic3_clk_enable@PLT
	mov	esi, 5000
	mov	edi, 1000
	call	usleep_range@PLT
	mov	esi, DWORD PTR SEL[rip]
	mov	edi, DWORD PTR CLOCK[rip]
	mov	r12d, DWORD PTR CLOCK_SEL_CX[rip]
	or	r12d, DWORD PTR CLOCK_SEL_SD_HCLK_SEL[rip]
	call	ASIC3_OFFSET@PLT
	mov	edx, r12d
	mov	rdi, rbx
	mov	esi, eax
	call	asic3_write_register@PLT
	mov	rax, QWORD PTR 16[rbx]
	mov	rdx, QWORD PTR ASIC3_CLOCK_SD_HOST[rip]
	mov	rdi, rbx
	lea	rsi, [rax+rdx*4]
	call	asic3_clk_enable@PLT
	mov	rdx, QWORD PTR ASIC3_CLOCK_SD_BUS[rip]
	mov	rax, QWORD PTR 16[rbx]
	mov	rdi, rbx
	lea	rsi, [rax+rdx*4]
	call	asic3_clk_enable@PLT
	mov	esi, 5000
	mov	edi, 1000
	call	usleep_range@PLT
	mov	esi, DWORD PTR SELECT[rip]
	mov	edi, DWORD PTR EXTCF[rip]
	mov	r12d, DWORD PTR ASIC3_EXTCF_SD_MEM_ENABLE[rip]
	call	ASIC3_OFFSET@PLT
	mov	ecx, 1
	mov	rdi, rbx
	mov	edx, r12d
	mov	esi, eax
	call	asic3_set_register@PLT
	mov	esi, DWORD PTR SDCONF[rip]
	mov	edi, DWORD PTR SDHWCTRL[rip]
	mov	r12d, DWORD PTR ASIC3_SDHWCTRL_SDPWR[rip]
	call	ASIC3_OFFSET@PLT
	mov	rdi, rbx
	mov	ecx, 1
	mov	edx, r12d
	mov	esi, eax
	call	asic3_set_register@PLT
	mov	edx, DWORD PTR ASIC3_SD_CTRL_BASE[rip]
	mov	edi, DWORD PTR 8[rbx]
	mov	esi, 1
	sub	rsi, QWORD PTR [rbx]
	sar	edx
	call	tmio_core_mmc_enable@PLT
	add	rsp, 8
	.cfi_def_cfa_offset 24
	xor	eax, eax
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE0:
	.size	asic3_mmc_enable, .-asic3_mmc_enable
	.comm	SELECT,4,4
	.comm	SEL,4,4
	.comm	SDHWCTRL,4,4
	.comm	SDCONF,4,4
	.comm	EXTCF,4,4
	.comm	CLOCK_SEL_SD_HCLK_SEL,4,4
	.comm	CLOCK_SEL_CX,4,4
	.comm	CLOCK,4,4
	.comm	ASIC3_SD_CTRL_BASE,4,4
	.comm	ASIC3_SDHWCTRL_SUSPEND,4,4
	.comm	ASIC3_SDHWCTRL_SDPWR,4,4
	.comm	ASIC3_SDHWCTRL_PCLR,4,4
	.comm	ASIC3_SDHWCTRL_LEVWP,4,4
	.comm	ASIC3_SDHWCTRL_LEVCD,4,4
	.comm	ASIC3_EXTCF_SD_MEM_ENABLE,4,4
	.comm	ASIC3_CLOCK_SD_HOST,8,8
	.comm	ASIC3_CLOCK_SD_BUS,8,8
	.comm	ASIC3_CLOCK_EX1,8,8
	.comm	ASIC3_CLOCK_EX0,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_asic3.c_asic3_mmc_enable.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	asic3_mmc_enable, %function
asic3_mmc_enable:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	ldr	r0, [r0]
	bl	dev_get_drvdata
	ldr	r6, .L4
	ldr	r5, .L4+4
	mov	r4, r0
	ldr	r1, [r6]
	ldr	r0, [r5]
	bl	ASIC3_OFFSET
	ldr	r3, .L4+8
	mov	r1, r0
	ldr	r2, [r3]
	mov	r0, r4
	mov	r3, #1
	bl	asic3_set_register
	ldr	r1, [r6]
	ldr	r0, [r5]
	bl	ASIC3_OFFSET
	ldr	r3, .L4+12
	mov	r1, r0
	ldr	r2, [r3]
	mov	r0, r4
	mov	r3, #1
	bl	asic3_set_register
	ldr	r1, [r6]
	ldr	r0, [r5]
	bl	ASIC3_OFFSET
	ldr	r3, .L4+16
	mov	r1, r0
	ldr	r2, [r3]
	mov	r0, r4
	mov	r3, #0
	bl	asic3_set_register
	ldr	r1, [r6]
	ldr	r0, [r5]
	bl	ASIC3_OFFSET
	ldr	r3, .L4+20
	mov	r1, r0
	ldr	r2, [r3]
	mov	r0, r4
	mov	r3, #0
	bl	asic3_set_register
	ldr	r2, .L4+24
	ldr	r3, [r4, #8]
	ldr	r1, [r2]
	mov	r0, r4
	add	r1, r3, r1, lsl #2
	bl	asic3_clk_enable
	ldr	r2, .L4+28
	ldr	r3, [r4, #8]
	ldr	r1, [r2]
	ldr	r7, .L4+32
	add	r1, r3, r1, lsl #2
	mov	r0, r4
	bl	asic3_clk_enable
	mov	r1, r7
	mov	r0, #1000
	bl	usleep_range
	ldr	r2, .L4+36
	ldr	r3, .L4+40
	ldr	r1, [r2]
	ldr	r0, [r3]
	bl	ASIC3_OFFSET
	ldr	r2, .L4+44
	ldr	r3, .L4+48
	ldr	r2, [r2]
	ldr	r3, [r3]
	mov	r1, r0
	orr	r2, r2, r3
	mov	r0, r4
	bl	asic3_write_register
	ldr	r2, .L4+52
	ldr	r3, [r4, #8]
	ldr	r1, [r2]
	mov	r0, r4
	add	r1, r3, r1, lsl #2
	bl	asic3_clk_enable
	ldr	r2, .L4+56
	ldr	r3, [r4, #8]
	ldr	r1, [r2]
	mov	r0, r4
	add	r1, r3, r1, lsl #2
	bl	asic3_clk_enable
	mov	r1, r7
	mov	r0, #1000
	bl	usleep_range
	ldr	r2, .L4+60
	ldr	r3, .L4+64
	ldr	r1, [r2]
	ldr	r0, [r3]
	bl	ASIC3_OFFSET
	ldr	r3, .L4+68
	mov	r1, r0
	ldr	r2, [r3]
	mov	r0, r4
	mov	r3, #1
	bl	asic3_set_register
	ldr	r1, [r6]
	ldr	r0, [r5]
	bl	ASIC3_OFFSET
	ldr	r3, .L4+72
	mov	r1, r0
	ldr	r2, [r3]
	mov	r0, r4
	mov	r3, #1
	bl	asic3_set_register
	ldr	r3, .L4+76
	ldr	r1, [r4]
	ldr	r2, [r3]
	ldr	r0, [r4, #4]
	rsb	r1, r1, #1
	asr	r2, r2, #1
	bl	tmio_core_mmc_enable
	mov	r0, #0
	pop	{r4, r5, r6, r7, r8, pc}
.L5:
	.align	2
.L4:
	.word	SDCONF
	.word	SDHWCTRL
	.word	ASIC3_SDHWCTRL_LEVCD
	.word	ASIC3_SDHWCTRL_LEVWP
	.word	ASIC3_SDHWCTRL_SUSPEND
	.word	ASIC3_SDHWCTRL_PCLR
	.word	ASIC3_CLOCK_EX0
	.word	ASIC3_CLOCK_EX1
	.word	5000
	.word	SEL
	.word	CLOCK
	.word	CLOCK_SEL_CX
	.word	CLOCK_SEL_SD_HCLK_SEL
	.word	ASIC3_CLOCK_SD_HOST
	.word	ASIC3_CLOCK_SD_BUS
	.word	SELECT
	.word	EXTCF
	.word	ASIC3_EXTCF_SD_MEM_ENABLE
	.word	ASIC3_SDHWCTRL_SDPWR
	.word	ASIC3_SD_CTRL_BASE
	.size	asic3_mmc_enable, .-asic3_mmc_enable
	.comm	SELECT,4,4
	.comm	SEL,4,4
	.comm	SDHWCTRL,4,4
	.comm	SDCONF,4,4
	.comm	EXTCF,4,4
	.comm	CLOCK_SEL_SD_HCLK_SEL,4,4
	.comm	CLOCK_SEL_CX,4,4
	.comm	CLOCK,4,4
	.comm	ASIC3_SD_CTRL_BASE,4,4
	.comm	ASIC3_SDHWCTRL_SUSPEND,4,4
	.comm	ASIC3_SDHWCTRL_SDPWR,4,4
	.comm	ASIC3_SDHWCTRL_PCLR,4,4
	.comm	ASIC3_SDHWCTRL_LEVWP,4,4
	.comm	ASIC3_SDHWCTRL_LEVCD,4,4
	.comm	ASIC3_EXTCF_SD_MEM_ENABLE,4,4
	.comm	ASIC3_CLOCK_SD_HOST,4,4
	.comm	ASIC3_CLOCK_SD_BUS,4,4
	.comm	ASIC3_CLOCK_EX1,4,4
	.comm	ASIC3_CLOCK_EX0,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
