	.file	"extr_pmu.c_reprogram_gp_counter.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC0:
	.string	"kvm pmu: pin control bit is ignored\n"
	.text
	.p2align 4
	.type	reprogram_gp_counter, @function
reprogram_gp_counter:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	mov	ebx, esi
	sub	rsp, 8
	.cfi_def_cfa_offset 48
	mov	r13d, DWORD PTR PERF_TYPE_RAW[rip]
	test	DWORD PTR ARCH_PERFMON_EVENTSEL_PIN_CONTROL[rip], esi
	jne	.L16
.L2:
	mov	DWORD PTR 0[rbp], ebx
	mov	rdi, rbp
	call	stop_counter@PLT
	test	DWORD PTR ARCH_PERFMON_EVENTSEL_ENABLE[rip], ebx
	jne	.L17
.L1:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L17:
	.cfi_restore_state
	mov	rdi, rbp
	call	pmc_enabled@PLT
	test	eax, eax
	je	.L1
	mov	eax, DWORD PTR ARCH_PERFMON_EVENTSEL_EDGE[rip]
	or	eax, DWORD PTR ARCH_PERFMON_EVENTSEL_INV[rip]
	or	eax, DWORD PTR ARCH_PERFMON_EVENTSEL_CMASK[rip]
	test	eax, ebx
	je	.L18
.L6:
	cmp	DWORD PTR PERF_TYPE_RAW[rip], r13d
	jne	.L7
	mov	r12d, DWORD PTR X86_RAW_EVENT_MASK[rip]
	and	r12d, ebx
.L7:
	xor	r8d, r8d
	test	DWORD PTR ARCH_PERFMON_EVENTSEL_OS[rip], ebx
	mov	edx, r12d
	mov	esi, r13d
	sete	r8b
	xor	ecx, ecx
	test	DWORD PTR ARCH_PERFMON_EVENTSEL_USR[rip], ebx
	mov	rdi, rbp
	sete	cl
	and	ebx, DWORD PTR ARCH_PERFMON_EVENTSEL_INT[rip]
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	r9d, ebx
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	jmp	reprogram_counter@PLT
	.p2align 4,,10
	.p2align 3
.L16:
	.cfi_restore_state
	lea	rdi, .LC0[rip]
	call	printk_once@PLT
	jmp	.L2
	.p2align 4,,10
	.p2align 3
.L18:
	mov	edx, DWORD PTR ARCH_PERFMON_EVENTSEL_UMASK[rip]
	mov	esi, DWORD PTR ARCH_PERFMON_EVENTSEL_EVENT[rip]
	mov	rdi, QWORD PTR 8[rbp]
	and	edx, ebx
	and	esi, ebx
	sar	edx, 8
	call	find_arch_event@PLT
	cmp	DWORD PTR PERF_COUNT_HW_MAX[rip], eax
	mov	r12d, eax
	je	.L6
	mov	r13d, DWORD PTR PERF_TYPE_HARDWARE[rip]
	jmp	.L6
	.cfi_endproc
.LFE0:
	.size	reprogram_gp_counter, .-reprogram_gp_counter
	.comm	X86_RAW_EVENT_MASK,4,4
	.comm	PERF_TYPE_RAW,4,4
	.comm	PERF_TYPE_HARDWARE,4,4
	.comm	PERF_COUNT_HW_MAX,4,4
	.comm	ARCH_PERFMON_EVENTSEL_USR,4,4
	.comm	ARCH_PERFMON_EVENTSEL_UMASK,4,4
	.comm	ARCH_PERFMON_EVENTSEL_PIN_CONTROL,4,4
	.comm	ARCH_PERFMON_EVENTSEL_OS,4,4
	.comm	ARCH_PERFMON_EVENTSEL_INV,4,4
	.comm	ARCH_PERFMON_EVENTSEL_INT,4,4
	.comm	ARCH_PERFMON_EVENTSEL_EVENT,4,4
	.comm	ARCH_PERFMON_EVENTSEL_ENABLE,4,4
	.comm	ARCH_PERFMON_EVENTSEL_EDGE,4,4
	.comm	ARCH_PERFMON_EVENTSEL_CMASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_pmu.c_reprogram_gp_counter.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"kvm pmu: pin control bit is ignored\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	reprogram_gp_counter, %function
reprogram_gp_counter:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	ldr	r3, .L19
	ldr	r6, .L19+4
	ldr	r3, [r3]
	mov	r4, r1
	tst	r1, r3
	mov	r5, r0
	ldr	r8, [r6]
	sub	sp, sp, #8
	bne	.L16
.L2:
	mov	r0, r5
	str	r4, [r5]
	bl	stop_counter
	ldr	r3, .L19+8
	ldr	r3, [r3]
	tst	r4, r3
	bne	.L17
.L1:
	add	sp, sp, #8
	@ sp needed
	pop	{r4, r5, r6, r7, r8, pc}
.L17:
	mov	r0, r5
	bl	pmc_enabled
	cmp	r0, #0
	beq	.L1
	ldr	r3, .L19+12
	ldr	r1, .L19+16
	ldr	r2, .L19+20
	ldr	r3, [r3]
	ldr	r1, [r1]
	ldr	r2, [r2]
	orr	r3, r3, r1
	orr	r3, r3, r2
	tst	r3, r4
	beq	.L18
.L6:
	ldr	r3, [r6]
	ldr	r2, .L19+24
	cmp	r3, r8
	ldreq	r3, .L19+28
	ldr	r2, [r2]
	ldreq	r7, [r3]
	ldr	r3, .L19+32
	andeq	r7, r7, r4
	ldr	r3, [r3]
	ldr	r1, .L19+36
	tst	r4, r3
	moveq	r3, #1
	movne	r3, #0
	tst	r4, r2
	moveq	ip, #1
	movne	ip, #0
	ldr	r0, [r1]
	mov	r2, r7
	and	r4, r4, r0
	mov	r1, r8
	mov	r0, r5
	str	ip, [sp]
	str	r4, [sp, #4]
	bl	reprogram_counter
	add	sp, sp, #8
	@ sp needed
	pop	{r4, r5, r6, r7, r8, pc}
.L16:
	ldr	r0, .L19+40
	bl	printk_once
	b	.L2
.L18:
	ldr	r2, .L19+44
	ldr	r3, .L19+48
	ldr	r2, [r2]
	ldr	r1, [r3]
	and	r2, r2, r4
	ldr	r0, [r5, #4]
	asr	r2, r2, #8
	and	r1, r1, r4
	bl	find_arch_event
	ldr	r3, .L19+52
	mov	r7, r0
	ldr	r3, [r3]
	cmp	r3, r0
	ldrne	r3, .L19+56
	ldrne	r8, [r3]
	b	.L6
.L20:
	.align	2
.L19:
	.word	ARCH_PERFMON_EVENTSEL_PIN_CONTROL
	.word	PERF_TYPE_RAW
	.word	ARCH_PERFMON_EVENTSEL_ENABLE
	.word	ARCH_PERFMON_EVENTSEL_EDGE
	.word	ARCH_PERFMON_EVENTSEL_INV
	.word	ARCH_PERFMON_EVENTSEL_CMASK
	.word	ARCH_PERFMON_EVENTSEL_OS
	.word	X86_RAW_EVENT_MASK
	.word	ARCH_PERFMON_EVENTSEL_USR
	.word	ARCH_PERFMON_EVENTSEL_INT
	.word	.LC0
	.word	ARCH_PERFMON_EVENTSEL_UMASK
	.word	ARCH_PERFMON_EVENTSEL_EVENT
	.word	PERF_COUNT_HW_MAX
	.word	PERF_TYPE_HARDWARE
	.size	reprogram_gp_counter, .-reprogram_gp_counter
	.comm	X86_RAW_EVENT_MASK,4,4
	.comm	PERF_TYPE_RAW,4,4
	.comm	PERF_TYPE_HARDWARE,4,4
	.comm	PERF_COUNT_HW_MAX,4,4
	.comm	ARCH_PERFMON_EVENTSEL_USR,4,4
	.comm	ARCH_PERFMON_EVENTSEL_UMASK,4,4
	.comm	ARCH_PERFMON_EVENTSEL_PIN_CONTROL,4,4
	.comm	ARCH_PERFMON_EVENTSEL_OS,4,4
	.comm	ARCH_PERFMON_EVENTSEL_INV,4,4
	.comm	ARCH_PERFMON_EVENTSEL_INT,4,4
	.comm	ARCH_PERFMON_EVENTSEL_EVENT,4,4
	.comm	ARCH_PERFMON_EVENTSEL_ENABLE,4,4
	.comm	ARCH_PERFMON_EVENTSEL_EDGE,4,4
	.comm	ARCH_PERFMON_EVENTSEL_CMASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
