	.file	"extr_soc15.c_soc15_common_set_clockgating_state.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	soc15_common_set_clockgating_state, @function
soc15_common_set_clockgating_state:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	mov	ebx, esi
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	call	amdgpu_sriov_vf@PLT
	test	rax, rax
	jne	.L2
	mov	eax, DWORD PTR 0[rbp]
	cmp	eax, 132
	jg	.L3
	cmp	eax, 130
	jg	.L4
	add	eax, -128
	cmp	eax, 2
	ja	.L2
	mov	rax, QWORD PTR 8[rbp]
	xor	esi, esi
	cmp	DWORD PTR AMD_CG_STATE_GATE[rip], ebx
	mov	rdi, rbp
	sete	sil
	call	[QWORD PTR 8[rax]]
	mov	rax, QWORD PTR 8[rbp]
	xor	esi, esi
	cmp	DWORD PTR AMD_CG_STATE_GATE[rip], ebx
	sete	sil
	mov	rdi, rbp
	call	[QWORD PTR [rax]]
	xor	esi, esi
	cmp	DWORD PTR AMD_CG_STATE_GATE[rip], ebx
	mov	rdi, rbp
	sete	sil
	call	soc15_update_hdp_light_sleep@PLT
	xor	esi, esi
	cmp	DWORD PTR AMD_CG_STATE_GATE[rip], ebx
	mov	rdi, rbp
	sete	sil
	call	soc15_update_drm_clock_gating@PLT
	xor	esi, esi
	cmp	DWORD PTR AMD_CG_STATE_GATE[rip], ebx
	mov	rdi, rbp
	sete	sil
	call	soc15_update_drm_light_sleep@PLT
	xor	esi, esi
	cmp	DWORD PTR AMD_CG_STATE_GATE[rip], ebx
	mov	rdi, rbp
	sete	sil
	call	soc15_update_rom_medium_grain_clock_gating@PLT
	mov	rax, QWORD PTR 16[rbp]
	xor	esi, esi
	mov	rdi, rbp
	cmp	DWORD PTR AMD_CG_STATE_GATE[rip], ebx
	sete	sil
	call	[QWORD PTR [rax]]
.L2:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	xor	eax, eax
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L3:
	.cfi_restore_state
	cmp	eax, 133
	jne	.L2
	xor	esi, esi
	cmp	DWORD PTR AMD_CG_STATE_GATE[rip], ebx
	mov	rdi, rbp
	sete	sil
	call	soc15_update_hdp_light_sleep@PLT
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	xor	eax, eax
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L4:
	.cfi_restore_state
	mov	rax, QWORD PTR 8[rbp]
	xor	esi, esi
	cmp	DWORD PTR AMD_CG_STATE_GATE[rip], ebx
	mov	rdi, rbp
	sete	sil
	call	[QWORD PTR 8[rax]]
	mov	rax, QWORD PTR 8[rbp]
	xor	esi, esi
	cmp	DWORD PTR AMD_CG_STATE_GATE[rip], ebx
	sete	sil
	mov	rdi, rbp
	call	[QWORD PTR [rax]]
	xor	esi, esi
	cmp	DWORD PTR AMD_CG_STATE_GATE[rip], ebx
	mov	rdi, rbp
	sete	sil
	call	soc15_update_hdp_light_sleep@PLT
	xor	esi, esi
	cmp	DWORD PTR AMD_CG_STATE_GATE[rip], ebx
	mov	rdi, rbp
	sete	sil
	call	soc15_update_drm_clock_gating@PLT
	xor	esi, esi
	cmp	DWORD PTR AMD_CG_STATE_GATE[rip], ebx
	mov	rdi, rbp
	sete	sil
	call	soc15_update_drm_light_sleep@PLT
	xor	esi, esi
	cmp	DWORD PTR AMD_CG_STATE_GATE[rip], ebx
	mov	rdi, rbp
	sete	sil
	call	soc15_update_rom_medium_grain_clock_gating@PLT
	add	rsp, 8
	.cfi_def_cfa_offset 24
	xor	eax, eax
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE0:
	.size	soc15_common_set_clockgating_state, .-soc15_common_set_clockgating_state
	.comm	AMD_CG_STATE_GATE,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_soc15.c_soc15_common_set_clockgating_state.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	soc15_common_set_clockgating_state, %function
soc15_common_set_clockgating_state:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, lr}
	mov	r5, r1
	mov	r4, r0
	bl	amdgpu_sriov_vf
	cmp	r0, #0
	bne	.L2
	ldr	r3, [r4]
	cmp	r3, #132
	bgt	.L3
	cmp	r3, #130
	bgt	.L4
	sub	r3, r3, #128
	cmp	r3, #2
	bhi	.L2
	ldr	r6, .L10
	ldr	r3, [r4, #4]
	ldr	r1, [r6]
	ldr	r3, [r3, #4]
	sub	r1, r1, r5
	clz	r1, r1
	mov	r0, r4
	lsr	r1, r1, #5
	blx	r3
	ldr	r1, [r6]
	ldr	r3, [r4, #4]
	sub	r1, r1, r5
	clz	r1, r1
	ldr	r3, [r3]
	lsr	r1, r1, #5
	mov	r0, r4
	blx	r3
	ldr	r1, [r6]
	mov	r0, r4
	sub	r1, r1, r5
	clz	r1, r1
	lsr	r1, r1, #5
	bl	soc15_update_hdp_light_sleep
	ldr	r1, [r6]
	mov	r0, r4
	sub	r1, r1, r5
	clz	r1, r1
	lsr	r1, r1, #5
	bl	soc15_update_drm_clock_gating
	ldr	r1, [r6]
	mov	r0, r4
	sub	r1, r1, r5
	clz	r1, r1
	lsr	r1, r1, #5
	bl	soc15_update_drm_light_sleep
	ldr	r1, [r6]
	mov	r0, r4
	sub	r1, r1, r5
	clz	r1, r1
	lsr	r1, r1, #5
	bl	soc15_update_rom_medium_grain_clock_gating
	ldr	r1, [r6]
	ldr	r3, [r4, #8]
	sub	r1, r1, r5
	clz	r1, r1
	mov	r0, r4
	ldr	r3, [r3]
	lsr	r1, r1, #5
	blx	r3
.L2:
	mov	r0, #0
	pop	{r4, r5, r6, pc}
.L3:
	cmp	r3, #133
	bne	.L2
	ldr	r3, .L10
	mov	r0, r4
	ldr	r1, [r3]
	sub	r1, r1, r5
	clz	r1, r1
	lsr	r1, r1, #5
	bl	soc15_update_hdp_light_sleep
	mov	r0, #0
	pop	{r4, r5, r6, pc}
.L4:
	ldr	r6, .L10
	ldr	r3, [r4, #4]
	ldr	r1, [r6]
	mov	r0, r4
	sub	r1, r1, r5
	clz	r1, r1
	ldr	r3, [r3, #4]
	lsr	r1, r1, #5
	blx	r3
	ldr	r1, [r6]
	ldr	r3, [r4, #4]
	sub	r1, r1, r5
	clz	r1, r1
	ldr	r3, [r3]
	mov	r0, r4
	lsr	r1, r1, #5
	blx	r3
	ldr	r1, [r6]
	mov	r0, r4
	sub	r1, r1, r5
	clz	r1, r1
	lsr	r1, r1, #5
	bl	soc15_update_hdp_light_sleep
	ldr	r1, [r6]
	mov	r0, r4
	sub	r1, r1, r5
	clz	r1, r1
	lsr	r1, r1, #5
	bl	soc15_update_drm_clock_gating
	ldr	r1, [r6]
	mov	r0, r4
	sub	r1, r1, r5
	clz	r1, r1
	lsr	r1, r1, #5
	bl	soc15_update_drm_light_sleep
	ldr	r1, [r6]
	mov	r0, r4
	sub	r1, r1, r5
	clz	r1, r1
	lsr	r1, r1, #5
	bl	soc15_update_rom_medium_grain_clock_gating
	mov	r0, #0
	pop	{r4, r5, r6, pc}
.L11:
	.align	2
.L10:
	.word	AMD_CG_STATE_GATE
	.size	soc15_common_set_clockgating_state, .-soc15_common_set_clockgating_state
	.comm	AMD_CG_STATE_GATE,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
