	.file	"extr_pci-layerscape.c_ls_pcie_link_up.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	ls_pcie_link_up, @function
ls_pcie_link_up:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	call	to_ls_pcie@PLT
	mov	rbx, rax
	mov	rax, QWORD PTR [rax]
	mov	rdi, QWORD PTR 8[rbx]
	add	rdi, QWORD PTR 8[rax]
	call	ioread32@PLT
	mov	rdx, QWORD PTR [rbx]
	pop	rbx
	.cfi_def_cfa_offset 8
	mov	ecx, DWORD PTR [rdx]
	sar	eax, cl
	and	eax, DWORD PTR LTSSM_STATE_MASK[rip]
	cmp	DWORD PTR LTSSM_PCIE_L0[rip], eax
	setle	al
	movzx	eax, al
	ret
	.cfi_endproc
.LFE0:
	.size	ls_pcie_link_up, .-ls_pcie_link_up
	.comm	LTSSM_STATE_MASK,4,4
	.comm	LTSSM_PCIE_L0,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_pci-layerscape.c_ls_pcie_link_up.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	ls_pcie_link_up, %function
ls_pcie_link_up:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, lr}
	bl	to_ls_pcie
	mov	r4, r0
	ldm	r0, {r2, r3}
	ldr	r0, [r2, #4]
	add	r0, r0, r3
	bl	ioread32
	ldr	r1, [r4]
	ldr	r3, .L4
	ldr	r2, .L4+4
	ldr	r1, [r1]
	ldr	r3, [r3]
	ldr	r2, [r2]
	and	r0, r3, r0, asr r1
	cmp	r2, r0
	movgt	r0, #0
	movle	r0, #1
	pop	{r4, pc}
.L5:
	.align	2
.L4:
	.word	LTSSM_STATE_MASK
	.word	LTSSM_PCIE_L0
	.size	ls_pcie_link_up, .-ls_pcie_link_up
	.comm	LTSSM_STATE_MASK,4,4
	.comm	LTSSM_PCIE_L0,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
