	.file	"extr_pinmux.c_crisv32_pinmux_alloc_fixed.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	crisv32_pinmux_alloc_fixed
	.type	crisv32_pinmux_alloc_fixed, @function
crisv32_pinmux_alloc_fixed:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xor	esi, esi
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	ebx, edi
	lea	rdi, pinmux_lock[rip]
	add	ebx, -128
	sub	rsp, 504
	.cfi_def_cfa_offset 560
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 488[rsp], rax
	xor	eax, eax
	lea	rbp, 480[rsp]
	call	spin_lock_irqsave@PLT
	mov	rsi, QWORD PTR pins[rip]
	mov	edx, 8
	mov	rdi, rbp
	call	memcpy@PLT
	xor	eax, eax
	call	crisv32_pinmux_init@PLT
	mov	ecx, DWORD PTR rw_hwprot[rip]
	mov	edx, DWORD PTR regi_pinmux[rip]
	lea	rdi, 32[rsp]
	mov	esi, DWORD PTR pinmux[rip]
	call	REG_RD@PLT
	mov	rax, QWORD PTR 32[rsp]
	mov	r15, QWORD PTR 48[rsp]
	lea	rdi, 256[rsp]
	mov	ecx, DWORD PTR rw_clk_ctrl[rip]
	mov	edx, DWORD PTR regi_clkgen[rip]
	mov	esi, DWORD PTR clkgen[rip]
	mov	QWORD PTR [rsp], rax
	mov	rax, QWORD PTR 64[rsp]
	mov	r14, QWORD PTR 56[rsp]
	mov	r13, QWORD PTR 184[rsp]
	mov	QWORD PTR 8[rsp], rax
	mov	rax, QWORD PTR 160[rsp]
	mov	QWORD PTR 16[rsp], rax
	mov	rax, QWORD PTR 224[rsp]
	mov	QWORD PTR 24[rsp], rax
	call	REG_RD@PLT
	mov	r12, QWORD PTR 424[rsp]
	cmp	ebx, 19
	ja	.L2
	lea	rdx, .L4[rip]
	movsx	rax, DWORD PTR [rdx+rbx*4]
	add	rax, rdx
	notrack jmp	rax
	.section	.rodata
	.align 4
	.align 4
.L4:
	.long	.L23-.L4
	.long	.L22-.L4
	.long	.L21-.L4
	.long	.L20-.L4
	.long	.L19-.L4
	.long	.L18-.L4
	.long	.L17-.L4
	.long	.L16-.L4
	.long	.L15-.L4
	.long	.L14-.L4
	.long	.L13-.L4
	.long	.L12-.L4
	.long	.L11-.L4
	.long	.L10-.L4
	.long	.L9-.L4
	.long	.L8-.L4
	.long	.L7-.L4
	.long	.L6-.L4
	.long	.L5-.L4
	.long	.L3-.L4
	.text
	.p2align 4,,10
	.p2align 3
.L5:
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_B[rip]
	mov	edx, 7
	xor	esi, esi
	call	crisv32_pinmux_alloc@PLT
	mov	ebx, eax
	mov	rax, QWORD PTR regk_pinmux_yes[rip]
	mov	QWORD PTR 216[rsp], rax
	.p2align 4,,10
	.p2align 3
.L24:
	test	ebx, ebx
	jne	.L26
.L25:
	mov	rax, QWORD PTR 8[rsp]
	mov	QWORD PTR 48[rsp], r15
	sub	rsp, 8
	.cfi_def_cfa_offset 568
	xor	ebx, ebx
	mov	QWORD PTR 64[rsp], r14
	mov	QWORD PTR 72[rsp], rax
	mov	rax, QWORD PTR 24[rsp]
	mov	QWORD PTR 192[rsp], r13
	mov	QWORD PTR 168[rsp], rax
	mov	rax, QWORD PTR 32[rsp]
	mov	QWORD PTR 232[rsp], rax
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 576
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 584
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 592
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 600
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 608
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 616
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 624
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 632
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 640
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 648
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 656
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 664
	mov	edx, DWORD PTR rw_hwprot[rip]
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 672
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 680
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 688
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 696
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 704
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 712
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 720
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 728
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 736
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 744
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 752
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 760
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 768
	push	QWORD PTR 248[rsp]
	.cfi_def_cfa_offset 776
	push	QWORD PTR 216[rsp]
	.cfi_def_cfa_offset 784
	mov	esi, DWORD PTR regi_pinmux[rip]
	mov	edi, DWORD PTR pinmux[rip]
	call	REG_WR@PLT
	mov	QWORD PTR 648[rsp], r12
	add	rsp, 216
	.cfi_def_cfa_offset 568
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 576
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 584
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 592
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 600
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 608
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 616
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 624
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 632
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 640
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 648
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 656
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 664
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 672
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 680
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 688
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 696
	mov	edx, DWORD PTR rw_clk_ctrl[rip]
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 704
	mov	esi, DWORD PTR regi_clkgen[rip]
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 712
	mov	edi, DWORD PTR clkgen[rip]
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 720
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 728
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 736
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 744
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 752
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 760
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 768
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 776
	push	QWORD PTR 472[rsp]
	.cfi_def_cfa_offset 784
	call	REG_WR@PLT
	add	rsp, 224
	.cfi_def_cfa_offset 560
.L27:
	xor	esi, esi
	lea	rdi, pinmux_lock[rip]
	call	spin_unlock_irqrestore@PLT
	mov	rax, QWORD PTR 488[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L31
	add	rsp, 504
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	eax, ebx
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L6:
	.cfi_restore_state
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_A[rip]
	mov	edx, 1
	xor	esi, esi
	call	crisv32_pinmux_alloc@PLT
	mov	ebx, eax
	mov	rax, QWORD PTR regk_pinmux_yes[rip]
	mov	QWORD PTR 72[rsp], rax
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L7:
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_A[rip]
	mov	edx, 3
	mov	esi, 2
	call	crisv32_pinmux_alloc@PLT
	mov	ebx, eax
	mov	rax, QWORD PTR regk_pinmux_yes[rip]
	mov	QWORD PTR 40[rsp], rax
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L8:
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_A[rip]
	mov	edx, 3
	mov	esi, 2
	call	crisv32_pinmux_alloc@PLT
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_A[rip]
	mov	edx, 7
	mov	esi, 7
	mov	ebx, eax
	call	crisv32_pinmux_alloc@PLT
	or	ebx, eax
	mov	rax, QWORD PTR regk_pinmux_yes[rip]
	mov	QWORD PTR 8[rsp], rax
	mov	QWORD PTR 40[rsp], rax
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L9:
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_A[rip]
	mov	edx, 4
	mov	esi, 2
	call	crisv32_pinmux_alloc@PLT
	mov	r14, QWORD PTR regk_pinmux_yes[rip]
	mov	ebx, eax
	mov	QWORD PTR 40[rsp], r14
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L10:
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_A[rip]
	mov	edx, 3
	mov	esi, 2
	call	crisv32_pinmux_alloc@PLT
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_A[rip]
	mov	edx, 5
	mov	esi, 5
	mov	ebx, eax
	call	crisv32_pinmux_alloc@PLT
	mov	r15, QWORD PTR regk_pinmux_yes[rip]
	or	ebx, eax
	mov	QWORD PTR 40[rsp], r15
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L11:
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_A[rip]
	mov	edx, 3
	mov	esi, 2
	call	crisv32_pinmux_alloc@PLT
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_A[rip]
	mov	edx, 6
	mov	esi, 6
	mov	ebx, eax
	call	crisv32_pinmux_alloc@PLT
	or	ebx, eax
	mov	rax, QWORD PTR regk_pinmux_yes[rip]
	mov	QWORD PTR [rsp], rax
	mov	QWORD PTR 40[rsp], rax
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L12:
	mov	rax, QWORD PTR regk_pinmux_yes[rip]
	mov	QWORD PTR 104[rsp], rax
	jmp	.L25
	.p2align 4,,10
	.p2align 3
.L13:
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_A[rip]
	mov	edx, 30
	mov	esi, 30
	call	crisv32_pinmux_alloc@PLT
	mov	ebx, eax
	mov	rax, QWORD PTR regk_pinmux_yes[rip]
	mov	QWORD PTR 96[rsp], rax
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L14:
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_A[rip]
	mov	edx, 31
	mov	esi, 31
	call	crisv32_pinmux_alloc@PLT
	mov	ebx, eax
	mov	rax, QWORD PTR regk_pinmux_yes[rip]
	mov	QWORD PTR 88[rsp], rax
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L15:
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_B[rip]
	mov	edx, 26
	mov	esi, 26
	call	crisv32_pinmux_alloc@PLT
	mov	ebx, eax
	mov	rax, QWORD PTR regk_pinmux_yes[rip]
	mov	QWORD PTR 80[rsp], rax
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L16:
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_A[rip]
	mov	edx, 25
	mov	esi, 24
	mov	rax, QWORD PTR regk_clkgen_yes[rip]
	mov	QWORD PTR 344[rsp], rax
	call	crisv32_pinmux_alloc@PLT
	mov	ebx, eax
	mov	rax, QWORD PTR regk_pinmux_yes[rip]
	mov	QWORD PTR 152[rsp], rax
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L17:
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_A[rip]
	mov	edx, 27
	mov	esi, 26
	mov	rax, QWORD PTR regk_clkgen_yes[rip]
	mov	QWORD PTR 344[rsp], rax
	call	crisv32_pinmux_alloc@PLT
	mov	ebx, eax
	mov	rax, QWORD PTR regk_pinmux_yes[rip]
	mov	QWORD PTR 144[rsp], rax
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L18:
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_A[rip]
	mov	edx, 29
	mov	esi, 28
	mov	rax, QWORD PTR regk_clkgen_yes[rip]
	mov	QWORD PTR 344[rsp], rax
	call	crisv32_pinmux_alloc@PLT
	mov	ebx, eax
	mov	rax, QWORD PTR regk_pinmux_yes[rip]
	mov	QWORD PTR 136[rsp], rax
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L19:
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_A[rip]
	mov	edx, 31
	mov	esi, 30
	mov	rax, QWORD PTR regk_clkgen_yes[rip]
	mov	QWORD PTR 344[rsp], rax
	call	crisv32_pinmux_alloc@PLT
	mov	ebx, eax
	mov	rax, QWORD PTR regk_pinmux_yes[rip]
	mov	QWORD PTR 128[rsp], rax
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L20:
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_A[rip]
	mov	edx, 23
	mov	esi, 19
	mov	rax, QWORD PTR regk_clkgen_yes[rip]
	mov	QWORD PTR 344[rsp], rax
	call	crisv32_pinmux_alloc@PLT
	mov	ebx, eax
	mov	rax, QWORD PTR regk_pinmux_yes[rip]
	mov	QWORD PTR 112[rsp], rax
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L21:
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_B[rip]
	mov	edx, 31
	mov	esi, 27
	mov	r12, QWORD PTR regk_clkgen_yes[rip]
	mov	QWORD PTR 432[rsp], r12
	call	crisv32_pinmux_alloc@PLT
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_C[rip]
	xor	esi, esi
	mov	edx, 15
	mov	ebx, eax
	call	crisv32_pinmux_alloc@PLT
	mov	r13, QWORD PTR regk_pinmux_yes[rip]
	or	ebx, eax
	mov	QWORD PTR 192[rsp], r13
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L22:
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_B[rip]
	mov	edx, 29
	mov	esi, 27
	mov	r12, QWORD PTR regk_clkgen_yes[rip]
	mov	QWORD PTR 432[rsp], r12
	call	crisv32_pinmux_alloc@PLT
	mov	r13, QWORD PTR regk_pinmux_yes[rip]
	mov	ebx, eax
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L23:
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_A[rip]
	mov	edx, 18
	mov	esi, 8
	mov	rax, QWORD PTR regk_clkgen_yes[rip]
	mov	QWORD PTR 400[rsp], rax
	call	crisv32_pinmux_alloc@PLT
	mov	ebx, eax
	mov	rax, QWORD PTR regk_pinmux_yes[rip]
	mov	QWORD PTR 16[rsp], rax
	mov	QWORD PTR 168[rsp], rax
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L3:
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_B[rip]
	mov	edx, 23
	mov	esi, 8
	mov	rax, QWORD PTR regk_clkgen_yes[rip]
	mov	QWORD PTR 456[rsp], rax
	mov	QWORD PTR 464[rsp], rax
	call	crisv32_pinmux_alloc@PLT
	mov	ecx, DWORD PTR pinmux_fixed[rip]
	mov	edi, DWORD PTR PORT_B[rip]
	mov	edx, 25
	mov	esi, 24
	mov	ebx, eax
	call	crisv32_pinmux_alloc@PLT
	or	ebx, eax
	mov	rax, QWORD PTR regk_pinmux_yes[rip]
	mov	QWORD PTR 24[rsp], rax
	mov	QWORD PTR 232[rsp], rax
	jmp	.L24
	.p2align 4,,10
	.p2align 3
.L26:
	mov	rdi, QWORD PTR pins[rip]
	mov	edx, 8
	mov	rsi, rbp
	call	memcpy@PLT
	jmp	.L27
.L2:
	mov	ebx, DWORD PTR EINVAL[rip]
	neg	ebx
	jmp	.L24
.L31:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	crisv32_pinmux_alloc_fixed, .-crisv32_pinmux_alloc_fixed
	.comm	rw_hwprot,4,4
	.comm	rw_clk_ctrl,4,4
	.comm	regk_pinmux_yes,8,8
	.comm	regk_clkgen_yes,8,8
	.comm	regi_pinmux,4,4
	.comm	regi_clkgen,4,4
	.comm	pins,8,8
	.comm	pinmux_lock,4,4
	.comm	pinmux_fixed,4,4
	.comm	pinmux,4,4
	.comm	clkgen,4,4
	.comm	PORT_C,4,4
	.comm	PORT_B,4,4
	.comm	PORT_A,4,4
	.comm	EINVAL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_pinmux.c_crisv32_pinmux_alloc_fixed.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	crisv32_pinmux_alloc_fixed
	.syntax unified
	.arm
	.fpu softvfp
	.type	crisv32_pinmux_alloc_fixed, %function
crisv32_pinmux_alloc_fixed:
	@ args = 0, pretend = 0, frame = 256
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	mov	r10, r0
	ldr	r3, .L32
	ldr	fp, .L32+4
	sub	sp, sp, #364
	mov	r1, #0
	ldr	r0, .L32+8
	ldr	r7, .L32+12
	ldr	r8, .L32+16
	ldr	r9, .L32+20
	ldr	r3, [r3]
	str	r3, [sp, #356]
	mov	r3,#0
	bl	spin_lock_irqsave
	mov	r2, #4
	ldr	r1, [fp]
	add	r0, sp, #352
	bl	memcpy
	bl	crisv32_pinmux_init
	ldr	r3, [r7]
	ldr	r2, [r8]
	ldr	r1, [r9]
	add	r0, sp, #136
	bl	REG_RD
	ldr	ip, [sp, #136]
	ldr	r4, .L32+24
	str	ip, [sp, #112]
	ldr	ip, [sp, #144]
	ldr	r5, .L32+28
	str	ip, [sp, #116]
	ldr	ip, [sp, #148]
	ldr	r6, .L32+32
	str	ip, [sp, #120]
	ldr	ip, [sp, #152]
	ldr	r3, [r4]
	str	ip, [sp, #124]
	ldr	ip, [sp, #200]
	ldr	r2, [r5]
	str	ip, [sp, #128]
	ldr	ip, [sp, #212]
	ldr	r1, [r6]
	str	ip, [sp, #104]
	ldr	ip, [sp, #232]
	add	r0, sp, #244
	str	ip, [sp, #132]
	bl	REG_RD
	ldr	r3, [sp, #328]
	sub	r10, r10, #128
	str	r3, [sp, #108]
	cmp	r10, #19
	ldrls	pc, [pc, r10, asl #2]
	b	.L2
.L4:
	.word	.L23
	.word	.L22
	.word	.L21
	.word	.L20
	.word	.L19
	.word	.L18
	.word	.L17
	.word	.L16
	.word	.L15
	.word	.L14
	.word	.L13
	.word	.L12
	.word	.L11
	.word	.L10
	.word	.L9
	.word	.L8
	.word	.L7
	.word	.L6
	.word	.L5
	.word	.L3
.L3:
	ldr	r3, .L32+36
	ldr	r10, .L32+40
	ldr	ip, [r3]
	ldr	r3, .L32+44
	mov	r2, #23
	mov	r1, #8
	ldr	r3, [r3]
	ldr	r0, [r10]
	str	ip, [sp, #344]
	str	ip, [sp, #348]
	bl	crisv32_pinmux_alloc
	mov	ip, r0
	ldr	r3, .L32+44
	ldr	r0, [r10]
	ldr	r3, [r3]
	mov	r2, #25
	mov	r1, #24
	mov	r10, ip
	bl	crisv32_pinmux_alloc
	ldr	r3, .L32+48
	orr	r10, r10, r0
	ldr	r3, [r3]
	str	r3, [sp, #132]
	str	r3, [sp, #236]
.L24:
	cmp	r10, #0
	bne	.L26
.L25:
	ldr	r3, [sp, #112]
	ldr	r9, [r9]
	str	r3, [sp, #136]
	ldr	r3, [sp, #116]
	ldr	r8, [r8]
	str	r3, [sp, #144]
	ldr	r3, [sp, #120]
	ldr	r7, [r7]
	str	r3, [sp, #148]
	ldr	r3, [sp, #124]
	mov	r2, #104
	str	r3, [sp, #152]
	ldr	r3, [sp, #128]
	add	r1, sp, #140
	str	r3, [sp, #200]
	ldr	r3, [sp, #104]
	mov	r0, sp
	str	r3, [sp, #212]
	ldr	r3, [sp, #132]
	mov	r10, #0
	str	r3, [sp, #232]
	bl	memcpy
	mov	r2, r7
	mov	r1, r8
	ldr	r3, [sp, #136]
	mov	r0, r9
	bl	REG_WR
	ldr	r3, [sp, #108]
	ldr	r6, [r6]
	ldr	r5, [r5]
	ldr	r4, [r4]
	mov	r2, #104
	add	r1, sp, #248
	mov	r0, sp
	str	r3, [sp, #328]
	bl	memcpy
	mov	r2, r4
	mov	r1, r5
	mov	r0, r6
	ldr	r3, [sp, #244]
	bl	REG_WR
.L27:
	mov	r1, #0
	ldr	r0, .L32+8
	bl	spin_unlock_irqrestore
	ldr	r3, .L32
	ldr	r2, [r3]
	ldr	r3, [sp, #356]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L31
	mov	r0, r10
	add	sp, sp, #364
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L5:
	ldr	r2, .L32+40
	ldr	r3, .L32+44
	ldr	r0, [r2]
	ldr	r3, [r3]
	mov	r2, #7
	mov	r1, #0
	bl	crisv32_pinmux_alloc
	ldr	r3, .L32+48
	mov	r10, r0
	ldr	r3, [r3]
	str	r3, [sp, #228]
	b	.L24
.L6:
	ldr	r2, .L32+52
	ldr	r3, .L32+44
	ldr	r0, [r2]
	ldr	r3, [r3]
	mov	r2, #1
	mov	r1, #0
	bl	crisv32_pinmux_alloc
	ldr	r3, .L32+48
	mov	r10, r0
	ldr	r3, [r3]
	str	r3, [sp, #156]
	b	.L24
.L7:
	ldr	r2, .L32+52
	ldr	r3, .L32+44
	ldr	r0, [r2]
	ldr	r3, [r3]
	mov	r2, #3
	mov	r1, #2
	bl	crisv32_pinmux_alloc
	ldr	r3, .L32+48
	mov	r10, r0
	ldr	r3, [r3]
	str	r3, [sp, #140]
	b	.L24
.L8:
	ldr	r10, .L32+52
	ldr	r3, .L32+44
	mov	r2, #3
	mov	r1, #2
	ldr	r3, [r3]
	ldr	r0, [r10]
	bl	crisv32_pinmux_alloc
	mov	r2, #7
	mov	ip, r0
	ldr	r3, .L32+44
	ldr	r0, [r10]
	ldr	r3, [r3]
	mov	r1, r2
	mov	r10, ip
	bl	crisv32_pinmux_alloc
	ldr	r3, .L32+48
	orr	r10, r10, r0
	ldr	r3, [r3]
	str	r3, [sp, #124]
	str	r3, [sp, #140]
	b	.L24
.L9:
	ldr	r2, .L32+52
	ldr	r3, .L32+44
	ldr	r0, [r2]
	ldr	r3, [r3]
	mov	r2, #4
	mov	r1, #2
	bl	crisv32_pinmux_alloc
	ldr	r3, .L32+48
	mov	r10, r0
	ldr	r3, [r3]
	str	r3, [sp, #120]
	str	r3, [sp, #140]
	b	.L24
.L10:
	ldr	r10, .L32+52
	ldr	r3, .L32+44
	mov	r2, #3
	mov	r1, #2
	ldr	r3, [r3]
	ldr	r0, [r10]
	bl	crisv32_pinmux_alloc
	mov	r2, #5
	mov	ip, r0
	ldr	r3, .L32+44
	ldr	r0, [r10]
	ldr	r3, [r3]
	mov	r1, r2
	mov	r10, ip
	bl	crisv32_pinmux_alloc
	ldr	r3, .L32+48
	orr	r10, r10, r0
	ldr	r3, [r3]
	str	r3, [sp, #116]
	str	r3, [sp, #140]
	b	.L24
.L11:
	ldr	r10, .L32+52
	ldr	r3, .L32+44
	mov	r2, #3
	mov	r1, #2
	ldr	r3, [r3]
	ldr	r0, [r10]
	bl	crisv32_pinmux_alloc
	mov	r2, #6
	mov	ip, r0
	ldr	r3, .L32+44
	ldr	r0, [r10]
	ldr	r3, [r3]
	mov	r1, r2
	mov	r10, ip
	bl	crisv32_pinmux_alloc
	ldr	r3, .L32+48
	orr	r10, r10, r0
	ldr	r3, [r3]
	str	r3, [sp, #112]
	str	r3, [sp, #140]
	b	.L24
.L12:
	ldr	r3, .L32+48
	ldr	r3, [r3]
	str	r3, [sp, #172]
	b	.L25
.L13:
	mov	r2, #30
	ldr	r3, .L32+44
	ldr	r0, .L32+52
	ldr	r3, [r3]
	mov	r1, r2
	ldr	r0, [r0]
	bl	crisv32_pinmux_alloc
	ldr	r3, .L32+48
	mov	r10, r0
	ldr	r3, [r3]
	str	r3, [sp, #168]
	b	.L24
.L14:
	mov	r2, #31
	ldr	r3, .L32+44
	ldr	r0, .L32+52
	ldr	r3, [r3]
	mov	r1, r2
	ldr	r0, [r0]
	bl	crisv32_pinmux_alloc
	ldr	r3, .L32+48
	mov	r10, r0
	ldr	r3, [r3]
	str	r3, [sp, #164]
	b	.L24
.L15:
	mov	r2, #26
	ldr	r3, .L32+44
	ldr	r0, .L32+40
	ldr	r3, [r3]
	mov	r1, r2
	ldr	r0, [r0]
	bl	crisv32_pinmux_alloc
	ldr	r3, .L32+48
	mov	r10, r0
	ldr	r3, [r3]
	str	r3, [sp, #160]
	b	.L24
.L16:
	ldr	r1, .L32+36
	ldr	r2, .L32+52
	ldr	r3, .L32+44
	ldr	ip, [r1]
	ldr	r3, [r3]
	ldr	r0, [r2]
	mov	r1, #24
	mov	r2, #25
	str	ip, [sp, #288]
	bl	crisv32_pinmux_alloc
	ldr	r3, .L32+48
	mov	r10, r0
	ldr	r3, [r3]
	str	r3, [sp, #196]
	b	.L24
.L17:
	ldr	r1, .L32+36
	ldr	r2, .L32+52
	ldr	r3, .L32+44
	ldr	ip, [r1]
	ldr	r3, [r3]
	ldr	r0, [r2]
	mov	r1, #26
	mov	r2, #27
	str	ip, [sp, #288]
	bl	crisv32_pinmux_alloc
	ldr	r3, .L32+48
	mov	r10, r0
	ldr	r3, [r3]
	str	r3, [sp, #192]
	b	.L24
.L18:
	ldr	r1, .L32+36
	ldr	r2, .L32+52
	ldr	r3, .L32+44
	ldr	ip, [r1]
	ldr	r3, [r3]
	ldr	r0, [r2]
	mov	r1, #28
	mov	r2, #29
	str	ip, [sp, #288]
	bl	crisv32_pinmux_alloc
	ldr	r3, .L32+48
	mov	r10, r0
	ldr	r3, [r3]
	str	r3, [sp, #188]
	b	.L24
.L19:
	ldr	r1, .L32+36
	ldr	r2, .L32+52
	ldr	r3, .L32+44
	ldr	ip, [r1]
	ldr	r3, [r3]
	ldr	r0, [r2]
	mov	r1, #30
	mov	r2, #31
	str	ip, [sp, #288]
	bl	crisv32_pinmux_alloc
	ldr	r3, .L32+48
	mov	r10, r0
	ldr	r3, [r3]
	str	r3, [sp, #184]
	b	.L24
.L20:
	ldr	r1, .L32+36
	ldr	r2, .L32+52
	ldr	r3, .L32+44
	ldr	ip, [r1]
	ldr	r3, [r3]
	ldr	r0, [r2]
	mov	r1, #19
	mov	r2, #23
	str	ip, [sp, #288]
	bl	crisv32_pinmux_alloc
	ldr	r3, .L32+48
	mov	r10, r0
	ldr	r3, [r3]
	str	r3, [sp, #176]
	b	.L24
.L21:
	ldr	r3, .L32+36
	ldr	r2, .L32+40
	ldr	r3, [r3]
	mov	r1, #27
	mov	ip, r3
	str	r3, [sp, #108]
	ldr	r3, .L32+44
	ldr	r0, [r2]
	ldr	r3, [r3]
	mov	r2, #31
	str	ip, [sp, #332]
	bl	crisv32_pinmux_alloc
	ldr	r2, .L32+56
	ldr	r3, .L32+44
	mov	r10, r0
	ldr	r3, [r3]
	ldr	r0, [r2]
	mov	r1, #0
	mov	r2, #15
	bl	crisv32_pinmux_alloc
	ldr	r3, .L32+48
	orr	r10, r10, r0
	ldr	r3, [r3]
	str	r3, [sp, #104]
	str	r3, [sp, #216]
	b	.L24
.L22:
	ldr	r1, .L32+36
	ldr	r2, .L32+40
	ldr	r1, [r1]
	ldr	r3, .L32+44
	mov	ip, r1
	ldr	r3, [r3]
	ldr	r0, [r2]
	str	r1, [sp, #108]
	mov	r2, #29
	mov	r1, #27
	str	ip, [sp, #332]
	bl	crisv32_pinmux_alloc
	ldr	r3, .L32+48
	mov	r10, r0
	ldr	r3, [r3]
	str	r3, [sp, #104]
	b	.L24
.L23:
	ldr	r1, .L32+36
	ldr	r2, .L32+52
	ldr	r3, .L32+44
	ldr	ip, [r1]
	ldr	r3, [r3]
	ldr	r0, [r2]
	mov	r1, #8
	mov	r2, #18
	str	ip, [sp, #316]
	bl	crisv32_pinmux_alloc
	ldr	r3, .L32+48
	mov	r10, r0
	ldr	r3, [r3]
	str	r3, [sp, #128]
	str	r3, [sp, #204]
	b	.L24
.L26:
	mov	r2, #4
	ldr	r0, [fp]
	add	r1, sp, #352
	bl	memcpy
	b	.L27
.L31:
	bl	__stack_chk_fail
.L2:
	ldr	r3, .L32+60
	ldr	r10, [r3]
	rsb	r10, r10, #0
	b	.L24
.L33:
	.align	2
.L32:
	.word	.LC0
	.word	pins
	.word	pinmux_lock
	.word	rw_hwprot
	.word	regi_pinmux
	.word	pinmux
	.word	rw_clk_ctrl
	.word	regi_clkgen
	.word	clkgen
	.word	regk_clkgen_yes
	.word	PORT_B
	.word	pinmux_fixed
	.word	regk_pinmux_yes
	.word	PORT_A
	.word	PORT_C
	.word	EINVAL
	.size	crisv32_pinmux_alloc_fixed, .-crisv32_pinmux_alloc_fixed
	.comm	rw_hwprot,4,4
	.comm	rw_clk_ctrl,4,4
	.comm	regk_pinmux_yes,4,4
	.comm	regk_clkgen_yes,4,4
	.comm	regi_pinmux,4,4
	.comm	regi_clkgen,4,4
	.comm	pins,4,4
	.comm	pinmux_lock,4,4
	.comm	pinmux_fixed,4,4
	.comm	pinmux,4,4
	.comm	clkgen,4,4
	.comm	PORT_C,4,4
	.comm	PORT_B,4,4
	.comm	PORT_A,4,4
	.comm	EINVAL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
