	.file	"extr_vgavideo.c_vgaHLine.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	vgaHLine
	.type	vgaHLine, @function
vgaHLine:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	mov	r14d, ecx
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	mov	r13d, edx
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	mov	r12d, edi
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	ebp, esi
	lea	esi, -1[rdi]
	lea	r15d, [r12+r13]
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	edi, esi
	sub	rsp, 40
	.cfi_def_cfa_offset 96
	mov	DWORD PTR 20[rsp], esi
	call	mod8@PLT
	mov	ecx, 7
	mov	edi, r15d
	sub	ecx, eax
	mov	DWORD PTR 8[rsp], ecx
	call	mod8@PLT
	mov	esi, DWORD PTR 20[rsp]
	movsx	r8, ebp
	mov	edx, r13d
	movsx	rbx, eax
	mov	rax, QWORD PTR y80[rip]
	movsx	rcx, DWORD PTR 8[rsp]
	and	esi, -8
	mov	ebp, DWORD PTR [rax+r8*4]
	mov	rax, QWORD PTR xconv[rip]
	movsx	rsi, esi
	sub	edx, ecx
	sub	edx, ebx
	add	ebp, DWORD PTR [rax+rsi*4]
	lea	eax, [rcx+rbx]
	cmp	eax, r13d
	jg	.L10
	test	ecx, ecx
	mov	DWORD PTR 8[rsp], ecx
	jg	.L11
	cmp	edx, 7
	jg	.L12
.L5:
	test	ebx, ebx
	jg	.L13
.L6:
	mov	eax, DWORD PTR TRUE[rip]
	add	rsp, 40
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L13:
	.cfi_restore_state
	mov	rax, QWORD PTR y80[rip]
	mov	edi, DWORD PTR GRA_I[rip]
	sub	r15d, ebx
	mov	esi, 8
	movsx	r15, r15d
	mov	ebp, DWORD PTR [rax+r8*4]
	mov	rax, QWORD PTR xconv[rip]
	add	ebp, DWORD PTR [rax+r15*4]
	call	WRITE_PORT_UCHAR@PLT
	mov	rax, QWORD PTR endmasks[rip]
	mov	esi, DWORD PTR [rax+rbx*4]
.L8:
	mov	edi, DWORD PTR GRA_D[rip]
	call	WRITE_PORT_UCHAR@PLT
	mov	edi, DWORD PTR vidmem[rip]
	add	edi, ebp
	call	READ_REGISTER_UCHAR@PLT
	mov	edi, DWORD PTR vidmem[rip]
	mov	esi, r14d
	add	edi, ebp
	call	WRITE_REGISTER_UCHAR@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L11:
	mov	edi, DWORD PTR GRA_I[rip]
	mov	esi, 8
	mov	DWORD PTR 20[rsp], edx
	add	r12d, 8
	mov	QWORD PTR 24[rsp], r8
	call	WRITE_PORT_UCHAR@PLT
	movsx	rcx, DWORD PTR 8[rsp]
	mov	rax, QWORD PTR startmasks[rip]
	mov	edi, DWORD PTR GRA_D[rip]
	mov	esi, DWORD PTR [rax+rcx*4]
	call	WRITE_PORT_UCHAR@PLT
	mov	edi, DWORD PTR vidmem[rip]
	add	edi, ebp
	call	READ_REGISTER_UCHAR@PLT
	mov	edi, DWORD PTR vidmem[rip]
	mov	esi, r14d
	add	edi, ebp
	call	WRITE_REGISTER_UCHAR@PLT
	mov	edx, DWORD PTR 20[rsp]
	mov	r8, QWORD PTR 24[rsp]
	cmp	edx, 7
	jle	.L5
.L12:
	mov	rax, QWORD PTR y80[rip]
	mov	edi, DWORD PTR GRA_I[rip]
	movsx	r12, r12d
	mov	DWORD PTR 20[rsp], edx
	mov	esi, 8
	mov	QWORD PTR 8[rsp], r8
	mov	ebp, DWORD PTR [rax+r8*4]
	mov	rax, QWORD PTR xconv[rip]
	add	ebp, DWORD PTR [rax+r12*4]
	call	WRITE_PORT_UCHAR@PLT
	mov	edi, DWORD PTR GRA_D[rip]
	mov	esi, 255
	call	WRITE_PORT_UCHAR@PLT
	mov	edx, DWORD PTR 20[rsp]
	mov	edi, DWORD PTR vidmem[rip]
	mov	esi, r14d
	sar	edx, 3
	add	edi, ebp
	call	memset@PLT
	mov	r8, QWORD PTR 8[rsp]
	jmp	.L5
	.p2align 4,,10
	.p2align 3
.L10:
	mov	rax, QWORD PTR startmasks[rip]
	mov	edi, DWORD PTR GRA_I[rip]
	mov	esi, 8
	mov	rdx, QWORD PTR endmasks[rip]
	mov	r12d, DWORD PTR [rax+rcx*4]
	and	r12d, DWORD PTR [rdx+rbx*4]
	call	WRITE_PORT_UCHAR@PLT
	mov	esi, r12d
	jmp	.L8
	.cfi_endproc
.LFE0:
	.size	vgaHLine, .-vgaHLine
	.comm	y80,8,8
	.comm	xconv,8,8
	.comm	vidmem,4,4
	.comm	startmasks,8,8
	.comm	endmasks,8,8
	.comm	TRUE,4,4
	.comm	GRA_I,8,8
	.comm	GRA_D,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_vgavideo.c_vgaHLine.c"
	.text
	.align	2
	.global	vgaHLine
	.syntax unified
	.arm
	.fpu softvfp
	.type	vgaHLine, %function
vgaHLine:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	sub	r9, r0, #1
	mov	r4, r2
	sub	sp, sp, #12
	mov	r6, r0
	mov	r0, r9
	mov	r8, r3
	str	r1, [sp, #4]
	bl	mod8
	add	r10, r6, r4
	mov	r7, r0
	mov	r0, r10
	bl	mod8
	mov	r5, r0
	ldr	r3, .L13
	ldr	fp, .L13+4
	ldr	ip, [r3]
	ldr	r1, [fp]
	ldr	r2, [sp, #4]
	rsb	r7, r7, #7
	bic	r9, r9, #7
	ldr	r9, [ip, r9, lsl #2]
	ldr	r1, [r1, r2, lsl #2]
	add	r0, r7, r0
	cmp	r0, r4
	sub	r4, r4, r7
	sub	r4, r4, r5
	add	r9, r9, r1
	bgt	.L9
	cmp	r7, #0
	bgt	.L10
	cmp	r4, #7
	bgt	.L11
.L5:
	cmp	r5, #0
	bgt	.L12
.L6:
	ldr	r3, .L13+8
	ldr	r0, [r3]
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L12:
	ldr	r1, [r3]
	ldr	r0, [sp, #4]
	ldr	r3, [fp]
	ldr	r2, .L13+12
	sub	r10, r10, r5
	ldr	r3, [r3, r0, lsl #2]
	ldr	r4, [r1, r10, lsl #2]
	ldr	r0, [r2]
	mov	r1, #8
	add	r4, r4, r3
	bl	WRITE_PORT_UCHAR
	ldr	r2, .L13+16
	ldr	r3, .L13+20
	ldr	r2, [r2]
	ldr	r6, .L13+24
	ldr	r1, [r2, r5, lsl #2]
	ldr	r0, [r3]
	bl	WRITE_PORT_UCHAR
	ldr	r0, [r6]
	add	r0, r4, r0
	bl	READ_REGISTER_UCHAR
	ldr	r0, [r6]
	mov	r1, r8
	add	r0, r4, r0
	bl	WRITE_REGISTER_UCHAR
	b	.L6
.L10:
	ldr	r0, .L13+12
	mov	r1, #8
	ldr	r0, [r0]
	bl	WRITE_PORT_UCHAR
	ldr	r1, .L13+28
	ldr	r0, .L13+20
	ldr	r1, [r1]
	ldr	r0, [r0]
	ldr	r1, [r1, r7, lsl #2]
	ldr	r7, .L13+24
	bl	WRITE_PORT_UCHAR
	ldr	r0, [r7]
	add	r6, r6, #8
	add	r0, r9, r0
	bl	READ_REGISTER_UCHAR
	ldr	r0, [r7]
	mov	r1, r8
	add	r0, r9, r0
	bl	WRITE_REGISTER_UCHAR
	cmp	r4, #7
	ldr	r3, .L13
	ble	.L5
.L11:
	ldr	r0, [r3]
	ldr	r2, [fp]
	ldr	r3, [sp, #4]
	ldr	r1, .L13+12
	ldr	r2, [r2, r3, lsl #2]
	ldr	r6, [r0, r6, lsl #2]
	ldr	r0, [r1]
	mov	r1, #8
	add	r6, r6, r2
	bl	WRITE_PORT_UCHAR
	ldr	r2, .L13+20
	mov	r1, #255
	ldr	r0, [r2]
	bl	WRITE_PORT_UCHAR
	ldr	r1, .L13+24
	asr	r2, r4, #3
	ldr	r0, [r1]
	mov	r1, r8
	add	r0, r6, r0
	bl	memset
	ldr	r3, .L13
	b	.L5
.L9:
	ldr	r1, .L13+28
	ldr	r3, .L13+16
	ldr	r1, [r1]
	ldr	r3, [r3]
	ldr	r2, .L13+12
	ldr	r4, [r1, r7, lsl #2]
	ldr	r3, [r3, r5, lsl #2]
	ldr	r0, [r2]
	mov	r1, #8
	and	r4, r4, r3
	bl	WRITE_PORT_UCHAR
	ldr	r3, .L13+20
	ldr	r5, .L13+24
	mov	r1, r4
	ldr	r0, [r3]
	bl	WRITE_PORT_UCHAR
	ldr	r0, [r5]
	add	r0, r9, r0
	bl	READ_REGISTER_UCHAR
	ldr	r0, [r5]
	mov	r1, r8
	add	r0, r9, r0
	bl	WRITE_REGISTER_UCHAR
	ldr	r3, .L13+8
	ldr	r0, [r3]
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L14:
	.align	2
.L13:
	.word	xconv
	.word	y80
	.word	TRUE
	.word	GRA_I
	.word	endmasks
	.word	GRA_D
	.word	vidmem
	.word	startmasks
	.size	vgaHLine, .-vgaHLine
	.comm	y80,4,4
	.comm	xconv,4,4
	.comm	vidmem,4,4
	.comm	startmasks,4,4
	.comm	endmasks,4,4
	.comm	TRUE,4,4
	.comm	GRA_I,4,4
	.comm	GRA_D,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
