	.file	"extr_atl1c_main.c_atl1c_intr.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC0:
	.string	"atl1c hardware error (status = 0x%x)\n"
	.align 8
.LC1:
	.string	"TX/RX overflow (status = 0x%x)\n"
	.text
	.p2align 4
	.type	atl1c_intr, @function
atl1c_intr:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	mov	rdi, rsi
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 40
	.cfi_def_cfa_offset 96
	mov	QWORD PTR 8[rsp], rsi
	lea	rbp, 20[rsp]
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 24[rsp], rax
	xor	eax, eax
	call	netdev_priv@PLT
	mov	ebx, DWORD PTR AT_MAX_INT_WORK[rip]
	mov	r12d, DWORD PTR IRQ_NONE[rip]
	mov	r15, rax
	mov	rax, QWORD PTR 16[rax]
	lea	r13, 12[r15]
	mov	QWORD PTR [rsp], rax
	jmp	.L17
	.p2align 4,,10
	.p2align 3
.L5:
	mov	esi, DWORD PTR REG_ISR[rip]
	or	edx, r14d
	mov	rdi, r15
	call	AT_WRITE_REG@PLT
	test	DWORD PTR ISR_RX_PKT[rip], r14d
	jne	.L40
.L7:
	test	DWORD PTR ISR_TX_PKT[rip], r14d
	jne	.L41
	mov	r12d, DWORD PTR IRQ_HANDLED[rip]
	test	DWORD PTR ISR_ERROR[rip], r14d
	jne	.L42
.L10:
	test	DWORD PTR ISR_OVER[rip], r14d
	jne	.L43
.L14:
	mov	eax, DWORD PTR ISR_GPHY[rip]
	or	eax, DWORD PTR ISR_MANUAL[rip]
	test	eax, r14d
	jne	.L44
	sub	ebx, 1
	test	ebx, ebx
	jle	.L4
.L17:
	mov	esi, DWORD PTR REG_ISR[rip]
	mov	rdx, rbp
	mov	rdi, r15
	call	AT_READ_REG@PLT
	mov	ecx, DWORD PTR [r15]
	and	ecx, DWORD PTR 20[rsp]
	mov	r14d, ecx
	je	.L2
	mov	edx, DWORD PTR ISR_DIS_INT[rip]
	test	edx, ecx
	jne	.L2
	test	DWORD PTR ISR_GPHY[rip], ecx
	je	.L5
	mov	rdi, r15
	call	atl1c_clear_phy_int@PLT
	mov	edx, DWORD PTR ISR_DIS_INT[rip]
	jmp	.L5
	.p2align 4,,10
	.p2align 3
.L41:
	mov	esi, DWORD PTR atl1c_trans_normal[rip]
	mov	rdi, r15
	call	atl1c_clean_tx_irq@PLT
	mov	r12d, DWORD PTR IRQ_HANDLED[rip]
	test	DWORD PTR ISR_ERROR[rip], r14d
	je	.L10
.L42:
	mov	rdi, r15
	call	netif_msg_hw@PLT
	test	rax, rax
	jne	.L45
.L11:
	mov	edi, DWORD PTR ATL1C_WORK_EVENT_RESET[rip]
	lea	rsi, 8[r15]
	call	set_bit@PLT
	lea	rdi, 4[r15]
	call	schedule_work@PLT
	mov	r12d, DWORD PTR IRQ_HANDLED[rip]
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L40:
	mov	rdi, r13
	call	napi_schedule_prep@PLT
	mov	edi, eax
	call	likely@PLT
	test	rax, rax
	je	.L7
	mov	edx, DWORD PTR ISR_RX_PKT[rip]
	mov	rdi, r15
	not	edx
	and	edx, DWORD PTR [r15]
	mov	DWORD PTR [r15], edx
	mov	esi, DWORD PTR REG_IMR[rip]
	call	AT_WRITE_REG@PLT
	mov	rdi, r13
	call	__napi_schedule@PLT
	jmp	.L7
	.p2align 4,,10
	.p2align 3
.L43:
	mov	rdi, r15
	call	netif_msg_intr@PLT
	test	rax, rax
	je	.L14
	mov	edx, DWORD PTR ISR_OVER[rip]
	mov	rdi, QWORD PTR [rsp]
	lea	rsi, .LC1[rip]
	and	edx, r14d
	call	dev_warn@PLT
	jmp	.L14
	.p2align 4,,10
	.p2align 3
.L2:
	cmp	DWORD PTR AT_MAX_INT_WORK[rip], ebx
	je	.L4
	mov	r12d, DWORD PTR IRQ_HANDLED[rip]
.L4:
	mov	esi, DWORD PTR REG_ISR[rip]
	xor	edx, edx
	mov	rdi, r15
	call	AT_WRITE_REG@PLT
.L1:
	mov	rax, QWORD PTR 24[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L46
	add	rsp, 40
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	eax, r12d
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L44:
	.cfi_restore_state
	mov	rax, QWORD PTR 8[rsp]
	mov	rdi, r15
	add	DWORD PTR [rax], 1
	call	atl1c_link_chg_event@PLT
	jmp	.L4
.L45:
	mov	edx, DWORD PTR ISR_ERROR[rip]
	mov	rdi, QWORD PTR [rsp]
	lea	rsi, .LC0[rip]
	and	edx, r14d
	call	dev_err@PLT
	jmp	.L11
.L46:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	atl1c_intr, .-atl1c_intr
	.comm	atl1c_trans_normal,4,4
	.comm	REG_ISR,4,4
	.comm	REG_IMR,4,4
	.comm	ISR_TX_PKT,4,4
	.comm	ISR_RX_PKT,4,4
	.comm	ISR_OVER,4,4
	.comm	ISR_MANUAL,4,4
	.comm	ISR_GPHY,4,4
	.comm	ISR_ERROR,4,4
	.comm	ISR_DIS_INT,4,4
	.comm	IRQ_NONE,4,4
	.comm	IRQ_HANDLED,4,4
	.comm	AT_MAX_INT_WORK,4,4
	.comm	ATL1C_WORK_EVENT_RESET,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_atl1c_main.c_atl1c_intr.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"atl1c hardware error (status = 0x%x)\012\000"
	.align	2
.LC1:
	.ascii	"TX/RX overflow (status = 0x%x)\012\000"
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC2:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	atl1c_intr, %function
atl1c_intr:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r3, .L47
	sub	sp, sp, #20
	str	r1, [sp, #4]
	mov	r0, r1
	ldr	r3, [r3]
	str	r3, [sp, #12]
	mov	r3,#0
	bl	netdev_priv
	ldr	r2, [r0, #16]
	ldr	r3, .L47+4
	str	r2, [sp]
	ldr	r2, .L47+8
	mov	r5, r0
	ldr	r6, [r2]
	ldr	r9, [r3]
	ldr	r7, .L47+12
	ldr	r8, .L47+16
	ldr	r10, .L47+20
	ldr	fp, .L47+24
	b	.L17
.L5:
	mov	r0, r5
	ldr	r1, [r7]
	orr	r2, r4, r2
	bl	AT_WRITE_REG
	ldr	r3, [r10]
	tst	r4, r3
	bne	.L40
.L7:
	ldr	r3, [fp]
	tst	r4, r3
	bne	.L41
.L9:
	ldr	r2, .L47+28
	ldr	r3, .L47+32
	ldr	r1, [r2]
	ldr	r9, [r3]
	tst	r4, r1
	bne	.L42
	ldr	r3, .L47+36
	ldr	r2, [r3]
	tst	r4, r2
	bne	.L43
.L14:
	ldr	r2, .L47+40
	ldr	r3, [r8]
	ldr	r2, [r2]
	orr	r3, r3, r2
	tst	r3, r4
	bne	.L44
	sub	r6, r6, #1
	cmp	r6, #0
	ble	.L4
.L17:
	mov	r0, r5
	ldr	r1, [r7]
	add	r2, sp, #8
	bl	AT_READ_REG
	ldr	r4, [r5]
	ldr	r3, [sp, #8]
	ands	r4, r4, r3
	beq	.L2
	ldr	r3, .L47+44
	ldr	r2, [r3]
	tst	r2, r4
	bne	.L2
	ldr	r3, [r8]
	tst	r4, r3
	beq	.L5
	mov	r0, r5
	bl	atl1c_clear_phy_int
	ldr	r3, .L47+44
	ldr	r2, [r3]
	b	.L5
.L41:
	ldr	r3, .L47+48
	mov	r0, r5
	ldr	r1, [r3]
	bl	atl1c_clean_tx_irq
	b	.L9
.L40:
	add	r9, r5, #12
	mov	r0, r9
	bl	napi_schedule_prep
	bl	likely
	cmp	r0, #0
	beq	.L7
	ldr	r3, [r10]
	ldr	r2, [r5]
	mov	r0, r5
	bic	r2, r2, r3
	ldr	r3, .L47+52
	str	r2, [r5]
	ldr	r1, [r3]
	bl	AT_WRITE_REG
	mov	r0, r9
	bl	__napi_schedule
	b	.L7
.L43:
	mov	r0, r5
	bl	netif_msg_intr
	cmp	r0, #0
	ldr	r3, .L47+36
	beq	.L14
	ldr	r2, [r3]
	ldr	r1, .L47+56
	ldr	r0, [sp]
	and	r2, r2, r4
	bl	dev_warn
	b	.L14
.L2:
	ldr	r3, .L47+8
	ldr	r3, [r3]
	cmp	r3, r6
	ldrne	r3, .L47+32
	ldrne	r9, [r3]
.L4:
	mov	r0, r5
	mov	r2, #0
	ldr	r1, [r7]
	bl	AT_WRITE_REG
.L1:
	ldr	r3, .L47
	ldr	r2, [r3]
	ldr	r3, [sp, #12]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L45
	mov	r0, r9
	add	sp, sp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L42:
	mov	r0, r5
	bl	netif_msg_hw
	cmp	r0, #0
	ldr	r2, .L47+28
	bne	.L46
.L11:
	ldr	r2, .L47+60
	add	r1, r5, #8
	ldr	r0, [r2]
	bl	set_bit
	add	r0, r5, #4
	bl	schedule_work
	ldr	r3, .L47+32
	ldr	r9, [r3]
	b	.L1
.L44:
	ldr	r2, [sp, #4]
	mov	r0, r5
	ldr	r3, [r2]
	add	r3, r3, #1
	str	r3, [r2]
	bl	atl1c_link_chg_event
	b	.L4
.L46:
	ldr	r2, [r2]
	ldr	r0, [sp]
	ldr	r1, .L47+64
	and	r2, r2, r4
	bl	dev_err
	b	.L11
.L45:
	bl	__stack_chk_fail
.L48:
	.align	2
.L47:
	.word	.LC2
	.word	IRQ_NONE
	.word	AT_MAX_INT_WORK
	.word	REG_ISR
	.word	ISR_GPHY
	.word	ISR_RX_PKT
	.word	ISR_TX_PKT
	.word	ISR_ERROR
	.word	IRQ_HANDLED
	.word	ISR_OVER
	.word	ISR_MANUAL
	.word	ISR_DIS_INT
	.word	atl1c_trans_normal
	.word	REG_IMR
	.word	.LC1
	.word	ATL1C_WORK_EVENT_RESET
	.word	.LC0
	.size	atl1c_intr, .-atl1c_intr
	.comm	atl1c_trans_normal,4,4
	.comm	REG_ISR,4,4
	.comm	REG_IMR,4,4
	.comm	ISR_TX_PKT,4,4
	.comm	ISR_RX_PKT,4,4
	.comm	ISR_OVER,4,4
	.comm	ISR_MANUAL,4,4
	.comm	ISR_GPHY,4,4
	.comm	ISR_ERROR,4,4
	.comm	ISR_DIS_INT,4,4
	.comm	IRQ_NONE,4,4
	.comm	IRQ_HANDLED,4,4
	.comm	AT_MAX_INT_WORK,4,4
	.comm	ATL1C_WORK_EVENT_RESET,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
