	.file	"extr_dsi.c_dsi_config_cmd_mode_interleaving.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC0:
	.string	"DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n"
	.align 8
.LC1:
	.string	"DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n"
	.text
	.p2align 4
	.type	dsi_config_cmd_mode_interleaving, @function
dsi_config_cmd_mode_interleaving:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 72
	.cfi_def_cfa_offset 128
	call	dsi_get_dsidrv_data@PLT
	mov	edi, DWORD PTR 16[rax]
	mov	r13, rax
	call	dsi_get_pixel_size@PLT
	mov	rdx, QWORD PTR HSDIV_DSI[rip]
	mov	esi, DWORD PTR DSI_CTRL[rip]
	mov	rdi, rbp
	mov	r15d, eax
	mov	eax, DWORD PTR 0[r13]
	lea	r8d, -1[rax]
	mov	rax, QWORD PTR 8[r13]
	mov	DWORD PTR 40[rsp], r8d
	mov	eax, DWORD PTR [rax+rdx*4]
	add	eax, 1
	mov	DWORD PTR 8[rsp], eax
	call	dsi_read_reg@PLT
	mov	edx, 20
	mov	esi, 20
	mov	r14d, eax
	mov	edi, eax
	call	FLD_GET@PLT
	mov	edi, r14d
	mov	edx, 21
	mov	esi, 21
	mov	DWORD PTR 32[rsp], eax
	call	FLD_GET@PLT
	mov	edi, r14d
	mov	edx, 22
	mov	esi, 22
	mov	r12d, eax
	call	FLD_GET@PLT
	mov	edx, 23
	mov	edi, r14d
	mov	esi, 23
	mov	DWORD PTR 36[rsp], eax
	call	FLD_GET@PLT
	mov	esi, DWORD PTR DSI_VM_TIMING1[rip]
	mov	rdi, rbp
	mov	r14d, eax
	call	dsi_read_reg@PLT
	xor	edx, edx
	mov	esi, 11
	mov	ebx, eax
	mov	edi, eax
	call	FLD_GET@PLT
	mov	edi, ebx
	mov	edx, 12
	mov	esi, 23
	mov	DWORD PTR 44[rsp], eax
	call	FLD_GET@PLT
	mov	edx, 24
	mov	edi, ebx
	mov	esi, 31
	mov	DWORD PTR 48[rsp], eax
	call	FLD_GET@PLT
	mov	esi, DWORD PTR DSI_CLK_TIMING[rip]
	mov	rdi, rbp
	mov	DWORD PTR 52[rsp], eax
	call	dsi_read_reg@PLT
	xor	edx, edx
	mov	esi, 7
	mov	ebx, eax
	mov	edi, eax
	call	FLD_GET@PLT
	mov	edx, 8
	mov	edi, ebx
	mov	esi, 15
	mov	DWORD PTR 12[rsp], eax
	call	FLD_GET@PLT
	mov	esi, DWORD PTR DSI_VM_TIMING7[rip]
	mov	rdi, rbp
	mov	DWORD PTR 16[rsp], eax
	call	dsi_read_reg@PLT
	xor	edx, edx
	mov	esi, 15
	mov	ebx, eax
	mov	edi, eax
	call	FLD_GET@PLT
	mov	edx, 16
	mov	edi, ebx
	mov	esi, 31
	mov	DWORD PTR [rsp], eax
	call	FLD_GET@PLT
	mov	esi, DWORD PTR DSI_CLK_CTRL[rip]
	mov	rdi, rbp
	mov	DWORD PTR 4[rsp], eax
	call	dsi_read_reg@PLT
	xor	edx, edx
	mov	esi, 12
	mov	ebx, eax
	mov	edi, eax
	call	FLD_GET@PLT
	mov	edx, 13
	mov	edi, ebx
	mov	esi, 13
	mov	DWORD PTR 20[rsp], eax
	call	FLD_GET@PLT
	mov	esi, DWORD PTR DSI_DSIPHY_CFG0[rip]
	mov	rdi, rbp
	mov	DWORD PTR 24[rsp], eax
	call	dsi_read_reg@PLT
	xor	edx, edx
	mov	esi, 7
	mov	edi, eax
	call	FLD_GET@PLT
	mov	esi, DWORD PTR DSI_DSIPHY_CFG1[rip]
	mov	rdi, rbp
	mov	ebx, eax
	call	dsi_read_reg@PLT
	mov	edx, 8
	mov	esi, 15
	mov	edi, eax
	call	FLD_GET@PLT
	mov	edi, DWORD PTR 20[r13]
	mov	esi, 8
	add	eax, ebx
	imul	edi, r15d
	mov	DWORD PTR 28[rsp], eax
	xor	r15d, r15d
	call	DIV_ROUND_UP@PLT
	mov	r8d, DWORD PTR 40[rsp]
	lea	edi, 6[rax]
	mov	esi, r8d
	call	DIV_ROUND_UP@PLT
	xor	r11d, r11d
	mov	DWORD PTR 40[rsp], eax
	test	r14d, r14d
	je	.L13
	xor	r14d, r14d
	xor	r10d, r10d
	test	r12d, r12d
	je	.L14
.L3:
	mov	r8d, DWORD PTR 36[rsp]
	xor	r13d, r13d
	xor	ebx, ebx
	test	r8d, r8d
	je	.L15
.L4:
	mov	ecx, DWORD PTR 32[rsp]
	xor	r12d, r12d
	xor	r9d, r9d
	test	ecx, ecx
	je	.L16
.L5:
	mov	r8d, r9d
	mov	edx, r10d
	mov	esi, r11d
	mov	ecx, ebx
	lea	rdi, .LC0[rip]
	mov	DWORD PTR 8[rsp], r9d
	mov	DWORD PTR 4[rsp], r10d
	mov	DWORD PTR [rsp], r11d
	call	DSSDBG@PLT
	mov	r8d, r12d
	mov	ecx, r13d
	mov	edx, r14d
	mov	esi, r15d
	lea	rdi, .LC1[rip]
	call	DSSDBG@PLT
	mov	esi, DWORD PTR DSI_VM_TIMING4[rip]
	mov	rdi, rbp
	call	dsi_read_reg@PLT
	mov	r11d, DWORD PTR [rsp]
	mov	ecx, 16
	mov	edx, 23
	mov	edi, eax
	mov	esi, r11d
	call	FLD_MOD@PLT
	mov	r10d, DWORD PTR 4[rsp]
	mov	ecx, 8
	mov	edx, 15
	mov	edi, eax
	mov	esi, r10d
	call	FLD_MOD@PLT
	xor	ecx, ecx
	mov	esi, ebx
	mov	edx, 7
	mov	edi, eax
	call	FLD_MOD@PLT
	mov	esi, DWORD PTR DSI_VM_TIMING4[rip]
	mov	rdi, rbp
	mov	edx, eax
	call	dsi_write_reg@PLT
	mov	esi, DWORD PTR DSI_VM_TIMING5[rip]
	mov	rdi, rbp
	call	dsi_read_reg@PLT
	mov	esi, r15d
	mov	ecx, 16
	mov	edx, 23
	mov	edi, eax
	call	FLD_MOD@PLT
	mov	esi, r14d
	mov	ecx, 8
	mov	edx, 15
	mov	edi, eax
	call	FLD_MOD@PLT
	xor	ecx, ecx
	mov	esi, r13d
	mov	edx, 7
	mov	edi, eax
	call	FLD_MOD@PLT
	mov	esi, DWORD PTR DSI_VM_TIMING5[rip]
	mov	rdi, rbp
	mov	edx, eax
	call	dsi_write_reg@PLT
	mov	esi, DWORD PTR DSI_VM_TIMING6[rip]
	mov	rdi, rbp
	call	dsi_read_reg@PLT
	mov	r9d, DWORD PTR 8[rsp]
	mov	ecx, 15
	mov	edx, 31
	mov	edi, eax
	mov	esi, r9d
	call	FLD_MOD@PLT
	mov	esi, r12d
	mov	edx, 16
	xor	ecx, ecx
	mov	edi, eax
	call	FLD_MOD@PLT
	mov	esi, DWORD PTR DSI_VM_TIMING6[rip]
	add	rsp, 72
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	rdi, rbp
	pop	rbx
	.cfi_def_cfa_offset 48
	mov	edx, eax
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	jmp	dsi_write_reg@PLT
	.p2align 4,,10
	.p2align 3
.L13:
	.cfi_restore_state
	sub	rsp, 8
	.cfi_def_cfa_offset 136
	mov	eax, DWORD PTR 20[rsp]
	push	rax
	.cfi_def_cfa_offset 144
	mov	r14d, DWORD PTR 16[rsp]
	mov	r15d, DWORD PTR 20[rsp]
	mov	ebx, DWORD PTR 68[rsp]
	mov	r9d, DWORD PTR 32[rsp]
	mov	r8d, DWORD PTR 44[rsp]
	mov	ecx, r14d
	mov	esi, DWORD PTR 40[rsp]
	mov	edx, r15d
	mov	edi, ebx
	call	dsi_compute_interleave_hs@PLT
	mov	r8d, DWORD PTR 24[rsp]
	mov	ecx, DWORD PTR 36[rsp]
	mov	edi, ebx
	mov	edx, r14d
	mov	esi, r15d
	mov	DWORD PTR 72[rsp], eax
	xor	r14d, r14d
	call	dsi_compute_interleave_lp@PLT
	pop	r11
	.cfi_def_cfa_offset 136
	xor	r10d, r10d
	pop	rbx
	.cfi_def_cfa_offset 128
	mov	r15d, eax
	mov	r11d, DWORD PTR 56[rsp]
	test	r12d, r12d
	jne	.L3
.L14:
	mov	DWORD PTR 60[rsp], r11d
	sub	rsp, 8
	.cfi_def_cfa_offset 136
	mov	eax, DWORD PTR 20[rsp]
	push	rax
	.cfi_def_cfa_offset 144
	mov	r13d, DWORD PTR 16[rsp]
	mov	r14d, DWORD PTR 20[rsp]
	mov	ebx, DWORD PTR 64[rsp]
	mov	r9d, DWORD PTR 32[rsp]
	mov	r8d, DWORD PTR 44[rsp]
	mov	ecx, r13d
	mov	esi, DWORD PTR 40[rsp]
	mov	edx, r14d
	mov	edi, ebx
	call	dsi_compute_interleave_hs@PLT
	mov	r8d, DWORD PTR 24[rsp]
	mov	ecx, DWORD PTR 36[rsp]
	mov	edi, ebx
	mov	edx, r13d
	mov	esi, r14d
	mov	DWORD PTR 72[rsp], eax
	xor	r13d, r13d
	call	dsi_compute_interleave_lp@PLT
	pop	r9
	.cfi_def_cfa_offset 136
	pop	r10
	.cfi_def_cfa_offset 128
	xor	ebx, ebx
	mov	r8d, DWORD PTR 36[rsp]
	mov	r11d, DWORD PTR 60[rsp]
	mov	r14d, eax
	mov	r10d, DWORD PTR 56[rsp]
	test	r8d, r8d
	jne	.L4
.L15:
	mov	DWORD PTR 56[rsp], r10d
	sub	rsp, 8
	.cfi_def_cfa_offset 136
	mov	DWORD PTR 44[rsp], r11d
	mov	eax, DWORD PTR 20[rsp]
	push	rax
	.cfi_def_cfa_offset 144
	mov	r13d, DWORD PTR 20[rsp]
	mov	r12d, DWORD PTR 60[rsp]
	mov	r9d, DWORD PTR 32[rsp]
	mov	r8d, DWORD PTR 44[rsp]
	mov	ecx, DWORD PTR 16[rsp]
	mov	edx, r13d
	mov	esi, DWORD PTR 40[rsp]
	mov	edi, r12d
	call	dsi_compute_interleave_hs@PLT
	mov	ecx, DWORD PTR 36[rsp]
	mov	edx, DWORD PTR 16[rsp]
	mov	esi, r13d
	mov	r8d, DWORD PTR 24[rsp]
	mov	edi, r12d
	mov	ebx, eax
	xor	r12d, r12d
	call	dsi_compute_interleave_lp@PLT
	pop	rsi
	.cfi_def_cfa_offset 136
	pop	rdi
	.cfi_def_cfa_offset 128
	xor	r9d, r9d
	mov	ecx, DWORD PTR 32[rsp]
	mov	r10d, DWORD PTR 56[rsp]
	mov	r13d, eax
	mov	r11d, DWORD PTR 36[rsp]
	test	ecx, ecx
	jne	.L5
.L16:
	mov	r12d, DWORD PTR 44[rsp]
	mov	DWORD PTR 36[rsp], r10d
	sub	rsp, 8
	.cfi_def_cfa_offset 136
	add	r12d, DWORD PTR 56[rsp]
	add	r12d, DWORD PTR 60[rsp]
	mov	DWORD PTR 40[rsp], r11d
	add	r12d, DWORD PTR 48[rsp]
	mov	eax, DWORD PTR 20[rsp]
	mov	edi, r12d
	push	rax
	.cfi_def_cfa_offset 144
	mov	r9d, DWORD PTR 32[rsp]
	mov	r8d, DWORD PTR 44[rsp]
	mov	ecx, DWORD PTR 16[rsp]
	mov	edx, DWORD PTR 20[rsp]
	mov	esi, DWORD PTR 40[rsp]
	call	dsi_compute_interleave_hs@PLT
	mov	ecx, DWORD PTR 36[rsp]
	mov	edx, DWORD PTR 16[rsp]
	mov	edi, r12d
	mov	r8d, DWORD PTR 24[rsp]
	mov	esi, DWORD PTR 20[rsp]
	mov	DWORD PTR 28[rsp], eax
	call	dsi_compute_interleave_lp@PLT
	mov	r12d, eax
	pop	rax
	.cfi_def_cfa_offset 136
	pop	rdx
	.cfi_def_cfa_offset 128
	mov	r10d, DWORD PTR 36[rsp]
	mov	r11d, DWORD PTR 32[rsp]
	mov	r9d, DWORD PTR 12[rsp]
	jmp	.L5
	.cfi_endproc
.LFE0:
	.size	dsi_config_cmd_mode_interleaving, .-dsi_config_cmd_mode_interleaving
	.comm	HSDIV_DSI,8,8
	.comm	DSI_VM_TIMING7,4,4
	.comm	DSI_VM_TIMING6,4,4
	.comm	DSI_VM_TIMING5,4,4
	.comm	DSI_VM_TIMING4,4,4
	.comm	DSI_VM_TIMING1,4,4
	.comm	DSI_DSIPHY_CFG1,4,4
	.comm	DSI_DSIPHY_CFG0,4,4
	.comm	DSI_CTRL,4,4
	.comm	DSI_CLK_TIMING,4,4
	.comm	DSI_CLK_CTRL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_dsi.c_dsi_config_cmd_mode_interleaving.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HB"
	.ascii	"P %d, BLLP %d\012\000"
	.align	2
.LC1:
	.ascii	"DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, "
	.ascii	"BLLP %d\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	dsi_config_cmd_mode_interleaving, %function
dsi_config_cmd_mode_interleaving:
	@ args = 0, pretend = 0, frame = 56
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	sub	sp, sp, #76
	mov	r4, r0
	bl	dsi_get_dsidrv_data
	mov	r6, r0
	ldr	r0, [r0, #8]
	bl	dsi_get_pixel_size
	ldr	r2, .L16
	ldr	r3, [r6, #4]
	ldr	r1, [r2]
	ldr	r2, .L16+4
	ldr	r3, [r3, r1, lsl #2]
	mov	r9, r0
	add	r3, r3, #1
	ldr	r1, [r2]
	mov	r0, r4
	str	r3, [sp, #24]
	ldr	r7, [r6]
	bl	dsi_read_reg
	mov	r2, #20
	mov	r1, r2
	mov	r5, r0
	bl	FLD_GET
	mov	r2, #21
	mov	r3, r0
	mov	r1, r2
	mov	r0, r5
	str	r3, [sp, #48]
	bl	FLD_GET
	mov	r2, #22
	mov	r3, r0
	mov	r1, r2
	mov	r0, r5
	str	r3, [sp, #52]
	bl	FLD_GET
	mov	r2, #23
	mov	r3, r0
	mov	r1, r2
	mov	r0, r5
	str	r3, [sp, #56]
	bl	FLD_GET
	ldr	r3, .L16+8
	mov	r10, r0
	ldr	r1, [r3]
	mov	r0, r4
	bl	dsi_read_reg
	mov	r2, #0
	mov	r1, #11
	mov	r8, r0
	bl	FLD_GET
	mov	r5, r0
	mov	r2, #12
	mov	r0, r8
	mov	r1, #23
	str	r5, [sp, #60]
	bl	FLD_GET
	mov	r5, r0
	mov	r2, #24
	mov	r0, r8
	mov	r1, #31
	str	r5, [sp, #64]
	bl	FLD_GET
	mov	r5, r0
	ldr	r3, .L16+12
	mov	r0, r4
	ldr	r1, [r3]
	str	r5, [sp, #68]
	bl	dsi_read_reg
	mov	r2, #0
	mov	r1, #7
	mov	r5, r0
	bl	FLD_GET
	mov	r3, r0
	mov	r2, #8
	mov	r0, r5
	mov	r1, #15
	str	r3, [sp, #28]
	bl	FLD_GET
	mov	r3, r0
	ldr	r2, .L16+16
	mov	r0, r4
	ldr	r1, [r2]
	str	r3, [sp, #32]
	bl	dsi_read_reg
	mov	r2, #0
	mov	r1, #15
	mov	r5, r0
	bl	FLD_GET
	mov	r2, #16
	mov	r1, #31
	mov	r8, r0
	mov	r0, r5
	bl	FLD_GET
	ldr	r3, .L16+20
	mov	fp, r0
	ldr	r1, [r3]
	mov	r0, r4
	bl	dsi_read_reg
	mov	r2, #0
	mov	r1, #12
	mov	r5, r0
	bl	FLD_GET
	mov	r2, #13
	mov	r3, r0
	mov	r1, r2
	mov	r0, r5
	str	r3, [sp, #36]
	bl	FLD_GET
	mov	r3, r0
	ldr	r2, .L16+24
	mov	r0, r4
	ldr	r1, [r2]
	str	r3, [sp, #40]
	bl	dsi_read_reg
	mov	r2, #0
	mov	r1, #7
	bl	FLD_GET
	ldr	r3, .L16+28
	mov	r5, r0
	ldr	r1, [r3]
	mov	r0, r4
	bl	dsi_read_reg
	mov	r2, #8
	mov	r1, #15
	bl	FLD_GET
	mov	r3, r0
	ldr	r0, [r6, #12]
	add	r3, r5, r3
	mov	r1, #8
	mul	r0, r9, r0
	str	r3, [sp, #44]
	bl	DIV_ROUND_UP
	sub	r7, r7, #1
	mov	r1, r7
	add	r0, r0, #6
	bl	DIV_ROUND_UP
	cmp	r10, #0
	movne	r3, #0
	mov	r5, r0
	strne	r3, [sp, #20]
	strne	r3, [sp, #16]
	beq	.L12
.L2:
	ldr	r3, [sp, #52]
	cmp	r3, #0
	movne	r7, #0
	movne	r10, r7
	beq	.L13
.L3:
	ldr	r3, [sp, #56]
	cmp	r3, #0
	movne	r6, #0
	movne	r9, r6
	beq	.L14
.L4:
	ldr	r3, [sp, #48]
	cmp	r3, #0
	movne	r5, #0
	movne	r8, r5
	beq	.L15
.L5:
	mov	r3, r9
	mov	r2, r10
	ldr	r1, [sp, #16]
	ldr	fp, .L16+32
	str	r8, [sp]
	ldr	r0, .L16+36
	bl	DSSDBG
	mov	r3, r6
	mov	r2, r7
	ldr	r1, [sp, #20]
	str	r5, [sp]
	ldr	r0, .L16+40
	bl	DSSDBG
	ldr	r1, [fp]
	mov	r0, r4
	bl	dsi_read_reg
	ldr	r1, [sp, #16]
	mov	r3, #16
	mov	r2, #23
	bl	FLD_MOD
	mov	r1, r10
	mov	r3, #8
	mov	r2, #15
	bl	FLD_MOD
	mov	r3, #0
	mov	r1, r9
	mov	r2, #7
	bl	FLD_MOD
	ldr	r10, .L16+44
	mov	r2, r0
	ldr	r1, [fp]
	mov	r0, r4
	bl	dsi_write_reg
	ldr	r1, [r10]
	mov	r0, r4
	bl	dsi_read_reg
	ldr	r1, [sp, #20]
	mov	r3, #16
	mov	r2, #23
	bl	FLD_MOD
	mov	r1, r7
	mov	r3, #8
	mov	r2, #15
	bl	FLD_MOD
	mov	r3, #0
	mov	r1, r6
	mov	r2, #7
	bl	FLD_MOD
	ldr	r7, .L16+48
	mov	r2, r0
	ldr	r1, [r10]
	mov	r0, r4
	bl	dsi_write_reg
	ldr	r1, [r7]
	mov	r0, r4
	bl	dsi_read_reg
	mov	r1, r8
	mov	r3, #15
	mov	r2, #31
	bl	FLD_MOD
	mov	r1, r5
	mov	r3, #0
	mov	r2, #16
	bl	FLD_MOD
	mov	r2, r0
	mov	r0, r4
	ldr	r1, [r7]
	add	sp, sp, #76
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	b	dsi_write_reg
.L12:
	ldr	r3, [sp, #28]
	ldr	r6, [sp, #68]
	str	r3, [sp, #8]
	ldr	r3, [sp, #32]
	mov	r2, fp
	str	r3, [sp, #4]
	ldr	r3, [sp, #44]
	ldr	r1, [sp, #40]
	str	r3, [sp]
	mov	r0, r6
	mov	r3, r8
	bl	dsi_compute_interleave_hs
	mov	ip, r0
	ldr	r3, [sp, #24]
	mov	r2, r8
	str	r3, [sp]
	mov	r1, fp
	mov	r0, r6
	ldr	r3, [sp, #36]
	str	ip, [sp, #16]
	bl	dsi_compute_interleave_lp
	str	r0, [sp, #20]
	b	.L2
.L15:
	ldr	r3, [sp, #60]
	ldr	r2, [sp, #64]
	ldr	r1, [sp, #40]
	add	r0, r3, r2
	ldr	r3, [sp, #68]
	mov	r2, fp
	add	r0, r0, r3
	ldr	r3, [sp, #28]
	add	r5, r0, r5
	str	r3, [sp, #8]
	ldr	r3, [sp, #32]
	mov	r0, r5
	str	r3, [sp, #4]
	ldr	r3, [sp, #44]
	str	r3, [sp]
	mov	r3, r8
	bl	dsi_compute_interleave_hs
	mov	ip, r0
	ldr	r3, [sp, #24]
	mov	r0, r5
	mov	r2, r8
	str	r3, [sp]
	mov	r1, fp
	ldr	r3, [sp, #36]
	mov	r8, ip
	bl	dsi_compute_interleave_lp
	mov	r5, r0
	b	.L5
.L14:
	ldr	r3, [sp, #28]
	ldr	r6, [sp, #60]
	str	r3, [sp, #8]
	ldr	r3, [sp, #32]
	mov	r2, fp
	str	r3, [sp, #4]
	ldr	r3, [sp, #44]
	mov	r0, r6
	ldr	r1, [sp, #40]
	str	r3, [sp]
	mov	r3, r8
	bl	dsi_compute_interleave_hs
	ldr	r3, [sp, #24]
	mov	r9, r0
	str	r3, [sp]
	mov	r0, r6
	mov	r2, r8
	mov	r1, fp
	ldr	r3, [sp, #36]
	bl	dsi_compute_interleave_lp
	mov	r6, r0
	b	.L4
.L13:
	ldr	r3, [sp, #28]
	ldr	r6, [sp, #64]
	str	r3, [sp, #8]
	ldr	r3, [sp, #32]
	mov	r2, fp
	str	r3, [sp, #4]
	ldr	r3, [sp, #44]
	ldr	r1, [sp, #40]
	str	r3, [sp]
	mov	r0, r6
	mov	r3, r8
	bl	dsi_compute_interleave_hs
	ldr	r3, [sp, #24]
	mov	r10, r0
	str	r3, [sp]
	mov	r2, r8
	mov	r1, fp
	mov	r0, r6
	ldr	r3, [sp, #36]
	bl	dsi_compute_interleave_lp
	mov	r7, r0
	b	.L3
.L17:
	.align	2
.L16:
	.word	HSDIV_DSI
	.word	DSI_CTRL
	.word	DSI_VM_TIMING1
	.word	DSI_CLK_TIMING
	.word	DSI_VM_TIMING7
	.word	DSI_CLK_CTRL
	.word	DSI_DSIPHY_CFG0
	.word	DSI_DSIPHY_CFG1
	.word	DSI_VM_TIMING4
	.word	.LC0
	.word	.LC1
	.word	DSI_VM_TIMING5
	.word	DSI_VM_TIMING6
	.size	dsi_config_cmd_mode_interleaving, .-dsi_config_cmd_mode_interleaving
	.comm	HSDIV_DSI,4,4
	.comm	DSI_VM_TIMING7,4,4
	.comm	DSI_VM_TIMING6,4,4
	.comm	DSI_VM_TIMING5,4,4
	.comm	DSI_VM_TIMING4,4,4
	.comm	DSI_VM_TIMING1,4,4
	.comm	DSI_DSIPHY_CFG1,4,4
	.comm	DSI_DSIPHY_CFG0,4,4
	.comm	DSI_CTRL,4,4
	.comm	DSI_CLK_TIMING,4,4
	.comm	DSI_CLK_CTRL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
