	.file	"extr_tlv320aic32x4.c_aic32x4_setup_clocks.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"pll"
.LC1:
	.string	"nadc"
.LC2:
	.string	"madc"
.LC3:
	.string	"ndac"
.LC4:
	.string	"mdac"
.LC5:
	.string	"bdiv"
.LC6:
	.string	"Sampling rate not supported\n"
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC7:
	.string	"Could not set clocks to support sample rate.\n"
	.text
	.p2align 4
	.type	aic32x4_setup_clocks, @function
aic32x4_setup_clocks:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	mov	ecx, 11
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	ebx, esi
	sub	rsp, 200
	.cfi_def_cfa_offset 256
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 184[rsp], rax
	xor	eax, eax
	lea	rdi, 88[rsp]
	lea	r12, 80[rsp]
	rep stosq
	lea	rax, .LC0[rip]
	mov	rdi, r12
	mov	QWORD PTR 80[rsp], rax
	lea	rax, .LC1[rip]
	mov	QWORD PTR 96[rsp], rax
	lea	rax, .LC2[rip]
	mov	QWORD PTR 112[rsp], rax
	lea	rax, .LC3[rip]
	mov	QWORD PTR 128[rsp], rax
	lea	rax, .LC4[rip]
	mov	QWORD PTR 144[rsp], rax
	lea	rax, .LC5[rip]
	mov	QWORD PTR 160[rsp], rax
	call	ARRAY_SIZE@PLT
	mov	edi, DWORD PTR 0[rbp]
	mov	rdx, r12
	mov	esi, eax
	call	devm_clk_bulk_get@PLT
	mov	r15d, eax
	test	eax, eax
	jne	.L1
	cmp	ebx, 48000
	jbe	.L36
	cmp	ebx, 96000
	jbe	.L37
	cmp	ebx, 192000
	jne	.L6
	mov	rdi, rbp
	mov	edx, 19
	mov	esi, 13
	mov	r13d, 2
	call	aic32x4_set_processing_blocks@PLT
	mov	r12d, 4
	mov	edi, 96
	mov	DWORD PTR 32[rsp], 2
	mov	DWORD PTR 8[rsp], 32
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L15:
	add	DWORD PTR 4[rsp], 1
	mov	eax, DWORD PTR 4[rsp]
	mov	ecx, DWORD PTR 68[rsp]
	add	ebp, DWORD PTR 52[rsp]
	add	DWORD PTR 12[rsp], ecx
	cmp	eax, 129
	jne	.L12
	mov	ebp, r12d
.L11:
	mov	edx, DWORD PTR 72[rsp]
	sub	r14d, DWORD PTR 32[rsp]
	add	DWORD PTR 52[rsp], edx
	cmp	DWORD PTR 28[rsp], r14d
	jle	.L8
	mov	r13d, ebp
.L16:
	add	r13d, DWORD PTR 76[rsp]
	sub	DWORD PTR 36[rsp], 1
	jne	.L9
	mov	rbp, QWORD PTR 56[rsp]
.L10:
	mov	edi, DWORD PTR 0[rbp]
	lea	rsi, .LC7[rip]
	call	dev_err@PLT
	mov	r15d, DWORD PTR EINVAL[rip]
	neg	r15d
	.p2align 4,,10
	.p2align 3
.L1:
	mov	rax, QWORD PTR 184[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L38
	add	rsp, 200
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	eax, r15d
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L36:
	.cfi_restore_state
	mov	rdi, rbp
	mov	edx, 1
	mov	esi, 1
	mov	r13d, 8
	call	aic32x4_set_processing_blocks@PLT
	mov	r12d, 8
	mov	edi, 192
	mov	DWORD PTR 32[rsp], 8
	mov	DWORD PTR 8[rsp], 128
.L4:
	mov	r14d, DWORD PTR 8[rsp]
	mov	esi, r14d
	call	DIV_ROUND_UP@PLT
	xor	edx, edx
	mov	ecx, r14d
	mov	edi, eax
	mov	DWORD PTR 24[rsp], eax
	mov	eax, DWORD PTR AIC32X4_MAX_DOSR_FREQ[rip]
	imul	ecx, edi
	div	ebx
	xor	edx, edx
	imul	ecx, ebx
	div	r13d
	xor	edx, edx
	imul	eax, r13d
	mov	DWORD PTR 16[rsp], eax
	mov	eax, DWORD PTR AIC32X4_MIN_DOSR_FREQ[rip]
	div	ebx
	xor	edx, edx
	div	r13d
	xor	edx, edx
	imul	eax, r13d
	mov	DWORD PTR 28[rsp], eax
	mov	eax, DWORD PTR AIC32X4_MAX_CODEC_CLKIN_FREQ[rip]
	div	ecx
	mov	DWORD PTR 36[rsp], eax
	test	eax, eax
	jle	.L10
	mov	edx, DWORD PTR 24[rsp]
	mov	edi, DWORD PTR 8[rsp]
	sal	r12d, 5
	mov	DWORD PTR 20[rsp], ebx
	mov	DWORD PTR 40[rsp], r12d
	mov	eax, edx
	imul	edx, DWORD PTR 36[rsp]
	mov	DWORD PTR 64[rsp], r15d
	neg	eax
	mov	QWORD PTR 56[rsp], rbp
	imul	eax, edi
	mov	ecx, edx
	imul	ecx, edi
	imul	eax, ebx
	imul	ecx, ebx
	mov	DWORD PTR 76[rsp], eax
	mov	eax, DWORD PTR 32[rsp]
	imul	eax, ebx
	mov	r13d, ecx
	mov	DWORD PTR 72[rsp], eax
	mov	eax, DWORD PTR 16[rsp]
	imul	eax, ebx
	neg	eax
	mov	DWORD PTR 44[rsp], eax
.L9:
	mov	eax, DWORD PTR 44[rsp]
	mov	edx, DWORD PTR 28[rsp]
	mov	ebp, r13d
	mov	DWORD PTR 52[rsp], eax
	mov	eax, DWORD PTR 16[rsp]
	mov	r14d, eax
	cmp	eax, edx
	jl	.L16
.L8:
	mov	edi, DWORD PTR 40[rsp]
	mov	esi, r14d
	call	DIV_ROUND_UP@PLT
	mov	esi, DWORD PTR 20[rsp]
	xor	edx, edx
	mov	ecx, eax
	mov	DWORD PTR 4[rsp], eax
	mov	edi, eax
	mov	eax, DWORD PTR AIC32X4_MAX_CODEC_CLKIN_FREQ[rip]
	imul	ecx, r14d
	imul	ecx, esi
	div	ecx
	mov	r15d, eax
	cmp	edi, 128
	jg	.L11
	mov	ebx, edi
	imul	ebx, esi
	imul	esi, r14d
	imul	ebx, r14d
	mov	DWORD PTR 48[rsp], esi
	imul	esi, eax
	mov	r12d, ebx
	imul	ebx, eax
	mov	eax, ebp
	mov	DWORD PTR 68[rsp], esi
	neg	r12d
	mov	ebp, r12d
	mov	r12d, eax
	mov	DWORD PTR 12[rsp], ebx
.L12:
	mov	r13d, DWORD PTR 12[rsp]
	mov	ebx, r15d
	test	r15d, r15d
	jg	.L14
	jmp	.L15
	.p2align 4,,10
	.p2align 3
.L13:
	add	r13d, ebp
	sub	ebx, 1
	je	.L15
.L14:
	cmp	r13d, r12d
	jne	.L13
	mov	edi, DWORD PTR 88[rsp]
	mov	esi, r13d
	call	clk_round_rate@PLT
	test	rax, rax
	je	.L13
	mov	edi, DWORD PTR 88[rsp]
	mov	esi, r13d
	mov	rbp, QWORD PTR 56[rsp]
	mov	ebx, DWORD PTR 20[rsp]
	mov	r15d, DWORD PTR 64[rsp]
	call	clk_set_rate@PLT
	mov	r13d, DWORD PTR 8[rsp]
	mov	esi, DWORD PTR 24[rsp]
	mov	edi, DWORD PTR 104[rsp]
	mov	r12d, r13d
	imul	r12d, ebx
	sal	ebx, 5
	imul	esi, r12d
	call	clk_set_rate@PLT
	mov	edi, DWORD PTR 120[rsp]
	mov	esi, r12d
	call	clk_set_rate@PLT
	mov	esi, r13d
	mov	rdi, rbp
	call	aic32x4_set_aosr@PLT
	mov	r12d, DWORD PTR 48[rsp]
	mov	eax, DWORD PTR 4[rsp]
	mov	edi, DWORD PTR 136[rsp]
	imul	eax, r12d
	mov	esi, eax
	call	clk_set_rate@PLT
	mov	edi, DWORD PTR 152[rsp]
	mov	esi, r12d
	call	clk_set_rate@PLT
	mov	esi, r14d
	mov	rdi, rbp
	call	aic32x4_set_dosr@PLT
	mov	edi, DWORD PTR 168[rsp]
	mov	esi, ebx
	call	clk_set_rate@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L6:
	mov	edi, DWORD PTR 0[rbp]
	lea	rsi, .LC6[rip]
	call	dev_err@PLT
	mov	r15d, DWORD PTR EINVAL[rip]
	neg	r15d
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L37:
	mov	rdi, rbp
	mov	edx, 9
	mov	esi, 1
	mov	r13d, 4
	call	aic32x4_set_processing_blocks@PLT
	mov	r12d, 8
	mov	edi, 192
	mov	DWORD PTR 32[rsp], 4
	mov	DWORD PTR 8[rsp], 64
	jmp	.L4
.L38:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	aic32x4_setup_clocks, .-aic32x4_setup_clocks
	.comm	EINVAL,4,4
	.comm	AIC32X4_MIN_DOSR_FREQ,4,4
	.comm	AIC32X4_MAX_DOSR_FREQ,4,4
	.comm	AIC32X4_MAX_CODEC_CLKIN_FREQ,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_tlv320aic32x4.c_aic32x4_setup_clocks.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"pll\000"
	.align	2
.LC1:
	.ascii	"nadc\000"
	.align	2
.LC2:
	.ascii	"madc\000"
	.align	2
.LC3:
	.ascii	"ndac\000"
	.align	2
.LC4:
	.ascii	"mdac\000"
	.align	2
.LC5:
	.ascii	"bdiv\000"
	.align	2
.LC6:
	.ascii	"Sampling rate not supported\012\000"
	.global	__aeabi_uidiv
	.align	2
.LC7:
	.ascii	"Could not set clocks to support sample rate.\012\000"
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC8:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	aic32x4_setup_clocks, %function
aic32x4_setup_clocks:
	@ args = 0, pretend = 0, frame = 120
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	mov	r8, r0
	sub	sp, sp, #124
	ldr	r3, .L35
	mov	r2, #44
	mov	r6, r1
	add	r0, sp, #72
	mov	r1, #0
	ldr	r3, [r3]
	str	r3, [sp, #116]
	mov	r3,#0
	bl	memset
	ldr	r2, .L35+4
	ldr	r3, .L35+8
	str	r2, [sp, #68]
	str	r3, [sp, #76]
	ldr	r2, .L35+12
	ldr	r3, .L35+16
	str	r2, [sp, #84]
	str	r3, [sp, #92]
	ldr	r2, .L35+20
	ldr	r3, .L35+24
	add	r0, sp, #68
	str	r3, [sp, #108]
	ldr	r4, [r8]
	str	r2, [sp, #100]
	bl	ARRAY_SIZE
	add	r2, sp, #68
	mov	r1, r0
	mov	r0, r4
	bl	devm_clk_bulk_get
	subs	r3, r0, #0
	str	r3, [sp]
	bne	.L1
	ldr	r3, .L35+28
	cmp	r6, r3
	bls	.L32
	ldr	r3, .L35+32
	cmp	r6, r3
	bls	.L33
	ldr	r3, .L35+36
	cmp	r6, r3
	bne	.L6
	mov	r5, #2
	mov	r2, #19
	mov	r1, #13
	mov	r0, r8
	bl	aic32x4_set_processing_blocks
	mov	r4, #4
	mov	r0, #96
	mov	fp, #32
	str	r5, [sp, #24]
	b	.L4
.L15:
	ldr	r3, [sp, #32]
	add	r9, r9, #1
	add	r5, r5, r3
	ldr	r3, [sp, #52]
	cmp	r9, #129
	add	r6, r6, r3
	bne	.L12
.L11:
	ldr	r3, [sp, #24]
	ldr	r2, [sp, #56]
	sub	r10, r10, r3
	ldr	r3, [sp, #16]
	cmp	r3, r10
	ldr	r3, [sp, #32]
	add	r3, r3, r2
	str	r3, [sp, #32]
	ble	.L8
	mov	r7, r8
.L16:
	ldr	r3, [sp, #20]
	subs	r3, r3, #1
	str	r3, [sp, #20]
	ldr	r3, [sp, #60]
	add	r7, r7, r3
	bne	.L9
	ldr	r8, [sp, #40]
.L10:
	ldr	r0, [r8]
	ldr	r1, .L35+40
	bl	dev_err
	ldr	r3, .L35+44
	ldr	r3, [r3]
	rsb	r3, r3, #0
	str	r3, [sp]
.L1:
	ldr	r3, .L35
	ldr	r2, [r3]
	ldr	r3, [sp, #116]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L34
	ldr	r0, [sp]
	add	sp, sp, #124
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L32:
	mov	r2, #1
	mov	r5, #8
	mov	r1, r2
	mov	r0, r8
	bl	aic32x4_set_processing_blocks
	mov	r4, r5
	mov	r0, #192
	mov	fp, #128
	str	r5, [sp, #24]
.L4:
	mov	r1, fp
	bl	DIV_ROUND_UP
	mov	r3, r0
	ldr	r2, .L35+48
	mov	r1, r6
	ldr	r0, [r2]
	mov	r7, r3
	str	r3, [sp, #12]
	bl	__aeabi_uidiv
	mov	r1, r5
	bl	__aeabi_uidiv
	mov	r3, r0
	ldr	r2, .L35+52
	mov	r1, r6
	ldr	r0, [r2]
	mul	r2, r5, r3
	str	r2, [sp, #4]
	bl	__aeabi_uidiv
	mov	r1, r5
	bl	__aeabi_uidiv
	mov	r1, r7
	mov	r3, r0
	ldr	r2, .L35+56
	mul	r1, fp, r1
	ldr	r0, [r2]
	mul	r2, r5, r3
	mul	r1, r6, r1
	str	r2, [sp, #16]
	bl	__aeabi_uidiv
	subs	r3, r0, #0
	str	r3, [sp, #20]
	ble	.L10
	ldr	r3, [sp, #12]
	ldr	r2, [sp, #20]
	mov	r5, r3
	mul	r5, r2, r5
	mul	r5, fp, r5
	mul	r5, r6, r5
	mov	r7, r5
	rsb	r3, r3, #0
	mul	r3, fp, r3
	mul	r1, r6, r3
	ldr	r3, [sp, #24]
	ldr	r2, [sp, #4]
	mul	r3, r6, r3
	mul	r2, r6, r2
	str	r3, [sp, #56]
	lsl	r3, r4, #5
	str	r3, [sp, #28]
	rsb	r3, r2, #0
	str	r1, [sp, #60]
	str	r3, [sp, #44]
	str	fp, [sp, #48]
	str	r8, [sp, #40]
	str	r6, [sp, #8]
.L9:
	ldr	r3, [sp, #4]
	ldr	r2, [sp, #16]
	cmp	r3, r2
	blt	.L16
	mov	r8, r7
	ldr	r3, [sp, #44]
	ldr	r10, [sp, #4]
	str	r3, [sp, #32]
.L8:
	mov	r1, r10
	ldr	r0, [sp, #28]
	bl	DIV_ROUND_UP
	ldr	r3, .L35+56
	ldr	r4, [sp, #8]
	mul	r1, r10, r0
	mov	r9, r0
	ldr	r0, [r3]
	mov	r3, r4
	mul	r3, r1, r3
	mov	r1, r3
	bl	__aeabi_uidiv
	cmp	r9, #128
	mov	r7, r0
	bgt	.L11
	mov	r6, r4
	mov	r3, r4
	mul	r6, r9, r6
	mul	r3, r10, r3
	mul	r6, r10, r6
	str	r3, [sp, #36]
	mul	r3, r0, r3
	rsb	r5, r6, #0
	mul	r6, r0, r6
	str	r3, [sp, #52]
.L12:
	cmp	r7, #0
	movgt	fp, r6
	movgt	r4, r7
	bgt	.L14
	b	.L15
.L13:
	subs	r4, r4, #1
	add	fp, fp, r5
	beq	.L15
.L14:
	cmp	fp, r8
	bne	.L13
	mov	r1, fp
	ldr	r0, [sp, #72]
	bl	clk_round_rate
	cmp	r0, #0
	beq	.L13
	mov	r7, fp
	ldr	r6, [sp, #8]
	ldr	fp, [sp, #48]
	mov	r1, r7
	mul	r4, r6, fp
	ldr	r0, [sp, #72]
	ldr	r8, [sp, #40]
	bl	clk_set_rate
	ldr	r1, [sp, #12]
	ldr	r0, [sp, #80]
	mul	r1, r4, r1
	bl	clk_set_rate
	mov	r1, r4
	ldr	r0, [sp, #88]
	bl	clk_set_rate
	mov	r1, fp
	mov	r0, r8
	bl	aic32x4_set_aosr
	ldr	r4, [sp, #36]
	ldr	r0, [sp, #96]
	mov	r3, r4
	mul	r3, r9, r3
	mov	r1, r3
	bl	clk_set_rate
	mov	r1, r4
	ldr	r0, [sp, #104]
	bl	clk_set_rate
	mov	r1, r10
	mov	r0, r8
	bl	aic32x4_set_dosr
	ldr	r0, [sp, #112]
	lsl	r1, r6, #5
	bl	clk_set_rate
	b	.L1
.L6:
	ldr	r0, [r8]
	ldr	r1, .L35+60
	bl	dev_err
	ldr	r3, .L35+44
	ldr	r0, [r3]
	rsb	r3, r0, #0
	str	r3, [sp]
	b	.L1
.L33:
	mov	r5, #4
	mov	r2, #9
	mov	r1, #1
	mov	r0, r8
	bl	aic32x4_set_processing_blocks
	mov	r4, #8
	mov	r0, #192
	mov	fp, #64
	str	r5, [sp, #24]
	b	.L4
.L34:
	bl	__stack_chk_fail
.L36:
	.align	2
.L35:
	.word	.LC8
	.word	.LC0
	.word	.LC1
	.word	.LC2
	.word	.LC3
	.word	.LC4
	.word	.LC5
	.word	48000
	.word	96000
	.word	192000
	.word	.LC7
	.word	EINVAL
	.word	AIC32X4_MAX_DOSR_FREQ
	.word	AIC32X4_MIN_DOSR_FREQ
	.word	AIC32X4_MAX_CODEC_CLKIN_FREQ
	.word	.LC6
	.size	aic32x4_setup_clocks, .-aic32x4_setup_clocks
	.comm	EINVAL,4,4
	.comm	AIC32X4_MIN_DOSR_FREQ,4,4
	.comm	AIC32X4_MAX_DOSR_FREQ,4,4
	.comm	AIC32X4_MAX_CODEC_CLKIN_FREQ,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
