	.file	"extr_serial-tegra.c_tegra_uart_set_termios.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Failed to set baud rate\n"
	.text
	.p2align 4
	.type	tegra_uart_set_termios, @function
tegra_uart_set_termios:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	mov	r15, rdx
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	rbx, rsi
	sub	rsp, 24
	.cfi_def_cfa_offset 80
	call	to_tegra_uport@PLT
	mov	edi, DWORD PTR 40[rax]
	mov	r13, rax
	call	clk_get_parent@PLT
	mov	rdi, rax
	call	clk_get_rate@PLT
	mov	rdi, rbp
	mov	QWORD PTR [rsp], rax
	mov	rax, QWORD PTR 32[r13]
	cmp	QWORD PTR [rax], 1
	sbb	r12, r12
	xor	esi, esi
	call	spin_lock_irqsave@PLT
	and	r12d, 524288
	add	r12, 524272
	cmp	QWORD PTR 24[r13], 0
	jne	.L30
.L3:
	mov	edx, DWORD PTR UART_IER[rip]
	mov	esi, DWORD PTR 0[r13]
	mov	rdi, r13
	or	esi, DWORD PTR UART_IER_RDI[rip]
	call	tegra_uart_write@PLT
	mov	esi, DWORD PTR UART_IER[rip]
	mov	rdi, r13
	call	tegra_uart_read@PLT
	mov	edx, DWORD PTR UART_IER[rip]
	xor	esi, esi
	mov	rdi, r13
	call	tegra_uart_write@PLT
	mov	esi, DWORD PTR UART_IER[rip]
	mov	rdi, r13
	call	tegra_uart_read@PLT
	mov	eax, DWORD PTR CMSPAR[rip]
	mov	ecx, DWORD PTR 4[r13]
	mov	esi, DWORD PTR PARENB[rip]
	mov	edx, DWORD PTR UART_LCR_PARITY[rip]
	not	eax
	and	eax, DWORD PTR [rbx]
	mov	edi, eax
	mov	DWORD PTR [rbx], eax
	and	edi, esi
	cmp	esi, edi
	je	.L4
	not	edx
	mov	r14d, 1
	and	edx, ecx
.L5:
	mov	edi, DWORD PTR UART_LCR_WLEN8[rip]
	mov	esi, DWORD PTR CSIZE[rip]
	mov	ecx, edi
	and	esi, eax
	not	ecx
	and	ecx, edx
	cmp	esi, 129
	je	.L7
	cmp	esi, 130
	je	.L8
	cmp	esi, 128
	je	.L31
	mov	ecx, edi
	add	r14d, 8
	or	ecx, edx
.L11:
	mov	edx, DWORD PTR UART_LCR_STOP[rip]
	test	DWORD PTR CSTOPB[rip], eax
	je	.L12
	or	ecx, edx
	add	r14d, 2
.L13:
	mov	edx, DWORD PTR UART_LCR[rip]
	mov	esi, ecx
	mov	rdi, r13
	mov	DWORD PTR 12[rsp], ecx
	call	tegra_uart_write@PLT
	mov	rax, QWORD PTR [rsp]
	xor	edx, edx
	mov	ecx, DWORD PTR 12[rsp]
	mov	DWORD PTR 8[r13], r14d
	mov	rsi, rbx
	mov	rdi, rbp
	div	r12
	mov	DWORD PTR 4[r13], ecx
	mov	rdx, r15
	mov	rcx, rax
	mov	rax, QWORD PTR [rsp]
	shr	rax, 4
	mov	r8, rax
	call	uart_get_baud_rate@PLT
	xor	esi, esi
	mov	rdi, rbp
	mov	r12d, eax
	call	spin_unlock_irqrestore@PLT
	mov	esi, r12d
	mov	rdi, r13
	call	tegra_set_baudrate@PLT
	test	eax, eax
	js	.L32
	mov	rdi, rbx
	call	tty_termios_baud_rate@PLT
	test	rax, rax
	jne	.L33
.L15:
	xor	esi, esi
	mov	rdi, rbp
	call	spin_lock_irqsave@PLT
	mov	eax, DWORD PTR [rbx]
	test	DWORD PTR CRTSCTS[rip], eax
	jne	.L34
	mov	esi, DWORD PTR TEGRA_UART_MCR_CTS_EN[rip]
	or	esi, DWORD PTR TEGRA_UART_MCR_RTS_EN[rip]
	mov	rdi, r13
	not	esi
	and	esi, DWORD PTR 12[r13]
	mov	edx, DWORD PTR UART_MCR[rip]
	mov	DWORD PTR 12[r13], esi
	call	tegra_uart_write@PLT
.L17:
	mov	esi, DWORD PTR [rbx]
	mov	edx, r12d
	mov	rdi, rbp
	call	uart_update_timeout@PLT
	mov	esi, DWORD PTR UART_IER[rip]
	mov	rdi, r13
	call	tegra_uart_read@PLT
	mov	edx, DWORD PTR UART_IER[rip]
	mov	esi, DWORD PTR 0[r13]
	mov	rdi, r13
	call	tegra_uart_write@PLT
	mov	esi, DWORD PTR UART_IER[rip]
	mov	rdi, r13
	call	tegra_uart_read@PLT
	mov	DWORD PTR 16[r13], 0
	mov	eax, DWORD PTR [rbx]
	test	DWORD PTR CREAD[rip], eax
	jne	.L18
	mov	eax, DWORD PTR UART_LSR_DR[rip]
	mov	DWORD PTR 16[r13], eax
.L18:
	mov	eax, DWORD PTR 4[rbx]
	test	DWORD PTR IGNBRK[rip], eax
	je	.L19
	mov	eax, DWORD PTR UART_LSR_BI[rip]
	or	DWORD PTR 16[r13], eax
.L19:
	add	rsp, 24
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	rdi, rbp
	xor	esi, esi
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	jmp	spin_unlock_irqrestore@PLT
	.p2align 4,,10
	.p2align 3
.L12:
	.cfi_restore_state
	not	edx
	add	r14d, 1
	and	ecx, edx
	jmp	.L13
	.p2align 4,,10
	.p2align 3
.L34:
	mov	eax, DWORD PTR TEGRA_UART_MCR_RTS_EN[rip]
	mov	esi, DWORD PTR 12[r13]
	mov	rdi, r13
	or	esi, DWORD PTR TEGRA_UART_MCR_CTS_EN[rip]
	mov	edx, DWORD PTR UART_MCR[rip]
	not	eax
	and	esi, eax
	mov	DWORD PTR 12[r13], esi
	call	tegra_uart_write@PLT
	cmp	QWORD PTR 24[r13], 0
	je	.L17
	mov	esi, 1
	mov	rdi, r13
	call	set_rts@PLT
	jmp	.L17
	.p2align 4,,10
	.p2align 3
.L33:
	mov	edx, r12d
	mov	esi, r12d
	mov	rdi, rbx
	call	tty_termios_encode_baud_rate@PLT
	jmp	.L15
	.p2align 4,,10
	.p2align 3
.L4:
	mov	esi, DWORD PTR UART_LCR_EPAR[rip]
	mov	edi, DWORD PTR UART_LCR_SPAR[rip]
	test	DWORD PTR PARODD[rip], eax
	je	.L6
	or	edx, ecx
	mov	ecx, esi
	mov	r14d, 2
	or	ecx, edi
	not	ecx
	and	edx, ecx
	jmp	.L5
	.p2align 4,,10
	.p2align 3
.L30:
	xor	esi, esi
	mov	rdi, r13
	call	set_rts@PLT
	jmp	.L3
	.p2align 4,,10
	.p2align 3
.L32:
	mov	edi, DWORD PTR 20[r13]
	add	rsp, 24
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	lea	rsi, .LC0[rip]
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	jmp	dev_err@PLT
	.p2align 4,,10
	.p2align 3
.L31:
	.cfi_restore_state
	or	ecx, DWORD PTR UART_LCR_WLEN7[rip]
	add	r14d, 7
	jmp	.L11
	.p2align 4,,10
	.p2align 3
.L8:
	or	ecx, DWORD PTR UART_LCR_WLEN5[rip]
	add	r14d, 5
	jmp	.L11
	.p2align 4,,10
	.p2align 3
.L7:
	or	ecx, DWORD PTR UART_LCR_WLEN6[rip]
	add	r14d, 6
	jmp	.L11
	.p2align 4,,10
	.p2align 3
.L6:
	or	edx, esi
	mov	r14d, 2
	or	ecx, edx
	mov	edx, edi
	not	edx
	and	edx, ecx
	jmp	.L5
	.cfi_endproc
.LFE0:
	.size	tegra_uart_set_termios, .-tegra_uart_set_termios
	.comm	UART_MCR,4,4
	.comm	UART_LSR_DR,4,4
	.comm	UART_LSR_BI,4,4
	.comm	UART_LCR_WLEN8,4,4
	.comm	UART_LCR_WLEN7,4,4
	.comm	UART_LCR_WLEN6,4,4
	.comm	UART_LCR_WLEN5,4,4
	.comm	UART_LCR_STOP,4,4
	.comm	UART_LCR_SPAR,4,4
	.comm	UART_LCR_PARITY,4,4
	.comm	UART_LCR_EPAR,4,4
	.comm	UART_LCR,4,4
	.comm	UART_IER_RDI,4,4
	.comm	UART_IER,4,4
	.comm	TEGRA_UART_MCR_RTS_EN,4,4
	.comm	TEGRA_UART_MCR_CTS_EN,4,4
	.comm	PARODD,4,4
	.comm	PARENB,4,4
	.comm	IGNBRK,4,4
	.comm	CSTOPB,4,4
	.comm	CSIZE,4,4
	.comm	CRTSCTS,4,4
	.comm	CREAD,4,4
	.comm	CMSPAR,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_serial-tegra.c_tegra_uart_set_termios.c"
	.text
	.global	__aeabi_uidiv
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"Failed to set baud rate\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	tegra_uart_set_termios, %function
tegra_uart_set_termios:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	sub	sp, sp, #20
	mov	r5, r1
	mov	r9, r2
	mov	r6, r0
	bl	to_tegra_uport
	mov	r4, r0
	ldr	r0, [r0, #32]
	bl	clk_get_parent
	bl	clk_get_rate
	ldr	r3, [r4, #28]
	mov	r8, r0
	ldr	r2, [r3]
	ldr	r3, .L41
	cmp	r2, #0
	mov	r0, r6
	mov	r1, #0
	ldr	r10, .L41+4
	moveq	r10, r3
	bl	spin_lock_irqsave
	ldr	r3, [r4, #24]
	cmp	r3, #0
	bne	.L36
.L3:
	ldr	r3, .L41+8
	ldr	r7, .L41+12
	ldr	r3, [r3]
	ldr	r1, [r4]
	ldr	r2, [r7]
	orr	r1, r1, r3
	mov	r0, r4
	bl	tegra_uart_write
	ldr	r1, [r7]
	mov	r0, r4
	bl	tegra_uart_read
	ldr	r2, [r7]
	mov	r1, #0
	mov	r0, r4
	bl	tegra_uart_write
	ldr	r1, [r7]
	mov	r0, r4
	bl	tegra_uart_read
	ldr	r3, .L41+16
	ldr	r1, .L41+20
	ldr	r2, [r3]
	ldr	r3, [r5]
	ldr	r1, [r1]
	bic	r3, r3, r2
	ldr	r2, .L41+24
	bics	r1, r1, r3
	ldr	r2, [r2]
	ldr	r1, [r4, #4]
	str	r3, [r5]
	beq	.L4
	mov	r0, #1
	bic	r1, r1, r2
.L5:
	ldr	r2, .L41+28
	ldr	ip, .L41+32
	ldr	r2, [r2]
	ldr	ip, [ip]
	and	r2, r2, r3
	cmp	r2, #129
	bic	fp, r1, ip
	beq	.L7
	cmp	r2, #130
	beq	.L8
	cmp	r2, #128
	orrne	fp, ip, r1
	addne	r0, r0, #8
	beq	.L37
.L11:
	ldr	r2, .L41+36
	ldr	r1, .L41+40
	ldr	r2, [r2]
	ldr	r1, [r1]
	tst	r3, r2
	ldr	r2, .L41+44
	orrne	fp, fp, r1
	biceq	fp, fp, r1
	addne	r3, r0, #2
	addeq	r3, r0, #1
	ldr	r2, [r2]
	mov	r1, fp
	mov	r0, r4
	str	r3, [sp, #12]
	bl	tegra_uart_write
	ldr	r3, [sp, #12]
	mov	r1, r10
	mov	r0, r8
	str	r3, [r4, #8]
	str	fp, [r4, #4]
	bl	__aeabi_uidiv
	lsr	r8, r8, #4
	mov	r3, r0
	mov	r2, r9
	mov	r1, r5
	str	r8, [sp]
	mov	r0, r6
	bl	uart_get_baud_rate
	mov	r8, r0
	mov	r1, #0
	mov	r0, r6
	bl	spin_unlock_irqrestore
	mov	r1, r8
	mov	r0, r4
	bl	tegra_set_baudrate
	cmp	r0, #0
	blt	.L38
	mov	r0, r5
	bl	tty_termios_baud_rate
	cmp	r0, #0
	bne	.L39
.L15:
	mov	r1, #0
	mov	r0, r6
	bl	spin_lock_irqsave
	ldr	r3, .L41+48
	ldr	r2, [r5]
	ldr	r3, [r3]
	tst	r2, r3
	ldr	r3, .L41+52
	ldr	r2, .L41+56
	ldr	r3, [r3]
	bne	.L40
	ldr	r2, [r2]
	ldr	r1, [r4, #12]
	orr	r3, r3, r2
	ldr	r2, .L41+60
	bic	r1, r1, r3
	mov	r0, r4
	ldr	r2, [r2]
	str	r1, [r4, #12]
	bl	tegra_uart_write
.L17:
	mov	r2, r8
	ldr	r1, [r5]
	mov	r0, r6
	bl	uart_update_timeout
	ldr	r1, [r7]
	mov	r0, r4
	bl	tegra_uart_read
	ldr	r2, [r7]
	ldr	r1, [r4]
	mov	r0, r4
	bl	tegra_uart_write
	ldr	r1, [r7]
	mov	r0, r4
	bl	tegra_uart_read
	mov	r1, #0
	ldr	r2, [r5]
	mov	r0, r6
	str	r1, [r4, #16]
	mov	r1, #0
	ldr	r3, .L41+64
	ldr	r3, [r3]
	tst	r2, r3
	ldreq	r3, .L41+68
	ldr	r2, [r5, #4]
	ldreq	r3, [r3]
	streq	r3, [r4, #16]
	ldr	r3, .L41+72
	ldr	r3, [r3]
	tst	r2, r3
	ldrne	r2, .L41+76
	ldrne	r3, [r4, #16]
	ldrne	r2, [r2]
	orrne	r3, r3, r2
	strne	r3, [r4, #16]
	add	sp, sp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	b	spin_unlock_irqrestore
.L40:
	ldr	r1, [r4, #12]
	ldr	r2, [r2]
	orr	r1, r1, r3
	ldr	r3, .L41+60
	bic	r1, r1, r2
	mov	r0, r4
	ldr	r2, [r3]
	str	r1, [r4, #12]
	bl	tegra_uart_write
	ldr	r3, [r4, #24]
	cmp	r3, #0
	beq	.L17
	mov	r1, #1
	mov	r0, r4
	bl	set_rts
	b	.L17
.L39:
	mov	r2, r8
	mov	r1, r8
	mov	r0, r5
	bl	tty_termios_encode_baud_rate
	b	.L15
.L4:
	ldr	r0, .L41+80
	ldr	ip, .L41+84
	ldr	lr, [r0]
	ldr	r0, .L41+88
	ldr	ip, [ip]
	tst	r3, lr
	ldr	fp, [r0]
	orreq	r2, r2, ip
	orrne	r1, r2, r1
	orrne	fp, ip, fp
	orreq	r1, r2, r1
	movne	r0, #2
	moveq	r0, #2
	bicne	r1, r1, fp
	biceq	r1, r1, fp
	b	.L5
.L36:
	mov	r1, #0
	mov	r0, r4
	bl	set_rts
	b	.L3
.L38:
	ldr	r0, [r4, #20]
	ldr	r1, .L41+92
	add	sp, sp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	b	dev_err
.L37:
	ldr	r2, .L41+96
	add	r0, r0, #7
	ldr	r1, [r2]
	orr	fp, fp, r1
	b	.L11
.L8:
	ldr	r2, .L41+100
	add	r0, r0, #5
	ldr	r1, [r2]
	orr	fp, fp, r1
	b	.L11
.L7:
	ldr	r2, .L41+104
	add	r0, r0, #6
	ldr	r1, [r2]
	orr	fp, fp, r1
	b	.L11
.L42:
	.align	2
.L41:
	.word	1048560
	.word	524272
	.word	UART_IER_RDI
	.word	UART_IER
	.word	CMSPAR
	.word	PARENB
	.word	UART_LCR_PARITY
	.word	CSIZE
	.word	UART_LCR_WLEN8
	.word	CSTOPB
	.word	UART_LCR_STOP
	.word	UART_LCR
	.word	CRTSCTS
	.word	TEGRA_UART_MCR_CTS_EN
	.word	TEGRA_UART_MCR_RTS_EN
	.word	UART_MCR
	.word	CREAD
	.word	UART_LSR_DR
	.word	IGNBRK
	.word	UART_LSR_BI
	.word	PARODD
	.word	UART_LCR_EPAR
	.word	UART_LCR_SPAR
	.word	.LC0
	.word	UART_LCR_WLEN7
	.word	UART_LCR_WLEN5
	.word	UART_LCR_WLEN6
	.size	tegra_uart_set_termios, .-tegra_uart_set_termios
	.comm	UART_MCR,4,4
	.comm	UART_LSR_DR,4,4
	.comm	UART_LSR_BI,4,4
	.comm	UART_LCR_WLEN8,4,4
	.comm	UART_LCR_WLEN7,4,4
	.comm	UART_LCR_WLEN6,4,4
	.comm	UART_LCR_WLEN5,4,4
	.comm	UART_LCR_STOP,4,4
	.comm	UART_LCR_SPAR,4,4
	.comm	UART_LCR_PARITY,4,4
	.comm	UART_LCR_EPAR,4,4
	.comm	UART_LCR,4,4
	.comm	UART_IER_RDI,4,4
	.comm	UART_IER,4,4
	.comm	TEGRA_UART_MCR_RTS_EN,4,4
	.comm	TEGRA_UART_MCR_CTS_EN,4,4
	.comm	PARODD,4,4
	.comm	PARENB,4,4
	.comm	IGNBRK,4,4
	.comm	CSTOPB,4,4
	.comm	CSIZE,4,4
	.comm	CRTSCTS,4,4
	.comm	CREAD,4,4
	.comm	CMSPAR,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
