	.file	"extr_intel_cdclk.c_vlv_set_cdclk.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC0:
	.string	"timed out waiting for CDclk change\n"
	.text
	.p2align 4
	.type	vlv_set_cdclk, @function
vlv_set_cdclk:
.LFB0:
	.cfi_startproc
	endbr64
	push	r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	push	r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	push	r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	push	rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	mov	r12d, DWORD PTR [rsi]
	cmp	r12d, 320000
	je	.L2
	jg	.L3
	cmp	r12d, 200000
	je	.L2
	cmp	r12d, 266667
	je	.L2
.L4:
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	edi, r12d
	pop	rbp
	.cfi_def_cfa_offset 32
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	jmp	MISSING_CASE@PLT
	.p2align 4,,10
	.p2align 3
.L3:
	.cfi_restore_state
	cmp	r12d, 333333
	je	.L2
	cmp	r12d, 400000
	jne	.L4
.L2:
	mov	r14d, DWORD PTR 4[rsi]
	mov	esi, DWORD PTR POWER_DOMAIN_DISPLAY_CORE[rip]
	mov	rdi, rbp
	call	intel_display_power_get@PLT
	mov	edi, DWORD PTR VLV_IOSF_SB_CCK[rip]
	mov	r13d, eax
	call	BIT@PLT
	mov	edi, DWORD PTR VLV_IOSF_SB_BUNIT[rip]
	mov	ebx, eax
	call	BIT@PLT
	mov	edi, DWORD PTR VLV_IOSF_SB_PUNIT[rip]
	or	ebx, eax
	call	BIT@PLT
	mov	rdi, rbp
	or	ebx, eax
	mov	esi, ebx
	call	vlv_iosf_sb_get@PLT
	mov	esi, DWORD PTR PUNIT_REG_DSPSSPM[rip]
	mov	rdi, rbp
	call	vlv_punit_read@PLT
	mov	ecx, DWORD PTR DSPFREQGUAR_SHIFT[rip]
	mov	edx, r14d
	mov	rdi, rbp
	mov	r8d, eax
	mov	eax, DWORD PTR DSPFREQGUAR_MASK[rip]
	mov	esi, DWORD PTR PUNIT_REG_DSPSSPM[rip]
	sal	edx, cl
	not	eax
	and	eax, r8d
	or	edx, eax
	call	vlv_punit_write@PLT
	mov	esi, DWORD PTR PUNIT_REG_DSPSSPM[rip]
	mov	rdi, rbp
	call	vlv_punit_read@PLT
	mov	ecx, DWORD PTR DSPFREQSTAT_SHIFT[rip]
	and	eax, DWORD PTR DSPFREQSTAT_MASK[rip]
	xor	edi, edi
	mov	esi, 50
	sal	r14d, cl
	cmp	eax, r14d
	sete	dil
	call	wait_for@PLT
	test	rax, rax
	jne	.L32
	cmp	r12d, 400000
	je	.L33
.L6:
	mov	esi, DWORD PTR BUNIT_REG_BISOC[rip]
	mov	rdi, rbp
	call	vlv_bunit_read@PLT
	and	eax, -128
	mov	edx, eax
	or	edx, 12
.L8:
	mov	esi, DWORD PTR BUNIT_REG_BISOC[rip]
	mov	rdi, rbp
	call	vlv_bunit_write@PLT
	mov	edi, DWORD PTR VLV_IOSF_SB_CCK[rip]
	call	BIT@PLT
	mov	edi, DWORD PTR VLV_IOSF_SB_BUNIT[rip]
	mov	r12d, eax
	call	BIT@PLT
	mov	edi, DWORD PTR VLV_IOSF_SB_PUNIT[rip]
	or	r12d, eax
	call	BIT@PLT
	mov	esi, r12d
	mov	rdi, rbp
	or	esi, eax
	call	vlv_iosf_sb_put@PLT
	mov	rdi, rbp
	call	intel_update_cdclk@PLT
	mov	rdi, rbp
	call	vlv_program_pfi_credits@PLT
	mov	esi, DWORD PTR POWER_DOMAIN_DISPLAY_CORE[rip]
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	edx, r13d
	mov	rdi, rbp
	pop	rbp
	.cfi_def_cfa_offset 32
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	jmp	intel_display_power_put@PLT
	.p2align 4,,10
	.p2align 3
.L32:
	.cfi_restore_state
	lea	rdi, .LC0[rip]
	call	DRM_ERROR@PLT
	cmp	r12d, 400000
	jne	.L6
.L33:
	mov	eax, DWORD PTR 0[rbp]
	mov	esi, 400000
	lea	edi, [rax+rax]
	call	DIV_ROUND_CLOSEST@PLT
	mov	esi, DWORD PTR CCK_DISPLAY_CLOCK_CONTROL[rip]
	mov	rdi, rbp
	lea	ebx, -1[rax]
	call	vlv_cck_read@PLT
	mov	esi, DWORD PTR CCK_DISPLAY_CLOCK_CONTROL[rip]
	mov	rdi, rbp
	mov	r8d, eax
	mov	eax, DWORD PTR CCK_FREQUENCY_VALUES[rip]
	not	eax
	and	eax, r8d
	or	eax, ebx
	mov	edx, eax
	call	vlv_cck_write@PLT
	mov	esi, DWORD PTR CCK_DISPLAY_CLOCK_CONTROL[rip]
	mov	rdi, rbp
	call	vlv_cck_read@PLT
	mov	ecx, DWORD PTR CCK_FREQUENCY_STATUS_SHIFT[rip]
	and	eax, DWORD PTR CCK_FREQUENCY_STATUS[rip]
	xor	edi, edi
	mov	esi, 50
	sal	ebx, cl
	cmp	eax, ebx
	sete	dil
	call	wait_for@PLT
	test	rax, rax
	jne	.L34
.L7:
	mov	esi, DWORD PTR BUNIT_REG_BISOC[rip]
	mov	rdi, rbp
	call	vlv_bunit_read@PLT
	and	eax, -128
	mov	edx, eax
	or	edx, 18
	jmp	.L8
	.p2align 4,,10
	.p2align 3
.L34:
	lea	rdi, .LC0[rip]
	call	DRM_ERROR@PLT
	jmp	.L7
	.cfi_endproc
.LFE0:
	.size	vlv_set_cdclk, .-vlv_set_cdclk
	.comm	VLV_IOSF_SB_PUNIT,4,4
	.comm	VLV_IOSF_SB_CCK,4,4
	.comm	VLV_IOSF_SB_BUNIT,4,4
	.comm	PUNIT_REG_DSPSSPM,4,4
	.comm	POWER_DOMAIN_DISPLAY_CORE,4,4
	.comm	DSPFREQSTAT_SHIFT,4,4
	.comm	DSPFREQSTAT_MASK,4,4
	.comm	DSPFREQGUAR_SHIFT,4,4
	.comm	DSPFREQGUAR_MASK,4,4
	.comm	CCK_FREQUENCY_VALUES,4,4
	.comm	CCK_FREQUENCY_STATUS_SHIFT,4,4
	.comm	CCK_FREQUENCY_STATUS,4,4
	.comm	CCK_DISPLAY_CLOCK_CONTROL,4,4
	.comm	BUNIT_REG_BISOC,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_intel_cdclk.c_vlv_set_cdclk.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"timed out waiting for CDclk change\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	vlv_set_cdclk, %function
vlv_set_cdclk:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r3, [r1]
	mov	r2, r1
	ldr	r1, .L20
	mov	r4, r0
	cmp	r3, r1
	sub	sp, sp, #12
	beq	.L2
	bgt	.L3
	ldr	r1, .L20+4
	cmp	r3, r1
	beq	.L2
	add	r1, r1, #66560
	add	r1, r1, #107
	cmp	r3, r1
	beq	.L2
.L4:
	mov	r0, r3
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	b	MISSING_CASE
.L3:
	ldr	r1, .L20+8
	cmp	r3, r1
	beq	.L2
	ldr	r1, .L20+12
	cmp	r3, r1
	bne	.L4
.L2:
	ldr	r7, .L20+16
	mov	r0, r4
	ldr	r1, [r7]
	str	r3, [sp, #4]
	ldr	fp, [r2, #4]
	bl	intel_display_power_get
	ldr	r10, .L20+20
	mov	r5, r0
	ldr	r0, [r10]
	bl	BIT
	ldr	r8, .L20+24
	mov	r6, r0
	ldr	r0, [r8]
	bl	BIT
	ldr	r9, .L20+28
	orr	r1, r6, r0
	ldr	r0, [r9]
	str	r1, [sp]
	bl	BIT
	ldr	r1, [sp]
	ldr	r6, .L20+32
	orr	r1, r1, r0
	mov	r0, r4
	bl	vlv_iosf_sb_get
	ldr	r1, [r6]
	mov	r0, r4
	bl	vlv_punit_read
	ldr	r1, .L20+36
	ldr	r2, .L20+40
	ldr	r1, [r1]
	ldr	r2, [r2]
	bic	r0, r0, r1
	orr	r2, r0, fp, lsl r2
	ldr	r1, [r6]
	mov	r0, r4
	bl	vlv_punit_write
	ldr	r1, [r6]
	mov	r0, r4
	bl	vlv_punit_read
	ldr	r1, .L20+44
	ldr	r2, .L20+48
	ldr	r1, [r1]
	ldr	r2, [r2]
	and	r0, r0, r1
	cmp	r0, fp, lsl r2
	moveq	r0, #1
	movne	r0, #0
	mov	r1, #50
	bl	wait_for
	cmp	r0, #0
	ldr	r3, [sp, #4]
	bne	.L17
	ldr	r2, .L20+12
	cmp	r3, r2
	beq	.L18
.L6:
	ldr	r6, .L20+52
	mov	r0, r4
	ldr	r1, [r6]
	bl	vlv_bunit_read
	bic	r2, r0, #127
	orr	r2, r2, #12
.L8:
	ldr	r1, [r6]
	mov	r0, r4
	bl	vlv_bunit_write
	ldr	r0, [r10]
	bl	BIT
	mov	r6, r0
	ldr	r0, [r8]
	bl	BIT
	mov	r1, r0
	ldr	r0, [r9]
	orr	r6, r6, r1
	bl	BIT
	mov	r1, r0
	mov	r0, r4
	orr	r1, r6, r1
	bl	vlv_iosf_sb_put
	mov	r0, r4
	bl	intel_update_cdclk
	mov	r0, r4
	bl	vlv_program_pfi_credits
	mov	r2, r5
	mov	r0, r4
	ldr	r1, [r7]
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	b	intel_display_power_put
.L17:
	ldr	r0, .L20+56
	str	r3, [sp]
	bl	DRM_ERROR
	ldr	r3, [sp]
	ldr	r2, .L20+12
	cmp	r3, r2
	bne	.L6
.L18:
	ldr	r0, [r4]
	mov	r1, r3
	lsl	r0, r0, #1
	bl	DIV_ROUND_CLOSEST
	ldr	fp, .L20+60
	mov	r6, r0
	ldr	r1, [fp]
	mov	r0, r4
	bl	vlv_cck_read
	mov	r2, r0
	ldr	r3, .L20+64
	sub	r6, r6, #1
	ldr	r3, [r3]
	ldr	r1, [fp]
	bic	r2, r2, r3
	orr	r2, r6, r2
	mov	r0, r4
	bl	vlv_cck_write
	ldr	r1, [fp]
	mov	r0, r4
	bl	vlv_cck_read
	ldr	r2, .L20+68
	ldr	r3, .L20+72
	ldr	r2, [r2]
	ldr	r3, [r3]
	and	r0, r0, r2
	cmp	r0, r6, lsl r3
	moveq	r0, #1
	movne	r0, #0
	mov	r1, #50
	bl	wait_for
	cmp	r0, #0
	bne	.L19
.L7:
	ldr	r6, .L20+52
	mov	r0, r4
	ldr	r1, [r6]
	bl	vlv_bunit_read
	bic	r2, r0, #127
	orr	r2, r2, #18
	b	.L8
.L19:
	ldr	r0, .L20+56
	bl	DRM_ERROR
	b	.L7
.L21:
	.align	2
.L20:
	.word	320000
	.word	200000
	.word	333333
	.word	400000
	.word	POWER_DOMAIN_DISPLAY_CORE
	.word	VLV_IOSF_SB_CCK
	.word	VLV_IOSF_SB_BUNIT
	.word	VLV_IOSF_SB_PUNIT
	.word	PUNIT_REG_DSPSSPM
	.word	DSPFREQGUAR_MASK
	.word	DSPFREQGUAR_SHIFT
	.word	DSPFREQSTAT_MASK
	.word	DSPFREQSTAT_SHIFT
	.word	BUNIT_REG_BISOC
	.word	.LC0
	.word	CCK_DISPLAY_CLOCK_CONTROL
	.word	CCK_FREQUENCY_VALUES
	.word	CCK_FREQUENCY_STATUS
	.word	CCK_FREQUENCY_STATUS_SHIFT
	.size	vlv_set_cdclk, .-vlv_set_cdclk
	.comm	VLV_IOSF_SB_PUNIT,4,4
	.comm	VLV_IOSF_SB_CCK,4,4
	.comm	VLV_IOSF_SB_BUNIT,4,4
	.comm	PUNIT_REG_DSPSSPM,4,4
	.comm	POWER_DOMAIN_DISPLAY_CORE,4,4
	.comm	DSPFREQSTAT_SHIFT,4,4
	.comm	DSPFREQSTAT_MASK,4,4
	.comm	DSPFREQGUAR_SHIFT,4,4
	.comm	DSPFREQGUAR_MASK,4,4
	.comm	CCK_FREQUENCY_VALUES,4,4
	.comm	CCK_FREQUENCY_STATUS_SHIFT,4,4
	.comm	CCK_FREQUENCY_STATUS,4,4
	.comm	CCK_DISPLAY_CLOCK_CONTROL,4,4
	.comm	BUNIT_REG_BISOC,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
