	.file	"extr_bootloader_random.c_bootloader_random_enable.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	bootloader_random_enable
	.type	bootloader_random_enable, @function
bootloader_random_enable:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	push	rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	mov	edi, DWORD PTR PERIPH_RNG_MODULE[rip]
	call	periph_module_enable@PLT
	mov	ecx, DWORD PTR RTC_CNTL_DTEST_RTC_S[rip]
	mov	esi, DWORD PTR RTC_CNTL_DTEST_RTC[rip]
	mov	edx, 2
	mov	edi, DWORD PTR RTC_CNTL_TEST_MUX_REG[rip]
	call	SET_PERI_REG_BITS@PLT
	mov	esi, DWORD PTR RTC_CNTL_ENT_RTC[rip]
	mov	edi, DWORD PTR RTC_CNTL_TEST_MUX_REG[rip]
	call	SET_PERI_REG_MASK@PLT
	mov	edi, DWORD PTR SYSCON_SARADC_SAR2_PATT_TAB1_REG[rip]
	mov	esi, -1381126739
	call	WRITE_PERI_REG@PLT
	mov	edi, DWORD PTR SYSCON_SARADC_SAR2_PATT_TAB2_REG[rip]
	mov	esi, -1381126739
	call	WRITE_PERI_REG@PLT
	mov	edi, DWORD PTR SYSCON_SARADC_SAR2_PATT_TAB3_REG[rip]
	mov	esi, -1381126739
	call	WRITE_PERI_REG@PLT
	mov	edi, DWORD PTR SYSCON_SARADC_SAR2_PATT_TAB4_REG[rip]
	mov	esi, -1381126739
	call	WRITE_PERI_REG@PLT
	mov	ecx, DWORD PTR SYSCON_SARADC_SAR_CLK_DIV_S[rip]
	mov	esi, DWORD PTR SYSCON_SARADC_SAR_CLK_DIV[rip]
	mov	edx, 4
	mov	edi, DWORD PTR SYSCON_SARADC_CTRL_REG[rip]
	call	SET_PERI_REG_BITS@PLT
	mov	ecx, DWORD PTR SYSCON_SARADC_RSTB_WAIT_S[rip]
	mov	esi, DWORD PTR SYSCON_SARADC_RSTB_WAIT[rip]
	mov	edx, 8
	mov	edi, DWORD PTR SYSCON_SARADC_FSM_REG[rip]
	call	SET_PERI_REG_BITS@PLT
	mov	ecx, DWORD PTR SYSCON_SARADC_WORK_MODE_S[rip]
	mov	esi, DWORD PTR SYSCON_SARADC_WORK_MODE[rip]
	xor	edx, edx
	mov	edi, DWORD PTR SYSCON_SARADC_CTRL_REG[rip]
	call	SET_PERI_REG_BITS@PLT
	mov	esi, DWORD PTR SYSCON_SARADC_SAR_SEL[rip]
	mov	edi, DWORD PTR SYSCON_SARADC_CTRL_REG[rip]
	call	SET_PERI_REG_MASK@PLT
	mov	esi, DWORD PTR SYSCON_SARADC_DATA_SAR_SEL[rip]
	mov	edi, DWORD PTR SYSCON_SARADC_CTRL_REG[rip]
	call	CLEAR_PERI_REG_MASK@PLT
	mov	r12d, DWORD PTR I2S_RX_BCK_DIV_NUM_S[rip]
	mov	ebp, DWORD PTR I2S_RX_BCK_DIV_NUM[rip]
	xor	edi, edi
	call	I2S_SAMPLE_RATE_CONF_REG@PLT
	mov	edx, 20
	mov	ecx, r12d
	mov	esi, ebp
	mov	edi, eax
	call	SET_PERI_REG_BITS@PLT
	mov	esi, DWORD PTR SYSCON_SARADC_DATA_TO_I2S[rip]
	mov	edi, DWORD PTR SYSCON_SARADC_CTRL_REG[rip]
	call	SET_PERI_REG_MASK@PLT
	mov	ebp, DWORD PTR I2S_CAMERA_EN[rip]
	xor	edi, edi
	call	I2S_CONF2_REG@PLT
	mov	edi, eax
	mov	esi, ebp
	call	CLEAR_PERI_REG_MASK@PLT
	mov	ebp, DWORD PTR I2S_LCD_EN[rip]
	xor	edi, edi
	call	I2S_CONF2_REG@PLT
	mov	edi, eax
	mov	esi, ebp
	call	SET_PERI_REG_MASK@PLT
	mov	ebp, DWORD PTR I2S_DATA_ENABLE[rip]
	xor	edi, edi
	call	I2S_CONF2_REG@PLT
	mov	edi, eax
	mov	esi, ebp
	call	SET_PERI_REG_MASK@PLT
	mov	ebp, DWORD PTR I2S_DATA_ENABLE_TEST_EN[rip]
	xor	edi, edi
	call	I2S_CONF2_REG@PLT
	mov	edi, eax
	mov	esi, ebp
	call	SET_PERI_REG_MASK@PLT
	mov	ebp, DWORD PTR I2S_RX_START[rip]
	xor	edi, edi
	call	I2S_CONF_REG@PLT
	add	rsp, 8
	.cfi_def_cfa_offset 24
	mov	esi, ebp
	mov	edi, eax
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	jmp	SET_PERI_REG_MASK@PLT
	.cfi_endproc
.LFE0:
	.size	bootloader_random_enable, .-bootloader_random_enable
	.comm	SYSCON_SARADC_WORK_MODE_S,4,4
	.comm	SYSCON_SARADC_WORK_MODE,4,4
	.comm	SYSCON_SARADC_START_WAIT_S,4,4
	.comm	SYSCON_SARADC_START_WAIT,4,4
	.comm	SYSCON_SARADC_SAR_SEL,4,4
	.comm	SYSCON_SARADC_SAR_CLK_DIV_S,4,4
	.comm	SYSCON_SARADC_SAR_CLK_DIV,4,4
	.comm	SYSCON_SARADC_SAR2_PATT_TAB4_REG,4,4
	.comm	SYSCON_SARADC_SAR2_PATT_TAB3_REG,4,4
	.comm	SYSCON_SARADC_SAR2_PATT_TAB2_REG,4,4
	.comm	SYSCON_SARADC_SAR2_PATT_TAB1_REG,4,4
	.comm	SYSCON_SARADC_SAR2_MUX,4,4
	.comm	SYSCON_SARADC_RSTB_WAIT_S,4,4
	.comm	SYSCON_SARADC_RSTB_WAIT,4,4
	.comm	SYSCON_SARADC_FSM_REG,4,4
	.comm	SYSCON_SARADC_DATA_TO_I2S,4,4
	.comm	SYSCON_SARADC_DATA_SAR_SEL,4,4
	.comm	SYSCON_SARADC_CTRL_REG,4,4
	.comm	SENS_ULP_CP_START_TOP,4,4
	.comm	SENS_ULP_CP_FORCE_START_TOP,4,4
	.comm	SENS_SAR_START_FORCE_REG,4,4
	.comm	SENS_SAR_READ_CTRL_REG,4,4
	.comm	SENS_SAR_READ_CTRL2_REG,4,4
	.comm	SENS_SAR_POWER_XPD_SAR_REG,4,4
	.comm	SENS_SAR_MEAS_WAIT2_REG,4,4
	.comm	SENS_SAR_MEAS2_CTRL1_REG,4,4
	.comm	SENS_SAR_MEAS1_MUX_REG,4,4
	.comm	SENS_SAR2_EN_TEST,4,4
	.comm	SENS_SAR2_DIG_FORCE,4,4
	.comm	SENS_SAR1_DIG_FORCE,4,4
	.comm	SENS_FORCE_XPD_SAR_S,4,4
	.comm	SENS_FORCE_XPD_SAR,4,4
	.comm	RTC_CNTL_ULP_CP_START_TOP,4,4
	.comm	RTC_CNTL_ULP_CP_FORCE_START_TOP,4,4
	.comm	RTC_CNTL_ULP_CP_CTRL_REG,4,4
	.comm	RTC_CNTL_TEST_MUX_REG,4,4
	.comm	RTC_CNTL_ENT_RTC,4,4
	.comm	RTC_CNTL_DTEST_RTC_S,4,4
	.comm	RTC_CNTL_DTEST_RTC,4,4
	.comm	PERIPH_RNG_MODULE,4,4
	.comm	PERIPH_I2S0_MODULE,4,4
	.comm	I2S_RX_START,4,4
	.comm	I2S_RX_BCK_DIV_NUM_S,4,4
	.comm	I2S_RX_BCK_DIV_NUM,4,4
	.comm	I2S_LCD_EN,4,4
	.comm	I2S_DATA_ENABLE_TEST_EN,4,4
	.comm	I2S_DATA_ENABLE,4,4
	.comm	I2S_CAMERA_EN,4,4
	.comm	DPORT_WIFI_CLK_RNG_EN,4,4
	.comm	DPORT_WIFI_CLK_EN_REG,4,4
	.comm	DPORT_PERIP_CLK_EN_REG,4,4
	.comm	DPORT_I2S0_CLK_EN,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_bootloader_random.c_bootloader_random_enable.c"
	.text
	.align	2
	.global	bootloader_random_enable
	.syntax unified
	.arm
	.fpu softvfp
	.type	bootloader_random_enable, %function
bootloader_random_enable:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	ldr	r3, .L4
	push	{r4, lr}
	ldr	r0, [r3]
	bl	periph_module_enable
	ldr	r4, .L4+4
	ldr	r2, .L4+8
	ldr	r3, .L4+12
	ldr	r1, [r2]
	ldr	r3, [r3]
	mov	r2, #2
	ldr	r0, [r4]
	bl	SET_PERI_REG_BITS
	ldr	r3, .L4+16
	ldr	r0, [r4]
	ldr	r1, [r3]
	bl	SET_PERI_REG_MASK
	ldr	r4, .L4+20
	ldr	r3, .L4+24
	mov	r1, r4
	ldr	r0, [r3]
	bl	WRITE_PERI_REG
	ldr	r3, .L4+28
	mov	r1, r4
	ldr	r0, [r3]
	bl	WRITE_PERI_REG
	ldr	r3, .L4+32
	mov	r1, r4
	ldr	r0, [r3]
	bl	WRITE_PERI_REG
	ldr	r3, .L4+36
	mov	r1, r4
	ldr	r0, [r3]
	bl	WRITE_PERI_REG
	ldr	r4, .L4+40
	ldr	r2, .L4+44
	ldr	r3, .L4+48
	ldr	r1, [r2]
	ldr	r3, [r3]
	mov	r2, #4
	ldr	r0, [r4]
	bl	SET_PERI_REG_BITS
	ldr	r2, .L4+52
	ldr	r3, .L4+56
	ldr	r1, .L4+60
	ldr	r3, [r3]
	ldr	r1, [r1]
	ldr	r0, [r2]
	mov	r2, #8
	bl	SET_PERI_REG_BITS
	ldr	r2, .L4+64
	ldr	r3, .L4+68
	ldr	r1, [r2]
	ldr	r0, [r4]
	mov	r2, #0
	ldr	r3, [r3]
	bl	SET_PERI_REG_BITS
	ldr	r3, .L4+72
	ldr	r0, [r4]
	ldr	r1, [r3]
	bl	SET_PERI_REG_MASK
	ldr	r3, .L4+76
	ldr	r0, [r4]
	ldr	r1, [r3]
	bl	CLEAR_PERI_REG_MASK
	mov	r0, #0
	bl	I2S_SAMPLE_RATE_CONF_REG
	ldr	r2, .L4+80
	ldr	r3, .L4+84
	ldr	r1, [r2]
	ldr	r3, [r3]
	mov	r2, #20
	bl	SET_PERI_REG_BITS
	ldr	r3, .L4+88
	ldr	r0, [r4]
	ldr	r1, [r3]
	bl	SET_PERI_REG_MASK
	mov	r0, #0
	bl	I2S_CONF2_REG
	ldr	r3, .L4+92
	ldr	r1, [r3]
	bl	CLEAR_PERI_REG_MASK
	mov	r0, #0
	bl	I2S_CONF2_REG
	ldr	r3, .L4+96
	ldr	r1, [r3]
	bl	SET_PERI_REG_MASK
	mov	r0, #0
	bl	I2S_CONF2_REG
	ldr	r3, .L4+100
	ldr	r1, [r3]
	bl	SET_PERI_REG_MASK
	mov	r0, #0
	bl	I2S_CONF2_REG
	ldr	r3, .L4+104
	ldr	r1, [r3]
	bl	SET_PERI_REG_MASK
	mov	r0, #0
	bl	I2S_CONF_REG
	pop	{r4, lr}
	ldr	r3, .L4+108
	ldr	r1, [r3]
	b	SET_PERI_REG_MASK
.L5:
	.align	2
.L4:
	.word	PERIPH_RNG_MODULE
	.word	RTC_CNTL_TEST_MUX_REG
	.word	RTC_CNTL_DTEST_RTC
	.word	RTC_CNTL_DTEST_RTC_S
	.word	RTC_CNTL_ENT_RTC
	.word	-1381126739
	.word	SYSCON_SARADC_SAR2_PATT_TAB1_REG
	.word	SYSCON_SARADC_SAR2_PATT_TAB2_REG
	.word	SYSCON_SARADC_SAR2_PATT_TAB3_REG
	.word	SYSCON_SARADC_SAR2_PATT_TAB4_REG
	.word	SYSCON_SARADC_CTRL_REG
	.word	SYSCON_SARADC_SAR_CLK_DIV
	.word	SYSCON_SARADC_SAR_CLK_DIV_S
	.word	SYSCON_SARADC_FSM_REG
	.word	SYSCON_SARADC_RSTB_WAIT_S
	.word	SYSCON_SARADC_RSTB_WAIT
	.word	SYSCON_SARADC_WORK_MODE
	.word	SYSCON_SARADC_WORK_MODE_S
	.word	SYSCON_SARADC_SAR_SEL
	.word	SYSCON_SARADC_DATA_SAR_SEL
	.word	I2S_RX_BCK_DIV_NUM
	.word	I2S_RX_BCK_DIV_NUM_S
	.word	SYSCON_SARADC_DATA_TO_I2S
	.word	I2S_CAMERA_EN
	.word	I2S_LCD_EN
	.word	I2S_DATA_ENABLE
	.word	I2S_DATA_ENABLE_TEST_EN
	.word	I2S_RX_START
	.size	bootloader_random_enable, .-bootloader_random_enable
	.comm	SYSCON_SARADC_WORK_MODE_S,4,4
	.comm	SYSCON_SARADC_WORK_MODE,4,4
	.comm	SYSCON_SARADC_START_WAIT_S,4,4
	.comm	SYSCON_SARADC_START_WAIT,4,4
	.comm	SYSCON_SARADC_SAR_SEL,4,4
	.comm	SYSCON_SARADC_SAR_CLK_DIV_S,4,4
	.comm	SYSCON_SARADC_SAR_CLK_DIV,4,4
	.comm	SYSCON_SARADC_SAR2_PATT_TAB4_REG,4,4
	.comm	SYSCON_SARADC_SAR2_PATT_TAB3_REG,4,4
	.comm	SYSCON_SARADC_SAR2_PATT_TAB2_REG,4,4
	.comm	SYSCON_SARADC_SAR2_PATT_TAB1_REG,4,4
	.comm	SYSCON_SARADC_SAR2_MUX,4,4
	.comm	SYSCON_SARADC_RSTB_WAIT_S,4,4
	.comm	SYSCON_SARADC_RSTB_WAIT,4,4
	.comm	SYSCON_SARADC_FSM_REG,4,4
	.comm	SYSCON_SARADC_DATA_TO_I2S,4,4
	.comm	SYSCON_SARADC_DATA_SAR_SEL,4,4
	.comm	SYSCON_SARADC_CTRL_REG,4,4
	.comm	SENS_ULP_CP_START_TOP,4,4
	.comm	SENS_ULP_CP_FORCE_START_TOP,4,4
	.comm	SENS_SAR_START_FORCE_REG,4,4
	.comm	SENS_SAR_READ_CTRL_REG,4,4
	.comm	SENS_SAR_READ_CTRL2_REG,4,4
	.comm	SENS_SAR_POWER_XPD_SAR_REG,4,4
	.comm	SENS_SAR_MEAS_WAIT2_REG,4,4
	.comm	SENS_SAR_MEAS2_CTRL1_REG,4,4
	.comm	SENS_SAR_MEAS1_MUX_REG,4,4
	.comm	SENS_SAR2_EN_TEST,4,4
	.comm	SENS_SAR2_DIG_FORCE,4,4
	.comm	SENS_SAR1_DIG_FORCE,4,4
	.comm	SENS_FORCE_XPD_SAR_S,4,4
	.comm	SENS_FORCE_XPD_SAR,4,4
	.comm	RTC_CNTL_ULP_CP_START_TOP,4,4
	.comm	RTC_CNTL_ULP_CP_FORCE_START_TOP,4,4
	.comm	RTC_CNTL_ULP_CP_CTRL_REG,4,4
	.comm	RTC_CNTL_TEST_MUX_REG,4,4
	.comm	RTC_CNTL_ENT_RTC,4,4
	.comm	RTC_CNTL_DTEST_RTC_S,4,4
	.comm	RTC_CNTL_DTEST_RTC,4,4
	.comm	PERIPH_RNG_MODULE,4,4
	.comm	PERIPH_I2S0_MODULE,4,4
	.comm	I2S_RX_START,4,4
	.comm	I2S_RX_BCK_DIV_NUM_S,4,4
	.comm	I2S_RX_BCK_DIV_NUM,4,4
	.comm	I2S_LCD_EN,4,4
	.comm	I2S_DATA_ENABLE_TEST_EN,4,4
	.comm	I2S_DATA_ENABLE,4,4
	.comm	I2S_CAMERA_EN,4,4
	.comm	DPORT_WIFI_CLK_RNG_EN,4,4
	.comm	DPORT_WIFI_CLK_EN_REG,4,4
	.comm	DPORT_PERIP_CLK_EN_REG,4,4
	.comm	DPORT_I2S0_CLK_EN,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
