	.file	"extr_i40e_main.c_i40e_handle_mdd_event.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC0:
	.string	"Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n"
	.align 8
.LC1:
	.string	"Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n"
	.align 8
.LC2:
	.string	"TX driver issue detected on PF\n"
	.align 8
.LC3:
	.string	"RX driver issue detected on PF\n"
	.align 8
.LC4:
	.string	"TX driver issue detected on VF %d\n"
	.align 8
.LC5:
	.string	"Use PF Control I/F to re-enable the VF\n"
	.align 8
.LC6:
	.string	"RX driver issue detected on VF %d\n"
	.text
	.p2align 4
	.type	i40e_handle_mdd_event, @function
i40e_handle_mdd_event:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	rbx, rdi
	sub	rsp, 40
	.cfi_def_cfa_offset 96
	mov	esi, DWORD PTR 4[rdi]
	mov	edi, DWORD PTR __I40E_MDD_EVENT_PENDING[rip]
	call	test_bit@PLT
	test	eax, eax
	jne	.L38
	add	rsp, 40
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L38:
	.cfi_restore_state
	mov	esi, DWORD PTR I40E_GL_MDET_TX[rip]
	lea	rbp, 24[rbx]
	mov	rdi, rbp
	call	rd32@PLT
	mov	r13d, eax
	test	DWORD PTR I40E_GL_MDET_TX_VALID_MASK[rip], eax
	jne	.L39
	mov	esi, DWORD PTR I40E_GL_MDET_RX[rip]
	mov	rdi, rbp
	call	rd32@PLT
	mov	r13d, eax
	test	DWORD PTR I40E_GL_MDET_RX_VALID_MASK[rip], eax
	je	.L9
.L13:
	mov	eax, DWORD PTR I40E_GL_MDET_RX_FUNCTION_SHIFT[rip]
	mov	rdi, rbx
	mov	r15d, DWORD PTR 24[rbx]
	mov	r14d, DWORD PTR I40E_GL_MDET_RX_FUNCTION_MASK[rip]
	mov	r12d, DWORD PTR I40E_GL_MDET_RX_QUEUE_MASK[rip]
	mov	DWORD PTR 8[rsp], eax
	mov	eax, DWORD PTR I40E_GL_MDET_RX_EVENT_MASK[rip]
	mov	DWORD PTR 12[rsp], eax
	mov	eax, DWORD PTR I40E_GL_MDET_RX_EVENT_SHIFT[rip]
	mov	DWORD PTR 16[rsp], eax
	mov	eax, DWORD PTR I40E_GL_MDET_RX_QUEUE_SHIFT[rip]
	mov	DWORD PTR 20[rsp], eax
	call	netif_msg_rx_err@PLT
	test	rax, rax
	jne	.L40
.L6:
	mov	esi, DWORD PTR I40E_GL_MDET_RX[rip]
	mov	edx, -1
	mov	rdi, rbp
	call	wr32@PLT
.L5:
	mov	esi, DWORD PTR I40E_PF_MDET_TX[rip]
	mov	rdi, rbp
	call	rd32@PLT
	test	DWORD PTR I40E_PF_MDET_TX_VALID_MASK[rip], eax
	jne	.L41
.L7:
	mov	esi, DWORD PTR I40E_PF_MDET_RX[rip]
	mov	rdi, rbp
	call	rd32@PLT
	test	DWORD PTR I40E_PF_MDET_RX_VALID_MASK[rip], eax
	jne	.L42
.L8:
	mov	eax, DWORD PTR [rbx]
	test	eax, eax
	jle	.L9
	xor	r12d, r12d
	lea	r15, .LC4[rip]
	jmp	.L12
	.p2align 4,,10
	.p2align 3
.L10:
	mov	edi, r14d
	call	I40E_VP_MDET_RX@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	rd32@PLT
	test	DWORD PTR I40E_VP_MDET_RX_VALID_MASK[rip], eax
	jne	.L43
.L11:
	add	r12, 1
	cmp	DWORD PTR [rbx], r12d
	jle	.L9
.L12:
	mov	rax, QWORD PTR 16[rbx]
	mov	edi, r12d
	mov	r14d, r12d
	lea	r13, [rax+r12*8]
	call	I40E_VP_MDET_TX@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	rd32@PLT
	test	DWORD PTR I40E_VP_MDET_TX_VALID_MASK[rip], eax
	je	.L10
	mov	edi, r12d
	call	I40E_VP_MDET_TX@PLT
	mov	rdi, rbp
	mov	edx, 65535
	mov	esi, eax
	call	wr32@PLT
	add	DWORD PTR 4[r13], 1
	mov	rdi, QWORD PTR 8[rbx]
	xor	eax, eax
	mov	edx, r12d
	mov	rsi, r15
	call	dev_info@PLT
	mov	rdi, QWORD PTR 8[rbx]
	lea	rsi, .LC5[rip]
	xor	eax, eax
	call	dev_info@PLT
	mov	edi, DWORD PTR I40E_VF_STATE_DISABLED[rip]
	mov	rsi, r13
	call	set_bit@PLT
	jmp	.L10
	.p2align 4,,10
	.p2align 3
.L9:
	mov	esi, DWORD PTR 4[rbx]
	mov	edi, DWORD PTR __I40E_MDD_EVENT_PENDING[rip]
	call	clear_bit@PLT
	mov	esi, DWORD PTR I40E_PFINT_ICR0_ENA[rip]
	mov	rdi, rbp
	call	rd32@PLT
	mov	esi, DWORD PTR I40E_PFINT_ICR0_ENA[rip]
	or	eax, DWORD PTR I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK[rip]
	mov	rdi, rbp
	mov	edx, eax
	call	wr32@PLT
	add	rsp, 40
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	rdi, rbp
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	jmp	i40e_flush@PLT
	.p2align 4,,10
	.p2align 3
.L43:
	.cfi_restore_state
	mov	edi, r14d
	call	I40E_VP_MDET_RX@PLT
	mov	rdi, rbp
	mov	edx, 65535
	mov	esi, eax
	call	wr32@PLT
	add	DWORD PTR 4[r13], 1
	mov	rdi, QWORD PTR 8[rbx]
	xor	eax, eax
	mov	edx, r14d
	lea	rsi, .LC6[rip]
	call	dev_info@PLT
	mov	rdi, QWORD PTR 8[rbx]
	lea	rsi, .LC5[rip]
	xor	eax, eax
	call	dev_info@PLT
	mov	edi, DWORD PTR I40E_VF_STATE_DISABLED[rip]
	mov	rsi, r13
	call	set_bit@PLT
	jmp	.L11
	.p2align 4,,10
	.p2align 3
.L39:
	mov	eax, DWORD PTR I40E_GL_MDET_TX_PF_NUM_MASK[rip]
	mov	rdi, rbx
	mov	r15d, DWORD PTR 24[rbx]
	mov	r14d, DWORD PTR I40E_GL_MDET_TX_VF_NUM_MASK[rip]
	mov	r12d, DWORD PTR I40E_GL_MDET_TX_QUEUE_MASK[rip]
	mov	DWORD PTR 8[rsp], eax
	mov	eax, DWORD PTR I40E_GL_MDET_TX_PF_NUM_SHIFT[rip]
	mov	DWORD PTR 12[rsp], eax
	mov	eax, DWORD PTR I40E_GL_MDET_TX_VF_NUM_SHIFT[rip]
	mov	DWORD PTR 16[rsp], eax
	mov	eax, DWORD PTR I40E_GL_MDET_TX_EVENT_MASK[rip]
	mov	DWORD PTR 20[rsp], eax
	mov	eax, DWORD PTR I40E_GL_MDET_TX_EVENT_SHIFT[rip]
	mov	DWORD PTR 24[rsp], eax
	mov	eax, DWORD PTR I40E_GL_MDET_TX_QUEUE_SHIFT[rip]
	mov	DWORD PTR 28[rsp], eax
	call	netif_msg_tx_err@PLT
	test	rax, rax
	jne	.L44
.L4:
	mov	esi, DWORD PTR I40E_GL_MDET_TX[rip]
	mov	edx, -1
	mov	rdi, rbp
	call	wr32@PLT
	mov	esi, DWORD PTR I40E_GL_MDET_RX[rip]
	mov	rdi, rbp
	call	rd32@PLT
	mov	r13d, eax
	test	DWORD PTR I40E_GL_MDET_RX_VALID_MASK[rip], eax
	je	.L5
	jmp	.L13
	.p2align 4,,10
	.p2align 3
.L42:
	mov	esi, DWORD PTR I40E_PF_MDET_RX[rip]
	mov	rdi, rbp
	mov	edx, 65535
	call	wr32@PLT
	mov	rdi, QWORD PTR 8[rbx]
	lea	rsi, .LC3[rip]
	call	dev_dbg@PLT
	jmp	.L8
	.p2align 4,,10
	.p2align 3
.L41:
	mov	esi, DWORD PTR I40E_PF_MDET_TX[rip]
	mov	rdi, rbp
	mov	edx, 65535
	call	wr32@PLT
	mov	rdi, QWORD PTR 8[rbx]
	lea	rsi, .LC2[rip]
	call	dev_dbg@PLT
	jmp	.L7
	.p2align 4,,10
	.p2align 3
.L44:
	movzx	ecx, BYTE PTR 28[rsp]
	mov	edx, DWORD PTR 20[rsp]
	and	r12d, r13d
	mov	r9d, r14d
	mov	r8d, DWORD PTR 8[rsp]
	and	r9d, r13d
	mov	rdi, QWORD PTR 8[rbx]
	xor	eax, eax
	sar	r12d, cl
	movzx	ecx, BYTE PTR 24[rsp]
	and	edx, r13d
	lea	rsi, .LC0[rip]
	and	r8d, r13d
	sub	r12d, r15d
	sar	edx, cl
	movzx	ecx, BYTE PTR 16[rsp]
	sar	r9d, cl
	movzx	ecx, BYTE PTR 12[rsp]
	sar	r8d, cl
	mov	ecx, r12d
	call	dev_info@PLT
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L40:
	movzx	ecx, BYTE PTR 20[rsp]
	mov	edx, DWORD PTR 12[rsp]
	and	r12d, r13d
	mov	r8d, r14d
	and	r8d, r13d
	mov	rdi, QWORD PTR 8[rbx]
	lea	rsi, .LC1[rip]
	xor	eax, eax
	sar	r12d, cl
	movzx	ecx, BYTE PTR 16[rsp]
	and	edx, r13d
	sub	r12d, r15d
	sar	edx, cl
	movzx	ecx, BYTE PTR 8[rsp]
	sar	r8d, cl
	mov	ecx, r12d
	call	dev_info@PLT
	jmp	.L6
	.cfi_endproc
.LFE0:
	.size	i40e_handle_mdd_event, .-i40e_handle_mdd_event
	.comm	__I40E_MDD_EVENT_PENDING,4,4
	.comm	I40E_VP_MDET_TX_VALID_MASK,4,4
	.comm	I40E_VP_MDET_RX_VALID_MASK,4,4
	.comm	I40E_VF_STATE_DISABLED,4,4
	.comm	I40E_PF_MDET_TX_VALID_MASK,4,4
	.comm	I40E_PF_MDET_TX,4,4
	.comm	I40E_PF_MDET_RX_VALID_MASK,4,4
	.comm	I40E_PF_MDET_RX,4,4
	.comm	I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK,4,4
	.comm	I40E_PFINT_ICR0_ENA,4,4
	.comm	I40E_GL_MDET_TX_VF_NUM_SHIFT,4,4
	.comm	I40E_GL_MDET_TX_VF_NUM_MASK,4,4
	.comm	I40E_GL_MDET_TX_VALID_MASK,4,4
	.comm	I40E_GL_MDET_TX_QUEUE_SHIFT,4,4
	.comm	I40E_GL_MDET_TX_QUEUE_MASK,4,4
	.comm	I40E_GL_MDET_TX_PF_NUM_SHIFT,4,4
	.comm	I40E_GL_MDET_TX_PF_NUM_MASK,4,4
	.comm	I40E_GL_MDET_TX_EVENT_SHIFT,4,4
	.comm	I40E_GL_MDET_TX_EVENT_MASK,4,4
	.comm	I40E_GL_MDET_TX,4,4
	.comm	I40E_GL_MDET_RX_VALID_MASK,4,4
	.comm	I40E_GL_MDET_RX_QUEUE_SHIFT,4,4
	.comm	I40E_GL_MDET_RX_QUEUE_MASK,4,4
	.comm	I40E_GL_MDET_RX_FUNCTION_SHIFT,4,4
	.comm	I40E_GL_MDET_RX_FUNCTION_MASK,4,4
	.comm	I40E_GL_MDET_RX_EVENT_SHIFT,4,4
	.comm	I40E_GL_MDET_RX_EVENT_MASK,4,4
	.comm	I40E_GL_MDET_RX,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_i40e_main.c_i40e_handle_mdd_event.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"Malicious Driver Detection event 0x%02x on TX queue"
	.ascii	" %d PF number 0x%02x VF number 0x%02x\012\000"
	.align	2
.LC1:
	.ascii	"Malicious Driver Detection event 0x%02x on RX queue"
	.ascii	" %d of function 0x%02x\012\000"
	.align	2
.LC2:
	.ascii	"TX driver issue detected on PF\012\000"
	.align	2
.LC3:
	.ascii	"RX driver issue detected on PF\012\000"
	.align	2
.LC4:
	.ascii	"TX driver issue detected on VF %d\012\000"
	.align	2
.LC5:
	.ascii	"Use PF Control I/F to re-enable the VF\012\000"
	.align	2
.LC6:
	.ascii	"RX driver issue detected on VF %d\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	i40e_handle_mdd_event, %function
i40e_handle_mdd_event:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r3, .L45
	ldr	r1, [r0, #4]
	mov	r5, r0
	sub	sp, sp, #36
	ldr	r0, [r3]
	bl	test_bit
	cmp	r0, #0
	bne	.L38
	add	sp, sp, #36
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L38:
	ldr	r7, .L45+4
	add	r6, r5, #16
	mov	r0, r6
	ldr	r1, [r7]
	bl	rd32
	ldr	r3, .L45+8
	mov	fp, r0
	ldr	r3, [r3]
	tst	r0, r3
	bne	.L39
	ldr	r4, .L45+12
	mov	r0, r6
	ldr	r1, [r4]
	bl	rd32
	ldr	r3, .L45+16
	mov	r9, r0
	ldr	r3, [r3]
	tst	r0, r3
	beq	.L9
.L13:
	ldr	ip, .L45+20
	ldr	r1, .L45+24
	ldr	r2, [ip]
	ldr	r3, .L45+28
	ldr	r8, .L45+32
	ldr	lr, .L45+36
	ldr	r10, [r3]
	str	r2, [sp, #12]
	ldr	r3, [r5, #16]
	ldr	r2, [r1]
	ldr	r7, .L45+40
	mov	r0, r5
	ldr	fp, [r8]
	ldr	r7, [r7]
	ldr	r8, [lr]
	str	r2, [sp, #16]
	str	r3, [sp, #20]
	bl	netif_msg_rx_err
	cmp	r0, #0
	bne	.L40
.L6:
	mvn	r2, #0
	mov	r0, r6
	ldr	r1, [r4]
	bl	wr32
.L5:
	ldr	r4, .L45+44
	mov	r0, r6
	ldr	r1, [r4]
	bl	rd32
	ldr	r3, .L45+48
	ldr	r3, [r3]
	tst	r0, r3
	bne	.L41
.L7:
	ldr	r4, .L45+52
	mov	r0, r6
	ldr	r1, [r4]
	bl	rd32
	ldr	r3, .L45+56
	ldr	r3, [r3]
	tst	r0, r3
	bne	.L42
.L8:
	ldr	r3, [r5]
	cmp	r3, #0
	ble	.L9
	mov	r9, #0
	ldr	r8, .L45+60
	ldr	r7, .L45+64
	ldr	fp, .L45+68
	ldr	r10, .L45+72
	b	.L12
.L10:
	mov	r0, r9
	bl	I40E_VP_MDET_RX
	mov	r1, r0
	mov	r0, r6
	bl	rd32
	ldr	r3, [r7]
	tst	r0, r3
	bne	.L43
.L11:
	ldr	r3, [r5]
	add	r9, r9, #1
	cmp	r3, r9
	ble	.L9
.L12:
	mov	r0, r9
	ldr	r4, [r5, #12]
	bl	I40E_VP_MDET_TX
	mov	r1, r0
	mov	r0, r6
	bl	rd32
	ldr	r3, [r8]
	add	r4, r4, r9, lsl #3
	tst	r0, r3
	beq	.L10
	mov	r0, r9
	bl	I40E_VP_MDET_TX
	mov	r2, fp
	mov	r1, r0
	mov	r0, r6
	bl	wr32
	ldr	r3, [r4, #4]
	mov	r2, r9
	add	r3, r3, #1
	str	r3, [r4, #4]
	ldr	r1, .L45+76
	ldr	r0, [r5, #8]
	bl	dev_info
	mov	r1, r10
	ldr	r0, [r5, #8]
	bl	dev_info
	ldr	r3, .L45+80
	mov	r1, r4
	ldr	r0, [r3]
	bl	set_bit
	b	.L10
.L9:
	ldr	r3, .L45
	ldr	r4, .L45+84
	ldr	r1, [r5, #4]
	ldr	r0, [r3]
	bl	clear_bit
	ldr	r1, [r4]
	mov	r0, r6
	bl	rd32
	mov	r2, r0
	ldr	r3, .L45+88
	mov	r0, r6
	ldr	r3, [r3]
	ldr	r1, [r4]
	orr	r2, r2, r3
	bl	wr32
	mov	r0, r6
	add	sp, sp, #36
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	b	i40e_flush
.L43:
	mov	r0, r9
	bl	I40E_VP_MDET_RX
	mov	r2, fp
	mov	r1, r0
	mov	r0, r6
	bl	wr32
	ldr	r3, [r4, #4]
	mov	r2, r9
	add	r3, r3, #1
	str	r3, [r4, #4]
	ldr	r1, .L45+92
	ldr	r0, [r5, #8]
	bl	dev_info
	mov	r1, r10
	ldr	r0, [r5, #8]
	bl	dev_info
	ldr	r3, .L45+80
	mov	r1, r4
	ldr	r0, [r3]
	bl	set_bit
	b	.L11
.L39:
	ldr	lr, .L45+96
	ldr	ip, .L45+100
	ldr	r2, [lr]
	ldr	r3, .L45+104
	ldr	r1, .L45+108
	ldr	r3, [r3]
	str	r2, [sp, #12]
	ldr	r2, [ip]
	str	r3, [sp, #24]
	str	r2, [sp, #16]
	ldr	r3, [r5, #16]
	ldr	r2, [r1]
	ldr	r4, .L45+112
	ldr	r9, .L45+116
	ldr	r8, .L45+120
	ldr	r10, .L45+124
	mov	r0, r5
	ldr	r4, [r4]
	ldr	r9, [r9]
	ldr	r8, [r8]
	ldr	r10, [r10]
	str	r2, [sp, #20]
	str	r3, [sp, #28]
	bl	netif_msg_tx_err
	cmp	r0, #0
	bne	.L44
.L4:
	ldr	r4, .L45+12
	mvn	r2, #0
	ldr	r1, [r7]
	mov	r0, r6
	bl	wr32
	mov	r0, r6
	ldr	r1, [r4]
	bl	rd32
	ldr	r3, .L45+16
	mov	r9, r0
	ldr	r3, [r3]
	tst	r0, r3
	beq	.L5
	b	.L13
.L42:
	ldr	r1, [r4]
	mov	r0, r6
	ldr	r2, .L45+68
	bl	wr32
	ldr	r1, .L45+128
	ldr	r0, [r5, #8]
	bl	dev_dbg
	b	.L8
.L41:
	ldr	r1, [r4]
	mov	r0, r6
	ldr	r2, .L45+68
	bl	wr32
	ldr	r1, .L45+132
	ldr	r0, [r5, #8]
	bl	dev_dbg
	b	.L7
.L44:
	ldr	r3, [sp, #20]
	and	r8, r8, fp
	and	r4, r4, fp
	ldr	r1, [sp, #28]
	ldr	r0, [sp, #24]
	asr	r10, r8, r10
	asr	r9, r4, r9
	stm	sp, {r9, r10}
	ldr	r2, [sp, #12]
	and	r3, r3, fp
	rsb	r3, r1, r3, asr r0
	ldr	r1, [sp, #16]
	and	r2, r2, fp
	asr	r2, r2, r1
	ldr	r0, [r5, #8]
	ldr	r1, .L45+136
	bl	dev_info
	b	.L4
.L40:
	ldr	r3, [sp, #16]
	ldr	r1, [sp, #20]
	and	r7, r7, r9
	and	r3, r3, r9
	asr	fp, r7, fp
	rsb	r3, r1, r3, asr r10
	ldr	r1, [sp, #12]
	and	r2, r8, r9
	str	fp, [sp]
	asr	r2, r2, r1
	ldr	r0, [r5, #8]
	ldr	r1, .L45+140
	bl	dev_info
	b	.L6
.L46:
	.align	2
.L45:
	.word	__I40E_MDD_EVENT_PENDING
	.word	I40E_GL_MDET_TX
	.word	I40E_GL_MDET_TX_VALID_MASK
	.word	I40E_GL_MDET_RX
	.word	I40E_GL_MDET_RX_VALID_MASK
	.word	I40E_GL_MDET_RX_EVENT_SHIFT
	.word	I40E_GL_MDET_RX_QUEUE_MASK
	.word	I40E_GL_MDET_RX_QUEUE_SHIFT
	.word	I40E_GL_MDET_RX_FUNCTION_SHIFT
	.word	I40E_GL_MDET_RX_EVENT_MASK
	.word	I40E_GL_MDET_RX_FUNCTION_MASK
	.word	I40E_PF_MDET_TX
	.word	I40E_PF_MDET_TX_VALID_MASK
	.word	I40E_PF_MDET_RX
	.word	I40E_PF_MDET_RX_VALID_MASK
	.word	I40E_VP_MDET_TX_VALID_MASK
	.word	I40E_VP_MDET_RX_VALID_MASK
	.word	65535
	.word	.LC5
	.word	.LC4
	.word	I40E_VF_STATE_DISABLED
	.word	I40E_PFINT_ICR0_ENA
	.word	I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK
	.word	.LC6
	.word	I40E_GL_MDET_TX_EVENT_MASK
	.word	I40E_GL_MDET_TX_EVENT_SHIFT
	.word	I40E_GL_MDET_TX_QUEUE_SHIFT
	.word	I40E_GL_MDET_TX_QUEUE_MASK
	.word	I40E_GL_MDET_TX_PF_NUM_MASK
	.word	I40E_GL_MDET_TX_PF_NUM_SHIFT
	.word	I40E_GL_MDET_TX_VF_NUM_MASK
	.word	I40E_GL_MDET_TX_VF_NUM_SHIFT
	.word	.LC3
	.word	.LC2
	.word	.LC0
	.word	.LC1
	.size	i40e_handle_mdd_event, .-i40e_handle_mdd_event
	.comm	__I40E_MDD_EVENT_PENDING,4,4
	.comm	I40E_VP_MDET_TX_VALID_MASK,4,4
	.comm	I40E_VP_MDET_RX_VALID_MASK,4,4
	.comm	I40E_VF_STATE_DISABLED,4,4
	.comm	I40E_PF_MDET_TX_VALID_MASK,4,4
	.comm	I40E_PF_MDET_TX,4,4
	.comm	I40E_PF_MDET_RX_VALID_MASK,4,4
	.comm	I40E_PF_MDET_RX,4,4
	.comm	I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK,4,4
	.comm	I40E_PFINT_ICR0_ENA,4,4
	.comm	I40E_GL_MDET_TX_VF_NUM_SHIFT,4,4
	.comm	I40E_GL_MDET_TX_VF_NUM_MASK,4,4
	.comm	I40E_GL_MDET_TX_VALID_MASK,4,4
	.comm	I40E_GL_MDET_TX_QUEUE_SHIFT,4,4
	.comm	I40E_GL_MDET_TX_QUEUE_MASK,4,4
	.comm	I40E_GL_MDET_TX_PF_NUM_SHIFT,4,4
	.comm	I40E_GL_MDET_TX_PF_NUM_MASK,4,4
	.comm	I40E_GL_MDET_TX_EVENT_SHIFT,4,4
	.comm	I40E_GL_MDET_TX_EVENT_MASK,4,4
	.comm	I40E_GL_MDET_TX,4,4
	.comm	I40E_GL_MDET_RX_VALID_MASK,4,4
	.comm	I40E_GL_MDET_RX_QUEUE_SHIFT,4,4
	.comm	I40E_GL_MDET_RX_QUEUE_MASK,4,4
	.comm	I40E_GL_MDET_RX_FUNCTION_SHIFT,4,4
	.comm	I40E_GL_MDET_RX_FUNCTION_MASK,4,4
	.comm	I40E_GL_MDET_RX_EVENT_SHIFT,4,4
	.comm	I40E_GL_MDET_RX_EVENT_MASK,4,4
	.comm	I40E_GL_MDET_RX,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
