	.file	"extr_ig4_iic.c_ig4iic_set_config.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"i2crst"
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC1:
	.string	"controller error during attach-1\n"
	.text
	.p2align 4
	.type	ig4iic_set_config, @function
ig4iic_set_config:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	push	rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	mov	ebp, esi
	mov	esi, DWORD PTR IG4_REG_DEVIDLE_CTRL[rip]
	push	rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	mov	rbx, rdi
	call	reg_read@PLT
	mov	rdi, QWORD PTR [rbx]
	mov	r12d, eax
	call	IG4_HAS_ADDREGS@PLT
	test	rax, rax
	je	.L2
	mov	edx, DWORD PTR IG4_RESTORE_REQUIRED[rip]
	test	edx, r12d
	jne	.L40
.L2:
	mov	rdi, QWORD PTR [rbx]
	mov	r8, QWORD PTR IG4_HASWELL[rip]
	cmp	rdi, r8
	je	.L6
	cmp	rdi, QWORD PTR IG4_ATOM[rip]
	je	.L41
.L4:
	call	IG4_HAS_ADDREGS@PLT
	test	rax, rax
	je	.L5
	test	ebp, ebp
	jne	.L42
	.p2align 4,,10
	.p2align 3
.L5:
	mov	rdi, QWORD PTR [rbx]
	cmp	rdi, QWORD PTR IG4_ATOM[rip]
	je	.L43
	cmp	rdi, QWORD PTR IG4_HASWELL[rip]
	je	.L9
.L19:
	call	IG4_HAS_ADDREGS@PLT
	test	rax, rax
	jne	.L44
.L12:
	mov	rax, QWORD PTR [rbx]
	cmp	rax, QWORD PTR IG4_HASWELL[rip]
	je	.L14
.L46:
	cmp	rax, QWORD PTR IG4_ATOM[rip]
	je	.L14
.L15:
	xor	esi, esi
	mov	rdi, rbx
	call	set_controller@PLT
	test	rax, rax
	jne	.L45
	mov	esi, DWORD PTR IG4_REG_CLR_INTR[rip]
	mov	rdi, rbx
	call	reg_read@PLT
	mov	esi, DWORD PTR IG4_REG_INTR_MASK[rip]
	xor	edx, edx
	mov	rdi, rbx
	call	reg_write@PLT
	mov	QWORD PTR 48[rbx], 0
	mov	edx, DWORD PTR 16[rbx]
	mov	rdi, rbx
	mov	esi, DWORD PTR IG4_REG_SS_SCL_HCNT[rip]
	call	reg_write@PLT
	mov	edx, DWORD PTR 20[rbx]
	mov	esi, DWORD PTR IG4_REG_SS_SCL_LCNT[rip]
	mov	rdi, rbx
	call	reg_write@PLT
	mov	edx, DWORD PTR 24[rbx]
	mov	esi, DWORD PTR IG4_REG_FS_SCL_HCNT[rip]
	mov	rdi, rbx
	call	reg_write@PLT
	mov	edx, DWORD PTR 28[rbx]
	mov	esi, DWORD PTR IG4_REG_FS_SCL_LCNT[rip]
	mov	rdi, rbx
	call	reg_write@PLT
	mov	edx, DWORD PTR 40[rbx]
	mov	eax, DWORD PTR 32[rbx]
	mov	rdi, rbx
	mov	esi, DWORD PTR IG4_REG_SDA_HOLD[rip]
	and	eax, DWORD PTR IG4_CTL_SPEED_MASK[rip]
	cmp	eax, DWORD PTR IG4_CTL_SPEED_STD[rip]
	cmove	edx, DWORD PTR 36[rbx]
	call	reg_write@PLT
	mov	esi, DWORD PTR IG4_REG_RX_TL[rip]
	mov	rdi, rbx
	xor	edx, edx
	call	reg_write@PLT
	mov	esi, DWORD PTR IG4_REG_TX_TL[rip]
	mov	rdi, rbx
	xor	edx, edx
	call	reg_write@PLT
	mov	eax, DWORD PTR 32[rbx]
	mov	edx, DWORD PTR IG4_CTL_MASTER[rip]
	mov	rdi, rbx
	or	edx, DWORD PTR IG4_CTL_SLAVE_DISABLE[rip]
	and	eax, DWORD PTR IG4_CTL_SPEED_MASK[rip]
	or	edx, DWORD PTR IG4_CTL_RESTARTEN[rip]
	mov	esi, DWORD PTR IG4_REG_CTL[rip]
	or	edx, eax
	call	reg_write@PLT
	mov	QWORD PTR 8[rbx], 0
	xor	eax, eax
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L43:
	.cfi_restore_state
	mov	esi, DWORD PTR IG4_REG_COMP_TYPE[rip]
	mov	rdi, rbx
	call	reg_read@PLT
	mov	rdi, QWORD PTR [rbx]
	cmp	QWORD PTR IG4_HASWELL[rip], rdi
	je	.L9
	cmp	QWORD PTR IG4_ATOM[rip], rdi
	jne	.L19
.L9:
	mov	esi, DWORD PTR IG4_REG_COMP_PARAM1[rip]
	mov	rdi, rbx
	call	reg_read@PLT
	mov	esi, DWORD PTR IG4_REG_GENERAL[rip]
	mov	rdi, rbx
	call	reg_read@PLT
	mov	rdi, QWORD PTR [rbx]
	cmp	rdi, QWORD PTR IG4_HASWELL[rip]
	jne	.L19
	mov	edx, DWORD PTR IG4_GENERAL_SWMODE[rip]
	test	edx, eax
	je	.L11
.L13:
	mov	esi, DWORD PTR IG4_REG_SW_LTR_VALUE[rip]
	mov	rdi, rbx
	call	reg_read@PLT
	mov	esi, DWORD PTR IG4_REG_AUTO_LTR_VALUE[rip]
	mov	rdi, rbx
	call	reg_read@PLT
	mov	rax, QWORD PTR [rbx]
	cmp	rax, QWORD PTR IG4_HASWELL[rip]
	jne	.L46
	.p2align 4,,10
	.p2align 3
.L14:
	mov	esi, DWORD PTR IG4_REG_COMP_VER[rip]
	mov	rdi, rbx
	call	reg_read@PLT
	cmp	DWORD PTR IG4_COMP_MIN_VER[rip], eax
	jle	.L15
	mov	eax, DWORD PTR ENXIO[rip]
.L47:
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L41:
	.cfi_restore_state
	mov	r8, rdi
.L6:
	test	ebp, ebp
	jne	.L3
	mov	rdi, r8
	call	IG4_HAS_ADDREGS@PLT
	jmp	.L5
	.p2align 4,,10
	.p2align 3
.L45:
	mov	edi, DWORD PTR 56[rbx]
	lea	rsi, .LC1[rip]
	call	device_printf@PLT
	mov	eax, DWORD PTR ENXIO[rip]
	jmp	.L47
	.p2align 4,,10
	.p2align 3
.L44:
	mov	esi, DWORD PTR IG4_REG_ACTIVE_LTR_VALUE[rip]
	mov	rdi, rbx
	call	reg_read@PLT
	mov	esi, DWORD PTR IG4_REG_IDLE_LTR_VALUE[rip]
	mov	rdi, rbx
	call	reg_read@PLT
	jmp	.L12
	.p2align 4,,10
	.p2align 3
.L40:
	mov	esi, DWORD PTR IG4_REG_DEVIDLE_CTRL[rip]
	or	edx, DWORD PTR IG4_DEVICE_IDLE[rip]
	mov	rdi, rbx
	call	reg_write@PLT
	mov	esi, DWORD PTR IG4_REG_DEVIDLE_CTRL[rip]
	xor	edx, edx
	mov	rdi, rbx
	call	reg_write@PLT
	lea	rdi, .LC0[rip]
	mov	esi, 1
	call	pause@PLT
	mov	rdi, QWORD PTR [rbx]
	cmp	QWORD PTR IG4_HASWELL[rip], rdi
	je	.L3
	cmp	QWORD PTR IG4_ATOM[rip], rdi
	mov	ebp, 1
	jne	.L4
.L3:
	mov	edx, DWORD PTR IG4_RESETS_ASSERT_HSW[rip]
	mov	esi, DWORD PTR IG4_REG_RESETS_HSW[rip]
	mov	rdi, rbx
	call	reg_write@PLT
	mov	edx, DWORD PTR IG4_RESETS_DEASSERT_HSW[rip]
	mov	esi, DWORD PTR IG4_REG_RESETS_HSW[rip]
	mov	rdi, rbx
	call	reg_write@PLT
	jmp	.L5
	.p2align 4,,10
	.p2align 3
.L42:
	mov	edx, DWORD PTR IG4_RESETS_ASSERT_SKL[rip]
	mov	esi, DWORD PTR IG4_REG_RESETS_SKL[rip]
	mov	rdi, rbx
	call	reg_write@PLT
	mov	edx, DWORD PTR IG4_RESETS_DEASSERT_SKL[rip]
	mov	esi, DWORD PTR IG4_REG_RESETS_SKL[rip]
	mov	rdi, rbx
	call	reg_write@PLT
	jmp	.L5
	.p2align 4,,10
	.p2align 3
.L11:
	mov	esi, DWORD PTR IG4_REG_GENERAL[rip]
	or	edx, eax
	mov	rdi, rbx
	call	reg_write@PLT
	mov	esi, DWORD PTR IG4_REG_GENERAL[rip]
	mov	rdi, rbx
	call	reg_read@PLT
	mov	rdi, QWORD PTR [rbx]
	cmp	rdi, QWORD PTR IG4_HASWELL[rip]
	je	.L13
	jmp	.L19
	.cfi_endproc
.LFE0:
	.size	ig4iic_set_config, .-ig4iic_set_config
	.comm	IG4_RESTORE_REQUIRED,4,4
	.comm	IG4_RESETS_DEASSERT_SKL,4,4
	.comm	IG4_RESETS_DEASSERT_HSW,4,4
	.comm	IG4_RESETS_ASSERT_SKL,4,4
	.comm	IG4_RESETS_ASSERT_HSW,4,4
	.comm	IG4_REG_TX_TL,4,4
	.comm	IG4_REG_SW_LTR_VALUE,4,4
	.comm	IG4_REG_SS_SCL_LCNT,4,4
	.comm	IG4_REG_SS_SCL_HCNT,4,4
	.comm	IG4_REG_SDA_HOLD,4,4
	.comm	IG4_REG_RX_TL,4,4
	.comm	IG4_REG_RESETS_SKL,4,4
	.comm	IG4_REG_RESETS_HSW,4,4
	.comm	IG4_REG_INTR_MASK,4,4
	.comm	IG4_REG_IDLE_LTR_VALUE,4,4
	.comm	IG4_REG_GENERAL,4,4
	.comm	IG4_REG_FS_SCL_LCNT,4,4
	.comm	IG4_REG_FS_SCL_HCNT,4,4
	.comm	IG4_REG_DEVIDLE_CTRL,4,4
	.comm	IG4_REG_CTL,4,4
	.comm	IG4_REG_COMP_VER,4,4
	.comm	IG4_REG_COMP_TYPE,4,4
	.comm	IG4_REG_COMP_PARAM1,4,4
	.comm	IG4_REG_CLR_INTR,4,4
	.comm	IG4_REG_AUTO_LTR_VALUE,4,4
	.comm	IG4_REG_ACTIVE_LTR_VALUE,4,4
	.comm	IG4_HASWELL,8,8
	.comm	IG4_GENERAL_SWMODE,4,4
	.comm	IG4_DEVICE_IDLE,4,4
	.comm	IG4_CTL_SPEED_STD,4,4
	.comm	IG4_CTL_SPEED_MASK,4,4
	.comm	IG4_CTL_SLAVE_DISABLE,4,4
	.comm	IG4_CTL_RESTARTEN,4,4
	.comm	IG4_CTL_MASTER,4,4
	.comm	IG4_COMP_MIN_VER,4,4
	.comm	IG4_ATOM,8,8
	.comm	ENXIO,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_ig4_iic.c_ig4iic_set_config.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"i2crst\000"
	.align	2
.LC1:
	.ascii	"controller error during attach-1\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	ig4iic_set_config, %function
ig4iic_set_config:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	ldr	r7, .L48
	mov	r6, r1
	ldr	r1, [r7]
	mov	r4, r0
	bl	reg_read
	mov	r5, r0
	ldr	r0, [r4]
	bl	IG4_HAS_ADDREGS
	cmp	r0, #0
	beq	.L2
	ldr	r3, .L48+4
	ldr	r3, [r3]
	tst	r3, r5
	bne	.L41
.L2:
	ldr	r5, .L48+8
	ldr	r0, [r4]
	ldr	r3, [r5]
	ldr	r7, .L48+12
	cmp	r0, r3
	beq	.L6
	ldr	r3, [r7]
	cmp	r0, r3
	beq	.L42
.L4:
	bl	IG4_HAS_ADDREGS
	cmp	r0, #0
	cmpne	r6, #0
	bne	.L43
.L5:
	ldr	r0, [r4]
	ldr	r3, [r7]
	cmp	r0, r3
	beq	.L44
	ldr	r3, [r5]
	cmp	r0, r3
	beq	.L9
.L19:
	bl	IG4_HAS_ADDREGS
	cmp	r0, #0
	bne	.L45
.L12:
	ldr	r2, [r5]
	ldr	r3, [r4]
	cmp	r3, r2
	beq	.L14
	ldr	r2, [r7]
	cmp	r3, r2
	beq	.L14
.L15:
	mov	r1, #0
	mov	r0, r4
	bl	set_controller
	subs	r5, r0, #0
	bne	.L46
	ldr	r3, .L48+16
	mov	r0, r4
	ldr	r1, [r3]
	bl	reg_read
	ldr	r3, .L48+20
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	reg_write
	ldr	r3, .L48+24
	ldr	r2, [r4, #8]
	ldr	r1, [r3]
	mov	r0, r4
	str	r5, [r4, #36]
	bl	reg_write
	ldr	r3, .L48+28
	ldr	r2, [r4, #12]
	ldr	r1, [r3]
	mov	r0, r4
	bl	reg_write
	ldr	r3, .L48+32
	ldr	r2, [r4, #16]
	ldr	r1, [r3]
	mov	r0, r4
	bl	reg_write
	ldr	r3, .L48+36
	ldr	r2, [r4, #20]
	ldr	r1, [r3]
	ldr	r6, .L48+40
	mov	r0, r4
	bl	reg_write
	ldr	r2, .L48+44
	ldr	r1, [r6]
	ldr	r3, [r4, #24]
	ldr	r2, [r2]
	ldr	ip, [r4, #28]
	ldr	r0, [r4, #32]
	and	r3, r3, r1
	ldr	r1, .L48+48
	cmp	r3, r2
	moveq	r2, ip
	movne	r2, r0
	ldr	r1, [r1]
	mov	r0, r4
	bl	reg_write
	ldr	r3, .L48+52
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	reg_write
	ldr	r3, .L48+56
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	reg_write
	ldr	r2, .L48+60
	ldr	r3, .L48+64
	ldr	r0, .L48+68
	ldr	r1, [r2]
	ldr	r3, [r3]
	ldr	ip, [r6]
	ldr	r2, [r4, #24]
	ldr	r0, [r0]
	orr	r3, r3, r1
	ldr	r1, .L48+72
	orr	r3, r3, r0
	and	r2, r2, ip
	mov	r0, r4
	ldr	r1, [r1]
	orr	r2, r3, r2
	bl	reg_write
	mov	r0, r5
	str	r5, [r4, #4]
	pop	{r4, r5, r6, r7, r8, pc}
.L14:
	ldr	r3, .L48+76
	mov	r0, r4
	ldr	r1, [r3]
	bl	reg_read
	ldr	r3, .L48+80
	ldr	r3, [r3]
	cmp	r3, r0
	ble	.L15
	ldr	r3, .L48+84
	ldr	r5, [r3]
.L47:
	mov	r0, r5
	pop	{r4, r5, r6, r7, r8, pc}
.L44:
	ldr	r3, .L48+88
	mov	r0, r4
	ldr	r1, [r3]
	bl	reg_read
	ldr	r0, [r4]
	ldr	r3, [r5]
	cmp	r3, r0
	beq	.L9
	ldr	r3, [r7]
	cmp	r3, r0
	bne	.L19
.L9:
	ldr	r3, .L48+92
	ldr	r6, .L48+96
	ldr	r1, [r3]
	mov	r0, r4
	bl	reg_read
	mov	r0, r4
	ldr	r1, [r6]
	bl	reg_read
	ldr	r3, [r5]
	mov	r2, r0
	ldr	r0, [r4]
	cmp	r0, r3
	bne	.L19
	ldr	r3, .L48+100
	ldr	r3, [r3]
	tst	r3, r2
	beq	.L11
.L13:
	ldr	r3, .L48+104
	mov	r0, r4
	ldr	r1, [r3]
	bl	reg_read
	ldr	r3, .L48+108
	mov	r0, r4
	ldr	r1, [r3]
	bl	reg_read
	b	.L12
.L42:
	mov	r3, r0
.L6:
	cmp	r6, #0
	bne	.L3
	mov	r0, r3
	bl	IG4_HAS_ADDREGS
	b	.L5
.L46:
	ldr	r0, [r4, #40]
	ldr	r1, .L48+112
	bl	device_printf
	ldr	r3, .L48+84
	ldr	r5, [r3]
	b	.L47
.L45:
	ldr	r3, .L48+116
	mov	r0, r4
	ldr	r1, [r3]
	bl	reg_read
	ldr	r3, .L48+120
	mov	r0, r4
	ldr	r1, [r3]
	bl	reg_read
	b	.L12
.L41:
	ldr	r2, .L48+124
	ldr	r1, [r7]
	ldr	r2, [r2]
	mov	r0, r4
	orr	r2, r3, r2
	bl	reg_write
	ldr	r5, .L48+8
	ldr	r1, [r7]
	mov	r2, #0
	mov	r0, r4
	bl	reg_write
	mov	r1, #1
	ldr	r0, .L48+128
	bl	pause
	ldr	r3, [r5]
	ldr	r0, [r4]
	ldr	r7, .L48+12
	cmp	r3, r0
	beq	.L3
	ldr	r3, [r7]
	cmp	r3, r0
	movne	r6, #1
	bne	.L4
.L3:
	ldr	r3, .L48+132
	ldr	r6, .L48+136
	ldr	r2, [r3]
	ldr	r1, [r6]
	mov	r0, r4
	bl	reg_write
	ldr	r3, .L48+140
	mov	r0, r4
	ldr	r1, [r6]
	ldr	r2, [r3]
	bl	reg_write
	b	.L5
.L11:
	orr	r2, r3, r2
	ldr	r1, [r6]
	mov	r0, r4
	bl	reg_write
	mov	r0, r4
	ldr	r1, [r6]
	bl	reg_read
	ldr	r0, [r4]
	ldr	r3, [r5]
	cmp	r0, r3
	beq	.L13
	b	.L19
.L43:
	ldr	r3, .L48+144
	ldr	r6, .L48+148
	ldr	r2, [r3]
	ldr	r1, [r6]
	mov	r0, r4
	bl	reg_write
	ldr	r3, .L48+152
	mov	r0, r4
	ldr	r1, [r6]
	ldr	r2, [r3]
	bl	reg_write
	b	.L5
.L49:
	.align	2
.L48:
	.word	IG4_REG_DEVIDLE_CTRL
	.word	IG4_RESTORE_REQUIRED
	.word	IG4_HASWELL
	.word	IG4_ATOM
	.word	IG4_REG_CLR_INTR
	.word	IG4_REG_INTR_MASK
	.word	IG4_REG_SS_SCL_HCNT
	.word	IG4_REG_SS_SCL_LCNT
	.word	IG4_REG_FS_SCL_HCNT
	.word	IG4_REG_FS_SCL_LCNT
	.word	IG4_CTL_SPEED_MASK
	.word	IG4_CTL_SPEED_STD
	.word	IG4_REG_SDA_HOLD
	.word	IG4_REG_RX_TL
	.word	IG4_REG_TX_TL
	.word	IG4_CTL_SLAVE_DISABLE
	.word	IG4_CTL_MASTER
	.word	IG4_CTL_RESTARTEN
	.word	IG4_REG_CTL
	.word	IG4_REG_COMP_VER
	.word	IG4_COMP_MIN_VER
	.word	ENXIO
	.word	IG4_REG_COMP_TYPE
	.word	IG4_REG_COMP_PARAM1
	.word	IG4_REG_GENERAL
	.word	IG4_GENERAL_SWMODE
	.word	IG4_REG_SW_LTR_VALUE
	.word	IG4_REG_AUTO_LTR_VALUE
	.word	.LC1
	.word	IG4_REG_ACTIVE_LTR_VALUE
	.word	IG4_REG_IDLE_LTR_VALUE
	.word	IG4_DEVICE_IDLE
	.word	.LC0
	.word	IG4_RESETS_ASSERT_HSW
	.word	IG4_REG_RESETS_HSW
	.word	IG4_RESETS_DEASSERT_HSW
	.word	IG4_RESETS_ASSERT_SKL
	.word	IG4_REG_RESETS_SKL
	.word	IG4_RESETS_DEASSERT_SKL
	.size	ig4iic_set_config, .-ig4iic_set_config
	.comm	IG4_RESTORE_REQUIRED,4,4
	.comm	IG4_RESETS_DEASSERT_SKL,4,4
	.comm	IG4_RESETS_DEASSERT_HSW,4,4
	.comm	IG4_RESETS_ASSERT_SKL,4,4
	.comm	IG4_RESETS_ASSERT_HSW,4,4
	.comm	IG4_REG_TX_TL,4,4
	.comm	IG4_REG_SW_LTR_VALUE,4,4
	.comm	IG4_REG_SS_SCL_LCNT,4,4
	.comm	IG4_REG_SS_SCL_HCNT,4,4
	.comm	IG4_REG_SDA_HOLD,4,4
	.comm	IG4_REG_RX_TL,4,4
	.comm	IG4_REG_RESETS_SKL,4,4
	.comm	IG4_REG_RESETS_HSW,4,4
	.comm	IG4_REG_INTR_MASK,4,4
	.comm	IG4_REG_IDLE_LTR_VALUE,4,4
	.comm	IG4_REG_GENERAL,4,4
	.comm	IG4_REG_FS_SCL_LCNT,4,4
	.comm	IG4_REG_FS_SCL_HCNT,4,4
	.comm	IG4_REG_DEVIDLE_CTRL,4,4
	.comm	IG4_REG_CTL,4,4
	.comm	IG4_REG_COMP_VER,4,4
	.comm	IG4_REG_COMP_TYPE,4,4
	.comm	IG4_REG_COMP_PARAM1,4,4
	.comm	IG4_REG_CLR_INTR,4,4
	.comm	IG4_REG_AUTO_LTR_VALUE,4,4
	.comm	IG4_REG_ACTIVE_LTR_VALUE,4,4
	.comm	IG4_HASWELL,4,4
	.comm	IG4_GENERAL_SWMODE,4,4
	.comm	IG4_DEVICE_IDLE,4,4
	.comm	IG4_CTL_SPEED_STD,4,4
	.comm	IG4_CTL_SPEED_MASK,4,4
	.comm	IG4_CTL_SLAVE_DISABLE,4,4
	.comm	IG4_CTL_RESTARTEN,4,4
	.comm	IG4_CTL_MASTER,4,4
	.comm	IG4_COMP_MIN_VER,4,4
	.comm	IG4_ATOM,4,4
	.comm	ENXIO,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
