	.file	"extr_dcn20_dccg.c_dccg2_update_dpp_dto.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	dccg2_update_dpp_dto
	.type	dccg2_update_dpp_dto, @function
dccg2_update_dpp_dto:
.LFB0:
	.cfi_startproc
	endbr64
	push	r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	mov	r14d, ecx
	push	r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	mov	r13d, edx
	push	r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	push	rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movsx	rbp, esi
	push	rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	mov	rbx, rdi
	sub	rsp, 16
	.cfi_def_cfa_offset 64
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 8[rsp], rax
	xor	eax, eax
	call	TO_DCN_DCCG@PLT
	mov	r12d, DWORD PTR [rbx]
	test	r13d, r13d
	je	.L2
	test	r12d, r12d
	jne	.L18
.L2:
	mov	rax, QWORD PTR DPPCLK_DTO_ENABLE[rip]
	mov	edi, DWORD PTR DPPCLK_DTO_CTRL[rip]
	xor	edx, edx
	mov	esi, DWORD PTR [rax+rbp*4]
	call	REG_UPDATE@PLT
.L1:
	mov	rax, QWORD PTR 8[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L19
	add	rsp, 16
	.cfi_remember_state
	.cfi_def_cfa_offset 48
	pop	rbx
	.cfi_def_cfa_offset 40
	pop	rbp
	.cfi_def_cfa_offset 32
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L18:
	.cfi_restore_state
	xor	edi, edi
	cmp	r12d, r13d
	setge	dil
	call	ASSERT@PLT
	cmp	r12d, 255
	jle	.L3
	lea	ecx, 254[r12]
	mov	eax, 2155905153
	imul	rcx, rax
	mov	eax, r12d
	cdq
	shr	rcx, 39
	idiv	ecx
	mov	r12d, eax
	lea	eax, -1[rcx+r13]
	cdq
	idiv	ecx
	cmp	eax, r12d
	cmovg	eax, r12d
	mov	r13d, eax
.L3:
	mov	rax, QWORD PTR DPPCLK_DTO_PARAM[rip]
	mov	ecx, DWORD PTR DPPCLK0_DTO_MODULO[rip]
	mov	rdx, rsp
	lea	r8, 4[rsp]
	mov	esi, DWORD PTR DPPCLK0_DTO_PHASE[rip]
	mov	edi, DWORD PTR [rax+rbp*4]
	call	REG_GET_2@PLT
	test	r14d, r14d
	je	.L4
	mov	rax, QWORD PTR DPPCLK_DTO_PARAM[rip]
	mov	r9d, DWORD PTR 4[rsp]
	mov	ecx, DWORD PTR [rsp]
	mov	r8d, DWORD PTR DPPCLK0_DTO_MODULO[rip]
	mov	edi, DWORD PTR [rax+rbp*4]
	mov	esi, r9d
	mov	edx, DWORD PTR DPPCLK0_DTO_PHASE[rip]
	mov	eax, ecx
	imul	esi, r13d
	imul	eax, r12d
	cmp	esi, eax
	jl	.L16
	mov	r9d, r12d
	mov	ecx, r13d
	xor	esi, esi
	call	REG_SET_2@PLT
.L6:
	mov	rax, QWORD PTR DPPCLK_DTO_ENABLE[rip]
	mov	edi, DWORD PTR DPPCLK_DTO_CTRL[rip]
	mov	edx, 1
	mov	esi, DWORD PTR [rax+rbp*4]
	call	REG_UPDATE@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L4:
	mov	rax, QWORD PTR DPPCLK_DTO_PARAM[rip]
	mov	r8d, DWORD PTR DPPCLK0_DTO_MODULO[rip]
	mov	r9d, r12d
	mov	ecx, r13d
	mov	edx, DWORD PTR DPPCLK0_DTO_PHASE[rip]
	mov	edi, DWORD PTR [rax+rbp*4]
.L16:
	xor	esi, esi
	call	REG_SET_2@PLT
	jmp	.L6
.L19:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	dccg2_update_dpp_dto, .-dccg2_update_dpp_dto
	.comm	DPPCLK_DTO_PARAM,8,8
	.comm	DPPCLK_DTO_ENABLE,8,8
	.comm	DPPCLK_DTO_CTRL,4,4
	.comm	DPPCLK0_DTO_PHASE,4,4
	.comm	DPPCLK0_DTO_MODULO,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_dcn20_dccg.c_dccg2_update_dpp_dto.c"
	.text
	.global	__aeabi_idiv
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	dccg2_update_dpp_dto
	.syntax unified
	.arm
	.fpu softvfp
	.type	dccg2_update_dpp_dto, %function
dccg2_update_dpp_dto:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, lr}
	mov	r6, r0
	mov	r4, r2
	mov	r7, r3
	ldr	r3, .L13
	sub	sp, sp, #24
	mov	r5, r1
	ldr	r3, [r3]
	str	r3, [sp, #20]
	mov	r3,#0
	bl	TO_DCN_DCCG
	ldr	r6, [r6]
	subs	r2, r6, #0
	movne	r2, #1
	cmp	r4, #0
	moveq	r2, #0
	cmp	r2, #0
	bne	.L11
	ldr	r1, .L13+4
	ldr	r3, .L13+8
	ldr	r1, [r1]
	ldr	r0, [r3]
	ldr	r1, [r1, r5, lsl #2]
	bl	REG_UPDATE
.L1:
	ldr	r3, .L13
	ldr	r2, [r3]
	ldr	r3, [sp, #20]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L12
	add	sp, sp, #24
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
.L11:
	cmp	r6, r4
	movlt	r0, #0
	movge	r0, #1
	bl	ASSERT
	cmp	r6, #255
	ble	.L3
	ldr	r1, .L13+12
	add	r8, r6, #254
	umull	r3, r8, r1, r8
	lsr	r8, r8, #7
	mov	r0, r6
	mov	r1, r8
	bl	__aeabi_idiv
	mov	r6, r0
	add	r0, r4, r8
	mov	r1, r8
	sub	r0, r0, #1
	bl	__aeabi_idiv
	cmp	r0, r6
	movlt	r4, r0
	movge	r4, r6
.L3:
	ldr	r10, .L13+16
	ldr	r9, .L13+20
	ldr	r3, [r10]
	ldr	r8, .L13+24
	add	r2, sp, #16
	ldr	r0, [r3, r5, lsl #2]
	ldr	r1, [r8]
	ldr	r3, [r9]
	str	r2, [sp]
	add	r2, sp, #12
	bl	REG_GET_2
	cmp	r7, #0
	beq	.L4
	ldr	r1, [sp, #16]
	ldr	r3, [sp, #12]
	mul	ip, r4, r1
	mul	r0, r6, r3
	ldr	r2, [r10]
	cmp	ip, r0
	ldr	ip, [r9]
	ldr	r0, [r2, r5, lsl #2]
	movge	r3, r4
	ldr	r2, [r8]
	strlt	r1, [sp, #4]
	strge	r6, [sp, #4]
	mov	r1, #0
	strge	ip, [sp]
	strlt	ip, [sp]
	bl	REG_SET_2
.L6:
	ldr	r3, .L13+4
	ldr	r2, .L13+8
	ldr	r3, [r3]
	ldr	r0, [r2]
	ldr	r1, [r3, r5, lsl #2]
	mov	r2, #1
	bl	REG_UPDATE
	b	.L1
.L4:
	ldr	r3, [r10]
	ldr	r2, [r9]
	ldr	r0, [r3, r5, lsl #2]
	stm	sp, {r2, r6}
	mov	r3, r4
	mov	r1, r7
	ldr	r2, [r8]
	bl	REG_SET_2
	b	.L6
.L12:
	bl	__stack_chk_fail
.L14:
	.align	2
.L13:
	.word	.LC0
	.word	DPPCLK_DTO_ENABLE
	.word	DPPCLK_DTO_CTRL
	.word	-2139062143
	.word	DPPCLK_DTO_PARAM
	.word	DPPCLK0_DTO_MODULO
	.word	DPPCLK0_DTO_PHASE
	.size	dccg2_update_dpp_dto, .-dccg2_update_dpp_dto
	.comm	DPPCLK_DTO_PARAM,4,4
	.comm	DPPCLK_DTO_ENABLE,4,4
	.comm	DPPCLK_DTO_CTRL,4,4
	.comm	DPPCLK0_DTO_PHASE,4,4
	.comm	DPPCLK0_DTO_MODULO,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
