	.file	"extr_sun8i_hdmi_phy.c_sun8i_hdmi_phy_init_h3.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	sun8i_hdmi_phy_init_h3, @function
sun8i_hdmi_phy_init_h3:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	mov	rbx, rdi
	sub	rsp, 16
	.cfi_def_cfa_offset 32
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 8[rsp], rax
	xor	eax, eax
	call	sun8i_hdmi_phy_unlock@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_REG[rip]
	xor	edx, edx
	call	regmap_write@PLT
	mov	edx, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_ENBI[rip]
	mov	esi, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_REG[rip]
	mov	edi, DWORD PTR 4[rbx]
	mov	ecx, edx
	call	regmap_update_bits@PLT
	mov	edi, 5
	call	udelay@PLT
	mov	edx, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN[rip]
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_REG[rip]
	mov	ecx, edx
	call	regmap_update_bits@PLT
	mov	edx, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_ENVBS[rip]
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_REG[rip]
	mov	ecx, edx
	call	regmap_update_bits@PLT
	mov	esi, 20
	mov	edi, 10
	call	usleep_range@PLT
	mov	edx, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_LDOEN[rip]
	mov	esi, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_REG[rip]
	mov	edi, DWORD PTR 4[rbx]
	mov	ecx, edx
	call	regmap_update_bits@PLT
	mov	edi, 5
	call	udelay@PLT
	mov	edx, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_CKEN[rip]
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_REG[rip]
	mov	ecx, edx
	call	regmap_update_bits@PLT
	mov	esi, 100
	mov	edi, 40
	call	usleep_range@PLT
	mov	edx, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL[rip]
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_REG[rip]
	mov	ecx, edx
	call	regmap_update_bits@PLT
	mov	esi, 200
	mov	edi, 100
	call	usleep_range@PLT
	mov	edx, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG[rip]
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_REG[rip]
	mov	ecx, edx
	call	regmap_update_bits@PLT
	mov	edx, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0[rip]
	mov	edi, DWORD PTR 4[rbx]
	or	edx, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1[rip]
	mov	esi, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_REG[rip]
	or	edx, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2[rip]
	mov	ecx, edx
	call	regmap_update_bits@PLT
	mov	edx, DWORD PTR 4[rsp]
	mov	edi, DWORD PTR 4[rbx]
	mov	r9d, 2000
	mov	ecx, DWORD PTR SUN8I_HDMI_PHY_ANA_STS_RCALEND2D[rip]
	mov	esi, DWORD PTR SUN8I_HDMI_PHY_ANA_STS_REG[rip]
	mov	r8d, 100
	and	ecx, edx
	call	regmap_read_poll_timeout@PLT
	mov	edx, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK[rip]
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_REG[rip]
	mov	ecx, edx
	call	regmap_update_bits@PLT
	mov	edx, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0[rip]
	mov	edi, DWORD PTR 4[rbx]
	or	edx, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1[rip]
	mov	esi, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_REG[rip]
	or	edx, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2[rip]
	or	edx, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK[rip]
	mov	ecx, edx
	call	regmap_update_bits@PLT
	mov	edx, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG3_SCLEN[rip]
	mov	edi, DWORD PTR 4[rbx]
	or	edx, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG3_SDAEN[rip]
	mov	esi, DWORD PTR SUN8I_HDMI_PHY_ANA_CFG3_REG[rip]
	mov	ecx, edx
	call	regmap_update_bits@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	edx, DWORD PTR SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK[rip]
	xor	ecx, ecx
	mov	esi, DWORD PTR SUN8I_HDMI_PHY_PLL_CFG1_REG[rip]
	call	regmap_update_bits@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR SUN8I_HDMI_PHY_CEC_REG[rip]
	xor	edx, edx
	call	regmap_write@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	esi, DWORD PTR SUN8I_HDMI_PHY_ANA_STS_REG[rip]
	lea	rdx, 4[rsp]
	call	regmap_read@PLT
	mov	eax, DWORD PTR 4[rsp]
	and	eax, DWORD PTR SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK[rip]
	shr	eax, 2
	mov	DWORD PTR [rbx], eax
	mov	rax, QWORD PTR 8[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L5
	add	rsp, 16
	.cfi_remember_state
	.cfi_def_cfa_offset 16
	pop	rbx
	.cfi_def_cfa_offset 8
	ret
.L5:
	.cfi_restore_state
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	sun8i_hdmi_phy_init_h3, .-sun8i_hdmi_phy_init_h3
	.comm	SUN8I_HDMI_PHY_PLL_CFG1_REG,4,4
	.comm	SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,4,4
	.comm	SUN8I_HDMI_PHY_CEC_REG,4,4
	.comm	SUN8I_HDMI_PHY_ANA_STS_REG,4,4
	.comm	SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK,4,4
	.comm	SUN8I_HDMI_PHY_ANA_STS_RCALEND2D,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG3_SDAEN,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG3_SCLEN,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG3_REG,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_REG,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_LDOEN,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_ENVBS,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_ENBI,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_CKEN,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_sun8i_hdmi_phy.c_sun8i_hdmi_phy_init_h3.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	sun8i_hdmi_phy_init_h3, %function
sun8i_hdmi_phy_init_h3:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, lr}
	mov	r4, r0
	ldr	r5, .L6
	ldr	r3, .L6+4
	sub	sp, sp, #16
	ldr	r3, [r3]
	str	r3, [sp, #12]
	mov	r3,#0
	bl	sun8i_hdmi_phy_unlock
	mov	r2, #0
	ldr	r1, [r5]
	ldr	r0, [r4, #4]
	bl	regmap_write
	ldr	r3, .L6+8
	ldr	r1, [r5]
	ldr	r3, [r3]
	ldr	r0, [r4, #4]
	mov	r2, r3
	bl	regmap_update_bits
	mov	r0, #5
	bl	udelay
	ldr	r3, .L6+12
	ldr	r1, [r5]
	ldr	r3, [r3]
	ldr	r0, [r4, #4]
	mov	r2, r3
	bl	regmap_update_bits
	ldr	r3, .L6+16
	ldr	r1, [r5]
	ldr	r3, [r3]
	ldr	r0, [r4, #4]
	mov	r2, r3
	bl	regmap_update_bits
	mov	r1, #20
	mov	r0, #10
	bl	usleep_range
	ldr	r3, .L6+20
	ldr	r1, [r5]
	ldr	r3, [r3]
	ldr	r0, [r4, #4]
	mov	r2, r3
	bl	regmap_update_bits
	mov	r0, #5
	bl	udelay
	ldr	r3, .L6+24
	ldr	r1, [r5]
	ldr	r3, [r3]
	ldr	r0, [r4, #4]
	mov	r2, r3
	bl	regmap_update_bits
	mov	r1, #100
	mov	r0, #40
	bl	usleep_range
	ldr	r3, .L6+28
	ldr	r1, [r5]
	ldr	r3, [r3]
	ldr	r0, [r4, #4]
	mov	r2, r3
	bl	regmap_update_bits
	mov	r1, #200
	mov	r0, #100
	bl	usleep_range
	ldr	r3, .L6+32
	ldr	r1, [r5]
	ldr	r3, [r3]
	ldr	r0, [r4, #4]
	mov	r2, r3
	bl	regmap_update_bits
	ldr	r3, .L6+36
	ldr	r1, .L6+40
	ldr	r2, .L6+44
	ldr	r1, [r1]
	ldr	r3, [r3]
	ldr	r2, [r2]
	orr	r3, r3, r1
	orr	r3, r3, r2
	mov	r2, r3
	ldr	r1, [r5]
	ldr	r0, [r4, #4]
	bl	regmap_update_bits
	mov	ip, #2000
	mov	r1, #100
	ldr	r3, .L6+48
	ldr	r2, [sp, #8]
	ldr	r3, [r3]
	ldr	r6, .L6+52
	and	r3, r3, r2
	ldr	r0, [r4, #4]
	stm	sp, {r1, ip}
	ldr	r1, [r6]
	bl	regmap_read_poll_timeout
	ldr	r3, .L6+56
	ldr	r1, [r5]
	ldr	r3, [r3]
	ldr	r0, [r4, #4]
	mov	r2, r3
	bl	regmap_update_bits
	ldr	r2, .L6+60
	ldr	r3, .L6+64
	ldr	r1, .L6+68
	ldr	r0, [r2]
	ldr	r3, [r3]
	ldr	r2, .L6+72
	ldr	r1, [r1]
	ldr	r2, [r2]
	orr	r3, r3, r0
	orr	r3, r3, r1
	orr	r3, r3, r2
	mov	r2, r3
	ldr	r1, [r5]
	ldr	r0, [r4, #4]
	bl	regmap_update_bits
	ldr	r3, .L6+76
	ldr	r2, .L6+80
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	r1, .L6+84
	orr	r3, r3, r2
	mov	r2, r3
	ldr	r1, [r1]
	ldr	r0, [r4, #4]
	bl	regmap_update_bits
	ldr	r3, .L6+88
	ldr	r2, .L6+92
	ldr	r1, [r3]
	ldr	r2, [r2]
	mov	r3, #0
	ldr	r0, [r4, #4]
	bl	regmap_update_bits
	ldr	r3, .L6+96
	mov	r2, #0
	ldr	r1, [r3]
	ldr	r0, [r4, #4]
	bl	regmap_write
	add	r2, sp, #8
	ldr	r1, [r6]
	ldr	r0, [r4, #4]
	bl	regmap_read
	ldr	r2, .L6+100
	ldr	r3, [sp, #8]
	ldr	r2, [r2]
	and	r3, r3, r2
	lsr	r3, r3, #2
	str	r3, [r4]
	ldr	r3, .L6+4
	ldr	r2, [r3]
	ldr	r3, [sp, #12]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L5
	add	sp, sp, #16
	@ sp needed
	pop	{r4, r5, r6, pc}
.L5:
	bl	__stack_chk_fail
.L7:
	.align	2
.L6:
	.word	SUN8I_HDMI_PHY_ANA_CFG1_REG
	.word	.LC0
	.word	SUN8I_HDMI_PHY_ANA_CFG1_ENBI
	.word	SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN
	.word	SUN8I_HDMI_PHY_ANA_CFG1_ENVBS
	.word	SUN8I_HDMI_PHY_ANA_CFG1_LDOEN
	.word	SUN8I_HDMI_PHY_ANA_CFG1_CKEN
	.word	SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL
	.word	SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG
	.word	SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0
	.word	SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1
	.word	SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2
	.word	SUN8I_HDMI_PHY_ANA_STS_RCALEND2D
	.word	SUN8I_HDMI_PHY_ANA_STS_REG
	.word	SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK
	.word	SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1
	.word	SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0
	.word	SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2
	.word	SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK
	.word	SUN8I_HDMI_PHY_ANA_CFG3_SCLEN
	.word	SUN8I_HDMI_PHY_ANA_CFG3_SDAEN
	.word	SUN8I_HDMI_PHY_ANA_CFG3_REG
	.word	SUN8I_HDMI_PHY_PLL_CFG1_REG
	.word	SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK
	.word	SUN8I_HDMI_PHY_CEC_REG
	.word	SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK
	.size	sun8i_hdmi_phy_init_h3, .-sun8i_hdmi_phy_init_h3
	.comm	SUN8I_HDMI_PHY_PLL_CFG1_REG,4,4
	.comm	SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,4,4
	.comm	SUN8I_HDMI_PHY_CEC_REG,4,4
	.comm	SUN8I_HDMI_PHY_ANA_STS_REG,4,4
	.comm	SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK,4,4
	.comm	SUN8I_HDMI_PHY_ANA_STS_RCALEND2D,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG3_SDAEN,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG3_SCLEN,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG3_REG,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_REG,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_LDOEN,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_ENVBS,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_ENBI,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_CKEN,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1,4,4
	.comm	SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
