	.file	"extr_r8152.c_r8153_hw_phy_cfg.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	r8153_hw_phy_cfg, @function
r8153_hw_phy_cfg:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	xor	esi, esi
	mov	rbx, rdi
	call	r8153_aldps_en@PLT
	xor	esi, esi
	mov	rdi, rbx
	call	rtl_eee_enable@PLT
	cmp	DWORD PTR [rbx], 131
	je	.L7
.L2:
	mov	esi, DWORD PTR OCP_POWER_CFG[rip]
	mov	rdi, rbx
	call	ocp_reg_read@PLT
	mov	esi, DWORD PTR OCP_POWER_CFG[rip]
	or	eax, DWORD PTR EEE_CLKDIV_EN[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	ocp_reg_write@PLT
	mov	esi, DWORD PTR OCP_DOWN_SPEED[rip]
	mov	rdi, rbx
	call	ocp_reg_read@PLT
	mov	esi, DWORD PTR OCP_DOWN_SPEED[rip]
	or	eax, DWORD PTR EN_10M_BGOFF[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	ocp_reg_write@PLT
	mov	esi, DWORD PTR OCP_POWER_CFG[rip]
	mov	rdi, rbx
	call	ocp_reg_read@PLT
	mov	esi, DWORD PTR OCP_POWER_CFG[rip]
	or	eax, DWORD PTR EN_10M_PLLOFF[rip]
	mov	rdi, rbx
	mov	edx, eax
	call	ocp_reg_write@PLT
	mov	esi, DWORD PTR SRAM_IMPEDANCE[rip]
	mov	edx, 2835
	mov	rdi, rbx
	call	sram_write@PLT
	mov	edx, DWORD PTR PLA_PHY_PWR[rip]
	mov	esi, DWORD PTR MCU_TYPE_PLA[rip]
	mov	rdi, rbx
	call	ocp_read_word@PLT
	mov	edx, DWORD PTR PLA_PHY_PWR[rip]
	or	eax, DWORD PTR PFM_PWM_SWITCH[rip]
	mov	rdi, rbx
	mov	esi, DWORD PTR MCU_TYPE_PLA[rip]
	mov	ecx, eax
	call	ocp_write_word@PLT
	mov	esi, DWORD PTR SRAM_LPF_CFG[rip]
	mov	edx, 63247
	mov	rdi, rbx
	call	sram_write@PLT
	mov	esi, DWORD PTR SRAM_10M_AMP1[rip]
	mov	edx, 175
	mov	rdi, rbx
	call	sram_write@PLT
	mov	esi, DWORD PTR SRAM_10M_AMP2[rip]
	mov	edx, 520
	mov	rdi, rbx
	call	sram_write@PLT
	cmp	QWORD PTR 8[rbx], 0
	jne	.L8
.L3:
	mov	esi, 1
	mov	rdi, rbx
	call	r8153_aldps_en@PLT
	mov	rdi, rbx
	call	r8152b_enable_fc@PLT
	mov	eax, DWORD PTR [rbx]
	sub	eax, 130
	cmp	eax, 1
	jbe	.L4
	mov	esi, 1
	mov	rdi, rbx
	call	r8153_u2p3en@PLT
.L4:
	mov	edi, DWORD PTR PHY_RESET[rip]
	lea	rsi, 4[rbx]
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	set_bit@PLT
	.p2align 4,,10
	.p2align 3
.L8:
	.cfi_restore_state
	mov	esi, 1
	mov	rdi, rbx
	call	rtl_eee_enable@PLT
	jmp	.L3
	.p2align 4,,10
	.p2align 3
.L7:
	mov	esi, DWORD PTR OCP_EEE_CFG[rip]
	mov	rdi, rbx
	call	ocp_reg_read@PLT
	mov	edx, DWORD PTR CTAP_SHORT_EN[rip]
	mov	esi, DWORD PTR OCP_EEE_CFG[rip]
	mov	rdi, rbx
	not	edx
	and	edx, eax
	call	ocp_reg_write@PLT
	jmp	.L2
	.cfi_endproc
.LFE0:
	.size	r8153_hw_phy_cfg, .-r8153_hw_phy_cfg
	.comm	SRAM_LPF_CFG,4,4
	.comm	SRAM_IMPEDANCE,4,4
	.comm	SRAM_10M_AMP2,4,4
	.comm	SRAM_10M_AMP1,4,4
	.comm	PLA_PHY_PWR,4,4
	.comm	PHY_RESET,4,4
	.comm	PFM_PWM_SWITCH,4,4
	.comm	OCP_POWER_CFG,4,4
	.comm	OCP_EEE_CFG,4,4
	.comm	OCP_DOWN_SPEED,4,4
	.comm	MCU_TYPE_PLA,4,4
	.comm	EN_10M_PLLOFF,4,4
	.comm	EN_10M_BGOFF,4,4
	.comm	EEE_CLKDIV_EN,4,4
	.comm	CTAP_SHORT_EN,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_r8152.c_r8153_hw_phy_cfg.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	r8153_hw_phy_cfg, %function
r8153_hw_phy_cfg:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, lr}
	mov	r4, r0
	mov	r1, #0
	bl	r8153_aldps_en
	mov	r0, r4
	mov	r1, #0
	bl	rtl_eee_enable
	ldr	r3, [r4]
	cmp	r3, #131
	beq	.L10
.L2:
	ldr	r5, .L12
	mov	r0, r4
	ldr	r1, [r5]
	bl	ocp_reg_read
	ldr	r3, .L12+4
	ldr	r6, .L12+8
	ldr	r2, [r3]
	ldr	r1, [r5]
	orr	r2, r0, r2
	mov	r0, r4
	bl	ocp_reg_write
	ldr	r1, [r6]
	mov	r0, r4
	bl	ocp_reg_read
	mov	r2, r0
	ldr	r3, .L12+12
	ldr	r1, [r6]
	ldr	r3, [r3]
	mov	r0, r4
	orr	r2, r2, r3
	bl	ocp_reg_write
	ldr	r1, [r5]
	mov	r0, r4
	bl	ocp_reg_read
	mov	r2, r0
	ldr	r3, .L12+16
	ldr	r1, [r5]
	ldr	r3, [r3]
	mov	r0, r4
	orr	r2, r2, r3
	bl	ocp_reg_write
	ldr	r3, .L12+20
	ldr	r6, .L12+24
	ldr	r5, .L12+28
	ldr	r1, [r3]
	ldr	r2, .L12+32
	mov	r0, r4
	bl	sram_write
	ldr	r2, [r6]
	ldr	r1, [r5]
	mov	r0, r4
	bl	ocp_read_word
	ldr	r3, .L12+36
	ldr	r2, [r6]
	ldr	r3, [r3]
	ldr	r1, [r5]
	orr	r3, r0, r3
	mov	r0, r4
	bl	ocp_write_word
	ldr	r3, .L12+40
	ldr	r2, .L12+44
	ldr	r1, [r3]
	mov	r0, r4
	bl	sram_write
	ldr	r3, .L12+48
	mov	r2, #175
	ldr	r1, [r3]
	mov	r0, r4
	bl	sram_write
	ldr	r3, .L12+52
	mov	r2, #520
	ldr	r1, [r3]
	mov	r0, r4
	bl	sram_write
	ldr	r3, [r4, #8]
	cmp	r3, #0
	bne	.L11
.L3:
	mov	r1, #1
	mov	r0, r4
	bl	r8153_aldps_en
	mov	r0, r4
	bl	r8152b_enable_fc
	ldr	r3, [r4]
	sub	r3, r3, #130
	cmp	r3, #1
	bls	.L4
	mov	r1, #1
	mov	r0, r4
	bl	r8153_u2p3en
.L4:
	ldr	r3, .L12+56
	add	r1, r4, #4
	ldr	r0, [r3]
	pop	{r4, r5, r6, lr}
	b	set_bit
.L11:
	mov	r1, #1
	mov	r0, r4
	bl	rtl_eee_enable
	b	.L3
.L10:
	ldr	r5, .L12+60
	mov	r0, r4
	ldr	r1, [r5]
	bl	ocp_reg_read
	mov	r3, r0
	ldr	r2, .L12+64
	mov	r0, r4
	ldr	r2, [r2]
	ldr	r1, [r5]
	bic	r2, r3, r2
	bl	ocp_reg_write
	b	.L2
.L13:
	.align	2
.L12:
	.word	OCP_POWER_CFG
	.word	EEE_CLKDIV_EN
	.word	OCP_DOWN_SPEED
	.word	EN_10M_BGOFF
	.word	EN_10M_PLLOFF
	.word	SRAM_IMPEDANCE
	.word	PLA_PHY_PWR
	.word	MCU_TYPE_PLA
	.word	2835
	.word	PFM_PWM_SWITCH
	.word	SRAM_LPF_CFG
	.word	63247
	.word	SRAM_10M_AMP1
	.word	SRAM_10M_AMP2
	.word	PHY_RESET
	.word	OCP_EEE_CFG
	.word	CTAP_SHORT_EN
	.size	r8153_hw_phy_cfg, .-r8153_hw_phy_cfg
	.comm	SRAM_LPF_CFG,4,4
	.comm	SRAM_IMPEDANCE,4,4
	.comm	SRAM_10M_AMP2,4,4
	.comm	SRAM_10M_AMP1,4,4
	.comm	PLA_PHY_PWR,4,4
	.comm	PHY_RESET,4,4
	.comm	PFM_PWM_SWITCH,4,4
	.comm	OCP_POWER_CFG,4,4
	.comm	OCP_EEE_CFG,4,4
	.comm	OCP_DOWN_SPEED,4,4
	.comm	MCU_TYPE_PLA,4,4
	.comm	EN_10M_PLLOFF,4,4
	.comm	EN_10M_BGOFF,4,4
	.comm	EEE_CLKDIV_EN,4,4
	.comm	CTAP_SHORT_EN,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
