	.file	"extr_bnx2x_main.c_bnx2x_init_hw_func.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"starting func init  func %d\n"
.LC1:
	.string	"NIC MODE disabled\n"
.LC2:
	.string	"NIC MODE configured\n"
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC3:
	.string	"Hmmm... Parity errors in HC block during function init (0x%x)!\n"
	.text
	.p2align 4
	.type	bnx2x_init_hw_func, @function
bnx2x_init_hw_func:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 24
	.cfi_def_cfa_offset 80
	call	BP_PORT@PLT
	mov	rdi, rbp
	mov	DWORD PTR 12[rsp], eax
	call	BP_FUNC@PLT
	mov	r12d, DWORD PTR PHASE_PF0[rip]
	mov	rdi, rbp
	mov	ebx, eax
	mov	DWORD PTR 8[rsp], eax
	add	r12d, eax
	call	BP_ILT@PLT
	mov	edi, DWORD PTR NETIF_MSG_HW[rip]
	xor	eax, eax
	mov	edx, ebx
	lea	rsi, .LC0[rip]
	call	DP@PLT
	mov	rdi, rbp
	call	CHIP_IS_E1x@PLT
	test	rax, rax
	je	.L78
.L2:
	mov	rax, QWORD PTR INT_BLOCK_HC[rip]
	cmp	QWORD PTR 32[rbp], rax
	jne	.L4
	mov	edx, DWORD PTR 12[rsp]
	mov	r13d, DWORD PTR HC_REG_CONFIG_1[rip]
	mov	rdi, rbp
	test	edx, edx
	cmove	r13d, DWORD PTR HC_REG_CONFIG_0[rip]
	mov	esi, r13d
	call	REG_RD@PLT
	or	eax, DWORD PTR HC_CONFIG_0_REG_MSI_ATTN_EN_0[rip]
	mov	esi, r13d
	mov	rdi, rbp
	mov	edx, eax
	call	REG_WR@PLT
.L4:
	mov	esi, DWORD PTR BLOCK_PXP[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_PXP2[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	rdi, rbp
	call	BP_ILT@PLT
	mov	rdx, QWORD PTR ILT_CLIENT_CDU[rip]
	mov	rdi, rbp
	mov	rbx, rax
	mov	rax, QWORD PTR 8[rax]
	mov	r13d, DWORD PTR [rax+rdx*4]
	call	IS_SRIOV@PLT
	test	rax, rax
	jne	.L79
.L7:
	mov	esi, r13d
	mov	rdi, rbp
	xor	r14d, r14d
	xor	r15d, r15d
	call	bnx2x_iov_init_ilt@PLT
	mov	rax, QWORD PTR 8[rbx]
	mov	rdx, QWORD PTR ILT_CLIENT_CDU[rip]
	movsx	rax, DWORD PTR [rax+rdx*4]
	lea	r13, [rax+rax*2]
	sal	r13, 2
	jmp	.L8
	.p2align 4,,10
	.p2align 3
.L9:
	mov	rcx, QWORD PTR 40[rbp]
	lea	rax, 0[r13+r14]
	add	rax, QWORD PTR [rbx]
	add	r15d, 1
	add	rcx, r14
	add	r14, 12
	mov	edi, DWORD PTR 8[rcx]
	mov	DWORD PTR 8[rax], edi
	mov	edi, DWORD PTR 4[rcx]
	mov	ecx, DWORD PTR [rcx]
	mov	DWORD PTR 4[rax], edi
	mov	DWORD PTR [rax], ecx
.L8:
	mov	rdi, rbp
	call	L2_ILT_LINES@PLT
	cmp	eax, r15d
	jg	.L9
	mov	esi, DWORD PTR INITOP_SET[rip]
	mov	rdi, rbp
	call	bnx2x_ilt_init_op@PLT
	mov	rdi, rbp
	call	CONFIGURE_NIC_MODE@PLT
	test	eax, eax
	je	.L80
	mov	esi, DWORD PTR PRS_REG_NIC_MODE[rip]
	mov	rdi, rbp
	mov	edx, 1
	call	REG_WR@PLT
	mov	edi, DWORD PTR NETIF_MSG_IFUP[rip]
	lea	rsi, .LC2[rip]
	xor	eax, eax
	call	DP@PLT
.L11:
	mov	rdi, rbp
	call	CHIP_IS_E1x@PLT
	test	rax, rax
	jne	.L12
	mov	r13d, DWORD PTR IGU_PF_CONF_FUNC_EN[rip]
	mov	eax, DWORD PTR 0[rbp]
	test	DWORD PTR USING_MSIX_FLAG[rip], eax
	jne	.L13
	or	r13d, DWORD PTR IGU_PF_CONF_SINGLE_ISR_EN[rip]
.L13:
	mov	edi, 20
	call	msleep@PLT
	mov	esi, DWORD PTR PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER[rip]
	mov	edx, 1
	mov	rdi, rbp
	call	REG_WR@PLT
	mov	esi, DWORD PTR IGU_REG_PF_CONFIGURATION[rip]
	mov	edx, r13d
	mov	rdi, rbp
	call	REG_WR@PLT
.L12:
	mov	DWORD PTR 4[rbp], 1
	mov	esi, DWORD PTR BLOCK_PGLUE_B[rip]
	mov	rdi, rbp
	mov	edx, r12d
	call	bnx2x_init_block@PLT
	mov	rdi, rbp
	call	CHIP_IS_E1x@PLT
	test	rax, rax
	je	.L81
.L14:
	mov	esi, DWORD PTR BLOCK_ATC[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_DMAE[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_NIG[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_SRC[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_MISC[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_TCM[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_UCM[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_CCM[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_XCM[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_TSEM[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_USEM[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_CSEM[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_XSEM[rip]
	mov	rdi, rbp
	mov	edx, r12d
	call	bnx2x_init_block@PLT
	mov	rdi, rbp
	call	CHIP_IS_E1x@PLT
	test	rax, rax
	je	.L82
.L15:
	mov	rdi, rbp
	call	CHIP_IS_E1x@PLT
	test	rax, rax
	je	.L83
.L16:
	mov	esi, DWORD PTR BLOCK_QM[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_TM[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_DORQ[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	rdi, rbp
	call	bnx2x_iov_init_dq@PLT
	mov	esi, DWORD PTR BLOCK_BRB1[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_PRS[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_TSDM[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_CSDM[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_USDM[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_XSDM[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_UPB[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_XPB[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_PBF[rip]
	mov	rdi, rbp
	mov	edx, r12d
	call	bnx2x_init_block@PLT
	mov	rdi, rbp
	call	CHIP_IS_E1x@PLT
	test	rax, rax
	je	.L84
.L17:
	mov	esi, DWORD PTR BLOCK_CDU[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	esi, DWORD PTR BLOCK_CFC[rip]
	mov	rdi, rbp
	mov	edx, r12d
	call	bnx2x_init_block@PLT
	mov	rdi, rbp
	call	CHIP_IS_E1x@PLT
	test	rax, rax
	je	.L85
.L18:
	mov	rdi, rbp
	call	IS_MF@PLT
	test	rax, rax
	jne	.L86
.L19:
	mov	esi, DWORD PTR BLOCK_MISC_AEU[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	mov	rax, QWORD PTR INT_BLOCK_HC[rip]
	cmp	QWORD PTR 32[rbp], rax
	je	.L87
	mov	eax, DWORD PTR MISC_REG_AEU_GENERAL_ATTN_12[rip]
	mov	ecx, DWORD PTR 8[rsp]
	xor	edx, edx
	mov	rdi, rbp
	lea	esi, [rax+rcx*4]
	call	REG_WR@PLT
	mov	rdi, rbp
	call	CHIP_IS_E1x@PLT
	test	rax, rax
	je	.L88
.L23:
	mov	esi, DWORD PTR BLOCK_IGU[rip]
	mov	rdi, rbp
	mov	edx, r12d
	call	bnx2x_init_block@PLT
	mov	rdi, rbp
	call	CHIP_IS_E1x@PLT
	test	rax, rax
	je	.L89
.L22:
	mov	edx, -1
	mov	esi, 8468
	mov	rdi, rbp
	call	REG_WR@PLT
	mov	rdi, rbp
	mov	edx, -1
	mov	esi, 8480
	call	REG_WR@PLT
	mov	rdi, rbp
	call	CHIP_IS_E1x@PLT
	test	rax, rax
	jne	.L90
.L42:
	lea	rdi, 24[rbp]
	xor	r13d, r13d
	call	bnx2x_phy_probe@PLT
.L1:
	add	rsp, 24
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	eax, r13d
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L80:
	.cfi_restore_state
	mov	rdi, rbp
	call	bnx2x_init_searcher@PLT
	mov	esi, DWORD PTR PRS_REG_NIC_MODE[rip]
	mov	rdi, rbp
	xor	edx, edx
	call	REG_WR@PLT
	mov	edi, DWORD PTR NETIF_MSG_IFUP[rip]
	lea	rsi, .LC1[rip]
	xor	eax, eax
	call	DP@PLT
	jmp	.L11
	.p2align 4,,10
	.p2align 3
.L79:
	mov	eax, DWORD PTR BNX2X_FIRST_VF_CID[rip]
	cdq
	idiv	DWORD PTR ILT_PAGE_CIDS[rip]
	add	r13d, eax
	jmp	.L7
	.p2align 4,,10
	.p2align 3
.L78:
	mov	rdi, rbp
	call	bnx2x_pf_flr_clnup@PLT
	mov	r13d, eax
	test	eax, eax
	je	.L2
	mov	rdi, rbp
	call	bnx2x_fw_dump@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L87:
	mov	rdi, rbp
	call	CHIP_IS_E1H@PLT
	test	rax, rax
	jne	.L91
.L21:
	mov	esi, DWORD PTR BLOCK_HC[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	bnx2x_init_block@PLT
	jmp	.L22
	.p2align 4,,10
	.p2align 3
.L90:
	mov	eax, DWORD PTR HC_REG_MAIN_MEMORY_SIZE[rip]
	mov	rdi, rbp
	mov	r12d, eax
	shr	r12d, 31
	add	r12d, eax
	call	BP_PORT@PLT
	sar	r12d
	mov	r13d, DWORD PTR HC_REG_HC_PRTY_STS_CLR[rip]
	mov	rdi, rbp
	imul	eax, r12d
	mov	edx, DWORD PTR HC_REG_MAIN_MEMORY[rip]
	mov	esi, r13d
	lea	ebx, [rdx+rax*4]
	call	REG_RD@PLT
	test	eax, eax
	jne	.L92
.L43:
	lea	r12d, [rbx+r12*4]
	cmp	ebx, r12d
	jge	.L45
	.p2align 4,,10
	.p2align 3
.L44:
	mov	edx, 2
	mov	esi, ebx
	mov	rdi, rbp
	call	bnx2x_read_dmae@PLT
	mov	esi, DWORD PTR wb_data[rip]
	mov	rdi, rbp
	call	bnx2x_sp_mapping@PLT
	mov	edx, ebx
	mov	ecx, 2
	mov	rdi, rbp
	mov	esi, eax
	add	ebx, 8
	call	bnx2x_write_dmae@PLT
	cmp	ebx, r12d
	jl	.L44
.L45:
	mov	esi, r13d
	mov	rdi, rbp
	call	REG_RD@PLT
	jmp	.L42
	.p2align 4,,10
	.p2align 3
.L86:
	mov	eax, DWORD PTR 12[rsp]
	mov	esi, DWORD PTR NIG_REG_LLH0_FUNC_EN[rip]
	mov	rdi, rbp
	mov	edx, 1
	lea	ebx, 0[0+rax*8]
	add	esi, ebx
	call	REG_WR@PLT
	add	ebx, DWORD PTR NIG_REG_LLH0_FUNC_VLAN_ID[rip]
	mov	edx, DWORD PTR 8[rbp]
	mov	rdi, rbp
	mov	esi, ebx
	call	REG_WR@PLT
	jmp	.L19
	.p2align 4,,10
	.p2align 3
.L85:
	mov	esi, DWORD PTR CFC_REG_WEAK_ENABLE_PF[rip]
	mov	edx, 1
	mov	rdi, rbp
	call	REG_WR@PLT
	jmp	.L18
	.p2align 4,,10
	.p2align 3
.L84:
	mov	esi, DWORD PTR PBF_REG_DISABLE_PF[rip]
	xor	edx, edx
	mov	rdi, rbp
	call	REG_WR@PLT
	jmp	.L17
	.p2align 4,,10
	.p2align 3
.L83:
	mov	ebx, DWORD PTR 8[rsp]
	mov	edx, DWORD PTR BNX2X_MAX_NUM_OF_VFS[rip]
	mov	rdi, rbp
	mov	esi, DWORD PTR TSEM_REG_VFPF_ERR_NUM[rip]
	add	edx, ebx
	call	REG_WR@PLT
	mov	edx, DWORD PTR BNX2X_MAX_NUM_OF_VFS[rip]
	mov	esi, DWORD PTR USEM_REG_VFPF_ERR_NUM[rip]
	mov	rdi, rbp
	add	edx, ebx
	call	REG_WR@PLT
	mov	edx, DWORD PTR BNX2X_MAX_NUM_OF_VFS[rip]
	mov	esi, DWORD PTR CSEM_REG_VFPF_ERR_NUM[rip]
	mov	rdi, rbp
	add	edx, ebx
	call	REG_WR@PLT
	add	ebx, DWORD PTR BNX2X_MAX_NUM_OF_VFS[rip]
	mov	esi, DWORD PTR XSEM_REG_VFPF_ERR_NUM[rip]
	mov	rdi, rbp
	mov	edx, ebx
	call	REG_WR@PLT
	jmp	.L16
	.p2align 4,,10
	.p2align 3
.L82:
	mov	esi, DWORD PTR QM_REG_PF_EN[rip]
	mov	edx, 1
	mov	rdi, rbp
	call	REG_WR@PLT
	jmp	.L15
	.p2align 4,,10
	.p2align 3
.L81:
	mov	edx, DWORD PTR 8[rsp]
	mov	esi, DWORD PTR PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR[rip]
	mov	rdi, rbp
	call	REG_WR@PLT
	jmp	.L14
	.p2align 4,,10
	.p2align 3
.L88:
	mov	esi, DWORD PTR IGU_REG_LEADING_EDGE_LATCH[rip]
	xor	edx, edx
	mov	rdi, rbp
	call	REG_WR@PLT
	mov	esi, DWORD PTR IGU_REG_TRAILING_EDGE_LATCH[rip]
	xor	edx, edx
	mov	rdi, rbp
	call	REG_WR@PLT
	jmp	.L23
	.p2align 4,,10
	.p2align 3
.L89:
	mov	rdi, rbp
	call	CHIP_INT_MODE_IS_BC@PLT
	mov	r14d, DWORD PTR IGU_BC_NDSB_NUM_SEGS[rip]
	test	rax, rax
	mov	eax, DWORD PTR 12[rbp]
	cmove	r14d, DWORD PTR IGU_NORM_NDSB_NUM_SEGS[rip]
	xor	r13d, r13d
	test	eax, eax
	jle	.L31
	.p2align 4,,10
	.p2align 3
.L26:
	mov	esi, DWORD PTR 16[rbp]
	add	esi, r13d
	mov	r12d, esi
	imul	r12d, r14d
	test	r14d, r14d
	jle	.L29
	lea	ebx, 0[0+r12*4]
	add	r12d, r14d
	sal	r12d, 2
	.p2align 4,,10
	.p2align 3
.L30:
	mov	esi, DWORD PTR IGU_REG_PROD_CONS_MEMORY[rip]
	xor	edx, edx
	mov	rdi, rbp
	add	esi, ebx
	add	ebx, 4
	call	REG_WR@PLT
	cmp	r12d, ebx
	jne	.L30
	mov	esi, DWORD PTR 16[rbp]
	add	esi, r13d
.L29:
	mov	r8d, DWORD PTR IGU_INT_NOP[rip]
	mov	edx, DWORD PTR USTORM_ID[rip]
	mov	r9d, 1
	xor	ecx, ecx
	mov	rdi, rbp
	call	bnx2x_ack_sb@PLT
	mov	esi, DWORD PTR 16[rbp]
	mov	rdi, rbp
	add	esi, r13d
	add	r13d, 1
	call	bnx2x_igu_clear_sb@PLT
	cmp	DWORD PTR 12[rbp], r13d
	jg	.L26
.L31:
	mov	rdi, rbp
	call	CHIP_INT_MODE_IS_BC@PLT
	mov	rdi, rbp
	mov	r13d, DWORD PTR IGU_NORM_DSB_NUM_SEGS[rip]
	test	rax, rax
	cmovne	r13d, DWORD PTR IGU_BC_DSB_NUM_SEGS[rip]
	call	CHIP_MODE_IS_4_PORT@PLT
	test	rax, rax
	jne	.L93
	mov	rdi, rbp
	call	BP_VN@PLT
	mov	rdi, rbp
	mov	r12d, eax
	call	CHIP_INT_MODE_IS_BC@PLT
	test	rax, rax
	je	.L35
.L95:
	add	r12d, DWORD PTR IGU_BC_BASE_DSB_PROD[rip]
.L36:
	mov	eax, DWORD PTR E1HVN_MAX[rip]
	xor	ebx, ebx
	imul	eax, r13d
	test	eax, eax
	jle	.L40
	.p2align 4,,10
	.p2align 3
.L37:
	mov	eax, DWORD PTR IGU_REG_PROD_CONS_MEMORY[rip]
	lea	edx, [r12+rbx]
	mov	rdi, rbp
	lea	esi, [rax+rdx*4]
	xor	edx, edx
	call	REG_WR@PLT
	mov	eax, DWORD PTR E1HVN_MAX[rip]
	add	ebx, eax
	imul	eax, r13d
	cmp	eax, ebx
	jg	.L37
.L40:
	mov	rdi, rbp
	call	CHIP_INT_MODE_IS_BC@PLT
	test	rax, rax
	je	.L94
	mov	esi, DWORD PTR 20[rbp]
	mov	r8d, DWORD PTR IGU_INT_NOP[rip]
	xor	ecx, ecx
	mov	rdi, rbp
	mov	edx, DWORD PTR USTORM_ID[rip]
	mov	r9d, 1
	call	bnx2x_ack_sb@PLT
	mov	esi, DWORD PTR 20[rbp]
	mov	edx, DWORD PTR CSTORM_ID[rip]
	xor	ecx, ecx
	mov	r8d, DWORD PTR IGU_INT_NOP[rip]
	mov	r9d, 1
	mov	rdi, rbp
	call	bnx2x_ack_sb@PLT
	mov	esi, DWORD PTR 20[rbp]
	mov	edx, DWORD PTR XSTORM_ID[rip]
	xor	ecx, ecx
	mov	r8d, DWORD PTR IGU_INT_NOP[rip]
	mov	r9d, 1
	mov	rdi, rbp
	call	bnx2x_ack_sb@PLT
	mov	esi, DWORD PTR 20[rbp]
	mov	edx, DWORD PTR TSTORM_ID[rip]
	xor	ecx, ecx
	mov	r8d, DWORD PTR IGU_INT_NOP[rip]
	mov	r9d, 1
.L76:
	mov	rdi, rbp
	call	bnx2x_ack_sb@PLT
	mov	esi, DWORD PTR 20[rbp]
	mov	edx, DWORD PTR ATTENTION_ID[rip]
	xor	ecx, ecx
	mov	r8d, DWORD PTR IGU_INT_NOP[rip]
	mov	r9d, 1
	mov	rdi, rbp
	call	bnx2x_ack_sb@PLT
	mov	esi, DWORD PTR 20[rbp]
	mov	rdi, rbp
	call	bnx2x_igu_clear_sb@PLT
	mov	esi, DWORD PTR IGU_REG_SB_INT_BEFORE_MASK_LSB[rip]
	xor	edx, edx
	mov	rdi, rbp
	call	REG_WR@PLT
	mov	esi, DWORD PTR IGU_REG_SB_INT_BEFORE_MASK_MSB[rip]
	xor	edx, edx
	mov	rdi, rbp
	call	REG_WR@PLT
	mov	esi, DWORD PTR IGU_REG_SB_MASK_LSB[rip]
	xor	edx, edx
	mov	rdi, rbp
	call	REG_WR@PLT
	mov	esi, DWORD PTR IGU_REG_SB_MASK_MSB[rip]
	xor	edx, edx
	mov	rdi, rbp
	call	REG_WR@PLT
	mov	esi, DWORD PTR IGU_REG_PBA_STATUS_LSB[rip]
	xor	edx, edx
	mov	rdi, rbp
	call	REG_WR@PLT
	mov	esi, DWORD PTR IGU_REG_PBA_STATUS_MSB[rip]
	xor	edx, edx
	mov	rdi, rbp
	call	REG_WR@PLT
	jmp	.L22
.L93:
	mov	rdi, rbp
	call	BP_FUNC@PLT
	mov	rdi, rbp
	mov	r12d, eax
	call	CHIP_INT_MODE_IS_BC@PLT
	test	rax, rax
	jne	.L95
.L35:
	add	r12d, DWORD PTR IGU_NORM_BASE_DSB_PROD[rip]
	jmp	.L36
.L91:
	mov	ecx, DWORD PTR 8[rsp]
	mov	eax, DWORD PTR MISC_REG_AEU_GENERAL_ATTN_12[rip]
	xor	edx, edx
	mov	rdi, rbp
	lea	esi, [rax+rcx*4]
	call	REG_WR@PLT
	mov	r15d, DWORD PTR 12[rsp]
	xor	edx, edx
	mov	rdi, rbp
	mov	esi, DWORD PTR HC_REG_LEADING_EDGE_0[rip]
	sal	r15d, 3
	add	esi, r15d
	call	REG_WR@PLT
	mov	esi, DWORD PTR HC_REG_TRAILING_EDGE_0[rip]
	xor	edx, edx
	mov	rdi, rbp
	add	esi, r15d
	call	REG_WR@PLT
	jmp	.L21
.L92:
	mov	edi, DWORD PTR NETIF_MSG_HW[rip]
	mov	edx, eax
	lea	rsi, .LC3[rip]
	xor	eax, eax
	call	DP@PLT
	jmp	.L43
.L94:
	mov	esi, DWORD PTR 20[rbp]
	mov	r8d, DWORD PTR IGU_INT_NOP[rip]
	mov	r9d, 1
	xor	ecx, ecx
	mov	edx, DWORD PTR USTORM_ID[rip]
	jmp	.L76
	.cfi_endproc
.LFE0:
	.size	bnx2x_init_hw_func, .-bnx2x_init_hw_func
	.comm	wb_data,4,4
	.comm	XSTORM_ID,4,4
	.comm	XSEM_REG_VFPF_ERR_NUM,4,4
	.comm	USTORM_ID,4,4
	.comm	USING_MSIX_FLAG,4,4
	.comm	USEM_REG_VFPF_ERR_NUM,4,4
	.comm	TSTORM_ID,4,4
	.comm	TSEM_REG_VFPF_ERR_NUM,4,4
	.comm	QM_REG_PF_EN,4,4
	.comm	PRS_REG_NIC_MODE,4,4
	.comm	PHASE_PF0,4,4
	.comm	PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,4,4
	.comm	PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,4,4
	.comm	PBF_REG_DISABLE_PF,4,4
	.comm	NIG_REG_LLH0_FUNC_VLAN_ID,4,4
	.comm	NIG_REG_LLH0_FUNC_EN,4,4
	.comm	NETIF_MSG_IFUP,4,4
	.comm	NETIF_MSG_HW,4,4
	.comm	MISC_REG_AEU_GENERAL_ATTN_12,4,4
	.comm	INT_BLOCK_HC,8,8
	.comm	INITOP_SET,4,4
	.comm	ILT_PAGE_CIDS,4,4
	.comm	ILT_CLIENT_CDU,8,8
	.comm	IGU_REG_TRAILING_EDGE_LATCH,4,4
	.comm	IGU_REG_SB_MASK_MSB,4,4
	.comm	IGU_REG_SB_MASK_LSB,4,4
	.comm	IGU_REG_SB_INT_BEFORE_MASK_MSB,4,4
	.comm	IGU_REG_SB_INT_BEFORE_MASK_LSB,4,4
	.comm	IGU_REG_PROD_CONS_MEMORY,4,4
	.comm	IGU_REG_PF_CONFIGURATION,4,4
	.comm	IGU_REG_PBA_STATUS_MSB,4,4
	.comm	IGU_REG_PBA_STATUS_LSB,4,4
	.comm	IGU_REG_LEADING_EDGE_LATCH,4,4
	.comm	IGU_PF_CONF_SINGLE_ISR_EN,4,4
	.comm	IGU_PF_CONF_FUNC_EN,4,4
	.comm	IGU_NORM_NDSB_NUM_SEGS,4,4
	.comm	IGU_NORM_DSB_NUM_SEGS,4,4
	.comm	IGU_NORM_BASE_DSB_PROD,4,4
	.comm	IGU_INT_NOP,4,4
	.comm	IGU_BC_NDSB_NUM_SEGS,4,4
	.comm	IGU_BC_DSB_NUM_SEGS,4,4
	.comm	IGU_BC_BASE_DSB_PROD,4,4
	.comm	HC_REG_TRAILING_EDGE_0,4,4
	.comm	HC_REG_MAIN_MEMORY_SIZE,4,4
	.comm	HC_REG_MAIN_MEMORY,4,4
	.comm	HC_REG_LEADING_EDGE_0,4,4
	.comm	HC_REG_HC_PRTY_STS_CLR,4,4
	.comm	HC_REG_CONFIG_1,4,4
	.comm	HC_REG_CONFIG_0,4,4
	.comm	HC_CONFIG_0_REG_MSI_ATTN_EN_0,4,4
	.comm	E1HVN_MAX,4,4
	.comm	CSTORM_ID,4,4
	.comm	CSEM_REG_VFPF_ERR_NUM,4,4
	.comm	CFC_REG_WEAK_ENABLE_PF,4,4
	.comm	BNX2X_MAX_NUM_OF_VFS,4,4
	.comm	BNX2X_FIRST_VF_CID,4,4
	.comm	BLOCK_XSEM,4,4
	.comm	BLOCK_XSDM,4,4
	.comm	BLOCK_XPB,4,4
	.comm	BLOCK_XCM,4,4
	.comm	BLOCK_USEM,4,4
	.comm	BLOCK_USDM,4,4
	.comm	BLOCK_UPB,4,4
	.comm	BLOCK_UCM,4,4
	.comm	BLOCK_TSEM,4,4
	.comm	BLOCK_TSDM,4,4
	.comm	BLOCK_TM,4,4
	.comm	BLOCK_TCM,4,4
	.comm	BLOCK_SRC,4,4
	.comm	BLOCK_QM,4,4
	.comm	BLOCK_PXP2,4,4
	.comm	BLOCK_PXP,4,4
	.comm	BLOCK_PRS,4,4
	.comm	BLOCK_PGLUE_B,4,4
	.comm	BLOCK_PBF,4,4
	.comm	BLOCK_NIG,4,4
	.comm	BLOCK_MISC_AEU,4,4
	.comm	BLOCK_MISC,4,4
	.comm	BLOCK_IGU,4,4
	.comm	BLOCK_HC,4,4
	.comm	BLOCK_DORQ,4,4
	.comm	BLOCK_DMAE,4,4
	.comm	BLOCK_CSEM,4,4
	.comm	BLOCK_CSDM,4,4
	.comm	BLOCK_CFC,4,4
	.comm	BLOCK_CDU,4,4
	.comm	BLOCK_CCM,4,4
	.comm	BLOCK_BRB1,4,4
	.comm	BLOCK_ATC,4,4
	.comm	BAR_XSTRORM_INTMEM,8,8
	.comm	BAR_USTRORM_INTMEM,8,8
	.comm	BAR_TSTRORM_INTMEM,8,8
	.comm	BAR_CSTRORM_INTMEM,8,8
	.comm	ATTENTION_ID,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_bnx2x_main.c_bnx2x_init_hw_func.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"starting func init  func %d\012\000"
	.global	__aeabi_idiv
	.align	2
.LC1:
	.ascii	"NIC MODE disabled\012\000"
	.align	2
.LC2:
	.ascii	"NIC MODE configured\012\000"
	.align	2
.LC3:
	.ascii	"Hmmm... Parity errors in HC block during function i"
	.ascii	"nit (0x%x)!\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	bnx2x_init_hw_func, %function
bnx2x_init_hw_func:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	sub	sp, sp, #20
	mov	r4, r0
	bl	BP_PORT
	mov	r9, r0
	mov	r0, r4
	bl	BP_FUNC
	mov	r8, r0
	ldr	r3, .L93
	mov	r0, r4
	ldr	r6, [r3]
	bl	BP_ILT
	ldr	r3, .L93+4
	mov	r2, r8
	ldr	r0, [r3]
	ldr	r1, .L93+8
	bl	DP
	mov	r0, r4
	bl	CHIP_IS_E1x
	cmp	r0, #0
	add	r6, r8, r6
	beq	.L75
.L2:
	ldr	r10, .L93+12
	ldr	r2, [r4, #28]
	ldr	r3, [r10]
	cmp	r2, r3
	bne	.L4
	cmp	r9, #0
	ldrne	r3, .L93+16
	ldreq	r3, .L93+20
	mov	r0, r4
	ldr	r5, [r3]
	mov	r1, r5
	bl	REG_RD
	mov	r2, r0
	ldr	r3, .L93+24
	mov	r1, r5
	ldr	r3, [r3]
	mov	r0, r4
	orr	r2, r2, r3
	bl	REG_WR
.L4:
	ldr	r3, .L93+28
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+32
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	mov	r0, r4
	bl	BP_ILT
	ldr	r5, .L93+36
	ldr	r3, [r0, #4]
	ldr	r2, [r5]
	mov	r7, r0
	mov	r0, r4
	ldr	fp, [r3, r2, lsl #2]
	bl	IS_SRIOV
	cmp	r0, #0
	bne	.L76
.L7:
	mov	r1, fp
	mov	r0, r4
	bl	bnx2x_iov_init_ilt
	ldr	r2, [r5]
	ldr	r3, [r7, #4]
	mov	r5, #0
	ldr	r3, [r3, r2, lsl #2]
	add	r3, r3, r3, lsl #1
	lsl	fp, r3, #2
	b	.L8
.L9:
	ldr	r1, [r4, #32]
	add	r0, r5, r5, lsl #1
	ldr	r3, [r7]
	add	r2, r1, r0, lsl #2
	ldr	r1, [r1, r0, lsl #2]
	ldmib	r2, {r0, ip}
	add	r2, r3, fp
	stmib	r2, {r0, ip}
	add	r5, r5, #1
	str	r1, [r3, fp]
	add	fp, fp, #12
.L8:
	mov	r0, r4
	bl	L2_ILT_LINES
	cmp	r0, r5
	bgt	.L9
	ldr	r3, .L93+40
	mov	r0, r4
	ldr	r1, [r3]
	bl	bnx2x_ilt_init_op
	mov	r0, r4
	bl	CONFIGURE_NIC_MODE
	subs	r5, r0, #0
	beq	.L77
	ldr	r3, .L93+44
	mov	r2, #1
	ldr	r1, [r3]
	mov	r0, r4
	bl	REG_WR
	ldr	r3, .L93+48
	ldr	r1, .L93+52
	ldr	r0, [r3]
	bl	DP
.L11:
	mov	r0, r4
	bl	CHIP_IS_E1x
	cmp	r0, #0
	bne	.L12
	ldr	r3, .L93+56
	ldr	r1, [r4]
	ldr	r2, [r3]
	ldr	r3, .L93+60
	tst	r1, r2
	ldr	r5, [r3]
	ldreq	r3, .L93+64
	mov	r0, #20
	ldreq	r3, [r3]
	orreq	r5, r5, r3
	bl	msleep
	ldr	r3, .L93+68
	mov	r2, #1
	ldr	r1, [r3]
	mov	r0, r4
	bl	REG_WR
	ldr	r3, .L93+72
	mov	r2, r5
	mov	r0, r4
	ldr	r1, [r3]
	bl	REG_WR
.L12:
	mov	r2, #1
	ldr	r3, .L93+76
	str	r2, [r4, #4]
	ldr	r1, [r3]
	mov	r2, r6
	mov	r0, r4
	bl	bnx2x_init_block
	mov	r0, r4
	bl	CHIP_IS_E1x
	cmp	r0, #0
	beq	.L78
.L14:
	ldr	r3, .L93+80
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+84
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+88
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+92
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+96
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+100
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+104
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+108
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+112
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+116
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+120
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+124
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+128
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	mov	r0, r4
	bl	CHIP_IS_E1x
	cmp	r0, #0
	beq	.L79
	mov	r0, r4
	bl	CHIP_IS_E1x
	cmp	r0, #0
	beq	.L80
.L16:
	ldr	r3, .L93+132
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+136
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+140
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	mov	r0, r4
	bl	bnx2x_iov_init_dq
	ldr	r3, .L93+144
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+148
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+152
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+156
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+160
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+164
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+168
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+172
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+176
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	mov	r0, r4
	bl	CHIP_IS_E1x
	subs	r2, r0, #0
	beq	.L81
.L17:
	ldr	r3, .L93+180
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, .L93+184
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	mov	r0, r4
	bl	CHIP_IS_E1x
	cmp	r0, #0
	beq	.L82
.L18:
	mov	r0, r4
	bl	IS_MF
	cmp	r0, #0
	bne	.L83
.L19:
	ldr	r3, .L93+188
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	ldr	r3, [r10]
	ldr	r2, [r4, #28]
	cmp	r2, r3
	beq	.L84
	ldr	r3, .L93+192
	mov	r2, #0
	ldr	r1, [r3]
	mov	r0, r4
	add	r1, r1, r8, lsl #2
	bl	REG_WR
	mov	r0, r4
	bl	CHIP_IS_E1x
	subs	r5, r0, #0
	beq	.L85
.L23:
	ldr	r3, .L93+196
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r4
	bl	bnx2x_init_block
	mov	r0, r4
	bl	CHIP_IS_E1x
	subs	r8, r0, #0
	beq	.L86
.L22:
	mvn	r2, #0
	ldr	r1, .L93+200
	mov	r0, r4
	bl	REG_WR
	mvn	r2, #0
	ldr	r1, .L93+204
	mov	r0, r4
	bl	REG_WR
	mov	r0, r4
	bl	CHIP_IS_E1x
	cmp	r0, #0
	bne	.L87
.L42:
	add	r0, r4, #24
	bl	bnx2x_phy_probe
	mov	r5, #0
.L1:
	mov	r0, r5
	add	sp, sp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L77:
	mov	r0, r4
	bl	bnx2x_init_searcher
	ldr	r3, .L93+44
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	REG_WR
	ldr	r3, .L93+48
	ldr	r1, .L93+208
	ldr	r0, [r3]
	bl	DP
	b	.L11
.L76:
	ldr	r1, .L93+212
	ldr	r2, .L93+216
	ldr	r0, [r1]
	ldr	r1, [r2]
	bl	__aeabi_idiv
	add	fp, fp, r0
	b	.L7
.L75:
	mov	r0, r4
	bl	bnx2x_pf_flr_clnup
	subs	r5, r0, #0
	beq	.L2
	mov	r0, r4
	bl	bnx2x_fw_dump
	b	.L1
.L84:
	mov	r0, r4
	bl	CHIP_IS_E1H
	cmp	r0, #0
	bne	.L88
.L21:
	ldr	r3, .L93+220
	mov	r2, r6
	mov	r0, r4
	ldr	r1, [r3]
	bl	bnx2x_init_block
	b	.L22
.L79:
	ldr	r3, .L93+224
	mov	r2, #1
	ldr	r1, [r3]
	mov	r0, r4
	bl	REG_WR
	mov	r0, r4
	bl	CHIP_IS_E1x
	cmp	r0, #0
	bne	.L16
.L80:
	ldr	r5, .L93+228
	ldr	r3, .L93+232
	ldr	r2, [r5]
	ldr	r1, [r3]
	add	r2, r8, r2
	mov	r0, r4
	bl	REG_WR
	ldr	r2, [r5]
	ldr	r3, .L93+236
	add	r2, r8, r2
	ldr	r1, [r3]
	mov	r0, r4
	bl	REG_WR
	ldr	r2, [r5]
	ldr	r3, .L93+240
	add	r2, r8, r2
	ldr	r1, [r3]
	mov	r0, r4
	bl	REG_WR
	ldr	r2, [r5]
	ldr	r3, .L93+244
	mov	r0, r4
	ldr	r1, [r3]
	add	r2, r8, r2
	bl	REG_WR
	b	.L16
.L78:
	ldr	r3, .L93+248
	mov	r2, r8
	mov	r0, r4
	ldr	r1, [r3]
	bl	REG_WR
	b	.L14
.L87:
	ldr	r3, .L93+252
	mov	r0, r4
	ldr	r6, [r3]
	bl	BP_PORT
	add	r6, r6, r6, lsr #31
	ldr	r1, .L93+256
	asr	r6, r6, #1
	mul	r3, r6, r0
	ldr	r2, .L93+260
	ldr	r8, [r1]
	ldr	r5, [r2]
	mov	r1, r8
	mov	r0, r4
	add	r5, r5, r3, lsl #2
	bl	REG_RD
	subs	r2, r0, #0
	bne	.L89
.L43:
	add	r6, r5, r6, lsl #2
	cmp	r5, r6
	bge	.L45
	ldr	r7, .L93+264
.L44:
	mov	r2, #2
	mov	r1, r5
	mov	r0, r4
	bl	bnx2x_read_dmae
	ldr	r1, [r7]
	mov	r0, r4
	bl	bnx2x_sp_mapping
	mov	r2, r5
	mov	r1, r0
	mov	r3, #2
	mov	r0, r4
	add	r5, r5, #8
	bl	bnx2x_write_dmae
	cmp	r5, r6
	blt	.L44
.L45:
	mov	r1, r8
	mov	r0, r4
	bl	REG_RD
	b	.L42
.L83:
	ldr	r3, .L93+268
	mov	r2, #1
	ldr	r1, [r3]
	mov	r0, r4
	add	r1, r1, r9, lsl #3
	bl	REG_WR
	ldr	r2, .L93+272
	lsl	r3, r9, #3
	ldr	r1, [r2]
	mov	r0, r4
	ldr	r2, [r4, #8]
	add	r1, r3, r1
	bl	REG_WR
	b	.L19
.L82:
	ldr	r3, .L93+276
	mov	r2, #1
	mov	r0, r4
	ldr	r1, [r3]
	bl	REG_WR
	b	.L18
.L81:
	ldr	r3, .L93+280
	mov	r0, r4
	ldr	r1, [r3]
	bl	REG_WR
	b	.L17
.L85:
	ldr	r3, .L93+284
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r4
	bl	REG_WR
	ldr	r3, .L93+288
	mov	r2, r5
	mov	r0, r4
	ldr	r1, [r3]
	bl	REG_WR
	b	.L23
.L86:
	mov	r0, r4
	bl	CHIP_INT_MODE_IS_BC
	cmp	r0, #0
	ldrne	r3, .L93+292
	ldreq	r3, .L93+296
	ldr	r9, [r3]
	ldr	r3, [r4, #12]
	cmp	r3, #0
	ble	.L90
	mov	r7, #0
	ldr	fp, .L93+300
	ldr	r10, .L93+304
	ldr	r6, .L93+308
	str	fp, [sp, #8]
	str	r8, [sp, #12]
.L26:
	ldr	r1, [r4, #16]
	cmp	r9, #0
	add	r1, r7, r1
	mul	r3, r9, r1
	ble	.L29
	add	r5, r3, r9
	lsl	r5, r5, #2
	lsl	r8, r3, #2
.L30:
	ldr	r1, [r6]
	mov	r2, #0
	add	r1, r8, r1
	mov	r0, r4
	add	r8, r8, #4
	bl	REG_WR
	cmp	r5, r8
	bne	.L30
	ldr	r1, [r4, #16]
	add	r1, r7, r1
.L29:
	mov	r2, #1
	ldr	r3, [r10]
	str	r2, [sp, #4]
	str	r3, [sp]
	ldr	r2, [fp]
	mov	r3, #0
	mov	r0, r4
	bl	bnx2x_ack_sb
	ldr	r1, [r4, #16]
	mov	r0, r4
	add	r1, r7, r1
	bl	bnx2x_igu_clear_sb
	ldr	r3, [r4, #12]
	add	r7, r7, #1
	cmp	r3, r7
	bgt	.L26
	ldr	r8, [sp, #12]
.L31:
	mov	r0, r4
	bl	CHIP_INT_MODE_IS_BC
	cmp	r0, #0
	beq	.L91
	ldr	r3, .L93+312
	ldr	r7, [r3]
.L32:
	mov	r0, r4
	bl	CHIP_MODE_IS_4_PORT
	cmp	r0, #0
	mov	r0, r4
	beq	.L33
	bl	BP_FUNC
	mov	r5, r0
.L34:
	mov	r0, r4
	bl	CHIP_INT_MODE_IS_BC
	cmp	r0, #0
	ldrne	r3, .L93+316
	ldreq	r3, .L93+320
	ldr	r6, .L93+324
	ldr	r3, [r3]
	add	r5, r5, r3
	ldr	r3, [r6]
	mul	r3, r7, r3
	cmp	r3, #0
	ble	.L40
	ldr	r9, .L93+308
.L37:
	ldr	r3, [r9]
	add	r1, r5, r8
	mov	r2, #0
	add	r1, r3, r1, lsl #2
	mov	r0, r4
	bl	REG_WR
	ldr	r3, [r6]
	mul	r2, r7, r3
	add	r8, r8, r3
	cmp	r2, r8
	bgt	.L37
.L40:
	mov	r0, r4
	bl	CHIP_INT_MODE_IS_BC
	subs	r5, r0, #0
	beq	.L92
	mov	r5, #1
	ldr	r3, [r10]
	ldr	r2, [sp, #8]
	mov	r0, r4
	ldr	r2, [r2]
	stm	sp, {r3, r5}
	mov	r3, #0
	ldr	r1, [r4, #20]
	bl	bnx2x_ack_sb
	ldr	r3, [r10]
	ldr	r2, .L93+328
	str	r5, [sp, #4]
	ldr	r2, [r2]
	str	r3, [sp]
	ldr	r1, [r4, #20]
	mov	r3, #0
	mov	r0, r4
	bl	bnx2x_ack_sb
	ldr	r3, [r10]
	ldr	r2, .L93+332
	str	r5, [sp, #4]
	ldr	r2, [r2]
	str	r3, [sp]
	ldr	r1, [r4, #20]
	mov	r3, #0
	mov	r0, r4
	bl	bnx2x_ack_sb
	ldr	r3, [r10]
	ldr	r2, .L93+336
	str	r5, [sp, #4]
	ldr	r2, [r2]
	str	r3, [sp]
	ldr	r1, [r4, #20]
	mov	r3, #0
	mov	r0, r4
	bl	bnx2x_ack_sb
	ldr	r2, [r10]
	ldr	r3, .L93+340
	stm	sp, {r2, r5}
	mov	r0, r4
	ldr	r2, [r3]
	ldr	r1, [r4, #20]
	mov	r3, #0
	bl	bnx2x_ack_sb
.L41:
	ldr	r1, [r4, #20]
	mov	r0, r4
	bl	bnx2x_igu_clear_sb
	ldr	r3, .L93+344
	mov	r2, #0
	ldr	r1, [r3]
	mov	r0, r4
	bl	REG_WR
	ldr	r3, .L93+348
	mov	r2, #0
	ldr	r1, [r3]
	mov	r0, r4
	bl	REG_WR
	ldr	r3, .L93+352
	mov	r2, #0
	ldr	r1, [r3]
	mov	r0, r4
	bl	REG_WR
	ldr	r3, .L93+356
	mov	r2, #0
	ldr	r1, [r3]
	mov	r0, r4
	bl	REG_WR
	ldr	r3, .L93+360
	mov	r2, #0
	ldr	r1, [r3]
	mov	r0, r4
	bl	REG_WR
	ldr	r3, .L93+364
	mov	r2, #0
	mov	r0, r4
	ldr	r1, [r3]
	bl	REG_WR
	b	.L22
.L88:
	ldr	r3, .L93+192
	mov	r2, #0
	ldr	r1, [r3]
	mov	r0, r4
	add	r1, r1, r8, lsl #2
	bl	REG_WR
	ldr	r3, .L93+368
	mov	r2, #0
	ldr	r1, [r3]
	mov	r0, r4
	add	r1, r1, r9, lsl #3
	bl	REG_WR
	ldr	r3, .L93+372
	lsl	r9, r9, #3
	ldr	r1, [r3]
	mov	r2, #0
	mov	r0, r4
	add	r1, r9, r1
	bl	REG_WR
	b	.L21
.L92:
	mov	r6, #1
	ldr	r3, [r10]
	ldr	r2, [sp, #8]
	mov	r0, r4
	ldr	r2, [r2]
	stm	sp, {r3, r6}
	mov	r3, r5
	ldr	r1, [r4, #20]
	bl	bnx2x_ack_sb
	ldr	r3, [r10]
	ldr	r2, .L93+340
	stm	sp, {r3, r6}
	mov	r0, r4
	mov	r3, r5
	ldr	r2, [r2]
	ldr	r1, [r4, #20]
	bl	bnx2x_ack_sb
	b	.L41
.L89:
	ldr	r3, .L93+4
	ldr	r1, .L93+376
	ldr	r0, [r3]
	bl	DP
	b	.L43
.L33:
	bl	BP_VN
	mov	r5, r0
	b	.L34
.L91:
	ldr	r3, .L93+380
	ldr	r7, [r3]
	b	.L32
.L90:
	ldr	r3, .L93+300
	ldr	r10, .L93+304
	str	r3, [sp, #8]
	b	.L31
.L94:
	.align	2
.L93:
	.word	PHASE_PF0
	.word	NETIF_MSG_HW
	.word	.LC0
	.word	INT_BLOCK_HC
	.word	HC_REG_CONFIG_1
	.word	HC_REG_CONFIG_0
	.word	HC_CONFIG_0_REG_MSI_ATTN_EN_0
	.word	BLOCK_PXP
	.word	BLOCK_PXP2
	.word	ILT_CLIENT_CDU
	.word	INITOP_SET
	.word	PRS_REG_NIC_MODE
	.word	NETIF_MSG_IFUP
	.word	.LC2
	.word	USING_MSIX_FLAG
	.word	IGU_PF_CONF_FUNC_EN
	.word	IGU_PF_CONF_SINGLE_ISR_EN
	.word	PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
	.word	IGU_REG_PF_CONFIGURATION
	.word	BLOCK_PGLUE_B
	.word	BLOCK_ATC
	.word	BLOCK_DMAE
	.word	BLOCK_NIG
	.word	BLOCK_SRC
	.word	BLOCK_MISC
	.word	BLOCK_TCM
	.word	BLOCK_UCM
	.word	BLOCK_CCM
	.word	BLOCK_XCM
	.word	BLOCK_TSEM
	.word	BLOCK_USEM
	.word	BLOCK_CSEM
	.word	BLOCK_XSEM
	.word	BLOCK_QM
	.word	BLOCK_TM
	.word	BLOCK_DORQ
	.word	BLOCK_BRB1
	.word	BLOCK_PRS
	.word	BLOCK_TSDM
	.word	BLOCK_CSDM
	.word	BLOCK_USDM
	.word	BLOCK_XSDM
	.word	BLOCK_UPB
	.word	BLOCK_XPB
	.word	BLOCK_PBF
	.word	BLOCK_CDU
	.word	BLOCK_CFC
	.word	BLOCK_MISC_AEU
	.word	MISC_REG_AEU_GENERAL_ATTN_12
	.word	BLOCK_IGU
	.word	8468
	.word	8480
	.word	.LC1
	.word	BNX2X_FIRST_VF_CID
	.word	ILT_PAGE_CIDS
	.word	BLOCK_HC
	.word	QM_REG_PF_EN
	.word	BNX2X_MAX_NUM_OF_VFS
	.word	TSEM_REG_VFPF_ERR_NUM
	.word	USEM_REG_VFPF_ERR_NUM
	.word	CSEM_REG_VFPF_ERR_NUM
	.word	XSEM_REG_VFPF_ERR_NUM
	.word	PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR
	.word	HC_REG_MAIN_MEMORY_SIZE
	.word	HC_REG_HC_PRTY_STS_CLR
	.word	HC_REG_MAIN_MEMORY
	.word	wb_data
	.word	NIG_REG_LLH0_FUNC_EN
	.word	NIG_REG_LLH0_FUNC_VLAN_ID
	.word	CFC_REG_WEAK_ENABLE_PF
	.word	PBF_REG_DISABLE_PF
	.word	IGU_REG_LEADING_EDGE_LATCH
	.word	IGU_REG_TRAILING_EDGE_LATCH
	.word	IGU_BC_NDSB_NUM_SEGS
	.word	IGU_NORM_NDSB_NUM_SEGS
	.word	USTORM_ID
	.word	IGU_INT_NOP
	.word	IGU_REG_PROD_CONS_MEMORY
	.word	IGU_BC_DSB_NUM_SEGS
	.word	IGU_BC_BASE_DSB_PROD
	.word	IGU_NORM_BASE_DSB_PROD
	.word	E1HVN_MAX
	.word	CSTORM_ID
	.word	XSTORM_ID
	.word	TSTORM_ID
	.word	ATTENTION_ID
	.word	IGU_REG_SB_INT_BEFORE_MASK_LSB
	.word	IGU_REG_SB_INT_BEFORE_MASK_MSB
	.word	IGU_REG_SB_MASK_LSB
	.word	IGU_REG_SB_MASK_MSB
	.word	IGU_REG_PBA_STATUS_LSB
	.word	IGU_REG_PBA_STATUS_MSB
	.word	HC_REG_LEADING_EDGE_0
	.word	HC_REG_TRAILING_EDGE_0
	.word	.LC3
	.word	IGU_NORM_DSB_NUM_SEGS
	.size	bnx2x_init_hw_func, .-bnx2x_init_hw_func
	.comm	wb_data,4,4
	.comm	XSTORM_ID,4,4
	.comm	XSEM_REG_VFPF_ERR_NUM,4,4
	.comm	USTORM_ID,4,4
	.comm	USING_MSIX_FLAG,4,4
	.comm	USEM_REG_VFPF_ERR_NUM,4,4
	.comm	TSTORM_ID,4,4
	.comm	TSEM_REG_VFPF_ERR_NUM,4,4
	.comm	QM_REG_PF_EN,4,4
	.comm	PRS_REG_NIC_MODE,4,4
	.comm	PHASE_PF0,4,4
	.comm	PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,4,4
	.comm	PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,4,4
	.comm	PBF_REG_DISABLE_PF,4,4
	.comm	NIG_REG_LLH0_FUNC_VLAN_ID,4,4
	.comm	NIG_REG_LLH0_FUNC_EN,4,4
	.comm	NETIF_MSG_IFUP,4,4
	.comm	NETIF_MSG_HW,4,4
	.comm	MISC_REG_AEU_GENERAL_ATTN_12,4,4
	.comm	INT_BLOCK_HC,4,4
	.comm	INITOP_SET,4,4
	.comm	ILT_PAGE_CIDS,4,4
	.comm	ILT_CLIENT_CDU,4,4
	.comm	IGU_REG_TRAILING_EDGE_LATCH,4,4
	.comm	IGU_REG_SB_MASK_MSB,4,4
	.comm	IGU_REG_SB_MASK_LSB,4,4
	.comm	IGU_REG_SB_INT_BEFORE_MASK_MSB,4,4
	.comm	IGU_REG_SB_INT_BEFORE_MASK_LSB,4,4
	.comm	IGU_REG_PROD_CONS_MEMORY,4,4
	.comm	IGU_REG_PF_CONFIGURATION,4,4
	.comm	IGU_REG_PBA_STATUS_MSB,4,4
	.comm	IGU_REG_PBA_STATUS_LSB,4,4
	.comm	IGU_REG_LEADING_EDGE_LATCH,4,4
	.comm	IGU_PF_CONF_SINGLE_ISR_EN,4,4
	.comm	IGU_PF_CONF_FUNC_EN,4,4
	.comm	IGU_NORM_NDSB_NUM_SEGS,4,4
	.comm	IGU_NORM_DSB_NUM_SEGS,4,4
	.comm	IGU_NORM_BASE_DSB_PROD,4,4
	.comm	IGU_INT_NOP,4,4
	.comm	IGU_BC_NDSB_NUM_SEGS,4,4
	.comm	IGU_BC_DSB_NUM_SEGS,4,4
	.comm	IGU_BC_BASE_DSB_PROD,4,4
	.comm	HC_REG_TRAILING_EDGE_0,4,4
	.comm	HC_REG_MAIN_MEMORY_SIZE,4,4
	.comm	HC_REG_MAIN_MEMORY,4,4
	.comm	HC_REG_LEADING_EDGE_0,4,4
	.comm	HC_REG_HC_PRTY_STS_CLR,4,4
	.comm	HC_REG_CONFIG_1,4,4
	.comm	HC_REG_CONFIG_0,4,4
	.comm	HC_CONFIG_0_REG_MSI_ATTN_EN_0,4,4
	.comm	E1HVN_MAX,4,4
	.comm	CSTORM_ID,4,4
	.comm	CSEM_REG_VFPF_ERR_NUM,4,4
	.comm	CFC_REG_WEAK_ENABLE_PF,4,4
	.comm	BNX2X_MAX_NUM_OF_VFS,4,4
	.comm	BNX2X_FIRST_VF_CID,4,4
	.comm	BLOCK_XSEM,4,4
	.comm	BLOCK_XSDM,4,4
	.comm	BLOCK_XPB,4,4
	.comm	BLOCK_XCM,4,4
	.comm	BLOCK_USEM,4,4
	.comm	BLOCK_USDM,4,4
	.comm	BLOCK_UPB,4,4
	.comm	BLOCK_UCM,4,4
	.comm	BLOCK_TSEM,4,4
	.comm	BLOCK_TSDM,4,4
	.comm	BLOCK_TM,4,4
	.comm	BLOCK_TCM,4,4
	.comm	BLOCK_SRC,4,4
	.comm	BLOCK_QM,4,4
	.comm	BLOCK_PXP2,4,4
	.comm	BLOCK_PXP,4,4
	.comm	BLOCK_PRS,4,4
	.comm	BLOCK_PGLUE_B,4,4
	.comm	BLOCK_PBF,4,4
	.comm	BLOCK_NIG,4,4
	.comm	BLOCK_MISC_AEU,4,4
	.comm	BLOCK_MISC,4,4
	.comm	BLOCK_IGU,4,4
	.comm	BLOCK_HC,4,4
	.comm	BLOCK_DORQ,4,4
	.comm	BLOCK_DMAE,4,4
	.comm	BLOCK_CSEM,4,4
	.comm	BLOCK_CSDM,4,4
	.comm	BLOCK_CFC,4,4
	.comm	BLOCK_CDU,4,4
	.comm	BLOCK_CCM,4,4
	.comm	BLOCK_BRB1,4,4
	.comm	BLOCK_ATC,4,4
	.comm	BAR_XSTRORM_INTMEM,4,4
	.comm	BAR_USTRORM_INTMEM,4,4
	.comm	BAR_TSTRORM_INTMEM,4,4
	.comm	BAR_CSTRORM_INTMEM,4,4
	.comm	ATTENTION_ID,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
