	.file	"extr_rs780_dpm.c_rs780_set_engine_clock_scaling.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	rs780_set_engine_clock_scaling, @function
rs780_set_engine_clock_scaling:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	mov	r13, rdi
	mov	rdi, rsi
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	mov	rbp, rdx
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	sub	rsp, 104
	.cfi_def_cfa_offset 144
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 88[rsp], rax
	xor	eax, eax
	call	rs780_get_ps@PLT
	mov	rdi, rbp
	mov	rbx, rax
	call	rs780_get_ps@PLT
	mov	rdx, QWORD PTR 8[rbx]
	mov	rbp, rax
	mov	rax, QWORD PTR [rax]
	cmp	QWORD PTR [rbx], rax
	jne	.L3
	cmp	rdx, QWORD PTR 8[rbp]
	je	.L7
.L3:
	mov	esi, DWORD PTR COMPUTE_ENGINE_PLL_PARAM[rip]
	mov	r8, rsp
	xor	ecx, ecx
	mov	rdi, r13
	call	radeon_atom_get_clock_dividers@PLT
	mov	r12d, eax
	test	eax, eax
	je	.L11
.L1:
	mov	rax, QWORD PTR 88[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L12
	add	rsp, 104
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	eax, r12d
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L11:
	.cfi_restore_state
	mov	rdx, QWORD PTR [rbx]
	mov	esi, DWORD PTR COMPUTE_ENGINE_PLL_PARAM[rip]
	lea	r8, 32[rsp]
	xor	ecx, ecx
	mov	rdi, r13
	call	radeon_atom_get_clock_dividers@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L1
	mov	rdx, QWORD PTR 0[rbp]
	mov	esi, DWORD PTR COMPUTE_ENGINE_PLL_PARAM[rip]
	xor	ecx, ecx
	mov	rdi, r13
	lea	r8, 64[rsp]
	call	radeon_atom_get_clock_dividers@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L1
	mov	rax, QWORD PTR 32[rsp]
	cmp	QWORD PTR [rsp], rax
	jne	.L5
	mov	rdx, QWORD PTR 40[rsp]
	cmp	QWORD PTR 8[rsp], rdx
	jne	.L5
	cmp	rax, QWORD PTR 64[rsp]
	jne	.L5
	cmp	rdx, QWORD PTR 72[rsp]
	jne	.L5
	mov	rsi, QWORD PTR 48[rsp]
	mov	rdi, r13
	call	rs780_force_fbdiv@PLT
	mov	rdi, QWORD PTR 16[rsp]
	cmp	QWORD PTR 48[rsp], rdi
	jle	.L7
	mov	r13d, DWORD PTR MIN_FEEDBACK_DIV_MASK[rip]
	or	r13d, DWORD PTR MAX_FEEDBACK_DIV_MASK[rip]
	call	MIN_FEEDBACK_DIV@PLT
	mov	rdi, QWORD PTR 48[rsp]
	not	r13d
	mov	ebx, eax
	call	MAX_FEEDBACK_DIV@PLT
	mov	edi, DWORD PTR FVTHROT_FBDIV_REG0[rip]
	mov	edx, r13d
	or	ebx, eax
	mov	esi, ebx
	call	WREG32_P@PLT
	mov	edx, DWORD PTR FORCE_FEEDBACK_DIV[rip]
	mov	edi, DWORD PTR FVTHROT_FBDIV_REG1[rip]
	xor	esi, esi
	not	edx
	call	WREG32_P@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L7:
	xor	r12d, r12d
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L5:
	mov	r12d, DWORD PTR EINVAL[rip]
	neg	r12d
	jmp	.L1
.L12:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	rs780_set_engine_clock_scaling, .-rs780_set_engine_clock_scaling
	.comm	MIN_FEEDBACK_DIV_MASK,4,4
	.comm	MAX_FEEDBACK_DIV_MASK,4,4
	.comm	FVTHROT_FBDIV_REG1,4,4
	.comm	FVTHROT_FBDIV_REG0,4,4
	.comm	FORCE_FEEDBACK_DIV,4,4
	.comm	EINVAL,4,4
	.comm	COMPUTE_ENGINE_PLL_PARAM,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_rs780_dpm.c_rs780_set_engine_clock_scaling.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	rs780_set_engine_clock_scaling, %function
rs780_set_engine_clock_scaling:
	@ args = 0, pretend = 0, frame = 48
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, lr}
	ldr	r3, .L13
	sub	sp, sp, #60
	mov	r6, r0
	mov	r0, r1
	mov	r4, r2
	ldr	r3, [r3]
	str	r3, [sp, #52]
	mov	r3,#0
	bl	rs780_get_ps
	mov	r3, r0
	mov	r0, r4
	mov	r4, r3
	bl	rs780_get_ps
	ldr	r2, [r4]
	ldr	r3, [r0]
	mov	r5, r0
	cmp	r2, r3
	ldr	r2, [r4, #4]
	bne	.L3
	ldr	r3, [r0, #4]
	cmp	r2, r3
	beq	.L7
.L3:
	ldr	r7, .L13+4
	add	r3, sp, #16
	str	r3, [sp]
	mov	r0, r6
	mov	r3, #0
	ldr	r1, [r7]
	bl	radeon_atom_get_clock_dividers
	subs	r3, r0, #0
	beq	.L11
.L1:
	ldr	r2, .L13
	ldr	r1, [r2]
	ldr	r2, [sp, #52]
	eors	r1, r2, r1
	mov	r2, #0
	bne	.L12
	mov	r0, r3
	add	sp, sp, #60
	@ sp needed
	pop	{r4, r5, r6, r7, pc}
.L11:
	add	r1, sp, #28
	ldr	r2, [r4]
	mov	r0, r6
	str	r1, [sp]
	ldr	r1, [r7]
	bl	radeon_atom_get_clock_dividers
	subs	r3, r0, #0
	bne	.L1
	add	r0, sp, #40
	ldr	r2, [r5]
	ldr	r1, [r7]
	str	r0, [sp]
	mov	r0, r6
	bl	radeon_atom_get_clock_dividers
	subs	r3, r0, #0
	bne	.L1
	ldr	r1, [sp, #28]
	ldr	r2, [sp, #16]
	cmp	r2, r1
	bne	.L5
	ldr	r0, [sp, #32]
	ldr	r1, [sp, #20]
	cmp	r1, r0
	bne	.L5
	ldr	r0, [sp, #40]
	cmp	r2, r0
	bne	.L5
	ldr	r2, [sp, #44]
	cmp	r1, r2
	bne	.L5
	mov	r0, r6
	ldr	r1, [sp, #36]
	str	r3, [sp, #12]
	bl	rs780_force_fbdiv
	ldr	r0, [sp, #24]
	ldr	r2, [sp, #36]
	cmp	r2, r0
	ble	.L7
	ldr	r2, .L13+8
	ldr	r5, [r2]
	bl	MIN_FEEDBACK_DIV
	mov	r4, r0
	ldr	r0, [sp, #36]
	bl	MAX_FEEDBACK_DIV
	ldr	r1, .L13+12
	ldr	r2, .L13+16
	ldr	ip, [r1]
	ldr	r2, [r2]
	orr	r1, r4, r0
	orr	r2, r2, ip
	mvn	r2, r2
	mov	r0, r5
	bl	WREG32_P
	ldr	r2, .L13+20
	ldr	r3, [sp, #12]
	ldr	r1, .L13+24
	ldr	r2, [r2]
	ldr	r0, [r1]
	mvn	r2, r2
	mov	r1, r3
	bl	WREG32_P
	ldr	r3, [sp, #12]
	b	.L1
.L7:
	mov	r3, #0
	b	.L1
.L5:
	ldr	r3, .L13+28
	ldr	r3, [r3]
	rsb	r3, r3, #0
	b	.L1
.L12:
	bl	__stack_chk_fail
.L14:
	.align	2
.L13:
	.word	.LC0
	.word	COMPUTE_ENGINE_PLL_PARAM
	.word	FVTHROT_FBDIV_REG0
	.word	MAX_FEEDBACK_DIV_MASK
	.word	MIN_FEEDBACK_DIV_MASK
	.word	FORCE_FEEDBACK_DIV
	.word	FVTHROT_FBDIV_REG1
	.word	EINVAL
	.size	rs780_set_engine_clock_scaling, .-rs780_set_engine_clock_scaling
	.comm	MIN_FEEDBACK_DIV_MASK,4,4
	.comm	MAX_FEEDBACK_DIV_MASK,4,4
	.comm	FVTHROT_FBDIV_REG1,4,4
	.comm	FVTHROT_FBDIV_REG0,4,4
	.comm	FORCE_FEEDBACK_DIV,4,4
	.comm	EINVAL,4,4
	.comm	COMPUTE_ENGINE_PLL_PARAM,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
