	.file	"extr_rtc_init.c_rtc_vddsdio_get_config.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	rtc_vddsdio_get_config
	.type	rtc_vddsdio_get_config, @function
rtc_vddsdio_get_config:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	mov	r13, rdi
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 24
	.cfi_def_cfa_offset 80
	mov	edi, DWORD PTR RTC_CNTL_SDIO_CONF_REG[rip]
	call	REG_READ@PLT
	mov	ebp, DWORD PTR RTC_CNTL_DREFH_SDIO_M[rip]
	mov	ecx, DWORD PTR RTC_CNTL_DREFH_SDIO_S[rip]
	mov	ebx, DWORD PTR RTC_CNTL_DREFM_SDIO_M[rip]
	mov	r12d, DWORD PTR RTC_CNTL_DREFL_SDIO_M[rip]
	and	ebp, eax
	sar	ebp, cl
	mov	ecx, DWORD PTR RTC_CNTL_DREFM_SDIO_S[rip]
	and	ebx, eax
	and	r12d, eax
	sar	ebx, cl
	mov	ecx, DWORD PTR RTC_CNTL_DREFL_SDIO_S[rip]
	sar	r12d, cl
	test	DWORD PTR RTC_CNTL_SDIO_FORCE[rip], eax
	je	.L2
	mov	edx, DWORD PTR RTC_CNTL_XPD_SDIO_REG_M[rip]
	mov	ecx, DWORD PTR RTC_CNTL_XPD_SDIO_REG_S[rip]
	mov	DWORD PTR 0[r13], ebp
	mov	DWORD PTR 4[r13], ebx
	and	edx, eax
	and	eax, DWORD PTR RTC_CNTL_SDIO_TIEH_M[rip]
	mov	DWORD PTR 8[r13], r12d
	sar	edx, cl
	mov	ecx, DWORD PTR RTC_CNTL_SDIO_TIEH_S[rip]
	mov	DWORD PTR 12[r13], 1
	mov	DWORD PTR 16[r13], edx
	sar	eax, cl
	mov	DWORD PTR 20[r13], eax
.L1:
	add	rsp, 24
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	rax, r13
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L2:
	.cfi_restore_state
	mov	edi, DWORD PTR EFUSE_BLK0_RDATA4_REG[rip]
	call	REG_READ@PLT
	test	DWORD PTR EFUSE_RD_SDIO_FORCE[rip], eax
	jne	.L10
	mov	edi, DWORD PTR GPIO_STRAP_REG[rip]
	call	REG_READ@PLT
	mov	edi, 5
	mov	r14d, eax
	call	BIT@PLT
	mov	DWORD PTR 0[r13], ebp
	movabs	rsi, 4294967296
	test	eax, r14d
	mov	eax, DWORD PTR RTC_VDDSDIO_TIEH_1_8V[rip]
	cmove	eax, DWORD PTR RTC_VDDSDIO_TIEH_3_3V[rip]
	mov	DWORD PTR 4[r13], ebx
	mov	DWORD PTR 8[r13], r12d
	mov	QWORD PTR 12[r13], rsi
	mov	DWORD PTR 20[r13], eax
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L10:
	mov	r15d, DWORD PTR EFUSE_RD_XPD_SDIO_REG_M[rip]
	mov	ecx, DWORD PTR EFUSE_RD_XPD_SDIO_REG_S[rip]
	mov	r14d, eax
	mov	DWORD PTR 12[rsp], eax
	mov	esi, DWORD PTR EFUSE_RD_BLK3_PART_RESERVE[rip]
	mov	edi, DWORD PTR EFUSE_BLK0_RDATA3_REG[rip]
	and	r15d, eax
	and	r14d, DWORD PTR EFUSE_RD_SDIO_TIEH_M[rip]
	sar	r15d, cl
	mov	ecx, DWORD PTR EFUSE_RD_SDIO_TIEH_S[rip]
	sar	r14d, cl
	call	REG_GET_FIELD@PLT
	test	rax, rax
	jne	.L5
	mov	edx, DWORD PTR 12[rsp]
	mov	ebp, DWORD PTR EFUSE_RD_SDIO_DREFH_M[rip]
	mov	ecx, DWORD PTR EFUSE_RD_SDIO_DREFH_S[rip]
	mov	ebx, DWORD PTR EFUSE_RD_SDIO_DREFM_M[rip]
	and	ebp, edx
	sar	ebp, cl
	mov	ecx, DWORD PTR EFUSE_RD_SDIO_DREFM_S[rip]
	and	ebx, edx
	and	edx, DWORD PTR EFUSE_RD_SDIO_DREFL_M[rip]
	mov	r12d, edx
	sar	ebx, cl
	mov	ecx, DWORD PTR EFUSE_RD_SDIO_DREFL_S[rip]
	sar	r12d, cl
.L5:
	mov	DWORD PTR 0[r13], ebp
	mov	DWORD PTR 4[r13], ebx
	mov	DWORD PTR 8[r13], r12d
	mov	DWORD PTR 12[r13], 0
	mov	DWORD PTR 16[r13], r15d
	mov	DWORD PTR 20[r13], r14d
	jmp	.L1
	.cfi_endproc
.LFE0:
	.size	rtc_vddsdio_get_config, .-rtc_vddsdio_get_config
	.comm	RTC_VDDSDIO_TIEH_3_3V,4,4
	.comm	RTC_VDDSDIO_TIEH_1_8V,4,4
	.comm	RTC_CNTL_XPD_SDIO_REG_S,4,4
	.comm	RTC_CNTL_XPD_SDIO_REG_M,4,4
	.comm	RTC_CNTL_SDIO_TIEH_S,4,4
	.comm	RTC_CNTL_SDIO_TIEH_M,4,4
	.comm	RTC_CNTL_SDIO_FORCE,4,4
	.comm	RTC_CNTL_SDIO_CONF_REG,4,4
	.comm	RTC_CNTL_DREFM_SDIO_S,4,4
	.comm	RTC_CNTL_DREFM_SDIO_M,4,4
	.comm	RTC_CNTL_DREFL_SDIO_S,4,4
	.comm	RTC_CNTL_DREFL_SDIO_M,4,4
	.comm	RTC_CNTL_DREFH_SDIO_S,4,4
	.comm	RTC_CNTL_DREFH_SDIO_M,4,4
	.comm	GPIO_STRAP_REG,4,4
	.comm	EFUSE_RD_XPD_SDIO_REG_S,4,4
	.comm	EFUSE_RD_XPD_SDIO_REG_M,4,4
	.comm	EFUSE_RD_SDIO_TIEH_S,4,4
	.comm	EFUSE_RD_SDIO_TIEH_M,4,4
	.comm	EFUSE_RD_SDIO_FORCE,4,4
	.comm	EFUSE_RD_SDIO_DREFM_S,4,4
	.comm	EFUSE_RD_SDIO_DREFM_M,4,4
	.comm	EFUSE_RD_SDIO_DREFL_S,4,4
	.comm	EFUSE_RD_SDIO_DREFL_M,4,4
	.comm	EFUSE_RD_SDIO_DREFH_S,4,4
	.comm	EFUSE_RD_SDIO_DREFH_M,4,4
	.comm	EFUSE_RD_BLK3_PART_RESERVE,4,4
	.comm	EFUSE_BLK0_RDATA4_REG,4,4
	.comm	EFUSE_BLK0_RDATA3_REG,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_rtc_init.c_rtc_vddsdio_get_config.c"
	.text
	.align	2
	.global	rtc_vddsdio_get_config
	.syntax unified
	.arm
	.fpu softvfp
	.type	rtc_vddsdio_get_config, %function
rtc_vddsdio_get_config:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	ldr	r3, .L11
	push	{r4, r5, r6, r7, r8, r9, r10, lr}
	mov	r4, r0
	ldr	r0, [r3]
	bl	REG_READ
	ldr	r3, .L11+4
	ldr	r2, .L11+8
	ldr	r3, [r3]
	ldr	lr, .L11+12
	ldr	ip, .L11+16
	ldr	r6, [r2]
	ldr	r1, .L11+20
	ldr	r2, .L11+24
	tst	r0, r3
	ldr	r3, .L11+28
	ldr	r7, [lr]
	ldr	r5, [ip]
	ldr	r1, [r1]
	ldr	r2, [r2]
	ldr	r3, [r3]
	and	r7, r7, r0
	and	r5, r5, r0
	and	r6, r6, r0
	asr	r7, r7, r1
	asr	r5, r5, r2
	asr	r6, r6, r3
	beq	.L2
	mov	r1, #1
	ldr	r2, .L11+32
	ldr	r3, .L11+36
	ldr	r2, [r2]
	ldr	r3, [r3]
	and	r2, r2, r0
	and	r3, r3, r0
	ldr	r0, .L11+40
	str	r7, [r4]
	ldr	ip, [r0]
	ldr	r0, .L11+44
	asr	r2, r2, ip
	ldr	r0, [r0]
	str	r5, [r4, #4]
	asr	r3, r3, r0
	str	r6, [r4, #8]
	mov	r0, r4
	str	r2, [r4, #16]
	str	r3, [r4, #20]
	str	r1, [r4, #12]
	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
.L2:
	ldr	r3, .L11+48
	ldr	r0, [r3]
	bl	REG_READ
	ldr	r3, .L11+52
	mov	r8, r0
	ldr	r3, [r3]
	tst	r0, r3
	bne	.L10
	ldr	r3, .L11+56
	ldr	r0, [r3]
	bl	REG_READ
	mov	r8, r0
	mov	r0, #5
	bl	BIT
	tst	r0, r8
	ldrne	r3, .L11+60
	ldreq	r3, .L11+64
	mov	r2, #0
	ldr	r1, [r3]
	mov	r3, #1
	mov	r0, r4
	stmib	r4, {r5, r6}
	str	r7, [r4]
	str	r1, [r4, #20]
	str	r2, [r4, #12]
	str	r3, [r4, #16]
	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
.L10:
	ldr	r0, .L11+68
	ldr	r1, .L11+72
	ldr	r2, .L11+76
	ldr	r3, .L11+80
	ldr	r10, [r0]
	ldr	r9, [r1]
	ldr	r0, .L11+84
	ldr	r1, .L11+88
	ldr	r2, [r2]
	ldr	r3, [r3]
	ldr	r1, [r1]
	ldr	r0, [r0]
	and	r10, r10, r8
	and	r9, r9, r8
	asr	r10, r10, r2
	asr	r9, r9, r3
	bl	REG_GET_FIELD
	cmp	r0, #0
	bne	.L5
	ldr	r0, .L11+92
	ldr	r1, .L11+96
	ldr	r3, .L11+100
	ldr	r7, [r0]
	ldr	r5, [r1]
	ldr	r0, [r3]
	ldr	r2, .L11+104
	ldr	r3, .L11+108
	ldr	r1, .L11+112
	ldr	r2, [r2]
	ldr	r3, [r3]
	ldr	r6, [r1]
	and	r7, r7, r8
	and	r5, r5, r8
	and	r8, r8, r0
	asr	r7, r7, r2
	asr	r5, r5, r3
	asr	r6, r8, r6
.L5:
	mov	r3, #0
	mov	r0, r4
	stmib	r4, {r5, r6}
	str	r7, [r4]
	str	r10, [r4, #16]
	str	r9, [r4, #20]
	str	r3, [r4, #12]
	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
.L12:
	.align	2
.L11:
	.word	RTC_CNTL_SDIO_CONF_REG
	.word	RTC_CNTL_SDIO_FORCE
	.word	RTC_CNTL_DREFL_SDIO_M
	.word	RTC_CNTL_DREFH_SDIO_M
	.word	RTC_CNTL_DREFM_SDIO_M
	.word	RTC_CNTL_DREFH_SDIO_S
	.word	RTC_CNTL_DREFM_SDIO_S
	.word	RTC_CNTL_DREFL_SDIO_S
	.word	RTC_CNTL_XPD_SDIO_REG_M
	.word	RTC_CNTL_SDIO_TIEH_M
	.word	RTC_CNTL_XPD_SDIO_REG_S
	.word	RTC_CNTL_SDIO_TIEH_S
	.word	EFUSE_BLK0_RDATA4_REG
	.word	EFUSE_RD_SDIO_FORCE
	.word	GPIO_STRAP_REG
	.word	RTC_VDDSDIO_TIEH_1_8V
	.word	RTC_VDDSDIO_TIEH_3_3V
	.word	EFUSE_RD_XPD_SDIO_REG_M
	.word	EFUSE_RD_SDIO_TIEH_M
	.word	EFUSE_RD_XPD_SDIO_REG_S
	.word	EFUSE_RD_SDIO_TIEH_S
	.word	EFUSE_BLK0_RDATA3_REG
	.word	EFUSE_RD_BLK3_PART_RESERVE
	.word	EFUSE_RD_SDIO_DREFH_M
	.word	EFUSE_RD_SDIO_DREFM_M
	.word	EFUSE_RD_SDIO_DREFL_M
	.word	EFUSE_RD_SDIO_DREFH_S
	.word	EFUSE_RD_SDIO_DREFM_S
	.word	EFUSE_RD_SDIO_DREFL_S
	.size	rtc_vddsdio_get_config, .-rtc_vddsdio_get_config
	.comm	RTC_VDDSDIO_TIEH_3_3V,4,4
	.comm	RTC_VDDSDIO_TIEH_1_8V,4,4
	.comm	RTC_CNTL_XPD_SDIO_REG_S,4,4
	.comm	RTC_CNTL_XPD_SDIO_REG_M,4,4
	.comm	RTC_CNTL_SDIO_TIEH_S,4,4
	.comm	RTC_CNTL_SDIO_TIEH_M,4,4
	.comm	RTC_CNTL_SDIO_FORCE,4,4
	.comm	RTC_CNTL_SDIO_CONF_REG,4,4
	.comm	RTC_CNTL_DREFM_SDIO_S,4,4
	.comm	RTC_CNTL_DREFM_SDIO_M,4,4
	.comm	RTC_CNTL_DREFL_SDIO_S,4,4
	.comm	RTC_CNTL_DREFL_SDIO_M,4,4
	.comm	RTC_CNTL_DREFH_SDIO_S,4,4
	.comm	RTC_CNTL_DREFH_SDIO_M,4,4
	.comm	GPIO_STRAP_REG,4,4
	.comm	EFUSE_RD_XPD_SDIO_REG_S,4,4
	.comm	EFUSE_RD_XPD_SDIO_REG_M,4,4
	.comm	EFUSE_RD_SDIO_TIEH_S,4,4
	.comm	EFUSE_RD_SDIO_TIEH_M,4,4
	.comm	EFUSE_RD_SDIO_FORCE,4,4
	.comm	EFUSE_RD_SDIO_DREFM_S,4,4
	.comm	EFUSE_RD_SDIO_DREFM_M,4,4
	.comm	EFUSE_RD_SDIO_DREFL_S,4,4
	.comm	EFUSE_RD_SDIO_DREFL_M,4,4
	.comm	EFUSE_RD_SDIO_DREFH_S,4,4
	.comm	EFUSE_RD_SDIO_DREFH_M,4,4
	.comm	EFUSE_RD_BLK3_PART_RESERVE,4,4
	.comm	EFUSE_BLK0_RDATA4_REG,4,4
	.comm	EFUSE_BLK0_RDATA3_REG,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
