	.file	"extr_clock.c___clk_disable.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	__clk_disable, @function
__clk_disable:
.LFB0:
	.cfi_startproc
	endbr64
	test	rdi, rdi
	je	.L16
	push	rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	mov	rbx, rdi
	jmp	.L10
	.p2align 4,,10
	.p2align 3
.L4:
	mov	rbx, QWORD PTR 8[rbx]
	test	rbx, rbx
	je	.L20
.L10:
	xor	edi, edi
	cmp	QWORD PTR [rbx], 0
	sete	dil
	call	BUG_ON@PLT
	sub	QWORD PTR [rbx], 1
	jne	.L4
	mov	rdi, rbx
	call	clk_is_pll1@PLT
	test	rax, rax
	je	.L5
	xor	eax, eax
	call	chipcHw_pll1Disable@PLT
	mov	rbx, QWORD PTR 8[rbx]
	test	rbx, rbx
	jne	.L10
.L20:
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L5:
	.cfi_restore_state
	mov	rdi, rbx
	call	clk_is_pll2@PLT
	test	rax, rax
	je	.L6
	xor	eax, eax
	call	chipcHw_pll2Disable@PLT
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L6:
	mov	rdi, rbx
	call	clk_is_using_xtal@PLT
	test	rax, rax
	je	.L7
	mov	rdi, rbx
	call	clk_is_primary@PLT
	test	eax, eax
	jne	.L4
	mov	edi, DWORD PTR 16[rbx]
	call	chipcHw_bypassClockDisable@PLT
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L7:
	mov	edi, DWORD PTR 16[rbx]
	call	chipcHw_setClockDisable@PLT
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L16:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	ret
	.cfi_endproc
.LFE0:
	.size	__clk_disable, .-__clk_disable
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_clock.c___clk_disable.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	__clk_disable, %function
__clk_disable:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, lr}
	subs	r4, r0, #0
	bne	.L10
	pop	{r4, pc}
.L4:
	ldr	r4, [r4, #4]
	cmp	r4, #0
	popeq	{r4, pc}
.L10:
	ldr	r0, [r4]
	clz	r0, r0
	lsr	r0, r0, #5
	bl	BUG_ON
	ldr	r3, [r4]
	sub	r3, r3, #1
	cmp	r3, #0
	str	r3, [r4]
	bne	.L4
	mov	r0, r4
	bl	clk_is_pll1
	cmp	r0, #0
	beq	.L5
	bl	chipcHw_pll1Disable
	b	.L4
.L5:
	mov	r0, r4
	bl	clk_is_pll2
	cmp	r0, #0
	beq	.L6
	bl	chipcHw_pll2Disable
	b	.L4
.L6:
	mov	r0, r4
	bl	clk_is_using_xtal
	cmp	r0, #0
	beq	.L7
	mov	r0, r4
	bl	clk_is_primary
	cmp	r0, #0
	bne	.L4
	ldr	r0, [r4, #8]
	bl	chipcHw_bypassClockDisable
	b	.L4
.L7:
	ldr	r0, [r4, #8]
	bl	chipcHw_setClockDisable
	b	.L4
	.size	__clk_disable, .-__clk_disable
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
