	.file	"extr_ni_tio.c_ni_tio_set_gate_src.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	ni_tio_set_gate_src
	.type	ni_tio_set_gate_src, @function
ni_tio_set_gate_src:
.LFB0:
	.cfi_startproc
	endbr64
	push	r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	push	r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	push	r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	mov	r12d, edx
	push	rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	mov	r14, QWORD PTR 8[rdi]
	mov	ebx, esi
	mov	edi, DWORD PTR [rdi]
	call	NITIO_Gi_Second_Gate_Reg@PLT
	test	ebx, ebx
	je	.L2
	cmp	ebx, 1
	jne	.L17
	mov	rdi, r14
	mov	r13d, eax
	call	ni_tio_second_gate_registers_present@PLT
	test	eax, eax
	jne	.L11
.L17:
	mov	eax, DWORD PTR EINVAL[rip]
	neg	eax
.L1:
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	pop	rbp
	.cfi_def_cfa_offset 32
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L2:
	.cfi_restore_state
	mov	edi, r12d
	call	CR_CHAN@PLT
	cmp	eax, DWORD PTR NI_GPCT_DISABLED_GATE_SELECT[rip]
	je	.L20
	mov	esi, r12d
	mov	rdi, rbp
	call	ni_tio_set_first_gate_modifiers@PLT
	mov	eax, DWORD PTR [r14]
	cmp	eax, 129
	jle	.L21
	cmp	eax, 130
	jne	.L9
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	esi, r12d
	mov	rdi, rbp
	pop	rbp
	.cfi_def_cfa_offset 32
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	jmp	ni_660x_set_first_gate@PLT
	.p2align 4,,10
	.p2align 3
.L21:
	.cfi_restore_state
	cmp	eax, 127
	jg	.L22
.L9:
	xor	eax, eax
	call	BUG@PLT
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	xor	eax, eax
	pop	rbp
	.cfi_def_cfa_offset 32
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L11:
	.cfi_restore_state
	mov	edi, r12d
	call	CR_CHAN@PLT
	mov	rdx, QWORD PTR 8[r14]
	mov	r8d, eax
	mov	eax, r13d
	cmp	r8d, DWORD PTR NI_GPCT_DISABLED_GATE_SELECT[rip]
	lea	rax, [rdx+rax*4]
	je	.L23
	mov	edx, DWORD PTR Gi_Second_Gate_Polarity_Bit[rip]
	mov	esi, DWORD PTR [rax]
	mov	ecx, edx
	or	edx, esi
	not	ecx
	and	ecx, esi
	test	DWORD PTR CR_INVERT[rip], r12d
	cmove	edx, ecx
	mov	DWORD PTR [rax], edx
	mov	eax, DWORD PTR [r14]
	cmp	eax, 128
	je	.L15
	cmp	eax, 130
	jne	.L9
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	esi, r12d
	mov	rdi, rbp
	pop	rbp
	.cfi_def_cfa_offset 32
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	jmp	ni_660x_set_second_gate@PLT
	.p2align 4,,10
	.p2align 3
.L22:
	.cfi_restore_state
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	esi, r12d
	mov	rdi, rbp
	pop	rbp
	.cfi_def_cfa_offset 32
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	jmp	ni_m_series_set_first_gate@PLT
	.p2align 4,,10
	.p2align 3
.L20:
	.cfi_restore_state
	mov	edi, DWORD PTR 0[rbp]
	mov	r13d, DWORD PTR Gi_Gating_Disabled_Bits[rip]
	mov	r12d, DWORD PTR Gi_Gating_Mode_Mask[rip]
	call	NITIO_Gi_Mode_Reg@PLT
	mov	ecx, r13d
	mov	rdi, rbp
	mov	esi, eax
	mov	edx, r12d
	call	ni_tio_set_bits@PLT
	xor	eax, eax
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L15:
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	esi, r12d
	mov	rdi, rbp
	pop	rbp
	.cfi_def_cfa_offset 32
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	jmp	ni_m_series_set_second_gate@PLT
	.p2align 4,,10
	.p2align 3
.L23:
	.cfi_restore_state
	mov	esi, DWORD PTR Gi_Second_Gate_Mode_Bit[rip]
	mov	edx, r13d
	mov	rdi, rbp
	not	esi
	and	esi, DWORD PTR [rax]
	mov	DWORD PTR [rax], esi
	call	write_register@PLT
	xor	eax, eax
	jmp	.L1
	.cfi_endproc
.LFE0:
	.size	ni_tio_set_gate_src, .-ni_tio_set_gate_src
	.comm	NI_GPCT_DISABLED_GATE_SELECT,4,4
	.comm	Gi_Second_Gate_Polarity_Bit,4,4
	.comm	Gi_Second_Gate_Mode_Bit,4,4
	.comm	Gi_Gating_Mode_Mask,4,4
	.comm	Gi_Gating_Disabled_Bits,4,4
	.comm	EINVAL,4,4
	.comm	CR_INVERT,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_ni_tio.c_ni_tio_set_gate_src.c"
	.text
	.align	2
	.global	ni_tio_set_gate_src
	.syntax unified
	.arm
	.fpu softvfp
	.type	ni_tio_set_gate_src, %function
ni_tio_set_gate_src:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	mov	r6, r0
	mov	r4, r1
	ldr	r0, [r0]
	mov	r7, r2
	ldr	r8, [r6, #4]
	bl	NITIO_Gi_Second_Gate_Reg
	cmp	r4, #0
	beq	.L2
	cmp	r4, #1
	bne	.L17
	mov	r5, r0
	mov	r0, r8
	bl	ni_tio_second_gate_registers_present
	cmp	r0, #0
	bne	.L11
.L17:
	ldr	r3, .L24
	ldr	r0, [r3]
	rsb	r0, r0, #0
	pop	{r4, r5, r6, r7, r8, pc}
.L2:
	mov	r0, r7
	bl	CR_CHAN
	ldr	r3, .L24+4
	ldr	r3, [r3]
	cmp	r0, r3
	beq	.L20
	mov	r1, r7
	mov	r0, r6
	bl	ni_tio_set_first_gate_modifiers
	ldr	r3, [r8]
	cmp	r3, #129
	ble	.L21
	cmp	r3, #130
	bne	.L9
	mov	r1, r7
	mov	r0, r6
	pop	{r4, r5, r6, r7, r8, lr}
	b	ni_660x_set_first_gate
.L21:
	cmp	r3, #127
	bgt	.L22
.L9:
	bl	BUG
	mov	r0, #0
	pop	{r4, r5, r6, r7, r8, pc}
.L11:
	mov	r0, r7
	bl	CR_CHAN
	ldr	r3, .L24+4
	ldr	r3, [r3]
	cmp	r0, r3
	beq	.L23
	ldr	r3, .L24+8
	ldr	r2, [r8, #4]
	ldr	r3, [r3]
	ldr	r1, .L24+12
	tst	r7, r3
	ldr	r1, [r1]
	ldr	r3, [r2, r5, lsl #2]
	orrne	r3, r3, r1
	biceq	r3, r3, r1
	str	r3, [r2, r5, lsl #2]
	ldr	r3, [r8]
	cmp	r3, #128
	beq	.L15
	cmp	r3, #130
	bne	.L9
	mov	r1, r7
	mov	r0, r6
	pop	{r4, r5, r6, r7, r8, lr}
	b	ni_660x_set_second_gate
.L22:
	mov	r1, r7
	mov	r0, r6
	pop	{r4, r5, r6, r7, r8, lr}
	b	ni_m_series_set_first_gate
.L20:
	ldr	r0, [r6]
	bl	NITIO_Gi_Mode_Reg
	ldr	r3, .L24+16
	ldr	r2, .L24+20
	mov	r1, r0
	ldr	r3, [r3]
	mov	r0, r6
	ldr	r2, [r2]
	bl	ni_tio_set_bits
	mov	r0, r4
	pop	{r4, r5, r6, r7, r8, pc}
.L15:
	mov	r1, r7
	mov	r0, r6
	pop	{r4, r5, r6, r7, r8, lr}
	b	ni_m_series_set_second_gate
.L23:
	ldr	r3, [r8, #4]
	ldr	r2, .L24+24
	ldr	r1, [r3, r5, lsl #2]
	ldr	r2, [r2]
	mov	r0, r6
	bic	r1, r1, r2
	str	r1, [r3, r5, lsl #2]
	mov	r2, r5
	bl	write_register
	mov	r0, #0
	pop	{r4, r5, r6, r7, r8, pc}
.L25:
	.align	2
.L24:
	.word	EINVAL
	.word	NI_GPCT_DISABLED_GATE_SELECT
	.word	CR_INVERT
	.word	Gi_Second_Gate_Polarity_Bit
	.word	Gi_Gating_Disabled_Bits
	.word	Gi_Gating_Mode_Mask
	.word	Gi_Second_Gate_Mode_Bit
	.size	ni_tio_set_gate_src, .-ni_tio_set_gate_src
	.comm	NI_GPCT_DISABLED_GATE_SELECT,4,4
	.comm	Gi_Second_Gate_Polarity_Bit,4,4
	.comm	Gi_Second_Gate_Mode_Bit,4,4
	.comm	Gi_Gating_Mode_Mask,4,4
	.comm	Gi_Gating_Disabled_Bits,4,4
	.comm	EINVAL,4,4
	.comm	CR_INVERT,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
