	.file	"extr_bxe_elink.c_elink_warpcore_set_20G_DXGXS.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	elink_warpcore_set_20G_DXGXS, @function
elink_warpcore_set_20G_DXGXS:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	mov	rcx, QWORD PTR MDIO_WC_REG_RX0_ANARXCONTROL1G[rip]
	mov	r8d, 144
	mov	r12, rsi
	push	rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	mov	ebx, edx
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	sal	ebx, 4
	call	elink_cl45_write@PLT
	mov	rcx, QWORD PTR MDIO_WC_REG_RX2_ANARXCONTROL1G[rip]
	mov	rsi, r12
	mov	rdi, rbp
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	mov	r8d, 144
	call	elink_cl45_write@PLT
	mov	rcx, QWORD PTR MDIO_WC_REG_RX66_SCW0[rip]
	mov	rsi, r12
	mov	rdi, rbp
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	mov	r8d, 57456
	call	elink_cl45_write@PLT
	mov	rcx, QWORD PTR MDIO_WC_REG_RX66_SCW1[rip]
	mov	rsi, r12
	mov	rdi, rbp
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	mov	r8d, 49360
	call	elink_cl45_write@PLT
	mov	rcx, QWORD PTR MDIO_WC_REG_RX66_SCW2[rip]
	mov	rsi, r12
	mov	rdi, rbp
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	mov	r8d, 41136
	call	elink_cl45_write@PLT
	mov	rcx, QWORD PTR MDIO_WC_REG_RX66_SCW3[rip]
	mov	rsi, r12
	mov	rdi, rbp
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	mov	r8d, 32912
	call	elink_cl45_write@PLT
	mov	rcx, QWORD PTR MDIO_WC_REG_RX66_SCW0_MASK[rip]
	mov	rsi, r12
	mov	rdi, rbp
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	mov	r8d, 61680
	call	elink_cl45_write@PLT
	mov	rcx, QWORD PTR MDIO_WC_REG_RX66_SCW1_MASK[rip]
	mov	rsi, r12
	mov	rdi, rbp
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	mov	r8d, 61680
	call	elink_cl45_write@PLT
	mov	rcx, QWORD PTR MDIO_WC_REG_RX66_SCW2_MASK[rip]
	mov	rsi, r12
	mov	rdi, rbp
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	mov	r8d, 61680
	call	elink_cl45_write@PLT
	mov	rcx, QWORD PTR MDIO_WC_REG_RX66_SCW3_MASK[rip]
	mov	rsi, r12
	mov	rdi, rbp
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	mov	r8d, 61680
	call	elink_cl45_write@PLT
	mov	rcx, QWORD PTR MDIO_WC_REG_SERDESDIGITAL_MISC1[rip]
	mov	rsi, r12
	mov	rdi, rbp
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	mov	r8d, 24584
	call	elink_cl45_write@PLT
	mov	rcx, QWORD PTR MDIO_WC_REG_DIGITAL4_MISC3[rip]
	mov	rsi, r12
	mov	rdi, rbp
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	mov	r8d, 32904
	call	elink_cl45_write@PLT
	xor	edx, edx
	mov	esi, 45
	mov	edi, 18
	call	WC_TX_FIR@PLT
	mov	rcx, QWORD PTR MDIO_WC_REG_TX_FIR_TAP[rip]
	mov	rsi, r12
	mov	rdi, rbp
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	or	eax, DWORD PTR MDIO_WC_REG_TX_FIR_TAP_ENABLE[rip]
	mov	r8d, eax
	call	elink_cl45_write@PLT
	xor	ecx, ecx
	mov	edx, 2
	mov	esi, 2
	mov	edi, 2
	call	WC_TX_DRIVER@PLT
	movsx	rcx, ebx
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	pop	rbx
	.cfi_def_cfa_offset 24
	mov	rsi, r12
	mov	rdi, rbp
	mov	r8d, eax
	pop	rbp
	.cfi_def_cfa_offset 16
	add	rcx, QWORD PTR MDIO_WC_REG_TX0_TX_DRIVER[rip]
	pop	r12
	.cfi_def_cfa_offset 8
	jmp	elink_cl45_write@PLT
	.cfi_endproc
.LFE0:
	.size	elink_warpcore_set_20G_DXGXS, .-elink_warpcore_set_20G_DXGXS
	.comm	MDIO_WC_REG_TX_FIR_TAP_ENABLE,4,4
	.comm	MDIO_WC_REG_TX_FIR_TAP,8,8
	.comm	MDIO_WC_REG_TX0_TX_DRIVER,8,8
	.comm	MDIO_WC_REG_SERDESDIGITAL_MISC1,8,8
	.comm	MDIO_WC_REG_RX66_SCW3_MASK,8,8
	.comm	MDIO_WC_REG_RX66_SCW3,8,8
	.comm	MDIO_WC_REG_RX66_SCW2_MASK,8,8
	.comm	MDIO_WC_REG_RX66_SCW2,8,8
	.comm	MDIO_WC_REG_RX66_SCW1_MASK,8,8
	.comm	MDIO_WC_REG_RX66_SCW1,8,8
	.comm	MDIO_WC_REG_RX66_SCW0_MASK,8,8
	.comm	MDIO_WC_REG_RX66_SCW0,8,8
	.comm	MDIO_WC_REG_RX2_ANARXCONTROL1G,8,8
	.comm	MDIO_WC_REG_RX0_ANARXCONTROL1G,8,8
	.comm	MDIO_WC_REG_DIGITAL4_MISC3,8,8
	.comm	MDIO_WC_DEVAD,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_bxe_elink.c_elink_warpcore_set_20G_DXGXS.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	elink_warpcore_set_20G_DXGXS, %function
elink_warpcore_set_20G_DXGXS:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, lr}
	mov	r7, #144
	mov	r4, r0
	mov	r5, r1
	sub	sp, sp, #12
	ldr	r6, .L4
	ldr	r3, .L4+4
	str	r7, [sp]
	mov	r8, r2
	ldr	r3, [r3]
	ldr	r2, [r6]
	bl	elink_cl45_write
	ldr	r3, .L4+8
	str	r7, [sp]
	mov	r1, r5
	ldr	r2, [r6]
	mov	r0, r4
	ldr	r3, [r3]
	bl	elink_cl45_write
	ldr	ip, .L4+12
	ldr	r3, .L4+16
	mov	r1, r5
	ldr	r2, [r6]
	ldr	r3, [r3]
	mov	r0, r4
	str	ip, [sp]
	bl	elink_cl45_write
	ldr	ip, .L4+20
	ldr	r3, .L4+24
	mov	r1, r5
	ldr	r2, [r6]
	ldr	r3, [r3]
	mov	r0, r4
	str	ip, [sp]
	bl	elink_cl45_write
	ldr	ip, .L4+28
	ldr	r3, .L4+32
	mov	r1, r5
	ldr	r2, [r6]
	ldr	r3, [r3]
	mov	r0, r4
	str	ip, [sp]
	bl	elink_cl45_write
	ldr	ip, .L4+36
	ldr	r3, .L4+40
	mov	r1, r5
	ldr	r2, [r6]
	ldr	r3, [r3]
	mov	r0, r4
	str	ip, [sp]
	bl	elink_cl45_write
	ldr	r7, .L4+44
	ldr	r3, .L4+48
	mov	r1, r5
	ldr	r2, [r6]
	ldr	r3, [r3]
	mov	r0, r4
	str	r7, [sp]
	bl	elink_cl45_write
	ldr	r3, .L4+52
	str	r7, [sp]
	mov	r1, r5
	ldr	r2, [r6]
	mov	r0, r4
	ldr	r3, [r3]
	bl	elink_cl45_write
	ldr	r3, .L4+56
	str	r7, [sp]
	mov	r1, r5
	ldr	r2, [r6]
	mov	r0, r4
	ldr	r3, [r3]
	bl	elink_cl45_write
	ldr	r3, .L4+60
	str	r7, [sp]
	mov	r1, r5
	ldr	r2, [r6]
	mov	r0, r4
	ldr	r3, [r3]
	bl	elink_cl45_write
	ldr	ip, .L4+64
	ldr	r3, .L4+68
	mov	r1, r5
	ldr	r2, [r6]
	ldr	r3, [r3]
	mov	r0, r4
	str	ip, [sp]
	bl	elink_cl45_write
	ldr	ip, .L4+72
	ldr	r3, .L4+76
	mov	r1, r5
	ldr	r2, [r6]
	ldr	r3, [r3]
	mov	r0, r4
	str	ip, [sp]
	bl	elink_cl45_write
	ldr	r3, .L4+80
	mov	r2, #0
	mov	r1, #45
	mov	r0, #18
	ldr	r7, [r6]
	ldr	r9, [r3]
	bl	WC_TX_FIR
	ldr	r2, .L4+84
	mov	r3, r9
	ldr	r1, [r2]
	mov	r2, r7
	orr	r0, r0, r1
	str	r0, [sp]
	mov	r1, r5
	mov	r0, r4
	bl	elink_cl45_write
	mov	r2, #2
	ldr	r3, .L4+88
	mov	r1, r2
	ldr	ip, [r3]
	mov	r0, r2
	mov	r3, #0
	add	r8, ip, r8, lsl #4
	ldr	r7, [r6]
	bl	WC_TX_DRIVER
	mov	ip, r0
	mov	r3, r8
	mov	r2, r7
	mov	r1, r5
	mov	r0, r4
	str	ip, [sp]
	bl	elink_cl45_write
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, pc}
.L5:
	.align	2
.L4:
	.word	MDIO_WC_DEVAD
	.word	MDIO_WC_REG_RX0_ANARXCONTROL1G
	.word	MDIO_WC_REG_RX2_ANARXCONTROL1G
	.word	57456
	.word	MDIO_WC_REG_RX66_SCW0
	.word	49360
	.word	MDIO_WC_REG_RX66_SCW1
	.word	41136
	.word	MDIO_WC_REG_RX66_SCW2
	.word	32912
	.word	MDIO_WC_REG_RX66_SCW3
	.word	61680
	.word	MDIO_WC_REG_RX66_SCW0_MASK
	.word	MDIO_WC_REG_RX66_SCW1_MASK
	.word	MDIO_WC_REG_RX66_SCW2_MASK
	.word	MDIO_WC_REG_RX66_SCW3_MASK
	.word	24584
	.word	MDIO_WC_REG_SERDESDIGITAL_MISC1
	.word	32904
	.word	MDIO_WC_REG_DIGITAL4_MISC3
	.word	MDIO_WC_REG_TX_FIR_TAP
	.word	MDIO_WC_REG_TX_FIR_TAP_ENABLE
	.word	MDIO_WC_REG_TX0_TX_DRIVER
	.size	elink_warpcore_set_20G_DXGXS, .-elink_warpcore_set_20G_DXGXS
	.comm	MDIO_WC_REG_TX_FIR_TAP_ENABLE,4,4
	.comm	MDIO_WC_REG_TX_FIR_TAP,4,4
	.comm	MDIO_WC_REG_TX0_TX_DRIVER,4,4
	.comm	MDIO_WC_REG_SERDESDIGITAL_MISC1,4,4
	.comm	MDIO_WC_REG_RX66_SCW3_MASK,4,4
	.comm	MDIO_WC_REG_RX66_SCW3,4,4
	.comm	MDIO_WC_REG_RX66_SCW2_MASK,4,4
	.comm	MDIO_WC_REG_RX66_SCW2,4,4
	.comm	MDIO_WC_REG_RX66_SCW1_MASK,4,4
	.comm	MDIO_WC_REG_RX66_SCW1,4,4
	.comm	MDIO_WC_REG_RX66_SCW0_MASK,4,4
	.comm	MDIO_WC_REG_RX66_SCW0,4,4
	.comm	MDIO_WC_REG_RX2_ANARXCONTROL1G,4,4
	.comm	MDIO_WC_REG_RX0_ANARXCONTROL1G,4,4
	.comm	MDIO_WC_REG_DIGITAL4_MISC3,4,4
	.comm	MDIO_WC_DEVAD,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
