	.file	"extr_fsl_sata.c_fsl_sata_end_transaction.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	fsl_sata_end_transaction, @function
fsl_sata_end_transaction:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	mov	r13d, esi
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	rbx, rdi
	sub	rsp, 8
	.cfi_def_cfa_offset 64
	mov	rbp, QWORD PTR 24[rdi]
	mov	r12, QWORD PTR 8[rdi]
	mov	edx, DWORD PTR BUS_DMASYNC_POSTREAD[rip]
	or	edx, DWORD PTR BUS_DMASYNC_POSTWRITE[rip]
	mov	esi, DWORD PTR 132[rbp]
	mov	edi, DWORD PTR 136[rbp]
	call	bus_dmamap_sync@PLT
	mov	rsi, rbx
	mov	rdi, rbp
	call	FSL_SATA_CLP@PLT
	mov	r14, QWORD PTR [r12]
	cmp	r14, QWORD PTR XPT_ATA_IO[rip]
	mov	r15, rax
	je	.L83
	mov	eax, DWORD PTR 8[r12]
	and	eax, DWORD PTR CAM_DIR_MASK[rip]
	cmp	eax, DWORD PTR CAM_DIR_NONE[rip]
	jne	.L81
.L49:
	mov	ecx, DWORD PTR [rbx]
	mov	eax, 1
	mov	edx, DWORD PTR 12[r12]
	sal	eax, cl
	cmp	r13d, 131
	je	.L11
	or	DWORD PTR 0[rbp], eax
	mov	eax, DWORD PTR CAM_DEV_QFRZN[rip]
	and	eax, edx
	or	eax, DWORD PTR 88[rbp]
	je	.L84
.L12:
	mov	eax, DWORD PTR CAM_STATUS_MASK[rip]
	not	eax
	and	eax, edx
	lea	edx, -128[r13]
	mov	DWORD PTR 12[r12], eax
	cmp	edx, 6
	ja	.L13
	lea	rcx, .L15[rip]
	movsx	rdx, DWORD PTR [rcx+rdx*4]
	add	rdx, rcx
	notrack jmp	rdx
	.section	.rodata
	.align 4
	.align 4
.L15:
	.long	.L19-.L15
	.long	.L17-.L15
	.long	.L18-.L15
	.long	.L13-.L15
	.long	.L17-.L15
	.long	.L16-.L15
	.long	.L14-.L15
	.text
	.p2align 4,,10
	.p2align 3
.L83:
	cmp	r13d, 129
	je	.L3
	mov	eax, DWORD PTR 8[r12]
	test	DWORD PTR CAM_ATAIO_NEEDRESULT[rip], eax
	jne	.L3
	lea	rdi, 24[r12]
	mov	esi, 72
	call	bzero@PLT
	mov	eax, DWORD PTR 8[r12]
.L5:
	mov	ecx, DWORD PTR CAM_DIR_MASK[rip]
	mov	edx, DWORD PTR CAM_DIR_NONE[rip]
	and	ecx, eax
	test	DWORD PTR CAM_ATAIO_FPDMA[rip], eax
	jne	.L6
	cmp	ecx, edx
	je	.L49
	mov	r14, QWORD PTR [r12]
.L81:
	mov	edi, DWORD PTR [r15]
	call	le32toh@PLT
	sub	r14, rax
	mov	eax, DWORD PTR 8[r12]
	mov	QWORD PTR 16[r12], r14
	mov	ecx, DWORD PTR CAM_DIR_MASK[rip]
	mov	edx, DWORD PTR CAM_DIR_NONE[rip]
	and	ecx, eax
.L6:
	cmp	ecx, edx
	je	.L49
	mov	esi, DWORD PTR 20[rbx]
	mov	edi, DWORD PTR 128[rbp]
	test	DWORD PTR CAM_DIR_IN[rip], eax
	mov	edx, DWORD PTR BUS_DMASYNC_POSTREAD[rip]
	cmove	edx, DWORD PTR BUS_DMASYNC_POSTWRITE[rip]
	call	bus_dmamap_sync@PLT
	mov	esi, DWORD PTR 20[rbx]
	mov	edi, DWORD PTR 128[rbp]
	call	bus_dmamap_unload@PLT
	jmp	.L49
	.p2align 4,,10
	.p2align 3
.L3:
	mov	rsi, rbx
	mov	rdi, rbp
	call	FSL_SATA_CTP@PLT
	mov	rax, QWORD PTR [rax]
	mov	rdx, QWORD PTR 16[rax]
	mov	QWORD PTR 88[r12], rdx
	mov	rdx, QWORD PTR 24[rax]
	mov	QWORD PTR 80[r12], rdx
	mov	rdx, QWORD PTR 32[rax]
	mov	DWORD PTR 24[r12], edx
	mov	rdx, QWORD PTR 40[rax]
	mov	DWORD PTR 28[r12], edx
	mov	rdx, QWORD PTR 48[rax]
	mov	DWORD PTR 32[r12], edx
	mov	rdx, QWORD PTR 56[rax]
	mov	QWORD PTR 72[r12], rdx
	mov	rdx, QWORD PTR 64[rax]
	mov	QWORD PTR 64[r12], rdx
	mov	rdx, QWORD PTR 72[rax]
	mov	QWORD PTR 56[r12], rdx
	mov	rdx, QWORD PTR 80[rax]
	mov	QWORD PTR 48[r12], rdx
	mov	rdx, QWORD PTR 96[rax]
	mov	rax, QWORD PTR 104[rax]
	mov	DWORD PTR 36[r12], edx
	mov	QWORD PTR 40[r12], rax
	mov	eax, DWORD PTR 8[r12]
	test	DWORD PTR CAM_ATAIO_CONTROL[rip], eax
	je	.L5
	mov	edx, DWORD PTR 12[r12]
	test	DWORD PTR ATA_A_RESET[rip], edx
	jne	.L5
	mov	edi, DWORD PTR 116[rbp]
	mov	esi, DWORD PTR FSL_SATA_P_SIG[rip]
	call	ATA_INL@PLT
	mov	edx, eax
	mov	DWORD PTR 36[r12], eax
	sar	edx, 24
	mov	DWORD PTR 32[r12], edx
	mov	edx, eax
	sar	edx, 16
	mov	DWORD PTR 28[r12], edx
	mov	edx, eax
	mov	eax, DWORD PTR 8[r12]
	sar	edx, 8
	mov	DWORD PTR 24[r12], edx
	jmp	.L5
	.p2align 4,,10
	.p2align 3
.L11:
	mov	ecx, DWORD PTR CAM_STATUS_MASK[rip]
	mov	rdi, QWORD PTR XPT_SCSI_IO[rip]
	not	ecx
	and	edx, ecx
	or	edx, DWORD PTR CAM_REQ_CMP[rip]
	mov	DWORD PTR 12[r12], edx
	cmp	QWORD PTR [r12], rdi
	je	.L85
	.p2align 4,,10
	.p2align 3
.L20:
	not	eax
	and	DWORD PTR 8[rbp], eax
	mov	rdx, QWORD PTR 16[r12]
	and	DWORD PTR 12[rbp], eax
	and	DWORD PTR 16[rbp], eax
	mov	eax, DWORD PTR FSL_SATA_SLOT_EMPTY[rip]
	mov	QWORD PTR 8[rbx], 0
	mov	DWORD PTR 16[rbx], eax
	mov	rax, QWORD PTR 120[rbp]
	sub	QWORD PTR 24[rbp], 1
	sub	DWORD PTR [rax+rdx*4], 1
	mov	ecx, DWORD PTR [rbx]
	mov	edx, 1
	mov	edi, DWORD PTR 116[rbp]
	mov	esi, DWORD PTR FSL_SATA_P_CCR[rip]
	sal	edx, cl
	call	ATA_OUTL@PLT
	mov	rdx, QWORD PTR XPT_ATA_IO[rip]
	cmp	QWORD PTR [r12], rdx
	je	.L86
.L24:
	cmp	r13d, 128
	je	.L27
.L48:
	mov	ecx, DWORD PTR [rbx]
	mov	eax, 1
	mov	esi, DWORD PTR 32[rbp]
	sal	eax, cl
	mov	ecx, eax
	not	ecx
	and	ecx, esi
	mov	DWORD PTR 32[rbp], ecx
	cmp	esi, eax
	je	.L87
.L26:
	cmp	QWORD PTR [r12], rdx
	je	.L88
.L27:
	mov	rax, QWORD PTR 24[r12]
	cmp	rax, QWORD PTR RECOVERY_READ_LOG[rip]
	je	.L89
	cmp	rax, QWORD PTR RECOVERY_REQUEST_SENSE[rip]
	je	.L90
	cmp	r13d, 132
	je	.L31
	mov	eax, DWORD PTR 12[r12]
	and	eax, DWORD PTR CAM_STATUS_MASK[rip]
	cmp	eax, DWORD PTR CAM_SCSI_STATUS_ERROR[rip]
	jne	.L32
	mov	eax, DWORD PTR 8[r12]
	test	DWORD PTR CAM_DIS_AUTOSENSE[rip], eax
	jne	.L32
.L31:
	movsx	rdx, DWORD PTR [rbx]
	mov	rax, QWORD PTR 96[rbp]
	mov	QWORD PTR [rax+rdx*8], r12
	add	QWORD PTR 80[rbp], 1
.L29:
	mov	edx, DWORD PTR 12[rbp]
	mov	eax, DWORD PTR 32[rbp]
	test	edx, edx
	jne	.L33
.L93:
	test	eax, eax
	jne	.L34
	mov	ecx, DWORD PTR 4[rbp]
	test	ecx, ecx
	je	.L35
.L34:
	mov	rdi, rbp
	call	fsl_sata_reset@PLT
.L36:
	mov	rsi, QWORD PTR 72[rbp]
	test	rsi, rsi
	je	.L41
	mov	rdi, rbp
	call	fsl_sata_check_collision@PLT
	test	eax, eax
	je	.L91
.L41:
	cmp	QWORD PTR 24[rbp], 0
	jne	.L1
	mov	eax, DWORD PTR 36[rbp]
	cmp	eax, 3
	jle	.L1
	cmp	QWORD PTR 48[rbp], 0
	mov	rdx, QWORD PTR 56[rbp]
	je	.L44
	add	rdx, 60
.L44:
	mov	edx, DWORD PTR [rdx]
	test	DWORD PTR CTS_SATA_CAPS_D_PMREQ[rip], edx
	je	.L1
	mov	edx, DWORD PTR hz[rip]
	cmp	eax, 4
	je	.L92
	test	edx, edx
	lea	esi, 7[rdx]
	cmovns	esi, edx
	sar	esi, 3
.L46:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	lea	rdi, 40[rbp]
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	jmp	callout_schedule@PLT
	.p2align 4,,10
	.p2align 3
.L1:
	.cfi_restore_state
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L32:
	.cfi_restore_state
	mov	rsi, r12
	mov	rdi, rbp
	call	fsl_sata_done@PLT
	mov	edx, DWORD PTR 12[rbp]
	mov	eax, DWORD PTR 32[rbp]
	test	edx, edx
	je	.L93
.L33:
	not	eax
	test	eax, edx
	jne	.L36
	cmp	r13d, 128
	je	.L36
	mov	rdi, rbp
	call	fsl_sata_rearm_timeout@PLT
	jmp	.L36
	.p2align 4,,10
	.p2align 3
.L86:
	mov	eax, DWORD PTR 8[r12]
	test	DWORD PTR CAM_ATAIO_FPDMA[rip], eax
	je	.L24
	mov	rcx, QWORD PTR 16[r12]
	mov	rax, QWORD PTR 104[rbp]
	sub	DWORD PTR 112[rbp], 1
	sub	DWORD PTR [rax+rcx*4], 1
	cmp	r13d, 128
	jne	.L48
	jmp	.L26
	.p2align 4,,10
	.p2align 3
.L88:
	mov	eax, DWORD PTR CAM_ATAIO_CONTROL[rip]
	test	DWORD PTR 8[r12], eax
	je	.L27
	mov	edx, DWORD PTR 12[r12]
	mov	eax, DWORD PTR ATA_A_RESET[rip]
	test	edx, eax
	je	.L27
	cmp	r13d, 131
	jne	.L27
	not	eax
	mov	rsi, r12
	mov	rdi, rbp
	and	eax, edx
	mov	DWORD PTR 12[r12], eax
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	jmp	fsl_sata_begin_transaction@PLT
	.p2align 4,,10
	.p2align 3
.L89:
	.cfi_restore_state
	mov	rsi, r12
	mov	rdi, rbp
	call	fsl_sata_process_read_log@PLT
	jmp	.L29
	.p2align 4,,10
	.p2align 3
.L17:
	mov	rdi, QWORD PTR XPT_SCSI_IO[rip]
	cmp	QWORD PTR [r12], rdi
	je	.L94
	or	eax, DWORD PTR CAM_ATA_STATUS_ERROR[rip]
	mov	ecx, DWORD PTR [rbx]
	mov	DWORD PTR 12[r12], eax
	mov	eax, 1
	sal	eax, cl
	jmp	.L20
	.p2align 4,,10
	.p2align 3
.L84:
	mov	edi, DWORD PTR 32[r12]
	mov	esi, 1
	call	xpt_freeze_devq@PLT
	mov	eax, DWORD PTR 12[r12]
	or	eax, DWORD PTR CAM_DEV_QFRZN[rip]
	mov	edx, eax
	jmp	.L12
	.p2align 4,,10
	.p2align 3
.L35:
	mov	edx, DWORD PTR 0[rbp]
	test	edx, edx
	jne	.L95
.L37:
	mov	eax, DWORD PTR 88[rbp]
	test	eax, eax
	jne	.L36
	cmp	QWORD PTR 80[rbp], 0
	je	.L36
	mov	rdi, rbp
	call	fsl_sata_issue_recovery@PLT
	jmp	.L36
	.p2align 4,,10
	.p2align 3
.L14:
	or	eax, DWORD PTR CAM_REQUEUE_REQ[rip]
	mov	ecx, DWORD PTR [rbx]
	mov	DWORD PTR 12[r12], eax
	mov	eax, 1
	sal	eax, cl
	jmp	.L20
	.p2align 4,,10
	.p2align 3
.L19:
	mov	esi, DWORD PTR 88[rbp]
	test	esi, esi
	je	.L96
.L23:
	or	eax, DWORD PTR CAM_CMD_TIMEOUT[rip]
	mov	ecx, DWORD PTR [rbx]
	mov	DWORD PTR 12[r12], eax
	mov	eax, 1
	sal	eax, cl
	jmp	.L20
	.p2align 4,,10
	.p2align 3
.L16:
	or	eax, DWORD PTR CAM_REQ_INVALID[rip]
	mov	ecx, DWORD PTR [rbx]
	mov	DWORD PTR 4[rbp], 1
	mov	DWORD PTR 12[r12], eax
	mov	eax, 1
	sal	eax, cl
	jmp	.L20
	.p2align 4,,10
	.p2align 3
.L18:
	mov	edi, DWORD PTR 88[rbp]
	mov	DWORD PTR 4[rbp], 1
	test	edi, edi
	je	.L97
.L22:
	or	eax, DWORD PTR CAM_UNCOR_PARITY[rip]
	mov	ecx, DWORD PTR [rbx]
	mov	DWORD PTR 12[r12], eax
	mov	eax, 1
	sal	eax, cl
	jmp	.L20
	.p2align 4,,10
	.p2align 3
.L91:
	mov	rsi, QWORD PTR 72[rbp]
	mov	QWORD PTR 72[rbp], 0
	mov	rdi, rbp
	call	fsl_sata_begin_transaction@PLT
	mov	edi, DWORD PTR 64[rbp]
	mov	esi, DWORD PTR TRUE[rip]
	call	xpt_release_simq@PLT
	jmp	.L41
	.p2align 4,,10
	.p2align 3
.L90:
	mov	rsi, r12
	mov	rdi, rbp
	call	fsl_sata_process_request_sense@PLT
	jmp	.L29
.L13:
	or	eax, DWORD PTR CAM_REQ_CMP_ERR[rip]
	mov	ecx, DWORD PTR [rbx]
	mov	DWORD PTR 4[rbp], 1
	mov	DWORD PTR 12[r12], eax
	mov	eax, 1
	sal	eax, cl
	jmp	.L20
	.p2align 4,,10
	.p2align 3
.L87:
	mov	edi, DWORD PTR 64[rbp]
	mov	esi, DWORD PTR TRUE[rip]
	call	xpt_release_simq@PLT
	mov	rdx, QWORD PTR XPT_ATA_IO[rip]
	jmp	.L26
	.p2align 4,,10
	.p2align 3
.L95:
	mov	rdi, rbp
	call	fsl_sata_stop@PLT
	mov	rdi, rbp
	call	fsl_sata_start@PLT
	jmp	.L37
	.p2align 4,,10
	.p2align 3
.L94:
	or	eax, DWORD PTR CAM_SCSI_STATUS_ERROR[rip]
	mov	ecx, DWORD PTR [rbx]
	mov	DWORD PTR 12[r12], eax
	mov	eax, DWORD PTR SCSI_STATUS_CHECK_COND[rip]
	mov	DWORD PTR 8[r12], eax
	mov	eax, 1
	sal	eax, cl
	jmp	.L20
	.p2align 4,,10
	.p2align 3
.L85:
	mov	edx, DWORD PTR SCSI_STATUS_OK[rip]
	mov	DWORD PTR 8[r12], edx
	jmp	.L20
	.p2align 4,,10
	.p2align 3
.L97:
	mov	edi, DWORD PTR 64[rbp]
	mov	esi, 1
	call	xpt_freeze_simq@PLT
	mov	eax, DWORD PTR CAM_STATUS_MASK[rip]
	not	eax
	and	eax, DWORD PTR 12[r12]
	or	eax, DWORD PTR CAM_RELEASE_SIMQ[rip]
	jmp	.L22
	.p2align 4,,10
	.p2align 3
.L96:
	mov	edi, DWORD PTR 64[rbp]
	mov	esi, 1
	call	xpt_freeze_simq@PLT
	mov	eax, DWORD PTR CAM_STATUS_MASK[rip]
	not	eax
	and	eax, DWORD PTR 12[r12]
	or	eax, DWORD PTR CAM_RELEASE_SIMQ[rip]
	jmp	.L23
	.p2align 4,,10
	.p2align 3
.L92:
	movsx	rsi, edx
	sar	edx, 31
	imul	rsi, rsi, 274877907
	sar	rsi, 38
	sub	esi, edx
	jmp	.L46
	.cfi_endproc
.LFE0:
	.size	fsl_sata_end_transaction, .-fsl_sata_end_transaction
	.comm	hz,4,4
	.comm	XPT_SCSI_IO,8,8
	.comm	XPT_ATA_IO,8,8
	.comm	TRUE,4,4
	.comm	SCSI_STATUS_OK,4,4
	.comm	SCSI_STATUS_CHECK_COND,4,4
	.comm	RECOVERY_REQUEST_SENSE,8,8
	.comm	RECOVERY_READ_LOG,8,8
	.comm	FSL_SATA_SLOT_EMPTY,4,4
	.comm	FSL_SATA_P_SIG,4,4
	.comm	FSL_SATA_P_CCR,4,4
	.comm	CTS_SATA_CAPS_D_PMREQ,4,4
	.comm	CAM_UNCOR_PARITY,4,4
	.comm	CAM_STATUS_MASK,4,4
	.comm	CAM_SCSI_STATUS_ERROR,4,4
	.comm	CAM_REQ_INVALID,4,4
	.comm	CAM_REQ_CMP_ERR,4,4
	.comm	CAM_REQ_CMP,4,4
	.comm	CAM_REQUEUE_REQ,4,4
	.comm	CAM_RELEASE_SIMQ,4,4
	.comm	CAM_DIS_AUTOSENSE,4,4
	.comm	CAM_DIR_NONE,4,4
	.comm	CAM_DIR_MASK,4,4
	.comm	CAM_DIR_IN,4,4
	.comm	CAM_DEV_QFRZN,4,4
	.comm	CAM_CMD_TIMEOUT,4,4
	.comm	CAM_ATA_STATUS_ERROR,4,4
	.comm	CAM_ATAIO_NEEDRESULT,4,4
	.comm	CAM_ATAIO_FPDMA,4,4
	.comm	CAM_ATAIO_CONTROL,4,4
	.comm	BUS_DMASYNC_POSTWRITE,4,4
	.comm	BUS_DMASYNC_POSTREAD,4,4
	.comm	ATA_A_RESET,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_fsl_sata.c_fsl_sata_end_transaction.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	fsl_sata_end_transaction, %function
fsl_sata_end_transaction:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	mov	r6, r0
	ldr	fp, .L104
	ldr	r10, .L104+4
	ldr	r4, [r0, #16]
	ldr	r3, [r10]
	ldr	r2, [fp]
	sub	sp, sp, #12
	orr	r2, r2, r3
	mov	r7, r1
	ldr	r0, [r4, #88]
	ldr	r1, [r4, #84]
	ldr	r5, [r6, #4]
	bl	bus_dmamap_sync
	mov	r1, r6
	mov	r0, r4
	bl	FSL_SATA_CLP
	ldr	r8, .L104+8
	ldr	r2, [r5]
	ldr	r3, [r8]
	mov	r9, r0
	cmp	r2, r3
	beq	.L87
	ldr	r3, .L104+12
	ldr	r1, .L104+16
	ldr	lr, [r3]
	ldr	r0, [r5, #4]
	ldr	ip, [r1]
	and	r0, r0, lr
	cmp	r0, ip
	str	r2, [sp, #4]
	bne	.L88
.L49:
	mov	r1, #1
	ldr	r3, [r6]
	cmp	r7, #131
	ldr	r0, [r5, #8]
	lsl	r3, r1, r3
	beq	.L11
	ldr	r9, .L104+20
	ldr	r2, [r4]
	ldr	ip, [r9]
	ldr	lr, [r4, #56]
	and	ip, ip, r0
	orr	r3, r2, r3
	orrs	ip, ip, lr
	str	r3, [r4]
	beq	.L89
.L12:
	ldr	r9, .L104+24
	sub	r3, r7, #128
	ldr	r2, [r9]
	bic	r2, r0, r2
	str	r2, [r5, #8]
	cmp	r3, #6
	ldrls	pc, [pc, r3, asl #2]
	b	.L13
.L15:
	.word	.L19
	.word	.L17
	.word	.L18
	.word	.L13
	.word	.L17
	.word	.L16
	.word	.L14
.L88:
	ldr	r0, [r9]
	bl	le32toh
	ldr	r3, .L104+12
	ldr	r2, [sp, #4]
	ldr	r1, .L104+16
	ldr	r3, [r3]
	ldr	ip, [r5, #4]
	sub	r2, r2, r0
	ldr	lr, [r1]
	str	r2, [r5, #8]
	and	r3, r3, ip
.L6:
	cmp	r3, lr
	beq	.L49
	ldr	r3, .L104+28
	ldr	r1, [r6, #12]
	ldr	r3, [r3]
	ldr	r0, [r4, #80]
	tst	ip, r3
	ldrne	r2, [fp]
	ldreq	r2, [r10]
	bl	bus_dmamap_sync
	ldr	r1, [r6, #12]
	ldr	r0, [r4, #80]
	bl	bus_dmamap_unload
	b	.L49
.L87:
	cmp	r7, #129
	beq	.L3
	ldr	r3, .L104+32
	ldr	r2, [r5, #4]
	ldr	r3, [r3]
	tst	r2, r3
	beq	.L4
.L3:
	mov	r1, r6
	mov	r0, r4
	bl	FSL_SATA_CTP
	ldr	r3, [r0]
	ldr	r1, .L104+36
	ldr	r2, [r3, #8]
	ldr	r1, [r1]
	str	r2, [r5, #56]
	ldr	r2, [r3, #12]
	str	r2, [r5, #52]
	ldr	r2, [r3, #28]
	ldr	ip, [r3, #20]
	ldr	lr, [r3, #16]
	ldr	r0, [r3, #24]
	str	r2, [r5, #48]
	ldr	r2, [r3, #32]
	str	lr, [r5, #16]
	str	r2, [r5, #44]
	ldr	r2, [r3, #36]
	str	ip, [r5, #20]
	str	r2, [r5, #40]
	ldr	r2, [r3, #40]
	ldr	ip, [r5, #4]
	str	r2, [r5, #36]
	ldr	r2, [r3, #48]
	ldr	r3, [r3, #52]
	tst	ip, r1
	str	r0, [r5, #24]
	str	r2, [r5, #28]
	str	r3, [r5, #32]
	beq	.L5
	ldr	r3, .L104+40
	ldr	r2, [r5, #8]
	ldr	r3, [r3]
	tst	r2, r3
	beq	.L90
.L5:
	ldr	r3, .L104+44
	ldr	r1, .L104+12
	ldr	r0, [r3]
	ldr	r2, .L104+16
	ldr	r3, [r1]
	tst	ip, r0
	ldr	lr, [r2]
	and	r3, r3, ip
	bne	.L6
	cmp	r3, lr
	beq	.L49
	ldr	r0, [r9]
	ldr	r9, [r5]
	bl	le32toh
	ldr	r1, .L104+12
	ldr	ip, [r5, #4]
	ldr	r3, [r1]
	ldr	r2, .L104+16
	sub	r9, r9, r0
	ldr	lr, [r2]
	str	r9, [r5, #12]
	and	r3, r3, ip
	b	.L6
.L11:
	ldr	r9, .L104+24
	ldr	ip, .L104+48
	ldr	r2, [r9]
	ldr	r1, .L104+52
	bic	r2, r0, r2
	ldr	ip, [ip]
	ldr	r1, [r1]
	ldr	r0, [r5]
	orr	r2, r2, ip
	cmp	r0, r1
	str	r2, [r5, #8]
	beq	.L91
.L20:
	mov	r0, #0
	mov	r2, #1
	ldr	r1, [r4, #8]
	ldr	ip, .L104+56
	bic	r1, r1, r3
	ldr	r10, [ip]
	ldr	ip, [r4, #12]
	str	r1, [r4, #8]
	ldr	r1, [r4, #16]
	bic	ip, ip, r3
	str	ip, [r4, #12]
	ldr	lr, [r4, #76]
	ldr	ip, [r5, #12]
	bic	r3, r1, r3
	str	r3, [r4, #16]
	str	r10, [r6, #8]
	ldr	r3, [lr, ip, lsl #2]
	ldr	r1, [r4, #20]
	sub	r3, r3, #1
	sub	r1, r1, #1
	str	r0, [r6, #4]
	str	r1, [r4, #20]
	str	r3, [lr, ip, lsl #2]
	ldr	r1, [r6]
	ldr	r3, .L104+60
	lsl	r2, r2, r1
	ldr	r0, [r4, #72]
	ldr	r1, [r3]
	bl	ATA_OUTL
	ldr	r1, [r8]
	ldr	r3, [r5]
	cmp	r3, r1
	beq	.L92
.L24:
	cmp	r7, #128
	beq	.L27
.L48:
	mov	r2, #1
	ldr	r0, [r6]
	ldr	r3, [r4, #24]
	lsl	r2, r2, r0
	cmp	r3, r2
	bic	r3, r3, r2
	str	r3, [r4, #24]
	beq	.L93
.L26:
	ldr	r3, [r5]
	cmp	r3, r1
	beq	.L94
.L27:
	ldr	r2, .L104+64
	ldr	r3, [r5, #16]
	ldr	r2, [r2]
	cmp	r3, r2
	beq	.L95
	ldr	r2, .L104+68
	ldr	r2, [r2]
	cmp	r3, r2
	beq	.L96
	cmp	r7, #132
	beq	.L31
	ldr	r2, .L104+72
	ldr	r1, [r9]
	ldr	r3, [r5, #8]
	ldr	r2, [r2]
	and	r3, r3, r1
	cmp	r3, r2
	bne	.L32
	ldr	r3, .L104+76
	ldr	r2, [r5, #4]
	ldr	r3, [r3]
	tst	r2, r3
	bne	.L32
.L31:
	ldr	r3, [r4, #52]
	ldr	r1, [r6]
	ldr	r2, [r4, #60]
	add	r3, r3, #1
	str	r5, [r2, r1, lsl #2]
	str	r3, [r4, #52]
.L29:
	ldr	r3, [r4, #12]
	ldr	r2, [r4, #24]
	cmp	r3, #0
	bne	.L33
.L99:
	cmp	r2, #0
	bne	.L34
	ldr	r3, [r4, #4]
	cmp	r3, #0
	beq	.L35
.L34:
	mov	r0, r4
	bl	fsl_sata_reset
.L36:
	ldr	r1, [r4, #48]
	cmp	r1, #0
	beq	.L41
	mov	r0, r4
	bl	fsl_sata_check_collision
	subs	r3, r0, #0
	beq	.L97
.L41:
	ldr	r3, [r4, #20]
	cmp	r3, #0
	bne	.L1
	ldr	r3, [r4, #28]
	cmp	r3, #3
	ble	.L1
	ldr	r1, [r4, #36]
	ldr	r2, [r4, #40]
	cmp	r1, #0
	ldr	r0, .L104+80
	addne	r2, r2, #60
	ldr	r1, [r2]
	ldr	r2, [r0]
	tst	r1, r2
	beq	.L1
	ldr	r2, .L104+84
	cmp	r3, #4
	add	r0, r4, #32
	ldr	r3, [r2]
	beq	.L98
	add	r1, r3, #7
	cmp	r3, #0
	movlt	r3, r1
	asr	r1, r3, #3
.L46:
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	b	callout_schedule
.L1:
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L32:
	mov	r1, r5
	mov	r0, r4
	bl	fsl_sata_done
	ldr	r3, [r4, #12]
	ldr	r2, [r4, #24]
	cmp	r3, #0
	beq	.L99
.L33:
	subs	r7, r7, #128
	bic	r3, r3, r2
	movne	r7, #1
	cmp	r3, #0
	movne	r7, #0
	cmp	r7, #0
	beq	.L36
	mov	r0, r4
	bl	fsl_sata_rearm_timeout
	b	.L36
.L92:
	ldr	r3, .L104+44
	ldr	r2, [r5, #4]
	ldr	r3, [r3]
	tst	r2, r3
	beq	.L24
	ldr	r3, [r4, #68]
	ldr	r0, [r5, #12]
	ldr	r2, [r4, #64]
	sub	r3, r3, #1
	str	r3, [r4, #68]
	ldr	r3, [r2, r0, lsl #2]
	cmp	r7, #128
	sub	r3, r3, #1
	str	r3, [r2, r0, lsl #2]
	bne	.L48
	b	.L26
.L94:
	ldr	r2, .L104+36
	ldr	r3, [r5, #4]
	ldr	r2, [r2]
	tst	r2, r3
	beq	.L27
	sub	r1, r7, #131
	clz	r1, r1
	ldr	r2, .L104+40
	ldr	r3, [r5, #8]
	ldr	r2, [r2]
	lsr	r1, r1, #5
	and	r0, r3, r2
	cmp	r0, #0
	moveq	r1, #0
	cmp	r1, #0
	beq	.L27
	mov	r1, r5
	mov	r0, r4
	bic	r3, r3, r2
	str	r3, [r5, #8]
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	b	fsl_sata_begin_transaction
.L95:
	mov	r1, r5
	mov	r0, r4
	bl	fsl_sata_process_read_log
	b	.L29
.L17:
	ldr	r3, .L104+52
	ldr	r1, [r5]
	ldr	r3, [r3]
	mov	r0, #1
	cmp	r1, r3
	ldrne	r3, .L104+88
	beq	.L100
.L85:
	ldr	r1, [r3]
	ldr	r3, [r6]
	orr	r2, r1, r2
	str	r2, [r5, #8]
	lsl	r3, r0, r3
	b	.L20
.L89:
	ldr	r0, [r5, #20]
	bl	xpt_freeze_devq
	ldr	r3, [r9]
	ldr	r2, [r5, #8]
	orr	r0, r2, r3
	b	.L12
.L35:
	ldr	r3, [r4]
	cmp	r3, #0
	bne	.L101
.L37:
	ldr	r3, [r4, #56]
	cmp	r3, #0
	bne	.L36
	ldr	r3, [r4, #52]
	cmp	r3, #0
	beq	.L36
	mov	r0, r4
	bl	fsl_sata_issue_recovery
	b	.L36
.L14:
	mov	r0, #1
	ldr	r3, .L104+92
	b	.L85
.L16:
	mov	r3, #1
	ldr	r1, .L104+96
.L84:
	str	r3, [r4, #4]
	ldr	r1, [r1]
	ldr	r0, [r6]
	orr	r2, r1, r2
	str	r2, [r5, #8]
	lsl	r3, r3, r0
	b	.L20
.L18:
	mov	r1, #1
	ldr	r3, [r4, #56]
	str	r1, [r4, #4]
	cmp	r3, #0
	beq	.L102
.L22:
	mov	r0, #1
	ldr	r3, .L104+100
	b	.L85
.L19:
	ldr	r3, [r4, #56]
	cmp	r3, #0
	beq	.L103
.L23:
	mov	r0, #1
	ldr	r3, .L104+104
	b	.L85
.L4:
	mov	r1, #44
	add	r0, r5, #16
	bl	bzero
	ldr	ip, [r5, #4]
	b	.L5
.L97:
	ldr	r1, [r4, #48]
	mov	r0, r4
	str	r3, [r4, #48]
	bl	fsl_sata_begin_transaction
	ldr	r3, .L104+108
	ldr	r0, [r4, #44]
	ldr	r1, [r3]
	bl	xpt_release_simq
	b	.L41
.L96:
	mov	r1, r5
	mov	r0, r4
	bl	fsl_sata_process_request_sense
	b	.L29
.L13:
	mov	r3, #1
	ldr	r1, .L104+112
	b	.L84
.L93:
	ldr	r3, .L104+108
	ldr	r0, [r4, #44]
	ldr	r1, [r3]
	bl	xpt_release_simq
	ldr	r1, [r8]
	b	.L26
.L101:
	mov	r0, r4
	bl	fsl_sata_stop
	mov	r0, r4
	bl	fsl_sata_start
	b	.L37
.L90:
	ldr	r3, .L104+116
	ldr	r0, [r4, #72]
	ldr	r1, [r3]
	bl	ATA_INL
	asr	r2, r0, #24
	asr	r3, r0, #16
	str	r0, [r5, #28]
	asr	r0, r0, #8
	ldr	ip, [r5, #4]
	str	r2, [r5, #24]
	str	r3, [r5, #20]
	str	r0, [r5, #16]
	b	.L5
.L100:
	ldr	r1, .L104+72
	ldr	r3, .L104+120
	ldr	r1, [r1]
	ldr	ip, [r3]
	ldr	r3, [r6]
	orr	r2, r1, r2
	str	r2, [r5, #8]
	str	ip, [r5, #4]
	lsl	r3, r0, r3
	b	.L20
.L91:
	ldr	r2, .L104+124
	ldr	r2, [r2]
	str	r2, [r5, #4]
	b	.L20
.L103:
	mov	r1, #1
	ldr	r0, [r4, #44]
	bl	xpt_freeze_simq
	ldr	r3, .L104+128
	ldr	r1, [r9]
	ldr	r2, [r5, #8]
	ldr	r3, [r3]
	bic	r2, r2, r1
	orr	r2, r2, r3
	b	.L23
.L102:
	ldr	r0, [r4, #44]
	bl	xpt_freeze_simq
	ldr	r3, .L104+128
	ldr	r1, [r9]
	ldr	r2, [r5, #8]
	ldr	r3, [r3]
	bic	r2, r2, r1
	orr	r2, r2, r3
	b	.L22
.L98:
	ldr	r2, .L104+132
	asr	r1, r3, #31
	smull	ip, r3, r2, r3
	rsb	r1, r1, r3, asr #6
	b	.L46
.L105:
	.align	2
.L104:
	.word	BUS_DMASYNC_POSTREAD
	.word	BUS_DMASYNC_POSTWRITE
	.word	XPT_ATA_IO
	.word	CAM_DIR_MASK
	.word	CAM_DIR_NONE
	.word	CAM_DEV_QFRZN
	.word	CAM_STATUS_MASK
	.word	CAM_DIR_IN
	.word	CAM_ATAIO_NEEDRESULT
	.word	CAM_ATAIO_CONTROL
	.word	ATA_A_RESET
	.word	CAM_ATAIO_FPDMA
	.word	CAM_REQ_CMP
	.word	XPT_SCSI_IO
	.word	FSL_SATA_SLOT_EMPTY
	.word	FSL_SATA_P_CCR
	.word	RECOVERY_READ_LOG
	.word	RECOVERY_REQUEST_SENSE
	.word	CAM_SCSI_STATUS_ERROR
	.word	CAM_DIS_AUTOSENSE
	.word	CTS_SATA_CAPS_D_PMREQ
	.word	hz
	.word	CAM_ATA_STATUS_ERROR
	.word	CAM_REQUEUE_REQ
	.word	CAM_REQ_INVALID
	.word	CAM_UNCOR_PARITY
	.word	CAM_CMD_TIMEOUT
	.word	TRUE
	.word	CAM_REQ_CMP_ERR
	.word	FSL_SATA_P_SIG
	.word	SCSI_STATUS_CHECK_COND
	.word	SCSI_STATUS_OK
	.word	CAM_RELEASE_SIMQ
	.word	274877907
	.size	fsl_sata_end_transaction, .-fsl_sata_end_transaction
	.comm	hz,4,4
	.comm	XPT_SCSI_IO,4,4
	.comm	XPT_ATA_IO,4,4
	.comm	TRUE,4,4
	.comm	SCSI_STATUS_OK,4,4
	.comm	SCSI_STATUS_CHECK_COND,4,4
	.comm	RECOVERY_REQUEST_SENSE,4,4
	.comm	RECOVERY_READ_LOG,4,4
	.comm	FSL_SATA_SLOT_EMPTY,4,4
	.comm	FSL_SATA_P_SIG,4,4
	.comm	FSL_SATA_P_CCR,4,4
	.comm	CTS_SATA_CAPS_D_PMREQ,4,4
	.comm	CAM_UNCOR_PARITY,4,4
	.comm	CAM_STATUS_MASK,4,4
	.comm	CAM_SCSI_STATUS_ERROR,4,4
	.comm	CAM_REQ_INVALID,4,4
	.comm	CAM_REQ_CMP_ERR,4,4
	.comm	CAM_REQ_CMP,4,4
	.comm	CAM_REQUEUE_REQ,4,4
	.comm	CAM_RELEASE_SIMQ,4,4
	.comm	CAM_DIS_AUTOSENSE,4,4
	.comm	CAM_DIR_NONE,4,4
	.comm	CAM_DIR_MASK,4,4
	.comm	CAM_DIR_IN,4,4
	.comm	CAM_DEV_QFRZN,4,4
	.comm	CAM_CMD_TIMEOUT,4,4
	.comm	CAM_ATA_STATUS_ERROR,4,4
	.comm	CAM_ATAIO_NEEDRESULT,4,4
	.comm	CAM_ATAIO_FPDMA,4,4
	.comm	CAM_ATAIO_CONTROL,4,4
	.comm	BUS_DMASYNC_POSTWRITE,4,4
	.comm	BUS_DMASYNC_POSTREAD,4,4
	.comm	ATA_A_RESET,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
