	.file	"extr_gfx_v7_0.c_gfx_v7_0_init_gfx_cgpg.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	gfx_v7_0_init_gfx_cgpg, @function
gfx_v7_0_init_gfx_cgpg:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	cmp	QWORD PTR 32[rbp], 0
	mov	esi, DWORD PTR RLC_CLEAR_STATE_DESCRIPTOR_OFFSET[rip]
	mov	edi, DWORD PTR mmRLC_GPM_SCRATCH_ADDR[rip]
	je	.L2
	call	WREG32@PLT
	mov	edi, DWORD PTR 28[rbp]
	call	upper_32_bits@PLT
	mov	edi, DWORD PTR mmRLC_GPM_SCRATCH_DATA[rip]
	mov	esi, eax
	call	WREG32@PLT
	mov	edi, DWORD PTR 28[rbp]
	call	lower_32_bits@PLT
	mov	edi, DWORD PTR mmRLC_GPM_SCRATCH_DATA[rip]
	mov	esi, eax
	call	WREG32@PLT
	mov	esi, DWORD PTR 0[rbp]
	mov	edi, DWORD PTR mmRLC_GPM_SCRATCH_DATA[rip]
	call	WREG32@PLT
.L3:
	cmp	QWORD PTR 8[rbp], 0
	je	.L7
	mov	esi, DWORD PTR RLC_SAVE_AND_RESTORE_STARTING_OFFSET[rip]
	mov	edi, DWORD PTR mmRLC_GPM_SCRATCH_ADDR[rip]
	call	WREG32@PLT
	mov	eax, DWORD PTR 16[rbp]
	test	eax, eax
	jle	.L7
	xor	ebx, ebx
	.p2align 4,,10
	.p2align 3
.L8:
	mov	rax, QWORD PTR 8[rbp]
	mov	edi, DWORD PTR mmRLC_GPM_SCRATCH_DATA[rip]
	mov	esi, DWORD PTR [rax+rbx*4]
	add	rbx, 1
	call	WREG32@PLT
	cmp	DWORD PTR 16[rbp], ebx
	jg	.L8
.L7:
	mov	edi, DWORD PTR mmRLC_PG_CNTL[rip]
	call	RREG32@PLT
	mov	esi, DWORD PTR RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK[rip]
	or	esi, eax
	cmp	eax, esi
	je	.L6
	mov	edi, DWORD PTR mmRLC_PG_CNTL[rip]
	call	WREG32@PLT
.L6:
	mov	esi, DWORD PTR 20[rbp]
	mov	edi, DWORD PTR mmRLC_SAVE_AND_RESTORE_BASE[rip]
	sar	esi, 8
	call	WREG32@PLT
	mov	esi, DWORD PTR 24[rbp]
	mov	edi, DWORD PTR mmRLC_JUMP_TABLE_RESTORE[rip]
	sar	esi, 8
	call	WREG32@PLT
	mov	edi, DWORD PTR mmCP_RB_WPTR_POLL_CNTL[rip]
	call	RREG32@PLT
	mov	esi, DWORD PTR CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK[rip]
	mov	ecx, DWORD PTR CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT[rip]
	mov	edi, DWORD PTR mmCP_RB_WPTR_POLL_CNTL[rip]
	not	esi
	and	eax, esi
	mov	esi, 96
	sal	esi, cl
	or	esi, eax
	call	WREG32@PLT
	mov	edi, DWORD PTR mmRLC_PG_DELAY[rip]
	mov	esi, 269488144
	call	WREG32@PLT
	mov	edi, DWORD PTR mmRLC_PG_DELAY_2[rip]
	call	RREG32@PLT
	mov	edi, DWORD PTR mmRLC_PG_DELAY_2[rip]
	xor	al, al
	mov	esi, eax
	or	esi, 3
	call	WREG32@PLT
	mov	edi, DWORD PTR mmRLC_AUTO_PG_CTRL[rip]
	call	RREG32@PLT
	mov	esi, DWORD PTR RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK[rip]
	mov	ecx, DWORD PTR RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT[rip]
	mov	edi, DWORD PTR mmRLC_AUTO_PG_CTRL[rip]
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	not	esi
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	and	eax, esi
	mov	esi, 1792
	sal	esi, cl
	or	esi, eax
	jmp	WREG32@PLT
	.p2align 4,,10
	.p2align 3
.L2:
	.cfi_restore_state
	call	WREG32@PLT
	mov	edi, DWORD PTR mmRLC_GPM_SCRATCH_DATA[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	edi, DWORD PTR mmRLC_GPM_SCRATCH_DATA[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	edi, DWORD PTR mmRLC_GPM_SCRATCH_DATA[rip]
	xor	esi, esi
	call	WREG32@PLT
	jmp	.L3
	.cfi_endproc
.LFE0:
	.size	gfx_v7_0_init_gfx_cgpg, .-gfx_v7_0_init_gfx_cgpg
	.comm	mmRLC_SAVE_AND_RESTORE_BASE,4,4
	.comm	mmRLC_PG_DELAY_2,4,4
	.comm	mmRLC_PG_DELAY,4,4
	.comm	mmRLC_PG_CNTL,4,4
	.comm	mmRLC_JUMP_TABLE_RESTORE,4,4
	.comm	mmRLC_GPM_SCRATCH_DATA,4,4
	.comm	mmRLC_GPM_SCRATCH_ADDR,4,4
	.comm	mmRLC_AUTO_PG_CTRL,4,4
	.comm	mmCP_RB_WPTR_POLL_CNTL,4,4
	.comm	RLC_SAVE_AND_RESTORE_STARTING_OFFSET,4,4
	.comm	RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK,4,4
	.comm	RLC_CLEAR_STATE_DESCRIPTOR_OFFSET,4,4
	.comm	RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT,4,4
	.comm	RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK,4,4
	.comm	CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT,4,4
	.comm	CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_gfx_v7_0.c_gfx_v7_0_init_gfx_cgpg.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	gfx_v7_0_init_gfx_cgpg, %function
gfx_v7_0_init_gfx_cgpg:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	ldr	r4, [r0, #24]
	ldr	r7, .L12
	ldr	r3, .L12+4
	cmp	r4, #0
	mov	r5, r0
	ldr	r6, .L12+8
	ldr	r0, [r7]
	ldr	r1, [r3]
	beq	.L2
	bl	WREG32
	ldr	r0, [r5, #20]
	ldr	r4, [r6]
	bl	upper_32_bits
	mov	r1, r0
	mov	r0, r4
	bl	WREG32
	ldr	r0, [r5, #20]
	ldr	r4, [r6]
	bl	lower_32_bits
	mov	r1, r0
	mov	r0, r4
	bl	WREG32
	ldr	r0, [r6]
	ldr	r1, [r5]
	bl	WREG32
.L3:
	ldr	r3, [r5, #4]
	cmp	r3, #0
	beq	.L7
	ldr	r3, .L12+12
	ldr	r0, [r7]
	ldr	r1, [r3]
	bl	WREG32
	ldr	r3, [r5, #8]
	cmp	r3, #0
	ble	.L7
	mov	r4, #0
.L8:
	ldr	r3, [r5, #4]
	ldr	r0, [r6]
	ldr	r1, [r3, r4, lsl #2]
	bl	WREG32
	ldr	r3, [r5, #8]
	add	r4, r4, #1
	cmp	r3, r4
	bgt	.L8
.L7:
	ldr	r4, .L12+16
	ldr	r0, [r4]
	bl	RREG32
	ldr	r3, .L12+20
	ldr	r1, [r3]
	bics	r3, r1, r0
	orr	r1, r0, r1
	beq	.L6
	ldr	r0, [r4]
	bl	WREG32
.L6:
	ldr	r1, [r5, #12]
	ldr	r3, .L12+24
	asr	r1, r1, #8
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L12+28
	ldr	r1, [r5, #16]
	ldr	r4, .L12+32
	ldr	r0, [r3]
	asr	r1, r1, #8
	bl	WREG32
	ldr	r0, [r4]
	bl	RREG32
	mov	r1, #96
	ldr	r3, .L12+36
	ldr	r2, .L12+40
	ldr	r3, [r3]
	ldr	r2, [r2]
	bic	r3, r0, r3
	orr	r1, r3, r1, lsl r2
	ldr	r0, [r4]
	bl	WREG32
	ldr	r3, .L12+44
	ldr	r5, .L12+48
	ldr	r0, [r3]
	ldr	r1, .L12+52
	bl	WREG32
	ldr	r0, [r5]
	bl	RREG32
	ldr	r4, .L12+56
	bic	r1, r0, #255
	orr	r1, r1, #3
	ldr	r0, [r5]
	bl	WREG32
	ldr	r0, [r4]
	bl	RREG32
	mov	r1, #1792
	ldr	r3, .L12+60
	ldr	r2, .L12+64
	ldr	r3, [r3]
	ldr	r2, [r2]
	bic	r3, r0, r3
	orr	r1, r3, r1, lsl r2
	ldr	r0, [r4]
	pop	{r4, r5, r6, r7, r8, lr}
	b	WREG32
.L2:
	bl	WREG32
	mov	r1, r4
	ldr	r0, [r6]
	bl	WREG32
	mov	r1, r4
	ldr	r0, [r6]
	bl	WREG32
	mov	r1, r4
	ldr	r0, [r6]
	bl	WREG32
	b	.L3
.L13:
	.align	2
.L12:
	.word	mmRLC_GPM_SCRATCH_ADDR
	.word	RLC_CLEAR_STATE_DESCRIPTOR_OFFSET
	.word	mmRLC_GPM_SCRATCH_DATA
	.word	RLC_SAVE_AND_RESTORE_STARTING_OFFSET
	.word	mmRLC_PG_CNTL
	.word	RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK
	.word	mmRLC_SAVE_AND_RESTORE_BASE
	.word	mmRLC_JUMP_TABLE_RESTORE
	.word	mmCP_RB_WPTR_POLL_CNTL
	.word	CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK
	.word	CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT
	.word	mmRLC_PG_DELAY
	.word	mmRLC_PG_DELAY_2
	.word	269488144
	.word	mmRLC_AUTO_PG_CTRL
	.word	RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK
	.word	RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT
	.size	gfx_v7_0_init_gfx_cgpg, .-gfx_v7_0_init_gfx_cgpg
	.comm	mmRLC_SAVE_AND_RESTORE_BASE,4,4
	.comm	mmRLC_PG_DELAY_2,4,4
	.comm	mmRLC_PG_DELAY,4,4
	.comm	mmRLC_PG_CNTL,4,4
	.comm	mmRLC_JUMP_TABLE_RESTORE,4,4
	.comm	mmRLC_GPM_SCRATCH_DATA,4,4
	.comm	mmRLC_GPM_SCRATCH_ADDR,4,4
	.comm	mmRLC_AUTO_PG_CTRL,4,4
	.comm	mmCP_RB_WPTR_POLL_CNTL,4,4
	.comm	RLC_SAVE_AND_RESTORE_STARTING_OFFSET,4,4
	.comm	RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK,4,4
	.comm	RLC_CLEAR_STATE_DESCRIPTOR_OFFSET,4,4
	.comm	RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT,4,4
	.comm	RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK,4,4
	.comm	CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT,4,4
	.comm	CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
