	.file	"extr_gmc_v10_0.c_gmc_v10_0_vm_fault_interrupt_state.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	gmc_v10_0_vm_fault_interrupt_state, @function
gmc_v10_0_vm_fault_interrupt_state:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	push	r15
	push	r14
	push	r13
	.cfi_offset 15, -24
	.cfi_offset 14, -32
	.cfi_offset 13, -40
	mov	r13, rdi
	push	r12
	push	rbx
	sub	rsp, 24
	.cfi_offset 12, -48
	.cfi_offset 3, -56
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -56[rbp], rax
	xor	eax, eax
	movsx	rax, DWORD PTR AMDGPU_MAX_VMHUBS[rip]
	mov	rbx, rsp
	lea	rax, 15[0+rax*4]
	mov	rdx, rax
	and	rax, -4096
	sub	rbx, rax
	and	rdx, -16
	mov	rax, rbx
	cmp	rsp, rax
	je	.L3
.L22:
	sub	rsp, 4096
	or	QWORD PTR 4088[rsp], 0
	cmp	rsp, rax
	jne	.L22
.L3:
	and	edx, 4095
	sub	rsp, rdx
	test	rdx, rdx
	jne	.L23
.L4:
	mov	rdx, QWORD PTR AMDGPU_GFXHUB_0[rip]
	mov	rbx, rsp
	mov	eax, DWORD PTR GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK[rip]
	or	eax, DWORD PTR GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK[rip]
	or	eax, DWORD PTR GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK[rip]
	or	eax, DWORD PTR GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK[rip]
	or	eax, DWORD PTR GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK[rip]
	or	eax, DWORD PTR GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK[rip]
	or	eax, DWORD PTR GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK[rip]
	mov	DWORD PTR [rbx+rdx*4], eax
	mov	rdx, QWORD PTR AMDGPU_MMHUB_0[rip]
	mov	eax, DWORD PTR MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK[rip]
	or	eax, DWORD PTR MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK[rip]
	or	eax, DWORD PTR MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK[rip]
	or	eax, DWORD PTR MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK[rip]
	or	eax, DWORD PTR MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK[rip]
	or	eax, DWORD PTR MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK[rip]
	or	eax, DWORD PTR MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK[rip]
	mov	DWORD PTR [rbx+rdx*4], eax
	cmp	ecx, 128
	je	.L5
	cmp	ecx, 129
	jne	.L6
	mov	rax, QWORD PTR 0[r13]
	xor	r14d, r14d
	lea	r12, [rax+rdx*4]
	.p2align 4,,10
	.p2align 3
.L7:
	mov	r15d, DWORD PTR [r12]
	add	r15d, r14d
	add	r14d, 1
	mov	edi, r15d
	call	RREG32@PLT
	mov	rdx, QWORD PTR AMDGPU_MMHUB_0[rip]
	mov	edi, r15d
	mov	esi, DWORD PTR [rbx+rdx*4]
	not	esi
	and	esi, eax
	call	WREG32@PLT
	cmp	r14d, 16
	jne	.L7
	mov	rax, QWORD PTR 0[r13]
	mov	rdx, QWORD PTR AMDGPU_GFXHUB_0[rip]
	xor	r13d, r13d
	lea	r12, [rax+rdx*4]
	.p2align 4,,10
	.p2align 3
.L8:
	mov	r14d, DWORD PTR [r12]
	add	r14d, r13d
	add	r13d, 1
	mov	edi, r14d
	call	RREG32@PLT
	mov	rdx, QWORD PTR AMDGPU_GFXHUB_0[rip]
	mov	edi, r14d
	mov	esi, DWORD PTR [rbx+rdx*4]
	not	esi
	and	esi, eax
	call	WREG32@PLT
	cmp	r13d, 16
	jne	.L8
.L6:
	mov	rax, QWORD PTR -56[rbp]
	xor	rax, QWORD PTR fs:40
	jne	.L24
	lea	rsp, -40[rbp]
	xor	eax, eax
	pop	rbx
	pop	r12
	pop	r13
	pop	r14
	pop	r15
	pop	rbp
	.cfi_remember_state
	.cfi_def_cfa 7, 8
	ret
	.p2align 4,,10
	.p2align 3
.L5:
	.cfi_restore_state
	mov	rax, QWORD PTR 0[r13]
	xor	r12d, r12d
	lea	r14, [rax+rdx*4]
	.p2align 4,,10
	.p2align 3
.L9:
	mov	r15d, DWORD PTR [r14]
	add	r15d, r12d
	add	r12d, 1
	mov	edi, r15d
	call	RREG32@PLT
	mov	rdx, QWORD PTR AMDGPU_MMHUB_0[rip]
	mov	edi, r15d
	or	eax, DWORD PTR [rbx+rdx*4]
	mov	esi, eax
	call	WREG32@PLT
	cmp	r12d, 16
	jne	.L9
	mov	rax, QWORD PTR 0[r13]
	mov	rdx, QWORD PTR AMDGPU_GFXHUB_0[rip]
	xor	r12d, r12d
	lea	r13, [rax+rdx*4]
	.p2align 4,,10
	.p2align 3
.L10:
	mov	r14d, DWORD PTR 0[r13]
	add	r14d, r12d
	add	r12d, 1
	mov	edi, r14d
	call	RREG32@PLT
	mov	rdx, QWORD PTR AMDGPU_GFXHUB_0[rip]
	mov	edi, r14d
	or	eax, DWORD PTR [rbx+rdx*4]
	mov	esi, eax
	call	WREG32@PLT
	cmp	r12d, 16
	jne	.L10
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L23:
	or	QWORD PTR -8[rsp+rdx], 0
	jmp	.L4
.L24:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	gmc_v10_0_vm_fault_interrupt_state, .-gmc_v10_0_vm_fault_interrupt_state
	.comm	MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	AMDGPU_MMHUB_0,8,8
	.comm	AMDGPU_MAX_VMHUBS,4,4
	.comm	AMDGPU_GFXHUB_0,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_gmc_v10_0.c_gmc_v10_0_vm_fault_interrupt_state.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	gmc_v10_0_vm_fault_interrupt_state, %function
gmc_v10_0_vm_fault_interrupt_state:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	add	fp, sp, #32
	sub	sp, sp, #12
	ldr	r2, .L17
	ldr	r4, .L17+4
	ldr	r2, [r2]
	ldr	r1, .L17+8
	lsl	r2, r2, #2
	add	r2, r2, #7
	bic	r2, r2, #7
	sub	sp, sp, r2
	mov	r5, sp
	ldr	lr, .L17+12
	ldr	r6, [r4]
	ldr	r2, .L17+16
	ldr	ip, .L17+20
	ldr	r1, [r1]
	ldr	r4, [lr]
	ldr	lr, .L17+24
	ldr	ip, [ip]
	orr	r1, r1, r6
	ldr	r2, [r2]
	ldr	r6, .L17+28
	ldr	lr, [lr]
	ldr	r6, [r6]
	orr	r2, r2, r4
	orr	r1, r1, ip
	ldr	r4, .L17+32
	ldr	ip, .L17+36
	orr	r2, r2, lr
	ldr	lr, .L17+40
	ldr	r4, [r4]
	ldr	ip, [ip]
	orr	r1, r1, r6
	ldr	r6, .L17+44
	ldr	lr, [lr]
	ldr	r6, [r6]
	orr	r2, r2, r4
	orr	r1, r1, ip
	ldr	r4, .L17+48
	ldr	ip, .L17+52
	orr	r2, r2, lr
	ldr	lr, .L17+56
	ldr	ip, [ip]
	orr	r1, r1, r6
	ldr	r4, [r4]
	ldr	r6, .L17+60
	ldr	r7, .L17+64
	ldr	lr, [lr]
	orr	r1, r1, ip
	mov	r8, r0
	ldr	ip, [r6]
	ldr	r0, .L17+68
	ldr	r10, [r7]
	orr	r2, r2, r4
	orr	r2, r2, lr
	cmp	r3, #128
	ldr	r0, [r0]
	str	r0, [fp, #-40]
	mov	r0,#0
	str	r1, [r5, ip, lsl #2]
	str	r2, [r5, r10, lsl #2]
	beq	.L2
	cmp	r3, #129
	bne	.L3
	mov	r9, #0
	ldr	r3, [r8]
	add	r10, r3, r10, lsl #2
.L4:
	ldr	r4, [r10]
	add	r4, r9, r4
	mov	r0, r4
	bl	RREG32
	mov	r3, r0
	ldr	r2, [r7]
	mov	r0, r4
	ldr	r1, [r5, r2, lsl #2]
	add	r9, r9, #1
	bic	r1, r3, r1
	bl	WREG32
	cmp	r9, #16
	bne	.L4
	mov	r7, #0
	ldr	r8, [r8]
	ldr	r3, [r6]
	add	r8, r8, r3, lsl #2
.L5:
	ldr	r4, [r8]
	add	r4, r7, r4
	mov	r0, r4
	bl	RREG32
	mov	r3, r0
	ldr	r2, [r6]
	mov	r0, r4
	ldr	r1, [r5, r2, lsl #2]
	add	r7, r7, #1
	bic	r1, r3, r1
	bl	WREG32
	cmp	r7, #16
	bne	.L5
.L3:
	ldr	r3, .L17+68
	ldr	r2, [r3]
	ldr	r3, [fp, #-40]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L16
	mov	r0, #0
	sub	sp, fp, #32
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L2:
	mov	r9, #0
	ldr	r3, [r8]
	add	r10, r3, r10, lsl #2
.L6:
	ldr	r4, [r10]
	add	r4, r9, r4
	mov	r0, r4
	bl	RREG32
	mov	r1, r0
	ldr	r3, [r7]
	mov	r0, r4
	ldr	r3, [r5, r3, lsl #2]
	add	r9, r9, #1
	orr	r1, r1, r3
	bl	WREG32
	cmp	r9, #16
	bne	.L6
	mov	r7, #0
	ldr	r8, [r8]
	ldr	r3, [r6]
	add	r8, r8, r3, lsl #2
.L7:
	ldr	r4, [r8]
	add	r4, r7, r4
	mov	r0, r4
	bl	RREG32
	mov	r1, r0
	ldr	r3, [r6]
	mov	r0, r4
	ldr	r3, [r5, r3, lsl #2]
	add	r7, r7, #1
	orr	r1, r1, r3
	bl	WREG32
	cmp	r7, #16
	bne	.L7
	b	.L3
.L16:
	bl	__stack_chk_fail
.L18:
	.align	2
.L17:
	.word	AMDGPU_MAX_VMHUBS
	.word	GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.word	GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.word	MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.word	MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.word	GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.word	MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.word	GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.word	MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.word	GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.word	MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.word	GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.word	MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.word	GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.word	MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
	.word	AMDGPU_GFXHUB_0
	.word	AMDGPU_MMHUB_0
	.word	.LC0
	.size	gmc_v10_0_vm_fault_interrupt_state, .-gmc_v10_0_vm_fault_interrupt_state
	.comm	MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK,4,4
	.comm	AMDGPU_MMHUB_0,4,4
	.comm	AMDGPU_MAX_VMHUBS,4,4
	.comm	AMDGPU_GFXHUB_0,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
