	.file	"extr_bnx2x_link.c_bnx2x_warpcore_link_reset.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	bnx2x_warpcore_link_reset, @function
bnx2x_warpcore_link_reset:
.LFB0:
	.cfi_startproc
	endbr64
	push	r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	xor	edx, edx
	push	r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	mov	r13, rsi
	push	r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	push	rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	sub	rsp, 16
	.cfi_def_cfa_offset 64
	mov	r12, QWORD PTR [rsi]
	mov	rsi, rdi
	mov	rdi, r13
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 8[rsp], rax
	xor	eax, eax
	lea	r14, 4[rsp]
	call	bnx2x_sfp_e3_set_transmitter@PLT
	mov	rsi, r13
	mov	rdi, r12
	call	bnx2x_set_mdio_emac_per_phy@PLT
	mov	rsi, rbp
	mov	rdi, r13
	call	bnx2x_set_aer_mmd@PLT
	mov	edx, 1
	mov	rsi, rbp
	mov	rdi, r12
	call	bnx2x_warpcore_reset_lane@PLT
	mov	ecx, DWORD PTR MDIO_WC_REG_COMBO_IEEE0_MIICTRL[rip]
	mov	rsi, rbp
	mov	rdi, r12
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	mov	r8d, 49151
	call	bnx2x_cl45_read_and_write@PLT
	mov	ecx, DWORD PTR MDIO_WC_REG_IEEE0BLK_MIICNTL[rip]
	mov	rsi, rbp
	mov	rdi, r12
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	mov	r8d, 65534
	call	bnx2x_cl45_read_and_write@PLT
	xor	r8d, r8d
	mov	rsi, rbp
	mov	rdi, r12
	mov	ecx, DWORD PTR MDIO_AER_BLOCK_AER_REG[rip]
	mov	edx, DWORD PTR MDIO_REG_BANK_AER_BLOCK[rip]
	call	CL22_WR_OVER_CL45@PLT
	mov	ecx, DWORD PTR MDIO_WC_REG_XGXSBLK0_XGXSCONTROL[rip]
	mov	rsi, rbp
	mov	rdi, r12
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	mov	r8d, -17
	call	bnx2x_cl45_read_and_write@PLT
	mov	ecx, DWORD PTR MDIO_WC_REG_XGXSBLK1_LANECTRL2[rip]
	mov	rsi, rbp
	mov	rdi, r12
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	mov	r8d, 65280
	call	bnx2x_cl45_read_and_write@PLT
	mov	rsi, r13
	mov	rdi, rbp
	call	bnx2x_get_warpcore_lane@PLT
	mov	r8, r14
	mov	rsi, rbp
	mov	rdi, r12
	mov	ecx, DWORD PTR MDIO_WC_REG_XGXSBLK1_LANECTRL0[rip]
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	mov	ebx, eax
	call	bnx2x_cl45_read@PLT
	mov	r8d, 17
	mov	ecx, ebx
	mov	eax, DWORD PTR 0[rbp]
	sal	r8d, cl
	or	r8d, DWORD PTR 4[rsp]
	mov	DWORD PTR 4[rsp], r8d
	test	DWORD PTR FLAGS_WC_DUAL_MODE[rip], eax
	je	.L2
	mov	eax, 34
	sal	eax, cl
	or	r8d, eax
	mov	DWORD PTR 4[rsp], r8d
.L2:
	mov	ecx, DWORD PTR MDIO_WC_REG_XGXSBLK1_LANECTRL0[rip]
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	mov	rsi, rbp
	mov	rdi, r12
	call	bnx2x_cl45_write@PLT
	mov	r8, r14
	mov	rsi, rbp
	mov	rdi, r12
	mov	ecx, DWORD PTR MDIO_WC_REG_XGXSBLK1_LANECTRL1[rip]
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	call	bnx2x_cl45_read@PLT
	lea	ecx, [rbx+rbx]
	mov	r8d, 771
	mov	eax, 257
	sal	r8d, cl
	sal	eax, cl
	not	r8d
	and	r8d, DWORD PTR 4[rsp]
	or	r8d, eax
	mov	eax, DWORD PTR 0[rbp]
	mov	DWORD PTR 4[rsp], r8d
	test	DWORD PTR FLAGS_WC_DUAL_MODE[rip], eax
	je	.L3
	mov	eax, 3084
	sal	eax, cl
	not	eax
	and	r8d, eax
	mov	eax, 1028
	sal	eax, cl
	or	r8d, eax
	mov	DWORD PTR 4[rsp], r8d
.L3:
	mov	ecx, DWORD PTR MDIO_WC_REG_XGXSBLK1_LANECTRL1[rip]
	mov	edx, DWORD PTR MDIO_WC_DEVAD[rip]
	mov	rsi, rbp
	mov	rdi, r12
	call	bnx2x_cl45_write@PLT
	mov	rsi, rbp
	mov	rdi, r13
	call	bnx2x_set_aer_mmd@PLT
	mov	rax, QWORD PTR 8[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L13
	add	rsp, 16
	.cfi_remember_state
	.cfi_def_cfa_offset 48
	pop	rbx
	.cfi_def_cfa_offset 40
	pop	rbp
	.cfi_def_cfa_offset 32
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	ret
.L13:
	.cfi_restore_state
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	bnx2x_warpcore_link_reset, .-bnx2x_warpcore_link_reset
	.comm	MDIO_WC_REG_XGXSBLK1_LANECTRL2,4,4
	.comm	MDIO_WC_REG_XGXSBLK1_LANECTRL1,4,4
	.comm	MDIO_WC_REG_XGXSBLK1_LANECTRL0,4,4
	.comm	MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,4,4
	.comm	MDIO_WC_REG_IEEE0BLK_MIICNTL,4,4
	.comm	MDIO_WC_REG_COMBO_IEEE0_MIICTRL,4,4
	.comm	MDIO_WC_DEVAD,4,4
	.comm	MDIO_REG_BANK_AER_BLOCK,4,4
	.comm	MDIO_AER_BLOCK_AER_REG,4,4
	.comm	FLAGS_WC_DUAL_MODE,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_bnx2x_link.c_bnx2x_warpcore_link_reset.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	bnx2x_warpcore_link_reset, %function
bnx2x_warpcore_link_reset:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	mov	r7, r1
	mov	r4, r0
	ldr	r5, [r7]
	ldr	r3, .L14
	sub	sp, sp, #20
	mov	r2, #0
	mov	r1, r0
	mov	r0, r7
	ldr	r3, [r3]
	str	r3, [sp, #12]
	mov	r3,#0
	bl	bnx2x_sfp_e3_set_transmitter
	mov	r1, r7
	mov	r0, r5
	bl	bnx2x_set_mdio_emac_per_phy
	mov	r1, r4
	mov	r0, r7
	bl	bnx2x_set_aer_mmd
	mov	r1, r4
	mov	r2, #1
	mov	r0, r5
	bl	bnx2x_warpcore_reset_lane
	ldr	r8, .L14+4
	ldr	ip, .L14+8
	ldr	r3, .L14+12
	mov	r1, r4
	ldr	r3, [r3]
	ldr	r2, [r8]
	str	ip, [sp]
	mov	r0, r5
	bl	bnx2x_cl45_read_and_write
	ldr	ip, .L14+16
	ldr	r3, .L14+20
	mov	r1, r4
	ldr	r3, [r3]
	ldr	r2, [r8]
	str	ip, [sp]
	mov	r0, r5
	bl	bnx2x_cl45_read_and_write
	mov	ip, #0
	ldr	r3, .L14+24
	ldr	r2, .L14+28
	str	ip, [sp]
	mov	r1, r4
	ldr	r3, [r3]
	ldr	r2, [r2]
	mov	r0, r5
	bl	CL22_WR_OVER_CL45
	mvn	ip, #16
	ldr	r3, .L14+32
	str	ip, [sp]
	mov	r1, r4
	ldr	r2, [r8]
	ldr	r3, [r3]
	mov	r0, r5
	bl	bnx2x_cl45_read_and_write
	mov	ip, #65280
	ldr	r3, .L14+36
	str	ip, [sp]
	ldr	r2, [r8]
	ldr	r3, [r3]
	mov	r1, r4
	mov	r0, r5
	bl	bnx2x_cl45_read_and_write
	mov	r1, r7
	mov	r0, r4
	bl	bnx2x_get_warpcore_lane
	ldr	fp, .L14+40
	ldr	r9, .L14+44
	add	r10, sp, #8
	mov	r6, r0
	mov	r1, r4
	ldr	r2, [r8]
	ldr	r3, [fp]
	mov	r0, r5
	str	r10, [sp]
	bl	bnx2x_cl45_read
	ldr	r2, [r9]
	ldr	r1, [r4]
	mov	r0, #17
	tst	r1, r2
	movne	r2, #34
	ldr	r3, [sp, #8]
	mov	r1, r4
	orr	r3, r3, r0, lsl r6
	str	r3, [sp, #8]
	orrne	r3, r3, r2, lsl r6
	strne	r3, [sp, #8]
	ldr	r2, [r8]
	str	r3, [sp]
	mov	r0, r5
	ldr	r3, [fp]
	bl	bnx2x_cl45_write
	ldr	r3, .L14+48
	str	r10, [sp]
	mov	r1, r4
	ldr	r3, [r3]
	ldr	r2, [r8]
	mov	r0, r5
	bl	bnx2x_cl45_read
	ldr	r1, [r4]
	ldr	r2, [r9]
	ldr	r3, [sp, #8]
	ldr	ip, .L14+52
	tst	r1, r2
	lsl	r6, r6, #1
	ldr	r0, .L14+56
	ldrne	r1, .L14+60
	bic	r3, r3, ip, lsl r6
	orr	r3, r3, r0, lsl r6
	ldrne	r2, .L14+64
	str	r3, [sp, #8]
	bicne	r3, r3, r1, lsl r6
	orrne	r3, r3, r2, lsl r6
	strne	r3, [sp, #8]
	str	r3, [sp]
	ldr	r3, .L14+48
	ldr	r2, [r8]
	ldr	r3, [r3]
	mov	r1, r4
	mov	r0, r5
	bl	bnx2x_cl45_write
	mov	r1, r4
	mov	r0, r7
	bl	bnx2x_set_aer_mmd
	ldr	r3, .L14
	ldr	r2, [r3]
	ldr	r3, [sp, #12]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L13
	add	sp, sp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L13:
	bl	__stack_chk_fail
.L15:
	.align	2
.L14:
	.word	.LC0
	.word	MDIO_WC_DEVAD
	.word	49151
	.word	MDIO_WC_REG_COMBO_IEEE0_MIICTRL
	.word	65534
	.word	MDIO_WC_REG_IEEE0BLK_MIICNTL
	.word	MDIO_AER_BLOCK_AER_REG
	.word	MDIO_REG_BANK_AER_BLOCK
	.word	MDIO_WC_REG_XGXSBLK0_XGXSCONTROL
	.word	MDIO_WC_REG_XGXSBLK1_LANECTRL2
	.word	MDIO_WC_REG_XGXSBLK1_LANECTRL0
	.word	FLAGS_WC_DUAL_MODE
	.word	MDIO_WC_REG_XGXSBLK1_LANECTRL1
	.word	771
	.word	257
	.word	3084
	.word	1028
	.size	bnx2x_warpcore_link_reset, .-bnx2x_warpcore_link_reset
	.comm	MDIO_WC_REG_XGXSBLK1_LANECTRL2,4,4
	.comm	MDIO_WC_REG_XGXSBLK1_LANECTRL1,4,4
	.comm	MDIO_WC_REG_XGXSBLK1_LANECTRL0,4,4
	.comm	MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,4,4
	.comm	MDIO_WC_REG_IEEE0BLK_MIICNTL,4,4
	.comm	MDIO_WC_REG_COMBO_IEEE0_MIICTRL,4,4
	.comm	MDIO_WC_DEVAD,4,4
	.comm	MDIO_REG_BANK_AER_BLOCK,4,4
	.comm	MDIO_AER_BLOCK_AER_REG,4,4
	.comm	FLAGS_WC_DUAL_MODE,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
