	.file	"extr_mtk-sd.c_msdc_tune_response.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Final internal delay: 0x%x\n"
.LC1:
	.string	"Final cmd pad delay: %x\n"
	.text
	.p2align 4
	.type	msdc_tune_response, @function
msdc_tune_response:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	mov	r13d, esi
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 136
	.cfi_def_cfa_offset 192
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 120[rsp], rax
	xor	eax, eax
	call	mmc_priv@PLT
	mov	r15, rax
	mov	rax, QWORD PTR 16[rax]
	mov	eax, DWORD PTR [rax]
	mov	DWORD PTR 8[rsp], eax
	mov	rax, QWORD PTR 0[rbp]
	cmp	rax, QWORD PTR MMC_TIMING_MMC_HS200[rip]
	je	.L2
	cmp	rax, QWORD PTR MMC_TIMING_UHS_SDR104[rip]
	je	.L2
.L3:
	mov	esi, DWORD PTR MSDC_IOCON_RSPL[rip]
	mov	edi, DWORD PTR MSDC_IOCON[rip]
	add	edi, DWORD PTR [r15]
	call	sdr_clr_bits@PLT
	mov	r8d, DWORD PTR PAD_DELAY_MAX[rip]
	test	r8d, r8d
	jle	.L27
	mov	DWORD PTR 4[rsp], 0
	xor	r12d, r12d
	lea	r14, 28[rsp]
	.p2align 4,,10
	.p2align 3
.L8:
	mov	esi, r12d
	mov	rdi, r15
	mov	ebx, 3
	call	msdc_set_cmd_delay@PLT
	mov	eax, 1
	mov	ecx, r12d
	sal	eax, cl
	mov	DWORD PTR [rsp], eax
.L6:
	mov	rdi, rbp
	mov	rdx, r14
	mov	esi, r13d
	call	mmc_send_tuning@PLT
	mov	edi, DWORD PTR 28[rsp]
	test	edi, edi
	jne	.L5
	mov	ecx, DWORD PTR [rsp]
	or	DWORD PTR 4[rsp], ecx
	sub	ebx, 1
	jne	.L6
	add	r12d, 1
	cmp	DWORD PTR PAD_DELAY_MAX[rip], r12d
	jg	.L8
.L4:
	mov	edx, DWORD PTR 4[rsp]
	lea	rdi, 32[rsp]
	mov	rsi, r15
	call	get_best_delay@PLT
	mov	eax, DWORD PTR 32[rsp]
	mov	DWORD PTR 12[rsp], eax
	cmp	eax, 11
	jg	.L46
	cmp	QWORD PTR 40[rsp], 0
	jne	.L11
	cmp	DWORD PTR 12[rsp], 3
	jg	.L47
.L11:
	mov	esi, DWORD PTR MSDC_IOCON_RSPL[rip]
	mov	edi, DWORD PTR MSDC_IOCON[rip]
	add	edi, DWORD PTR [r15]
	call	sdr_set_bits@PLT
	mov	esi, DWORD PTR PAD_DELAY_MAX[rip]
	test	esi, esi
	jle	.L28
	mov	DWORD PTR 4[rsp], 0
	xor	r12d, r12d
	lea	r14, 28[rsp]
	.p2align 4,,10
	.p2align 3
.L16:
	mov	esi, r12d
	mov	rdi, r15
	mov	ebx, 3
	call	msdc_set_cmd_delay@PLT
	mov	eax, 1
	mov	ecx, r12d
	sal	eax, cl
	mov	DWORD PTR [rsp], eax
.L14:
	mov	rdx, r14
	mov	esi, r13d
	mov	rdi, rbp
	call	mmc_send_tuning@PLT
	mov	ecx, DWORD PTR 28[rsp]
	test	ecx, ecx
	jne	.L13
	mov	edx, DWORD PTR [rsp]
	or	DWORD PTR 4[rsp], edx
	sub	ebx, 1
	jne	.L14
	add	r12d, 1
	cmp	DWORD PTR PAD_DELAY_MAX[rip], r12d
	jg	.L16
.L12:
	mov	edx, DWORD PTR 4[rsp]
	lea	rdi, 64[rsp]
	mov	rsi, r15
	call	get_best_delay@PLT
	mov	r14d, DWORD PTR 64[rsp]
	mov	r12, QWORD PTR 72[rsp]
	mov	edi, DWORD PTR 12[rsp]
	mov	ebx, DWORD PTR 80[rsp]
	mov	esi, r14d
	call	max@PLT
	cmp	r12, 3
	jg	.L10
	cmp	r14d, 11
	jle	.L10
	mov	esi, DWORD PTR MSDC_IOCON_RSPL[rip]
	mov	edi, DWORD PTR MSDC_IOCON[rip]
	add	edi, DWORD PTR [r15]
.L19:
	call	sdr_set_bits@PLT
.L20:
	mov	esi, ebx
	mov	rdi, r15
	call	msdc_set_cmd_delay@PLT
	mov	rax, QWORD PTR 16[r15]
	cmp	QWORD PTR 8[rax], 0
	jne	.L21
	mov	eax, DWORD PTR 4[r15]
	mov	DWORD PTR [rsp], eax
	test	eax, eax
	jne	.L21
	mov	edx, DWORD PTR PAD_DELAY_MAX[rip]
	test	edx, edx
	jle	.L22
	xor	r12d, r12d
	lea	r14, 28[rsp]
	.p2align 4,,10
	.p2align 3
.L24:
	mov	esi, DWORD PTR MSDC_PAD_TUNE_CMDRRDLY[rip]
	mov	edi, DWORD PTR 8[rsp]
	mov	edx, r12d
	add	edi, DWORD PTR [r15]
	call	sdr_set_field@PLT
	mov	rdx, r14
	mov	esi, r13d
	mov	rdi, rbp
	call	mmc_send_tuning@PLT
	mov	eax, DWORD PTR 28[rsp]
	test	eax, eax
	jne	.L23
	mov	eax, 1
	mov	ecx, r12d
	sal	eax, cl
	or	DWORD PTR [rsp], eax
.L23:
	add	r12d, 1
	cmp	DWORD PTR PAD_DELAY_MAX[rip], r12d
	jg	.L24
.L22:
	mov	r14d, DWORD PTR [rsp]
	mov	edi, DWORD PTR 8[r15]
	lea	rsi, .LC0[rip]
	mov	edx, r14d
	call	dev_dbg@PLT
	lea	rdi, 96[rsp]
	mov	edx, r14d
	mov	rsi, r15
	call	get_best_delay@PLT
	mov	edx, DWORD PTR 112[rsp]
	mov	esi, DWORD PTR MSDC_PAD_TUNE_CMDRRDLY[rip]
	mov	edi, DWORD PTR 8[rsp]
	add	edi, DWORD PTR [r15]
	call	sdr_set_field@PLT
.L21:
	mov	edi, DWORD PTR 8[r15]
	mov	edx, ebx
	lea	rsi, .LC1[rip]
	call	dev_dbg@PLT
	xor	eax, eax
	cmp	ebx, 255
	jne	.L1
	mov	eax, DWORD PTR EIO[rip]
	neg	eax
.L1:
	mov	rbx, QWORD PTR 120[rsp]
	xor	rbx, QWORD PTR fs:40
	jne	.L48
	add	rsp, 136
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L5:
	.cfi_restore_state
	mov	eax, DWORD PTR [rsp]
	add	r12d, 1
	not	eax
	and	DWORD PTR 4[rsp], eax
	cmp	DWORD PTR PAD_DELAY_MAX[rip], r12d
	jg	.L8
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L46:
	xor	esi, esi
	mov	edi, eax
	xor	ebx, ebx
	call	max@PLT
.L10:
	mov	edi, DWORD PTR [r15]
	mov	esi, DWORD PTR MSDC_IOCON_RSPL[rip]
	add	edi, DWORD PTR MSDC_IOCON[rip]
	cmp	eax, DWORD PTR 12[rsp]
	jne	.L19
	call	sdr_clr_bits@PLT
	mov	ebx, DWORD PTR 48[rsp]
	jmp	.L20
	.p2align 4,,10
	.p2align 3
.L13:
	mov	eax, DWORD PTR [rsp]
	add	r12d, 1
	not	eax
	and	DWORD PTR 4[rsp], eax
	cmp	DWORD PTR PAD_DELAY_MAX[rip], r12d
	jg	.L16
	jmp	.L12
	.p2align 4,,10
	.p2align 3
.L2:
	mov	edx, DWORD PTR 4[r15]
	mov	esi, DWORD PTR MSDC_PAD_TUNE_CMDRRDLY[rip]
	mov	edi, DWORD PTR 8[rsp]
	add	edi, DWORD PTR [r15]
	call	sdr_set_field@PLT
	jmp	.L3
.L47:
	mov	edi, DWORD PTR 12[rsp]
	xor	esi, esi
	xor	ebx, ebx
	call	max@PLT
	jmp	.L10
.L28:
	mov	DWORD PTR 4[rsp], 0
	jmp	.L12
.L27:
	mov	DWORD PTR 4[rsp], 0
	jmp	.L4
.L48:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	msdc_tune_response, .-msdc_tune_response
	.comm	PAD_DELAY_MAX,4,4
	.comm	MSDC_PAD_TUNE_CMDRRDLY,4,4
	.comm	MSDC_IOCON_RSPL,4,4
	.comm	MSDC_IOCON,4,4
	.comm	MMC_TIMING_UHS_SDR104,8,8
	.comm	MMC_TIMING_MMC_HS200,8,8
	.comm	EIO,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_mtk-sd.c_msdc_tune_response.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"Final internal delay: 0x%x\012\000"
	.align	2
.LC1:
	.ascii	"Final cmd pad delay: %x\012\000"
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC2:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	msdc_tune_response, %function
msdc_tune_response:
	@ args = 0, pretend = 0, frame = 72
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r3, .L43
	sub	sp, sp, #76
	mov	r7, r1
	ldr	r3, [r3]
	str	r3, [sp, #68]
	mov	r3,#0
	mov	r6, r0
	bl	mmc_priv
	ldr	r2, .L43+4
	ldr	r3, [r6]
	ldr	r1, [r2]
	ldr	r2, [r0, #12]
	cmp	r3, r1
	ldr	r2, [r2]
	mov	r9, r0
	str	r2, [sp, #12]
	beq	.L2
	ldr	r2, .L43+8
	ldr	r2, [r2]
	cmp	r3, r2
	beq	.L2
.L3:
	ldr	r3, .L43+12
	ldr	r0, [r9]
	ldr	r3, [r3]
	ldr	fp, .L43+16
	add	r0, r0, r3
	ldr	r3, .L43+20
	ldr	r1, [r3]
	bl	sdr_clr_bits
	ldr	r3, [fp]
	cmp	r3, #0
	ble	.L26
	mov	r5, #0
	mov	r4, r5
	add	r8, sp, #16
	str	r9, [sp, #4]
.L8:
	mov	r1, r5
	ldr	r0, [sp, #4]
	bl	msdc_set_cmd_delay
	mov	r3, #1
	mov	r9, #3
	lsl	r10, r3, r5
.L6:
	mov	r2, r8
	mov	r1, r7
	mov	r0, r6
	bl	mmc_send_tuning
	ldr	r3, [sp, #16]
	cmp	r3, #0
	bne	.L5
	subs	r9, r9, #1
	orr	r4, r4, r10
	bne	.L6
	ldr	r3, [fp]
	add	r5, r5, #1
	cmp	r3, r5
	bgt	.L8
.L41:
	ldr	r9, [sp, #4]
.L4:
	mov	r2, r4
	mov	r1, r9
	add	r0, sp, #20
	bl	get_best_delay
	ldr	r3, [sp, #20]
	cmp	r3, #11
	str	r3, [sp, #8]
	bgt	.L37
	ldr	r3, [sp, #8]
	ldr	r4, [sp, #24]
	cmp	r3, #3
	movle	r5, #0
	movgt	r5, #1
	cmp	r4, #0
	movne	r5, #0
	cmp	r5, #0
	bne	.L37
	ldr	r3, .L43+12
	ldr	r0, [r9]
	ldr	r3, [r3]
	ldr	r2, .L43+20
	add	r0, r0, r3
	ldr	r1, [r2]
	bl	sdr_set_bits
	ldr	r3, [fp]
	mov	r4, r5
	cmp	r3, #0
	ble	.L12
	add	r8, sp, #16
	str	r9, [sp, #4]
.L16:
	mov	r1, r5
	ldr	r0, [sp, #4]
	bl	msdc_set_cmd_delay
	mov	r3, #1
	mov	r9, #3
	lsl	r10, r3, r5
.L14:
	mov	r2, r8
	mov	r1, r7
	mov	r0, r6
	bl	mmc_send_tuning
	ldr	r3, [sp, #16]
	cmp	r3, #0
	bne	.L13
	subs	r9, r9, #1
	orr	r4, r4, r10
	bne	.L14
	ldr	r3, [fp]
	add	r5, r5, #1
	cmp	r3, r5
	bgt	.L16
.L42:
	ldr	r9, [sp, #4]
.L12:
	mov	r2, r4
	mov	r1, r9
	add	r0, sp, #36
	bl	get_best_delay
	ldr	r5, [sp, #36]
	ldr	r4, [sp, #40]
	mov	r1, r5
	ldr	r0, [sp, #8]
	ldr	r10, [sp, #44]
	bl	max
	cmp	r4, #3
	movle	r4, #1
	movgt	r4, #0
	cmp	r5, #11
	movle	r4, #0
	cmp	r4, #0
	bne	.L17
.L10:
	ldr	r1, [sp, #8]
	ldr	r3, .L43+12
	cmp	r0, r1
	ldr	r3, [r3]
	ldr	r2, [r9]
	ldr	r1, .L43+20
	add	r0, r3, r2
	ldr	r1, [r1]
	beq	.L39
.L18:
	bl	sdr_set_bits
.L19:
	mov	r1, r10
	mov	r0, r9
	bl	msdc_set_cmd_delay
	ldr	r3, [r9, #12]
	ldr	r3, [r3, #4]
	cmp	r3, #0
	bne	.L20
	ldr	r4, [r9, #4]
	cmp	r4, #0
	bne	.L20
	ldr	r3, [fp]
	cmp	r3, #0
	ldrle	r3, .L43+24
	strle	r3, [sp, #4]
	ble	.L21
	ldr	r3, .L43+24
	add	r8, sp, #16
	str	r3, [sp, #4]
	mov	r3, r8
	mov	r5, r4
	mov	r8, r9
	mov	r9, r3
	str	r10, [sp, #8]
	ldr	r10, [sp, #12]
.L23:
	ldr	r3, [sp, #4]
	ldr	r0, [r8]
	ldr	r1, [r3]
	mov	r2, r5
	add	r0, r10, r0
	bl	sdr_set_field
	mov	r2, r9
	mov	r1, r7
	mov	r0, r6
	bl	mmc_send_tuning
	ldr	r2, [sp, #16]
	cmp	r2, #0
	moveq	r3, #1
	ldr	r2, [fp]
	orreq	r4, r4, r3, lsl r5
	add	r5, r5, #1
	cmp	r2, r5
	bgt	.L23
	mov	r9, r8
	ldr	r10, [sp, #8]
.L21:
	mov	r2, r4
	ldr	r1, .L43+28
	ldr	r0, [r9, #8]
	bl	dev_dbg
	mov	r2, r4
	mov	r1, r9
	add	r0, sp, #52
	bl	get_best_delay
	ldr	r3, [sp, #4]
	ldr	r0, [r9]
	ldr	r1, [r3]
	ldr	r3, [sp, #12]
	ldr	r2, [sp, #60]
	add	r0, r3, r0
	bl	sdr_set_field
.L20:
	mov	r2, r10
	ldr	r0, [r9, #8]
	ldr	r1, .L43+32
	bl	dev_dbg
	cmp	r10, #255
	ldreq	r3, .L43+36
	movne	r0, #0
	ldreq	r0, [r3]
	ldr	r3, .L43
	rsbeq	r0, r0, #0
	ldr	r2, [r3]
	ldr	r3, [sp, #68]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L40
	add	sp, sp, #76
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L5:
	ldr	r3, [fp]
	add	r5, r5, #1
	cmp	r3, r5
	bic	r4, r4, r10
	bgt	.L8
	b	.L41
.L39:
	bl	sdr_clr_bits
	ldr	r10, [sp, #28]
	b	.L19
.L17:
	ldr	r3, .L43+12
	ldr	r2, .L43+20
	ldr	r0, [r3]
	ldr	r3, [r9]
	ldr	r1, [r2]
	add	r0, r0, r3
	b	.L18
.L13:
	ldr	r3, [fp]
	add	r5, r5, #1
	cmp	r3, r5
	bic	r4, r4, r10
	bgt	.L16
	b	.L42
.L37:
	mov	r1, #0
	mov	r0, r3
	bl	max
	mov	r10, #0
	b	.L10
.L2:
	ldr	r3, .L43+24
	ldr	r0, [r9]
	ldr	r1, [r3]
	ldr	r3, [sp, #12]
	ldr	r2, [r9, #4]
	add	r0, r3, r0
	bl	sdr_set_field
	b	.L3
.L26:
	mov	r4, #0
	b	.L4
.L40:
	bl	__stack_chk_fail
.L44:
	.align	2
.L43:
	.word	.LC2
	.word	MMC_TIMING_MMC_HS200
	.word	MMC_TIMING_UHS_SDR104
	.word	MSDC_IOCON
	.word	PAD_DELAY_MAX
	.word	MSDC_IOCON_RSPL
	.word	MSDC_PAD_TUNE_CMDRRDLY
	.word	.LC0
	.word	.LC1
	.word	EIO
	.size	msdc_tune_response, .-msdc_tune_response
	.comm	PAD_DELAY_MAX,4,4
	.comm	MSDC_PAD_TUNE_CMDRRDLY,4,4
	.comm	MSDC_IOCON_RSPL,4,4
	.comm	MSDC_IOCON,4,4
	.comm	MMC_TIMING_UHS_SDR104,4,4
	.comm	MMC_TIMING_MMC_HS200,4,4
	.comm	EIO,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
