	.file	"extr_pcm512x.c_pcm512x_hw_params.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"hw_params %u Hz, %u channels\n"
.LC1:
	.string	"Bad frame size: %d\n"
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC2:
	.string	"Failed to enable slave mode: %d\n"
	.align 8
.LC3:
	.string	"Failed to enable clock divider autoset: %d\n"
	.section	.rodata.str1.1
.LC4:
	.string	"Failed to set frame size: %d\n"
.LC5:
	.string	"Failed to set FLEX_A: %d\n"
.LC6:
	.string	"Failed to set FLEX_B: %d\n"
	.section	.rodata.str1.8
	.align 8
.LC7:
	.string	"Failed to ignore auto-clock failures: %d\n"
	.section	.rodata.str1.1
.LC8:
	.string	"Failed to disable pll: %d\n"
	.section	.rodata.str1.8
	.align 8
.LC9:
	.string	"Failed to set gpio as pllref: %d\n"
	.align 8
.LC10:
	.string	"Failed to set gpio %d as pllin: %d\n"
	.section	.rodata.str1.1
.LC11:
	.string	"Failed to enable pll: %d\n"
	.section	.rodata.str1.8
	.align 8
.LC12:
	.string	"Failed to enable clock output: %d\n"
	.align 8
.LC13:
	.string	"Failed to enable master mode: %d\n"
	.section	.rodata.str1.1
.LC14:
	.string	"Failed to enable gpio %d: %d\n"
	.section	.rodata.str1.8
	.align 8
.LC15:
	.string	"Failed to output pll on %d: %d\n"
	.section	.rodata.str1.1
.LC16:
	.string	"Failed to halt clocks: %d\n"
.LC17:
	.string	"Failed to resume clocks: %d\n"
	.text
	.p2align 4
	.type	pcm512x_hw_params, @function
pcm512x_hw_params:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	mov	r13, rdx
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rsi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 24
	.cfi_def_cfa_offset 80
	mov	rbx, QWORD PTR [rdx]
	mov	rdi, rbx
	call	snd_soc_component_get_drvdata@PLT
	mov	rdi, rbp
	mov	r15, rax
	call	params_channels@PLT
	mov	rdi, rbp
	mov	r12d, eax
	call	params_rate@PLT
	mov	edi, DWORD PTR [rbx]
	mov	ecx, r12d
	lea	rsi, .LC0[rip]
	mov	edx, eax
	call	dev_dbg@PLT
	mov	rdi, rbp
	call	params_width@PLT
	cmp	eax, 24
	je	.L2
	jg	.L3
	cmp	eax, 16
	je	.L4
	cmp	eax, 20
	jne	.L6
	mov	ecx, DWORD PTR PCM512x_ALEN_20[rip]
	.p2align 4,,10
	.p2align 3
.L8:
	mov	eax, DWORD PTR [r15]
	and	eax, DWORD PTR SND_SOC_DAIFMT_MASTER_MASK[rip]
	cmp	eax, 129
	je	.L10
	cmp	eax, 130
	je	.L11
	mov	r12d, DWORD PTR EINVAL[rip]
	neg	r12d
	cmp	eax, 128
	je	.L50
.L1:
	add	rsp, 24
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	eax, r12d
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L3:
	.cfi_restore_state
	mov	ecx, DWORD PTR PCM512x_ALEN_32[rip]
	cmp	eax, 32
	je	.L8
.L6:
	mov	rdi, rbp
	call	params_width@PLT
	mov	edi, DWORD PTR [rbx]
	lea	rsi, .LC1[rip]
	mov	edx, eax
	xor	eax, eax
	call	dev_err@PLT
	mov	r12d, DWORD PTR EINVAL[rip]
	neg	r12d
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L50:
	mov	edi, DWORD PTR 12[r15]
	mov	esi, DWORD PTR PCM512x_BCLK_LRCLK_CFG[rip]
	xor	ecx, ecx
	mov	edx, DWORD PTR PCM512x_BCKP[rip]
	or	edx, DWORD PTR PCM512x_BCKO[rip]
	or	edx, DWORD PTR PCM512x_LRKO[rip]
	call	regmap_update_bits@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L51
	mov	edi, DWORD PTR 12[r15]
	mov	edx, DWORD PTR PCM512x_DCAS[rip]
	xor	ecx, ecx
	mov	esi, DWORD PTR PCM512x_ERROR_DETECT[rip]
	call	regmap_update_bits@PLT
	mov	r12d, eax
	test	eax, eax
	je	.L1
	mov	edi, DWORD PTR [rbx]
	mov	edx, eax
	lea	rsi, .LC3[rip]
	xor	eax, eax
	call	dev_err@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L11:
	mov	eax, DWORD PTR PCM512x_RLRK[rip]
	or	eax, DWORD PTR PCM512x_RBCK[rip]
	mov	DWORD PTR 12[rsp], eax
	mov	r14d, DWORD PTR PCM512x_BCKO[rip]
	or	r14d, DWORD PTR PCM512x_LRKO[rip]
.L14:
	mov	edi, DWORD PTR 12[r15]
	mov	edx, DWORD PTR PCM512x_ALEN[rip]
	mov	esi, DWORD PTR PCM512x_I2S_1[rip]
	call	regmap_update_bits@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L52
	mov	edx, DWORD PTR 4[r15]
	mov	edi, DWORD PTR 12[r15]
	test	edx, edx
	jne	.L53
	mov	eax, DWORD PTR PCM512x_IDCH[rip]
	mov	edx, DWORD PTR PCM512x_IDFS[rip]
	or	edx, DWORD PTR PCM512x_IDBK[rip]
	or	edx, DWORD PTR PCM512x_IDSK[rip]
	or	eax, edx
	mov	edx, DWORD PTR PCM512x_DCAS[rip]
	or	edx, DWORD PTR PCM512x_IPLK[rip]
	mov	ecx, eax
	mov	esi, DWORD PTR PCM512x_ERROR_DETECT[rip]
	or	ecx, edx
	or	edx, DWORD PTR PCM512x_IDCM[rip]
	or	edx, eax
	call	regmap_update_bits@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L48
	mov	edi, DWORD PTR 12[r15]
	mov	edx, DWORD PTR PCM512x_PLLE[rip]
	xor	ecx, ecx
	mov	esi, DWORD PTR PCM512x_PLL_EN[rip]
	call	regmap_update_bits@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L54
.L19:
	mov	rsi, rbp
	mov	rdi, r13
	call	pcm512x_set_dividers@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L1
	mov	eax, DWORD PTR 4[r15]
	mov	edi, DWORD PTR 12[r15]
	test	eax, eax
	je	.L21
	mov	ecx, DWORD PTR PCM512x_SREF_GPIO[rip]
	mov	edx, DWORD PTR PCM512x_SREF[rip]
	mov	esi, DWORD PTR PCM512x_PLL_REF[rip]
	call	regmap_update_bits@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L55
	mov	ecx, DWORD PTR PCM512x_GREF_GPIO1[rip]
	mov	edi, DWORD PTR 12[r15]
	add	ecx, DWORD PTR 8[r15]
	mov	edx, DWORD PTR PCM512x_GREF[rip]
	mov	esi, DWORD PTR PCM512x_GPIO_PLLIN[rip]
	sub	ecx, 1
	call	regmap_update_bits@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L56
	mov	edx, DWORD PTR PCM512x_PLLE[rip]
	mov	edi, DWORD PTR 12[r15]
	mov	esi, DWORD PTR PCM512x_PLL_EN[rip]
	mov	ecx, edx
	call	regmap_update_bits@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L24
	mov	edi, DWORD PTR 12[r15]
.L21:
	mov	esi, DWORD PTR PCM512x_BCLK_LRCLK_CFG[rip]
	mov	edx, DWORD PTR PCM512x_BCKP[rip]
	mov	ecx, r14d
	or	edx, DWORD PTR PCM512x_BCKO[rip]
	or	edx, DWORD PTR PCM512x_LRKO[rip]
	call	regmap_update_bits@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L57
	mov	edi, DWORD PTR 12[r15]
	mov	ecx, DWORD PTR 12[rsp]
	mov	esi, DWORD PTR PCM512x_MASTER_MODE[rip]
	mov	edx, DWORD PTR PCM512x_RLRK[rip]
	or	edx, DWORD PTR PCM512x_RBCK[rip]
	call	regmap_update_bits@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L58
	mov	ecx, DWORD PTR 4[r15]
	mov	edi, DWORD PTR 12[r15]
	test	ecx, ecx
	je	.L27
	mov	edx, DWORD PTR PCM512x_G1OE[rip]
	sub	ecx, 1
	mov	esi, DWORD PTR PCM512x_GPIO_EN[rip]
	sal	edx, cl
	mov	ecx, edx
	call	regmap_update_bits@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L59
	mov	esi, DWORD PTR PCM512x_GPIO_OUTPUT_1[rip]
	mov	edi, DWORD PTR 12[r15]
	add	esi, DWORD PTR 4[r15]
	mov	ecx, DWORD PTR PCM512x_GxSL_PLLCK[rip]
	mov	edx, DWORD PTR PCM512x_GxSL[rip]
	sub	esi, 1
	call	regmap_update_bits@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L29
	mov	edi, DWORD PTR 12[r15]
.L27:
	mov	ecx, DWORD PTR PCM512x_RQSY_HALT[rip]
	mov	edx, DWORD PTR PCM512x_RQSY[rip]
	mov	esi, DWORD PTR PCM512x_SYNCHRONIZE[rip]
	call	regmap_update_bits@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L60
	mov	edi, DWORD PTR 12[r15]
	mov	ecx, DWORD PTR PCM512x_RQSY_RESUME[rip]
	mov	edx, DWORD PTR PCM512x_RQSY[rip]
	mov	esi, DWORD PTR PCM512x_SYNCHRONIZE[rip]
	call	regmap_update_bits@PLT
	mov	r12d, eax
	test	eax, eax
	je	.L1
	mov	edi, DWORD PTR [rbx]
	mov	edx, eax
	lea	rsi, .LC17[rip]
	xor	eax, eax
	call	dev_err@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L10:
	mov	eax, DWORD PTR PCM512x_RBCK[rip]
	mov	r14d, DWORD PTR PCM512x_BCKO[rip]
	mov	DWORD PTR 12[rsp], eax
	jmp	.L14
	.p2align 4,,10
	.p2align 3
.L53:
	mov	esi, DWORD PTR PCM512x_FLEX_A[rip]
	mov	edx, 17
	call	regmap_write@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L61
	mov	edi, DWORD PTR 12[r15]
	mov	esi, DWORD PTR PCM512x_FLEX_B[rip]
	mov	edx, 255
	call	regmap_write@PLT
	mov	r12d, eax
	test	eax, eax
	jne	.L62
	mov	ecx, DWORD PTR PCM512x_IDCH[rip]
	mov	edx, DWORD PTR PCM512x_IDFS[rip]
	or	edx, DWORD PTR PCM512x_IDBK[rip]
	or	edx, DWORD PTR PCM512x_IDSK[rip]
	or	ecx, edx
	mov	eax, DWORD PTR PCM512x_DCAS[rip]
	mov	edi, DWORD PTR 12[r15]
	mov	edx, DWORD PTR PCM512x_IPLK[rip]
	mov	r9d, ecx
	mov	esi, DWORD PTR PCM512x_ERROR_DETECT[rip]
	or	r9d, eax
	or	eax, DWORD PTR PCM512x_IDCM[rip]
	or	edx, eax
	or	edx, ecx
	mov	ecx, r9d
	call	regmap_update_bits@PLT
	mov	r12d, eax
	test	eax, eax
	je	.L19
.L48:
	mov	edi, DWORD PTR [rbx]
	mov	edx, r12d
	lea	rsi, .LC7[rip]
	xor	eax, eax
	call	dev_err@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L51:
	mov	edi, DWORD PTR [rbx]
	mov	edx, eax
	lea	rsi, .LC2[rip]
	xor	eax, eax
	call	dev_err@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L2:
	mov	ecx, DWORD PTR PCM512x_ALEN_24[rip]
	jmp	.L8
	.p2align 4,,10
	.p2align 3
.L4:
	mov	ecx, DWORD PTR PCM512x_ALEN_16[rip]
	jmp	.L8
	.p2align 4,,10
	.p2align 3
.L52:
	mov	edi, DWORD PTR [rbx]
	mov	edx, eax
	lea	rsi, .LC4[rip]
	xor	eax, eax
	call	dev_err@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L61:
	mov	edi, DWORD PTR [rbx]
	mov	edx, eax
	lea	rsi, .LC5[rip]
	xor	eax, eax
	call	dev_err@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L57:
	mov	edi, DWORD PTR [rbx]
	mov	edx, eax
	lea	rsi, .LC12[rip]
	xor	eax, eax
	call	dev_err@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L62:
	mov	edi, DWORD PTR [rbx]
	mov	edx, eax
	lea	rsi, .LC6[rip]
	xor	eax, eax
	call	dev_err@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L54:
	mov	edi, DWORD PTR [rbx]
	mov	edx, eax
	lea	rsi, .LC8[rip]
	xor	eax, eax
	call	dev_err@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L55:
	mov	edi, DWORD PTR [rbx]
	mov	edx, eax
	lea	rsi, .LC9[rip]
	xor	eax, eax
	call	dev_err@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L56:
	mov	edx, DWORD PTR 8[r15]
	mov	edi, DWORD PTR [rbx]
	mov	ecx, eax
	lea	rsi, .LC10[rip]
	xor	eax, eax
	call	dev_err@PLT
	jmp	.L1
.L60:
	mov	edi, DWORD PTR [rbx]
	mov	edx, eax
	lea	rsi, .LC16[rip]
	xor	eax, eax
	call	dev_err@PLT
	jmp	.L1
.L58:
	mov	edi, DWORD PTR [rbx]
	mov	edx, eax
	lea	rsi, .LC13[rip]
	xor	eax, eax
	call	dev_err@PLT
	jmp	.L1
.L59:
	mov	edx, DWORD PTR 4[r15]
	mov	edi, DWORD PTR [rbx]
	mov	ecx, eax
	lea	rsi, .LC14[rip]
	xor	eax, eax
	call	dev_err@PLT
	jmp	.L1
.L24:
	mov	edi, DWORD PTR [rbx]
	mov	edx, eax
	lea	rsi, .LC11[rip]
	xor	eax, eax
	call	dev_err@PLT
	jmp	.L1
.L29:
	mov	ecx, DWORD PTR 4[r15]
	mov	edi, DWORD PTR [rbx]
	mov	edx, eax
	lea	rsi, .LC15[rip]
	xor	eax, eax
	call	dev_err@PLT
	jmp	.L1
	.cfi_endproc
.LFE0:
	.size	pcm512x_hw_params, .-pcm512x_hw_params
	.comm	SND_SOC_DAIFMT_MASTER_MASK,4,4
	.comm	PCM512x_SYNCHRONIZE,4,4
	.comm	PCM512x_SREF_GPIO,4,4
	.comm	PCM512x_SREF,4,4
	.comm	PCM512x_RQSY_RESUME,4,4
	.comm	PCM512x_RQSY_HALT,4,4
	.comm	PCM512x_RQSY,4,4
	.comm	PCM512x_RLRK,4,4
	.comm	PCM512x_RBCK,4,4
	.comm	PCM512x_PLL_REF,4,4
	.comm	PCM512x_PLL_EN,4,4
	.comm	PCM512x_PLLE,4,4
	.comm	PCM512x_MASTER_MODE,4,4
	.comm	PCM512x_LRKO,4,4
	.comm	PCM512x_IPLK,4,4
	.comm	PCM512x_IDSK,4,4
	.comm	PCM512x_IDFS,4,4
	.comm	PCM512x_IDCM,4,4
	.comm	PCM512x_IDCH,4,4
	.comm	PCM512x_IDBK,4,4
	.comm	PCM512x_I2S_1,4,4
	.comm	PCM512x_GxSL_PLLCK,4,4
	.comm	PCM512x_GxSL,4,4
	.comm	PCM512x_GREF_GPIO1,4,4
	.comm	PCM512x_GREF,4,4
	.comm	PCM512x_GPIO_PLLIN,4,4
	.comm	PCM512x_GPIO_OUTPUT_1,4,4
	.comm	PCM512x_GPIO_EN,4,4
	.comm	PCM512x_G1OE,4,4
	.comm	PCM512x_FLEX_B,4,4
	.comm	PCM512x_FLEX_A,4,4
	.comm	PCM512x_ERROR_DETECT,4,4
	.comm	PCM512x_DCAS,4,4
	.comm	PCM512x_BCLK_LRCLK_CFG,4,4
	.comm	PCM512x_BCKP,4,4
	.comm	PCM512x_BCKO,4,4
	.comm	PCM512x_ALEN_32,4,4
	.comm	PCM512x_ALEN_24,4,4
	.comm	PCM512x_ALEN_20,4,4
	.comm	PCM512x_ALEN_16,4,4
	.comm	PCM512x_ALEN,4,4
	.comm	EINVAL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_pcm512x.c_pcm512x_hw_params.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"hw_params %u Hz, %u channels\012\000"
	.align	2
.LC1:
	.ascii	"Bad frame size: %d\012\000"
	.align	2
.LC2:
	.ascii	"Failed to enable slave mode: %d\012\000"
	.align	2
.LC3:
	.ascii	"Failed to enable clock divider autoset: %d\012\000"
	.align	2
.LC4:
	.ascii	"Failed to set frame size: %d\012\000"
	.align	2
.LC5:
	.ascii	"Failed to set FLEX_A: %d\012\000"
	.align	2
.LC6:
	.ascii	"Failed to set FLEX_B: %d\012\000"
	.align	2
.LC7:
	.ascii	"Failed to ignore auto-clock failures: %d\012\000"
	.align	2
.LC8:
	.ascii	"Failed to disable pll: %d\012\000"
	.align	2
.LC9:
	.ascii	"Failed to set gpio as pllref: %d\012\000"
	.align	2
.LC10:
	.ascii	"Failed to set gpio %d as pllin: %d\012\000"
	.align	2
.LC11:
	.ascii	"Failed to enable pll: %d\012\000"
	.align	2
.LC12:
	.ascii	"Failed to enable clock output: %d\012\000"
	.align	2
.LC13:
	.ascii	"Failed to enable master mode: %d\012\000"
	.align	2
.LC14:
	.ascii	"Failed to enable gpio %d: %d\012\000"
	.align	2
.LC15:
	.ascii	"Failed to output pll on %d: %d\012\000"
	.align	2
.LC16:
	.ascii	"Failed to halt clocks: %d\012\000"
	.align	2
.LC17:
	.ascii	"Failed to resume clocks: %d\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	pcm512x_hw_params, %function
pcm512x_hw_params:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r8, [r2]
	sub	sp, sp, #12
	mov	r0, r8
	mov	r5, r1
	mov	r7, r2
	bl	snd_soc_component_get_drvdata
	mov	r6, r0
	mov	r0, r5
	ldr	r9, [r8]
	bl	params_rate
	mov	r4, r0
	mov	r0, r5
	bl	params_channels
	mov	r2, r4
	mov	r3, r0
	ldr	r1, .L63
	mov	r0, r9
	bl	dev_dbg
	mov	r0, r5
	bl	params_width
	sub	r0, r0, #16
	cmp	r0, #16
	ldrls	pc, [pc, r0, asl #2]
	b	.L2
.L4:
	.word	.L7
	.word	.L2
	.word	.L2
	.word	.L2
	.word	.L6
	.word	.L2
	.word	.L2
	.word	.L2
	.word	.L5
	.word	.L2
	.word	.L2
	.word	.L2
	.word	.L2
	.word	.L2
	.word	.L2
	.word	.L2
	.word	.L3
.L2:
	mov	r0, r5
	ldr	r4, [r8]
	bl	params_width
	ldr	r1, .L63+4
	mov	r2, r0
	mov	r0, r4
	bl	dev_err
	ldr	r3, .L63+8
	ldr	r0, [r3]
	rsb	r4, r0, #0
.L1:
	mov	r0, r4
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L7:
	ldr	r3, .L63+12
	ldr	r3, [r3]
.L8:
	ldr	r1, .L63+16
	ldr	r2, [r6]
	ldr	r1, [r1]
	and	r2, r2, r1
	cmp	r2, #129
	beq	.L10
	cmp	r2, #130
	beq	.L11
	cmp	r2, #128
	beq	.L52
	ldr	r3, .L63+8
	ldr	r0, [r3]
	rsb	r4, r0, #0
	mov	r0, r4
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L6:
	ldr	r3, .L63+20
	ldr	r3, [r3]
	b	.L8
.L5:
	ldr	r3, .L63+24
	ldr	r3, [r3]
	b	.L8
.L3:
	ldr	r3, .L63+28
	ldr	r3, [r3]
	b	.L8
.L52:
	ldr	r1, .L63+32
	ldr	r3, .L63+36
	ldr	r2, .L63+40
	ldr	r0, [r1]
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	r1, .L63+44
	orr	r3, r3, r0
	orr	r2, r3, r2
	ldr	r1, [r1]
	mov	r3, #0
	ldr	r0, [r6, #12]
	bl	regmap_update_bits
	subs	r4, r0, #0
	bne	.L53
	ldr	r2, .L63+48
	ldr	r1, .L63+52
	mov	r3, r4
	ldr	r0, [r6, #12]
	ldr	r2, [r2]
	ldr	r1, [r1]
	bl	regmap_update_bits
	subs	r4, r0, #0
	beq	.L1
	mov	r2, r4
	ldr	r0, [r8]
	ldr	r1, .L63+56
	bl	dev_err
	b	.L1
.L11:
	ldr	r1, .L63+40
	ldr	r2, .L63+60
	ldr	fp, .L63+64
	ldr	r10, .L63+32
	ldr	r0, [r1]
	ldr	r1, [r2]
	ldr	r2, [fp]
	ldr	r9, [r10]
	orr	r2, r1, r2
	orr	r9, r9, r0
	str	r2, [sp]
.L14:
	ldr	r2, .L63+68
	ldr	r1, .L63+72
	ldr	r2, [r2]
	ldr	r1, [r1]
	ldr	r0, [r6, #12]
	bl	regmap_update_bits
	subs	r4, r0, #0
	bne	.L54
	ldr	r3, [r6, #4]
	ldr	r0, [r6, #12]
	cmp	r3, #0
	beq	.L16
	ldr	r3, .L63+76
	mov	r2, #17
	ldr	r1, [r3]
	bl	regmap_write
	subs	r4, r0, #0
	bne	.L55
	ldr	r3, .L63+80
	mov	r2, #255
	ldr	r1, [r3]
	ldr	r0, [r6, #12]
	bl	regmap_write
	subs	r4, r0, #0
	bne	.L56
	ldr	r0, .L63+84
	ldr	r1, .L63+88
	ldr	r0, [r0]
	ldr	r1, [r1]
	ldr	ip, .L63+92
	orr	r1, r0, r1
	ldr	r3, .L63+48
	ldr	r2, .L63+96
	ldr	r0, .L63+100
	ldr	lr, [ip]
	ldr	ip, .L63+104
	ldr	r3, [r3]
	ldr	r0, [r0]
	ldr	r2, [r2]
	ldr	ip, [ip]
	orr	r1, r1, lr
	orr	r1, r1, r0
	orr	r2, r3, r2
	ldr	r0, .L63+52
	orr	r2, r2, ip
	orr	r3, r1, r3
	orr	r2, r2, r1
	ldr	r1, [r0]
	ldr	r0, [r6, #12]
	bl	regmap_update_bits
	subs	r4, r0, #0
	bne	.L50
.L19:
	mov	r1, r5
	mov	r0, r7
	bl	pcm512x_set_dividers
	subs	r4, r0, #0
	bne	.L1
	ldr	r3, [r6, #4]
	ldr	r0, [r6, #12]
	cmp	r3, #0
	beq	.L21
	ldr	r3, .L63+108
	ldr	r2, .L63+112
	ldr	r1, .L63+116
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	r1, [r1]
	bl	regmap_update_bits
	subs	r4, r0, #0
	bne	.L57
	ldr	r2, .L63+120
	ldr	r3, [r6, #8]
	ldr	r0, [r2]
	ldr	r1, .L63+124
	ldr	r2, .L63+128
	add	r3, r3, r0
	ldr	r2, [r2]
	ldr	r1, [r1]
	ldr	r0, [r6, #12]
	sub	r3, r3, #1
	bl	regmap_update_bits
	subs	r4, r0, #0
	bne	.L58
	ldr	r3, .L63+132
	ldr	r2, .L63+136
	ldr	r3, [r3]
	ldr	r1, [r2]
	ldr	r0, [r6, #12]
	mov	r2, r3
	bl	regmap_update_bits
	subs	r4, r0, #0
	bne	.L24
	ldr	r0, [r6, #12]
.L21:
	ldr	r3, .L63+36
	ldr	r1, .L63+40
	ldr	r3, [r3]
	ldr	r2, [r10]
	ldr	ip, [r1]
	ldr	r1, .L63+44
	orr	r2, r3, r2
	ldr	r1, [r1]
	mov	r3, r9
	orr	r2, r2, ip
	bl	regmap_update_bits
	subs	r4, r0, #0
	bne	.L59
	ldr	r3, .L63+60
	ldr	r2, [fp]
	ldr	r0, [r3]
	ldr	r1, .L63+140
	orr	r2, r0, r2
	ldr	r3, [sp]
	ldr	r1, [r1]
	ldr	r0, [r6, #12]
	bl	regmap_update_bits
	subs	r4, r0, #0
	bne	.L60
	ldr	r3, [r6, #4]
	ldr	r0, [r6, #12]
	cmp	r3, #0
	beq	.L27
	ldr	r2, .L63+144
	ldr	r1, .L63+148
	ldr	r2, [r2]
	sub	r3, r3, #1
	lsl	r3, r2, r3
	mov	r2, r3
	ldr	r1, [r1]
	bl	regmap_update_bits
	subs	r4, r0, #0
	bne	.L61
	ldr	r3, .L63+152
	ldr	r1, [r6, #4]
	ldr	r0, [r3]
	ldr	r2, .L63+156
	ldr	r3, .L63+160
	add	r1, r1, r0
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	r0, [r6, #12]
	sub	r1, r1, #1
	bl	regmap_update_bits
	subs	r4, r0, #0
	bne	.L29
	ldr	r0, [r6, #12]
.L27:
	ldr	r3, .L63+164
	ldr	r7, .L63+168
	ldr	r5, .L63+172
	ldr	r3, [r3]
	ldr	r2, [r7]
	ldr	r1, [r5]
	bl	regmap_update_bits
	subs	r4, r0, #0
	bne	.L62
	ldr	r3, .L63+176
	ldr	r2, [r7]
	ldr	r1, [r5]
	ldr	r0, [r6, #12]
	ldr	r3, [r3]
	bl	regmap_update_bits
	subs	r4, r0, #0
	beq	.L1
	mov	r2, r4
	ldr	r0, [r8]
	ldr	r1, .L63+180
	bl	dev_err
	b	.L1
.L10:
	ldr	fp, .L63+64
	ldr	r10, .L63+32
	ldr	r2, [fp]
	ldr	r9, [r10]
	str	r2, [sp]
	b	.L14
.L16:
	ldr	ip, .L63+84
	ldr	r1, .L63+88
	ldr	r4, .L63+92
	ldr	ip, [ip]
	ldr	r1, [r1]
	ldr	r4, [r4]
	ldr	lr, .L63+100
	orr	r1, ip, r1
	ldr	r3, .L63+48
	ldr	ip, .L63+104
	ldr	r2, .L63+96
	str	r4, [sp, #4]
	ldr	r3, [r3]
	ldr	r4, [lr]
	ldr	r2, [r2]
	ldr	lr, [ip]
	ldr	ip, [sp, #4]
	orr	r2, r3, r2
	orr	r1, r1, ip
	ldr	ip, .L63+52
	orr	r1, r1, r4
	orr	r3, r3, lr
	orr	r2, r2, lr
	orr	r3, r3, r1
	orr	r2, r2, r1
	ldr	r1, [ip]
	bl	regmap_update_bits
	subs	r4, r0, #0
	bne	.L50
	ldr	r2, .L63+132
	ldr	r1, .L63+136
	mov	r3, r4
	ldr	r2, [r2]
	ldr	r1, [r1]
	ldr	r0, [r6, #12]
	bl	regmap_update_bits
	subs	r4, r0, #0
	beq	.L19
	mov	r2, r4
	ldr	r0, [r8]
	ldr	r1, .L63+184
	bl	dev_err
	b	.L1
.L54:
	mov	r2, r4
	ldr	r0, [r8]
	ldr	r1, .L63+188
	bl	dev_err
	b	.L1
.L50:
	mov	r2, r4
	ldr	r0, [r8]
	ldr	r1, .L63+192
	bl	dev_err
	b	.L1
.L53:
	mov	r2, r4
	ldr	r0, [r8]
	ldr	r1, .L63+196
	bl	dev_err
	b	.L1
.L55:
	mov	r2, r4
	ldr	r0, [r8]
	ldr	r1, .L63+200
	bl	dev_err
	b	.L1
.L59:
	mov	r2, r4
	ldr	r0, [r8]
	ldr	r1, .L63+204
	bl	dev_err
	b	.L1
.L56:
	mov	r2, r4
	ldr	r0, [r8]
	ldr	r1, .L63+208
	bl	dev_err
	b	.L1
.L57:
	mov	r2, r4
	ldr	r0, [r8]
	ldr	r1, .L63+212
	bl	dev_err
	b	.L1
.L58:
	mov	r3, r4
	ldr	r2, [r6, #8]
	ldr	r0, [r8]
	ldr	r1, .L63+216
	bl	dev_err
	b	.L1
.L62:
	mov	r2, r4
	ldr	r0, [r8]
	ldr	r1, .L63+220
	bl	dev_err
	b	.L1
.L60:
	mov	r2, r4
	ldr	r0, [r8]
	ldr	r1, .L63+224
	bl	dev_err
	b	.L1
.L61:
	mov	r3, r4
	ldr	r2, [r6, #4]
	ldr	r0, [r8]
	ldr	r1, .L63+228
	bl	dev_err
	b	.L1
.L24:
	mov	r2, r4
	ldr	r0, [r8]
	ldr	r1, .L63+232
	bl	dev_err
	b	.L1
.L29:
	mov	r2, r4
	ldr	r3, [r6, #4]
	ldr	r0, [r8]
	ldr	r1, .L63+236
	bl	dev_err
	b	.L1
.L64:
	.align	2
.L63:
	.word	.LC0
	.word	.LC1
	.word	EINVAL
	.word	PCM512x_ALEN_16
	.word	SND_SOC_DAIFMT_MASTER_MASK
	.word	PCM512x_ALEN_20
	.word	PCM512x_ALEN_24
	.word	PCM512x_ALEN_32
	.word	PCM512x_BCKO
	.word	PCM512x_BCKP
	.word	PCM512x_LRKO
	.word	PCM512x_BCLK_LRCLK_CFG
	.word	PCM512x_DCAS
	.word	PCM512x_ERROR_DETECT
	.word	.LC3
	.word	PCM512x_RLRK
	.word	PCM512x_RBCK
	.word	PCM512x_ALEN
	.word	PCM512x_I2S_1
	.word	PCM512x_FLEX_A
	.word	PCM512x_FLEX_B
	.word	PCM512x_IDFS
	.word	PCM512x_IDBK
	.word	PCM512x_IDSK
	.word	PCM512x_IDCM
	.word	PCM512x_IDCH
	.word	PCM512x_IPLK
	.word	PCM512x_SREF_GPIO
	.word	PCM512x_SREF
	.word	PCM512x_PLL_REF
	.word	PCM512x_GREF_GPIO1
	.word	PCM512x_GPIO_PLLIN
	.word	PCM512x_GREF
	.word	PCM512x_PLLE
	.word	PCM512x_PLL_EN
	.word	PCM512x_MASTER_MODE
	.word	PCM512x_G1OE
	.word	PCM512x_GPIO_EN
	.word	PCM512x_GPIO_OUTPUT_1
	.word	PCM512x_GxSL
	.word	PCM512x_GxSL_PLLCK
	.word	PCM512x_RQSY_HALT
	.word	PCM512x_RQSY
	.word	PCM512x_SYNCHRONIZE
	.word	PCM512x_RQSY_RESUME
	.word	.LC17
	.word	.LC8
	.word	.LC4
	.word	.LC7
	.word	.LC2
	.word	.LC5
	.word	.LC12
	.word	.LC6
	.word	.LC9
	.word	.LC10
	.word	.LC16
	.word	.LC13
	.word	.LC14
	.word	.LC11
	.word	.LC15
	.size	pcm512x_hw_params, .-pcm512x_hw_params
	.comm	SND_SOC_DAIFMT_MASTER_MASK,4,4
	.comm	PCM512x_SYNCHRONIZE,4,4
	.comm	PCM512x_SREF_GPIO,4,4
	.comm	PCM512x_SREF,4,4
	.comm	PCM512x_RQSY_RESUME,4,4
	.comm	PCM512x_RQSY_HALT,4,4
	.comm	PCM512x_RQSY,4,4
	.comm	PCM512x_RLRK,4,4
	.comm	PCM512x_RBCK,4,4
	.comm	PCM512x_PLL_REF,4,4
	.comm	PCM512x_PLL_EN,4,4
	.comm	PCM512x_PLLE,4,4
	.comm	PCM512x_MASTER_MODE,4,4
	.comm	PCM512x_LRKO,4,4
	.comm	PCM512x_IPLK,4,4
	.comm	PCM512x_IDSK,4,4
	.comm	PCM512x_IDFS,4,4
	.comm	PCM512x_IDCM,4,4
	.comm	PCM512x_IDCH,4,4
	.comm	PCM512x_IDBK,4,4
	.comm	PCM512x_I2S_1,4,4
	.comm	PCM512x_GxSL_PLLCK,4,4
	.comm	PCM512x_GxSL,4,4
	.comm	PCM512x_GREF_GPIO1,4,4
	.comm	PCM512x_GREF,4,4
	.comm	PCM512x_GPIO_PLLIN,4,4
	.comm	PCM512x_GPIO_OUTPUT_1,4,4
	.comm	PCM512x_GPIO_EN,4,4
	.comm	PCM512x_G1OE,4,4
	.comm	PCM512x_FLEX_B,4,4
	.comm	PCM512x_FLEX_A,4,4
	.comm	PCM512x_ERROR_DETECT,4,4
	.comm	PCM512x_DCAS,4,4
	.comm	PCM512x_BCLK_LRCLK_CFG,4,4
	.comm	PCM512x_BCKP,4,4
	.comm	PCM512x_BCKO,4,4
	.comm	PCM512x_ALEN_32,4,4
	.comm	PCM512x_ALEN_24,4,4
	.comm	PCM512x_ALEN_20,4,4
	.comm	PCM512x_ALEN_16,4,4
	.comm	PCM512x_ALEN,4,4
	.comm	EINVAL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
