	.file	"extr_radeon_i2c.c_r100_hw_i2c_xfer.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC0:
	.string	"gpio not supported with hw i2c\n"
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"unsupported asic\n"
.LC2:
	.string	"i2c write error 0x%08x\n"
.LC3:
	.string	"i2c read error 0x%08x\n"
	.text
	.p2align 4
	.type	r100_hw_i2c_xfer, @function
r100_hw_i2c_xfer:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	rbx, rsi
	sub	rsp, 56
	.cfi_def_cfa_offset 112
	mov	DWORD PTR 16[rsp], edx
	call	i2c_get_adapdata@PLT
	mov	r12, rax
	mov	rax, QWORD PTR 16[rax]
	mov	r15, QWORD PTR [rax]
	lea	rax, 4[r15]
	mov	QWORD PTR 24[rsp], r15
	mov	rdi, rax
	mov	QWORD PTR 32[rsp], rax
	call	mutex_lock@PLT
	lea	rax, 8[r15]
	mov	rdi, rax
	mov	QWORD PTR 40[rsp], rax
	call	mutex_lock@PLT
	mov	rdi, r15
	call	radeon_get_i2c_prescale@PLT
	mov	ecx, DWORD PTR RADEON_I2C_PRESCALE_SHIFT[rip]
	mov	r14d, DWORD PTR RADEON_I2C_DRIVE_EN[rip]
	or	r14d, DWORD PTR RADEON_I2C_START[rip]
	or	r14d, DWORD PTR RADEON_I2C_STOP[rip]
	sal	eax, cl
	or	r14d, DWORD PTR RADEON_I2C_GO[rip]
	or	r14d, eax
	cmp	QWORD PTR 16[r15], 0
	jne	.L57
.L2:
	cmp	QWORD PTR 8[r12], 0
	je	.L3
	mov	ebp, DWORD PTR RADEON_I2C_CNTL_0[rip]
	mov	r15d, DWORD PTR RADEON_I2C_CNTL_1[rip]
	mov	r13d, DWORD PTR RADEON_I2C_DATA[rip]
.L4:
	cmp	DWORD PTR 16[rsp], 1
	je	.L58
	mov	edx, DWORD PTR 16[rsp]
	test	edx, edx
	jle	.L55
.L27:
	mov	DWORD PTR 20[rsp], 0
.L31:
	mov	eax, DWORD PTR [rbx]
	xor	r12d, r12d
	test	eax, eax
	jle	.L40
	.p2align 4,,10
	.p2align 3
.L30:
	mov	esi, DWORD PTR RADEON_I2C_DONE[rip]
	mov	eax, DWORD PTR 8[rbx]
	mov	edi, ebp
	or	esi, DWORD PTR RADEON_I2C_NACK[rip]
	or	esi, DWORD PTR RADEON_I2C_HALT[rip]
	or	esi, DWORD PTR RADEON_I2C_SOFT_RST[rip]
	test	DWORD PTR I2C_M_RD[rip], eax
	je	.L32
	call	WREG32@PLT
	mov	eax, DWORD PTR 4[rbx]
	mov	edi, r13d
	lea	esi, [rax+rax]
	movzx	esi, sil
	or	esi, 1
	call	WREG32@PLT
	mov	ecx, DWORD PTR RADEON_I2C_ADDR_COUNT_SHIFT[rip]
	mov	esi, 1
	mov	edi, r15d
	mov	eax, DWORD PTR RADEON_I2C_DATA_COUNT_SHIFT[rip]
	sal	esi, cl
	mov	ecx, DWORD PTR RADEON_I2C_TIME_LIMIT_SHIFT[rip]
	bts	esi, eax
	mov	eax, 48
	or	esi, DWORD PTR RADEON_I2C_EN[rip]
	sal	eax, cl
	or	esi, eax
	call	WREG32@PLT
	mov	esi, DWORD PTR RADEON_I2C_RECEIVE[rip]
	mov	edi, ebp
	or	esi, r14d
	call	WREG32@PLT
	mov	DWORD PTR 12[rsp], 32
.L34:
	mov	edi, 10
	call	udelay@PLT
	mov	edi, ebp
	call	RREG32@PLT
	test	DWORD PTR RADEON_I2C_GO[rip], eax
	je	.L33
	sub	DWORD PTR 12[rsp], 1
	jne	.L34
	.p2align 4,,10
	.p2align 3
.L35:
	mov	edi, r13d
	call	RREG32@PLT
	mov	rdx, QWORD PTR 16[rbx]
	movzx	eax, al
	mov	DWORD PTR [rdx+r12*4], eax
.L36:
	add	r12, 1
	cmp	DWORD PTR [rbx], r12d
	jg	.L30
.L40:
	add	DWORD PTR 20[rsp], 1
	add	rbx, 24
	mov	eax, DWORD PTR 20[rsp]
	cmp	DWORD PTR 16[rsp], eax
	jg	.L31
.L55:
	mov	r12d, DWORD PTR 16[rsp]
	jmp	.L12
	.p2align 4,,10
	.p2align 3
.L32:
	call	WREG32@PLT
	mov	eax, DWORD PTR 4[rbx]
	mov	edi, r13d
	lea	esi, [rax+rax]
	movzx	esi, sil
	call	WREG32@PLT
	mov	rax, QWORD PTR 16[rbx]
	mov	edi, r13d
	mov	esi, DWORD PTR [rax+r12*4]
	call	WREG32@PLT
	mov	ecx, DWORD PTR RADEON_I2C_ADDR_COUNT_SHIFT[rip]
	mov	esi, 1
	mov	edi, r15d
	mov	eax, DWORD PTR RADEON_I2C_DATA_COUNT_SHIFT[rip]
	sal	esi, cl
	mov	ecx, DWORD PTR RADEON_I2C_TIME_LIMIT_SHIFT[rip]
	bts	esi, eax
	mov	eax, 48
	or	esi, DWORD PTR RADEON_I2C_EN[rip]
	sal	eax, cl
	or	esi, eax
	call	WREG32@PLT
	mov	esi, r14d
	mov	edi, ebp
	call	WREG32@PLT
	mov	DWORD PTR 12[rsp], 32
.L38:
	mov	edi, 10
	call	udelay@PLT
	mov	edi, ebp
	call	RREG32@PLT
	test	DWORD PTR RADEON_I2C_GO[rip], eax
	je	.L37
	sub	DWORD PTR 12[rsp], 1
	jne	.L38
	jmp	.L36
	.p2align 4,,10
	.p2align 3
.L33:
	mov	edi, ebp
	call	RREG32@PLT
	mov	esi, eax
	test	DWORD PTR RADEON_I2C_DONE[rip], eax
	jne	.L35
	mov	DWORD PTR 12[rsp], eax
	lea	rdi, .LC3[rip]
	jmp	.L54
	.p2align 4,,10
	.p2align 3
.L37:
	mov	edi, ebp
	call	RREG32@PLT
	mov	esi, eax
	test	DWORD PTR RADEON_I2C_DONE[rip], eax
	jne	.L36
	mov	DWORD PTR 12[rsp], eax
	lea	rdi, .LC2[rip]
.L54:
	call	DRM_DEBUG@PLT
	mov	esi, DWORD PTR 12[rsp]
	mov	edi, ebp
	or	esi, DWORD PTR RADEON_I2C_ABORT[rip]
	call	WREG32@PLT
	mov	r12d, DWORD PTR EIO[rip]
	neg	r12d
.L12:
	xor	esi, esi
	mov	edi, ebp
	call	WREG32@PLT
	xor	esi, esi
	mov	edi, r15d
	call	WREG32@PLT
	mov	esi, DWORD PTR RADEON_I2C_DONE[rip]
	mov	edi, ebp
	or	esi, DWORD PTR RADEON_I2C_NACK[rip]
	or	esi, DWORD PTR RADEON_I2C_HALT[rip]
	or	esi, DWORD PTR RADEON_I2C_SOFT_RST[rip]
	call	WREG32@PLT
	mov	rax, QWORD PTR 24[rsp]
	cmp	QWORD PTR 16[rax], 0
	jne	.L59
.L41:
	mov	rdi, QWORD PTR 40[rsp]
	call	mutex_unlock@PLT
	mov	rdi, QWORD PTR 32[rsp]
	call	mutex_unlock@PLT
	add	rsp, 56
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	eax, r12d
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L3:
	.cfi_restore_state
	mov	rax, QWORD PTR 24[rsp]
	mov	ebp, DWORD PTR RADEON_DVI_I2C_CNTL_0[rip]
	mov	r15d, DWORD PTR RADEON_DVI_I2C_CNTL_1[rip]
	mov	r13d, DWORD PTR RADEON_DVI_I2C_DATA[rip]
	mov	eax, DWORD PTR [rax]
	mov	DWORD PTR 12[rsp], eax
	sub	eax, 132
	cmp	eax, 17
	ja	.L5
	lea	rdx, .L7[rip]
	movsx	rax, DWORD PTR [rdx+rax*4]
	add	rax, rdx
	notrack jmp	rax
	.section	.rodata
	.align 4
	.align 4
.L7:
	.long	.L10-.L7
	.long	.L10-.L7
	.long	.L10-.L7
	.long	.L11-.L7
	.long	.L11-.L7
	.long	.L6-.L7
	.long	.L6-.L7
	.long	.L10-.L7
	.long	.L10-.L7
	.long	.L6-.L7
	.long	.L6-.L7
	.long	.L6-.L7
	.long	.L10-.L7
	.long	.L10-.L7
	.long	.L9-.L7
	.long	.L9-.L7
	.long	.L8-.L7
	.long	.L6-.L7
	.text
	.p2align 4,,10
	.p2align 3
.L57:
	mov	edi, DWORD PTR RADEON_BIOS_6_SCRATCH[rip]
	call	RREG32@PLT
	mov	edi, DWORD PTR RADEON_BIOS_6_SCRATCH[rip]
	or	eax, DWORD PTR ATOM_S6_HW_I2C_BUSY_STATE[rip]
	mov	esi, eax
	call	WREG32@PLT
	jmp	.L2
	.p2align 4,,10
	.p2align 3
.L59:
	mov	edi, DWORD PTR RADEON_BIOS_6_SCRATCH[rip]
	call	RREG32@PLT
	mov	esi, DWORD PTR ATOM_S6_HW_I2C_BUSY_STATE[rip]
	mov	edi, DWORD PTR RADEON_BIOS_6_SCRATCH[rip]
	not	esi
	and	esi, eax
	call	WREG32@PLT
	jmp	.L41
	.p2align 4,,10
	.p2align 3
.L58:
	mov	ecx, DWORD PTR [rbx]
	test	ecx, ecx
	jne	.L27
	mov	esi, DWORD PTR RADEON_I2C_DONE[rip]
	mov	edi, ebp
	or	esi, DWORD PTR RADEON_I2C_NACK[rip]
	or	esi, DWORD PTR RADEON_I2C_HALT[rip]
	or	esi, DWORD PTR RADEON_I2C_SOFT_RST[rip]
	call	WREG32@PLT
	mov	esi, DWORD PTR 4[rbx]
	mov	edi, r13d
	mov	ebx, 32
	add	esi, esi
	movzx	esi, sil
	call	WREG32@PLT
	xor	esi, esi
	mov	edi, r13d
	call	WREG32@PLT
	mov	ecx, DWORD PTR RADEON_I2C_ADDR_COUNT_SHIFT[rip]
	mov	esi, DWORD PTR 16[rsp]
	mov	edi, r15d
	mov	eax, DWORD PTR RADEON_I2C_DATA_COUNT_SHIFT[rip]
	sal	esi, cl
	mov	ecx, DWORD PTR RADEON_I2C_TIME_LIMIT_SHIFT[rip]
	bts	esi, eax
	mov	eax, 48
	or	esi, DWORD PTR RADEON_I2C_EN[rip]
	sal	eax, cl
	or	esi, eax
	call	WREG32@PLT
	mov	esi, r14d
	mov	edi, ebp
	call	WREG32@PLT
.L29:
	mov	edi, 10
	call	udelay@PLT
	mov	edi, ebp
	call	RREG32@PLT
	test	DWORD PTR RADEON_I2C_GO[rip], eax
	je	.L28
	sub	ebx, 1
	jne	.L29
	mov	r12d, 1
	jmp	.L12
	.p2align 4,,10
	.p2align 3
.L10:
	mov	eax, DWORD PTR [r12]
	cmp	eax, 129
	je	.L22
	cmp	eax, 130
	je	.L23
	cmp	eax, 128
	je	.L53
.L24:
	lea	rdi, .LC0[rip]
	call	DRM_ERROR@PLT
	mov	r12d, DWORD PTR EINVAL[rip]
	neg	r12d
	jmp	.L12
.L6:
	cmp	DWORD PTR [r12], 130
	je	.L4
	jmp	.L24
.L9:
	mov	eax, DWORD PTR [r12]
	cmp	eax, 128
	je	.L53
	cmp	eax, 130
	jne	.L24
.L22:
	mov	edi, DWORD PTR R200_SEL_DDC3[rip]
	call	R200_DVI_I2C_PIN_SEL@PLT
	or	r14d, eax
	jmp	.L4
.L11:
	mov	eax, DWORD PTR [r12]
	cmp	eax, 130
	je	.L53
	cmp	eax, 131
	je	.L22
	cmp	eax, 128
	jne	.L24
.L23:
	mov	edi, DWORD PTR R200_SEL_DDC2[rip]
	call	R200_DVI_I2C_PIN_SEL@PLT
	or	r14d, eax
	jmp	.L4
.L8:
	mov	eax, DWORD PTR [r12]
	cmp	eax, 129
	je	.L22
	cmp	eax, 130
	jne	.L24
.L53:
	mov	edi, DWORD PTR R200_SEL_DDC1[rip]
	call	R200_DVI_I2C_PIN_SEL@PLT
	or	r14d, eax
	jmp	.L4
.L28:
	mov	edi, ebp
	mov	r12d, 1
	call	RREG32@PLT
	mov	ebx, eax
	test	DWORD PTR RADEON_I2C_DONE[rip], eax
	jne	.L12
	mov	esi, eax
	lea	rdi, .LC2[rip]
	call	DRM_DEBUG@PLT
	or	ebx, DWORD PTR RADEON_I2C_ABORT[rip]
	mov	edi, ebp
	mov	esi, ebx
	call	WREG32@PLT
	mov	r12d, DWORD PTR EIO[rip]
	neg	r12d
	jmp	.L12
.L5:
	lea	rdi, .LC1[rip]
	call	DRM_ERROR@PLT
	mov	r12d, DWORD PTR EINVAL[rip]
	neg	r12d
	jmp	.L12
	.cfi_endproc
.LFE0:
	.size	r100_hw_i2c_xfer, .-r100_hw_i2c_xfer
	.comm	RADEON_I2C_TIME_LIMIT_SHIFT,4,4
	.comm	RADEON_I2C_STOP,4,4
	.comm	RADEON_I2C_START,4,4
	.comm	RADEON_I2C_SOFT_RST,4,4
	.comm	RADEON_I2C_RECEIVE,4,4
	.comm	RADEON_I2C_PRESCALE_SHIFT,4,4
	.comm	RADEON_I2C_NACK,4,4
	.comm	RADEON_I2C_HALT,4,4
	.comm	RADEON_I2C_GO,4,4
	.comm	RADEON_I2C_EN,4,4
	.comm	RADEON_I2C_DRIVE_EN,4,4
	.comm	RADEON_I2C_DONE,4,4
	.comm	RADEON_I2C_DATA_COUNT_SHIFT,4,4
	.comm	RADEON_I2C_DATA,4,4
	.comm	RADEON_I2C_CNTL_1,4,4
	.comm	RADEON_I2C_CNTL_0,4,4
	.comm	RADEON_I2C_ADDR_COUNT_SHIFT,4,4
	.comm	RADEON_I2C_ABORT,4,4
	.comm	RADEON_DVI_I2C_DATA,4,4
	.comm	RADEON_DVI_I2C_CNTL_1,4,4
	.comm	RADEON_DVI_I2C_CNTL_0,4,4
	.comm	RADEON_BIOS_6_SCRATCH,4,4
	.comm	R200_SEL_DDC3,4,4
	.comm	R200_SEL_DDC2,4,4
	.comm	R200_SEL_DDC1,4,4
	.comm	I2C_M_RD,4,4
	.comm	EIO,4,4
	.comm	EINVAL,4,4
	.comm	ATOM_S6_HW_I2C_BUSY_STATE,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_radeon_i2c.c_r100_hw_i2c_xfer.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"gpio not supported with hw i2c\012\000"
	.align	2
.LC1:
	.ascii	"unsupported asic\012\000"
	.align	2
.LC2:
	.ascii	"i2c write error 0x%08x\012\000"
	.align	2
.LC3:
	.ascii	"i2c read error 0x%08x\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	r100_hw_i2c_xfer, %function
r100_hw_i2c_xfer:
	@ args = 0, pretend = 0, frame = 40
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	sub	sp, sp, #44
	mov	r5, r1
	str	r2, [sp, #20]
	bl	i2c_get_adapdata
	ldr	r3, [r0, #8]
	mov	r6, r0
	ldr	r4, [r3]
	ldr	r10, .L70
	add	r3, r4, #4
	mov	r0, r3
	str	r3, [sp, #32]
	add	r3, r4, #8
	mov	r7, r3
	str	r3, [sp, #36]
	str	r4, [sp, #24]
	bl	mutex_lock
	mov	r0, r7
	bl	mutex_lock
	mov	r0, r4
	bl	radeon_get_i2c_prescale
	ldr	r3, .L70+4
	ldr	r1, .L70+8
	ldr	r2, .L70+12
	ldr	r1, [r1]
	ldr	r3, [r3]
	ldr	r2, [r2]
	orr	r3, r3, r1
	orr	r3, r3, r2
	ldr	r1, .L70+16
	ldr	r2, [r10]
	ldr	r1, [r1]
	orr	r3, r3, r2
	ldr	r2, [r4, #12]
	orr	r3, r3, r0, lsl r1
	cmp	r2, #0
	str	r3, [sp, #16]
	bne	.L66
.L2:
	ldr	r3, [r6, #4]
	cmp	r3, #0
	beq	.L3
	ldr	r2, .L70+20
	ldr	r1, .L70+24
	ldr	r3, .L70+28
	ldr	r2, [r2]
	ldr	r4, [r1]
	ldr	r8, [r3]
	str	r2, [sp, #4]
.L4:
	ldr	r3, [sp, #20]
	cmp	r3, #1
	beq	.L67
	ldr	r3, [sp, #20]
	cmp	r3, #0
	ble	.L68
.L27:
	mov	r3, #0
	str	r3, [sp, #28]
	ldr	r3, .L70+32
	ldr	r7, .L70+36
	str	r3, [sp, #12]
	ldr	r3, .L70+40
	ldr	fp, .L70+44
	str	r3, [sp, #8]
.L31:
	ldr	r3, [r5]
	cmp	r3, #0
	movgt	r6, #0
	ble	.L40
.L30:
	ldr	r3, [sp, #12]
	ldr	r1, [r7]
	ldr	r2, [r3]
	ldr	r3, [sp, #8]
	orr	r1, r1, r2
	ldr	r2, .L70+48
	ldr	r3, [r3]
	ldr	r0, [r5, #8]
	ldr	r2, [r2]
	orr	r1, r1, r3
	ldr	r3, [fp]
	tst	r0, r2
	orr	r1, r1, r3
	mov	r0, r4
	beq	.L32
	bl	WREG32
	ldr	r1, [r5, #4]
	mov	r0, r8
	lsl	r1, r1, #1
	and	r1, r1, #255
	orr	r1, r1, #1
	bl	WREG32
	mov	r0, #1
	ldr	r2, .L70+52
	ldr	r3, .L70+56
	ldr	r1, [r2]
	ldr	r3, [r3]
	ldr	r2, .L70+60
	lsl	r3, r0, r3
	ldr	r2, [r2]
	orr	r3, r3, r0, lsl r1
	orr	r3, r3, r2
	mov	r2, #48
	ldr	r1, .L70+64
	ldr	r0, [sp, #4]
	ldr	r1, [r1]
	mov	r9, #32
	orr	r1, r3, r2, lsl r1
	bl	WREG32
	ldr	r3, .L70+68
	mov	r0, r4
	ldr	r1, [r3]
	ldr	r3, [sp, #16]
	orr	r1, r3, r1
	bl	WREG32
.L34:
	mov	r0, #10
	bl	udelay
	mov	r0, r4
	bl	RREG32
	ldr	r3, [r10]
	tst	r0, r3
	beq	.L33
	subs	r9, r9, #1
	bne	.L34
.L35:
	mov	r0, r8
	bl	RREG32
	ldr	r3, [r5, #12]
	and	r0, r0, #255
	str	r0, [r3, r6, lsl #2]
.L36:
	ldr	r3, [r5]
	add	r6, r6, #1
	cmp	r3, r6
	bgt	.L30
.L40:
	ldr	r3, [sp, #28]
	ldr	r2, [sp, #20]
	add	r3, r3, #1
	cmp	r2, r3
	str	r3, [sp, #28]
	add	r5, r5, #16
	bgt	.L31
	mov	r5, r2
	b	.L12
.L32:
	bl	WREG32
	ldr	r1, [r5, #4]
	mov	r0, r8
	lsl	r1, r1, #1
	and	r1, r1, #254
	bl	WREG32
	ldr	r3, [r5, #12]
	mov	r0, r8
	ldr	r1, [r3, r6, lsl #2]
	bl	WREG32
	mov	r0, #1
	ldr	r2, .L70+52
	ldr	r3, .L70+56
	ldr	r1, [r2]
	ldr	r3, [r3]
	ldr	r2, .L70+60
	lsl	r3, r0, r3
	ldr	r2, [r2]
	orr	r3, r3, r0, lsl r1
	orr	r3, r3, r2
	mov	r2, #48
	ldr	r1, .L70+64
	ldr	r0, [sp, #4]
	ldr	r1, [r1]
	mov	r9, #32
	orr	r1, r3, r2, lsl r1
	bl	WREG32
	mov	r0, r4
	ldr	r1, [sp, #16]
	bl	WREG32
.L38:
	mov	r0, #10
	bl	udelay
	mov	r0, r4
	bl	RREG32
	ldr	r3, [r10]
	tst	r0, r3
	beq	.L37
	subs	r9, r9, #1
	bne	.L38
	b	.L36
.L33:
	mov	r0, r4
	bl	RREG32
	ldr	r3, [r7]
	tst	r0, r3
	bne	.L35
	mov	r9, r0
	mov	r1, r0
	ldr	r0, .L70+72
	b	.L63
.L37:
	mov	r0, r4
	bl	RREG32
	ldr	r3, [r7]
	tst	r0, r3
	bne	.L36
	mov	r9, r0
	mov	r1, r0
	ldr	r0, .L70+76
.L63:
	bl	DRM_DEBUG
	ldr	r3, .L70+80
	mov	r0, r4
	ldr	r1, [r3]
	orr	r1, r9, r1
	bl	WREG32
	ldr	r3, .L70+84
	ldr	r5, [r3]
	rsb	r5, r5, #0
.L12:
	mov	r1, #0
	mov	r0, r4
	bl	WREG32
	mov	r1, #0
	ldr	r0, [sp, #4]
	bl	WREG32
	ldr	r2, [sp, #12]
	ldr	r3, [r7]
	ldr	r1, [r2]
	ldr	r2, [sp, #8]
	orr	r3, r3, r1
	ldr	r2, [r2]
	ldr	r1, [fp]
	orr	r3, r3, r2
	orr	r1, r3, r1
	mov	r0, r4
	bl	WREG32
	ldr	r3, [sp, #24]
	ldr	r3, [r3, #12]
	cmp	r3, #0
	bne	.L69
.L41:
	ldr	r0, [sp, #36]
	bl	mutex_unlock
	ldr	r0, [sp, #32]
	bl	mutex_unlock
	mov	r0, r5
	add	sp, sp, #44
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L3:
	ldr	r3, [sp, #24]
	ldr	r1, .L70+88
	ldr	r3, [r3]
	ldr	r0, .L70+92
	ldr	r2, .L70+96
	ldr	r1, [r1]
	sub	r3, r3, #132
	ldr	r4, [r0]
	ldr	r8, [r2]
	str	r1, [sp, #4]
	cmp	r3, #17
	ldrls	pc, [pc, r3, asl #2]
	b	.L5
.L7:
	.word	.L10
	.word	.L10
	.word	.L10
	.word	.L11
	.word	.L11
	.word	.L6
	.word	.L6
	.word	.L10
	.word	.L10
	.word	.L6
	.word	.L6
	.word	.L6
	.word	.L10
	.word	.L10
	.word	.L9
	.word	.L9
	.word	.L8
	.word	.L6
.L66:
	ldr	r4, .L70+100
	ldr	r0, [r4]
	bl	RREG32
	mov	r1, r0
	ldr	r3, .L70+104
	ldr	r0, [r4]
	ldr	r3, [r3]
	orr	r1, r1, r3
	bl	WREG32
	b	.L2
.L69:
	ldr	r4, .L70+100
	ldr	r0, [r4]
	bl	RREG32
	mov	r3, r0
	ldr	r2, .L70+104
	ldr	r0, [r4]
	ldr	r1, [r2]
	bic	r1, r3, r1
	bl	WREG32
	b	.L41
.L67:
	ldr	r6, [r5]
	cmp	r6, #0
	bne	.L27
	ldr	r2, .L70+32
	ldr	r7, .L70+36
	ldr	r0, .L70+40
	ldr	r1, [r2]
	ldr	r3, [r7]
	ldr	fp, .L70+44
	str	r2, [sp, #12]
	ldr	r2, [r0]
	orr	r3, r3, r1
	ldr	r1, [fp]
	orr	r3, r3, r2
	orr	r1, r3, r1
	str	r0, [sp, #8]
	mov	r0, r4
	bl	WREG32
	ldr	r1, [r5, #4]
	mov	r0, r8
	lsl	r1, r1, #1
	and	r1, r1, #254
	bl	WREG32
	mov	r1, r6
	mov	r0, r8
	bl	WREG32
	mov	r1, #48
	ldr	r3, .L70+56
	ldr	r2, .L70+52
	ldr	ip, [sp, #20]
	ldr	r3, [r3]
	ldr	r0, .L70+60
	ldr	r5, [r2]
	ldr	r2, .L70+64
	lsl	r3, ip, r3
	ldr	r0, [r0]
	orr	r5, r3, ip, lsl r5
	ldr	r2, [r2]
	orr	r0, r5, r0
	orr	r1, r0, r1, lsl r2
	ldr	r0, [sp, #4]
	bl	WREG32
	mov	r0, r4
	ldr	r1, [sp, #16]
	bl	WREG32
	mov	r5, #32
.L29:
	mov	r0, #10
	bl	udelay
	mov	r0, r4
	bl	RREG32
	ldr	r3, [r10]
	tst	r0, r3
	beq	.L28
	subs	r5, r5, #1
	bne	.L29
.L42:
	mov	r5, #1
	b	.L12
.L10:
	ldr	r3, [r6]
	cmp	r3, #129
	beq	.L22
	cmp	r3, #130
	beq	.L23
	cmp	r3, #128
	beq	.L64
.L24:
	ldr	r0, .L70+108
.L62:
	bl	DRM_ERROR
	ldr	r3, .L70+112
	ldr	r7, .L70+36
	ldr	r5, [r3]
	ldr	r3, .L70+32
	ldr	fp, .L70+44
	str	r3, [sp, #12]
	ldr	r3, .L70+40
	rsb	r5, r5, #0
	str	r3, [sp, #8]
	b	.L12
.L6:
	ldr	r3, [r6]
	cmp	r3, #130
	beq	.L4
	b	.L24
.L11:
	ldr	r3, [r6]
	cmp	r3, #130
	beq	.L64
	cmp	r3, #131
	beq	.L22
	cmp	r3, #128
	bne	.L24
.L23:
	ldr	r3, .L70+116
	b	.L61
.L9:
	ldr	r3, [r6]
	cmp	r3, #128
	beq	.L64
	cmp	r3, #130
	bne	.L24
.L22:
	ldr	r3, .L70+120
.L61:
	ldr	r0, [r3]
	bl	R200_DVI_I2C_PIN_SEL
	ldr	r3, [sp, #16]
	orr	r3, r3, r0
	str	r3, [sp, #16]
	b	.L4
.L8:
	ldr	r3, [r6]
	cmp	r3, #129
	beq	.L22
	cmp	r3, #130
	bne	.L24
.L64:
	ldr	r3, .L70+124
	b	.L61
.L28:
	mov	r0, r4
	bl	RREG32
	ldr	r3, [r7]
	mov	r5, r0
	tst	r0, r3
	bne	.L42
	mov	r1, r0
	ldr	r0, .L70+76
	bl	DRM_DEBUG
	ldr	r3, .L70+80
	mov	r0, r4
	ldr	r1, [r3]
	orr	r1, r5, r1
	bl	WREG32
	ldr	r3, .L70+84
	ldr	r5, [r3]
	rsb	r5, r5, #0
	b	.L12
.L68:
	mov	r5, r3
	ldr	r3, .L70+32
	ldr	r7, .L70+36
	str	r3, [sp, #12]
	ldr	r3, .L70+40
	ldr	fp, .L70+44
	str	r3, [sp, #8]
	b	.L12
.L5:
	ldr	r0, .L70+128
	b	.L62
.L71:
	.align	2
.L70:
	.word	RADEON_I2C_GO
	.word	RADEON_I2C_DRIVE_EN
	.word	RADEON_I2C_START
	.word	RADEON_I2C_STOP
	.word	RADEON_I2C_PRESCALE_SHIFT
	.word	RADEON_I2C_CNTL_1
	.word	RADEON_I2C_CNTL_0
	.word	RADEON_I2C_DATA
	.word	RADEON_I2C_NACK
	.word	RADEON_I2C_DONE
	.word	RADEON_I2C_HALT
	.word	RADEON_I2C_SOFT_RST
	.word	I2C_M_RD
	.word	RADEON_I2C_DATA_COUNT_SHIFT
	.word	RADEON_I2C_ADDR_COUNT_SHIFT
	.word	RADEON_I2C_EN
	.word	RADEON_I2C_TIME_LIMIT_SHIFT
	.word	RADEON_I2C_RECEIVE
	.word	.LC3
	.word	.LC2
	.word	RADEON_I2C_ABORT
	.word	EIO
	.word	RADEON_DVI_I2C_CNTL_1
	.word	RADEON_DVI_I2C_CNTL_0
	.word	RADEON_DVI_I2C_DATA
	.word	RADEON_BIOS_6_SCRATCH
	.word	ATOM_S6_HW_I2C_BUSY_STATE
	.word	.LC0
	.word	EINVAL
	.word	R200_SEL_DDC2
	.word	R200_SEL_DDC3
	.word	R200_SEL_DDC1
	.word	.LC1
	.size	r100_hw_i2c_xfer, .-r100_hw_i2c_xfer
	.comm	RADEON_I2C_TIME_LIMIT_SHIFT,4,4
	.comm	RADEON_I2C_STOP,4,4
	.comm	RADEON_I2C_START,4,4
	.comm	RADEON_I2C_SOFT_RST,4,4
	.comm	RADEON_I2C_RECEIVE,4,4
	.comm	RADEON_I2C_PRESCALE_SHIFT,4,4
	.comm	RADEON_I2C_NACK,4,4
	.comm	RADEON_I2C_HALT,4,4
	.comm	RADEON_I2C_GO,4,4
	.comm	RADEON_I2C_EN,4,4
	.comm	RADEON_I2C_DRIVE_EN,4,4
	.comm	RADEON_I2C_DONE,4,4
	.comm	RADEON_I2C_DATA_COUNT_SHIFT,4,4
	.comm	RADEON_I2C_DATA,4,4
	.comm	RADEON_I2C_CNTL_1,4,4
	.comm	RADEON_I2C_CNTL_0,4,4
	.comm	RADEON_I2C_ADDR_COUNT_SHIFT,4,4
	.comm	RADEON_I2C_ABORT,4,4
	.comm	RADEON_DVI_I2C_DATA,4,4
	.comm	RADEON_DVI_I2C_CNTL_1,4,4
	.comm	RADEON_DVI_I2C_CNTL_0,4,4
	.comm	RADEON_BIOS_6_SCRATCH,4,4
	.comm	R200_SEL_DDC3,4,4
	.comm	R200_SEL_DDC2,4,4
	.comm	R200_SEL_DDC1,4,4
	.comm	I2C_M_RD,4,4
	.comm	EIO,4,4
	.comm	EINVAL,4,4
	.comm	ATOM_S6_HW_I2C_BUSY_STATE,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
