	.file	"extr_rv515.c_rv515_ring_start.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	rv515_ring_start
	.type	rv515_ring_start, @function
rv515_ring_start:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	mov	edx, 64
	mov	r12, rdi
	push	rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	mov	rbp, rsi
	push	rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	call	radeon_ring_lock@PLT
	test	eax, eax
	je	.L5
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L5:
	.cfi_restore_state
	mov	edi, DWORD PTR ISYNC_CNTL[rip]
	xor	esi, esi
	mov	ebx, 6
	call	PACKET0@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	radeon_ring_write@PLT
	mov	rdi, rbp
	mov	esi, DWORD PTR ISYNC_ANY2D_IDLE3D[rip]
	or	esi, DWORD PTR ISYNC_ANY3D_IDLE2D[rip]
	or	esi, DWORD PTR ISYNC_WAIT_IDLEGUI[rip]
	or	esi, DWORD PTR ISYNC_CPSCRATCH_IDLEGUI[rip]
	call	radeon_ring_write@PLT
	mov	edi, DWORD PTR WAIT_UNTIL[rip]
	xor	esi, esi
	call	PACKET0@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	radeon_ring_write@PLT
	mov	rdi, rbp
	mov	esi, DWORD PTR WAIT_2D_IDLECLEAN[rip]
	or	esi, DWORD PTR WAIT_3D_IDLECLEAN[rip]
	call	radeon_ring_write@PLT
	mov	edi, DWORD PTR R300_DST_PIPE_CONFIG[rip]
	xor	esi, esi
	call	PACKET0@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	radeon_ring_write@PLT
	mov	esi, DWORD PTR R300_PIPE_AUTO_CONFIG[rip]
	mov	rdi, rbp
	call	radeon_ring_write@PLT
	mov	edi, DWORD PTR GB_SELECT[rip]
	xor	esi, esi
	call	PACKET0@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	radeon_ring_write@PLT
	xor	esi, esi
	mov	rdi, rbp
	call	radeon_ring_write@PLT
	mov	edi, DWORD PTR GB_ENABLE[rip]
	xor	esi, esi
	call	PACKET0@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	radeon_ring_write@PLT
	xor	esi, esi
	mov	rdi, rbp
	call	radeon_ring_write@PLT
	mov	edi, DWORD PTR R500_SU_REG_DEST[rip]
	xor	esi, esi
	call	PACKET0@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	radeon_ring_write@PLT
	mov	ecx, DWORD PTR [r12]
	mov	esi, 1
	mov	rdi, rbp
	sal	esi, cl
	sub	esi, 1
	call	radeon_ring_write@PLT
	mov	edi, DWORD PTR VAP_INDEX_OFFSET[rip]
	xor	esi, esi
	call	PACKET0@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	radeon_ring_write@PLT
	xor	esi, esi
	mov	rdi, rbp
	call	radeon_ring_write@PLT
	mov	edi, DWORD PTR RB3D_DSTCACHE_CTLSTAT[rip]
	xor	esi, esi
	call	PACKET0@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	radeon_ring_write@PLT
	mov	rdi, rbp
	mov	esi, DWORD PTR RB3D_DC_FLUSH[rip]
	or	esi, DWORD PTR RB3D_DC_FREE[rip]
	call	radeon_ring_write@PLT
	mov	edi, DWORD PTR ZB_ZCACHE_CTLSTAT[rip]
	xor	esi, esi
	call	PACKET0@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	radeon_ring_write@PLT
	mov	rdi, rbp
	mov	esi, DWORD PTR ZC_FLUSH[rip]
	or	esi, DWORD PTR ZC_FREE[rip]
	call	radeon_ring_write@PLT
	mov	edi, DWORD PTR WAIT_UNTIL[rip]
	xor	esi, esi
	call	PACKET0@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	radeon_ring_write@PLT
	mov	rdi, rbp
	mov	esi, DWORD PTR WAIT_2D_IDLECLEAN[rip]
	or	esi, DWORD PTR WAIT_3D_IDLECLEAN[rip]
	call	radeon_ring_write@PLT
	mov	edi, DWORD PTR GB_AA_CONFIG[rip]
	xor	esi, esi
	call	PACKET0@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	radeon_ring_write@PLT
	xor	esi, esi
	mov	rdi, rbp
	call	radeon_ring_write@PLT
	mov	edi, DWORD PTR RB3D_DSTCACHE_CTLSTAT[rip]
	xor	esi, esi
	call	PACKET0@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	radeon_ring_write@PLT
	mov	rdi, rbp
	mov	esi, DWORD PTR RB3D_DC_FLUSH[rip]
	or	esi, DWORD PTR RB3D_DC_FREE[rip]
	call	radeon_ring_write@PLT
	mov	edi, DWORD PTR ZB_ZCACHE_CTLSTAT[rip]
	xor	esi, esi
	call	PACKET0@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	radeon_ring_write@PLT
	mov	rdi, rbp
	mov	esi, DWORD PTR ZC_FLUSH[rip]
	or	esi, DWORD PTR ZC_FREE[rip]
	call	radeon_ring_write@PLT
	mov	edi, DWORD PTR GB_MSPOS0[rip]
	xor	esi, esi
	call	PACKET0@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	radeon_ring_write@PLT
	mov	ecx, DWORD PTR MS_X0_SHIFT[rip]
	mov	esi, ebx
	mov	eax, ebx
	mov	rdi, rbp
	sal	esi, cl
	mov	ecx, DWORD PTR MS_Y0_SHIFT[rip]
	sal	eax, cl
	mov	ecx, DWORD PTR MS_X1_SHIFT[rip]
	or	esi, eax
	mov	eax, ebx
	sal	eax, cl
	mov	ecx, DWORD PTR MS_Y1_SHIFT[rip]
	or	esi, eax
	mov	eax, ebx
	sal	eax, cl
	mov	ecx, DWORD PTR MS_X2_SHIFT[rip]
	or	esi, eax
	mov	eax, ebx
	sal	eax, cl
	mov	ecx, DWORD PTR MS_Y2_SHIFT[rip]
	or	esi, eax
	mov	eax, ebx
	sal	eax, cl
	mov	ecx, DWORD PTR MSBD0_Y_SHIFT[rip]
	or	esi, eax
	mov	eax, ebx
	sal	eax, cl
	mov	ecx, DWORD PTR MSBD0_X_SHIFT[rip]
	or	esi, eax
	mov	eax, ebx
	sal	eax, cl
	or	esi, eax
	call	radeon_ring_write@PLT
	mov	edi, DWORD PTR GB_MSPOS1[rip]
	xor	esi, esi
	call	PACKET0@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	radeon_ring_write@PLT
	mov	ecx, DWORD PTR MS_X3_SHIFT[rip]
	mov	esi, ebx
	mov	eax, ebx
	mov	rdi, rbp
	sal	esi, cl
	mov	ecx, DWORD PTR MS_Y3_SHIFT[rip]
	sal	eax, cl
	mov	ecx, DWORD PTR MS_X4_SHIFT[rip]
	or	esi, eax
	mov	eax, ebx
	sal	eax, cl
	mov	ecx, DWORD PTR MS_Y4_SHIFT[rip]
	or	esi, eax
	mov	eax, ebx
	sal	eax, cl
	mov	ecx, DWORD PTR MS_X5_SHIFT[rip]
	or	esi, eax
	mov	eax, ebx
	sal	eax, cl
	mov	ecx, DWORD PTR MS_Y5_SHIFT[rip]
	or	esi, eax
	mov	eax, ebx
	sal	eax, cl
	mov	ecx, DWORD PTR MSBD1_SHIFT[rip]
	or	esi, eax
	sal	ebx, cl
	or	esi, ebx
	call	radeon_ring_write@PLT
	mov	edi, DWORD PTR GA_ENHANCE[rip]
	xor	esi, esi
	call	PACKET0@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	radeon_ring_write@PLT
	mov	rdi, rbp
	mov	esi, DWORD PTR GA_DEADLOCK_CNTL[rip]
	or	esi, DWORD PTR GA_FASTSYNC_CNTL[rip]
	call	radeon_ring_write@PLT
	mov	edi, DWORD PTR GA_POLY_MODE[rip]
	xor	esi, esi
	call	PACKET0@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	radeon_ring_write@PLT
	mov	rdi, rbp
	mov	esi, DWORD PTR FRONT_PTYPE_TRIANGE[rip]
	or	esi, DWORD PTR BACK_PTYPE_TRIANGE[rip]
	call	radeon_ring_write@PLT
	mov	edi, DWORD PTR GA_ROUND_MODE[rip]
	xor	esi, esi
	call	PACKET0@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	radeon_ring_write@PLT
	mov	rdi, rbp
	mov	esi, DWORD PTR GEOMETRY_ROUND_NEAREST[rip]
	or	esi, DWORD PTR COLOR_ROUND_NEAREST[rip]
	call	radeon_ring_write@PLT
	xor	esi, esi
	mov	edi, 8392
	call	PACKET0@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	radeon_ring_write@PLT
	mov	rdi, rbp
	xor	esi, esi
	call	radeon_ring_write@PLT
	pop	rbx
	.cfi_def_cfa_offset 24
	mov	rsi, rbp
	mov	rdi, r12
	pop	rbp
	.cfi_def_cfa_offset 16
	xor	edx, edx
	pop	r12
	.cfi_def_cfa_offset 8
	jmp	radeon_ring_unlock_commit@PLT
	.cfi_endproc
.LFE0:
	.size	rv515_ring_start, .-rv515_ring_start
	.comm	ZC_FREE,4,4
	.comm	ZC_FLUSH,4,4
	.comm	ZB_ZCACHE_CTLSTAT,4,4
	.comm	WAIT_UNTIL,4,4
	.comm	WAIT_3D_IDLECLEAN,4,4
	.comm	WAIT_2D_IDLECLEAN,4,4
	.comm	VAP_INDEX_OFFSET,4,4
	.comm	RB3D_DSTCACHE_CTLSTAT,4,4
	.comm	RB3D_DC_FREE,4,4
	.comm	RB3D_DC_FLUSH,4,4
	.comm	R500_SU_REG_DEST,4,4
	.comm	R300_PIPE_AUTO_CONFIG,4,4
	.comm	R300_DST_PIPE_CONFIG,4,4
	.comm	MS_Y5_SHIFT,4,4
	.comm	MS_Y4_SHIFT,4,4
	.comm	MS_Y3_SHIFT,4,4
	.comm	MS_Y2_SHIFT,4,4
	.comm	MS_Y1_SHIFT,4,4
	.comm	MS_Y0_SHIFT,4,4
	.comm	MS_X5_SHIFT,4,4
	.comm	MS_X4_SHIFT,4,4
	.comm	MS_X3_SHIFT,4,4
	.comm	MS_X2_SHIFT,4,4
	.comm	MS_X1_SHIFT,4,4
	.comm	MS_X0_SHIFT,4,4
	.comm	MSBD1_SHIFT,4,4
	.comm	MSBD0_Y_SHIFT,4,4
	.comm	MSBD0_X_SHIFT,4,4
	.comm	ISYNC_WAIT_IDLEGUI,4,4
	.comm	ISYNC_CPSCRATCH_IDLEGUI,4,4
	.comm	ISYNC_CNTL,4,4
	.comm	ISYNC_ANY3D_IDLE2D,4,4
	.comm	ISYNC_ANY2D_IDLE3D,4,4
	.comm	GEOMETRY_ROUND_NEAREST,4,4
	.comm	GB_SELECT,4,4
	.comm	GB_MSPOS1,4,4
	.comm	GB_MSPOS0,4,4
	.comm	GB_ENABLE,4,4
	.comm	GB_AA_CONFIG,4,4
	.comm	GA_ROUND_MODE,4,4
	.comm	GA_POLY_MODE,4,4
	.comm	GA_FASTSYNC_CNTL,4,4
	.comm	GA_ENHANCE,4,4
	.comm	GA_DEADLOCK_CNTL,4,4
	.comm	FRONT_PTYPE_TRIANGE,4,4
	.comm	COLOR_ROUND_NEAREST,4,4
	.comm	BACK_PTYPE_TRIANGE,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_rv515.c_rv515_ring_start.c"
	.text
	.align	2
	.global	rv515_ring_start
	.syntax unified
	.arm
	.fpu softvfp
	.type	rv515_ring_start, %function
rv515_ring_start:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	mov	r2, #64
	mov	r7, r0
	mov	r4, r1
	bl	radeon_ring_lock
	subs	r5, r0, #0
	popne	{r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
	ldr	r3, .L5
	mov	r1, r5
	ldr	r0, [r3]
	bl	PACKET0
	mov	r1, r0
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r3, .L5+4
	ldr	r1, .L5+8
	ldr	r2, .L5+12
	ldr	r1, [r1]
	ldr	r3, [r3]
	ldr	r0, .L5+16
	ldr	r2, [r2]
	orr	r3, r3, r1
	ldr	r1, [r0]
	orr	r3, r3, r2
	orr	r1, r3, r1
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r3, .L5+20
	mov	r1, r5
	ldr	r0, [r3]
	bl	PACKET0
	mov	r1, r0
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r3, .L5+24
	ldr	r2, .L5+28
	ldr	r1, [r3]
	ldr	ip, [r2]
	mov	r0, r4
	orr	r1, ip, r1
	bl	radeon_ring_write
	ldr	r0, .L5+32
	mov	r1, r5
	ldr	r0, [r0]
	bl	PACKET0
	mov	r1, r0
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r1, .L5+36
	mov	r0, r4
	ldr	r1, [r1]
	bl	radeon_ring_write
	ldr	r0, .L5+40
	mov	r1, r5
	ldr	r0, [r0]
	bl	PACKET0
	mov	r1, r0
	mov	r0, r4
	bl	radeon_ring_write
	mov	r1, r5
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r0, .L5+44
	mov	r1, r5
	ldr	r0, [r0]
	bl	PACKET0
	mov	r1, r0
	mov	r0, r4
	bl	radeon_ring_write
	mov	r1, r5
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r0, .L5+48
	mov	r1, r5
	ldr	r0, [r0]
	bl	PACKET0
	mov	r1, r0
	mov	r0, r4
	bl	radeon_ring_write
	mvn	ip, #0
	ldr	r1, [r7]
	mov	r0, r4
	mvn	r1, ip, lsl r1
	bl	radeon_ring_write
	ldr	r0, .L5+52
	mov	r1, r5
	ldr	r0, [r0]
	bl	PACKET0
	mov	r1, r0
	mov	r0, r4
	bl	radeon_ring_write
	mov	r1, r5
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r2, .L5+56
	mov	r1, r5
	ldr	r0, [r2]
	bl	PACKET0
	ldr	r10, .L5+60
	ldr	r9, .L5+64
	mov	r1, r0
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r0, [r10]
	ldr	r1, [r9]
	ldr	r8, .L5+68
	orr	r1, r0, r1
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r1, .L5+72
	ldr	fp, .L5+76
	ldr	r0, [r1]
	mov	r1, r5
	bl	PACKET0
	mov	r1, r0
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r0, [r8]
	ldr	r1, [fp]
	mov	r6, #6
	orr	r1, r0, r1
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r3, .L5+20
	mov	r1, r5
	ldr	r0, [r3]
	bl	PACKET0
	mov	r1, r0
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r2, .L5+28
	ldr	r3, .L5+24
	ldr	r1, [r2]
	ldr	r3, [r3]
	mov	r0, r4
	orr	r1, r1, r3
	bl	radeon_ring_write
	ldr	r3, .L5+80
	mov	r1, r5
	ldr	r0, [r3]
	bl	PACKET0
	mov	r1, r0
	mov	r0, r4
	bl	radeon_ring_write
	mov	r1, r5
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r2, .L5+56
	mov	r1, r5
	ldr	r0, [r2]
	bl	PACKET0
	mov	r1, r0
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r3, [r9]
	ldr	r1, [r10]
	mov	r0, r4
	orr	r1, r1, r3
	bl	radeon_ring_write
	ldr	r3, .L5+72
	mov	r1, r5
	ldr	r0, [r3]
	bl	PACKET0
	mov	r1, r0
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r3, [fp]
	ldr	r1, [r8]
	mov	r0, r4
	orr	r1, r1, r3
	bl	radeon_ring_write
	ldr	r3, .L5+84
	mov	r1, r5
	ldr	r0, [r3]
	bl	PACKET0
	mov	r1, r0
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r3, .L5+88
	ldr	r1, .L5+92
	ldr	r3, [r3]
	ldr	r2, .L5+96
	ldr	r0, [r1]
	ldr	r1, .L5+100
	ldr	ip, [r2]
	lsl	r3, r6, r3
	ldr	r2, .L5+104
	orr	r3, r3, r6, lsl r0
	ldr	r0, [r1]
	ldr	r1, .L5+108
	orr	r3, r3, r6, lsl ip
	ldr	ip, [r2]
	ldr	r2, .L5+112
	ldr	r1, [r1]
	orr	r3, r3, r6, lsl r0
	ldr	r0, .L5+116
	orr	r3, r3, r6, lsl ip
	ldr	r2, [r2]
	orr	r3, r3, r6, lsl r1
	ldr	r1, [r0]
	orr	r3, r3, r6, lsl r2
	orr	r1, r3, r6, lsl r1
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r3, .L5+120
	mov	r1, r5
	ldr	r0, [r3]
	bl	PACKET0
	mov	r1, r0
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r3, .L5+124
	ldr	r2, .L5+128
	ldr	r3, [r3]
	ldr	r1, .L5+132
	ldr	ip, [r2]
	ldr	r2, .L5+136
	ldr	r0, [r1]
	lsl	r3, r6, r3
	ldr	r1, .L5+140
	orr	r3, r3, r6, lsl ip
	ldr	ip, [r2]
	ldr	r2, .L5+144
	ldr	r1, [r1]
	orr	r3, r3, r6, lsl r0
	ldr	r0, .L5+148
	orr	r3, r3, r6, lsl ip
	ldr	r2, [r2]
	orr	r3, r3, r6, lsl r1
	ldr	r1, [r0]
	orr	r3, r3, r6, lsl r2
	orr	r1, r3, r6, lsl r1
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r3, .L5+152
	mov	r1, r5
	ldr	r0, [r3]
	bl	PACKET0
	mov	r1, r0
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r2, .L5+156
	ldr	r3, .L5+160
	ldr	r1, [r2]
	ldr	r3, [r3]
	mov	r0, r4
	orr	r1, r1, r3
	bl	radeon_ring_write
	ldr	r3, .L5+164
	mov	r1, r5
	ldr	r0, [r3]
	bl	PACKET0
	mov	r1, r0
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r2, .L5+168
	ldr	r3, .L5+172
	ldr	r1, [r2]
	ldr	r3, [r3]
	mov	r0, r4
	orr	r1, r1, r3
	bl	radeon_ring_write
	ldr	r3, .L5+176
	mov	r1, r5
	ldr	r0, [r3]
	bl	PACKET0
	mov	r1, r0
	mov	r0, r4
	bl	radeon_ring_write
	ldr	r2, .L5+180
	ldr	r3, .L5+184
	ldr	r1, [r2]
	ldr	r3, [r3]
	mov	r0, r4
	orr	r1, r1, r3
	bl	radeon_ring_write
	mov	r1, r5
	ldr	r0, .L5+188
	bl	PACKET0
	mov	r1, r0
	mov	r0, r4
	bl	radeon_ring_write
	mov	r1, r5
	mov	r0, r4
	bl	radeon_ring_write
	mov	r2, r5
	mov	r1, r4
	mov	r0, r7
	pop	{r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	b	radeon_ring_unlock_commit
.L6:
	.align	2
.L5:
	.word	ISYNC_CNTL
	.word	ISYNC_ANY2D_IDLE3D
	.word	ISYNC_ANY3D_IDLE2D
	.word	ISYNC_WAIT_IDLEGUI
	.word	ISYNC_CPSCRATCH_IDLEGUI
	.word	WAIT_UNTIL
	.word	WAIT_3D_IDLECLEAN
	.word	WAIT_2D_IDLECLEAN
	.word	R300_DST_PIPE_CONFIG
	.word	R300_PIPE_AUTO_CONFIG
	.word	GB_SELECT
	.word	GB_ENABLE
	.word	R500_SU_REG_DEST
	.word	VAP_INDEX_OFFSET
	.word	RB3D_DSTCACHE_CTLSTAT
	.word	RB3D_DC_FLUSH
	.word	RB3D_DC_FREE
	.word	ZC_FLUSH
	.word	ZB_ZCACHE_CTLSTAT
	.word	ZC_FREE
	.word	GB_AA_CONFIG
	.word	GB_MSPOS0
	.word	MS_Y0_SHIFT
	.word	MS_X0_SHIFT
	.word	MS_X1_SHIFT
	.word	MS_Y1_SHIFT
	.word	MS_X2_SHIFT
	.word	MS_Y2_SHIFT
	.word	MSBD0_Y_SHIFT
	.word	MSBD0_X_SHIFT
	.word	GB_MSPOS1
	.word	MS_Y3_SHIFT
	.word	MS_X3_SHIFT
	.word	MS_X4_SHIFT
	.word	MS_Y4_SHIFT
	.word	MS_X5_SHIFT
	.word	MS_Y5_SHIFT
	.word	MSBD1_SHIFT
	.word	GA_ENHANCE
	.word	GA_DEADLOCK_CNTL
	.word	GA_FASTSYNC_CNTL
	.word	GA_POLY_MODE
	.word	FRONT_PTYPE_TRIANGE
	.word	BACK_PTYPE_TRIANGE
	.word	GA_ROUND_MODE
	.word	GEOMETRY_ROUND_NEAREST
	.word	COLOR_ROUND_NEAREST
	.word	8392
	.size	rv515_ring_start, .-rv515_ring_start
	.comm	ZC_FREE,4,4
	.comm	ZC_FLUSH,4,4
	.comm	ZB_ZCACHE_CTLSTAT,4,4
	.comm	WAIT_UNTIL,4,4
	.comm	WAIT_3D_IDLECLEAN,4,4
	.comm	WAIT_2D_IDLECLEAN,4,4
	.comm	VAP_INDEX_OFFSET,4,4
	.comm	RB3D_DSTCACHE_CTLSTAT,4,4
	.comm	RB3D_DC_FREE,4,4
	.comm	RB3D_DC_FLUSH,4,4
	.comm	R500_SU_REG_DEST,4,4
	.comm	R300_PIPE_AUTO_CONFIG,4,4
	.comm	R300_DST_PIPE_CONFIG,4,4
	.comm	MS_Y5_SHIFT,4,4
	.comm	MS_Y4_SHIFT,4,4
	.comm	MS_Y3_SHIFT,4,4
	.comm	MS_Y2_SHIFT,4,4
	.comm	MS_Y1_SHIFT,4,4
	.comm	MS_Y0_SHIFT,4,4
	.comm	MS_X5_SHIFT,4,4
	.comm	MS_X4_SHIFT,4,4
	.comm	MS_X3_SHIFT,4,4
	.comm	MS_X2_SHIFT,4,4
	.comm	MS_X1_SHIFT,4,4
	.comm	MS_X0_SHIFT,4,4
	.comm	MSBD1_SHIFT,4,4
	.comm	MSBD0_Y_SHIFT,4,4
	.comm	MSBD0_X_SHIFT,4,4
	.comm	ISYNC_WAIT_IDLEGUI,4,4
	.comm	ISYNC_CPSCRATCH_IDLEGUI,4,4
	.comm	ISYNC_CNTL,4,4
	.comm	ISYNC_ANY3D_IDLE2D,4,4
	.comm	ISYNC_ANY2D_IDLE3D,4,4
	.comm	GEOMETRY_ROUND_NEAREST,4,4
	.comm	GB_SELECT,4,4
	.comm	GB_MSPOS1,4,4
	.comm	GB_MSPOS0,4,4
	.comm	GB_ENABLE,4,4
	.comm	GB_AA_CONFIG,4,4
	.comm	GA_ROUND_MODE,4,4
	.comm	GA_POLY_MODE,4,4
	.comm	GA_FASTSYNC_CNTL,4,4
	.comm	GA_ENHANCE,4,4
	.comm	GA_DEADLOCK_CNTL,4,4
	.comm	FRONT_PTYPE_TRIANGE,4,4
	.comm	COLOR_ROUND_NEAREST,4,4
	.comm	BACK_PTYPE_TRIANGE,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
