	.file	"extr_gfx_v10_0.c_gfx_v10_0_ring_emit_fence_kiq.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	gfx_v10_0_ring_emit_fence_kiq, @function
gfx_v10_0_ring_emit_fence_kiq:
.LFB0:
	.cfi_startproc
	endbr64
	push	r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	mov	r14d, edx
	push	r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	mov	r13d, esi
	push	r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	mov	r12d, ecx
	push	rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	mov	rbp, rdi
	mov	edi, DWORD PTR AMDGPU_FENCE_FLAG_64BIT[rip]
	push	rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	and	edi, ecx
	call	BUG_ON@PLT
	mov	edi, DWORD PTR PACKET3_WRITE_DATA[rip]
	mov	esi, 3
	call	PACKET3@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	amdgpu_ring_write@PLT
	xor	edi, edi
	call	WRITE_DATA_ENGINE_SEL@PLT
	mov	edi, 5
	mov	ebx, eax
	call	WRITE_DATA_DST_SEL@PLT
	mov	esi, DWORD PTR WR_CONFIRM[rip]
	mov	rdi, rbp
	or	ebx, eax
	or	esi, ebx
	call	amdgpu_ring_write@PLT
	mov	edi, r13d
	call	lower_32_bits@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	amdgpu_ring_write@PLT
	mov	edi, r13d
	call	upper_32_bits@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	amdgpu_ring_write@PLT
	mov	edi, r14d
	call	lower_32_bits@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	amdgpu_ring_write@PLT
	test	DWORD PTR AMDGPU_FENCE_FLAG_INT[rip], r12d
	jne	.L5
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	pop	rbp
	.cfi_def_cfa_offset 32
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L5:
	.cfi_restore_state
	mov	edi, DWORD PTR PACKET3_WRITE_DATA[rip]
	mov	esi, 3
	call	PACKET3@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	amdgpu_ring_write@PLT
	xor	edi, edi
	call	WRITE_DATA_ENGINE_SEL@PLT
	xor	edi, edi
	mov	ebx, eax
	call	WRITE_DATA_DST_SEL@PLT
	mov	esi, DWORD PTR WR_CONFIRM[rip]
	mov	rdi, rbp
	or	ebx, eax
	or	esi, ebx
	call	amdgpu_ring_write@PLT
	mov	edx, DWORD PTR mmCPC_INT_STATUS[rip]
	mov	edi, DWORD PTR GC[rip]
	xor	esi, esi
	call	SOC15_REG_OFFSET@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	amdgpu_ring_write@PLT
	mov	rdi, rbp
	xor	esi, esi
	call	amdgpu_ring_write@PLT
	pop	rbx
	.cfi_def_cfa_offset 40
	mov	rdi, rbp
	mov	esi, 536870912
	pop	rbp
	.cfi_def_cfa_offset 32
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	jmp	amdgpu_ring_write@PLT
	.cfi_endproc
.LFE0:
	.size	gfx_v10_0_ring_emit_fence_kiq, .-gfx_v10_0_ring_emit_fence_kiq
	.comm	mmCPC_INT_STATUS,4,4
	.comm	WR_CONFIRM,4,4
	.comm	PACKET3_WRITE_DATA,4,4
	.comm	GC,4,4
	.comm	AMDGPU_FENCE_FLAG_INT,4,4
	.comm	AMDGPU_FENCE_FLAG_64BIT,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_gfx_v10_0.c_gfx_v10_0_ring_emit_fence_kiq.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	gfx_v10_0_ring_emit_fence_kiq, %function
gfx_v10_0_ring_emit_fence_kiq:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, lr}
	mov	r6, r3
	ldr	r3, .L5
	ldr	r9, .L5+4
	ldr	r3, [r3]
	mov	r4, r0
	and	r0, r6, r3
	mov	r8, r2
	mov	r7, r1
	bl	BUG_ON
	mov	r1, #3
	ldr	r0, [r9]
	bl	PACKET3
	mov	r1, r0
	mov	r0, r4
	bl	amdgpu_ring_write
	mov	r0, #0
	bl	WRITE_DATA_ENGINE_SEL
	mov	r5, r0
	mov	r0, #5
	bl	WRITE_DATA_DST_SEL
	ldr	r10, .L5+8
	orr	r5, r5, r0
	ldr	r1, [r10]
	mov	r0, r4
	orr	r1, r5, r1
	bl	amdgpu_ring_write
	mov	r0, r7
	bl	lower_32_bits
	mov	r1, r0
	mov	r0, r4
	bl	amdgpu_ring_write
	mov	r0, r7
	bl	upper_32_bits
	mov	r1, r0
	mov	r0, r4
	bl	amdgpu_ring_write
	mov	r0, r8
	bl	lower_32_bits
	mov	r1, r0
	mov	r0, r4
	bl	amdgpu_ring_write
	ldr	r3, .L5+12
	ldr	r3, [r3]
	tst	r6, r3
	popeq	{r4, r5, r6, r7, r8, r9, r10, pc}
	mov	r1, #3
	ldr	r0, [r9]
	bl	PACKET3
	mov	r1, r0
	mov	r0, r4
	bl	amdgpu_ring_write
	mov	r0, #0
	bl	WRITE_DATA_ENGINE_SEL
	mov	r5, r0
	mov	r0, #0
	bl	WRITE_DATA_DST_SEL
	ldr	r1, [r10]
	orr	r5, r5, r0
	orr	r1, r5, r1
	mov	r0, r4
	bl	amdgpu_ring_write
	ldr	r3, .L5+16
	ldr	r2, .L5+20
	ldr	r0, [r3]
	ldr	r2, [r2]
	mov	r1, #0
	bl	SOC15_REG_OFFSET
	mov	r1, r0
	mov	r0, r4
	bl	amdgpu_ring_write
	mov	r1, #0
	mov	r0, r4
	bl	amdgpu_ring_write
	mov	r0, r4
	pop	{r4, r5, r6, r7, r8, r9, r10, lr}
	mov	r1, #536870912
	b	amdgpu_ring_write
.L6:
	.align	2
.L5:
	.word	AMDGPU_FENCE_FLAG_64BIT
	.word	PACKET3_WRITE_DATA
	.word	WR_CONFIRM
	.word	AMDGPU_FENCE_FLAG_INT
	.word	GC
	.word	mmCPC_INT_STATUS
	.size	gfx_v10_0_ring_emit_fence_kiq, .-gfx_v10_0_ring_emit_fence_kiq
	.comm	mmCPC_INT_STATUS,4,4
	.comm	WR_CONFIRM,4,4
	.comm	PACKET3_WRITE_DATA,4,4
	.comm	GC,4,4
	.comm	AMDGPU_FENCE_FLAG_INT,4,4
	.comm	AMDGPU_FENCE_FLAG_64BIT,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
