	.file	"extr_gfx_v6_0.c_gfx_v6_0_rlc_resume.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	gfx_v6_0_rlc_resume, @function
gfx_v6_0_rlc_resume:
.LFB0:
	.cfi_startproc
	endbr64
	cmp	QWORD PTR 8[rdi], 0
	je	.L11
	push	r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	push	r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	push	r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	mov	r12, rdi
	push	rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	push	rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	mov	rax, QWORD PTR [rdi]
	call	[QWORD PTR 16[rax]]
	mov	rax, QWORD PTR [r12]
	mov	rdi, r12
	call	[QWORD PTR 8[rax]]
	mov	rdi, r12
	call	gfx_v6_0_init_pg@PLT
	mov	rdi, r12
	call	gfx_v6_0_init_cg@PLT
	mov	edi, DWORD PTR mmRLC_RL_BASE[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	edi, DWORD PTR mmRLC_RL_SIZE[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	edi, DWORD PTR mmRLC_LB_CNTL[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	edi, DWORD PTR mmRLC_LB_CNTR_MAX[rip]
	mov	esi, -1
	call	WREG32@PLT
	mov	edi, DWORD PTR mmRLC_LB_CNTR_INIT[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	edi, DWORD PTR mmRLC_LB_INIT_CU_MASK[rip]
	mov	esi, -1
	call	WREG32@PLT
	mov	edi, DWORD PTR mmRLC_MC_CNTL[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	edi, DWORD PTR mmRLC_UCODE_CNTL[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	rax, QWORD PTR 8[r12]
	mov	r14, QWORD PTR [rax]
	mov	edi, DWORD PTR 4[r14]
	call	le32_to_cpu@PLT
	mov	edi, DWORD PTR [r14]
	test	eax, eax
	lea	r13d, 3[rax]
	mov	ebx, eax
	cmovns	r13d, eax
	mov	rax, QWORD PTR 8[r12]
	mov	rbp, QWORD PTR [rax]
	sar	r13d, 2
	call	le32_to_cpu@PLT
	mov	rdi, r14
	cdqe
	add	rbp, rax
	call	amdgpu_ucode_print_rlc_hdr@PLT
	cmp	ebx, 3
	jle	.L4
	xor	ebx, ebx
	.p2align 4,,10
	.p2align 3
.L5:
	mov	edi, DWORD PTR mmRLC_UCODE_ADDR[rip]
	mov	esi, ebx
	add	ebx, 1
	call	WREG32@PLT
	mov	edi, ebp
	add	rbp, 4
	call	le32_to_cpup@PLT
	mov	edi, DWORD PTR mmRLC_UCODE_DATA[rip]
	mov	esi, eax
	call	WREG32@PLT
	cmp	r13d, ebx
	jg	.L5
.L4:
	mov	edi, DWORD PTR mmRLC_UCODE_ADDR[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	rdi, r12
	call	gfx_v6_0_lbpw_supported@PLT
	mov	rdi, r12
	mov	esi, eax
	call	gfx_v6_0_enable_lbpw@PLT
	mov	rax, QWORD PTR [r12]
	mov	rdi, r12
	call	[QWORD PTR [rax]]
	pop	rbx
	.cfi_def_cfa_offset 40
	xor	eax, eax
	pop	rbp
	.cfi_def_cfa_offset 32
	pop	r12
	.cfi_def_cfa_offset 24
	pop	r13
	.cfi_def_cfa_offset 16
	pop	r14
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L11:
	.cfi_restore 3
	.cfi_restore 6
	.cfi_restore 12
	.cfi_restore 13
	.cfi_restore 14
	mov	eax, DWORD PTR EINVAL[rip]
	neg	eax
	ret
	.cfi_endproc
.LFE0:
	.size	gfx_v6_0_rlc_resume, .-gfx_v6_0_rlc_resume
	.comm	mmRLC_UCODE_DATA,4,4
	.comm	mmRLC_UCODE_CNTL,4,4
	.comm	mmRLC_UCODE_ADDR,4,4
	.comm	mmRLC_RL_SIZE,4,4
	.comm	mmRLC_RL_BASE,4,4
	.comm	mmRLC_MC_CNTL,4,4
	.comm	mmRLC_LB_INIT_CU_MASK,4,4
	.comm	mmRLC_LB_CNTR_MAX,4,4
	.comm	mmRLC_LB_CNTR_INIT,4,4
	.comm	mmRLC_LB_CNTL,4,4
	.comm	EINVAL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_gfx_v6_0.c_gfx_v6_0_rlc_resume.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	gfx_v6_0_rlc_resume, %function
gfx_v6_0_rlc_resume:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	ldr	r3, [r0, #4]
	cmp	r3, #0
	beq	.L13
	push	{r4, r5, r6, r7, r8, r9, r10, lr}
	mov	r7, r0
	ldr	r3, [r0]
	ldr	r3, [r3, #8]
	blx	r3
	ldr	r3, [r7]
	mov	r0, r7
	ldr	r3, [r3, #4]
	blx	r3
	mov	r0, r7
	bl	gfx_v6_0_init_pg
	mov	r0, r7
	bl	gfx_v6_0_init_cg
	ldr	r3, .L14
	mov	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L14+4
	mov	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L14+8
	mov	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L14+12
	mvn	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L14+16
	mov	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L14+20
	mvn	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L14+24
	mov	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L14+28
	mov	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, [r7, #4]
	ldr	r6, [r3]
	ldr	r0, [r6, #4]
	bl	le32_to_cpu
	ldr	r3, [r7, #4]
	cmp	r0, #0
	add	r8, r0, #3
	mov	r4, r0
	movge	r8, r0
	ldr	r0, [r6]
	ldr	r5, [r3]
	bl	le32_to_cpu
	mov	r3, r0
	mov	r0, r6
	add	r5, r5, r3
	bl	amdgpu_ucode_print_rlc_hdr
	cmp	r4, #3
	ldrle	r9, .L14+32
	asr	r8, r8, #2
	ble	.L4
	mov	r4, #0
	ldr	r9, .L14+32
	ldr	r10, .L14+36
.L5:
	mov	r1, r4
	ldr	r0, [r9]
	bl	WREG32
	mov	r0, r5
	ldr	r6, [r10]
	bl	le32_to_cpup
	add	r4, r4, #1
	mov	r1, r0
	mov	r0, r6
	bl	WREG32
	cmp	r8, r4
	add	r5, r5, #4
	bgt	.L5
.L4:
	mov	r1, #0
	ldr	r0, [r9]
	bl	WREG32
	mov	r0, r7
	bl	gfx_v6_0_lbpw_supported
	mov	r1, r0
	mov	r0, r7
	bl	gfx_v6_0_enable_lbpw
	ldr	r3, [r7]
	mov	r0, r7
	ldr	r3, [r3]
	blx	r3
	mov	r0, #0
	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
.L13:
	ldr	r3, .L14+40
	ldr	r0, [r3]
	rsb	r0, r0, #0
	bx	lr
.L15:
	.align	2
.L14:
	.word	mmRLC_RL_BASE
	.word	mmRLC_RL_SIZE
	.word	mmRLC_LB_CNTL
	.word	mmRLC_LB_CNTR_MAX
	.word	mmRLC_LB_CNTR_INIT
	.word	mmRLC_LB_INIT_CU_MASK
	.word	mmRLC_MC_CNTL
	.word	mmRLC_UCODE_CNTL
	.word	mmRLC_UCODE_ADDR
	.word	mmRLC_UCODE_DATA
	.word	EINVAL
	.size	gfx_v6_0_rlc_resume, .-gfx_v6_0_rlc_resume
	.comm	mmRLC_UCODE_DATA,4,4
	.comm	mmRLC_UCODE_CNTL,4,4
	.comm	mmRLC_UCODE_ADDR,4,4
	.comm	mmRLC_RL_SIZE,4,4
	.comm	mmRLC_RL_BASE,4,4
	.comm	mmRLC_MC_CNTL,4,4
	.comm	mmRLC_LB_INIT_CU_MASK,4,4
	.comm	mmRLC_LB_CNTR_MAX,4,4
	.comm	mmRLC_LB_CNTR_INIT,4,4
	.comm	mmRLC_LB_CNTL,4,4
	.comm	EINVAL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
