	.file	"extr_mvpp2_prs.c_mvpp2_prs_sram_shift_set.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	mvpp2_prs_sram_shift_set, @function
mvpp2_prs_sram_shift_set:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	mov	r12d, edx
	mov	edx, 1
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	mov	ebx, esi
	sub	rsp, 8
	.cfi_def_cfa_offset 48
	mov	esi, DWORD PTR MVPP2_PRS_SRAM_SHIFT_SIGN_BIT[rip]
	test	ebx, ebx
	js	.L6
	call	mvpp2_prs_sram_bits_clear@PLT
.L3:
	mov	edi, DWORD PTR MVPP2_PRS_SRAM_SHIFT_OFFS[rip]
	mov	r13, QWORD PTR 0[rbp]
	call	MVPP2_BIT_TO_WORD@PLT
	mov	rdx, QWORD PTR 0[rbp]
	and	ebx, DWORD PTR MVPP2_PRS_SRAM_SHIFT_MASK[rip]
	mov	rdi, rbp
	or	ebx, DWORD PTR 0[r13+rax*4]
	mov	DWORD PTR [rdx+rax*4], ebx
	mov	edx, DWORD PTR MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK[rip]
	mov	esi, DWORD PTR MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS[rip]
	call	mvpp2_prs_sram_bits_clear@PLT
	mov	esi, DWORD PTR MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	mvpp2_prs_sram_bits_set@PLT
	mov	esi, DWORD PTR MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS[rip]
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	rdi, rbp
	pop	rbx
	.cfi_def_cfa_offset 32
	mov	edx, 1
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	jmp	mvpp2_prs_sram_bits_clear@PLT
	.p2align 4,,10
	.p2align 3
.L6:
	.cfi_restore_state
	call	mvpp2_prs_sram_bits_set@PLT
	neg	ebx
	jmp	.L3
	.cfi_endproc
.LFE0:
	.size	mvpp2_prs_sram_shift_set, .-mvpp2_prs_sram_shift_set
	.comm	MVPP2_PRS_SRAM_SHIFT_SIGN_BIT,4,4
	.comm	MVPP2_PRS_SRAM_SHIFT_OFFS,4,4
	.comm	MVPP2_PRS_SRAM_SHIFT_MASK,4,4
	.comm	MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,4,4
	.comm	MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK,4,4
	.comm	MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_mvpp2_prs.c_mvpp2_prs_sram_shift_set.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	mvpp2_prs_sram_shift_set, %function
mvpp2_prs_sram_shift_set:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	ldr	r3, .L7
	push	{r4, r5, r6, r7, r8, lr}
	subs	r5, r1, #0
	mov	r6, r2
	mov	r4, r0
	mov	r2, #1
	ldr	r1, [r3]
	blt	.L6
	bl	mvpp2_prs_sram_bits_clear
.L3:
	ldr	r3, .L7+4
	ldr	r7, [r4]
	ldr	r0, [r3]
	bl	MVPP2_BIT_TO_WORD
	ldr	r2, .L7+8
	ldr	r3, [r7, r0, lsl #2]
	ldr	r1, [r2]
	ldr	r2, [r4]
	and	r1, r1, r5
	orr	r1, r3, r1
	ldr	r5, .L7+12
	ldr	r3, .L7+16
	str	r1, [r2, r0, lsl #2]
	ldr	r2, [r3]
	ldr	r1, [r5]
	mov	r0, r4
	bl	mvpp2_prs_sram_bits_clear
	mov	r2, r6
	ldr	r1, [r5]
	mov	r0, r4
	bl	mvpp2_prs_sram_bits_set
	ldr	r3, .L7+20
	mov	r0, r4
	pop	{r4, r5, r6, r7, r8, lr}
	mov	r2, #1
	ldr	r1, [r3]
	b	mvpp2_prs_sram_bits_clear
.L6:
	rsb	r5, r5, #0
	bl	mvpp2_prs_sram_bits_set
	b	.L3
.L8:
	.align	2
.L7:
	.word	MVPP2_PRS_SRAM_SHIFT_SIGN_BIT
	.word	MVPP2_PRS_SRAM_SHIFT_OFFS
	.word	MVPP2_PRS_SRAM_SHIFT_MASK
	.word	MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS
	.word	MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK
	.word	MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS
	.size	mvpp2_prs_sram_shift_set, .-mvpp2_prs_sram_shift_set
	.comm	MVPP2_PRS_SRAM_SHIFT_SIGN_BIT,4,4
	.comm	MVPP2_PRS_SRAM_SHIFT_OFFS,4,4
	.comm	MVPP2_PRS_SRAM_SHIFT_MASK,4,4
	.comm	MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,4,4
	.comm	MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK,4,4
	.comm	MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
