	.file	"extr_twl_vreg.c_twl_vreg_disable_regulator.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	twl_vreg_disable_regulator, @function
twl_vreg_disable_regulator:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	mov	r13, rsi
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	sub	rsp, 24
	.cfi_def_cfa_offset 64
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 8[rsp], rax
	xor	eax, eax
	call	TWL_VREG_ASSERT_LOCKED@PLT
	lea	rdi, 4[rbp]
	call	sx_xlocked@PLT
	mov	ebx, eax
	test	eax, eax
	je	.L13
.L2:
	mov	edi, DWORD PTR 0[rbp]
	call	twl_is_4030@PLT
	test	rax, rax
	je	.L3
	mov	edx, DWORD PTR TWL_VREG_GRP[rip]
	lea	rcx, 4[rsp]
	mov	rsi, r13
	mov	rdi, rbp
	call	twl_vreg_read_1@PLT
	mov	r12d, eax
	test	eax, eax
	je	.L14
.L4:
	test	ebx, ebx
	je	.L15
.L1:
	mov	rax, QWORD PTR 8[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L16
	add	rsp, 24
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	eax, r12d
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L3:
	.cfi_restore_state
	mov	edi, DWORD PTR 0[rbp]
	call	twl_is_6030@PLT
	test	rax, rax
	je	.L5
	mov	edi, DWORD PTR 0[rbp]
	call	twl_is_6030@PLT
	xor	ecx, ecx
	test	rax, rax
	jne	.L17
.L7:
	mov	edx, DWORD PTR TWL_VREG_STATE[rip]
	mov	rsi, r13
	mov	rdi, rbp
	mov	DWORD PTR 4[rsp], eax
	call	twl_vreg_write_1@PLT
	mov	r12d, eax
	test	ebx, ebx
	jne	.L1
.L15:
	mov	rdi, rbp
	call	TWL_VREG_LOCK_DOWNGRADE@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L5:
	mov	edi, DWORD PTR 0[rbp]
	xor	r12d, r12d
	call	twl_is_6025@PLT
	test	rax, rax
	je	.L4
	mov	edi, DWORD PTR 0[rbp]
	call	twl_is_6030@PLT
	xor	ecx, ecx
	test	rax, rax
	je	.L7
	jmp	.L17
	.p2align 4,,10
	.p2align 3
.L14:
	mov	ecx, DWORD PTR TWL4030_P1_GRP[rip]
	mov	edx, DWORD PTR TWL_VREG_GRP[rip]
	mov	rsi, r13
	mov	rdi, rbp
	or	ecx, DWORD PTR TWL4030_P2_GRP[rip]
	or	ecx, DWORD PTR TWL4030_P3_GRP[rip]
	not	ecx
	and	ecx, DWORD PTR 4[rsp]
	mov	DWORD PTR 4[rsp], ecx
	call	twl_vreg_write_1@PLT
	mov	r12d, eax
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L13:
	mov	rdi, rbp
	call	TWL_VREG_LOCK_UPGRADE@PLT
	jmp	.L2
	.p2align 4,,10
	.p2align 3
.L17:
	mov	eax, DWORD PTR TWL6030_P1_GRP[rip]
	or	eax, DWORD PTR TWL6030_P2_GRP[rip]
	or	eax, DWORD PTR TWL6030_P3_GRP[rip]
	mov	ecx, eax
	sal	ecx, 5
	jmp	.L7
.L16:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	twl_vreg_disable_regulator, .-twl_vreg_disable_regulator
	.comm	TWL_VREG_STATE,4,4
	.comm	TWL_VREG_GRP,4,4
	.comm	TWL6030_P3_GRP,4,4
	.comm	TWL6030_P2_GRP,4,4
	.comm	TWL6030_P1_GRP,4,4
	.comm	TWL4030_P3_GRP,4,4
	.comm	TWL4030_P2_GRP,4,4
	.comm	TWL4030_P1_GRP,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_twl_vreg.c_twl_vreg_disable_regulator.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	twl_vreg_disable_regulator, %function
twl_vreg_disable_regulator:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	mov	r4, r0
	ldr	r3, .L18
	sub	sp, sp, #8
	mov	r7, r1
	ldr	r3, [r3]
	str	r3, [sp, #4]
	mov	r3,#0
	bl	TWL_VREG_ASSERT_LOCKED
	add	r0, r4, #4
	bl	sx_xlocked
	subs	r6, r0, #0
	beq	.L13
.L2:
	ldr	r0, [r4]
	bl	twl_is_4030
	cmp	r0, #0
	beq	.L3
	ldr	r8, .L18+4
	mov	r3, sp
	mov	r1, r7
	mov	r0, r4
	ldr	r2, [r8]
	bl	twl_vreg_read_1
	subs	r5, r0, #0
	beq	.L14
.L4:
	cmp	r6, #0
	beq	.L15
.L1:
	ldr	r3, .L18
	ldr	r2, [r3]
	ldr	r3, [sp, #4]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L16
	mov	r0, r5
	add	sp, sp, #8
	@ sp needed
	pop	{r4, r5, r6, r7, r8, pc}
.L3:
	ldr	r0, [r4]
	bl	twl_is_6030
	cmp	r0, #0
	beq	.L5
.L8:
	ldr	r0, [r4]
	bl	twl_is_6030
	subs	ip, r0, #0
	moveq	r3, ip
	bne	.L17
.L7:
	ldr	r2, .L18+8
	mov	r1, r7
	mov	r0, r4
	ldr	r2, [r2]
	str	ip, [sp]
	bl	twl_vreg_write_1
	cmp	r6, #0
	mov	r5, r0
	bne	.L1
.L15:
	mov	r0, r4
	bl	TWL_VREG_LOCK_DOWNGRADE
	b	.L1
.L5:
	ldr	r0, [r4]
	bl	twl_is_6025
	subs	r5, r0, #0
	bne	.L8
	b	.L4
.L14:
	ldr	r3, .L18+12
	ldr	r2, .L18+16
	ldr	r1, .L18+20
	ldr	r2, [r2]
	ldr	r3, [r3]
	ldr	r1, [r1]
	orr	r3, r3, r2
	ldr	r2, [sp]
	orr	r3, r3, r1
	bic	r3, r2, r3
	mov	r1, r7
	mov	r0, r4
	ldr	r2, [r8]
	str	r3, [sp]
	bl	twl_vreg_write_1
	mov	r5, r0
	b	.L4
.L13:
	mov	r0, r4
	bl	TWL_VREG_LOCK_UPGRADE
	b	.L2
.L17:
	ldr	r1, .L18+24
	ldr	r3, .L18+28
	ldr	r2, .L18+32
	ldr	r3, [r3]
	ldr	ip, [r1]
	ldr	r0, [r2]
	orr	ip, ip, r3
	orr	ip, ip, r0
	lsl	r3, ip, #5
	b	.L7
.L16:
	bl	__stack_chk_fail
.L19:
	.align	2
.L18:
	.word	.LC0
	.word	TWL_VREG_GRP
	.word	TWL_VREG_STATE
	.word	TWL4030_P1_GRP
	.word	TWL4030_P2_GRP
	.word	TWL4030_P3_GRP
	.word	TWL6030_P1_GRP
	.word	TWL6030_P2_GRP
	.word	TWL6030_P3_GRP
	.size	twl_vreg_disable_regulator, .-twl_vreg_disable_regulator
	.comm	TWL_VREG_STATE,4,4
	.comm	TWL_VREG_GRP,4,4
	.comm	TWL6030_P3_GRP,4,4
	.comm	TWL6030_P2_GRP,4,4
	.comm	TWL6030_P1_GRP,4,4
	.comm	TWL4030_P3_GRP,4,4
	.comm	TWL4030_P2_GRP,4,4
	.comm	TWL4030_P1_GRP,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
