	.file	"extr_ddk750_mode.c_programModeRegisters.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	programModeRegisters, @function
programModeRegisters:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	push	rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	mov	rbp, rdi
	mov	rdi, rsi
	push	rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	mov	rax, QWORD PTR [rsi]
	cmp	rax, QWORD PTR SECONDARY_PLL[rip]
	je	.L16
	cmp	rax, QWORD PTR PRIMARY_PLL[rip]
	jne	.L12
	call	sm750_format_pll_reg@PLT
	mov	edi, DWORD PTR PANEL_PLL_CTRL[rip]
	mov	esi, eax
	call	poke32@PLT
	mov	eax, DWORD PTR 0[rbp]
	mov	edx, DWORD PTR 4[rbp]
	mov	ecx, DWORD PTR PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT[rip]
	mov	edi, DWORD PTR PANEL_HORIZONTAL_TOTAL[rip]
	lea	esi, -1[rax]
	mov	eax, DWORD PTR PANEL_HORIZONTAL_TOTAL_TOTAL_MASK[rip]
	sal	esi, cl
	and	eax, esi
	lea	esi, -1[rdx]
	and	esi, DWORD PTR PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK[rip]
	or	esi, eax
	call	poke32@PLT
	mov	ecx, DWORD PTR PANEL_HORIZONTAL_SYNC_WIDTH_SHIFT[rip]
	mov	esi, DWORD PTR 8[rbp]
	mov	eax, DWORD PTR 12[rbp]
	mov	edi, DWORD PTR PANEL_HORIZONTAL_SYNC[rip]
	sal	esi, cl
	and	esi, DWORD PTR PANEL_HORIZONTAL_SYNC_WIDTH_MASK[rip]
	sub	eax, 1
	and	eax, DWORD PTR PANEL_HORIZONTAL_SYNC_START_MASK[rip]
	or	esi, eax
	call	poke32@PLT
	mov	eax, DWORD PTR 16[rbp]
	mov	ecx, DWORD PTR PANEL_VERTICAL_TOTAL_TOTAL_SHIFT[rip]
	mov	edi, DWORD PTR PANEL_VERTICAL_TOTAL[rip]
	lea	esi, -1[rax]
	mov	eax, DWORD PTR 20[rbp]
	sal	esi, cl
	and	esi, DWORD PTR PANEL_VERTICAL_TOTAL_TOTAL_MASK[rip]
	sub	eax, 1
	and	eax, DWORD PTR PANEL_VERTICAL_TOTAL_DISPLAY_END_MASK[rip]
	or	esi, eax
	call	poke32@PLT
	mov	ecx, DWORD PTR PANEL_VERTICAL_SYNC_HEIGHT_SHIFT[rip]
	mov	esi, DWORD PTR 24[rbp]
	mov	eax, DWORD PTR 28[rbp]
	mov	edi, DWORD PTR PANEL_VERTICAL_SYNC[rip]
	sal	esi, cl
	and	esi, DWORD PTR PANEL_VERTICAL_SYNC_HEIGHT_MASK[rip]
	sub	eax, 1
	and	eax, DWORD PTR PANEL_VERTICAL_SYNC_START_MASK[rip]
	or	esi, eax
	call	poke32@PLT
	mov	ebx, DWORD PTR DISPLAY_CTRL_TIMING[rip]
	or	ebx, DWORD PTR DISPLAY_CTRL_PLANE[rip]
	cmp	QWORD PTR 48[rbp], 0
	je	.L7
	or	ebx, DWORD PTR DISPLAY_CTRL_VSYNC_PHASE[rip]
.L7:
	cmp	QWORD PTR 40[rbp], 0
	je	.L8
	or	ebx, DWORD PTR DISPLAY_CTRL_HSYNC_PHASE[rip]
.L8:
	cmp	QWORD PTR 32[rbp], 0
	jne	.L17
.L9:
	mov	edi, DWORD PTR PANEL_DISPLAY_CTRL[rip]
	mov	eax, DWORD PTR PANEL_DISPLAY_CTRL_RESERVED_MASK[rip]
	or	eax, DWORD PTR PANEL_DISPLAY_CTRL_VSYNC[rip]
	mov	r12d, eax
	call	peek32@PLT
	mov	edi, DWORD PTR PANEL_DISPLAY_CTRL[rip]
	mov	ebp, r12d
	mov	r8d, eax
	mov	eax, DWORD PTR DISPLAY_CTRL_CLOCK_PHASE[rip]
	or	eax, DWORD PTR DISPLAY_CTRL_VSYNC_PHASE[rip]
	not	ebp
	or	eax, DWORD PTR DISPLAY_CTRL_HSYNC_PHASE[rip]
	or	eax, DWORD PTR DISPLAY_CTRL_TIMING[rip]
	or	eax, DWORD PTR DISPLAY_CTRL_PLANE[rip]
	or	eax, r12d
	mov	r12d, 1001
	not	eax
	and	eax, r8d
	or	ebx, eax
	mov	esi, ebx
	call	poke32@PLT
	jmp	.L10
	.p2align 4,,10
	.p2align 3
.L11:
	sub	r12d, 1
	je	.L13
	mov	edi, DWORD PTR PANEL_DISPLAY_CTRL[rip]
	mov	esi, ebx
	call	poke32@PLT
.L10:
	mov	edi, DWORD PTR PANEL_DISPLAY_CTRL[rip]
	call	peek32@PLT
	and	eax, ebp
	cmp	ebx, eax
	jne	.L11
.L13:
	xor	eax, eax
.L1:
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L17:
	.cfi_restore_state
	or	ebx, DWORD PTR DISPLAY_CTRL_CLOCK_PHASE[rip]
	jmp	.L9
	.p2align 4,,10
	.p2align 3
.L16:
	call	sm750_format_pll_reg@PLT
	mov	edi, DWORD PTR CRT_PLL_CTRL[rip]
	mov	esi, eax
	call	poke32@PLT
	mov	eax, DWORD PTR 0[rbp]
	mov	edx, DWORD PTR 4[rbp]
	mov	ecx, DWORD PTR CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT[rip]
	mov	edi, DWORD PTR CRT_HORIZONTAL_TOTAL[rip]
	lea	esi, -1[rax]
	mov	eax, DWORD PTR CRT_HORIZONTAL_TOTAL_TOTAL_MASK[rip]
	sal	esi, cl
	and	eax, esi
	lea	esi, -1[rdx]
	and	esi, DWORD PTR CRT_HORIZONTAL_TOTAL_DISPLAY_END_MASK[rip]
	or	esi, eax
	call	poke32@PLT
	mov	ecx, DWORD PTR CRT_HORIZONTAL_SYNC_WIDTH_SHIFT[rip]
	mov	esi, DWORD PTR 8[rbp]
	mov	edx, DWORD PTR 12[rbp]
	mov	eax, DWORD PTR CRT_HORIZONTAL_SYNC_WIDTH_MASK[rip]
	sal	esi, cl
	mov	edi, DWORD PTR CRT_HORIZONTAL_SYNC[rip]
	and	eax, esi
	lea	esi, -1[rdx]
	and	esi, DWORD PTR CRT_HORIZONTAL_SYNC_START_MASK[rip]
	or	esi, eax
	call	poke32@PLT
	mov	eax, DWORD PTR 16[rbp]
	mov	edx, DWORD PTR 20[rbp]
	mov	ecx, DWORD PTR CRT_VERTICAL_TOTAL_TOTAL_SHIFT[rip]
	mov	edi, DWORD PTR CRT_VERTICAL_TOTAL[rip]
	lea	esi, -1[rax]
	mov	eax, DWORD PTR CRT_VERTICAL_TOTAL_TOTAL_MASK[rip]
	sal	esi, cl
	and	eax, esi
	lea	esi, -1[rdx]
	and	esi, DWORD PTR CRT_VERTICAL_TOTAL_DISPLAY_END_MASK[rip]
	or	esi, eax
	call	poke32@PLT
	mov	ecx, DWORD PTR CRT_VERTICAL_SYNC_HEIGHT_SHIFT[rip]
	mov	esi, DWORD PTR 24[rbp]
	mov	eax, DWORD PTR CRT_VERTICAL_SYNC_HEIGHT_MASK[rip]
	mov	edx, DWORD PTR 28[rbp]
	sal	esi, cl
	mov	edi, DWORD PTR CRT_VERTICAL_SYNC[rip]
	and	eax, esi
	lea	esi, -1[rdx]
	and	esi, DWORD PTR CRT_VERTICAL_SYNC_START_MASK[rip]
	or	esi, eax
	call	poke32@PLT
	mov	esi, DWORD PTR DISPLAY_CTRL_TIMING[rip]
	or	esi, DWORD PTR DISPLAY_CTRL_PLANE[rip]
	cmp	QWORD PTR 48[rbp], 0
	mov	r12d, esi
	je	.L3
	or	r12d, DWORD PTR DISPLAY_CTRL_VSYNC_PHASE[rip]
.L3:
	cmp	QWORD PTR 40[rbp], 0
	je	.L4
	or	r12d, DWORD PTR DISPLAY_CTRL_HSYNC_PHASE[rip]
.L4:
	xor	eax, eax
	call	sm750_get_chip_type@PLT
	cmp	rax, QWORD PTR SM750LE[rip]
	je	.L18
	mov	edi, DWORD PTR CRT_DISPLAY_CTRL[rip]
	call	peek32@PLT
	mov	edi, DWORD PTR CRT_DISPLAY_CTRL[rip]
	mov	r8d, eax
	mov	eax, DWORD PTR DISPLAY_CTRL_VSYNC_PHASE[rip]
	or	eax, DWORD PTR DISPLAY_CTRL_HSYNC_PHASE[rip]
	or	eax, DWORD PTR DISPLAY_CTRL_TIMING[rip]
	or	eax, DWORD PTR DISPLAY_CTRL_PLANE[rip]
	not	eax
	and	eax, r8d
	or	eax, r12d
	mov	esi, eax
	call	poke32@PLT
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	xor	eax, eax
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
.L18:
	.cfi_restore_state
	mov	esi, r12d
	mov	rdi, rbp
	call	displayControlAdjust_SM750LE@PLT
	xor	eax, eax
	jmp	.L1
.L12:
	mov	eax, -1
	jmp	.L1
	.cfi_endproc
.LFE0:
	.size	programModeRegisters, .-programModeRegisters
	.comm	SM750LE,8,8
	.comm	SECONDARY_PLL,8,8
	.comm	PRIMARY_PLL,8,8
	.comm	PANEL_VERTICAL_TOTAL_TOTAL_SHIFT,4,4
	.comm	PANEL_VERTICAL_TOTAL_TOTAL_MASK,4,4
	.comm	PANEL_VERTICAL_TOTAL_DISPLAY_END_MASK,4,4
	.comm	PANEL_VERTICAL_TOTAL,4,4
	.comm	PANEL_VERTICAL_SYNC_START_MASK,4,4
	.comm	PANEL_VERTICAL_SYNC_HEIGHT_SHIFT,4,4
	.comm	PANEL_VERTICAL_SYNC_HEIGHT_MASK,4,4
	.comm	PANEL_VERTICAL_SYNC,4,4
	.comm	PANEL_PLL_CTRL,4,4
	.comm	PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT,4,4
	.comm	PANEL_HORIZONTAL_TOTAL_TOTAL_MASK,4,4
	.comm	PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK,4,4
	.comm	PANEL_HORIZONTAL_TOTAL,4,4
	.comm	PANEL_HORIZONTAL_SYNC_WIDTH_SHIFT,4,4
	.comm	PANEL_HORIZONTAL_SYNC_WIDTH_MASK,4,4
	.comm	PANEL_HORIZONTAL_SYNC_START_MASK,4,4
	.comm	PANEL_HORIZONTAL_SYNC,4,4
	.comm	PANEL_DISPLAY_CTRL_VSYNC,4,4
	.comm	PANEL_DISPLAY_CTRL_RESERVED_MASK,4,4
	.comm	PANEL_DISPLAY_CTRL,4,4
	.comm	DISPLAY_CTRL_VSYNC_PHASE,4,4
	.comm	DISPLAY_CTRL_TIMING,4,4
	.comm	DISPLAY_CTRL_PLANE,4,4
	.comm	DISPLAY_CTRL_HSYNC_PHASE,4,4
	.comm	DISPLAY_CTRL_CLOCK_PHASE,4,4
	.comm	CRT_VERTICAL_TOTAL_TOTAL_SHIFT,4,4
	.comm	CRT_VERTICAL_TOTAL_TOTAL_MASK,4,4
	.comm	CRT_VERTICAL_TOTAL_DISPLAY_END_MASK,4,4
	.comm	CRT_VERTICAL_TOTAL,4,4
	.comm	CRT_VERTICAL_SYNC_START_MASK,4,4
	.comm	CRT_VERTICAL_SYNC_HEIGHT_SHIFT,4,4
	.comm	CRT_VERTICAL_SYNC_HEIGHT_MASK,4,4
	.comm	CRT_VERTICAL_SYNC,4,4
	.comm	CRT_PLL_CTRL,4,4
	.comm	CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT,4,4
	.comm	CRT_HORIZONTAL_TOTAL_TOTAL_MASK,4,4
	.comm	CRT_HORIZONTAL_TOTAL_DISPLAY_END_MASK,4,4
	.comm	CRT_HORIZONTAL_TOTAL,4,4
	.comm	CRT_HORIZONTAL_SYNC_WIDTH_SHIFT,4,4
	.comm	CRT_HORIZONTAL_SYNC_WIDTH_MASK,4,4
	.comm	CRT_HORIZONTAL_SYNC_START_MASK,4,4
	.comm	CRT_HORIZONTAL_SYNC,4,4
	.comm	CRT_DISPLAY_CTRL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_ddk750_mode.c_programModeRegisters.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	programModeRegisters, %function
programModeRegisters:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r2, .L33
	ldr	r3, [r1]
	ldr	r2, [r2]
	mov	r4, r0
	cmp	r3, r2
	sub	sp, sp, #12
	beq	.L31
	ldr	r2, .L33+4
	ldr	r2, [r2]
	cmp	r3, r2
	bne	.L12
	ldr	r3, .L33+8
	mov	r0, r1
	ldr	r5, [r3]
	bl	sm750_format_pll_reg
	mov	r1, r0
	mov	r0, r5
	bl	poke32
	ldm	r4, {r2, r3}
	ldr	ip, .L33+12
	ldr	r1, .L33+16
	ldr	r0, .L33+20
	ldr	ip, [ip]
	ldr	r1, [r1]
	ldr	r0, [r0]
	sub	r2, r2, #1
	and	r1, r1, r2, lsl ip
	sub	r3, r3, #1
	ldr	r2, .L33+24
	and	r3, r3, r0
	orr	r1, r3, r1
	ldr	r0, [r2]
	bl	poke32
	ldr	r2, .L33+28
	ldr	r1, .L33+32
	ldr	r0, .L33+36
	ldr	ip, [r4, #8]
	ldr	r3, [r4, #12]
	ldr	r2, [r2]
	ldr	r1, [r1]
	ldr	r0, [r0]
	and	r1, r1, ip, lsl r2
	sub	r3, r3, #1
	ldr	r2, .L33+40
	and	r3, r3, r0
	orr	r1, r1, r3
	ldr	r0, [r2]
	bl	poke32
	ldr	ip, .L33+44
	ldr	r1, .L33+48
	ldr	r2, [r4, #16]
	ldr	r0, .L33+52
	ldr	r3, [r4, #20]
	ldr	ip, [ip]
	ldr	r1, [r1]
	ldr	r0, [r0]
	sub	r2, r2, #1
	and	r1, r1, r2, lsl ip
	sub	r3, r3, #1
	ldr	r2, .L33+56
	and	r3, r3, r0
	orr	r1, r1, r3
	ldr	r0, [r2]
	bl	poke32
	ldr	r2, .L33+60
	ldr	r1, .L33+64
	ldr	r0, .L33+68
	ldr	ip, [r4, #24]
	ldr	r3, [r4, #28]
	ldr	r2, [r2]
	ldr	r1, [r1]
	ldr	r0, [r0]
	and	r1, r1, ip, lsl r2
	sub	r3, r3, #1
	ldr	r2, .L33+72
	and	r3, r3, r0
	ldr	r10, .L33+76
	ldr	r9, .L33+80
	orr	r1, r1, r3
	ldr	r0, [r2]
	bl	poke32
	ldr	r5, [r10]
	ldr	r3, [r9]
	ldr	r2, [r4, #40]
	orr	r8, r5, r3
	ldr	r3, .L33+84
	cmp	r2, #0
	ldrne	r2, [r3]
	ldr	fp, .L33+88
	orrne	r8, r8, r2
	ldr	r2, [r4, #36]
	ldr	r1, .L33+92
	cmp	r2, #0
	ldrne	r2, [fp]
	ldr	r6, .L33+96
	orrne	r8, r8, r2
	ldr	r2, [r4, #32]
	ldr	r4, .L33+100
	cmp	r2, #0
	ldrne	r2, [r4]
	ldr	r7, [r1]
	orrne	r8, r8, r2
	ldr	r2, .L33+104
	ldr	r0, [r6]
	ldr	r2, [r2]
	str	r3, [sp, #4]
	orr	r7, r7, r2
	bl	peek32
	ldr	r3, [sp, #4]
	ldr	r5, [r4]
	ldr	r2, [r3]
	ldr	r3, [fp]
	orr	r5, r5, r2
	ldr	r2, [r10]
	orr	r5, r5, r3
	ldr	r3, [r9]
	orr	r5, r5, r2
	orr	r5, r5, r3
	orr	r5, r5, r7
	bic	r5, r0, r5
	orr	r5, r5, r8
	mov	r1, r5
	ldr	r0, [r6]
	mvn	r7, r7
	bl	poke32
	ldr	r4, .L33+108
	b	.L10
.L11:
	subs	r4, r4, #1
	beq	.L13
	mov	r1, r5
	ldr	r0, [r6]
	bl	poke32
.L10:
	ldr	r0, [r6]
	bl	peek32
	and	r0, r0, r7
	cmp	r5, r0
	bne	.L11
	mov	r0, #0
.L1:
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L31:
	ldr	r3, .L33+112
	mov	r0, r1
	ldr	r5, [r3]
	bl	sm750_format_pll_reg
	mov	r1, r0
	mov	r0, r5
	bl	poke32
	ldm	r4, {r2, r3}
	ldr	ip, .L33+116
	ldr	r1, .L33+120
	ldr	r0, .L33+124
	ldr	ip, [ip]
	ldr	r1, [r1]
	ldr	r0, [r0]
	sub	r2, r2, #1
	and	r1, r1, r2, lsl ip
	sub	r3, r3, #1
	ldr	r2, .L33+128
	and	r3, r3, r0
	orr	r1, r3, r1
	ldr	r0, [r2]
	bl	poke32
	ldr	r2, .L33+132
	ldr	r1, .L33+136
	ldr	r0, .L33+140
	ldr	r2, [r2]
	ldr	ip, [r4, #8]
	ldr	r3, [r4, #12]
	ldr	r1, [r1]
	ldr	r0, [r0]
	and	r1, r1, ip, lsl r2
	sub	r3, r3, #1
	ldr	r2, .L33+144
	and	r3, r3, r0
	orr	r1, r3, r1
	ldr	r0, [r2]
	bl	poke32
	ldr	ip, .L33+148
	ldr	r1, .L33+152
	ldr	r2, [r4, #16]
	ldr	r0, .L33+156
	ldr	ip, [ip]
	ldr	r3, [r4, #20]
	ldr	r1, [r1]
	ldr	r0, [r0]
	sub	r2, r2, #1
	and	r1, r1, r2, lsl ip
	sub	r3, r3, #1
	ldr	r2, .L33+160
	and	r3, r3, r0
	orr	r1, r3, r1
	ldr	r0, [r2]
	bl	poke32
	ldr	r2, .L33+164
	ldr	r1, .L33+168
	ldr	r0, .L33+172
	ldr	r2, [r2]
	ldr	ip, [r4, #24]
	ldr	r3, [r4, #28]
	ldr	r1, [r1]
	ldr	r0, [r0]
	and	r1, r1, ip, lsl r2
	sub	r3, r3, #1
	ldr	r2, .L33+176
	and	r3, r3, r0
	orr	r1, r3, r1
	ldr	r0, [r2]
	bl	poke32
	ldr	r3, [r4, #40]
	ldr	r10, .L33+76
	cmp	r3, #0
	ldr	r9, .L33+80
	ldrne	r3, .L33+84
	ldr	r5, [r10]
	ldr	r1, [r9]
	ldrne	r3, [r3]
	orr	r5, r5, r1
	orrne	r5, r5, r3
	ldr	r3, [r4, #36]
	cmp	r3, #0
	ldrne	r3, .L33+88
	ldrne	r3, [r3]
	orrne	r5, r5, r3
	bl	sm750_get_chip_type
	ldr	r3, .L33+180
	ldr	r3, [r3]
	cmp	r0, r3
	beq	.L32
	ldr	r4, .L33+184
	ldr	r0, [r4]
	bl	peek32
	ldr	r2, .L33+88
	ldr	r3, .L33+84
	ldr	ip, [r2]
	ldr	r3, [r3]
	ldr	r1, [r10]
	ldr	r2, [r9]
	orr	r3, r3, ip
	orr	r3, r3, r1
	orr	r3, r3, r2
	bic	r3, r0, r3
	orr	r1, r3, r5
	ldr	r0, [r4]
	bl	poke32
	mov	r0, #0
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L32:
	mov	r1, r5
	mov	r0, r4
	bl	displayControlAdjust_SM750LE
	mov	r0, #0
	b	.L1
.L13:
	mov	r0, r4
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L12:
	mvn	r0, #0
	b	.L1
.L34:
	.align	2
.L33:
	.word	SECONDARY_PLL
	.word	PRIMARY_PLL
	.word	PANEL_PLL_CTRL
	.word	PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT
	.word	PANEL_HORIZONTAL_TOTAL_TOTAL_MASK
	.word	PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK
	.word	PANEL_HORIZONTAL_TOTAL
	.word	PANEL_HORIZONTAL_SYNC_WIDTH_SHIFT
	.word	PANEL_HORIZONTAL_SYNC_WIDTH_MASK
	.word	PANEL_HORIZONTAL_SYNC_START_MASK
	.word	PANEL_HORIZONTAL_SYNC
	.word	PANEL_VERTICAL_TOTAL_TOTAL_SHIFT
	.word	PANEL_VERTICAL_TOTAL_TOTAL_MASK
	.word	PANEL_VERTICAL_TOTAL_DISPLAY_END_MASK
	.word	PANEL_VERTICAL_TOTAL
	.word	PANEL_VERTICAL_SYNC_HEIGHT_SHIFT
	.word	PANEL_VERTICAL_SYNC_HEIGHT_MASK
	.word	PANEL_VERTICAL_SYNC_START_MASK
	.word	PANEL_VERTICAL_SYNC
	.word	DISPLAY_CTRL_TIMING
	.word	DISPLAY_CTRL_PLANE
	.word	DISPLAY_CTRL_VSYNC_PHASE
	.word	DISPLAY_CTRL_HSYNC_PHASE
	.word	PANEL_DISPLAY_CTRL_RESERVED_MASK
	.word	PANEL_DISPLAY_CTRL
	.word	DISPLAY_CTRL_CLOCK_PHASE
	.word	PANEL_DISPLAY_CTRL_VSYNC
	.word	1001
	.word	CRT_PLL_CTRL
	.word	CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT
	.word	CRT_HORIZONTAL_TOTAL_TOTAL_MASK
	.word	CRT_HORIZONTAL_TOTAL_DISPLAY_END_MASK
	.word	CRT_HORIZONTAL_TOTAL
	.word	CRT_HORIZONTAL_SYNC_WIDTH_SHIFT
	.word	CRT_HORIZONTAL_SYNC_WIDTH_MASK
	.word	CRT_HORIZONTAL_SYNC_START_MASK
	.word	CRT_HORIZONTAL_SYNC
	.word	CRT_VERTICAL_TOTAL_TOTAL_SHIFT
	.word	CRT_VERTICAL_TOTAL_TOTAL_MASK
	.word	CRT_VERTICAL_TOTAL_DISPLAY_END_MASK
	.word	CRT_VERTICAL_TOTAL
	.word	CRT_VERTICAL_SYNC_HEIGHT_SHIFT
	.word	CRT_VERTICAL_SYNC_HEIGHT_MASK
	.word	CRT_VERTICAL_SYNC_START_MASK
	.word	CRT_VERTICAL_SYNC
	.word	SM750LE
	.word	CRT_DISPLAY_CTRL
	.size	programModeRegisters, .-programModeRegisters
	.comm	SM750LE,4,4
	.comm	SECONDARY_PLL,4,4
	.comm	PRIMARY_PLL,4,4
	.comm	PANEL_VERTICAL_TOTAL_TOTAL_SHIFT,4,4
	.comm	PANEL_VERTICAL_TOTAL_TOTAL_MASK,4,4
	.comm	PANEL_VERTICAL_TOTAL_DISPLAY_END_MASK,4,4
	.comm	PANEL_VERTICAL_TOTAL,4,4
	.comm	PANEL_VERTICAL_SYNC_START_MASK,4,4
	.comm	PANEL_VERTICAL_SYNC_HEIGHT_SHIFT,4,4
	.comm	PANEL_VERTICAL_SYNC_HEIGHT_MASK,4,4
	.comm	PANEL_VERTICAL_SYNC,4,4
	.comm	PANEL_PLL_CTRL,4,4
	.comm	PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT,4,4
	.comm	PANEL_HORIZONTAL_TOTAL_TOTAL_MASK,4,4
	.comm	PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK,4,4
	.comm	PANEL_HORIZONTAL_TOTAL,4,4
	.comm	PANEL_HORIZONTAL_SYNC_WIDTH_SHIFT,4,4
	.comm	PANEL_HORIZONTAL_SYNC_WIDTH_MASK,4,4
	.comm	PANEL_HORIZONTAL_SYNC_START_MASK,4,4
	.comm	PANEL_HORIZONTAL_SYNC,4,4
	.comm	PANEL_DISPLAY_CTRL_VSYNC,4,4
	.comm	PANEL_DISPLAY_CTRL_RESERVED_MASK,4,4
	.comm	PANEL_DISPLAY_CTRL,4,4
	.comm	DISPLAY_CTRL_VSYNC_PHASE,4,4
	.comm	DISPLAY_CTRL_TIMING,4,4
	.comm	DISPLAY_CTRL_PLANE,4,4
	.comm	DISPLAY_CTRL_HSYNC_PHASE,4,4
	.comm	DISPLAY_CTRL_CLOCK_PHASE,4,4
	.comm	CRT_VERTICAL_TOTAL_TOTAL_SHIFT,4,4
	.comm	CRT_VERTICAL_TOTAL_TOTAL_MASK,4,4
	.comm	CRT_VERTICAL_TOTAL_DISPLAY_END_MASK,4,4
	.comm	CRT_VERTICAL_TOTAL,4,4
	.comm	CRT_VERTICAL_SYNC_START_MASK,4,4
	.comm	CRT_VERTICAL_SYNC_HEIGHT_SHIFT,4,4
	.comm	CRT_VERTICAL_SYNC_HEIGHT_MASK,4,4
	.comm	CRT_VERTICAL_SYNC,4,4
	.comm	CRT_PLL_CTRL,4,4
	.comm	CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT,4,4
	.comm	CRT_HORIZONTAL_TOTAL_TOTAL_MASK,4,4
	.comm	CRT_HORIZONTAL_TOTAL_DISPLAY_END_MASK,4,4
	.comm	CRT_HORIZONTAL_TOTAL,4,4
	.comm	CRT_HORIZONTAL_SYNC_WIDTH_SHIFT,4,4
	.comm	CRT_HORIZONTAL_SYNC_WIDTH_MASK,4,4
	.comm	CRT_HORIZONTAL_SYNC_START_MASK,4,4
	.comm	CRT_HORIZONTAL_SYNC,4,4
	.comm	CRT_DISPLAY_CTRL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
