	.file	"extr_dce_dmcu.c_dce_psr_wait_loop.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	dce_psr_wait_loop, @function
dce_psr_wait_loop:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	push	rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	mov	ebp, esi
	push	rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	mov	rbx, rdi
	call	TO_DCE_DMCU@PLT
	cmp	DWORD PTR [rbx], ebp
	je	.L1
	mov	rdi, rbx
	call	dce_is_dmcu_initialized@PLT
	test	eax, eax
	jne	.L8
.L1:
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L8:
	.cfi_restore_state
	mov	esi, DWORD PTR MASTER_COMM_INTERRUPT[rip]
	mov	ecx, 1
	xor	edx, edx
	mov	r12d, ebp
	mov	edi, DWORD PTR MASTER_COMM_CNTL_REG[rip]
	mov	r8d, 10000
	call	REG_WAIT@PLT
	mov	DWORD PTR [rbx], ebp
	mov	edi, DWORD PTR MASTER_COMM_DATA_REG1[rip]
	call	REG@PLT
	mov	edi, DWORD PTR 4[rbx]
	mov	rdx, r12
	mov	esi, eax
	call	dm_write_reg@PLT
	mov	edx, DWORD PTR PSR_SET_WAITLOOP[rip]
	mov	esi, DWORD PTR MASTER_COMM_CMD_REG_BYTE0[rip]
	mov	edi, DWORD PTR MASTER_COMM_CMD_REG[rip]
	call	REG_UPDATE@PLT
	mov	esi, DWORD PTR MASTER_COMM_INTERRUPT[rip]
	pop	rbx
	.cfi_def_cfa_offset 24
	mov	edx, 1
	mov	edi, DWORD PTR MASTER_COMM_CNTL_REG[rip]
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	jmp	REG_UPDATE@PLT
	.cfi_endproc
.LFE0:
	.size	dce_psr_wait_loop, .-dce_psr_wait_loop
	.comm	PSR_SET_WAITLOOP,4,4
	.comm	MASTER_COMM_INTERRUPT,4,4
	.comm	MASTER_COMM_DATA_REG1,4,4
	.comm	MASTER_COMM_CNTL_REG,4,4
	.comm	MASTER_COMM_CMD_REG_BYTE0,4,4
	.comm	MASTER_COMM_CMD_REG,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_dce_dmcu.c_dce_psr_wait_loop.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	dce_psr_wait_loop, %function
dce_psr_wait_loop:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, lr}
	mov	r4, r0
	mov	r5, r1
	sub	sp, sp, #12
	bl	TO_DCE_DMCU
	ldr	r3, [r4]
	cmp	r3, r5
	beq	.L1
	mov	r0, r4
	bl	dce_is_dmcu_initialized
	cmp	r0, #0
	bne	.L10
.L1:
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, pc}
.L10:
	ldr	r7, .L11
	ldr	r6, .L11+4
	ldr	r3, .L11+8
	ldr	r1, [r7]
	mov	r2, #0
	str	r3, [sp]
	ldr	r0, [r6]
	mov	r3, #1
	bl	REG_WAIT
	ldr	r3, .L11+12
	str	r5, [r4]
	ldr	r0, [r3]
	ldr	r4, [r4, #4]
	bl	REG
	mov	r2, r5
	mov	r1, r0
	mov	r0, r4
	bl	dm_write_reg
	ldr	r3, .L11+16
	ldr	r2, .L11+20
	ldr	r1, .L11+24
	ldr	r2, [r2]
	ldr	r1, [r1]
	ldr	r0, [r3]
	bl	REG_UPDATE
	mov	r2, #1
	ldr	r1, [r7]
	ldr	r0, [r6]
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, lr}
	b	REG_UPDATE
.L12:
	.align	2
.L11:
	.word	MASTER_COMM_INTERRUPT
	.word	MASTER_COMM_CNTL_REG
	.word	10000
	.word	MASTER_COMM_DATA_REG1
	.word	MASTER_COMM_CMD_REG
	.word	PSR_SET_WAITLOOP
	.word	MASTER_COMM_CMD_REG_BYTE0
	.size	dce_psr_wait_loop, .-dce_psr_wait_loop
	.comm	PSR_SET_WAITLOOP,4,4
	.comm	MASTER_COMM_INTERRUPT,4,4
	.comm	MASTER_COMM_DATA_REG1,4,4
	.comm	MASTER_COMM_CNTL_REG,4,4
	.comm	MASTER_COMM_CMD_REG_BYTE0,4,4
	.comm	MASTER_COMM_CMD_REG,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
