	.file	"extr_pci-keystone.c_ks_pcie_setup_rc_app_regs.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	ks_pcie_setup_rc_app_regs, @function
ks_pcie_setup_rc_app_regs:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	mov	r12, rdi
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 8
	.cfi_def_cfa_offset 64
	mov	rbp, QWORD PTR 16[rdi]
	mov	r13d, DWORD PTR [rdi]
	mov	rax, QWORD PTR 0[rbp]
	mov	rbx, QWORD PTR [rax]
	mov	r14, QWORD PTR 8[rax]
	call	ks_pcie_set_dbi_mode@PLT
	mov	esi, DWORD PTR PCI_BASE_ADDRESS_0[rip]
	xor	edx, edx
	mov	rdi, rbp
	call	dw_pcie_writel_dbi@PLT
	mov	esi, DWORD PTR PCI_BASE_ADDRESS_1[rip]
	xor	edx, edx
	mov	rdi, rbp
	call	dw_pcie_writel_dbi@PLT
	mov	rdi, r12
	call	ks_pcie_clear_dbi_mode@PLT
	cmp	QWORD PTR 8[r12], 0
	je	.L18
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L18:
	.cfi_restore_state
	mov	rdi, QWORD PTR OB_WIN_SIZE[rip]
	call	ilog2@PLT
	mov	esi, DWORD PTR OB_SIZE[rip]
	mov	rdi, r12
	mov	edx, eax
	call	ks_pcie_app_writel@PLT
	cmp	rbx, r14
	jge	.L3
	test	r13d, r13d
	jle	.L3
	xor	ebp, ebp
	.p2align 4,,10
	.p2align 3
.L4:
	mov	rdi, rbx
	call	lower_32_bits@PLT
	mov	edi, ebp
	or	eax, DWORD PTR OB_ENABLEN[rip]
	mov	r15d, eax
	call	OB_OFFSET_INDEX@PLT
	mov	edx, r15d
	mov	rdi, r12
	mov	esi, eax
	call	ks_pcie_app_writel@PLT
	mov	rdi, rbx
	call	upper_32_bits@PLT
	mov	edi, ebp
	add	ebp, 1
	mov	r15d, eax
	call	OB_OFFSET_HI@PLT
	mov	edx, r15d
	mov	rdi, r12
	mov	esi, eax
	call	ks_pcie_app_writel@PLT
	add	rbx, QWORD PTR OB_WIN_SIZE[rip]
	cmp	r13d, ebp
	jle	.L3
	cmp	r14, rbx
	jg	.L4
.L3:
	mov	esi, DWORD PTR CMD_STATUS[rip]
	mov	rdi, r12
	call	ks_pcie_app_readl@PLT
	mov	esi, DWORD PTR CMD_STATUS[rip]
	or	eax, DWORD PTR OB_XLAT_EN_VAL[rip]
	add	rsp, 8
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	mov	rdi, r12
	pop	rbp
	.cfi_def_cfa_offset 40
	mov	edx, eax
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	jmp	ks_pcie_app_writel@PLT
	.cfi_endproc
.LFE0:
	.size	ks_pcie_setup_rc_app_regs, .-ks_pcie_setup_rc_app_regs
	.comm	PCI_BASE_ADDRESS_1,4,4
	.comm	PCI_BASE_ADDRESS_0,4,4
	.comm	OB_XLAT_EN_VAL,4,4
	.comm	OB_WIN_SIZE,8,8
	.comm	OB_SIZE,4,4
	.comm	OB_ENABLEN,4,4
	.comm	CMD_STATUS,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_pci-keystone.c_ks_pcie_setup_rc_app_regs.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	ks_pcie_setup_rc_app_regs, %function
ks_pcie_setup_rc_app_regs:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	mov	r6, r0
	ldr	r4, [r0, #8]
	ldr	r8, [r0]
	ldr	r3, [r4]
	ldm	r3, {r5, r9}
	bl	ks_pcie_set_dbi_mode
	ldr	r3, .L11
	mov	r0, r4
	ldr	r1, [r3]
	mov	r2, #0
	bl	dw_pcie_writel_dbi
	ldr	r3, .L11+4
	mov	r0, r4
	mov	r2, #0
	ldr	r1, [r3]
	bl	dw_pcie_writel_dbi
	mov	r0, r6
	bl	ks_pcie_clear_dbi_mode
	ldr	r4, [r6, #4]
	cmp	r4, #0
	popne	{r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
	ldr	fp, .L11+8
	ldr	r0, [fp]
	bl	ilog2
	ldr	r3, .L11+12
	mov	r2, r0
	ldr	r1, [r3]
	mov	r0, r6
	bl	ks_pcie_app_writel
	cmp	r5, r9
	movge	r3, #0
	movlt	r3, #1
	cmp	r8, #0
	movle	r3, #0
	cmp	r3, #0
	beq	.L3
	ldr	r10, .L11+16
.L4:
	mov	r0, r4
	bl	OB_OFFSET_INDEX
	mov	r7, r0
	mov	r0, r5
	bl	lower_32_bits
	ldr	r2, [r10]
	mov	r1, r7
	orr	r2, r0, r2
	mov	r0, r6
	bl	ks_pcie_app_writel
	mov	r0, r4
	bl	OB_OFFSET_HI
	mov	r7, r0
	mov	r0, r5
	bl	upper_32_bits
	mov	r1, r7
	mov	r2, r0
	mov	r0, r6
	bl	ks_pcie_app_writel
	ldr	r3, [fp]
	add	r4, r4, #1
	add	r5, r5, r3
	cmp	r8, r4
	cmpgt	r9, r5
	bgt	.L4
.L3:
	ldr	r4, .L11+20
	mov	r0, r6
	ldr	r1, [r4]
	bl	ks_pcie_app_readl
	mov	r2, r0
	ldr	r3, .L11+24
	mov	r0, r6
	ldr	r3, [r3]
	ldr	r1, [r4]
	orr	r2, r2, r3
	pop	{r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	b	ks_pcie_app_writel
.L12:
	.align	2
.L11:
	.word	PCI_BASE_ADDRESS_0
	.word	PCI_BASE_ADDRESS_1
	.word	OB_WIN_SIZE
	.word	OB_SIZE
	.word	OB_ENABLEN
	.word	CMD_STATUS
	.word	OB_XLAT_EN_VAL
	.size	ks_pcie_setup_rc_app_regs, .-ks_pcie_setup_rc_app_regs
	.comm	PCI_BASE_ADDRESS_1,4,4
	.comm	PCI_BASE_ADDRESS_0,4,4
	.comm	OB_XLAT_EN_VAL,4,4
	.comm	OB_WIN_SIZE,4,4
	.comm	OB_SIZE,4,4
	.comm	OB_ENABLEN,4,4
	.comm	CMD_STATUS,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
