	.file	"extr_radeon_clocks.c_calc_eng_mem_clock.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	calc_eng_mem_clock, @function
calc_eng_mem_clock:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	mov	r13, rdx
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	mov	r12, rdi
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	mov	rbp, rcx
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	mov	ebx, esi
	sub	rsp, 8
	.cfi_def_cfa_offset 48
	mov	esi, DWORD PTR [rdi]
	test	esi, esi
	je	.L9
.L2:
	cmp	ebx, 14999
	jg	.L3
	mov	DWORD PTR 0[rbp], 8
	sal	ebx, 3
.L4:
	imul	ebx, esi
	mov	ecx, DWORD PTR 4[r12]
	lea	eax, [rcx+rbx]
	add	ecx, ecx
	cdq
	idiv	ecx
	movzx	edx, al
	add	eax, eax
	mov	DWORD PTR 0[r13], edx
	and	eax, 131070
	imul	eax, DWORD PTR 4[r12]
	cdq
	idiv	esi
	cdq
	idiv	DWORD PTR 0[rbp]
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L3:
	.cfi_restore_state
	cmp	ebx, 29999
	jg	.L5
	mov	DWORD PTR 0[rbp], 4
	sal	ebx, 2
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L5:
	cmp	ebx, 59999
	jg	.L6
	mov	DWORD PTR 0[rbp], 2
	add	ebx, ebx
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L9:
	mov	edi, DWORD PTR RADEON_M_SPLL_REF_FB_DIV[rip]
	call	RREG32_PLL@PLT
	and	eax, DWORD PTR RADEON_M_SPLL_REF_DIV_MASK[rip]
	mov	esi, eax
	jmp	.L2
	.p2align 4,,10
	.p2align 3
.L6:
	mov	DWORD PTR 0[rbp], 1
	jmp	.L4
	.cfi_endproc
.LFE0:
	.size	calc_eng_mem_clock, .-calc_eng_mem_clock
	.comm	RADEON_M_SPLL_REF_FB_DIV,4,4
	.comm	RADEON_M_SPLL_REF_DIV_MASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_radeon_clocks.c_calc_eng_mem_clock.c"
	.text
	.global	__aeabi_idiv
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	calc_eng_mem_clock, %function
calc_eng_mem_clock:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, lr}
	ldr	r7, [r0]
	mov	r5, r0
	cmp	r7, #0
	mov	r4, r1
	mov	r8, r2
	mov	r6, r3
	beq	.L9
.L2:
	ldr	r3, .L10
	cmp	r4, r3
	bgt	.L3
	mov	r3, #8
	lsl	r4, r4, #3
	str	r3, [r6]
.L4:
	ldr	r1, [r5, #4]
	mla	r0, r7, r4, r1
	lsl	r1, r1, #1
	bl	__aeabi_idiv
	and	r3, r0, #255
	str	r3, [r8]
	ldr	r3, .L10+4
	ldr	r2, [r5, #4]
	and	r0, r3, r0, lsl #1
	mov	r1, r7
	mul	r0, r2, r0
	bl	__aeabi_idiv
	ldr	r1, [r6]
	bl	__aeabi_idiv
	pop	{r4, r5, r6, r7, r8, pc}
.L3:
	ldr	r3, .L10+8
	cmp	r4, r3
	movle	r3, #4
	lslle	r4, r4, #2
	strle	r3, [r6]
	ble	.L4
.L5:
	ldr	r3, .L10+12
	cmp	r4, r3
	movle	r3, #2
	movgt	r3, #1
	lslle	r4, r4, #1
	str	r3, [r6]
	b	.L4
.L9:
	ldr	r3, .L10+16
	ldr	r0, [r3]
	bl	RREG32_PLL
	ldr	r3, .L10+20
	ldr	r3, [r3]
	and	r7, r0, r3
	b	.L2
.L11:
	.align	2
.L10:
	.word	14999
	.word	131070
	.word	29999
	.word	59999
	.word	RADEON_M_SPLL_REF_FB_DIV
	.word	RADEON_M_SPLL_REF_DIV_MASK
	.size	calc_eng_mem_clock, .-calc_eng_mem_clock
	.comm	RADEON_M_SPLL_REF_FB_DIV,4,4
	.comm	RADEON_M_SPLL_REF_DIV_MASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
