	.file	"extr_gfx_v7_0.c_gfx_v7_0_ring_emit_hdp_flush.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	gfx_v7_0_ring_emit_hdp_flush, @function
gfx_v7_0_ring_emit_hdp_flush:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	xor	r13d, r13d
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	sub	rsp, 8
	.cfi_def_cfa_offset 48
	mov	rax, QWORD PTR 8[rdi]
	mov	r12d, DWORD PTR GPU_HDP_FLUSH_DONE__CP0_MASK[rip]
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR AMDGPU_RING_TYPE_COMPUTE[rip]
	cmp	rdx, rax
	setne	r13b
	je	.L10
.L6:
	mov	edi, DWORD PTR PACKET3_WAIT_REG_MEM[rip]
	mov	esi, 5
	call	PACKET3@PLT
	mov	rdi, rbp
	mov	esi, eax
	call	amdgpu_ring_write@PLT
	mov	edi, 1
	call	WAIT_REG_MEM_OPERATION@PLT
	mov	edi, 3
	mov	ebx, eax
	call	WAIT_REG_MEM_FUNCTION@PLT
	mov	edi, r13d
	or	ebx, eax
	call	WAIT_REG_MEM_ENGINE@PLT
	mov	rdi, rbp
	or	ebx, eax
	mov	esi, ebx
	call	amdgpu_ring_write@PLT
	mov	esi, DWORD PTR mmGPU_HDP_FLUSH_REQ[rip]
	mov	rdi, rbp
	call	amdgpu_ring_write@PLT
	mov	esi, DWORD PTR mmGPU_HDP_FLUSH_DONE[rip]
	mov	rdi, rbp
	call	amdgpu_ring_write@PLT
	mov	esi, r12d
	mov	rdi, rbp
	call	amdgpu_ring_write@PLT
	mov	esi, r12d
	mov	rdi, rbp
	call	amdgpu_ring_write@PLT
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	rdi, rbp
	mov	esi, 32
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	jmp	amdgpu_ring_write@PLT
	.p2align 4,,10
	.p2align 3
.L10:
	.cfi_restore_state
	mov	eax, DWORD PTR [rdi]
	cmp	eax, 1
	je	.L3
	cmp	eax, 2
	je	.L4
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L4:
	.cfi_restore_state
	mov	ecx, DWORD PTR 4[rdi]
	mov	r12d, DWORD PTR GPU_HDP_FLUSH_DONE__CP6_MASK[rip]
	sal	r12d, cl
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L3:
	mov	ecx, DWORD PTR 4[rdi]
	mov	r12d, DWORD PTR GPU_HDP_FLUSH_DONE__CP2_MASK[rip]
	sal	r12d, cl
	jmp	.L6
	.cfi_endproc
.LFE0:
	.size	gfx_v7_0_ring_emit_hdp_flush, .-gfx_v7_0_ring_emit_hdp_flush
	.comm	mmGPU_HDP_FLUSH_REQ,4,4
	.comm	mmGPU_HDP_FLUSH_DONE,4,4
	.comm	PACKET3_WAIT_REG_MEM,4,4
	.comm	GPU_HDP_FLUSH_DONE__CP6_MASK,4,4
	.comm	GPU_HDP_FLUSH_DONE__CP2_MASK,4,4
	.comm	GPU_HDP_FLUSH_DONE__CP0_MASK,4,4
	.comm	AMDGPU_RING_TYPE_COMPUTE,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_gfx_v7_0.c_gfx_v7_0_ring_emit_hdp_flush.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	gfx_v7_0_ring_emit_hdp_flush, %function
gfx_v7_0_ring_emit_hdp_flush:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	ldr	r3, .L12
	ldr	r2, [r0, #8]
	ldr	r3, [r3]
	ldr	r2, [r2]
	push	{r4, r5, r6, r7, r8, lr}
	cmp	r2, r3
	mov	r4, r0
	movne	r7, #1
	moveq	r7, #0
	beq	.L11
	ldr	r3, .L12+4
	ldr	r6, [r3]
.L6:
	ldr	r3, .L12+8
	mov	r1, #5
	ldr	r0, [r3]
	bl	PACKET3
	mov	r1, r0
	mov	r0, r4
	bl	amdgpu_ring_write
	mov	r0, #1
	bl	WAIT_REG_MEM_OPERATION
	mov	r5, r0
	mov	r0, #3
	bl	WAIT_REG_MEM_FUNCTION
	mov	r1, r0
	mov	r0, r7
	orr	r5, r5, r1
	bl	WAIT_REG_MEM_ENGINE
	mov	r1, r0
	mov	r0, r4
	orr	r1, r5, r1
	bl	amdgpu_ring_write
	ldr	r3, .L12+12
	mov	r0, r4
	ldr	r1, [r3]
	bl	amdgpu_ring_write
	ldr	r3, .L12+16
	mov	r0, r4
	ldr	r1, [r3]
	bl	amdgpu_ring_write
	mov	r1, r6
	mov	r0, r4
	bl	amdgpu_ring_write
	mov	r1, r6
	mov	r0, r4
	bl	amdgpu_ring_write
	mov	r0, r4
	pop	{r4, r5, r6, r7, r8, lr}
	mov	r1, #32
	b	amdgpu_ring_write
.L11:
	ldr	r3, [r0]
	cmp	r3, #1
	beq	.L3
	cmp	r3, #2
	popne	{r4, r5, r6, r7, r8, pc}
	ldr	r2, .L12+20
	ldr	r3, [r0, #4]
	ldr	r6, [r2]
	lsl	r6, r6, r3
	b	.L6
.L3:
	ldr	r2, .L12+24
	ldr	r3, [r0, #4]
	ldr	r6, [r2]
	lsl	r6, r6, r3
	b	.L6
.L13:
	.align	2
.L12:
	.word	AMDGPU_RING_TYPE_COMPUTE
	.word	GPU_HDP_FLUSH_DONE__CP0_MASK
	.word	PACKET3_WAIT_REG_MEM
	.word	mmGPU_HDP_FLUSH_REQ
	.word	mmGPU_HDP_FLUSH_DONE
	.word	GPU_HDP_FLUSH_DONE__CP6_MASK
	.word	GPU_HDP_FLUSH_DONE__CP2_MASK
	.size	gfx_v7_0_ring_emit_hdp_flush, .-gfx_v7_0_ring_emit_hdp_flush
	.comm	mmGPU_HDP_FLUSH_REQ,4,4
	.comm	mmGPU_HDP_FLUSH_DONE,4,4
	.comm	PACKET3_WAIT_REG_MEM,4,4
	.comm	GPU_HDP_FLUSH_DONE__CP6_MASK,4,4
	.comm	GPU_HDP_FLUSH_DONE__CP2_MASK,4,4
	.comm	GPU_HDP_FLUSH_DONE__CP0_MASK,4,4
	.comm	AMDGPU_RING_TYPE_COMPUTE,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
