	.file	"extr_etnaviv_gpu.c_etnaviv_hw_reset.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	""
.LC1:
	.string	"not "
.LC2:
	.string	"FE is not idle\n"
.LC3:
	.string	"GPU is not idle\n"
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC4:
	.string	"GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n"
	.text
	.p2align 4
	.type	etnaviv_hw_reset, @function
etnaviv_hw_reset:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	mov	r13d, 6
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	mov	rbp, rdi
	mov	edi, 1000
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	sub	rsp, 8
	.cfi_def_cfa_offset 48
	call	msecs_to_jiffies@PLT
	add	rax, QWORD PTR jiffies[rip]
	mov	r12, rax
.L2:
	mov	rdi, r12
	call	time_is_after_jiffies@PLT
	test	rax, rax
	je	.L22
.L10:
	mov	ecx, r13d
	mov	edi, 1
	sub	ecx, DWORD PTR 0[rbp]
	sal	edi, cl
	call	VIVS_HI_CLOCK_CONTROL_FSCALE_VAL@PLT
	mov	rdi, rbp
	mov	esi, eax
	mov	ebx, eax
	call	etnaviv_gpu_load_clock@PLT
	or	ebx, DWORD PTR VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU[rip]
	mov	esi, DWORD PTR VIVS_HI_CLOCK_CONTROL[rip]
	mov	rdi, rbp
	mov	edx, ebx
	call	gpu_write@PLT
	mov	rax, QWORD PTR ETNA_SEC_KERNEL[rip]
	cmp	QWORD PTR 8[rbp], rax
	je	.L23
	or	ebx, DWORD PTR VIVS_HI_CLOCK_CONTROL_SOFT_RESET[rip]
	mov	esi, DWORD PTR VIVS_HI_CLOCK_CONTROL[rip]
	mov	rdi, rbp
	mov	edx, ebx
	call	gpu_write@PLT
.L4:
	mov	esi, 20
	mov	edi, 10
	call	usleep_range@PLT
	mov	edx, DWORD PTR VIVS_HI_CLOCK_CONTROL_SOFT_RESET[rip]
	mov	esi, DWORD PTR VIVS_HI_CLOCK_CONTROL[rip]
	mov	rdi, rbp
	not	edx
	and	ebx, edx
	mov	edx, ebx
	call	gpu_write@PLT
	mov	edx, DWORD PTR VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU[rip]
	mov	esi, DWORD PTR VIVS_HI_CLOCK_CONTROL[rip]
	mov	rdi, rbp
	not	edx
	and	edx, ebx
	call	gpu_write@PLT
	mov	esi, DWORD PTR VIVS_HI_IDLE_STATE[rip]
	mov	rdi, rbp
	call	gpu_read@PLT
	test	DWORD PTR VIVS_HI_IDLE_STATE_FE[rip], eax
	je	.L24
	mov	esi, DWORD PTR VIVS_HI_CLOCK_CONTROL[rip]
	mov	rdi, rbp
	call	gpu_read@PLT
	test	DWORD PTR VIVS_HI_CLOCK_CONTROL_IDLE_3D[rip], eax
	je	.L7
	test	DWORD PTR VIVS_HI_CLOCK_CONTROL_IDLE_2D[rip], eax
	je	.L7
	mov	esi, DWORD PTR VIVS_HI_CLOCK_CONTROL[rip]
	or	eax, DWORD PTR VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS[rip]
	mov	rdi, rbp
	mov	edx, eax
	call	gpu_write@PLT
	mov	rdi, rbp
	call	etnaviv_gpu_update_clock@PLT
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	xor	eax, eax
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L7:
	.cfi_restore_state
	mov	edi, DWORD PTR 16[rbp]
	lea	rsi, .LC3[rip]
	call	dev_dbg@PLT
	mov	rdi, r12
	call	time_is_after_jiffies@PLT
	test	rax, rax
	jne	.L10
.L22:
	mov	esi, DWORD PTR VIVS_HI_IDLE_STATE[rip]
	mov	rdi, rbp
	call	gpu_read@PLT
	mov	esi, DWORD PTR VIVS_HI_CLOCK_CONTROL[rip]
	mov	rdi, rbp
	mov	ebx, eax
	call	gpu_read@PLT
	lea	rcx, .LC1[rip]
	lea	rdx, .LC0[rip]
	test	DWORD PTR VIVS_HI_CLOCK_CONTROL_IDLE_2D[rip], eax
	mov	r8, rcx
	mov	r9, rcx
	mov	edi, DWORD PTR 16[rbp]
	lea	rsi, .LC4[rip]
	cmovne	r8, rdx
	test	DWORD PTR VIVS_HI_CLOCK_CONTROL_IDLE_3D[rip], eax
	cmovne	r9, rdx
	test	DWORD PTR VIVS_HI_IDLE_STATE_FE[rip], ebx
	cmove	rdx, rcx
	mov	rcx, r9
	call	dev_err@PLT
	mov	eax, DWORD PTR EBUSY[rip]
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	neg	eax
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L23:
	.cfi_restore_state
	mov	edx, DWORD PTR VIVS_MMUv2_AHB_CONTROL_RESET[rip]
	mov	esi, DWORD PTR VIVS_MMUv2_AHB_CONTROL[rip]
	mov	rdi, rbp
	call	gpu_write@PLT
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L24:
	mov	edi, DWORD PTR 16[rbp]
	lea	rsi, .LC2[rip]
	call	dev_dbg@PLT
	jmp	.L2
	.cfi_endproc
.LFE0:
	.size	etnaviv_hw_reset, .-etnaviv_hw_reset
	.comm	jiffies,8,8
	.comm	VIVS_MMUv2_AHB_CONTROL_RESET,4,4
	.comm	VIVS_MMUv2_AHB_CONTROL,4,4
	.comm	VIVS_HI_IDLE_STATE_FE,4,4
	.comm	VIVS_HI_IDLE_STATE,4,4
	.comm	VIVS_HI_CLOCK_CONTROL_SOFT_RESET,4,4
	.comm	VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU,4,4
	.comm	VIVS_HI_CLOCK_CONTROL_IDLE_3D,4,4
	.comm	VIVS_HI_CLOCK_CONTROL_IDLE_2D,4,4
	.comm	VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS,4,4
	.comm	VIVS_HI_CLOCK_CONTROL,4,4
	.comm	ETNA_SEC_KERNEL,8,8
	.comm	EBUSY,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_etnaviv_gpu.c_etnaviv_hw_reset.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"\000"
	.align	2
.LC1:
	.ascii	"not \000"
	.align	2
.LC2:
	.ascii	"FE is not idle\012\000"
	.align	2
.LC3:
	.ascii	"GPU is not idle\012\000"
	.align	2
.LC4:
	.ascii	"GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidl"
	.ascii	"e\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	etnaviv_hw_reset, %function
etnaviv_hw_reset:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	mov	r4, r0
	sub	sp, sp, #12
	mov	r0, #1000
	bl	msecs_to_jiffies
	ldr	r3, .L24
	ldr	r5, .L24+4
	ldr	r3, [r3]
	ldr	r9, .L24+8
	ldr	r6, .L24+12
	ldr	r10, .L24+16
	ldr	r8, .L24+20
	add	r7, r0, r3
.L2:
	mov	r0, r7
	bl	time_is_after_jiffies
	cmp	r0, #0
	beq	.L22
.L10:
	mov	r0, #1
	ldr	r3, [r4]
	rsb	r3, r3, #6
	lsl	r0, r0, r3
	bl	VIVS_HI_CLOCK_CONTROL_FSCALE_VAL
	mov	fp, r0
	mov	r0, r4
	mov	r1, fp
	bl	etnaviv_gpu_load_clock
	ldr	r2, [r6]
	ldr	r1, [r5]
	orr	fp, fp, r2
	mov	r2, fp
	mov	r0, r4
	bl	gpu_write
	ldr	r3, [r10]
	ldr	r2, [r4, #4]
	mov	r0, r4
	cmp	r2, r3
	ldreq	r3, .L24+24
	ldrne	r3, [r8]
	ldreq	r2, [r3]
	ldreq	r3, .L24+28
	orrne	fp, fp, r3
	movne	r2, fp
	ldreq	r1, [r3]
	ldrne	r1, [r5]
	bl	gpu_write
	mov	r1, #20
	mov	r0, #10
	bl	usleep_range
	ldr	r2, [r8]
	ldr	r1, [r5]
	bic	fp, fp, r2
	mov	r2, fp
	mov	r0, r4
	bl	gpu_write
	ldr	r2, [r6]
	ldr	r1, [r5]
	bic	r2, fp, r2
	mov	r0, r4
	bl	gpu_write
	ldr	r3, .L24+32
	mov	r0, r4
	ldr	r1, [r3]
	bl	gpu_read
	ldr	r3, [r9]
	tst	r0, r3
	beq	.L23
	mov	r0, r4
	ldr	r1, [r5]
	bl	gpu_read
	ldr	r3, .L24+36
	ldr	r3, [r3]
	tst	r0, r3
	beq	.L7
	ldr	r3, .L24+40
	ldr	r3, [r3]
	tst	r0, r3
	beq	.L7
	mov	r2, r0
	ldr	r3, .L24+44
	ldr	r1, [r5]
	ldr	r3, [r3]
	mov	r0, r4
	orr	r2, r2, r3
	bl	gpu_write
	mov	r0, r4
	bl	etnaviv_gpu_update_clock
	mov	r0, #0
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L7:
	ldr	r1, .L24+48
	ldr	r0, [r4, #8]
	bl	dev_dbg
	mov	r0, r7
	bl	time_is_after_jiffies
	cmp	r0, #0
	bne	.L10
.L22:
	ldr	r3, .L24+32
	mov	r0, r4
	ldr	r1, [r3]
	bl	gpu_read
	mov	r3, r0
	ldr	r1, [r5]
	mov	r5, r3
	mov	r0, r4
	bl	gpu_read
	ldr	r2, [r9]
	ldr	r3, .L24+36
	tst	r5, r2
	ldr	r2, .L24+40
	ldr	r3, [r3]
	ldr	r1, .L24+52
	ldr	ip, .L24+56
	ldr	lr, [r2]
	movne	r2, r1
	moveq	r2, ip
	tst	r0, r3
	movne	r3, r1
	moveq	r3, ip
	tst	r0, lr
	moveq	r1, ip
	ldr	r0, [r4, #8]
	str	r1, [sp]
	ldr	r1, .L24+60
	bl	dev_err
	ldr	r3, .L24+64
	ldr	r0, [r3]
	rsb	r0, r0, #0
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L23:
	ldr	r1, .L24+68
	ldr	r0, [r4, #8]
	bl	dev_dbg
	b	.L2
.L25:
	.align	2
.L24:
	.word	jiffies
	.word	VIVS_HI_CLOCK_CONTROL
	.word	VIVS_HI_IDLE_STATE_FE
	.word	VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU
	.word	ETNA_SEC_KERNEL
	.word	VIVS_HI_CLOCK_CONTROL_SOFT_RESET
	.word	VIVS_MMUv2_AHB_CONTROL_RESET
	.word	VIVS_MMUv2_AHB_CONTROL
	.word	VIVS_HI_IDLE_STATE
	.word	VIVS_HI_CLOCK_CONTROL_IDLE_3D
	.word	VIVS_HI_CLOCK_CONTROL_IDLE_2D
	.word	VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS
	.word	.LC3
	.word	.LC0
	.word	.LC1
	.word	.LC4
	.word	EBUSY
	.word	.LC2
	.size	etnaviv_hw_reset, .-etnaviv_hw_reset
	.comm	jiffies,4,4
	.comm	VIVS_MMUv2_AHB_CONTROL_RESET,4,4
	.comm	VIVS_MMUv2_AHB_CONTROL,4,4
	.comm	VIVS_HI_IDLE_STATE_FE,4,4
	.comm	VIVS_HI_IDLE_STATE,4,4
	.comm	VIVS_HI_CLOCK_CONTROL_SOFT_RESET,4,4
	.comm	VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU,4,4
	.comm	VIVS_HI_CLOCK_CONTROL_IDLE_3D,4,4
	.comm	VIVS_HI_CLOCK_CONTROL_IDLE_2D,4,4
	.comm	VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS,4,4
	.comm	VIVS_HI_CLOCK_CONTROL,4,4
	.comm	ETNA_SEC_KERNEL,4,4
	.comm	EBUSY,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
