	.file	"extr_mn88443x.c_mn88443x_t_set_freq.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC0:
	.string	"Invalid clock, CLK:%d, ADCKT:%lld, IF:%d\n"
	.text
	.p2align 4
	.type	mn88443x_t_set_freq, @function
mn88443x_t_set_freq:
.LFB0:
	.cfi_startproc
	endbr64
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	mov	rbx, rdi
	sub	rsp, 8
	.cfi_def_cfa_offset 48
	mov	eax, DWORD PTR [rdi]
	cmp	eax, DWORD PTR CLK_LOW[rip]
	mov	r13, QWORD PTR 24[rdi]
	mov	rbp, QWORD PTR 16[rdi]
	mov	esi, DWORD PTR CLKSET1_T[rip]
	jl	.L2
	cmp	eax, DWORD PTR CLK_DIRECT[rip]
	jl	.L11
.L2:
	mov	DWORD PTR 4[rbx], 0
	xor	edx, edx
	mov	rdi, rbp
	call	regmap_write@PLT
	mov	r12d, DWORD PTR [rbx]
	mov	rsi, QWORD PTR 8[rbx]
	mov	edi, r12d
	call	mn88443x_t_is_valid_clk@PLT
	test	eax, eax
	je	.L12
.L4:
	mov	rax, QWORD PTR 8[rbx]
	cmp	rax, QWORD PTR DIRECT_IF_57MHZ[rip]
	je	.L6
	mov	edi, eax
	neg	edi
	cmp	rax, QWORD PTR DIRECT_IF_44MHZ[rip]
	je	.L6
.L8:
	mov	esi, r12d
	sal	edi, 24
	call	div_s64@PLT
	mov	esi, DWORD PTR S_T_FREQ[rip]
	mov	edi, r12d
	mov	r13d, eax
	sal	edi, 22
	call	div_s64@PLT
	mov	esi, DWORD PTR NCOFREQU_T[rip]
	mov	edx, r13d
	mov	rdi, rbp
	sar	edx, 16
	mov	r12d, eax
	call	regmap_write@PLT
	mov	esi, DWORD PTR NCOFREQM_T[rip]
	mov	edx, r13d
	mov	rdi, rbp
	sar	edx, 8
	call	regmap_write@PLT
	mov	esi, DWORD PTR NCOFREQL_T[rip]
	mov	edx, r13d
	mov	rdi, rbp
	call	regmap_write@PLT
	mov	esi, DWORD PTR FADU_T[rip]
	mov	edx, r12d
	mov	rdi, rbp
	sar	edx, 16
	call	regmap_write@PLT
	mov	esi, DWORD PTR FADM_T[rip]
	mov	edx, r12d
	mov	rdi, rbp
	sar	edx, 8
	call	regmap_write@PLT
	mov	esi, DWORD PTR FADL_T[rip]
	mov	edx, r12d
	mov	rdi, rbp
	call	regmap_write@PLT
	mov	ecx, DWORD PTR ADCSET1_T_REFSEL_1_5V[rip]
	mov	edx, DWORD PTR ADCSET1_T_REFSEL_MASK[rip]
	mov	rdi, rbp
	mov	esi, DWORD PTR ADCSET1_T[rip]
	call	regmap_update_bits@PLT
	mov	edx, DWORD PTR AGCSET2_T_IFPOLINV_INC[rip]
	mov	esi, DWORD PTR AGCSET2_T[rip]
	mov	rdi, rbp
	or	edx, DWORD PTR AGCSET2_T_RFPOLINV_INC[rip]
	mov	ecx, edx
	call	regmap_update_bits@PLT
	mov	esi, DWORD PTR AGCV3_T[rip]
	mov	rdi, rbp
	xor	edx, edx
	call	regmap_write@PLT
	mov	esi, DWORD PTR MDSET_T[rip]
	mov	rdi, rbp
	mov	edx, 250
	call	regmap_write@PLT
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	xor	eax, eax
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L11:
	.cfi_restore_state
	mov	DWORD PTR 4[rdi], 1
	mov	edx, 7
	mov	rdi, rbp
	xor	r12d, r12d
	call	regmap_write@PLT
	mov	rsi, QWORD PTR 8[rbx]
	mov	edi, r12d
	call	mn88443x_t_is_valid_clk@PLT
	test	eax, eax
	jne	.L4
.L12:
	mov	r8, QWORD PTR 8[rbx]
	mov	edx, DWORD PTR [rbx]
	mov	ecx, r12d
	mov	rdi, r13
	lea	rsi, .LC0[rip]
	call	dev_err@PLT
	mov	eax, DWORD PTR EINVAL[rip]
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	neg	eax
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L6:
	.cfi_restore_state
	lea	edi, [r12+r12]
	sub	edi, eax
	jmp	.L8
	.cfi_endproc
.LFE0:
	.size	mn88443x_t_set_freq, .-mn88443x_t_set_freq
	.comm	S_T_FREQ,4,4
	.comm	NCOFREQU_T,4,4
	.comm	NCOFREQM_T,4,4
	.comm	NCOFREQL_T,4,4
	.comm	MDSET_T,4,4
	.comm	FADU_T,4,4
	.comm	FADM_T,4,4
	.comm	FADL_T,4,4
	.comm	EINVAL,4,4
	.comm	DIRECT_IF_57MHZ,8,8
	.comm	DIRECT_IF_44MHZ,8,8
	.comm	CLK_LOW,4,4
	.comm	CLK_DIRECT,4,4
	.comm	CLKSET1_T,4,4
	.comm	AGCV3_T,4,4
	.comm	AGCSET2_T_RFPOLINV_INC,4,4
	.comm	AGCSET2_T_IFPOLINV_INC,4,4
	.comm	AGCSET2_T,4,4
	.comm	ADCSET1_T_REFSEL_MASK,4,4
	.comm	ADCSET1_T_REFSEL_1_5V,4,4
	.comm	ADCSET1_T,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_mn88443x.c_mn88443x_t_set_freq.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"Invalid clock, CLK:%d, ADCKT:%lld, IF:%d\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	mn88443x_t_set_freq, %function
mn88443x_t_set_freq:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, lr}
	ldr	r2, .L13
	ldr	r3, [r0]
	ldr	r1, [r2]
	ldr	r2, .L13+4
	cmp	r3, r1
	mov	r4, r0
	ldr	r6, [r0, #16]
	ldr	r5, [r0, #12]
	ldr	r1, [r2]
	sub	sp, sp, #12
	blt	.L2
	ldr	r2, .L13+8
	ldr	r2, [r2]
	cmp	r3, r2
	blt	.L11
.L2:
	mov	r2, #0
	mov	r0, r5
	str	r2, [r4, #4]
	bl	regmap_write
	ldr	r7, [r4]
.L3:
	mov	r0, r7
	ldr	r1, [r4, #8]
	bl	mn88443x_t_is_valid_clk
	cmp	r0, #0
	beq	.L12
	ldr	r3, .L13+12
	ldr	r0, [r4, #8]
	ldr	r3, [r3]
	cmp	r0, r3
	beq	.L6
	ldr	r3, .L13+16
	ldr	r3, [r3]
	cmp	r0, r3
	rsbne	r0, r0, #0
	beq	.L6
.L8:
	mov	r1, r7
	lsl	r0, r0, #24
	bl	div_s64
	ldr	r3, .L13+20
	mov	r6, r0
	ldr	r1, [r3]
	lsl	r0, r7, #22
	bl	div_s64
	mov	r4, r0
	ldr	r3, .L13+24
	asr	r2, r6, #16
	ldr	r1, [r3]
	mov	r0, r5
	bl	regmap_write
	ldr	r3, .L13+28
	asr	r2, r6, #8
	ldr	r1, [r3]
	mov	r0, r5
	bl	regmap_write
	ldr	r3, .L13+32
	mov	r2, r6
	ldr	r1, [r3]
	mov	r0, r5
	bl	regmap_write
	ldr	r3, .L13+36
	asr	r2, r4, #16
	ldr	r1, [r3]
	mov	r0, r5
	bl	regmap_write
	ldr	r3, .L13+40
	asr	r2, r4, #8
	ldr	r1, [r3]
	mov	r0, r5
	bl	regmap_write
	ldr	r3, .L13+44
	mov	r2, r4
	ldr	r1, [r3]
	mov	r0, r5
	bl	regmap_write
	ldr	r3, .L13+48
	ldr	r2, .L13+52
	ldr	r1, .L13+56
	mov	r0, r5
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	r1, [r1]
	bl	regmap_update_bits
	ldr	r3, .L13+60
	ldr	r2, .L13+64
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	r1, .L13+68
	orr	r3, r3, r2
	mov	r2, r3
	mov	r0, r5
	ldr	r1, [r1]
	bl	regmap_update_bits
	ldr	r3, .L13+72
	mov	r2, #0
	ldr	r1, [r3]
	mov	r0, r5
	bl	regmap_write
	ldr	r3, .L13+76
	mov	r0, r5
	mov	r2, #250
	ldr	r1, [r3]
	bl	regmap_write
	mov	r0, #0
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, pc}
.L11:
	mov	r3, #1
	mov	r2, #7
	str	r3, [r0, #4]
	mov	r0, r5
	bl	regmap_write
	mov	r7, #0
	b	.L3
.L6:
	rsb	r0, r0, r7, lsl #1
	b	.L8
.L12:
	ldr	r2, [r4, #8]
	mov	r3, r7
	str	r2, [sp]
	mov	r0, r6
	ldr	r2, [r4]
	ldr	r1, .L13+80
	bl	dev_err
	ldr	r3, .L13+84
	ldr	r0, [r3]
	rsb	r0, r0, #0
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, pc}
.L14:
	.align	2
.L13:
	.word	CLK_LOW
	.word	CLKSET1_T
	.word	CLK_DIRECT
	.word	DIRECT_IF_57MHZ
	.word	DIRECT_IF_44MHZ
	.word	S_T_FREQ
	.word	NCOFREQU_T
	.word	NCOFREQM_T
	.word	NCOFREQL_T
	.word	FADU_T
	.word	FADM_T
	.word	FADL_T
	.word	ADCSET1_T_REFSEL_1_5V
	.word	ADCSET1_T_REFSEL_MASK
	.word	ADCSET1_T
	.word	AGCSET2_T_IFPOLINV_INC
	.word	AGCSET2_T_RFPOLINV_INC
	.word	AGCSET2_T
	.word	AGCV3_T
	.word	MDSET_T
	.word	.LC0
	.word	EINVAL
	.size	mn88443x_t_set_freq, .-mn88443x_t_set_freq
	.comm	S_T_FREQ,4,4
	.comm	NCOFREQU_T,4,4
	.comm	NCOFREQM_T,4,4
	.comm	NCOFREQL_T,4,4
	.comm	MDSET_T,4,4
	.comm	FADU_T,4,4
	.comm	FADM_T,4,4
	.comm	FADL_T,4,4
	.comm	EINVAL,4,4
	.comm	DIRECT_IF_57MHZ,4,4
	.comm	DIRECT_IF_44MHZ,4,4
	.comm	CLK_LOW,4,4
	.comm	CLK_DIRECT,4,4
	.comm	CLKSET1_T,4,4
	.comm	AGCV3_T,4,4
	.comm	AGCSET2_T_RFPOLINV_INC,4,4
	.comm	AGCSET2_T_IFPOLINV_INC,4,4
	.comm	AGCSET2_T,4,4
	.comm	ADCSET1_T_REFSEL_MASK,4,4
	.comm	ADCSET1_T_REFSEL_1_5V,4,4
	.comm	ADCSET1_T,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
