	.file	"extr_bnx2x_link.c_bnx2x_link_reset.c"
	.intel_syntax noprefix
	.text
	.section	.rodata.str1.8,"aMS",@progbits,1
	.align 8
.LC0:
	.string	"Resetting the link of port %d\n"
	.text
	.p2align 4
	.globl	bnx2x_link_reset
	.type	bnx2x_link_reset, @function
bnx2x_link_reset:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	mov	r14d, edx
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	mov	rbx, rsi
	lea	rsi, .LC0[rip]
	sub	rsp, 24
	.cfi_def_cfa_offset 80
	mov	r15d, DWORD PTR [rdi]
	mov	r12, QWORD PTR 24[rdi]
	mov	edi, DWORD PTR NETIF_MSG_LINK[rip]
	mov	edx, r15d
	lea	r13d, 0[0+r15*4]
	call	DP@PLT
	mov	QWORD PTR 24[rbx], 0
	mov	esi, 1
	mov	rdi, rbp
	call	bnx2x_chng_link_count@PLT
	mov	rsi, QWORD PTR 24[rbx]
	mov	rdi, rbp
	call	bnx2x_update_mng@PLT
	mov	esi, DWORD PTR SHMEM_EEE_LP_ADV_STATUS_MASK[rip]
	mov	rdi, rbp
	or	esi, DWORD PTR SHMEM_EEE_ACTIVE_BIT[rip]
	not	esi
	and	esi, DWORD PTR [rbx]
	mov	DWORD PTR [rbx], esi
	call	bnx2x_update_mng_eee@PLT
	mov	rsi, QWORD PTR NIG_REG_MASK_INTERRUPT_PORT0[rip]
	movsx	rax, r13d
	mov	rdi, r12
	mov	edx, DWORD PTR NIG_MASK_XGXS0_LINK_STATUS[rip]
	or	edx, DWORD PTR NIG_MASK_XGXS0_LINK10G[rip]
	mov	r13, rax
	mov	QWORD PTR 8[rsp], rax
	or	edx, DWORD PTR NIG_MASK_SERDES0_LINK_STATUS[rip]
	add	rsi, rax
	or	edx, DWORD PTR NIG_MASK_MI_INT[rip]
	call	bnx2x_bits_dis@PLT
	mov	rsi, QWORD PTR NIG_REG_EGRESS_DRAIN0_MODE[rip]
	mov	rdi, r12
	mov	edx, 1
	add	rsi, r13
	call	REG_WR@PLT
	mov	rdi, r12
	call	CHIP_IS_E3@PLT
	test	eax, eax
	je	.L31
.L2:
	mov	rdi, r12
	call	CHIP_IS_E3@PLT
	test	eax, eax
	jne	.L3
	mov	esi, DWORD PTR 16[rbp]
	xor	ecx, ecx
	mov	rdi, r12
	mov	edx, r15d
	call	bnx2x_set_bmac_rx@PLT
	mov	rdi, r12
	call	CHIP_IS_E3@PLT
	test	eax, eax
	je	.L32
.L5:
	mov	esi, 20000
	mov	edi, 10000
	call	usleep_range@PLT
	mov	rsi, rbp
	mov	rdi, r12
	call	bnx2x_set_mdio_emac_per_phy@PLT
	mov	edx, DWORD PTR LED_MODE_OFF[rip]
	xor	ecx, ecx
	mov	rsi, rbx
	mov	rdi, rbp
	call	bnx2x_set_led@PLT
	test	r14d, r14d
	je	.L29
	mov	ecx, DWORD PTR EXT_PHY1[rip]
	mov	rdi, QWORD PTR 8[rbp]
	cmp	ecx, DWORD PTR 4[rbp]
	jge	.L7
	movsx	rdx, ecx
	xor	r14d, r14d
	sal	rdx, 4
	mov	r13, rdx
	.p2align 4,,10
	.p2align 3
.L10:
	lea	rsi, [rdi+r13]
	cmp	QWORD PTR 8[rsi], 0
	je	.L8
	mov	rdi, rbp
	mov	DWORD PTR 4[rsp], ecx
	call	bnx2x_set_aer_mmd@PLT
	mov	rax, QWORD PTR 8[rbp]
	mov	rsi, rbp
	add	rax, r13
	mov	rdi, rax
	call	[QWORD PTR 8[rax]]
	mov	rdi, QWORD PTR 8[rbp]
	mov	ecx, DWORD PTR 4[rsp]
	lea	rsi, [rdi+r13]
.L8:
	mov	eax, DWORD PTR [rsi]
	test	DWORD PTR FLAGS_REARM_LATCH_SIGNAL[rip], eax
	mov	eax, 1
	cmovne	r14d, eax
	add	ecx, 1
	add	r13, 16
	cmp	DWORD PTR 4[rbp], ecx
	jg	.L10
	test	r14d, r14d
	jne	.L33
.L7:
	mov	rax, QWORD PTR INT_PHY[rip]
	sal	rax, 4
	add	rdi, rax
	mov	rax, QWORD PTR 8[rdi]
	test	rax, rax
	je	.L11
	mov	rsi, rbp
	call	rax
.L11:
	mov	rdi, r12
	call	CHIP_IS_E3@PLT
	test	eax, eax
	je	.L34
	mov	eax, DWORD PTR 0[rbp]
	mov	r13, QWORD PTR GRCBASE_XMAC0[rip]
	test	eax, eax
	je	.L15
	mov	r13, QWORD PTR GRCBASE_XMAC1[rip]
.L15:
	xor	esi, esi
	xor	edx, edx
	mov	rdi, rbp
	call	bnx2x_set_xumac_nig@PLT
	mov	esi, DWORD PTR MISC_REG_RESET_REG_2[rip]
	mov	rdi, r12
	call	REG_RD@PLT
	test	DWORD PTR MISC_REGISTERS_RESET_REG_2_XMAC[rip], eax
	jne	.L35
.L13:
	mov	QWORD PTR 16[rbx], 0
	xor	eax, eax
	mov	QWORD PTR 8[rbx], 0
	add	rsp, 24
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L33:
	.cfi_restore_state
	xor	edx, edx
	mov	esi, r15d
	mov	rdi, r12
	call	bnx2x_rearm_latch_signal@PLT
	mov	ecx, DWORD PTR NIG_LATCH_BC_ENABLE_MI_INT[rip]
	mov	edx, 1
	mov	rdi, r12
	mov	rsi, QWORD PTR 8[rsp]
	add	rsi, QWORD PTR NIG_REG_LATCH_BC_0[rip]
	sal	edx, cl
	call	bnx2x_bits_dis@PLT
.L29:
	mov	rdi, QWORD PTR 8[rbp]
	jmp	.L7
	.p2align 4,,10
	.p2align 3
.L3:
	xor	esi, esi
	mov	rdi, rbp
	call	bnx2x_set_xmac_rxtx@PLT
	xor	esi, esi
	mov	rdi, rbp
	call	bnx2x_set_umac_rxtx@PLT
	mov	rdi, r12
	call	CHIP_IS_E3@PLT
	test	eax, eax
	jne	.L5
.L32:
	mov	rsi, QWORD PTR 8[rsp]
	xor	edx, edx
	mov	rdi, r12
	add	rsi, QWORD PTR NIG_REG_NIG_EMAC0_EN[rip]
	call	REG_WR@PLT
	jmp	.L5
	.p2align 4,,10
	.p2align 3
.L35:
	mov	rsi, QWORD PTR XMAC_REG_CTRL[rip]
	mov	edx, DWORD PTR XMAC_CTRL_REG_SOFT_RESET[rip]
	mov	rdi, r12
	add	rsi, r13
	call	REG_WR@PLT
	jmp	.L13
	.p2align 4,,10
	.p2align 3
.L31:
	mov	r13, QWORD PTR 8[rsp]
	mov	rsi, QWORD PTR NIG_REG_BMAC0_OUT_EN[rip]
	xor	edx, edx
	mov	rdi, r12
	add	rsi, r13
	call	REG_WR@PLT
	mov	rsi, QWORD PTR NIG_REG_EGRESS_EMAC0_OUT_EN[rip]
	xor	edx, edx
	mov	rdi, r12
	add	rsi, r13
	call	REG_WR@PLT
	jmp	.L2
	.p2align 4,,10
	.p2align 3
.L34:
	mov	edx, DWORD PTR MISC_REGISTERS_RESET_REG_2_RST_BMAC0[rip]
	mov	ecx, r15d
	mov	rdi, r12
	mov	rsi, QWORD PTR MISC_REGISTERS_RESET_REG_2_CLEAR[rip]
	add	rsi, QWORD PTR GRCBASE_MISC[rip]
	sal	edx, cl
	call	REG_WR@PLT
	mov	r15, QWORD PTR 8[rsp]
	xor	edx, edx
	mov	rdi, r12
	mov	rsi, QWORD PTR NIG_REG_BMAC0_IN_EN[rip]
	add	rsi, r15
	call	REG_WR@PLT
	mov	rsi, QWORD PTR NIG_REG_EMAC0_IN_EN[rip]
	xor	edx, edx
	mov	rdi, r12
	add	rsi, r15
	call	REG_WR@PLT
	jmp	.L13
	.cfi_endproc
.LFE0:
	.size	bnx2x_link_reset, .-bnx2x_link_reset
	.comm	XMAC_REG_CTRL,8,8
	.comm	XMAC_CTRL_REG_SOFT_RESET,4,4
	.comm	SHMEM_EEE_LP_ADV_STATUS_MASK,4,4
	.comm	SHMEM_EEE_ACTIVE_BIT,4,4
	.comm	NIG_REG_NIG_EMAC0_EN,8,8
	.comm	NIG_REG_MASK_INTERRUPT_PORT0,8,8
	.comm	NIG_REG_LATCH_BC_0,8,8
	.comm	NIG_REG_EMAC0_IN_EN,8,8
	.comm	NIG_REG_EGRESS_EMAC0_OUT_EN,8,8
	.comm	NIG_REG_EGRESS_DRAIN0_MODE,8,8
	.comm	NIG_REG_BMAC0_OUT_EN,8,8
	.comm	NIG_REG_BMAC0_IN_EN,8,8
	.comm	NIG_MASK_XGXS0_LINK_STATUS,4,4
	.comm	NIG_MASK_XGXS0_LINK10G,4,4
	.comm	NIG_MASK_SERDES0_LINK_STATUS,4,4
	.comm	NIG_MASK_MI_INT,4,4
	.comm	NIG_LATCH_BC_ENABLE_MI_INT,4,4
	.comm	NETIF_MSG_LINK,4,4
	.comm	MISC_REG_RESET_REG_2,4,4
	.comm	MISC_REGISTERS_RESET_REG_2_XMAC,4,4
	.comm	MISC_REGISTERS_RESET_REG_2_RST_BMAC0,4,4
	.comm	MISC_REGISTERS_RESET_REG_2_CLEAR,8,8
	.comm	LED_MODE_OFF,4,4
	.comm	INT_PHY,8,8
	.comm	GRCBASE_XMAC1,8,8
	.comm	GRCBASE_XMAC0,8,8
	.comm	GRCBASE_MISC,8,8
	.comm	FLAGS_REARM_LATCH_SIGNAL,4,4
	.comm	EXT_PHY1,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_bnx2x_link.c_bnx2x_link_reset.c"
	.text
	.section	.rodata.str1.4,"aMS",%progbits,1
	.align	2
.LC0:
	.ascii	"Resetting the link of port %d\012\000"
	.text
	.align	2
	.global	bnx2x_link_reset
	.syntax unified
	.arm
	.fpu softvfp
	.type	bnx2x_link_reset, %function
bnx2x_link_reset:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	mov	r4, r0
	ldr	r9, [r0]
	ldr	r3, .L39
	sub	sp, sp, #12
	mov	r7, r1
	ldr	r0, [r3]
	ldr	r1, .L39+4
	mov	r5, r2
	mov	r2, r9
	ldr	r6, [r4, #16]
	bl	DP
	mov	r3, #0
	mov	r1, #1
	str	r3, [r7, #12]
	mov	r0, r4
	bl	bnx2x_chng_link_count
	ldr	r1, [r7, #12]
	mov	r0, r4
	bl	bnx2x_update_mng
	ldr	r3, .L39+8
	ldr	r2, .L39+12
	ldr	r3, [r3]
	ldr	r2, [r2]
	ldr	r1, [r7]
	orr	r3, r3, r2
	bic	r1, r1, r3
	str	r1, [r7]
	mov	r0, r4
	bl	bnx2x_update_mng_eee
	ldr	r3, .L39+16
	ldr	r2, .L39+20
	ldr	r0, .L39+24
	ldr	ip, .L39+28
	ldr	r2, [r2]
	ldr	r3, [r3]
	ldr	r1, .L39+32
	ldr	r0, [r0]
	ldr	r1, [r1]
	orr	r3, r3, r2
	ldr	r2, [ip]
	orr	r3, r3, r0
	orr	r2, r3, r2
	add	r1, r1, r9, lsl #2
	mov	r0, r6
	bl	bnx2x_bits_dis
	ldr	r3, .L39+36
	lsl	r2, r9, #2
	ldr	r1, [r3]
	str	r2, [sp, #4]
	add	r1, r2, r1
	mov	r0, r6
	mov	r2, #1
	bl	REG_WR
	mov	r0, r6
	bl	CHIP_IS_E3
	subs	r8, r0, #0
	beq	.L34
.L2:
	mov	r0, r6
	bl	CHIP_IS_E3
	subs	r3, r0, #0
	bne	.L3
	mov	r2, r9
	ldr	r1, [r4, #12]
	mov	r0, r6
	bl	bnx2x_set_bmac_rx
	mov	r0, r6
	bl	CHIP_IS_E3
	subs	r2, r0, #0
	beq	.L35
.L5:
	ldr	r1, .L39+40
	ldr	r0, .L39+44
	bl	usleep_range
	mov	r1, r4
	mov	r0, r6
	bl	bnx2x_set_mdio_emac_per_phy
	ldr	r2, .L39+48
	mov	r3, #0
	mov	r1, r7
	mov	r0, r4
	ldr	r2, [r2]
	bl	bnx2x_set_led
	cmp	r5, #0
	beq	.L32
	ldr	r3, .L39+52
	ldr	ip, [r4, #4]
	ldr	r5, [r3]
	ldr	r0, [r4, #8]
	cmp	r5, ip
	bge	.L7
	mov	fp, #0
	ldr	r10, .L39+56
.L10:
	add	r1, r0, r5, lsl #3
	ldr	r2, [r1, #4]
	lsl	r8, r5, #3
	cmp	r2, #0
	add	r5, r5, #1
	beq	.L8
	mov	r0, r4
	bl	bnx2x_set_aer_mmd
	ldr	r0, [r4, #8]
	mov	r1, r4
	add	r0, r0, r8
	ldr	r2, [r0, #4]
	blx	r2
	ldr	r0, [r4, #8]
	ldr	ip, [r4, #4]
	add	r1, r0, r8
.L8:
	ldr	r1, [r1]
	ldr	r2, [r10]
	tst	r1, r2
	movne	fp, #1
	cmp	ip, r5
	bgt	.L10
	cmp	fp, #0
	bne	.L36
.L7:
	ldr	r3, .L39+60
	ldr	r3, [r3]
	add	r0, r0, r3, lsl #3
	ldr	r3, [r0, #4]
	cmp	r3, #0
	beq	.L11
	mov	r1, r4
	blx	r3
.L11:
	mov	r0, r6
	bl	CHIP_IS_E3
	subs	r5, r0, #0
	beq	.L37
	mov	r2, #0
	ldr	r3, [r4]
	mov	r1, r2
	cmp	r3, #0
	ldrne	r3, .L39+64
	ldreq	r3, .L39+68
	mov	r0, r4
	ldr	r5, [r3]
	bl	bnx2x_set_xumac_nig
	ldr	r3, .L39+72
	mov	r0, r6
	ldr	r1, [r3]
	bl	REG_RD
	ldr	r3, .L39+76
	ldr	r3, [r3]
	tst	r0, r3
	bne	.L38
.L13:
	mov	r0, #0
	str	r0, [r7, #8]
	str	r0, [r7, #4]
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L36:
	mov	r2, #0
	mov	r1, r9
	mov	r0, r6
	bl	bnx2x_rearm_latch_signal
	mov	r2, #1
	ldr	r3, .L39+80
	ldr	r1, .L39+84
	ldr	r3, [r3]
	ldr	r1, [r1]
	lsl	r2, r2, r3
	ldr	r3, [sp, #4]
	mov	r0, r6
	add	r1, r3, r1
	bl	bnx2x_bits_dis
.L32:
	ldr	r0, [r4, #8]
	b	.L7
.L3:
	mov	r1, #0
	mov	r0, r4
	bl	bnx2x_set_xmac_rxtx
	mov	r1, #0
	mov	r0, r4
	bl	bnx2x_set_umac_rxtx
	mov	r0, r6
	bl	CHIP_IS_E3
	subs	r2, r0, #0
	bne	.L5
.L35:
	ldr	r3, .L39+88
	mov	r0, r6
	ldr	r1, [r3]
	ldr	r3, [sp, #4]
	add	r1, r3, r1
	bl	REG_WR
	b	.L5
.L38:
	ldr	r2, .L39+92
	ldr	r3, .L39+96
	ldr	r1, [r2]
	mov	r0, r6
	ldr	r2, [r3]
	add	r1, r5, r1
	bl	REG_WR
	b	.L13
.L37:
	ldr	r2, .L39+100
	ldr	r1, .L39+104
	ldr	r3, .L39+108
	ldr	r2, [r2]
	ldr	r3, [r3]
	ldr	r1, [r1]
	lsl	r2, r2, r9
	add	r1, r1, r3
	mov	r0, r6
	bl	REG_WR
	ldr	r3, .L39+112
	ldr	r4, [sp, #4]
	ldr	r1, [r3]
	mov	r2, r5
	add	r1, r4, r1
	mov	r0, r6
	bl	REG_WR
	ldr	r3, .L39+116
	mov	r2, r5
	ldr	r1, [r3]
	mov	r0, r6
	add	r1, r4, r1
	bl	REG_WR
	b	.L13
.L34:
	ldr	r3, .L39+120
	ldr	r10, [sp, #4]
	ldr	r1, [r3]
	mov	r2, r8
	add	r1, r10, r1
	mov	r0, r6
	bl	REG_WR
	ldr	r3, .L39+124
	mov	r2, r8
	ldr	r1, [r3]
	mov	r0, r6
	add	r1, r10, r1
	bl	REG_WR
	b	.L2
.L40:
	.align	2
.L39:
	.word	NETIF_MSG_LINK
	.word	.LC0
	.word	SHMEM_EEE_LP_ADV_STATUS_MASK
	.word	SHMEM_EEE_ACTIVE_BIT
	.word	NIG_MASK_XGXS0_LINK_STATUS
	.word	NIG_MASK_XGXS0_LINK10G
	.word	NIG_MASK_SERDES0_LINK_STATUS
	.word	NIG_MASK_MI_INT
	.word	NIG_REG_MASK_INTERRUPT_PORT0
	.word	NIG_REG_EGRESS_DRAIN0_MODE
	.word	20000
	.word	10000
	.word	LED_MODE_OFF
	.word	EXT_PHY1
	.word	FLAGS_REARM_LATCH_SIGNAL
	.word	INT_PHY
	.word	GRCBASE_XMAC1
	.word	GRCBASE_XMAC0
	.word	MISC_REG_RESET_REG_2
	.word	MISC_REGISTERS_RESET_REG_2_XMAC
	.word	NIG_LATCH_BC_ENABLE_MI_INT
	.word	NIG_REG_LATCH_BC_0
	.word	NIG_REG_NIG_EMAC0_EN
	.word	XMAC_REG_CTRL
	.word	XMAC_CTRL_REG_SOFT_RESET
	.word	MISC_REGISTERS_RESET_REG_2_RST_BMAC0
	.word	GRCBASE_MISC
	.word	MISC_REGISTERS_RESET_REG_2_CLEAR
	.word	NIG_REG_BMAC0_IN_EN
	.word	NIG_REG_EMAC0_IN_EN
	.word	NIG_REG_BMAC0_OUT_EN
	.word	NIG_REG_EGRESS_EMAC0_OUT_EN
	.size	bnx2x_link_reset, .-bnx2x_link_reset
	.comm	XMAC_REG_CTRL,4,4
	.comm	XMAC_CTRL_REG_SOFT_RESET,4,4
	.comm	SHMEM_EEE_LP_ADV_STATUS_MASK,4,4
	.comm	SHMEM_EEE_ACTIVE_BIT,4,4
	.comm	NIG_REG_NIG_EMAC0_EN,4,4
	.comm	NIG_REG_MASK_INTERRUPT_PORT0,4,4
	.comm	NIG_REG_LATCH_BC_0,4,4
	.comm	NIG_REG_EMAC0_IN_EN,4,4
	.comm	NIG_REG_EGRESS_EMAC0_OUT_EN,4,4
	.comm	NIG_REG_EGRESS_DRAIN0_MODE,4,4
	.comm	NIG_REG_BMAC0_OUT_EN,4,4
	.comm	NIG_REG_BMAC0_IN_EN,4,4
	.comm	NIG_MASK_XGXS0_LINK_STATUS,4,4
	.comm	NIG_MASK_XGXS0_LINK10G,4,4
	.comm	NIG_MASK_SERDES0_LINK_STATUS,4,4
	.comm	NIG_MASK_MI_INT,4,4
	.comm	NIG_LATCH_BC_ENABLE_MI_INT,4,4
	.comm	NETIF_MSG_LINK,4,4
	.comm	MISC_REG_RESET_REG_2,4,4
	.comm	MISC_REGISTERS_RESET_REG_2_XMAC,4,4
	.comm	MISC_REGISTERS_RESET_REG_2_RST_BMAC0,4,4
	.comm	MISC_REGISTERS_RESET_REG_2_CLEAR,4,4
	.comm	LED_MODE_OFF,4,4
	.comm	INT_PHY,4,4
	.comm	GRCBASE_XMAC1,4,4
	.comm	GRCBASE_XMAC0,4,4
	.comm	GRCBASE_MISC,4,4
	.comm	FLAGS_REARM_LATCH_SIGNAL,4,4
	.comm	EXT_PHY1,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
