	.file	"extr_r600_dpm.c_r600_power_level_set_pcie_gen2.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	r600_power_level_set_pcie_gen2
	.type	r600_power_level_set_pcie_gen2, @function
r600_power_level_set_pcie_gen2:
.LFB0:
	.cfi_startproc
	endbr64
	mov	r8d, edx
	mov	edx, DWORD PTR CTXSW_FREQ_GEN2PCIE_VOLT[rip]
	not	esi
	test	r8d, r8d
	lea	rdi, 0[0+rsi*4]
	cmovne	r8d, edx
	and	edi, 12
	not	edx
	add	rdi, QWORD PTR CTXSW_PROFILE_INDEX[rip]
	mov	esi, r8d
	jmp	WREG32_P@PLT
	.cfi_endproc
.LFE0:
	.size	r600_power_level_set_pcie_gen2, .-r600_power_level_set_pcie_gen2
	.comm	CTXSW_PROFILE_INDEX,8,8
	.comm	CTXSW_FREQ_GEN2PCIE_VOLT,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_r600_dpm.c_r600_power_level_set_pcie_gen2.c"
	.text
	.align	2
	.global	r600_power_level_set_pcie_gen2
	.syntax unified
	.arm
	.fpu softvfp
	.type	r600_power_level_set_pcie_gen2, %function
r600_power_level_set_pcie_gen2:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	@ link register save eliminated.
	mvn	r1, r1
	ldr	r0, .L6
	ldr	r3, .L6+4
	ldr	ip, [r0]
	ldr	r3, [r3]
	and	r0, r1, #3
	subs	r1, r2, #0
	movne	r1, r3
	mvn	r2, r3
	add	r0, ip, r0, lsl #2
	b	WREG32_P
.L7:
	.align	2
.L6:
	.word	CTXSW_PROFILE_INDEX
	.word	CTXSW_FREQ_GEN2PCIE_VOLT
	.size	r600_power_level_set_pcie_gen2, .-r600_power_level_set_pcie_gen2
	.comm	CTXSW_PROFILE_INDEX,4,4
	.comm	CTXSW_FREQ_GEN2PCIE_VOLT,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
