	.file	"extr_psb_intel_display.c_psb_intel_crtc_clock_get.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	psb_intel_crtc_clock_get, @function
psb_intel_crtc_clock_get:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	mov	r12, rdi
	mov	rdi, rsi
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 40
	.cfi_def_cfa_offset 96
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 24[rsp], rax
	xor	eax, eax
	call	to_gma_crtc@PLT
	mov	r14, QWORD PTR [r12]
	xor	esi, esi
	mov	rdi, r12
	movsx	rax, DWORD PTR [rax]
	mov	r15, QWORD PTR 16[r14]
	mov	rbx, QWORD PTR 8[r14]
	mov	r13, rax
	lea	rax, [rax+rax*2]
	lea	rbp, 0[0+rax*4]
	call	gma_power_begin@PLT
	test	rax, rax
	jne	.L21
	lea	rax, [rbx+rbp]
	mov	ebp, DWORD PTR [rax]
	mov	ebx, DWORD PTR 8[rax]
	test	DWORD PTR DISPLAY_RATE_SELECT_FPA1[rip], ebp
	cmove	ebx, DWORD PTR 4[rax]
	xor	r15d, r15d
	cmp	r13d, 1
	je	.L22
.L6:
	mov	eax, DWORD PTR FP_M1_DIV_MASK[rip]
	mov	ecx, DWORD PTR FP_M1_DIV_SHIFT[rip]
	and	eax, ebx
	sar	eax, cl
	mov	ecx, DWORD PTR FP_M2_DIV_SHIFT[rip]
	mov	DWORD PTR [rsp], eax
	mov	eax, DWORD PTR FP_M2_DIV_MASK[rip]
	and	eax, ebx
	and	ebx, DWORD PTR FP_N_DIV_MASK[rip]
	sar	eax, cl
	mov	ecx, DWORD PTR FP_N_DIV_SHIFT[rip]
	mov	DWORD PTR 4[rsp], eax
	sar	ebx, cl
	mov	DWORD PTR 8[rsp], ebx
	test	r15d, r15d
	je	.L8
	mov	eax, DWORD PTR DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS[rip]
	mov	edx, -1
	mov	rsi, rsp
	mov	ecx, DWORD PTR DPLL_FPA01_P1_POST_DIV_SHIFT[rip]
	mov	DWORD PTR 16[rsp], 14
	and	eax, ebp
	sar	eax, cl
	bsf	eax, eax
	cmove	eax, edx
	and	ebp, DWORD PTR PLL_REF_INPUT_MASK[rip]
	add	eax, 1
	cmp	ebp, DWORD PTR PLLB_REF_INPUT_SPREADSPECTRUMIN[rip]
	mov	DWORD PTR 12[rsp], eax
	je	.L23
.L19:
	mov	edi, 48000
	call	psb_intel_clock@PLT
.L10:
	mov	rdx, QWORD PTR 24[rsp]
	xor	rdx, QWORD PTR fs:40
	mov	eax, DWORD PTR 20[rsp]
	jne	.L24
	add	rsp, 40
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L8:
	.cfi_restore_state
	mov	eax, 2
	test	DWORD PTR PLL_P1_DIVIDE_BY_TWO[rip], ebp
	je	.L25
.L11:
	and	ebp, DWORD PTR PLL_P2_DIVIDE_BY_4[rip]
	mov	DWORD PTR 12[rsp], eax
	mov	rsi, rsp
	cmp	ebp, 1
	sbb	eax, eax
	and	eax, -2
	add	eax, 4
	mov	DWORD PTR 16[rsp], eax
	jmp	.L19
	.p2align 4,,10
	.p2align 3
.L25:
	mov	eax, DWORD PTR DPLL_FPA01_P1_POST_DIV_MASK_I830[rip]
	mov	ecx, DWORD PTR DPLL_FPA01_P1_POST_DIV_SHIFT[rip]
	and	eax, ebp
	sar	eax, cl
	add	eax, 2
	jmp	.L11
	.p2align 4,,10
	.p2align 3
.L22:
	xor	r15d, r15d
	mov	eax, DWORD PTR [r14]
	test	DWORD PTR LVDS_PORT_EN[rip], eax
	setne	r15b
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L21:
	add	r15, rbp
	mov	edi, DWORD PTR 8[r15]
	call	REG_READ@PLT
	mov	ebp, eax
	test	DWORD PTR DISPLAY_RATE_SELECT_FPA1[rip], eax
	je	.L26
	mov	edi, DWORD PTR [r15]
	call	REG_READ@PLT
	mov	ebx, eax
.L4:
	xor	r15d, r15d
	cmp	r13d, 1
	je	.L27
.L5:
	mov	rdi, r12
	call	gma_power_end@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L23:
	mov	edi, 66000
	call	psb_intel_clock@PLT
	jmp	.L10
	.p2align 4,,10
	.p2align 3
.L26:
	mov	edi, DWORD PTR 4[r15]
	call	REG_READ@PLT
	mov	ebx, eax
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L27:
	mov	edi, DWORD PTR LVDS[rip]
	xor	r15d, r15d
	call	REG_READ@PLT
	test	DWORD PTR LVDS_PORT_EN[rip], eax
	setne	r15b
	jmp	.L5
.L24:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	psb_intel_crtc_clock_get, .-psb_intel_crtc_clock_get
	.comm	PLL_REF_INPUT_MASK,4,4
	.comm	PLL_P2_DIVIDE_BY_4,4,4
	.comm	PLL_P1_DIVIDE_BY_TWO,4,4
	.comm	PLLB_REF_INPUT_SPREADSPECTRUMIN,4,4
	.comm	LVDS_PORT_EN,4,4
	.comm	LVDS,4,4
	.comm	FP_N_DIV_SHIFT,4,4
	.comm	FP_N_DIV_MASK,4,4
	.comm	FP_M2_DIV_SHIFT,4,4
	.comm	FP_M2_DIV_MASK,4,4
	.comm	FP_M1_DIV_SHIFT,4,4
	.comm	FP_M1_DIV_MASK,4,4
	.comm	DPLL_FPA01_P1_POST_DIV_SHIFT,4,4
	.comm	DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS,4,4
	.comm	DPLL_FPA01_P1_POST_DIV_MASK_I830,4,4
	.comm	DISPLAY_RATE_SELECT_FPA1,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_psb_intel_display.c_psb_intel_crtc_clock_get.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	psb_intel_crtc_clock_get, %function
psb_intel_crtc_clock_get:
	@ args = 0, pretend = 0, frame = 32
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r3, .L23
	mov	r7, r0
	sub	sp, sp, #36
	mov	r0, r1
	ldr	r3, [r3]
	str	r3, [sp, #28]
	mov	r3,#0
	bl	to_gma_crtc
	ldr	r8, [r0]
	ldr	r9, [r7]
	add	r3, r8, r8, lsl #1
	mov	r0, r7
	mov	r1, #0
	ldr	r10, [r9, #8]
	ldr	fp, [r9, #4]
	lsl	r4, r3, #2
	bl	gma_power_begin
	subs	r6, r0, #0
	bne	.L19
	ldr	r3, .L23+4
	ldr	r5, [fp, r4]
	ldr	r2, [r3]
	add	r4, fp, r4
	tst	r5, r2
	ldmib	r4, {r3, r4}
	moveq	r4, r3
	cmp	r8, #1
	beq	.L20
.L6:
	ldr	r1, .L23+8
	ldr	r2, .L23+12
	ldr	r3, .L23+16
	ldr	r0, [r1]
	ldr	r2, [r2]
	ldr	r3, [r3]
	and	r2, r2, r4
	and	r3, r3, r4
	ldr	ip, .L23+20
	and	r4, r4, r0
	ldr	r1, .L23+24
	ldr	r0, .L23+28
	ldr	ip, [ip]
	ldr	r1, [r1]
	ldr	r0, [r0]
	asr	r2, r2, ip
	asr	r3, r3, r1
	asr	r4, r4, r0
	cmp	r6, #0
	stmib	sp, {r2, r3, r4}
	beq	.L8
	ldr	r3, .L23+32
	ldr	r2, .L23+36
	ldr	r3, [r3]
	ldr	r2, [r2]
	and	r3, r3, r5
	asr	r3, r3, r2
	rsb	r2, r3, #0
	and	r3, r3, r2
	clz	r3, r3
	mov	r2, #14
	ldr	r0, .L23+40
	ldr	r1, .L23+44
	ldr	r0, [r0]
	ldr	r1, [r1]
	and	r5, r5, r0
	cmp	r5, r1
	rsb	r3, r3, #32
	ldreq	r0, .L23+48
	ldrne	r0, .L23+52
	add	r1, sp, #4
	str	r3, [sp, #16]
	str	r2, [sp, #20]
	bl	psb_intel_clock
.L10:
	ldr	r3, .L23
	ldr	r0, [sp, #24]
	ldr	r2, [r3]
	ldr	r3, [sp, #28]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L21
	add	sp, sp, #36
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L8:
	ldr	r3, .L23+56
	add	r1, sp, #4
	ldr	r3, [r3]
	ldr	r0, .L23+52
	tst	r5, r3
	ldreq	r3, .L23+60
	ldreq	r2, .L23+36
	ldreq	r3, [r3]
	ldreq	r2, [r2]
	andeq	r3, r3, r5
	asreq	r3, r3, r2
	ldr	r2, .L23+64
	movne	r3, #2
	ldr	r2, [r2]
	addeq	r3, r3, #2
	tst	r5, r2
	movne	r2, #4
	moveq	r2, #2
	str	r3, [sp, #16]
	str	r2, [sp, #20]
	bl	psb_intel_clock
	b	.L10
.L20:
	ldr	r3, .L23+68
	ldr	r2, [r9]
	ldr	r3, [r3]
	tst	r2, r3
	movne	r6, #1
	moveq	r6, #0
	b	.L6
.L19:
	add	r6, r10, r4
	ldr	r0, [r6, #8]
	bl	REG_READ
	ldr	r3, .L23+4
	mov	r5, r0
	ldr	r3, [r3]
	tst	r0, r3
	ldreq	r0, [r6, #4]
	ldrne	r0, [r10, r4]
	bl	REG_READ
	cmp	r8, #1
	mov	r4, r0
	movne	r6, #0
	beq	.L22
.L5:
	mov	r0, r7
	bl	gma_power_end
	b	.L6
.L22:
	ldr	r3, .L23+72
	ldr	r0, [r3]
	bl	REG_READ
	ldr	r3, .L23+68
	ldr	r3, [r3]
	tst	r0, r3
	movne	r6, #1
	moveq	r6, #0
	b	.L5
.L21:
	bl	__stack_chk_fail
.L24:
	.align	2
.L23:
	.word	.LC0
	.word	DISPLAY_RATE_SELECT_FPA1
	.word	FP_N_DIV_MASK
	.word	FP_M1_DIV_MASK
	.word	FP_M2_DIV_MASK
	.word	FP_M1_DIV_SHIFT
	.word	FP_M2_DIV_SHIFT
	.word	FP_N_DIV_SHIFT
	.word	DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
	.word	DPLL_FPA01_P1_POST_DIV_SHIFT
	.word	PLL_REF_INPUT_MASK
	.word	PLLB_REF_INPUT_SPREADSPECTRUMIN
	.word	66000
	.word	48000
	.word	PLL_P1_DIVIDE_BY_TWO
	.word	DPLL_FPA01_P1_POST_DIV_MASK_I830
	.word	PLL_P2_DIVIDE_BY_4
	.word	LVDS_PORT_EN
	.word	LVDS
	.size	psb_intel_crtc_clock_get, .-psb_intel_crtc_clock_get
	.comm	PLL_REF_INPUT_MASK,4,4
	.comm	PLL_P2_DIVIDE_BY_4,4,4
	.comm	PLL_P1_DIVIDE_BY_TWO,4,4
	.comm	PLLB_REF_INPUT_SPREADSPECTRUMIN,4,4
	.comm	LVDS_PORT_EN,4,4
	.comm	LVDS,4,4
	.comm	FP_N_DIV_SHIFT,4,4
	.comm	FP_N_DIV_MASK,4,4
	.comm	FP_M2_DIV_SHIFT,4,4
	.comm	FP_M2_DIV_MASK,4,4
	.comm	FP_M1_DIV_SHIFT,4,4
	.comm	FP_M1_DIV_MASK,4,4
	.comm	DPLL_FPA01_P1_POST_DIV_SHIFT,4,4
	.comm	DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS,4,4
	.comm	DPLL_FPA01_P1_POST_DIV_MASK_I830,4,4
	.comm	DISPLAY_RATE_SELECT_FPA1,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
