	.file	"extr_aspeed-video.c_aspeed_video_check_and_set_polarity.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	aspeed_video_check_and_set_polarity, @function
aspeed_video_check_and_set_polarity:
.LFB0:
	.cfi_startproc
	endbr64
	mov	eax, DWORD PTR NUM_POLARITY_CHECKS[rip]
	test	eax, eax
	jle	.L23
	push	r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	mov	r13, rdi
	push	r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	xor	r12d, r12d
	push	rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	xor	ebp, ebp
	push	rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xor	ebx, ebx
	sub	rsp, 8
	.cfi_def_cfa_offset 48
	.p2align 4,,10
	.p2align 3
.L2:
	mov	esi, DWORD PTR VE_MODE_DETECT_STATUS[rip]
	mov	rdi, r13
	call	aspeed_video_read@PLT
	lea	edx, -1[rbp]
	add	ebp, 1
	test	DWORD PTR VE_MODE_DETECT_STATUS_VSYNC[rip], eax
	cmovne	ebp, edx
	lea	edx, -1[rbx]
	add	ebx, 1
	test	DWORD PTR VE_MODE_DETECT_STATUS_HSYNC[rip], eax
	cmovne	ebx, edx
	add	r12d, 1
	cmp	DWORD PTR NUM_POLARITY_CHECKS[rip], r12d
	jg	.L2
	test	ebx, ebx
	js	.L15
	test	ebp, ebp
	js	.L15
.L1:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	pop	rbx
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L15:
	.cfi_restore_state
	mov	eax, DWORD PTR 0[r13]
	mov	edx, DWORD PTR V4L2_DV_HSYNC_POS_POL[rip]
	test	ebx, ebx
	js	.L27
	or	eax, edx
	mov	DWORD PTR 0[r13], eax
.L11:
	mov	edx, DWORD PTR V4L2_DV_VSYNC_POS_POL[rip]
	mov	ecx, DWORD PTR VE_CTRL_VSYNC_POL[rip]
	not	edx
	and	eax, edx
.L13:
	mov	DWORD PTR 0[r13], eax
	test	ecx, ecx
	je	.L1
	mov	esi, DWORD PTR VE_CTRL[rip]
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	mov	rdi, r13
	xor	edx, edx
	pop	rbx
	.cfi_restore 3
	.cfi_def_cfa_offset 32
	pop	rbp
	.cfi_restore 6
	.cfi_def_cfa_offset 24
	pop	r12
	.cfi_restore 12
	.cfi_def_cfa_offset 16
	pop	r13
	.cfi_restore 13
	.cfi_def_cfa_offset 8
	jmp	aspeed_video_update@PLT
	.p2align 4,,10
	.p2align 3
.L27:
	.cfi_restore_state
	not	edx
	mov	ecx, DWORD PTR VE_CTRL_HSYNC_POL[rip]
	and	eax, edx
	mov	DWORD PTR 0[r13], eax
	test	ebp, ebp
	js	.L11
	or	eax, DWORD PTR V4L2_DV_VSYNC_POS_POL[rip]
	jmp	.L13
	.p2align 4,,10
	.p2align 3
.L23:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	.cfi_restore 6
	.cfi_restore 12
	.cfi_restore 13
	ret
	.cfi_endproc
.LFE0:
	.size	aspeed_video_check_and_set_polarity, .-aspeed_video_check_and_set_polarity
	.comm	VE_MODE_DETECT_STATUS_VSYNC,4,4
	.comm	VE_MODE_DETECT_STATUS_HSYNC,4,4
	.comm	VE_MODE_DETECT_STATUS,4,4
	.comm	VE_CTRL_VSYNC_POL,4,4
	.comm	VE_CTRL_HSYNC_POL,4,4
	.comm	VE_CTRL,4,4
	.comm	V4L2_DV_VSYNC_POS_POL,4,4
	.comm	V4L2_DV_HSYNC_POS_POL,4,4
	.comm	NUM_POLARITY_CHECKS,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_aspeed-video.c_aspeed_video_check_and_set_polarity.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	aspeed_video_check_and_set_polarity, %function
aspeed_video_check_and_set_polarity:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r8, .L25
	sub	sp, sp, #4
	ldr	r3, [r8]
	cmp	r3, #0
	ble	.L1
	mov	r5, #0
	mov	r7, r0
	mov	r6, r5
	mov	r4, r5
	ldr	r9, .L25+4
	ldr	fp, .L25+8
	ldr	r10, .L25+12
.L2:
	mov	r0, r7
	ldr	r1, [r9]
	bl	aspeed_video_read
	ldr	r3, [fp]
	add	r4, r4, #1
	tst	r0, r3
	ldr	r3, [r10]
	subne	r5, r5, #1
	addeq	r5, r5, #1
	tst	r0, r3
	ldr	r3, [r8]
	subne	r6, r6, #1
	addeq	r6, r6, #1
	cmp	r3, r4
	bgt	.L2
	orrs	r3, r6, r5
	bpl	.L1
	ldr	r3, .L25+16
	cmp	r6, #0
	ldr	r2, [r3]
	ldr	r3, [r7]
	orrge	r2, r2, r3
	strge	r2, [r7]
	blt	.L24
.L10:
	ldr	r1, .L25+20
	ldr	r3, .L25+24
	ldr	r1, [r1]
	ldr	r3, [r3]
	bic	r2, r2, r1
.L12:
	cmp	r3, #0
	str	r2, [r7]
	beq	.L1
	ldr	r2, .L25+28
	mov	r0, r7
	ldr	r1, [r2]
	mov	r2, #0
	add	sp, sp, #4
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	b	aspeed_video_update
.L1:
	add	sp, sp, #4
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L24:
	ldr	r1, .L25+32
	bic	r2, r3, r2
	cmp	r5, #0
	ldr	r3, [r1]
	str	r2, [r7]
	blt	.L10
	ldr	r1, .L25+20
	ldr	r1, [r1]
	orr	r2, r2, r1
	b	.L12
.L26:
	.align	2
.L25:
	.word	NUM_POLARITY_CHECKS
	.word	VE_MODE_DETECT_STATUS
	.word	VE_MODE_DETECT_STATUS_VSYNC
	.word	VE_MODE_DETECT_STATUS_HSYNC
	.word	V4L2_DV_HSYNC_POS_POL
	.word	V4L2_DV_VSYNC_POS_POL
	.word	VE_CTRL_VSYNC_POL
	.word	VE_CTRL
	.word	VE_CTRL_HSYNC_POL
	.size	aspeed_video_check_and_set_polarity, .-aspeed_video_check_and_set_polarity
	.comm	VE_MODE_DETECT_STATUS_VSYNC,4,4
	.comm	VE_MODE_DETECT_STATUS_HSYNC,4,4
	.comm	VE_MODE_DETECT_STATUS,4,4
	.comm	VE_CTRL_VSYNC_POL,4,4
	.comm	VE_CTRL_HSYNC_POL,4,4
	.comm	VE_CTRL,4,4
	.comm	V4L2_DV_VSYNC_POS_POL,4,4
	.comm	V4L2_DV_HSYNC_POS_POL,4,4
	.comm	NUM_POLARITY_CHECKS,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
