	.file	"extr_fsl_sai.c_fsl_sai_trigger.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	fsl_sai_trigger, @function
fsl_sai_trigger:
.LFB0:
	.cfi_startproc
	endbr64
	push	r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	push	r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	push	r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	mov	r13, rdi
	mov	rdi, rdx
	push	r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	push	rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	mov	ebp, esi
	push	rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	sub	rsp, 40
	.cfi_def_cfa_offset 96
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR 24[rsp], rax
	xor	eax, eax
	call	snd_soc_dai_get_drvdata@PLT
	mov	r15, QWORD PTR 0[r13]
	xor	r13d, r13d
	mov	r14, QWORD PTR SNDRV_PCM_STREAM_PLAYBACK[rip]
	mov	rbx, rax
	mov	rax, QWORD PTR 16[rax]
	mov	rdx, QWORD PTR TX[rip]
	cmp	r15, r14
	mov	r12d, DWORD PTR [rax]
	mov	rax, QWORD PTR 8[rbx]
	sete	r13b
	cmp	QWORD PTR [rax+rdx*8], 0
	jne	.L2
	mov	edx, DWORD PTR FSL_SAI_CR2_SYNC[rip]
	xor	ecx, ecx
.L3:
	mov	edi, r12d
	mov	DWORD PTR 12[rsp], edx
	mov	DWORD PTR 8[rsp], ecx
	call	FSL_SAI_TCR2@PLT
	mov	edx, DWORD PTR 12[rsp]
	mov	ecx, DWORD PTR 8[rsp]
	mov	edi, DWORD PTR [rbx]
	mov	esi, eax
	call	regmap_update_bits@PLT
	mov	rax, QWORD PTR 8[rbx]
	mov	rdx, QWORD PTR RX[rip]
	cmp	QWORD PTR [rax+rdx*8], 0
	jne	.L4
	mov	edx, DWORD PTR FSL_SAI_CR2_SYNC[rip]
	xor	ecx, ecx
.L5:
	mov	edi, r12d
	mov	DWORD PTR 12[rsp], edx
	mov	DWORD PTR 8[rsp], ecx
	call	FSL_SAI_RCR2@PLT
	mov	ecx, DWORD PTR 8[rsp]
	mov	edx, DWORD PTR 12[rsp]
	mov	edi, DWORD PTR [rbx]
	mov	esi, eax
	call	regmap_update_bits@PLT
	cmp	ebp, 132
	jg	.L6
	cmp	ebp, 129
	jg	.L7
	add	ebp, -128
	cmp	ebp, 1
	ja	.L8
.L9:
	mov	ebp, DWORD PTR FSL_SAI_CSR_FRDE[rip]
	mov	esi, r12d
	mov	edi, r13d
	call	FSL_SAI_xCSR@PLT
	mov	edi, DWORD PTR [rbx]
	xor	ecx, ecx
	mov	edx, ebp
	mov	esi, eax
	call	regmap_update_bits@PLT
	mov	ebp, DWORD PTR FSL_SAI_CSR_xIE_MASK[rip]
	mov	esi, r12d
	mov	edi, r13d
	call	FSL_SAI_xCSR@PLT
	mov	edi, DWORD PTR [rbx]
	xor	ecx, ecx
	mov	edx, ebp
	mov	esi, eax
	call	regmap_update_bits@PLT
	xor	edi, edi
	cmp	r15, r14
	mov	esi, r12d
	setne	dil
	lea	r14, 20[rsp]
	call	FSL_SAI_xCSR@PLT
	mov	edi, DWORD PTR [rbx]
	mov	rdx, r14
	mov	esi, eax
	call	regmap_read@PLT
	mov	eax, DWORD PTR 20[rsp]
	test	DWORD PTR FSL_SAI_CSR_FRDE[rip], eax
	je	.L11
.L14:
	xor	r13d, r13d
.L1:
	mov	rax, QWORD PTR 24[rsp]
	xor	rax, QWORD PTR fs:40
	jne	.L24
	add	rsp, 40
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	mov	eax, r13d
	pop	rbx
	.cfi_def_cfa_offset 48
	pop	rbp
	.cfi_def_cfa_offset 40
	pop	r12
	.cfi_def_cfa_offset 32
	pop	r13
	.cfi_def_cfa_offset 24
	pop	r14
	.cfi_def_cfa_offset 16
	pop	r15
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L6:
	.cfi_restore_state
	cmp	ebp, 133
	je	.L9
.L8:
	mov	r13d, DWORD PTR EINVAL[rip]
	neg	r13d
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L2:
	mov	ecx, DWORD PTR FSL_SAI_CR2_SYNC[rip]
	mov	edx, ecx
	jmp	.L3
	.p2align 4,,10
	.p2align 3
.L4:
	mov	ecx, DWORD PTR FSL_SAI_CR2_SYNC[rip]
	mov	edx, ecx
	jmp	.L5
	.p2align 4,,10
	.p2align 3
.L7:
	mov	r14d, DWORD PTR FSL_SAI_CSR_FRDE[rip]
	mov	edi, r13d
	mov	esi, r12d
	call	FSL_SAI_xCSR@PLT
	mov	edi, DWORD PTR [rbx]
	mov	ecx, r14d
	mov	edx, r14d
	mov	esi, eax
	call	regmap_update_bits@PLT
	mov	r14d, DWORD PTR FSL_SAI_CSR_TERE[rip]
	mov	edi, r12d
	call	FSL_SAI_RCSR@PLT
	mov	edi, DWORD PTR [rbx]
	mov	ecx, r14d
	mov	edx, r14d
	mov	esi, eax
	call	regmap_update_bits@PLT
	mov	r14d, DWORD PTR FSL_SAI_CSR_TERE[rip]
	mov	edi, r12d
	call	FSL_SAI_TCSR@PLT
	mov	edi, DWORD PTR [rbx]
	mov	ecx, r14d
	mov	edx, r14d
	mov	esi, eax
	call	regmap_update_bits@PLT
	mov	edi, r13d
	mov	esi, r12d
	xor	r13d, r13d
	mov	r15d, DWORD PTR FSL_SAI_FLAGS[rip]
	mov	r14d, DWORD PTR FSL_SAI_CSR_xIE_MASK[rip]
	call	FSL_SAI_xCSR@PLT
	mov	edi, DWORD PTR [rbx]
	mov	esi, eax
	mov	ecx, r15d
	mov	edx, r14d
	call	regmap_update_bits@PLT
	jmp	.L1
	.p2align 4,,10
	.p2align 3
.L11:
	mov	r15d, DWORD PTR FSL_SAI_CSR_TERE[rip]
	mov	edi, r12d
	mov	ebp, 99
	call	FSL_SAI_TCSR@PLT
	mov	edi, DWORD PTR [rbx]
	xor	ecx, ecx
	mov	edx, r15d
	mov	esi, eax
	call	regmap_update_bits@PLT
	mov	r15d, DWORD PTR FSL_SAI_CSR_TERE[rip]
	mov	edi, r12d
	call	FSL_SAI_RCSR@PLT
	mov	edi, DWORD PTR [rbx]
	xor	ecx, ecx
	mov	edx, r15d
	mov	esi, eax
	call	regmap_update_bits@PLT
	mov	edi, 10
	call	udelay@PLT
	mov	esi, r12d
	mov	edi, r13d
	call	FSL_SAI_xCSR@PLT
	mov	edi, DWORD PTR [rbx]
	mov	rdx, r14
	mov	esi, eax
	call	regmap_read@PLT
	jmp	.L12
	.p2align 4,,10
	.p2align 3
.L15:
	mov	edi, 10
	call	udelay@PLT
	mov	esi, r12d
	mov	edi, r13d
	call	FSL_SAI_xCSR@PLT
	mov	edi, DWORD PTR [rbx]
	mov	rdx, r14
	mov	esi, eax
	call	regmap_read@PLT
	sub	ebp, 1
	je	.L16
.L12:
	mov	eax, DWORD PTR 20[rsp]
	test	DWORD PTR FSL_SAI_CSR_TERE[rip], eax
	jne	.L15
.L16:
	mov	r13d, DWORD PTR FSL_SAI_CSR_FR[rip]
	mov	edi, r12d
	call	FSL_SAI_TCSR@PLT
	mov	edi, DWORD PTR [rbx]
	mov	ecx, r13d
	mov	edx, r13d
	mov	esi, eax
	call	regmap_update_bits@PLT
	mov	r13d, DWORD PTR FSL_SAI_CSR_FR[rip]
	mov	edi, r12d
	call	FSL_SAI_RCSR@PLT
	mov	edi, DWORD PTR [rbx]
	mov	ecx, r13d
	mov	edx, r13d
	mov	esi, eax
	call	regmap_update_bits@PLT
	mov	r13d, DWORD PTR 4[rbx]
	test	r13d, r13d
	jne	.L14
	mov	r14d, DWORD PTR FSL_SAI_CSR_SR[rip]
	mov	edi, r12d
	call	FSL_SAI_TCSR@PLT
	mov	edi, DWORD PTR [rbx]
	mov	edx, r14d
	mov	esi, eax
	call	regmap_write@PLT
	mov	r14d, DWORD PTR FSL_SAI_CSR_SR[rip]
	mov	edi, r12d
	call	FSL_SAI_RCSR@PLT
	mov	edi, DWORD PTR [rbx]
	mov	edx, r14d
	mov	esi, eax
	call	regmap_write@PLT
	mov	edi, r12d
	call	FSL_SAI_TCSR@PLT
	mov	edi, DWORD PTR [rbx]
	xor	edx, edx
	mov	esi, eax
	call	regmap_write@PLT
	mov	edi, r12d
	call	FSL_SAI_RCSR@PLT
	mov	edi, DWORD PTR [rbx]
	xor	edx, edx
	mov	esi, eax
	call	regmap_write@PLT
	jmp	.L1
.L24:
	call	__stack_chk_fail@PLT
	.cfi_endproc
.LFE0:
	.size	fsl_sai_trigger, .-fsl_sai_trigger
	.comm	TX,8,8
	.comm	SNDRV_PCM_STREAM_PLAYBACK,8,8
	.comm	RX,8,8
	.comm	FSL_SAI_FLAGS,4,4
	.comm	FSL_SAI_CSR_xIE_MASK,4,4
	.comm	FSL_SAI_CSR_TERE,4,4
	.comm	FSL_SAI_CSR_SR,4,4
	.comm	FSL_SAI_CSR_FRDE,4,4
	.comm	FSL_SAI_CSR_FR,4,4
	.comm	FSL_SAI_CR2_SYNC,4,4
	.comm	EINVAL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_fsl_sai.c_fsl_sai_trigger.c"
	.text
	.section	.rodata.cst4,"aM",%progbits,4
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	fsl_sai_trigger, %function
fsl_sai_trigger:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	ldr	r3, .L27
	sub	sp, sp, #12
	mov	r7, r0
	mov	r0, r2
	mov	r5, r1
	ldr	r3, [r3]
	str	r3, [sp, #4]
	mov	r3,#0
	bl	snd_soc_dai_get_drvdata
	mov	r4, r0
	ldr	r2, [r0, #12]
	ldr	r3, .L27+4
	ldr	r6, [r2]
	ldr	fp, [r4]
	mov	r0, r6
	ldr	r8, [r3]
	ldr	r9, [r7]
	bl	FSL_SAI_TCR2
	ldr	r2, .L27+8
	ldr	r3, [r4, #8]
	ldr	r2, [r2]
	ldr	r10, .L27+12
	ldr	r3, [r3, r2, lsl #2]
	ldr	r2, [r10]
	cmp	r3, #0
	movne	r3, r2
	mov	r1, r0
	mov	r0, fp
	bl	regmap_update_bits
	mov	r0, r6
	ldr	fp, [r4]
	bl	FSL_SAI_RCR2
	sub	r7, r9, r8
	clz	r7, r7
	ldr	r2, .L27+16
	mov	r1, r0
	ldr	r3, [r4, #8]
	ldr	r0, [r2]
	ldr	r2, [r10]
	ldr	r3, [r3, r0, lsl #2]
	mov	r0, fp
	cmp	r3, #0
	movne	r3, r2
	bl	regmap_update_bits
	cmp	r5, #132
	lsr	r7, r7, #5
	bgt	.L4
	cmp	r5, #129
	bgt	.L5
	sub	r5, r5, #128
	cmp	r5, #1
	bhi	.L6
.L7:
	mov	r1, r6
	mov	r0, r7
	ldr	r10, [r4]
	bl	FSL_SAI_xCSR
	ldr	r5, .L27+20
	mov	r1, r0
	ldr	r2, [r5]
	mov	r3, #0
	mov	r0, r10
	bl	regmap_update_bits
	mov	r1, r6
	mov	r0, r7
	ldr	r10, [r4]
	bl	FSL_SAI_xCSR
	ldr	r3, .L27+24
	mov	r1, r0
	ldr	r2, [r3]
	mov	r0, r10
	mov	r3, #0
	bl	regmap_update_bits
	subs	r0, r9, r8
	movne	r0, #1
	mov	r1, r6
	ldr	r8, [r4]
	bl	FSL_SAI_xCSR
	mov	r2, sp
	mov	r1, r0
	mov	r0, r8
	bl	regmap_read
	ldr	r5, [r5]
	ldr	r3, [sp]
	ands	r5, r3, r5
	beq	.L9
.L12:
	mov	r5, #0
.L1:
	ldr	r3, .L27
	ldr	r2, [r3]
	ldr	r3, [sp, #4]
	eors	r2, r3, r2
	mov	r3, #0
	bne	.L26
	mov	r0, r5
	add	sp, sp, #12
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L4:
	cmp	r5, #133
	beq	.L7
.L6:
	ldr	r3, .L27+28
	ldr	r5, [r3]
	rsb	r5, r5, #0
	b	.L1
.L5:
	mov	r1, r6
	mov	r0, r7
	ldr	r5, [r4]
	bl	FSL_SAI_xCSR
	ldr	r3, .L27+20
	mov	r1, r0
	ldr	r3, [r3]
	mov	r0, r5
	mov	r2, r3
	bl	regmap_update_bits
	mov	r0, r6
	ldr	r8, [r4]
	bl	FSL_SAI_RCSR
	ldr	r5, .L27+32
	mov	r1, r0
	ldr	r3, [r5]
	mov	r0, r8
	mov	r2, r3
	bl	regmap_update_bits
	mov	r0, r6
	ldr	r8, [r4]
	bl	FSL_SAI_TCSR
	ldr	r3, [r5]
	mov	r1, r0
	mov	r2, r3
	mov	r0, r8
	bl	regmap_update_bits
	mov	r1, r6
	mov	r0, r7
	ldr	r4, [r4]
	bl	FSL_SAI_xCSR
	ldr	r3, .L27+36
	ldr	r2, .L27+24
	mov	r1, r0
	ldr	r3, [r3]
	mov	r0, r4
	ldr	r2, [r2]
	bl	regmap_update_bits
	mov	r5, #0
	b	.L1
.L9:
	mov	r0, r6
	ldr	r8, [r4]
	bl	FSL_SAI_TCSR
	ldr	r9, .L27+32
	mov	r1, r0
	mov	r3, r5
	ldr	r2, [r9]
	mov	r0, r8
	bl	regmap_update_bits
	mov	r0, r6
	ldr	r8, [r4]
	bl	FSL_SAI_RCSR
	mov	r3, r5
	mov	r1, r0
	ldr	r2, [r9]
	mov	r0, r8
	bl	regmap_update_bits
	mov	r0, #10
	bl	udelay
	mov	r1, r6
	mov	r0, r7
	ldr	r5, [r4]
	bl	FSL_SAI_xCSR
	mov	r2, sp
	mov	r1, r0
	mov	r0, r5
	bl	regmap_read
	mov	r5, #99
	b	.L10
.L13:
	mov	r0, #10
	bl	udelay
	mov	r1, r6
	mov	r0, r7
	ldr	r8, [r4]
	bl	FSL_SAI_xCSR
	mov	r2, sp
	mov	r1, r0
	mov	r0, r8
	bl	regmap_read
	subs	r5, r5, #1
	beq	.L14
.L10:
	ldr	r2, [sp]
	ldr	r3, [r9]
	tst	r2, r3
	bne	.L13
.L14:
	mov	r0, r6
	ldr	r7, [r4]
	bl	FSL_SAI_TCSR
	ldr	r5, .L27+40
	mov	r1, r0
	ldr	r3, [r5]
	mov	r0, r7
	mov	r2, r3
	bl	regmap_update_bits
	mov	r0, r6
	ldr	r7, [r4]
	bl	FSL_SAI_RCSR
	ldr	r3, [r5]
	mov	r1, r0
	mov	r2, r3
	mov	r0, r7
	bl	regmap_update_bits
	ldr	r5, [r4, #4]
	cmp	r5, #0
	bne	.L12
	mov	r0, r6
	ldr	r8, [r4]
	bl	FSL_SAI_TCSR
	ldr	r7, .L27+44
	mov	r1, r0
	ldr	r2, [r7]
	mov	r0, r8
	bl	regmap_write
	mov	r0, r6
	ldr	r8, [r4]
	bl	FSL_SAI_RCSR
	ldr	r2, [r7]
	mov	r1, r0
	mov	r0, r8
	bl	regmap_write
	mov	r0, r6
	ldr	r7, [r4]
	bl	FSL_SAI_TCSR
	mov	r2, r5
	mov	r1, r0
	mov	r0, r7
	bl	regmap_write
	mov	r0, r6
	ldr	r4, [r4]
	bl	FSL_SAI_RCSR
	mov	r2, r5
	mov	r1, r0
	mov	r0, r4
	bl	regmap_write
	b	.L1
.L26:
	bl	__stack_chk_fail
.L28:
	.align	2
.L27:
	.word	.LC0
	.word	SNDRV_PCM_STREAM_PLAYBACK
	.word	TX
	.word	FSL_SAI_CR2_SYNC
	.word	RX
	.word	FSL_SAI_CSR_FRDE
	.word	FSL_SAI_CSR_xIE_MASK
	.word	EINVAL
	.word	FSL_SAI_CSR_TERE
	.word	FSL_SAI_FLAGS
	.word	FSL_SAI_CSR_FR
	.word	FSL_SAI_CSR_SR
	.size	fsl_sai_trigger, .-fsl_sai_trigger
	.comm	TX,4,4
	.comm	SNDRV_PCM_STREAM_PLAYBACK,4,4
	.comm	RX,4,4
	.comm	FSL_SAI_FLAGS,4,4
	.comm	FSL_SAI_CSR_xIE_MASK,4,4
	.comm	FSL_SAI_CSR_TERE,4,4
	.comm	FSL_SAI_CSR_SR,4,4
	.comm	FSL_SAI_CSR_FRDE,4,4
	.comm	FSL_SAI_CSR_FR,4,4
	.comm	FSL_SAI_CR2_SYNC,4,4
	.comm	EINVAL,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
