	.file	"extr_intel_display.c_intel_init_display.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	intel_init_display, @function
intel_init_display:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	mov	rbx, QWORD PTR [rdi]
	call	HAS_DDI@PLT
	test	rax, rax
	je	.L2
	mov	eax, DWORD PTR haswell_crtc_mode_set[rip]
	mov	DWORD PTR 52[rbx], eax
	mov	eax, DWORD PTR haswell_crtc_enable[rip]
	mov	DWORD PTR 48[rbx], eax
	mov	eax, DWORD PTR haswell_crtc_disable[rip]
	mov	DWORD PTR 44[rbx], eax
	mov	eax, DWORD PTR haswell_crtc_off[rip]
	mov	DWORD PTR 40[rbx], eax
	mov	rax, QWORD PTR ironlake_update_plane[rip]
	mov	QWORD PTR 32[rbx], rax
.L3:
	mov	rdi, rbp
	call	IS_VALLEYVIEW@PLT
	test	rax, rax
	je	.L5
.L41:
	mov	eax, DWORD PTR valleyview_get_display_clock_speed[rip]
	mov	DWORD PTR 24[rbx], eax
.L6:
	mov	rdi, rbp
	call	HAS_PCH_SPLIT@PLT
	mov	rdi, rbp
	test	rax, rax
	je	.L16
	call	IS_GEN5@PLT
	test	rax, rax
	je	.L17
	mov	eax, DWORD PTR ironlake_fdi_link_train[rip]
	mov	DWORD PTR 20[rbx], eax
	mov	rax, QWORD PTR ironlake_write_eld[rip]
	mov	QWORD PTR 8[rbx], rax
.L18:
	mov	eax, DWORD PTR intel_default_queue_flip[rip]
	mov	rdi, rbp
	mov	DWORD PTR [rbx], eax
	call	INTEL_INFO@PLT
	cmp	DWORD PTR [rax], 7
	ja	.L1
	mov	eax, DWORD PTR [rax]
	lea	rdx, .L25[rip]
	movsx	rax, DWORD PTR [rdx+rax*4]
	add	rax, rdx
	notrack jmp	rax
	.section	.rodata
	.align 4
	.align 4
.L25:
	.long	.L1-.L25
	.long	.L1-.L25
	.long	.L29-.L25
	.long	.L28-.L25
	.long	.L27-.L25
	.long	.L27-.L25
	.long	.L26-.L25
	.long	.L24-.L25
	.text
	.p2align 4,,10
	.p2align 3
.L16:
	call	IS_G4X@PLT
	test	rax, rax
	je	.L18
	mov	rax, QWORD PTR g4x_write_eld[rip]
	mov	QWORD PTR 8[rbx], rax
	jmp	.L18
	.p2align 4,,10
	.p2align 3
.L24:
	mov	eax, DWORD PTR intel_gen7_queue_flip[rip]
	mov	DWORD PTR [rbx], eax
.L1:
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L2:
	.cfi_restore_state
	mov	rdi, rbp
	call	HAS_PCH_SPLIT@PLT
	test	rax, rax
	je	.L4
	mov	eax, DWORD PTR ironlake_crtc_mode_set[rip]
	mov	rdi, rbp
	mov	DWORD PTR 52[rbx], eax
	mov	eax, DWORD PTR ironlake_crtc_enable[rip]
	mov	DWORD PTR 48[rbx], eax
	mov	eax, DWORD PTR ironlake_crtc_disable[rip]
	mov	DWORD PTR 44[rbx], eax
	mov	eax, DWORD PTR ironlake_crtc_off[rip]
	mov	DWORD PTR 40[rbx], eax
	mov	rax, QWORD PTR ironlake_update_plane[rip]
	mov	QWORD PTR 32[rbx], rax
	call	IS_VALLEYVIEW@PLT
	test	rax, rax
	jne	.L41
	.p2align 4,,10
	.p2align 3
.L5:
	mov	rdi, rbp
	call	IS_I945G@PLT
	test	rax, rax
	je	.L7
.L9:
	mov	eax, DWORD PTR i945_get_display_clock_speed[rip]
	mov	DWORD PTR 24[rbx], eax
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L27:
	mov	eax, DWORD PTR intel_gen4_queue_flip[rip]
	mov	DWORD PTR [rbx], eax
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L26:
	.cfi_restore_state
	mov	eax, DWORD PTR intel_gen6_queue_flip[rip]
	mov	DWORD PTR [rbx], eax
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L29:
	.cfi_restore_state
	mov	eax, DWORD PTR intel_gen2_queue_flip[rip]
	mov	DWORD PTR [rbx], eax
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L28:
	.cfi_restore_state
	mov	eax, DWORD PTR intel_gen3_queue_flip[rip]
	mov	DWORD PTR [rbx], eax
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L4:
	.cfi_restore_state
	mov	eax, DWORD PTR i9xx_crtc_mode_set[rip]
	mov	DWORD PTR 52[rbx], eax
	mov	eax, DWORD PTR i9xx_crtc_enable[rip]
	mov	DWORD PTR 48[rbx], eax
	mov	eax, DWORD PTR i9xx_crtc_disable[rip]
	mov	DWORD PTR 44[rbx], eax
	mov	eax, DWORD PTR i9xx_crtc_off[rip]
	mov	DWORD PTR 40[rbx], eax
	mov	rax, QWORD PTR i9xx_update_plane[rip]
	mov	QWORD PTR 32[rbx], rax
	jmp	.L3
	.p2align 4,,10
	.p2align 3
.L17:
	mov	rdi, rbp
	call	IS_GEN6@PLT
	test	rax, rax
	je	.L19
	mov	eax, DWORD PTR gen6_fdi_link_train[rip]
	mov	DWORD PTR 20[rbx], eax
	mov	rax, QWORD PTR ironlake_write_eld[rip]
	mov	QWORD PTR 8[rbx], rax
	jmp	.L18
	.p2align 4,,10
	.p2align 3
.L7:
	mov	rdi, rbp
	call	IS_G33@PLT
	test	rax, rax
	je	.L8
	mov	rdi, rbp
	call	IS_PINEVIEW_M@PLT
	test	rax, rax
	je	.L9
.L8:
	mov	rdi, rbp
	call	IS_I915G@PLT
	test	rax, rax
	je	.L10
	mov	eax, DWORD PTR i915_get_display_clock_speed[rip]
	mov	DWORD PTR 24[rbx], eax
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L19:
	mov	rdi, rbp
	call	IS_IVYBRIDGE@PLT
	test	rax, rax
	je	.L20
	mov	eax, DWORD PTR ivb_manual_fdi_link_train[rip]
	mov	DWORD PTR 20[rbx], eax
	mov	rax, QWORD PTR ironlake_write_eld[rip]
	mov	QWORD PTR 8[rbx], rax
	mov	eax, DWORD PTR ivb_modeset_global_resources[rip]
	mov	DWORD PTR 16[rbx], eax
	jmp	.L18
	.p2align 4,,10
	.p2align 3
.L20:
	mov	rdi, rbp
	call	IS_HASWELL@PLT
	test	rax, rax
	je	.L18
	mov	eax, DWORD PTR hsw_fdi_link_train[rip]
	mov	DWORD PTR 20[rbx], eax
	mov	rax, QWORD PTR haswell_write_eld[rip]
	mov	QWORD PTR 8[rbx], rax
	mov	eax, DWORD PTR haswell_modeset_global_resources[rip]
	mov	DWORD PTR 16[rbx], eax
	jmp	.L18
	.p2align 4,,10
	.p2align 3
.L10:
	mov	rdi, rbp
	call	IS_I945GM@PLT
	test	rax, rax
	je	.L11
.L12:
	mov	eax, DWORD PTR i9xx_misc_get_display_clock_speed[rip]
	mov	DWORD PTR 24[rbx], eax
	jmp	.L6
.L11:
	mov	rdi, rbp
	call	IS_845G@PLT
	test	rax, rax
	jne	.L12
	mov	rdi, rbp
	call	IS_PINEVIEW_M@PLT
	test	rax, rax
	jne	.L12
	mov	rdi, rbp
	call	IS_I915GM@PLT
	test	rax, rax
	je	.L13
	mov	eax, DWORD PTR i915gm_get_display_clock_speed[rip]
	mov	DWORD PTR 24[rbx], eax
	jmp	.L6
.L13:
	mov	rdi, rbp
	call	IS_I865G@PLT
	test	rax, rax
	je	.L14
	mov	eax, DWORD PTR i865_get_display_clock_speed[rip]
	mov	DWORD PTR 24[rbx], eax
	jmp	.L6
.L14:
	mov	rdi, rbp
	call	IS_I85X@PLT
	test	rax, rax
	je	.L15
	mov	eax, DWORD PTR i855_get_display_clock_speed[rip]
	mov	DWORD PTR 24[rbx], eax
	jmp	.L6
.L15:
	mov	eax, DWORD PTR i830_get_display_clock_speed[rip]
	mov	DWORD PTR 24[rbx], eax
	jmp	.L6
	.cfi_endproc
.LFE0:
	.size	intel_init_display, .-intel_init_display
	.comm	valleyview_get_display_clock_speed,4,4
	.comm	ivb_modeset_global_resources,4,4
	.comm	ivb_manual_fdi_link_train,4,4
	.comm	ironlake_write_eld,8,8
	.comm	ironlake_update_plane,8,8
	.comm	ironlake_fdi_link_train,4,4
	.comm	ironlake_crtc_off,4,4
	.comm	ironlake_crtc_mode_set,4,4
	.comm	ironlake_crtc_enable,4,4
	.comm	ironlake_crtc_disable,4,4
	.comm	intel_gen7_queue_flip,4,4
	.comm	intel_gen6_queue_flip,4,4
	.comm	intel_gen4_queue_flip,4,4
	.comm	intel_gen3_queue_flip,4,4
	.comm	intel_gen2_queue_flip,4,4
	.comm	intel_default_queue_flip,4,4
	.comm	i9xx_update_plane,8,8
	.comm	i9xx_misc_get_display_clock_speed,4,4
	.comm	i9xx_crtc_off,4,4
	.comm	i9xx_crtc_mode_set,4,4
	.comm	i9xx_crtc_enable,4,4
	.comm	i9xx_crtc_disable,4,4
	.comm	i945_get_display_clock_speed,4,4
	.comm	i915gm_get_display_clock_speed,4,4
	.comm	i915_get_display_clock_speed,4,4
	.comm	i865_get_display_clock_speed,4,4
	.comm	i855_get_display_clock_speed,4,4
	.comm	i830_get_display_clock_speed,4,4
	.comm	hsw_fdi_link_train,4,4
	.comm	haswell_write_eld,8,8
	.comm	haswell_modeset_global_resources,4,4
	.comm	haswell_crtc_off,4,4
	.comm	haswell_crtc_mode_set,4,4
	.comm	haswell_crtc_enable,4,4
	.comm	haswell_crtc_disable,4,4
	.comm	gen6_fdi_link_train,4,4
	.comm	g4x_write_eld,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_intel_display.c_intel_init_display.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	intel_init_display, %function
intel_init_display:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, lr}
	mov	r5, r0
	ldr	r4, [r0]
	bl	HAS_DDI
	cmp	r0, #0
	beq	.L2
	ldr	ip, .L44
	ldr	r0, .L44+4
	ldr	r1, .L44+8
	ldr	r2, .L44+12
	ldr	r3, .L44+16
.L40:
	ldr	r0, [r0]
	ldr	ip, [ip]
	ldr	r1, [r1]
	ldr	r2, [r2]
	ldr	r3, [r3]
	str	r0, [r4, #32]
	str	ip, [r4, #36]
	mov	r0, r5
	str	r1, [r4, #28]
	str	r2, [r4, #24]
	str	r3, [r4, #20]
	bl	IS_VALLEYVIEW
	cmp	r0, #0
	beq	.L5
	ldr	r3, .L44+20
	ldr	r3, [r3]
	str	r3, [r4, #16]
.L6:
	mov	r0, r5
	bl	HAS_PCH_SPLIT
	cmp	r0, #0
	mov	r0, r5
	beq	.L16
	bl	IS_GEN5
	cmp	r0, #0
	beq	.L17
	ldr	r2, .L44+24
.L41:
	ldr	r3, .L44+28
	ldr	r2, [r2]
	ldr	r3, [r3]
	str	r2, [r4, #12]
	str	r3, [r4, #4]
	b	.L18
.L16:
	bl	IS_G4X
	cmp	r0, #0
	ldrne	r3, .L44+32
	ldrne	r3, [r3]
	strne	r3, [r4, #4]
.L18:
	ldr	r3, .L44+36
	mov	r0, r5
	ldr	r3, [r3]
	str	r3, [r4]
	bl	INTEL_INFO
	ldr	r3, [r0]
	sub	r3, r3, #2
	cmp	r3, #5
	ldrls	pc, [pc, r3, asl #2]
	b	.L1
.L25:
	.word	.L29
	.word	.L28
	.word	.L27
	.word	.L27
	.word	.L26
	.word	.L24
.L24:
	ldr	r3, .L44+40
	ldr	r3, [r3]
	str	r3, [r4]
.L1:
	pop	{r4, r5, r6, pc}
.L5:
	mov	r0, r5
	bl	IS_I945G
	cmp	r0, #0
	beq	.L7
.L9:
	ldr	r3, .L44+44
	ldr	r3, [r3]
	str	r3, [r4, #16]
	b	.L6
.L2:
	mov	r0, r5
	bl	HAS_PCH_SPLIT
	cmp	r0, #0
	ldrne	ip, .L44+48
	ldrne	r0, .L44+52
	ldrne	r1, .L44+56
	ldrne	r2, .L44+60
	ldrne	r3, .L44+16
	ldreq	ip, .L44+64
	ldreq	r0, .L44+68
	ldreq	r1, .L44+72
	ldreq	r2, .L44+76
	ldreq	r3, .L44+80
	b	.L40
.L27:
	ldr	r3, .L44+84
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, r5, r6, pc}
.L26:
	ldr	r3, .L44+88
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, r5, r6, pc}
.L29:
	ldr	r3, .L44+92
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, r5, r6, pc}
.L28:
	ldr	r3, .L44+96
	ldr	r3, [r3]
	str	r3, [r4]
	pop	{r4, r5, r6, pc}
.L17:
	mov	r0, r5
	bl	IS_GEN6
	cmp	r0, #0
	beq	.L19
	ldr	r2, .L44+100
	b	.L41
.L7:
	mov	r0, r5
	bl	IS_G33
	cmp	r0, #0
	beq	.L8
	mov	r0, r5
	bl	IS_PINEVIEW_M
	cmp	r0, #0
	beq	.L9
.L8:
	mov	r0, r5
	bl	IS_I915G
	cmp	r0, #0
	beq	.L10
	ldr	r3, .L44+104
	ldr	r3, [r3]
	str	r3, [r4, #16]
	b	.L6
.L19:
	mov	r0, r5
	bl	IS_IVYBRIDGE
	cmp	r0, #0
	beq	.L20
	ldr	r1, .L44+108
	ldr	r2, .L44+28
	ldr	r3, .L44+112
.L42:
	ldr	r1, [r1]
	ldr	r2, [r2]
	ldr	r3, [r3]
	str	r1, [r4, #12]
	stmib	r4, {r2, r3}
	b	.L18
.L20:
	mov	r0, r5
	bl	IS_HASWELL
	cmp	r0, #0
	beq	.L18
	ldr	r1, .L44+116
	ldr	r2, .L44+120
	ldr	r3, .L44+124
	b	.L42
.L10:
	mov	r0, r5
	bl	IS_I945GM
	cmp	r0, #0
	beq	.L11
.L12:
	ldr	r3, .L44+128
	ldr	r3, [r3]
	str	r3, [r4, #16]
	b	.L6
.L11:
	mov	r0, r5
	bl	IS_845G
	cmp	r0, #0
	bne	.L12
	mov	r0, r5
	bl	IS_PINEVIEW_M
	cmp	r0, #0
	bne	.L12
	mov	r0, r5
	bl	IS_I915GM
	cmp	r0, #0
	ldrne	r3, .L44+132
	ldrne	r3, [r3]
	strne	r3, [r4, #16]
	bne	.L6
.L13:
	mov	r0, r5
	bl	IS_I865G
	cmp	r0, #0
	ldrne	r3, .L44+136
	ldrne	r3, [r3]
	strne	r3, [r4, #16]
	bne	.L6
.L14:
	mov	r0, r5
	bl	IS_I85X
	cmp	r0, #0
	ldrne	r3, .L44+140
	ldreq	r3, .L44+144
	ldr	r3, [r3]
	str	r3, [r4, #16]
	b	.L6
.L45:
	.align	2
.L44:
	.word	haswell_crtc_mode_set
	.word	haswell_crtc_enable
	.word	haswell_crtc_disable
	.word	haswell_crtc_off
	.word	ironlake_update_plane
	.word	valleyview_get_display_clock_speed
	.word	ironlake_fdi_link_train
	.word	ironlake_write_eld
	.word	g4x_write_eld
	.word	intel_default_queue_flip
	.word	intel_gen7_queue_flip
	.word	i945_get_display_clock_speed
	.word	ironlake_crtc_mode_set
	.word	ironlake_crtc_enable
	.word	ironlake_crtc_disable
	.word	ironlake_crtc_off
	.word	i9xx_crtc_mode_set
	.word	i9xx_crtc_enable
	.word	i9xx_crtc_disable
	.word	i9xx_crtc_off
	.word	i9xx_update_plane
	.word	intel_gen4_queue_flip
	.word	intel_gen6_queue_flip
	.word	intel_gen2_queue_flip
	.word	intel_gen3_queue_flip
	.word	gen6_fdi_link_train
	.word	i915_get_display_clock_speed
	.word	ivb_manual_fdi_link_train
	.word	ivb_modeset_global_resources
	.word	hsw_fdi_link_train
	.word	haswell_write_eld
	.word	haswell_modeset_global_resources
	.word	i9xx_misc_get_display_clock_speed
	.word	i915gm_get_display_clock_speed
	.word	i865_get_display_clock_speed
	.word	i855_get_display_clock_speed
	.word	i830_get_display_clock_speed
	.size	intel_init_display, .-intel_init_display
	.comm	valleyview_get_display_clock_speed,4,4
	.comm	ivb_modeset_global_resources,4,4
	.comm	ivb_manual_fdi_link_train,4,4
	.comm	ironlake_write_eld,4,4
	.comm	ironlake_update_plane,4,4
	.comm	ironlake_fdi_link_train,4,4
	.comm	ironlake_crtc_off,4,4
	.comm	ironlake_crtc_mode_set,4,4
	.comm	ironlake_crtc_enable,4,4
	.comm	ironlake_crtc_disable,4,4
	.comm	intel_gen7_queue_flip,4,4
	.comm	intel_gen6_queue_flip,4,4
	.comm	intel_gen4_queue_flip,4,4
	.comm	intel_gen3_queue_flip,4,4
	.comm	intel_gen2_queue_flip,4,4
	.comm	intel_default_queue_flip,4,4
	.comm	i9xx_update_plane,4,4
	.comm	i9xx_misc_get_display_clock_speed,4,4
	.comm	i9xx_crtc_off,4,4
	.comm	i9xx_crtc_mode_set,4,4
	.comm	i9xx_crtc_enable,4,4
	.comm	i9xx_crtc_disable,4,4
	.comm	i945_get_display_clock_speed,4,4
	.comm	i915gm_get_display_clock_speed,4,4
	.comm	i915_get_display_clock_speed,4,4
	.comm	i865_get_display_clock_speed,4,4
	.comm	i855_get_display_clock_speed,4,4
	.comm	i830_get_display_clock_speed,4,4
	.comm	hsw_fdi_link_train,4,4
	.comm	haswell_write_eld,4,4
	.comm	haswell_modeset_global_resources,4,4
	.comm	haswell_crtc_off,4,4
	.comm	haswell_crtc_mode_set,4,4
	.comm	haswell_crtc_enable,4,4
	.comm	haswell_crtc_disable,4,4
	.comm	gen6_fdi_link_train,4,4
	.comm	g4x_write_eld,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
