	.file	"extr_spi-synquacer.c_synquacer_spi_enable.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	synquacer_spi_enable, @function
synquacer_spi_enable:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	call	spi_master_get_devdata@PLT
	xor	edi, edi
	mov	rsi, QWORD PTR SYNQUACER_HSSPI_REG_MCTRL[rip]
	mov	rbp, rax
	add	rsi, QWORD PTR 8[rax]
	call	writel@PLT
	xor	esi, esi
	mov	rdi, rbp
	call	synquacer_spi_wait_status_update@PLT
	test	eax, eax
	js	.L1
	mov	rsi, QWORD PTR SYNQUACER_HSSPI_REG_TXE[rip]
	xor	edi, edi
	add	rsi, QWORD PTR 8[rbp]
	call	writel@PLT
	mov	rsi, QWORD PTR SYNQUACER_HSSPI_REG_RXE[rip]
	xor	edi, edi
	add	rsi, QWORD PTR 8[rbp]
	call	writel@PLT
	mov	rsi, QWORD PTR SYNQUACER_HSSPI_REG_TXC[rip]
	mov	edi, -1
	add	rsi, QWORD PTR 8[rbp]
	call	writel@PLT
	mov	rsi, QWORD PTR SYNQUACER_HSSPI_REG_RXC[rip]
	mov	edi, -1
	add	rsi, QWORD PTR 8[rbp]
	call	writel@PLT
	mov	rsi, QWORD PTR SYNQUACER_HSSPI_REG_FAULTC[rip]
	mov	edi, -1
	add	rsi, QWORD PTR 8[rbp]
	call	writel@PLT
	mov	rdi, QWORD PTR SYNQUACER_HSSPI_REG_DMCFG[rip]
	add	rdi, QWORD PTR 8[rbp]
	call	readl@PLT
	mov	edi, DWORD PTR SYNQUACER_HSSPI_DMCFG_SSDC[rip]
	or	edi, DWORD PTR SYNQUACER_HSSPI_DMCFG_MSTARTEN[rip]
	not	edi
	mov	rsi, QWORD PTR SYNQUACER_HSSPI_REG_DMCFG[rip]
	add	rsi, QWORD PTR 8[rbp]
	and	edi, eax
	call	writel@PLT
	mov	rdi, QWORD PTR SYNQUACER_HSSPI_REG_MCTRL[rip]
	add	rdi, QWORD PTR 8[rbp]
	call	readl@PLT
	mov	rcx, QWORD PTR SYNQUACER_HSSPI_CLOCK_SRC_IPCLK[rip]
	cmp	QWORD PTR 0[rbp], rcx
	je	.L7
	mov	edi, DWORD PTR SYNQUACER_HSSPI_MCTRL_CDSS[rip]
	not	edi
	and	eax, edi
.L4:
	mov	edi, DWORD PTR SYNQUACER_HSSPI_MCTRL_COMMAND_SEQUENCE_EN[rip]
	mov	rsi, QWORD PTR SYNQUACER_HSSPI_REG_MCTRL[rip]
	add	rsi, QWORD PTR 8[rbp]
	not	edi
	and	eax, edi
	mov	edi, DWORD PTR SYNQUACER_HSSPI_MCTRL_MEN[rip]
	or	edi, DWORD PTR SYNQUACER_HSSPI_MCTRL_SYNCON[rip]
	or	edi, eax
	call	writel@PLT
	mov	esi, 1
	mov	rdi, rbp
	call	synquacer_spi_wait_status_update@PLT
	mov	edx, 0
	test	eax, eax
	cmovg	eax, edx
.L1:
	pop	rbp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L7:
	.cfi_restore_state
	or	eax, DWORD PTR SYNQUACER_HSSPI_MCTRL_CDSS[rip]
	jmp	.L4
	.cfi_endproc
.LFE0:
	.size	synquacer_spi_enable, .-synquacer_spi_enable
	.comm	SYNQUACER_HSSPI_REG_TXE,8,8
	.comm	SYNQUACER_HSSPI_REG_TXC,8,8
	.comm	SYNQUACER_HSSPI_REG_RXE,8,8
	.comm	SYNQUACER_HSSPI_REG_RXC,8,8
	.comm	SYNQUACER_HSSPI_REG_MCTRL,8,8
	.comm	SYNQUACER_HSSPI_REG_FAULTC,8,8
	.comm	SYNQUACER_HSSPI_REG_DMCFG,8,8
	.comm	SYNQUACER_HSSPI_MCTRL_SYNCON,4,4
	.comm	SYNQUACER_HSSPI_MCTRL_MEN,4,4
	.comm	SYNQUACER_HSSPI_MCTRL_COMMAND_SEQUENCE_EN,4,4
	.comm	SYNQUACER_HSSPI_MCTRL_CDSS,4,4
	.comm	SYNQUACER_HSSPI_DMCFG_SSDC,4,4
	.comm	SYNQUACER_HSSPI_DMCFG_MSTARTEN,4,4
	.comm	SYNQUACER_HSSPI_CLOCK_SRC_IPCLK,8,8
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_spi-synquacer.c_synquacer_spi_enable.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	synquacer_spi_enable, %function
synquacer_spi_enable:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	push	{r4, r5, r6, lr}
	bl	spi_master_get_devdata
	mov	r4, r0
	ldr	r5, .L7
	ldr	r1, [r0, #4]
	ldr	r3, [r5]
	mov	r0, #0
	add	r1, r1, r3
	bl	writel
	mov	r0, r4
	mov	r1, #0
	bl	synquacer_spi_wait_status_update
	cmp	r0, #0
	poplt	{r4, r5, r6, pc}
	ldr	r3, .L7+4
	ldr	r1, [r4, #4]
	ldr	r3, [r3]
	mov	r0, #0
	add	r1, r1, r3
	bl	writel
	ldr	r3, .L7+8
	ldr	r1, [r4, #4]
	ldr	r3, [r3]
	mov	r0, #0
	add	r1, r1, r3
	bl	writel
	ldr	r3, .L7+12
	ldr	r1, [r4, #4]
	ldr	r3, [r3]
	mvn	r0, #0
	add	r1, r1, r3
	bl	writel
	ldr	r3, .L7+16
	ldr	r1, [r4, #4]
	ldr	r3, [r3]
	mvn	r0, #0
	add	r1, r1, r3
	bl	writel
	ldr	r3, .L7+20
	ldr	r1, [r4, #4]
	ldr	r3, [r3]
	ldr	r6, .L7+24
	add	r1, r1, r3
	mvn	r0, #0
	bl	writel
	ldr	r3, [r6]
	ldr	r0, [r4, #4]
	add	r0, r0, r3
	bl	readl
	ldr	r2, .L7+28
	ldr	r3, .L7+32
	ldr	ip, [r2]
	ldr	r3, [r3]
	ldr	r2, [r6]
	ldr	r1, [r4, #4]
	orr	r3, r3, ip
	add	r1, r1, r2
	bic	r0, r0, r3
	bl	writel
	ldr	r3, [r5]
	ldr	r0, [r4, #4]
	add	r0, r0, r3
	bl	readl
	ldr	r3, .L7+36
	ldr	r2, [r4]
	ldr	r3, [r3]
	ldr	r1, .L7+40
	cmp	r2, r3
	ldr	r3, .L7+44
	ldr	r2, .L7+48
	ldr	r3, [r3]
	ldr	ip, [r2]
	orreq	r3, r0, r3
	bicne	r3, r0, r3
	ldr	r0, .L7+52
	ldr	r2, [r5]
	ldr	lr, [r0]
	ldr	r0, [r1]
	ldr	r1, [r4, #4]
	bic	r3, r3, lr
	orr	r0, r0, ip
	add	r1, r1, r2
	orr	r0, r0, r3
	bl	writel
	mov	r0, r4
	mov	r1, #1
	bl	synquacer_spi_wait_status_update
	and	r0, r0, r0, asr #31
	pop	{r4, r5, r6, pc}
.L8:
	.align	2
.L7:
	.word	SYNQUACER_HSSPI_REG_MCTRL
	.word	SYNQUACER_HSSPI_REG_TXE
	.word	SYNQUACER_HSSPI_REG_RXE
	.word	SYNQUACER_HSSPI_REG_TXC
	.word	SYNQUACER_HSSPI_REG_RXC
	.word	SYNQUACER_HSSPI_REG_FAULTC
	.word	SYNQUACER_HSSPI_REG_DMCFG
	.word	SYNQUACER_HSSPI_DMCFG_MSTARTEN
	.word	SYNQUACER_HSSPI_DMCFG_SSDC
	.word	SYNQUACER_HSSPI_CLOCK_SRC_IPCLK
	.word	SYNQUACER_HSSPI_MCTRL_MEN
	.word	SYNQUACER_HSSPI_MCTRL_CDSS
	.word	SYNQUACER_HSSPI_MCTRL_SYNCON
	.word	SYNQUACER_HSSPI_MCTRL_COMMAND_SEQUENCE_EN
	.size	synquacer_spi_enable, .-synquacer_spi_enable
	.comm	SYNQUACER_HSSPI_REG_TXE,4,4
	.comm	SYNQUACER_HSSPI_REG_TXC,4,4
	.comm	SYNQUACER_HSSPI_REG_RXE,4,4
	.comm	SYNQUACER_HSSPI_REG_RXC,4,4
	.comm	SYNQUACER_HSSPI_REG_MCTRL,4,4
	.comm	SYNQUACER_HSSPI_REG_FAULTC,4,4
	.comm	SYNQUACER_HSSPI_REG_DMCFG,4,4
	.comm	SYNQUACER_HSSPI_MCTRL_SYNCON,4,4
	.comm	SYNQUACER_HSSPI_MCTRL_MEN,4,4
	.comm	SYNQUACER_HSSPI_MCTRL_COMMAND_SEQUENCE_EN,4,4
	.comm	SYNQUACER_HSSPI_MCTRL_CDSS,4,4
	.comm	SYNQUACER_HSSPI_DMCFG_SSDC,4,4
	.comm	SYNQUACER_HSSPI_DMCFG_MSTARTEN,4,4
	.comm	SYNQUACER_HSSPI_CLOCK_SRC_IPCLK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
