	.file	"extr_cik.c_cik_update_cg.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.globl	cik_update_cg
	.type	cik_update_cg, @function
cik_update_cg:
.LFB0:
	.cfi_startproc
	endbr64
	push	r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	mov	r12d, edx
	push	rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	mov	rbp, rdi
	push	rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	mov	ebx, esi
	test	DWORD PTR RADEON_CG_BLOCK_GFX[rip], esi
	jne	.L31
.L2:
	test	DWORD PTR RADEON_CG_BLOCK_MC[rip], ebx
	je	.L5
	mov	eax, DWORD PTR 0[rbp]
	test	DWORD PTR RADEON_IS_IGP[rip], eax
	je	.L32
.L5:
	test	DWORD PTR RADEON_CG_BLOCK_SDMA[rip], ebx
	jne	.L33
.L6:
	test	DWORD PTR RADEON_CG_BLOCK_BIF[rip], ebx
	jne	.L34
.L7:
	test	DWORD PTR RADEON_CG_BLOCK_UVD[rip], ebx
	je	.L8
	cmp	QWORD PTR 8[rbp], 0
	jne	.L35
.L8:
	test	DWORD PTR RADEON_CG_BLOCK_HDP[rip], ebx
	jne	.L36
.L9:
	test	DWORD PTR RADEON_CG_BLOCK_VCE[rip], ebx
	jne	.L37
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	ret
	.p2align 4,,10
	.p2align 3
.L31:
	.cfi_restore_state
	xor	esi, esi
	call	cik_enable_gui_idle_interrupt@PLT
	test	r12d, r12d
	jne	.L38
	xor	esi, esi
	mov	rdi, rbp
	call	cik_enable_cgcg@PLT
	xor	esi, esi
	mov	rdi, rbp
	call	cik_enable_mgcg@PLT
.L4:
	mov	esi, 1
	mov	rdi, rbp
	call	cik_enable_gui_idle_interrupt@PLT
	jmp	.L2
	.p2align 4,,10
	.p2align 3
.L34:
	mov	esi, r12d
	mov	rdi, rbp
	call	cik_enable_bif_mgls@PLT
	jmp	.L7
	.p2align 4,,10
	.p2align 3
.L33:
	mov	esi, r12d
	mov	rdi, rbp
	call	cik_enable_sdma_mgcg@PLT
	mov	esi, r12d
	mov	rdi, rbp
	call	cik_enable_sdma_mgls@PLT
	jmp	.L6
	.p2align 4,,10
	.p2align 3
.L37:
	pop	rbx
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	mov	esi, r12d
	mov	rdi, rbp
	pop	rbp
	.cfi_def_cfa_offset 16
	pop	r12
	.cfi_def_cfa_offset 8
	jmp	vce_v2_0_enable_mgcg@PLT
	.p2align 4,,10
	.p2align 3
.L36:
	.cfi_restore_state
	mov	esi, r12d
	mov	rdi, rbp
	call	cik_enable_hdp_mgcg@PLT
	mov	esi, r12d
	mov	rdi, rbp
	call	cik_enable_hdp_ls@PLT
	jmp	.L9
	.p2align 4,,10
	.p2align 3
.L38:
	mov	rdi, rbp
	mov	esi, 1
	call	cik_enable_mgcg@PLT
	mov	esi, 1
	mov	rdi, rbp
	call	cik_enable_cgcg@PLT
	jmp	.L4
	.p2align 4,,10
	.p2align 3
.L32:
	mov	esi, r12d
	mov	rdi, rbp
	call	cik_enable_mc_mgcg@PLT
	mov	esi, r12d
	mov	rdi, rbp
	call	cik_enable_mc_ls@PLT
	jmp	.L5
	.p2align 4,,10
	.p2align 3
.L35:
	mov	esi, r12d
	mov	rdi, rbp
	call	cik_enable_uvd_mgcg@PLT
	jmp	.L8
	.cfi_endproc
.LFE0:
	.size	cik_update_cg, .-cik_update_cg
	.comm	RADEON_IS_IGP,4,4
	.comm	RADEON_CG_BLOCK_VCE,4,4
	.comm	RADEON_CG_BLOCK_UVD,4,4
	.comm	RADEON_CG_BLOCK_SDMA,4,4
	.comm	RADEON_CG_BLOCK_MC,4,4
	.comm	RADEON_CG_BLOCK_HDP,4,4
	.comm	RADEON_CG_BLOCK_GFX,4,4
	.comm	RADEON_CG_BLOCK_BIF,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_cik.c_cik_update_cg.c"
	.text
	.align	2
	.global	cik_update_cg
	.syntax unified
	.arm
	.fpu softvfp
	.type	cik_update_cg, %function
cik_update_cg:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	ldr	r3, .L41
	push	{r4, r5, r6, lr}
	ldr	r3, [r3]
	mov	r4, r1
	tst	r1, r3
	mov	r6, r2
	mov	r5, r0
	bne	.L34
.L2:
	ldr	r3, .L41+4
	ldr	r3, [r3]
	tst	r4, r3
	beq	.L5
	ldr	r3, .L41+8
	ldr	r2, [r5]
	ldr	r3, [r3]
	tst	r2, r3
	beq	.L35
.L5:
	ldr	r3, .L41+12
	ldr	r3, [r3]
	tst	r4, r3
	bne	.L36
.L6:
	ldr	r3, .L41+16
	ldr	r3, [r3]
	tst	r4, r3
	bne	.L37
.L7:
	ldr	r3, .L41+20
	ldr	r3, [r3]
	tst	r4, r3
	beq	.L8
	ldr	r3, [r5, #4]
	cmp	r3, #0
	bne	.L38
.L8:
	ldr	r3, .L41+24
	ldr	r3, [r3]
	tst	r4, r3
	bne	.L39
.L9:
	ldr	r3, .L41+28
	ldr	r3, [r3]
	tst	r4, r3
	popeq	{r4, r5, r6, pc}
	mov	r1, r6
	mov	r0, r5
	pop	{r4, r5, r6, lr}
	b	vce_v2_0_enable_mgcg
.L39:
	mov	r1, r6
	mov	r0, r5
	bl	cik_enable_hdp_mgcg
	mov	r1, r6
	mov	r0, r5
	bl	cik_enable_hdp_ls
	b	.L9
.L34:
	mov	r1, #0
	bl	cik_enable_gui_idle_interrupt
	cmp	r6, #0
	bne	.L40
	mov	r1, r6
	mov	r0, r5
	bl	cik_enable_cgcg
	mov	r1, r6
	mov	r0, r5
	bl	cik_enable_mgcg
.L4:
	mov	r1, #1
	mov	r0, r5
	bl	cik_enable_gui_idle_interrupt
	b	.L2
.L37:
	mov	r1, r6
	mov	r0, r5
	bl	cik_enable_bif_mgls
	b	.L7
.L36:
	mov	r1, r6
	mov	r0, r5
	bl	cik_enable_sdma_mgcg
	mov	r1, r6
	mov	r0, r5
	bl	cik_enable_sdma_mgls
	b	.L6
.L40:
	mov	r1, #1
	mov	r0, r5
	bl	cik_enable_mgcg
	mov	r1, #1
	mov	r0, r5
	bl	cik_enable_cgcg
	b	.L4
.L35:
	mov	r1, r6
	mov	r0, r5
	bl	cik_enable_mc_mgcg
	mov	r1, r6
	mov	r0, r5
	bl	cik_enable_mc_ls
	b	.L5
.L38:
	mov	r1, r6
	mov	r0, r5
	bl	cik_enable_uvd_mgcg
	b	.L8
.L42:
	.align	2
.L41:
	.word	RADEON_CG_BLOCK_GFX
	.word	RADEON_CG_BLOCK_MC
	.word	RADEON_IS_IGP
	.word	RADEON_CG_BLOCK_SDMA
	.word	RADEON_CG_BLOCK_BIF
	.word	RADEON_CG_BLOCK_UVD
	.word	RADEON_CG_BLOCK_HDP
	.word	RADEON_CG_BLOCK_VCE
	.size	cik_update_cg, .-cik_update_cg
	.comm	RADEON_IS_IGP,4,4
	.comm	RADEON_CG_BLOCK_VCE,4,4
	.comm	RADEON_CG_BLOCK_UVD,4,4
	.comm	RADEON_CG_BLOCK_SDMA,4,4
	.comm	RADEON_CG_BLOCK_MC,4,4
	.comm	RADEON_CG_BLOCK_HDP,4,4
	.comm	RADEON_CG_BLOCK_GFX,4,4
	.comm	RADEON_CG_BLOCK_BIF,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
