	.file	"extr_gfx_v6_0.c_gfx_v6_0_constants_init.c"
	.intel_syntax noprefix
	.text
	.p2align 4
	.type	gfx_v6_0_constants_init, @function
gfx_v6_0_constants_init:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	push	rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	mov	rbx, rdi
	sub	rsp, 8
	.cfi_def_cfa_offset 32
	mov	eax, DWORD PTR [rdi]
	add	eax, -128
	cmp	eax, 4
	ja	.L2
	lea	rdx, .L4[rip]
	movsx	rax, DWORD PTR [rdx+rax*4]
	add	rax, rdx
	notrack jmp	rax
	.section	.rodata
	.align 4
	.align 4
.L4:
	.long	.L8-.L4
	.long	.L7-.L4
	.long	.L6-.L4
	.long	.L5-.L4
	.long	.L3-.L4
	.text
	.p2align 4,,10
	.p2align 3
.L5:
	movabs	rax, 25769803780
	mov	DWORD PTR 4[rdi], 1
	mov	QWORD PTR 8[rdi], rax
	movabs	rax, 8589934593
	mov	QWORD PTR 16[rdi], rax
	movabs	rax, 1099511627780
	mov	QWORD PTR 24[rdi], rax
	movabs	rax, 34359738384
.L22:
	mov	QWORD PTR 32[rbx], rax
	mov	ebp, DWORD PTR VERDE_GB_ADDR_CONFIG_GOLDEN[rip]
	movabs	rax, 274877906976
	mov	QWORD PTR 40[rbx], rax
	movabs	rax, 1305670058032
	mov	QWORD PTR 48[rbx], rax
.L9:
	mov	ecx, DWORD PTR GRBM_CNTL__READ_TIMEOUT__SHIFT[rip]
	mov	rdi, QWORD PTR mmGRBM_CNTL[rip]
	mov	esi, 255
	sal	esi, cl
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmSRBM_INT_CNTL[rip]
	mov	esi, 1
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmSRBM_INT_ACK[rip]
	mov	esi, 1
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmBIF_FB_EN[rip]
	mov	esi, DWORD PTR BIF_FB_EN__FB_READ_EN_MASK[rip]
	or	esi, DWORD PTR BIF_FB_EN__FB_WRITE_EN_MASK[rip]
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmMC_SHARED_CHMAP[rip]
	call	RREG32@PLT
	mov	rdi, QWORD PTR mmMC_ARB_RAMCFG[rip]
	call	RREG32@PLT
	mov	ecx, DWORD PTR MC_ARB_RAMCFG__NOOFCOLS__SHIFT[rip]
	mov	edx, DWORD PTR 8[rbx]
	mov	DWORD PTR 64[rbx], 256
	mov	DWORD PTR 56[rbx], eax
	and	eax, DWORD PTR MC_ARB_RAMCFG__NOOFCOLS_MASK[rip]
	sar	eax, cl
	mov	DWORD PTR 60[rbx], edx
	lea	ecx, 8[rax]
	mov	eax, 4
	sal	eax, cl
	cmp	eax, 5119
	jg	.L10
	test	eax, eax
	lea	edx, 1023[rax]
	mov	esi, DWORD PTR GB_ADDR_CONFIG__ROW_SIZE_MASK[rip]
	mov	DWORD PTR 80[rbx], 64
	cmovs	eax, edx
	movabs	rdx, 4294967328
	not	esi
	mov	QWORD PTR 72[rbx], rdx
	sar	eax, 10
	and	esi, ebp
	mov	DWORD PTR 68[rbx], eax
	cmp	eax, 2
	jne	.L24
	mov	ecx, DWORD PTR GB_ADDR_CONFIG__ROW_SIZE__SHIFT[rip]
	mov	eax, 1
	sal	eax, cl
	or	esi, eax
.L14:
	mov	ebp, DWORD PTR GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK[rip]
	not	ebp
	and	ebp, esi
	cmp	DWORD PTR 4[rbx], 2
	jne	.L15
	mov	ecx, DWORD PTR GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT[rip]
	mov	eax, 1
	sal	eax, cl
	or	ebp, eax
.L15:
	mov	DWORD PTR 84[rbx], ebp
	mov	rdi, QWORD PTR mmGB_ADDR_CONFIG[rip]
	mov	esi, ebp
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmDMIF_ADDR_CONFIG[rip]
	mov	esi, ebp
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmDMIF_ADDR_CALC[rip]
	mov	esi, ebp
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmHDP_ADDR_CONFIG[rip]
	mov	esi, ebp
	call	WREG32@PLT
	mov	esi, ebp
	mov	rdi, QWORD PTR DMA0_REGISTER_OFFSET[rip]
	add	rdi, QWORD PTR mmDMA_TILING_CONFIG[rip]
	call	WREG32@PLT
	mov	esi, ebp
	mov	rdi, QWORD PTR DMA1_REGISTER_OFFSET[rip]
	add	rdi, QWORD PTR mmDMA_TILING_CONFIG[rip]
	call	WREG32@PLT
	mov	rdi, rbx
	call	gfx_v6_0_tiling_mode_table_init@PLT
	mov	rdi, rbx
	call	gfx_v6_0_setup_rb@PLT
	mov	rdi, rbx
	call	gfx_v6_0_setup_spi@PLT
	mov	rdi, rbx
	call	gfx_v6_0_get_cu_info@PLT
	mov	rdi, rbx
	call	gfx_v6_0_config_init@PLT
	mov	ecx, DWORD PTR CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT[rip]
	mov	esi, 22
	mov	eax, 43
	mov	rdi, QWORD PTR mmCP_QUEUE_THRESHOLDS[rip]
	sal	esi, cl
	mov	ecx, DWORD PTR CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT[rip]
	sal	eax, cl
	or	esi, eax
	call	WREG32@PLT
	mov	ecx, DWORD PTR CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT[rip]
	mov	esi, 48
	mov	eax, 96
	mov	rdi, QWORD PTR mmCP_MEQ_THRESHOLDS[rip]
	sal	esi, cl
	mov	ecx, DWORD PTR CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT[rip]
	sal	eax, cl
	or	esi, eax
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmSX_DEBUG_1[rip]
	call	RREG32@PLT
	mov	rdi, QWORD PTR mmSX_DEBUG_1[rip]
	mov	rsi, rax
	call	WREG32@PLT
	mov	ecx, DWORD PTR SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT[rip]
	mov	esi, 4
	mov	rdi, QWORD PTR mmSPI_CONFIG_CNTL_1[rip]
	sal	esi, cl
	call	WREG32@PLT
	mov	ecx, DWORD PTR PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT[rip]
	mov	esi, DWORD PTR 40[rbx]
	mov	eax, DWORD PTR 44[rbx]
	mov	rdi, QWORD PTR mmPA_SC_FIFO_SIZE[rip]
	sal	esi, cl
	mov	ecx, DWORD PTR PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT[rip]
	sal	eax, cl
	mov	ecx, DWORD PTR PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT[rip]
	or	esi, eax
	mov	eax, DWORD PTR 48[rbx]
	sal	eax, cl
	mov	ecx, DWORD PTR PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT[rip]
	or	esi, eax
	mov	eax, DWORD PTR 52[rbx]
	sal	eax, cl
	or	esi, eax
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmVGT_NUM_INSTANCES[rip]
	mov	esi, 1
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmCP_PERFMON_CNTL[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmSQ_CONFIG[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	ecx, DWORD PTR PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT[rip]
	mov	esi, 4095
	mov	eax, 255
	mov	rdi, QWORD PTR mmPA_SC_FORCE_EOV_MAX_CNTS[rip]
	sal	esi, cl
	mov	ecx, DWORD PTR PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT[rip]
	sal	eax, cl
	or	esi, eax
	call	WREG32@PLT
	mov	ecx, DWORD PTR VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT[rip]
	mov	esi, DWORD PTR VC_AND_TC[rip]
	mov	eax, DWORD PTR ES_AND_GS_AUTO[rip]
	mov	rdi, QWORD PTR mmVGT_CACHE_INVALIDATION[rip]
	sal	esi, cl
	mov	ecx, DWORD PTR VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT[rip]
	sal	eax, cl
	or	esi, eax
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmVGT_GS_VERTEX_REUSE[rip]
	mov	esi, 16
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmPA_SC_LINE_STIPPLE_STATE[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmCB_PERFCOUNTER0_SELECT0[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmCB_PERFCOUNTER0_SELECT1[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmCB_PERFCOUNTER1_SELECT0[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmCB_PERFCOUNTER1_SELECT1[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmCB_PERFCOUNTER2_SELECT0[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmCB_PERFCOUNTER2_SELECT1[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmCB_PERFCOUNTER3_SELECT0[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmCB_PERFCOUNTER3_SELECT1[rip]
	xor	esi, esi
	call	WREG32@PLT
	mov	rdi, QWORD PTR mmHDP_HOST_PATH_CNTL[rip]
	call	RREG32@PLT
	mov	rdi, QWORD PTR mmHDP_HOST_PATH_CNTL[rip]
	mov	rsi, rax
	call	WREG32@PLT
	mov	ecx, DWORD PTR PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT[rip]
	mov	esi, 3
	mov	rdi, QWORD PTR mmPA_CL_ENHANCE[rip]
	sal	esi, cl
	or	esi, DWORD PTR PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK[rip]
	call	WREG32@PLT
	add	rsp, 8
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	mov	edi, 50
	pop	rbx
	.cfi_def_cfa_offset 16
	pop	rbp
	.cfi_def_cfa_offset 8
	jmp	udelay@PLT
	.p2align 4,,10
	.p2align 3
.L3:
	.cfi_restore_state
	movabs	rax, 21474836484
	mov	DWORD PTR 4[rdi], 1
	mov	ebp, DWORD PTR HAINAN_GB_ADDR_CONFIG_GOLDEN[rip]
	mov	QWORD PTR 8[rdi], rax
	movabs	rax, 4294967297
	mov	QWORD PTR 16[rdi], rax
	movabs	rax, 1099511627778
	mov	QWORD PTR 24[rdi], rax
	movabs	rax, 34359738384
	mov	QWORD PTR 32[rdi], rax
	movabs	rax, 274877906976
	mov	QWORD PTR 40[rdi], rax
	movabs	rax, 1305670058032
	mov	QWORD PTR 48[rdi], rax
	jmp	.L9
	.p2align 4,,10
	.p2align 3
.L8:
	movabs	rax, 21474836484
	mov	DWORD PTR 4[rdi], 1
	mov	QWORD PTR 8[rdi], rax
	movabs	rax, 17179869186
	mov	QWORD PTR 16[rdi], rax
	movabs	rax, 1099511627780
	mov	QWORD PTR 24[rdi], rax
	movabs	rax, 34359738400
	jmp	.L22
	.p2align 4,,10
	.p2align 3
.L7:
	movabs	rax, 34359738380
	mov	DWORD PTR 4[rdi], 2
	mov	QWORD PTR 8[rdi], rax
	movabs	rax, 17179869186
	mov	QWORD PTR 16[rdi], rax
	movabs	rax, 1099511627788
.L21:
	mov	QWORD PTR 24[rbx], rax
	mov	ebp, DWORD PTR TAHITI_GB_ADDR_CONFIG_GOLDEN[rip]
	movabs	rax, 34359738400
	mov	QWORD PTR 32[rbx], rax
	movabs	rax, 1099511627808
	mov	QWORD PTR 40[rbx], rax
	movabs	rax, 1305670058032
	mov	QWORD PTR 48[rbx], rax
	jmp	.L9
	.p2align 4,,10
	.p2align 3
.L6:
	movabs	rax, 21474836488
	mov	DWORD PTR 4[rdi], 2
	mov	QWORD PTR 8[rdi], rax
	movabs	rax, 17179869186
	mov	QWORD PTR 16[rdi], rax
	movabs	rax, 1099511627784
	jmp	.L21
	.p2align 4,,10
	.p2align 3
.L24:
	cmp	eax, 4
	jne	.L14
	jmp	.L13
	.p2align 4,,10
	.p2align 3
.L10:
	movabs	rax, 137438953476
	mov	esi, DWORD PTR GB_ADDR_CONFIG__ROW_SIZE_MASK[rip]
	mov	QWORD PTR 68[rbx], rax
	movabs	rax, 274877906945
	mov	QWORD PTR 76[rbx], rax
	not	esi
	and	esi, ebp
.L13:
	mov	ecx, DWORD PTR GB_ADDR_CONFIG__ROW_SIZE__SHIFT[rip]
	mov	eax, 2
	sal	eax, cl
	or	esi, eax
	jmp	.L14
.L2:
	xor	eax, eax
	xor	ebp, ebp
	call	BUG@PLT
	jmp	.L9
	.cfi_endproc
.LFE0:
	.size	gfx_v6_0_constants_init, .-gfx_v6_0_constants_init
	.comm	mmVGT_NUM_INSTANCES,8,8
	.comm	mmVGT_GS_VERTEX_REUSE,8,8
	.comm	mmVGT_CACHE_INVALIDATION,8,8
	.comm	mmUVD_UDEC_DB_ADDR_CONFIG,8,8
	.comm	mmUVD_UDEC_DBW_ADDR_CONFIG,8,8
	.comm	mmUVD_UDEC_ADDR_CONFIG,8,8
	.comm	mmSX_DEBUG_1,8,8
	.comm	mmSRBM_INT_CNTL,8,8
	.comm	mmSRBM_INT_ACK,8,8
	.comm	mmSQ_CONFIG,8,8
	.comm	mmSPI_CONFIG_CNTL_1,8,8
	.comm	mmPA_SC_LINE_STIPPLE_STATE,8,8
	.comm	mmPA_SC_FORCE_EOV_MAX_CNTS,8,8
	.comm	mmPA_SC_FIFO_SIZE,8,8
	.comm	mmPA_CL_ENHANCE,8,8
	.comm	mmMC_SHARED_CHMAP,8,8
	.comm	mmMC_ARB_RAMCFG,8,8
	.comm	mmHDP_HOST_PATH_CNTL,8,8
	.comm	mmHDP_ADDR_CONFIG,8,8
	.comm	mmGRBM_CNTL,8,8
	.comm	mmGB_ADDR_CONFIG,8,8
	.comm	mmDMIF_ADDR_CONFIG,8,8
	.comm	mmDMIF_ADDR_CALC,8,8
	.comm	mmDMA_TILING_CONFIG,8,8
	.comm	mmCP_QUEUE_THRESHOLDS,8,8
	.comm	mmCP_PERFMON_CNTL,8,8
	.comm	mmCP_MEQ_THRESHOLDS,8,8
	.comm	mmCB_PERFCOUNTER3_SELECT1,8,8
	.comm	mmCB_PERFCOUNTER3_SELECT0,8,8
	.comm	mmCB_PERFCOUNTER2_SELECT1,8,8
	.comm	mmCB_PERFCOUNTER2_SELECT0,8,8
	.comm	mmCB_PERFCOUNTER1_SELECT1,8,8
	.comm	mmCB_PERFCOUNTER1_SELECT0,8,8
	.comm	mmCB_PERFCOUNTER0_SELECT1,8,8
	.comm	mmCB_PERFCOUNTER0_SELECT0,8,8
	.comm	mmBIF_FB_EN,8,8
	.comm	VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT,4,4
	.comm	VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT,4,4
	.comm	VERDE_GB_ADDR_CONFIG_GOLDEN,4,4
	.comm	VC_AND_TC,4,4
	.comm	TAHITI_GB_ADDR_CONFIG_GOLDEN,4,4
	.comm	SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT,4,4
	.comm	PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT,4,4
	.comm	PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT,4,4
	.comm	PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT,4,4
	.comm	PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT,4,4
	.comm	PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT,4,4
	.comm	PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT,4,4
	.comm	PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT,4,4
	.comm	PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK,4,4
	.comm	MC_ARB_RAMCFG__NOOFCOLS__SHIFT,4,4
	.comm	MC_ARB_RAMCFG__NOOFCOLS_MASK,4,4
	.comm	HAINAN_GB_ADDR_CONFIG_GOLDEN,4,4
	.comm	GRBM_CNTL__READ_TIMEOUT__SHIFT,4,4
	.comm	GB_ADDR_CONFIG__ROW_SIZE__SHIFT,4,4
	.comm	GB_ADDR_CONFIG__ROW_SIZE_MASK,4,4
	.comm	GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT,4,4
	.comm	GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK,4,4
	.comm	ES_AND_GS_AUTO,4,4
	.comm	DMA1_REGISTER_OFFSET,8,8
	.comm	DMA0_REGISTER_OFFSET,8,8
	.comm	CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT,4,4
	.comm	CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT,4,4
	.comm	CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT,4,4
	.comm	CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT,4,4
	.comm	BIF_FB_EN__FB_WRITE_EN_MASK,4,4
	.comm	BIF_FB_EN__FB_READ_EN_MASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 2
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"extr_gfx_v6_0.c_gfx_v6_0_constants_init.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	gfx_v6_0_constants_init, %function
gfx_v6_0_constants_init:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 0, uses_anonymous_args = 0
	ldr	r3, [r0]
	push	{r4, r5, r6, r7, r8, r9, r10, lr}
	sub	r3, r3, #128
	mov	r4, r0
	cmp	r3, #4
	ldrls	pc, [pc, r3, asl #2]
	b	.L2
.L4:
	.word	.L8
	.word	.L7
	.word	.L6
	.word	.L5
	.word	.L3
.L3:
	mov	r3, #1
	mov	r5, #16
	mov	r9, #4
	mov	r8, #5
	mov	r7, #2
	mov	r6, #256
	mov	lr, #8
	mov	ip, #32
	mov	r0, #64
	mov	r1, #48
	mov	r2, #304
	str	r3, [r4, #4]
	str	r3, [r4, #16]
	str	r3, [r4, #20]
	ldr	r3, .L24
	str	r9, [r4, #8]
	str	r8, [r4, #12]
	str	r7, [r4, #24]
	str	r6, [r4, #28]
	str	r5, [r4, #32]
	str	lr, [r4, #36]
	str	ip, [r4, #40]
	str	r0, [r4, #44]
	str	r1, [r4, #48]
	str	r2, [r4, #52]
	ldr	r5, [r3]
.L9:
	mov	r1, #255
	ldr	r3, .L24+4
	ldr	r2, .L24+8
	ldr	r3, [r3]
	ldr	r0, [r2]
	lsl	r1, r1, r3
	bl	WREG32
	ldr	r3, .L24+12
	mov	r1, #1
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L24+16
	mov	r1, #1
	ldr	r0, [r3]
	bl	WREG32
	ldr	r2, .L24+20
	ldr	r3, .L24+24
	ldr	r1, [r2]
	ldr	r2, [r3]
	ldr	r3, .L24+28
	orr	r1, r1, r2
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L24+32
	ldr	r0, [r3]
	bl	RREG32
	ldr	r3, .L24+36
	ldr	r0, [r3]
	bl	RREG32
	mov	r2, #4
	mov	ip, #256
	ldr	r3, .L24+40
	ldr	r1, .L24+44
	ldr	r3, [r3]
	ldr	r1, [r1]
	and	r3, r3, r0
	asr	r3, r3, r1
	add	r3, r3, #8
	ldr	r1, [r4, #8]
	lsl	r3, r2, r3
	cmp	r3, #5120
	str	r0, [r4, #56]
	str	ip, [r4, #64]
	str	r1, [r4, #60]
	bge	.L10
	add	r2, r3, #1020
	cmp	r3, #0
	add	r2, r2, #3
	movlt	r3, r2
	mov	ip, #32
	mov	r2, #1
	mov	r0, #64
	ldr	r1, .L24+48
	asr	r3, r3, #10
	ldr	r1, [r1]
	cmp	r3, #2
	str	r3, [r4, #68]
	bic	r5, r5, r1
	str	ip, [r4, #72]
	str	r2, [r4, #76]
	str	r0, [r4, #80]
	bne	.L23
.L21:
	ldr	r3, .L24+52
	ldr	r3, [r3]
	orr	r5, r5, r2, lsl r3
.L14:
	ldr	r3, [r4, #4]
	ldr	r2, .L24+56
	cmp	r3, #2
	ldr	r1, [r2]
	moveq	r2, #1
	ldreq	r3, .L24+60
	bic	r5, r5, r1
	ldreq	r3, [r3]
	ldr	r6, .L24+64
	orreq	r5, r5, r2, lsl r3
	ldr	r3, .L24+68
	mov	r1, r5
	str	r5, [r4, #84]
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L24+72
	mov	r1, r5
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L24+76
	mov	r1, r5
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L24+80
	mov	r1, r5
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L24+84
	ldr	r0, [r6]
	ldr	r3, [r3]
	mov	r1, r5
	add	r0, r0, r3
	bl	WREG32
	ldr	r3, .L24+88
	ldr	r0, [r6]
	ldr	r3, [r3]
	mov	r1, r5
	add	r0, r0, r3
	bl	WREG32
	mov	r0, r4
	bl	gfx_v6_0_tiling_mode_table_init
	mov	r0, r4
	bl	gfx_v6_0_setup_rb
	mov	r0, r4
	bl	gfx_v6_0_setup_spi
	mov	r0, r4
	bl	gfx_v6_0_get_cu_info
	mov	r0, r4
	bl	gfx_v6_0_config_init
	mov	r3, #43
	mov	r1, #22
	ldr	r0, .L24+92
	ldr	r2, .L24+96
	ldr	ip, [r0]
	ldr	r0, [r2]
	ldr	r2, .L24+100
	lsl	r3, r3, ip
	orr	r1, r3, r1, lsl r0
	ldr	r0, [r2]
	bl	WREG32
	mov	r3, #96
	mov	r1, #48
	ldr	r0, .L24+104
	ldr	r2, .L24+108
	ldr	ip, [r0]
	ldr	r0, [r2]
	ldr	r2, .L24+112
	lsl	r3, r3, ip
	ldr	r5, .L24+116
	orr	r1, r3, r1, lsl r0
	ldr	r0, [r2]
	bl	WREG32
	ldr	r0, [r5]
	bl	RREG32
	mov	r1, r0
	ldr	r0, [r5]
	bl	WREG32
	mov	r1, #4
	ldr	r3, .L24+120
	ldr	r2, .L24+124
	ldr	r3, [r3]
	ldr	r0, [r2]
	lsl	r1, r1, r3
	bl	WREG32
	ldr	r3, .L24+128
	ldr	r2, .L24+132
	ldr	lr, [r3]
	ldr	ip, .L24+136
	ldr	r3, [r4, #44]
	ldr	r1, [r2]
	ldr	r0, [r4, #40]
	ldr	r2, .L24+140
	ldr	ip, [ip]
	lsl	r3, r3, lr
	ldr	lr, [r4, #48]
	orr	r3, r3, r0, lsl r1
	ldr	r0, [r2]
	ldr	r1, [r4, #52]
	ldr	r2, .L24+144
	orr	r3, r3, lr, lsl ip
	orr	r1, r3, r1, lsl r0
	ldr	r0, [r2]
	bl	WREG32
	ldr	r3, .L24+148
	mov	r1, #1
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L24+152
	mov	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L24+156
	mov	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	mov	r3, #255
	ldr	r1, .L24+160
	ldr	r2, .L24+164
	ldr	ip, [r1]
	ldr	r0, [r2]
	ldr	r1, .L24+168
	ldr	r2, .L24+172
	lsl	r3, r3, ip
	orr	r1, r3, r1, lsl r0
	ldr	r0, [r2]
	bl	WREG32
	ldr	r0, .L24+176
	ldr	r3, .L24+180
	ldr	r2, .L24+184
	ldr	r1, .L24+188
	ldr	ip, [r0]
	ldr	r3, [r3]
	ldr	r0, [r2]
	ldr	r1, [r1]
	ldr	r2, .L24+192
	lsl	r3, r3, ip
	orr	r1, r3, r1, lsl r0
	ldr	r0, [r2]
	bl	WREG32
	ldr	r3, .L24+196
	mov	r1, #16
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L24+200
	mov	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L24+204
	mov	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L24+208
	mov	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L24+212
	mov	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L24+216
	mov	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L24+220
	mov	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L24+224
	mov	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L24+228
	mov	r1, #0
	ldr	r0, [r3]
	bl	WREG32
	ldr	r3, .L24+232
	ldr	r4, .L24+236
	ldr	r0, [r3]
	mov	r1, #0
	bl	WREG32
	ldr	r0, [r4]
	bl	RREG32
	mov	r1, r0
	ldr	r0, [r4]
	bl	WREG32
	mov	r0, #3
	ldr	r2, .L24+240
	ldr	r3, .L24+244
	ldr	r1, [r2]
	ldr	r2, [r3]
	ldr	r3, .L24+248
	orr	r1, r2, r0, lsl r1
	ldr	r0, [r3]
	bl	WREG32
	pop	{r4, r5, r6, r7, r8, r9, r10, lr}
	mov	r0, #50
	b	udelay
.L8:
	mov	r3, #4
	mov	r5, #256
	mov	r2, #32
	mov	r8, #1
	mov	r7, #5
	mov	r6, #2
	mov	lr, #8
	mov	ip, #64
	mov	r0, #48
	mov	r1, #304
	str	r3, [r4, #8]
	str	r3, [r4, #20]
	str	r3, [r4, #24]
	ldr	r3, .L24+252
	str	r8, [r4, #4]
	str	r7, [r4, #12]
	str	r6, [r4, #16]
	str	r5, [r4, #28]
	str	r2, [r4, #32]
	str	r2, [r4, #40]
	str	lr, [r4, #36]
	str	ip, [r4, #44]
	str	r0, [r4, #48]
	str	r1, [r4, #52]
	ldr	r5, [r3]
	b	.L9
.L7:
	mov	r1, #8
	mov	ip, #2
	mov	r0, #12
	mov	r2, #256
	mov	r3, #32
	mov	r5, #48
	mov	r6, #4
	mov	lr, #304
	str	r1, [r4, #12]
	str	r1, [r4, #36]
	ldr	r1, .L24+256
	str	r5, [r4, #48]
	str	ip, [r4, #4]
	ldr	r5, [r1]
	str	ip, [r4, #16]
	str	r0, [r4, #8]
	str	r0, [r4, #24]
	str	r6, [r4, #20]
	str	r2, [r4, #28]
	str	r2, [r4, #44]
	str	r3, [r4, #32]
	str	r3, [r4, #40]
	str	lr, [r4, #52]
	b	.L9
.L6:
	mov	r3, #8
	mov	r0, #2
	mov	r5, #4
	mov	r1, #256
	mov	r2, #32
	mov	r6, #5
	mov	lr, #48
	mov	ip, #304
	str	r3, [r4, #8]
	str	r3, [r4, #24]
	str	r3, [r4, #36]
	ldr	r3, .L24+256
	str	r0, [r4, #4]
	str	r0, [r4, #16]
	str	r6, [r4, #12]
	str	r5, [r4, #20]
	str	r1, [r4, #28]
	str	r1, [r4, #44]
	str	r2, [r4, #32]
	str	r2, [r4, #40]
	str	lr, [r4, #48]
	str	ip, [r4, #52]
	ldr	r5, [r3]
	b	.L9
.L5:
	mov	r3, #4
	mov	r2, #1
	mov	r5, #8
	mov	r9, #6
	mov	r8, #2
	mov	r7, #256
	mov	r6, #16
	mov	lr, #32
	mov	ip, #64
	mov	r0, #48
	mov	r1, #304
	str	r3, [r4, #8]
	str	r3, [r4, #24]
	ldr	r3, .L24+252
	str	r2, [r4, #4]
	str	r2, [r4, #16]
	str	r9, [r4, #12]
	str	r8, [r4, #20]
	str	r7, [r4, #28]
	str	r6, [r4, #32]
	str	r5, [r4, #36]
	str	lr, [r4, #40]
	str	ip, [r4, #44]
	str	r0, [r4, #48]
	str	r1, [r4, #52]
	ldr	r5, [r3]
	b	.L9
.L23:
	cmp	r3, #4
	bne	.L14
	b	.L13
.L10:
	mov	ip, #32
	mov	r0, #1
	mov	r3, #64
	ldr	r1, .L24+48
	str	r2, [r4, #68]
	ldr	r1, [r1]
	str	ip, [r4, #72]
	bic	r5, r5, r1
	str	r0, [r4, #76]
	str	r3, [r4, #80]
.L13:
	mov	r2, #2
	b	.L21
.L2:
	bl	BUG
	mov	r5, #0
	b	.L9
.L25:
	.align	2
.L24:
	.word	HAINAN_GB_ADDR_CONFIG_GOLDEN
	.word	GRBM_CNTL__READ_TIMEOUT__SHIFT
	.word	mmGRBM_CNTL
	.word	mmSRBM_INT_CNTL
	.word	mmSRBM_INT_ACK
	.word	BIF_FB_EN__FB_READ_EN_MASK
	.word	BIF_FB_EN__FB_WRITE_EN_MASK
	.word	mmBIF_FB_EN
	.word	mmMC_SHARED_CHMAP
	.word	mmMC_ARB_RAMCFG
	.word	MC_ARB_RAMCFG__NOOFCOLS_MASK
	.word	MC_ARB_RAMCFG__NOOFCOLS__SHIFT
	.word	GB_ADDR_CONFIG__ROW_SIZE_MASK
	.word	GB_ADDR_CONFIG__ROW_SIZE__SHIFT
	.word	GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK
	.word	GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT
	.word	mmDMA_TILING_CONFIG
	.word	mmGB_ADDR_CONFIG
	.word	mmDMIF_ADDR_CONFIG
	.word	mmDMIF_ADDR_CALC
	.word	mmHDP_ADDR_CONFIG
	.word	DMA0_REGISTER_OFFSET
	.word	DMA1_REGISTER_OFFSET
	.word	CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT
	.word	CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT
	.word	mmCP_QUEUE_THRESHOLDS
	.word	CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT
	.word	CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT
	.word	mmCP_MEQ_THRESHOLDS
	.word	mmSX_DEBUG_1
	.word	SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT
	.word	mmSPI_CONFIG_CNTL_1
	.word	PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT
	.word	PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT
	.word	PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT
	.word	PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT
	.word	mmPA_SC_FIFO_SIZE
	.word	mmVGT_NUM_INSTANCES
	.word	mmCP_PERFMON_CNTL
	.word	mmSQ_CONFIG
	.word	PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT
	.word	PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT
	.word	4095
	.word	mmPA_SC_FORCE_EOV_MAX_CNTS
	.word	VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT
	.word	ES_AND_GS_AUTO
	.word	VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT
	.word	VC_AND_TC
	.word	mmVGT_CACHE_INVALIDATION
	.word	mmVGT_GS_VERTEX_REUSE
	.word	mmPA_SC_LINE_STIPPLE_STATE
	.word	mmCB_PERFCOUNTER0_SELECT0
	.word	mmCB_PERFCOUNTER0_SELECT1
	.word	mmCB_PERFCOUNTER1_SELECT0
	.word	mmCB_PERFCOUNTER1_SELECT1
	.word	mmCB_PERFCOUNTER2_SELECT0
	.word	mmCB_PERFCOUNTER2_SELECT1
	.word	mmCB_PERFCOUNTER3_SELECT0
	.word	mmCB_PERFCOUNTER3_SELECT1
	.word	mmHDP_HOST_PATH_CNTL
	.word	PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT
	.word	PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK
	.word	mmPA_CL_ENHANCE
	.word	VERDE_GB_ADDR_CONFIG_GOLDEN
	.word	TAHITI_GB_ADDR_CONFIG_GOLDEN
	.size	gfx_v6_0_constants_init, .-gfx_v6_0_constants_init
	.comm	mmVGT_NUM_INSTANCES,4,4
	.comm	mmVGT_GS_VERTEX_REUSE,4,4
	.comm	mmVGT_CACHE_INVALIDATION,4,4
	.comm	mmUVD_UDEC_DB_ADDR_CONFIG,4,4
	.comm	mmUVD_UDEC_DBW_ADDR_CONFIG,4,4
	.comm	mmUVD_UDEC_ADDR_CONFIG,4,4
	.comm	mmSX_DEBUG_1,4,4
	.comm	mmSRBM_INT_CNTL,4,4
	.comm	mmSRBM_INT_ACK,4,4
	.comm	mmSQ_CONFIG,4,4
	.comm	mmSPI_CONFIG_CNTL_1,4,4
	.comm	mmPA_SC_LINE_STIPPLE_STATE,4,4
	.comm	mmPA_SC_FORCE_EOV_MAX_CNTS,4,4
	.comm	mmPA_SC_FIFO_SIZE,4,4
	.comm	mmPA_CL_ENHANCE,4,4
	.comm	mmMC_SHARED_CHMAP,4,4
	.comm	mmMC_ARB_RAMCFG,4,4
	.comm	mmHDP_HOST_PATH_CNTL,4,4
	.comm	mmHDP_ADDR_CONFIG,4,4
	.comm	mmGRBM_CNTL,4,4
	.comm	mmGB_ADDR_CONFIG,4,4
	.comm	mmDMIF_ADDR_CONFIG,4,4
	.comm	mmDMIF_ADDR_CALC,4,4
	.comm	mmDMA_TILING_CONFIG,4,4
	.comm	mmCP_QUEUE_THRESHOLDS,4,4
	.comm	mmCP_PERFMON_CNTL,4,4
	.comm	mmCP_MEQ_THRESHOLDS,4,4
	.comm	mmCB_PERFCOUNTER3_SELECT1,4,4
	.comm	mmCB_PERFCOUNTER3_SELECT0,4,4
	.comm	mmCB_PERFCOUNTER2_SELECT1,4,4
	.comm	mmCB_PERFCOUNTER2_SELECT0,4,4
	.comm	mmCB_PERFCOUNTER1_SELECT1,4,4
	.comm	mmCB_PERFCOUNTER1_SELECT0,4,4
	.comm	mmCB_PERFCOUNTER0_SELECT1,4,4
	.comm	mmCB_PERFCOUNTER0_SELECT0,4,4
	.comm	mmBIF_FB_EN,4,4
	.comm	VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT,4,4
	.comm	VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT,4,4
	.comm	VERDE_GB_ADDR_CONFIG_GOLDEN,4,4
	.comm	VC_AND_TC,4,4
	.comm	TAHITI_GB_ADDR_CONFIG_GOLDEN,4,4
	.comm	SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT,4,4
	.comm	PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT,4,4
	.comm	PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT,4,4
	.comm	PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT,4,4
	.comm	PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT,4,4
	.comm	PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT,4,4
	.comm	PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT,4,4
	.comm	PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT,4,4
	.comm	PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK,4,4
	.comm	MC_ARB_RAMCFG__NOOFCOLS__SHIFT,4,4
	.comm	MC_ARB_RAMCFG__NOOFCOLS_MASK,4,4
	.comm	HAINAN_GB_ADDR_CONFIG_GOLDEN,4,4
	.comm	GRBM_CNTL__READ_TIMEOUT__SHIFT,4,4
	.comm	GB_ADDR_CONFIG__ROW_SIZE__SHIFT,4,4
	.comm	GB_ADDR_CONFIG__ROW_SIZE_MASK,4,4
	.comm	GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT,4,4
	.comm	GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK,4,4
	.comm	ES_AND_GS_AUTO,4,4
	.comm	DMA1_REGISTER_OFFSET,4,4
	.comm	DMA0_REGISTER_OFFSET,4,4
	.comm	CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT,4,4
	.comm	CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT,4,4
	.comm	CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT,4,4
	.comm	CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT,4,4
	.comm	BIF_FB_EN__FB_WRITE_EN_MASK,4,4
	.comm	BIF_FB_EN__FB_READ_EN_MASK,4,4
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
