From: angcl@Nyongwa.CAM.ORG (Claude Angers)
Subject: Re: WP-PCF, Linux, RISC?
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In article <C5rx8B.Kzp@ecf.toronto.edu> leebr@ecf.toronto.edu (LEE BRIAN) writes:
>In article <1qu8ud$2hd@sunb.ocs.mq.edu.au> eugene@mpce.mq.edu.au writes:
>>In article <C5o1yq.M34@csie.nctu.edu.tw> ghhwang@csie.nctu.edu.tw (ghhwang) writes:
>>>
>>>Dear friend,
>>>  The RISC means "reduced instruction set computer". The RISC usually has 
>>>small instruction set so as to reduce the circuit complex and can increase 
>>>the clock rate to have a high performance. You can read some books about
>>>computer architecture for more information about RISC.
>>
>>hmm... not that I am an authority on RISC ;-) but I clearly remember
>>reading that the instruction set on RISC CPUs is rather large.
>>The difference is in addressing modes - RISC instruction sets are not
>>as orthogonal is CISC.
>>
>>-- 
>
>Theoretically supposed to be reduced.... not any longer.  That's why everyone
>is arguing about RISC v.s. CISC.  Personally, I think CISC will win out.
>Just take a look at the Pentium!  (Not that I like Intel architectures either,
>but that's another story...)
>
>bye!
>

Do you mean that the Pentium is better than a Risc?  or that it will outsell
them all?  If the first, you have to remember that intel CISC (like the
pentium) are a always a generation away from the best riscs... also Riscs
cpu are more costly because they are not sold in the same quantities (not
even on the same order)...  but I remember reading about 3 years (maybe 2)
about a T800(?) from hypercube that did a 100 mips, was superscallar AND
reordered its instruction itself so
