From: Steffi.Beckhaus@newcastle.ac.uk (S. Beckhaus)
Subject: Re: WP-PCF, Linux, RISC?
Nntp-Posting-Host: turing
Organization: Computing Laboratory, U of Newcastle upon Tyne, UK NE1 7RU.
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In article <1qu8ud$2hd@sunb.ocs.mq.edu.au>, eugene@mpce.mq.edu.au writes:
>In article <C5o1yq.M34@csie.nctu.edu.tw> ghhwang@csie.nctu.edu.tw (ghhwang) writes:
>>
>>Dear friend,
>>  The RISC means "reduced instruction set computer". The RISC usually has 
>>small instruction set so as to reduce the circuit complex and can increase 
>>the clock rate to have a high performance. You can read some books about
>>computer architecture for more information about RISC.
>
>hmm... not that I am an authority on RISC ;-) but I clearly remember
>reading that the instruction set on RISC CPUs is rather large.
>The difference is in addressing modes - RISC instruction sets are not
>as orthogonal is CISC.
>

I hope this will clear it up :

(Taken from one of my lecture notes)

 " ...  The alternative approach (to CISC),
 which has been adopted by many in
 recent years, has come to be known as "RISC": the Reduced
 Instruction Set Computer.  This can be characterised simply as
 "Simpler is Faster"; by simplifying the design (e.g.  by reducing
 the variety of instructions & addressing modes), the hardware can be
 designed to run faster.  Even at the cost of needing more
 instructions, the same task can be done more quickly by the simpler,
 faster design.

 A typical RISC processor will:

    o provide a large number of registers (e.g.  32);

    o perform all data operations on registers;

    o provide few addressing modes (e.g. immediate or 'register + offset');

    o only allow load & store operations to access memory;

    o only use a few instruction formats;

    o only support a few data types (e.g. integer, unsigned, floating).

Steffi Beckhaus                 JANET: Steffi.Beckhaus@uk.ac.newcastle
If the odds are a million to one against something occurring, chances
are 50-50 it will.
