With technology scaling down, hundreds and thousands processing elements (PEs) can be integrated on a single chip. Network-on-chip (NoC) has been proposed as an efficient solution to handle this distinctive challenge. In this thesis, we have explored the high performance NoC design for MPSoC and CMP structures from the performance modeling in the offline design phase to the routing algorithm and NoC architecture optimization. More specifically, we first deal with the issue of how to estimate an NoC design fast and accurately in the synthesis inner loop. For this purpose, we propose a machine learning based latency regression model to evaluate the NoC designs with respect to different configurations. Then, for high performance NoC designs, we tackle one of the most important problems, i.e., the routing algorithms design. For avoiding temperature hotspots, a thermal-aware routing algorithm is proposed to achieve an even temperature profile for application-specific Network-on-chips (NoCs). For improving the reliability, a routing algorithm to achieve maximum performance under fault is proposed. Finally, in the architecture level, we propose two new NoC structures using bi-directional links for the performance optimization. In particular, we propose a flit-level speedup scheme to enhance the network-on-chip(NoC) performance utilizing bidirectional channels. We also propose a flexible NoC architecture which takes advantage of a dynamic distributed routing algorithm and improves the NoC communication performance with moderate energy overhead. From the simulation results on both synthetic traffic and real workload traces, significant performance improvement in terms of latency and throughput can be achieved.
Since the power consumption of the routers is as significant as the processor core, the thermal constraint should also be addressed in the routing algorithm design. There have been a lot of works on NoC routing algorithms for various purposes including low power routing @cite_106 , fault-tolerant routing @cite_109 and congestion avoidance routing to improve latency @cite_52 . However, there are only a few works @cite_34 @cite_50 @cite_93 taking temperature issue into account.
@cite_109 @cite_52 @cite_106 @cite_50 @cite_93 @cite_34
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With the advent in technology and shrinking the transistor size down to nano scale, static power may become the dominant power component in Networks-on-Chip (NoCs). Powergating is an efficient technique to reduce the static power of under-utilized resources in different types of circuits. For NoC, routers are promising candidates for power gating, since they present high idle time. However, routers in a NoC are not usually idle for long consecutive cycles due to distribution of resources in NoC and its communication-based nature, even in low network utilizations. Therefore, power-gating loses its efficiency due to performance and power overhead of the packets that encounter powered-off routers. In this paper, we propose Turn-on on Turn (TooT) which reduces the number of wake-ups by leveraging the characteristics of deterministic routing algorithms and mesh topology. In the proposed method, we avoid powering a router on when it forwards a straight packet or ejects a packet, i.e., a router is powered on only when either a packet turns through it or its associated node injects a packet. Experimental results on PARSEC benchmarks demonstrate that, compared with the conventional power-gating, the proposed method improves static power and performance by 57.9 and 35.3 , respectively, at the cost of a negligible area overhead. This paper proposes CoNoC (Contention-free optical NoC) as a new architecture for on-chip routing of optical packets. CoNoC is built upon all-optical switches (AOSs) which passively route optical data streams based on their wavelengths. The key idea of the proposed architecture is the utilization of per-receiver wavelength in the data network to prevent optical contention at the intermediate nodes. Routing optical packets according to their wavelength eliminates the need for resource reservation at the intermediate nodes and the corresponding latency, power, and area overheads. Since passive architecture of the AOS confines the optical contention to the end-points, we propose an electrical arbitration architecture for resolving optical contention at the destination nodes. By performing a series of simulations, we study the efficiency of the proposed architecture, its power and energy consumption, and the data transmission latency. Moreover, we compare the proposed architecture with electrical NoCs and alternative ONoC architectures under various synthetic traffic patterns. Averaged across different traffic patterns, the proposed architecture reduces per-packet power consumption by 19 , 28 , 29 , and 91 and achieves per-packet energy reduction of 28 , 40 , 20 , and 99 over Columbia, Phastlane, @l-router, and electrical torus, respectively. The inefficiency of energy usage on the Internet has become a critical problem with its rapid growth, as all network devices operate at full capacity in spite of the real traffic load. Existing studies try to develop energy efficient routings by aggregating traffic and switching underutilized devices into sleep mode. However, most existing approaches do not address the problem of routing convergence well. Since traffic changes frequently in a network, routing convergence may be triggered frequently for an energy efficient routing, which may induce routing loops and black holes, resulting in severe packet loss. In this paper, we present a fast rerouting-based (FRR-based) energy efficient routing scheme, namely GreenFRR, which leverages the technique of fast rerouting to reduce the convergence time. We first study typical fast rerouting techniques and address the challenge of guaranteeing loop-free routing. Then, we formalize the FRR-based energy efficient routing problem and prove that the problem is NP-hard. In order to solve this problem, we design heuristic algorithms to maximize the number of sleeping links. In particular, we consider link utilization ratio and path stretch in our algorithms. We evaluate our scheme by simulations on real and synthetic topologies with real and synthetic traffic traces. The results show that the power consumed by line cards achieves a saving of 40 and the convergence time can be reduced by 95 . Hard real-time embedded systems impose a strict latency requirement on interconnection subsystems. In the case of network-on-chip (NoC), this means each packet of a traffic stream has to be delivered within a time interval. In addition, with the increasing complexity of NoC, it consumes a significant portion of total chip power, which boosts the power footprint of such chips. In this work, we propose a methodology to minimize the energy consumption of NoC without violating the pre-specified latency deadlines of real-time applications. First, we develop a formal approach based on network calculus to obtain the worst-case delay bound of all packets, from which we derive a safe estimate of the number of cycles that a packet can be further delayed in the network without violating its deadline---the worst-case slack. With this information, we then develop an optimization algorithm that trades the slacks for lower NoC energy. Our algorithm recognizes the distribution of slacks for different traffic streams, and assigns different voltages and frequencies to different routers to achieve NoC energy-efficiency, while meeting the deadlines for all packets. To meet energy-efficient performance demands, the computing industry has moved to parallel computer architectures, such as chip multiprocessors (CMPs), internally interconnected via networks-on-chip (NoC) to meet growing communication needs. Achieving scaling performance as core counts increase to the hundreds in future CMPs, however, will require high performance, yet energy-efficient interconnects. Silicon nanophotonics is a promising replacement for electronic on-chip interconnect due to its high bandwidth and low latency, however, prior techniques have required high static power for the laser and ring thermal tuning. We propose a novel nano-photonic NoC (PNoC) architecture, LumiNOC, optimized for high performance and power-efficiency. This paper makes three primary contributions: a novel, nanophotonic architecture which partitions the network into subnets for better efficiency; a purely photonic, in-band, distributed arbitration scheme; and a channel sharing arrangement utilizing the same waveguides and wavelengths for arbitration as data transmission. In a 64-node NoC under synthetic traffic, LumiNOC enjoys 50 lower latency at low loads and @math higher throughput per Watt on synthetic traffic, versus other reported PNoCs. LumiNOC reduces latencies @math versus an electrical 2-D mesh NoCs on the PARSEC shared-memory, multithreaded benchmark suite. A growing challenge in embedded system design is coping with increasing power densities resulting from packing more and more transistors onto a small die area, which in turn transform into thermal hotspots. In the current late silicon era silicon structures have become more susceptible to transient faults and aging effects resulting from these thermal hotspots. In this paper we present an agent-based power distribution approach (TAPE) which aims to balance the power consumption of a multi many-core architecture in a pro-active manner. By further taking the system's thermal state into consideration when distributing the power throughout the chip, TAPE is able to noticeably reduce the peak temperature. In our simulation we provide a fair comparison with the state-of-the-art approaches HRTM [19] and PDTM [9] using the MiBench benchmark suite [18]. When running multiple applications simultaneously on a multi many-core architecture, we are able to achieve an 11.23 decrease in peak temperature compared to the approach that uses no thermal management [14]. At the same time we reduce the execution time (i.e. we increase the performance of the applications) by 44.2 and reduce the energy consumption by 44.4 compared to PDTM [9]. We also show that our approach exhibits higher scalability, requiring 11.9 times less communication overhead in an architecture with 96 cores compared to the state-of-the-art approaches. Categories and Subject Descriptors: C.3 [Special-Purpose and Application-Based Systems]: Real-time and embedded systems General Terms: Algorithms Nodes in a mobile ad hoc network are typically battery-powered. Energy consumption is therefore an important metric to consider in designing routing protocols for such networks. In this paper, we present our work on integrating energy-efficiency aspects into a standard MANET routing protocol, OLSR. We study the impact of different protocol modifications that aim to increase node lifetime and network performance, and evaluate them under a range of different scenarios. For static networks, little to no performance improvements are achieved, but significant performance gains of 15 to 30 are possible for more dynamic network topologies. At the same time, not all modifications are equally beneficial. In particular, changing the MPR selection criteria, a key OLSR optimization mechanism, is not promising under any of the studied scenarios. Reducing power consumption and increasing battery life of nodes in an ad-hoc network requires an integrated power control and routing strategy. Power optimal routing selects the multi-hop links that require the minimum total power cost for data transmission under a constraint on the link quality. This paper studies optimal power routing under the constraint of a fixed end-to-end probability of error and compares the power optimal routes obtained with this criterion with those from the more commonly used fixed per hop error rate constraint. The comparison is carried out by looking at the properties of the power optimal graph, formed by the union of all the power optimal routes. The paper also provides algorithms to determine the power optimal routes. In this paper, a routing model for minimizing hot spots in the network on chip (NOC) is presented. The model makes use of AntNet routing algorithm which is based on Ant colony. Using this algorithm, which we call AntNet routing algorithm, heavy packet traffics are distributed on the chip minimizing the occurrence of hot spots. To evaluate the efficiency of the scheme, the proposed algorithm was compared to the XY, Odd- Even, and DyAD routing models. The simulation results show that in realistic (Transpose) traffic as well as in heavy packet traffic, the proposed model has less average delay and peak power compared to the other routing models. In addition, the maximum temperature in the proposed algorithm is less than those of the other routing algorithms. Constructing 2D mesh topology network on chips (NoCs) without using virtual channels becomes attractive approach to building future massive multi-core computer systems because of its large amount of bandwidths, less design complexity, and less space consumption of routers. Dead lock problem on NoC is critical because it makes data transmission between nodes unreachable, and inevitable failures in hardware make mesh topology irregular. Although several fault-tolerant techniques are available, deadlock-free routing control algorithm for irregular mesh topology is promising approach to utilize large amount of bandwidths of NoC. The main drawback of available routing control algorithms is that many healthy nodes are deactivated to guarantee deadlock-freeness, and a number of deactivated nodes lead to traffic congestion. In this paper, we propose new fault-tolerant routing algorithm on 2D mesh topology NoC constructed without using virtual channels. The proposed algorithm is fully analyzed its dead lock-freeness, and the experimental result shows that the proposed algorithm can achieve both less number of deactivated nodes and higher throughput. Spin-Torque Transfer Magnetic RAM (STT-RAM), one of the emerging nonvolatile memory (NVM) technologies explored as the replacement for SRAM memory architectures, is particularly promising due to the fast access speed, high integration density, and zero standby power consumption. Recently, hybrid deigns with SRAM and STT-RAM buffers for routers in Network-on-Chip (NoC) systems have been widely implemented to maximize the mutually complementary characteristics of different memory technologies, and leverage the efficiency of intra-router latency and system power consumption. With the realization of Processing-in-Memory enabled by STT-RAM, in this paper, we novelly offload the execution from processors to the STT-RAM based on-chip routers to improve the application performance. On top of the hybrid buffer design in routers, we further present system-level approaches, including an ILP model and polynomial-time heuristic algorithms, to fine-tune the application mapping and scheduling on NoCs, with the objectives of improving system performance-energy efficiency. Network overhead caused by flit conflict in conventional communication circumstances can be ideally avoided by computing the contended flits in intermediate routers; meanwhile, the pressure of heavy workload on processors can be relieved by transferring partial operations to routers, such that network latency and system power consumption can be significantly reduced. Experimental results demonstrate that application schedule length and system energy consumption can be reduced by 35.62, 32.87 percent on average, respectively, in extensive evaluation experiments on PARSEC benchmark applications. In particular, the achievements of application performance and energy efficiency, averagely 36.44 and 33.19 percent, for the CNN application AlexNet have verified the practicability and effectiveness of our presented approaches. Abstract The energy efficiency of wired networks has received considerable attention over the past decade due to its economic and environmental impacts. However, because of the vertical integration of the control and data planes in conventional networks, optimizing energy consumption in such networks is challenging. Software-defined networking (SDN) is an emerging networking paradigm that decouples the control plane from the data plane and introduces network programmability for the development of network applications. In this work, we propose an energy-aware integral flow-routing solution to improve the energy efficiency of the SDN routing application. We consider discreteness of link rates and pose the routing problem as a mixed integer linear programming (MILP) problem, which is known to be NP complete. The proposed solution is a heuristic implementation of the Benders decomposition method that routes additional single and multiple flows without resolving the routing problem. Performance evaluations demonstrate that the proposed solution achieves a close-to-optimal performance (within 3.27 error) compared to CPLEX on various topologies with less than 0.056 of CPLEX average computation time. Furthermore, our solution outperforms the shortest path algorithm by 24.12 to 54.35 in power savings. The efficiency of routing algorithms in ad-hoc networks is measured by delay, throughput, and energy. Here, we focus on routing algorithms optimizing energy consumption while providing small routing delay. For this, we exploit the sender beamforming gain in the line-of-sight path-loss model, where multiple nodes (each with a single antenna) cooperate for beamforming and the routing algorithms provide distributed self-synchronization. While direct point-to-point communication over distance d in the line-of-sight model needs transmission power Θ(d 2 ), and multi-hop power needs power Θ(d) and delay Θ(d), we can reduce the power to Θ(√d) or Θ(log d) depending on the geometry. We present three algorithms with different trade-offs. The first algorithm is designed for grid nodes in the plane and has a point-to-point delay of Θ(log d) and overall power consumption of Θ(√d). The second algorithm for the same geometry decreases the delay to Θ(1 over e log log d) with power Θ((√d) 1+e ) for e > 0. The third algorithm requires a three-dimensional grid network and achieves a delay of Θ(log d) and reduces the energy needed by all nodes to Θ(log d). This paper presents and evaluates two principles for wireless routing protocols. The first is datapath validation: data traffic quickly discovers and fixes routing inconsistencies. The second is adaptive beaconing: extending the Trickle algorithm to routing control traffic reduces route repair latency and sends fewer beacons. We evaluate datapath validation and adaptive beaconing in CTP Noe, a sensor network tree collection protocol. We use 12 different testbeds ranging in size from 20--310 nodes, comprising seven platforms, and six different link layers, on both interference-free and interference-prone channels. In all cases, CTP Noe delivers > 90 of packets. Many experiments achieve 99.9 . Compared to standard beaconing, CTP Noe sends 73 fewer beacons while reducing topology repair latency by 99.8 . Finally, when using low-power link layers, CTP Noe has duty cycles of 3 while supporting aggregate loads of 30 packets minute. Nonorthogonal multiple access (NOMA) and mobile edge computing (MEC) have been emerging as promising techniques in narrowband Internet of Things (NB-IoT) systems to provide ubiquitously connected IoT devices with efficient transmission and computation. However, the successive interference cancellation (SIC) ordering of NOMA has become the bottleneck limiting the performance improvement for the uplink transmission, which is the dominant traffic flow of NB-IoT communications. Also, in order to guarantee the fairness of task execution latency across NB-IoT devices, the computation resource of MEC units has to be fairly allocated to tasks from IoT devices according to the task size. For these reasons, we investigate the joint optimization of SIC ordering and computation resource allocation in this paper. Specifically, we formulate a combinatorial optimization problem with the objective to minimize the maximum task execution latency required per task bit across NB-IoT devices under the limitation of computation resource. We prove the NP-hardness of this joint optimization problem. To tackle this challenging problem, we first propose an optimal algorithm to obtain the optimal SIC ordering and computation resource allocation in two stages: the convex computation resource allocation optimization followed by the combinatorial SIC ordering optimization. To reduce the computational complexity, we design an efficient heuristic algorithm for the SIC ordering optimization. As a good feature, the proposed low-complexity algorithm suffers a negligible performance degradation in comparison with the optimal algorithm. Simulation results demonstrate the benefits of NOMA in reducing the task execution latency. The task of moving data (i.e., the routing problem) in large-scale sensor networks has to contend with several obstacles, including severe power constraints at each node and temporary, but random, failures of nodes, rendering routing schemes designed for traditional communication networks ineffective. We consider the open problem of finding optimum routes between any fixed source-destination pair in a large-scale network, such that the communication load (i.e., the required power) is distributed among all the nodes, the overall latency is minimized, and the algorithm is decentralized and robust. A recent work addressed this problem in the context of a grid topology and showed how to obtain load-balanced routing, but transmissions are restricted to be among near-neighbors and the overall latency grows linearly with the number of nodes. We show how one can route messages between source and destination nodes along random small-world topologies using a decentralized algorithm. Specifically, nodes make connections independently (based only on the source and destination information in the packets), according to a distribution that guarantees an average latency of O(log sup 2 (N)), while preventing hotspot regions by providing an almost uniform distribution of traffic load over all nodes. Surprisingly, the randomized nature of the network structure keeps the average per-node power consumption almost the same as in the case of a grid topology (i.e., local transmissions), while providing an exponential reduction in latency, resulting in a highly fault-tolerant and stable design capable of working in very dynamic environments. b this paper we present a case for using new power-aware metn.cs for determining routes in wireless ad hoc networks. We present five erent metriw based on battery power consumption at nodw. We show that using th=e metrics in a shortest-cost routing algorithm reduces the cost packet of routing packets by 5-30 over shortwt-hop routing (this cost reduction is on top of a 40-70 reduction in energy consumption obtained by using PAMAS, our MAC layer prtocol). Furthermore, using these new metrics ensures that the mean time to node failure is increased si cantly. An interesting property of using shortest-cost routing is that packet delays do not increase. Fintiy, we note that our new metrim can be used in most tradition routing protocols for ad hoc networks. A thermal-aware technique is proposed to minimize the performance impact when thermal power control mechanism is triggered. This technique, called thermal-aware microprocessor (TAM), uses on-chip thermal sensors to detect hot-spots within the microprocessor die. There is a secondary pipeline within the core. It is architecturally simple with ultra low power implementation. This secondary pipeline has two main functions: 1. thermal relieve; 2. ultra low power implementation for certain mobile environment (such as any where any time email connect function). When temperature exceeds a given threshold, the core superscalar pipelines are clock-gated while a secondary in-order pipeline is engaged. Since the secondary pipeline consumes much less power, it will have a much lower temperature, and therefore, it will provide a temporary thermal relieve to the core pipelines when the thermal power mechanism is triggered. This relief reduces energy loss due to leakage, prevents overheating to improve product reliability, and eases cost for thermal solutions. The TAM can also combine with other low power techniques such voltage scaling to achieve ultra low power. As the size of High Performance Computing clusters grows, so does the probability of interconnect hot spots that degrade the latency and effective bandwidth the network provides. This paper presents a solution to this scalability problem for real life constant bisectional-bandwidth fat-tree topologies. It is shown that maximal bandwidth and cut-through latency can be achieved for MPI global collective traffic. To form such a congestion-free configuration, MPI programs should utilize collective communication, MPI-node-order should be topology aware, and the packet routing should match the MPI communication patterns. First, we show that MPI collectives can be classified into unidirectional and bidirectional shifts. Using this property, we propose a scheme for congestion-free routing of the global collectives in fully and partially populated fat trees running a single job. The no-contention result is then obtained for multiple jobs running on the same fat-tree by applying some job size and placement restrictions. Simulation results of the proposed routing, MPI-node-order and communication patterns show no contention which provides a 40 throughput improvement over previously published results for all-to-all collectives. Memory-bound algorithms show complex performance and energy consumption behavior on multicore processors. We choose the lattice-Boltzmann method (LBM) on an Intel Sandy Bridge cluster as a prototype scenario to investigate if and how single-chip performance and power characteristics can be generalized to the highly parallel case. First we perform an analysis of a sparse-lattice LBM implementation for complex geometries. Using a single-core performance model, we predict the intra-chip saturation characteristics and the optimal operating point in terms of energy to solution as a function of implementation details, clock frequency, vectorization, and number of active cores per chip. We show that high single-core performance and a correct choice of the number of active cores per chip are the essential optimizations for lowest energy to solution at minimal performance degradation. Then we extrapolate to the MPI-parallel level and quantify the energy-saving potential of various optimizations and execution modes, where we find these guidelines to be even more important, especially when communication overhead is non-negligible. In our setup we could achieve energy savings of 35 in this case, compared to a naive approach. We also demonstrate that a simple non-reflective reduction of the clock speed leaves most of the energy saving potential unused.