A physical unclonable function (PUF), like a fingerprint, exploits manufacturing randomness to endow each physical item with a unique identifier. One primary PUF application is the secure derivation of volatile cryptographic keys using a fuzzy extractor (FE) comprising: 1) a secure sketch and 2) an entropy extractor. Although the entropy extractor can be lightweight, the overhead of the secure sketch responsible for correcting naturally noisy PUF responses is usually high. We observe that, in general, response unreliability with respect to an enrolled reference measurement increases with increasing differences between the in-the-field PUF operating condition and the operating condition used in evaluating the enrolled reference response. For the first time, we exploit such an inadvertent but important observation. In contrast to the conventional single reference response enrollment, we propose enrolling multiple reference responses (MRRs) subject to the same challenge but under multiple distinct operating conditions. The critical observation here is that one of the reference operating conditions is likely to be closer to the operating condition of the field deployed PUF, thus resulting in minimizing the expected unreliability when compared to the single reference under the nominal condition. As a consequence, MRR greatly reduces the demand for the expected number of erroneous bits requiring correction and, subsequently, achieves a significant reduction in the error correction overhead. The significant implementation efficiency gains from the proposed MRR method are demonstrated from software implementations of FEs on batteryless resource constraint computational radio frequency identification devices, where realistic PUF data are collected from intrinsic static random access memory PUFs.
There are various silicon PUF constructions that include: delay-based PUF such as Arbiter PUF (APUF) @cite_42 @cite_41 and ring oscillator PUF (ROPUF) @cite_31 @cite_12 @cite_44 @cite_35 @cite_32 ; mismatch based PUFs such as the static random access memory (SRAM) PUF @cite_34 @cite_45 , latch PUF @cite_36 , flip-flop PUF @cite_33 @cite_26 and Buskeeper PUF @cite_43 ; current-based PUF @cite_16 , and nonlinear current mirror based PUF @cite_2 . Readers are referred to @cite_20 @cite_39 for details of various PUF constructions.
@cite_35 @cite_26 @cite_33 @cite_41 @cite_36 @cite_42 @cite_32 @cite_16 @cite_39 @cite_44 @cite_43 @cite_45 @cite_2 @cite_31 @cite_34 @cite_20 @cite_12
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This paper presents an easy to design Physically Unclonable Function (PUF). The proposed PUF implementation is a loop composed of @math identical and controllable delay chains which are serially assembled in a loop to create a single ring oscillator. The frequency discrepancies resulting from the oscillator driven by complementary combinations of the delay chains allows to characterize one device. The presented PUF, nicknamed the Loop PUF (LPUF), returns a frequency comparison of loops made of @math delay chains ( @math ). The comparisons are done sequentially on the same structure. Unlike others PUFs based on delays, there is no specific routing constraints. Hence the LPUF is particularly flexible and easy to design. The basic use of the Loop PUF is to generate intrinsic device keys for cryptographic algorithms. It can also be used to generate challenge response pairs for simple authentication. Experiments have been carried out on CYCLONE II FPGAs to assess the performance of the LPUF, such as randomness, uniqueness and steadiness. They clearly show both the easiness of design and the quality level of the LPUF. The measurement time steadiness, as well as resistance against side-channel and modeling attacks are discussed. Ring oscillator (RO)-based physical unclonable function (PUF) is an emerging hardware security primitive but its response reproducibility is susceptible to changes in operating conditions and device aging. Present solutions to increase RO PUF reliability either incur large hardware overhead or require sophisticated RO selection algorithm. This paper exploits the optimal biasing of current starved (CS) inverter for the design of RO PUF with very high reliability against both temperature and voltage variations. With two additional transistors, the CS inverter can be adaptively biased at idle time and in active mode to significantly reduce the overall stress, making the proposed CS RO PUF robust against both environmental condition variations and aging. Without using error correction code, the reliability is further improved by a low-cost proximity detector circuit with a small sacrifice on challenge-response pair space. The correlation between successive RO pairs of different input challenges is also broken by an irregular clocking of the linear feedback shift register used to encipher the input challenges. Based on Monte Carlo simulation in TSMC 40-nm CMOS process, the reliability of native PUF responses has been raised substantially from 89.78 for the regular RO PUF to 95.88 for the proposed CS RO PUF over a broad temperature range of −40°C to 120 °C and ± 20 supply variation. With the proximity detector, the proposed Aging-resistant Current-starved RO (ACRO) PUF can attain 100 reliability statistically by discarding 34.47 fewer challenge-response pairs than the regular RO PUF. It is also 3.7x more aging resilient than existing aging-resilient RO PUFs with 2.38x lower power dissipation. One main problem encountered in the FPGA implementation of Arbiter based Physical Unclonable Function (A-PUF) is the response instability caused by the metastability of delay flip-flop. This paper presents a new multi-arbiter approach to extract more entropy to extend the number of response bits to a single challenge. New multi-arbiter schemes based on the insertion of either a four-flip-flop arbiter or SR latch arbiter after each pair of multiplexers in the configurable paths are proposed to detect the metastable state when two copies of test pulse arrive at the arbiter inputs almost simultaneously. The detected metastable states are distinguishable by the encoded multiple valued outputs of the arbiter. The codes corresponding to the metastable states collectively form a deterministic ternary state that can be recoded to one of the stable states to improve the uniqueness and reliability of the PUF. Our analysis shows that the proposed design can generate robust and reliable challenge-response pairs with a uniqueness of 0.4982 and a reliability of 0.9985 at the expense of a relatively small FPGA resource overhead. Physically Unclonable Functions (PUFs) are lightweight hardware security primitives for generating unique signatures from the unpredictable nature of silicon. However, most of the proposed PUFs have been shown to be vulnerable to modeling attacks, especially against Machine Learning algorithms. A subset of challenge-response pairs can leak the required information to break a PUF due to the presence of a linear separating boundary between the PUF responses. In this paper, we propose a strong and secure PUF based on non-linear current mirrors. The fundamental idea is to propagate a current through two identical chains of non-linear current mirrors. The current through a single stage is shifted by some amount based on the strength of the input current. As the current shift is not a fixed value anymore, strong non-linearity is introduced into the challenge-response relationship. The proposed PUF shows excellent properties upon statistical circuit simulation. The average inter-distance and intra-distance of the proposed PUF are 49.9 and 0.8 respectively. One of the most striking features of the proposed PUF is the low information leakage measured in terms of its modeling attack resistance. By employing Support Vector Machine (SVM) based attacks, we observed that the proposed PUF is almost 10-30x stronger than the delay-based PUFs. Moreover, the current mode nature of the PUF circuit enables low power operation. The proposed PUF consumes about 15 lower energy than an arbiter PUF to produce a single response bit.