The Stixel World is a medium-level, compact representation of road scenes that abstracts millions of disparity pixels into hundreds or thousands of stixels. The goal of this work is to implement and evaluate a complete multi-stixel estimation pipeline on an embedded, energy-efficient, GPU-accelerated device. This work presents a full GPU-accelerated implementation of stixel estimation that produces reliable results at 26 frames per second (real-time) on the Tegra X1 for disparity images of 1024x440 pixels and stixel widths of 5 pixels, and achieves more than 400 frames per second on a high-end Titan X GPU card.
@cite_14 claim to run their FPGA implementation at 25 fps with stixel widths of 5 px, but the authors do not indicate the image resolution.
@cite_14
2074091263 1533497594 2533972219 1997702526
This paper focuses on real-time pedestrian detection on Field Programmable Gate Arrays (FPGAs) using the Histograms of Oriented Gradients (HOG) descriptor in combination with a Support Vector Machine (SVM) for classification as a basic method. We propose to process image data at twice the pixel frequency and to normalize blocks with the L1-Sqrt-norm resulting in an efficient resource utilization. This implementation allows for parallel computation of different scales. Combined with a time-multiplex approach we increase multiscale capabilities beyond resource limitations. We are able to process 64 high resolution images (1920 × 1080 pixels) per second at 18 scales with a latency of less than 150 u s. 1.79 million HOG descriptors and their SVM classifications can be calculated per second and per scale, which outperforms current FPGA implementations by a factor of 4. In this paper, we present an FPGA implementation of real-time Retinex video image enhancement. Our implementation is based on the previously proposed architecture, which can handle the variational approach of the Retinex theory. In order to efficiently reduce the enormous computational cost required for image enhancement, processing layers and repeat counts of iterations are determined in accordance with software evaluation result. As for processing architecture, our pipelining architecture can handle high resolution pictures in real-time. Our FPGA implementation supports WUXGA (1,920×1,200) 60 fps as well as 1080p60. This paper presents a novel design for real-time histogram equalization based on field programmable gate arrays (FPGAs). The design is implemented using non-conventional schemes to compute the histogram statistics and equalization in parallel. Counters are used in conjunction with a dedicated decoder specially designed for this purpose. The hardware is fast, simple, and flexible with reasonable development cost. The proposed system is implemented using Stratix II family chip type EP2S15F484C3. The maximum clock frequency can reach up to 250 MHz. In this case, the total time required to perform histogram equalization for an image of size 256 spl times 256 is 0.262 ms. We conducted high-frame-rate (HFR) video mosaicing for real-time synthesis of a panoramic image by implementing an improved feature-based video mosaicing algorithm on a field-programmable gate array (FPGA)-based high-speed vision platform. In the implementation of the mosaicing algorithm, feature point extraction was accelerated by implementing a parallel processing circuit module for Harris corner detection in the FPGA on the high-speed vision platform. Feature point correspondence matching can be executed for hundreds of selected feature points in the current frame by searching those in the previous frame in their neighbor ranges, assuming that frame-to-frame image displacement becomes considerably smaller in HFR vision. The system we developed can mosaic 512×512 images at 500 fps as a single synthesized image in real time by stitching the images based on their estimated frame-to-frame changes in displacement and orientation. The results of an experiment conducted, in which an outdoor scene was captured using a hand-held camera-head that was quickly moved by hand, verify the performance of our system.