The design of embedded systems is a complex activity that involves a lot of decisions. With high performance demands of present day usage scenarios and software, they often involve energy hungry state-of-the-art computing units. While focusing on power consumption of computing units, the physical properties of software are often ignored. Recently, there has been a growing interest to quantify and model the physical footprint of software (e.g. consumed power, generated heat, execution time, etc.), and a component based approach facilitates methods for describing such properties. Based on these, software architects can make energy-efficient software design solutions. This paper presents power consumption and execution time profiling of a component software that can be allocated on heterogenoeus computing units (CPU, GPU, FPGA) of a tracked robot.
There are numerous studies that compare the performance of CPUs, GPUs and FPGAs. Since the results of the performance are ambiguous in deciding which platform is the best, authors tend to focus on specific use cases, e.g. image processing, basic linear algebra subroutines, etc. A research by reports that for image processing (2D filters), a GPU is by far the best platform, followed by a CPU, but only for filters up to a certain size, beyond which an FPGA surpasses both a CPU and a GPU @cite_8 . However, the experiment results by , show that for real--time image processing an FPGA is without doubt the most suitable platform @cite_9 . A comparison between a CPU and a GPU by , showed that the performance gap between these platforms is not different in orders of magnitude as it is often considered @cite_0 . For software architects this means that the current software models must support multiple criteria. There are several papers that take into consideration software profiling from the perspective of energy consumption @cite_11 , and a lot more from the perspective of execution time @cite_4 @cite_3 , however additional research in this area is required for component based frameworks.
@cite_4 @cite_8 @cite_9 @cite_3 @cite_0 @cite_11
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Processing speed and energy efficiency are two of the most critical issues for computer systems. This paper presents a systematic approach for profiling the power and performance characteristics of application targeting heterogeneous multi-core computing platforms. Our approach enables rapid and automated design space exploration involving optimisation of workload distribution for systems with accelerators such as FPGAs and GPUs. We demonstrate that, with minor modification to the design, it is possible to estimate performance and power efficiency trade off to identify optimized workload distribution. Our approach shows that, for N-body computation, the fastest design which involves 2 CPU cores, 10 FPGA cores and 40960 GPU threads, is 2 times faster than a design with only FPGAs while achieving better overall energy efficiency. Many applications in image processing have high inherent parallelism. FPGAs have shown very high performance in spite of their low operational frequency by fully extracting the parallelism. In recent micro processors, it also becomes possible to utilize the parallelism using multi-cores which support improved SIMD instructions, though programmers have to use them explicitly to achieve high performance. Recent GPUs support a large number of cores, and have a potential for high performance in many applications. However, the cores are grouped, and data transfer between the groups is very limited. Programming tools for FPGA, SIMD instructions on CPU and a large number of cores on GPU have been developed, but it is still difficult to achieve high performance on these platforms. In this paper, we compare the performance of FPGA, GPU and CPU using three applications in image processing; two-dimensional filters, stereo-vision and k-means clustering, and make it clear which platform is faster under which conditions. Today's heterogeneous architectures bring together multiple general-purpose CPUs and multiple domain-specific GPUs and FPGAs to provide dramatic speedup for many applications. However, the challenge lies in utilizing these heterogeneous processors to optimize overall application performance by minimizing workload completion time. Operating system and application development for these systems is in their infancy. In this article, we propose a new scheduling and workload balancing scheme, HDSS, for execution of loops having dependent or independent iterations on heterogeneous multiprocessor systems. The new algorithm dynamically learns the computational power of each processor during an adaptive phase and then schedules the remainder of the workload using a weighted self-scheduling scheme during the completion phase. Different from previous studies, our scheme uniquely considers the runtime effects of block sizes on the performance for heterogeneous multiprocessors. It finds the right trade-off between large and small block sizes to maintain balanced workload while keeping the accelerator utilization at maximum. Our algorithm does not require offline training or architecture-specific parameters. We have evaluated our scheme on two different heterogeneous architectures: AMD 64-core Bulldozer system with nVidia Fermi C2050 GPU and Intel Xeon 32-core SGI Altix 4700 supercomputer with Xilinx Virtex 4 FPGAs. The experimental results show that our new scheduling algorithm can achieve performance improvements up to over 200p when compared to the closest existing load balancing scheme. Our algorithm also achieves full processor utilization with all processors completing at nearly the same time which is significantly better than alternative current approaches. Programmable graphics processing units (GPUs) currently offer the best ratio of floating point computational throughput to price for commodity processors, outdistancing same-generation CPUs by an order of magnitude, which has in turn led to their widespread adoption in a variety of computationally demanding fields. Adapting power system simulations to these processors is complicated by the unique hardware architecture of GPUs, which precludes the usage of direct linear system solvers based on Gaussian elimination. Krylov subspace methods are better suited to the GPU architecture, yet the ill-conditioned nature of power system matrices requires substantial preconditioning to ensure robustness of these methods. To reduce the time spent on preconditioning, we have developed a GPU-based preconditioner designed specifically to handle the large, sparse matrices typically encountered in power system simulations. The preconditioning technique used, based on Chebyshev polynomials, is described in detail, as are the design decisions made in adapting this algorithm to the GPU. Evaluation of the performance of the GPU-based preconditioner on a variety of sparse matrices, ranging in size from 30 x 30 to 3948 x 3948, shows significant computational savings relative to a CPU-based implementation of the same preconditioner and a typical incomplete LU (ILU) preconditioner.