Extreme Ultraviolet (EUV) photolithography is seen as the key enabler for increasing transistor density in the next decade. In EUV lithography, 13.5 nm EUV light is illuminated through a reticle, holding a pattern to be printed, onto a silicon wafer. This process is performed about 100 times per wafer, at a rate of over a hundred wafers an hour. During this process, a certain percentage of the light energy is converted into heat in the wafer. In turn, this heat causes the wafer to deform which increases the overlay error, and as a result, reduces the manufacturing yield. To alleviate this, we propose a firm real-time control system that uses a wafer heat feed-forward model to compensate for the wafer deformation. The model calculates the expected wafer deformation, and then, compensates for that by adjusting the light projection and or the wafer movement. However, the model computational demands are very high. As a result, it needs to be executed on dedicated HW that can perform computations quickly. To this end, we deploy Graphics Processing Units (GPUs) to accelerate the calculations. In order to fit the computations within the required time budgets, we combine in a novel manner multiple techniques, such as compression and mixed-precision arithmetic, with recent advancements in GPUs to build a GPU-based real-time control system. A proof-of-concept implementation using NVIDIA P100 GPUs is able to deliver decompression throughput of 33 GB s and a sustained 198 GFLOP s per GPU for mixed-precision dense matrix-vector multiplication.
The past decade witnessed an increase in the interest of using General Purpose GPU (GPGPU) computing in embedded, real-time, and industrial systems @cite_2 @cite_0 @cite_9 @cite_10 @cite_16 @cite_5 @cite_3 . @cite_2 , Elliot and Anderson discussed the applications that can benefit from GPUs and the constraints on using them. @cite_0 @cite_10 , discussed the potential of GPUs in embedded and industrial systems and the issues facing their adoption.
@cite_9 @cite_3 @cite_0 @cite_2 @cite_5 @cite_16 @cite_10
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Graphics processing units, GPUs, are powerful processors that can offer significant performance advantages over traditional CPUs. The last decade has seen rapid advancement in GPU computational power and generality. Recent technologies make it possible to use GPUs as co-processors to CPUs. The performance advantages of GPUs can be great, often outperforming traditional CPUs by orders of magnitude. While the motivations for developing systems with GPUs are clear, little research in the real-time systems field has been done to integrate GPUs into real-time multiprocessor systems. We present two real-time analysis methods, addressing real-world platform constraints, for such an integration into a soft real-time multiprocessor system and show that a GPU can be exploited to achieve greater levels of total system performance. Graphics processing units (GPUs) are being widely used as co-processors in many application domains to accelerate general-purpose workloads that are computationally intensive, known as GPGPU computing. Real-time multi-tasking support is a critical requirement for many emerging GPGPU computing domains. However, due to the asynchronous and non-preemptive nature of GPU processing, in multi-tasking environments, tasks with higher priority may be blocked by lower priority tasks for a lengthy duration. This severely harms the system’s timing predictability and is a serious impediment limiting the applicability of GPGPU in many real-time and embedded systems. In this paper, we present an efficient GPGPU preemptive execution system (GPES), which combines user-level and driverlevel runtime engines to reduce the pending time of high-priority GPGPU tasks that may be blocked by long-freezing low-priority competing workloads. GPES automatically slices a long-running kernel execution into multiple subkernel launches and splits data transaction into multiple chunks at user-level, then inserts preemption points between subkernel launches and memorycopy operations at driver-level. We implement a prototype of GPES, and use real-world benchmarks and case studies for evaluation. Experimental results demonstrate that GPES is able to reduce the pending time of high-priority tasks in a multitasking environment by up to 90 over the existing GPU driver solutions, while introducing small overheads. GPGPUs have recently emerged as powerful vehicles for general-purpose high-performance computing. Although a new Compute Unified Device Architecture (CUDA) programming model from NVIDIA offers improved programmability for general computing, programming GPGPUs is still complex and error-prone. This paper presents a compiler framework for automatic source-to-source translation of standard OpenMP applications into CUDA-based GPGPU applications. The goal of this translation is to further improve programmability and make existing OpenMP applications amenable to execution on GPGPUs. In this paper, we have identified several key transformation techniques, which enable efficient GPU global memory access, to achieve high performance. Experimental results from two important kernels (JACOBI and SPMUL) and two NAS OpenMP Parallel Benchmarks (EP and CG) show that the described translator and compile-time optimizations work well on both regular and irregular applications, leading to performance improvements of up to 50X over the unoptimized translation (up to 328X over serial). General purpose computing using graphics processing units (GPGPUs) is an attractive option to achieve power efficient throughput computing. But the power efficiency of GPGPUs can be significantly curtailed in the presence of divergence. This paper evaluates two important facets of this problem. First, we study the branch divergence behavior of various GPGPU workloads. We show that only a few branch divergence patterns are dominant in most workloads. In fact only five branch divergence patterns account for 60 of all the divergent instructions in our workloads. In the second part of this work we exploit this branch divergence pattern bias to propose a new divergence pattern aware warp scheduler, called PATS. PATS prioritizes scheduling warps with the same divergence pattern so as to create long idleness windows for any given execution lane. The long idleness windows are then exploited for efficiently power gating the unused lanes while amortizing the gating overhead. We describe the architectural implementation details of PATS and evaluate the power and performance impact of PATS. Our proposed design significantly improves power gating efficiency of GPGPUs with minimal performance overhead.