Power consumption costs takes upto half of operational expenses of datacenters making power management a critical concern. Advances in processor technology provide fine-grained control over operating frequency and voltage of processors and this control can be used to tradeoff power for performance. Although many power and performance models exist, they have a significant error margin while predicting the performance of memory or file-intensive tasks and HPC applications. Our investigations reveal that the prediction error is due in part to the fact that they do not take frequency AND CPU variations account, rather they just depend on the CPU by itself. In this paper, we empirically derive power and completion time models using linear regression with CPU utilization and operating frequency as parameters. We validate our power model on several Intel and AMD processors by predicting within 2-7 of measured power. We validate our completion time model using five kernels of NASA Parallel Benchmark suite and five CPU, memory and file-intensive benchmarks on four heterogeneous systems and predicting within 1-6 of observed performance. We then show how these models can be employed to realize as much as 15 savings in power while delivering 44 better performance for applications deployed in a virtualized environment.
Another flavor in literature is to use OS or hypervisor-driven techniques to provide frequency scaling. Nathuji and Schwan, in VirtualPower @cite_8 , proposed Soft Scaling' - a technique where VM will execute at the required frequency using CPU scheduling policy rather than hypervisor changing the frequency of the processor. Many other authors such as @cite_17 and @cite_21 proportionally reallocated CPU to simulate frequency changes.
@cite_21 @cite_17 @cite_8
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Nowadays, virtualization is present in almost all computing infrastructures. Thanks to server consolidation and VM migration, virtualization helps in power reduction. However, modern powerful computers with higher processor frequency, multiple cores and multiple CPUs constitute the main factor contributing to the continuously increase of energy consumption in numerous computing infrastructures. In this context, energy management takes a critical importance. A hardware technology, called Dynamic Voltage and Frequency Scaling (DVFS), serves to dynamically modify the processor frequency (according to the CPU needs) in order to achieve less energy consumption. However, lowering frequency also generates poor virtual machine (VM) performance. In this paper, we propose a solution consisting of an extended VM scheduler and DVFS, and report some experiments based on this proposal. This enhanced scheduler, according to VM CPU load, dynamically scales processor frequency in order to save energy. The idea is to adapt the current VM scheduler to analyze CPU load, and modify the current processor frequency to the lowest possible, but still support the guaranteed VM performance. The algorithm is designed and simulated on a web server as the sample application and Xen as the virtualization platform. Test results and performance evaluations prove our design and implementation. Applying classical dynamic voltage scaling (DVS) techniques to real-time systems running on processors with discrete voltage frequency modes causes a waste of computational resources. In fact, whenever the ideal speed level computed by the DVS algorithm is not available in the system, to guarantee the feasibility of the task set, the processor speed must be set to the nearest level greater than the optimal one, thus underutilizing the system. Whenever the task set allows a certain degree of flexibility in specifying timing constraints, rate adaptation techniques can be adopted to balance performance (which is a function of task rates) versus energy consumption (which is a function of the processor speed). In this paper, we propose a new method that combines discrete DVS management with elastic scheduling to fully exploit the available computational resources. Depending on the application requirements, the algorithm can be set to improve performance or reduce energy consumption, so enhancing the flexibility of the system. A reclaiming mechanism is also used to take advantage of early completions. To make the proposed approach usable in real-world applications, the task model is enhanced to consider some of the real CPU characteristics, such as discrete voltage frequency levels, switching overhead, task execution times nonlinear with the frequency, and tasks with different power consumption. Implementation issues and experimental results for the proposed algorithm are also discussed Dynamic Voltage Frequency Scaling (DVFS) has been the tool of choice for balancing power and performance in high-performance computing (HPC). With the introduction of Intel's Sandy Bridge family of processors, researchers now have a far more attractive option: user-specified, dynamic, hardware-enforced processor power bounds. In this paper we provide a first look at this technology in the HPC environment and detail both the opportunities and potential pitfalls of using this technique to control processor power. As part of this evaluation we measure power and performance for single-processor instances of several of the NAS Parallel Benchmarks. Additionally, we focus on the behavior of a single benchmark, MG, under several different power bounds. We quantify the well-known manufacturing variation in processor power efficiency and show that, in the absence of a power bound, this variation has no correlation to performance. We then show that execution under a power bound translates this variation in efficiency into variation in performance. Current capacity planning practices based on heavy over-provisioning of power infrastructure hurt (i) the operational costs of data centers as well as (ii) the computational work they can support. We explore a combination of statistical multiplexing techniques to improve the utilization of the power hierarchy within a data center. At the highest level of the power hierarchy, we employ controlled underprovisioning and over-booking of power needs of hosted workloads. At the lower levels, we introduce the novel notion of soft fuses to flexibly distribute provisioned power among hosted workloads based on their needs. Our techniques are built upon a measurement-driven profiling and prediction framework to characterize key statistical properties of the power needs of hosted workloads and their aggregates. We characterize the gains in terms of the amount of computational work (CPU cycles) per provisioned unit of power Computation per Provisioned Watt (CPW). Our technique is able to double the CPWoffered by a Power Distribution Unit (PDU) running the e-commerce benchmark TPC-W compared to conventional provisioning practices. Over-booking the PDU by 10 based on tails of power profiles yields a further improvement of 20 . Reactive techniques implemented on our Xen VMM-based servers dynamically modulate CPU DVFS states to ensure power draw below the limits imposed by soft fuses. Finally, information captured in our profiles also provide ways of controlling application performance degradation despite overbooking. The 95th percentile of TPC-W session response time only grew from 1.59 sec to 1.78 sec--a degradation of 12 .