An effective packet processing abstraction that leverages software or hardware acceleration techniques can simplify the implementation of high-performance virtual network functions. In this paper, we explore the suitability of SDN switches' stateful forwarding abstractions to model accelerated functions in both software and hardware accelerators, such as optimized software switches and FPGA-based NICs. In particular, we select an Extended Finite State Machine abstraction and demonstrate its suitability by implementing the Linux's iptables interface. By doing so, we provide the acceleration of functions such as stateful firewalls, load balancers and dynamic NATs. We find that supporting a flow-level programming consistency model is an important feature of a programming abstraction in this context. Furthermore, we demonstrate that such a model simplifies the scaling of the system when implemented in software, enabling efficient multi-core processing without harming state consistency.
FlexNIC @cite_48 envisions the support of RMT in future NICs, providing a way to execute the RMT-based processing while exchanging packets between the NIC and the host's memory. We consider such work orthogonal to our contribution, since the NIC could use an OPP-like processing model instead of one based on P4.
@cite_48
2225993331 1994680348 2061798300 1496406348
We propose FlexNIC, a flexible network DMA interface that can be used by operating systems and applications alike to reduce packet processing overheads. The recent surge of network I O performance has put enormous pressure on memory and software I O processing subsystems. Yet even at high speeds, flexibility in packet handling is still important for security, performance isolation, and virtualization. Thus, our proposal moves some of the packet processing traditionally done in software to the NIC DMA controller, where it can be done flexibly and at high speed. We show how FlexNIC can benefit widely used data center server applications, such as key-value stores. In the last decade, the FlexRay communication protocol has been promoted as a standard for dependable in-vehicular communications. In the FlexRay protocol, the communication timeline is organized as a sequence of four segments, whereas the Static Segment assigns a set of static slots for the transmission of synchronous messages. In this paper, we address the following problems: "How to efficiently transmit periodic messages in the Static Segment without requiring their periods to be multiples of, or to be synchronized with the FlexRay Communication Cycle?" "Is it possible to guarantee that periodic messages are transferred before their deadlines, without imposing such strict synchronization?" Unlike traditional approaches that use linear-programming based techniques, we evaluate the minimum number of allocated slots using traditional Response Time Analysis (RTA). The use of RTA techniques allows us to consider the timing requirements associated to each of the asynchronous message streams. Unlike other approaches, the RTA-based technique proposed in this paper: (a) is able to deal with message stream sets where periods are not multiple of the FlexRay cycle duration and (b) does not require the strict synchronization between tasks signals at the application layer and slots at the FlexRay communication controller. The proposed slot allocation scheme may be of high practical interest when considering the interconnection of FlexRay CAN in-vehicular communication systems, allowing the remapping of existing CAN message streams to FlexRay. FlexRay is a new industry standard for next-generation communication in automotives. Though there are a few recent researches on performance analysis of FlexRay, two important aspects of the FlexRay design have been overlooked. The first is a holistic integrated scheduling scheme that can handle both static and dynamic segments in a FlexRay network. The second is cost-effective and scalable performance. To address these aspects, we propose a novel holistic scheduling scheme, called HOSA, which can provide scalable performance by using flexible and ease-of-use dual channel communication in FlexRay. HOSA is built upon a novel slot pilfering technique to schedule and optimize the available slots in both static and dynamic segments. Moreover, to achieve efficient implementation, we propose approximate computation, which can efficiently support cost-effective and holistic scheduling by judiciously obtaining the tradeoff between computation complexity and available pilfered slots. HOSA hence offers the salient feature of improving bandwidth utilization. Moreover, to deliver high performance and bridge the gap between real-time communications in networks and storage management in end devices, we implement a deduplication-aware scheme in a real SSD prototype that can reduce space overhead and extend SSD lifespan (by significantly reducing duplicate write operations). The deduplication scheme meets the needs of message updates in FlexRay. Extensive experiments based on synthetic test cases and real-world case studies demonstrate the efficiency and efficacy of HOSA. Users' demands have dramatically increased due to widespread availability of broadband access and new Internet avenues for accessing, sharing and working with information. In response, operators have upgraded their infrastructures to survive in a market as mature as the current Internet. This has meant that most network processing tasks (e.g., routing, anomaly detection, monitoring) must deal with challenging rates, challenges traditionally accomplished by specialized hardware—e.g., FPGA. However, such approaches lack either flexibility or extensibility—or both. As an alternative, the research community has proposed the utilization of commodity hardware providing flexible and extensible cost-aware solutions, thus entailing lower operational and capital expenditure investments. In this scenario, we explain how the arrival of commodity packet engines has revolutionized the development of traffic processing tasks. Thanks to the optimization of both NIC drivers and standard network stacks and by exploiting concepts such as parallelism and memory affinity, impressive packet capture rates can be achieved in hardware valued at a few thousand dollars. This tutorial explains the foundation of this new paradigm, i.e., the knowledge required to capture packets at multi-Gb s rates on commodity hardware. Furthermore, we thoroughly explain and empirically compare current proposals, and importantly explain how apply such proposals with a number of code examples. Finally, we review successful use cases of applications developed over these novel engines.