Hash functions like SHA-1 or MD5 are one of the most important cryptographic primitives, especially in the field of information integrity. Considering the fact that increasing methods have been proposed to break these hash algorithms, a competition for a new family of hash functions was held by the US National Institute of Standards and Technology. Keccak was the winner and selected to be the next generation of hash function standard, named SHA-3. We aim to implement and optimize Batch mode based Keccak algorithms on NVIDIA GPU platform. Our work consider the case of processing multiple hash tasks at once and implement the case on CPU and GPU respectively. Our experimental results show that GPU performance is significantly higher than CPU is the case of processing large batches of small hash tasks.
Lowden @cite_3 focus on the exploration and analysis of the Keccak tree hashing mode on a GPU platform. Based on the implementation, there are core features of the GPU that could be used to accelerate the time it takes to complete a hash due to the massively parallel architecture of the device. In addition to analyzing the speed of the algorithm, the underlying hardware is profiled to identify the bottlenecks that limited the hash speed. The results of their work show that tree hashing can hash data at rates of up to 3 GB s for the fixed size tree mode.
@cite_3
1862268400 2151224499 2782604938 2200726339
In an effort to provide security and data integrity, hashing algorithms have been designed to consume an input of any length to produce a fixed length output. KECCAK was selected by NIST to become the next Secure Hashing Algorithm (SHA-3) after nearly five years of competition. In addition to providing a sequential operating mode, there is also a tree mode that allows large input messages to be hashed in parallel. This work focuses on the exploration and analysis of the KECCAK tree hashing mode on a GPU platform. Based on the implementation, there are core features of the GPU that could be used to accelerate the time it takes to complete a hash due to the massively parallel architecture of the device. In addition to analyzing the speed of the algorithm, the underlying hardware is profiled to identify the bottlenecks that limited the hash speed. The results of this work show that tree hashing can hash data at rates of up to 3 GB s for the fixed size tree mode. On a 3.40 GHz CPU, this is the equivalent of 1.03 cycles per byte, more than six times faster than a sequential implementation for a very large input. For the variable size tree mode, the throughput was 500 MB s. Based on the performance analysis, modification of the input rate of the KECCAK sponge resulted in a negligible change to the overall speed. As a result of the hardware profiling, the register and L1 cache usage in the GPU was a major bottleneck to the overall throughput. In-memory tree structured index search is a fundamental database operation. Modern processors provide tremendous computing power by integrating multiple cores, each with wide vector units. There has been much work to exploit modern processor architectures for database primitives like scan, sort, join and aggregation. However, unlike other primitives, tree search presents significant challenges due to irregular and unpredictable data accesses in tree traversal. In this paper, we present FAST, an extremely fast architecture sensitive layout of the index tree. FAST is a binary tree logically organized to optimize for architecture features like page size, cache line size, and SIMD width of the underlying hardware. FAST eliminates impact of memory latency, and exploits thread-level and datalevel parallelism on both CPUs and GPUs to achieve 50 million (CPU) and 85 million (GPU) queries per second, 5X (CPU) and 1.7X (GPU) faster than the best previously reported performance on the same architectures. FAST supports efficient bulk updates by rebuilding index trees in less than 0.1 seconds for datasets as large as 64Mkeys and naturally integrates compression techniques, overcoming the memory bandwidth bottleneck and achieving a 6X performance improvement over uncompressed index search for large keys on CPUs. In August 2015, SHA-3 Standard was published as the next generation of Secure Hashing Algorithm. Several optimized implementations of SHA-3 on a 24-core processor with software and hardware co-design are proposed in this paper. For software designs, a 4-core mapping scheme with shared-memory reduces the delay time by exploring the internal parallelism of the algorithm; the scheme of 5 cores with packet router improves flexibility; and 24-core mapping with circuit router fully explores the parallelism with higher energy efficiency. Hardware approaches: specific instructions and novel latch-based accelerators, are proposed to improve performance and energy efficiency. The three software mappings provide a speedup of 3.1, 3.6 and 19.6, respectively. Almost 2 times better performance and energy efficiency are obtained with three specific instructions. The implementation of 4 latch-based accelerators achieves a throughput of 81.9 Gbps at 850MHz with 3.7 pJ bit energy consumption per bit. This paper focuses on parallel hash functions based on tree modes of operation for a compression function. We discuss the various forms of optimality that can be obtained when designing such parallel hash functions. The first result is a scheme which optimizes the tree topology in order to decrease at best the running time. Then, without affecting the optimal running time we show that we can slightly change the corresponding tree topology so as to decrease at best the number of required processors as well. Consequently, the resulting scheme optimizes in the first place the running time and in the second place the number of required processors. The present work is of independent interest if we consider the problem of parallelizing the evaluation of an expression where the operator used is neither associative nor commutative.