A physical unclonable function (PUF), like a fingerprint, exploits manufacturing randomness to endow each physical item with a unique identifier. One primary PUF application is the secure derivation of volatile cryptographic keys using a fuzzy extractor (FE) comprising: 1) a secure sketch and 2) an entropy extractor. Although the entropy extractor can be lightweight, the overhead of the secure sketch responsible for correcting naturally noisy PUF responses is usually high. We observe that, in general, response unreliability with respect to an enrolled reference measurement increases with increasing differences between the in-the-field PUF operating condition and the operating condition used in evaluating the enrolled reference response. For the first time, we exploit such an inadvertent but important observation. In contrast to the conventional single reference response enrollment, we propose enrolling multiple reference responses (MRRs) subject to the same challenge but under multiple distinct operating conditions. The critical observation here is that one of the reference operating conditions is likely to be closer to the operating condition of the field deployed PUF, thus resulting in minimizing the expected unreliability when compared to the single reference under the nominal condition. As a consequence, MRR greatly reduces the demand for the expected number of erroneous bits requiring correction and, subsequently, achieves a significant reduction in the error correction overhead. The significant implementation efficiency gains from the proposed MRR method are demonstrated from software implementations of FEs on batteryless resource constraint computational radio frequency identification devices, where realistic PUF data are collected from intrinsic static random access memory PUFs.
This work chooses SRAM PUFs for experimentally demonstrating our MRR methodology. SRAM is pervasively embedded within various electronic commodities. When SRAM is powered up, each SRAM cell has a favored power-up state. However, the favored power-up state varies from cell to cell, and chip to chip. Therefore, the power-up pattern of SRAM memory can be treated as a PUF where the address of each cell is a challenge and power-up state the response. SRAM PUF is an intrinsic PUF attributing to its wide scale availability and the lack of a requirement for extra hardware overhead @cite_1 ; these properties make it one of the most popular silicon PUFs nowadays.
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We present a side-channel attack based on remanence decay in volatile memory and show how it can be exploited effectively to launch a noninvasive cloning attack against SRAM physically unclonable functions (PUFs) - an important class of PUFs typically proposed as lightweight security primitives, which use existing memory on the underlying device. We validate our approach using SRAM PUFs instantiated on two 65-nm CMOS devices. We discuss countermeasures against our attack and propose the constructive use of remanence decay to improve the cloning resistance of SRAM PUFs. Moreover, as a further contribution of independent interest, we show how to use our evaluation results to significantly improve the performance of the recently proposed TARDIS scheme, which is based on remanence decay in SRAM memory and used as a time-keeping mechanism for low-power clockless devices. Physically Unclonable Functions (PUFs) are lightweight hardware security primitives for generating unique signatures from the unpredictable nature of silicon. However, most of the proposed PUFs have been shown to be vulnerable to modeling attacks, especially against Machine Learning algorithms. A subset of challenge-response pairs can leak the required information to break a PUF due to the presence of a linear separating boundary between the PUF responses. In this paper, we propose a strong and secure PUF based on non-linear current mirrors. The fundamental idea is to propagate a current through two identical chains of non-linear current mirrors. The current through a single stage is shifted by some amount based on the strength of the input current. As the current shift is not a fixed value anymore, strong non-linearity is introduced into the challenge-response relationship. The proposed PUF shows excellent properties upon statistical circuit simulation. The average inter-distance and intra-distance of the proposed PUF are 49.9 and 0.8 respectively. One of the most striking features of the proposed PUF is the low information leakage measured in terms of its modeling attack resistance. By employing Support Vector Machine (SVM) based attacks, we observed that the proposed PUF is almost 10-30x stronger than the delay-based PUFs. Moreover, the current mode nature of the PUF circuit enables low power operation. The proposed PUF consumes about 15 lower energy than an arbiter PUF to produce a single response bit. We introduce the notion of a Physical Random Function (PUF). We argue that a complex integrated circuit can be viewed as a silicon PUF and describe a technique to identify and authenticate individual integrated circuits (ICs).We describe several possible circuit realizations of different PUFs. These circuits have been implemented in commodity Field Programmable Gate Arrays (FPGAs). We present experiments which indicate that reliable authentication of individual FPGAs can be performed even in the presence of significant environmental variations.We describe how secure smart cards can be built, and also briefly describe how PUFs can be applied to licensing and certification applications. Emerging Non-Volatile Memories (NVM) such as Spin-Torque Transfer RAM (STT-RAM) and Resistive RAM (RRAM) have been explored as potential alternatives for traditional SRAM-based Last-Level-Caches (LLCs) due to the benefits of higher density and lower leakage power. However, NVM technologies have long latency and high energy overhead associated with the write operations. Consequently, a hybrid STT-RAM and SRAM based LLC architecture has been proposed in the hope of exploiting high density and low leakage power of STT-RAM and low write overhead of SRAM. Such a hybrid cache design relies on an intelligent block placement policy that makes good use of the characteristics of both STT-RAM and SRAM technology.