We suggest a new optical solution for solving the YES NO version of the Exact Cover problem by using the massive parallelism of light. The idea is to build an optical device which can generate all possible solutions of the problem and then to pick the correct one. In our case the device has a graph-like representation and the light is traversing it by following the routes given by the connections between nodes. The nodes are connected by arcs in a special way which lets us to generate all possible covers (exact or not) of the given set. For selecting the correct solution we assign to each item, from the set to be covered, a special integer number. These numbers will actually represent delays induced to light when it passes through arcs. The solution is represented as a subray arriving at a certain moment in the destination node. This will tell us if an exact cover does exist or not.
In @cite_19 was presented a new, principally non-dissipative digital logic architecture which involves a distributed and parallel input scheme where logical functions are evaluated at the speed of light. The system is based on digital logic vectors rather than the Boolean scalars of electronic logic. This new logic paradigm was specially developed with optical implementation in mind.
@cite_19
2027217447 2157024459 2475736732 1522828591
Conventional architectures for the implementation of Boolean logic are based on a network of bistable elements assembled to realize cascades of simple Boolean logic gates. Since each such gate has two input signals and only one output signal, such architectures are fundamentally dissipative in information and energy. Their serial nature also induces a latency in the processing time. In this paper we present a new, principally non-dissipative digital logic architecture which mitigates the above impediments. Unlike traditional computing architectures, the proposed architecture involves a distributed and parallel input scheme where logical functions are evaluated at the speed of light. The system is based on digital logic vectors rather than the Boolean scalars of electronic logic. The architecture employs a novel conception of cascading which utilizes the strengths of both optics and electronics while avoiding their weaknesses. It is inherently non-dissipative, respects the linear nature of interactions in pure optics, and harnesses the control advantages of electrons without reducing the speed advantages of optics. This new logic paradigm was specially developed with optical implementation in mind. However, it is suitable for other implementations as well, including conventional electronic devices. (NOTE: Each chapter begins with an Introduction and concludes with a Summary, To Probe Further, and Exercises and Design Problems.) I. THE FABRICS. 1. Introduction. A Historical Perspective. Issues in Digital Integrated Circuit Design. Quality Metrics of a Digital Design. 2. The Manufacturing Process. The CMOS Manufacturing Process. Design Rules-The Contract between Designer and Process Engineer. Packaging Integrated Circuits. Perspective-Trends in Process Technology. 3. The Devices. The Diode. The MOS(FET) Transistor. A Word on Process Variations. Perspective: Technology Scaling. 4. The Wire. A First Glance. Interconnect Parameters-Capitance, Resistance, and Inductance. Electrical Wire Models. SPICE Wire Models. Perspective: A Look into the Future. II. A CIRCUIT PERSPECTIVE. 5. The CMOS Inverter. The Static CMOS Inverter-An Intuitive Perspective. Evaluating the Robustness of the CMOS Inverter: The Static Behavior. Performance of CMOS Inverter: The Dynamic Behavior. Power, Energy, and Energy-Delay. Perspective: Technology Scaling and Its Impact on the Inverter Metrics. 6. Designing Combinational Logic Gates in CMOS. Static CMOS Design. Dynamic CMOS Design. How to Choose a Logic Style? Perspective: Gate Design in the Ultra Deep-Submicron Era. 7. Designing Sequential Logic Circuits. Timing Metrics for Sequential Circuits. Classification of Memory Elements. Static Latches and Registers. Dynamic Latches and Registers. Pulse Registers. Sense-Amplifier Based Registers. Pipelining: An Approach to Optimize Sequential Circuits. Non-Bistable Sequential Circuits. Perspective: Choosing a Clocking Strategy. III. A SYSTEM PERSPECTIVE. 8. Implementation Strategies for Digital ICS. From Custom to Semicustom and Structured-Array Design Approaches. Custom Circuit Design. Cell-Based Design Methodology. Array-Based Implementation Approaches. Perspective-The Implementation Platform of the Future. 9. Coping with Interconnect. Capacitive Parasitics. Resistive Parasitics. Inductive Parasitics. Advanced Interconnect Techniques. Perspective: Networks-on-a-Chip. 10. Timing Issues in Digital Circuits. Timing Classification of Digital Systems. Synchronous Design-An In-Depth Perspective. Self-Timed Circuit Design. Synchronizers and Arbiters. Clock Synthesis and Synchronization Using a Phased-Locked Loop. Future Directions and Perspectives. 11. Designing Arithmetic Building Blocks. Datapaths in Digital Processor Architectures. The Adder. The Multiplier. The Shifter. Other Arithmetic Operators. Power and Spped Trade-Offs in Datapath Structures. Perspective: Design as a Trade-off. 12. Designing Memory and Array Structures. The Memory Core. Memory Peripheral Circuitry. Memory Reliability and Yield. Power Dissipation in Memories. Case Studies in Memory Design. Perspective: Semiconductor Memory Trends and Evolutions. Problem Solutions. Index. We propose a novel asynchronous parallel algorithmic framework for the minimization of the sum of a smooth nonconvex function and a convex nonsmooth regularizer, subject to both convex and nonconvex constraints. The proposed framework hinges on successive convex approximation techniques and a novel probabilistic model that captures key elements of modern computational architectures and asynchronous implementations in a more faithful way than current state of the art models. Key features of the proposed framework are: i) it accommodates inconsistent read, meaning that components of the vector variables may be written by some cores while being simultaneously read by others; ii) it covers in a unified way several different specific solution methods, and iii) it accommodates a variety of possible parallel computing architectures. Almost sure convergence to stationary solutions is proved. Numerical results, reported in the companion paper, on both convex and nonconvex problems show our method can consistently outperform existing parallel asynchronous algorithms. An approach is described to the specification and verification of digital systems implemented wholly or partly at the analog level of abstraction. The approach relies upon specifying the behaviours of analog components (such as transistors) by piecewise-linear predicates on voltages and currents. A decision procedure is described that can, for a wide class of specifications, automatically establish the correctness of an implementation.