This paper presents the development of a new algorithm for Gaussian based color image enhancement system. The algorithm has been designed into architecture suitable for FPGA ASIC implementation. The color image enhancement is achieved by first convolving an original image with a Gaussian kernel since Gaussian distribution is a point spread function which smoothes the image. Further, logarithm-domain processing and gain offset corrections are employed in order to enhance and translate pixels into the display range of 0 to 255. The proposed algorithm not only provides better dynamic range compression and color rendition effect but also achieves color constancy in an image. The design exploits high degrees of pipelining and parallel processing to achieve real time performance. The design has been realized by RTL compliant Verilog coding and fits into a single FPGA with a gate count utilization of 321,804. The proposed method is implemented using Xilinx Virtex-II Pro XC2VP40-7FF1148 FPGA device and is capable of processing high resolution color motion pictures of sizes of up to 1600×1200 pixels at the real time video rate of 116 frames per second. This shows that the proposed design would work for not only still images but also for high resolution video sequences.
Hiroshi @cite_2 proposed an FPGA implementation of adaptive real-time video image enhancement based on variational model of the Retinex theory. The authors have claimed that the architectures developed in this scheme are efficient and can handle color picture of size @math pixels at the real time video rate of 60 frames per sec. The authors have not justified how high throughput has been achieved in spite of time consuming iterations to the tune of 30. Abdullah M. @cite_8 proposed a new approach for histogram equalization using FPGAs. Although efficient architectures were developed for histogram equalization, the restored images using this scheme are generally not satisfactory.
@cite_8 @cite_2
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In this paper, we present an FPGA implementation of real-time Retinex video image enhancement. Our implementation is based on the previously proposed architecture, which can handle the variational approach of the Retinex theory. In order to efficiently reduce the enormous computational cost required for image enhancement, processing layers and repeat counts of iterations are determined in accordance with software evaluation result. As for processing architecture, our pipelining architecture can handle high resolution pictures in real-time. Our FPGA implementation supports WUXGA (1,920×1,200) 60 fps as well as 1080p60. A novel architecture for performing hue-saturation-value (HSV) domain enhancement of digital color images with non-uniform lighting conditions is proposed in this paper for video streaming applications. The approach promotes log-domain computation to eliminate all multiplications, divisions and exponentiations utilizing the effective logarithmic estimation modules. An optimized quadrant symmetric architecture is incorporated into the design of homomorphic filter for the enhancement of intensity value. Efficient modules are also presented for conversion between RGB and HSV color spaces. The design is able to bring out details hidden in shadow regions of the image. It is capable of producing 187.86 million outputs per second (MOPs) on Xilinx's Virtex II XC2V2000-4ff896 field programmable gate array (FPGA) at a clock frequency of 187.86 MHz. It can process over 179.1 (1024 X 1024) frames per second and consumes approximately 70.7 and 76.8 less hardware resource with 127 and 280 performance boost when compared to the designs with machine learning algorithm [10], and with separated dynamic and contrast enhancements [11], respectively. We conducted high-frame-rate (HFR) video mosaicing for real-time synthesis of a panoramic image by implementing an improved feature-based video mosaicing algorithm on a field-programmable gate array (FPGA)-based high-speed vision platform. In the implementation of the mosaicing algorithm, feature point extraction was accelerated by implementing a parallel processing circuit module for Harris corner detection in the FPGA on the high-speed vision platform. Feature point correspondence matching can be executed for hundreds of selected feature points in the current frame by searching those in the previous frame in their neighbor ranges, assuming that frame-to-frame image displacement becomes considerably smaller in HFR vision. The system we developed can mosaic 512×512 images at 500 fps as a single synthesized image in real time by stitching the images based on their estimated frame-to-frame changes in displacement and orientation. The results of an experiment conducted, in which an outdoor scene was captured using a hand-held camera-head that was quickly moved by hand, verify the performance of our system. A design of a high performance digital architecture for a nonlinear image enhancement technique is presented in this paper. The image enhancement is based on illuminance-reflectance model which improves the visual quality of digital images and video captured under insufficient or non-uniform lighting conditions [1]. Systolic, pipelined and parallel design techniques are utilized effectively in the proposed FPGA-based architectural design to achieve real-time performance. Estimation and folding techniques are used in the hardware algorithmic design to achieve faster, simpler and more efficient architecture. The video enhancement system is implemented using Xilinx's multimedia development board that contains a VirtexII-X2000 FPGA and it is capable of processing approximately 66 Mega-pixels (Mpixels) per second.