Extreme Ultraviolet (EUV) photolithography is seen as the key enabler for increasing transistor density in the next decade. In EUV lithography, 13.5 nm EUV light is illuminated through a reticle, holding a pattern to be printed, onto a silicon wafer. This process is performed about 100 times per wafer, at a rate of over a hundred wafers an hour. During this process, a certain percentage of the light energy is converted into heat in the wafer. In turn, this heat causes the wafer to deform which increases the overlay error, and as a result, reduces the manufacturing yield. To alleviate this, we propose a firm real-time control system that uses a wafer heat feed-forward model to compensate for the wafer deformation. The model calculates the expected wafer deformation, and then, compensates for that by adjusting the light projection and or the wafer movement. However, the model computational demands are very high. As a result, it needs to be executed on dedicated HW that can perform computations quickly. To this end, we deploy Graphics Processing Units (GPUs) to accelerate the calculations. In order to fit the computations within the required time budgets, we combine in a novel manner multiple techniques, such as compression and mixed-precision arithmetic, with recent advancements in GPUs to build a GPU-based real-time control system. A proof-of-concept implementation using NVIDIA P100 GPUs is able to deliver decompression throughput of 33 GB s and a sustained 198 GFLOP s per GPU for mixed-precision dense matrix-vector multiplication.
@cite_16 , Windmann and Niggemann presented a method for fault detection in an industrial automation process. The method incorporates a particle filter with switching neural networks in a fault detection method. The execution time of the method was reduced from 80 s on CPUs to around 6 s on GPUs. Compared to our proposed solution, @cite_16 differs in: (i) their target latency is 100x our target latency, and (ii) the model is compute-bound with rather low memory bandwidth requirements.
@cite_16
2578609449 2073074602 2339807279 2949245006
In the present work, fault detection in industrial automation processes is investigated. A fault detection method for observable process variables is extended for application cases, where the observations of process variables are noisy. The principle of this method consists in building a probability distribution model and evaluating the likelihood of observations under that model. The probability distribution model is based on a hybrid automaton which takes into account several system modes, i.e. phases with continuous system behaviour. Transitions between the modes are attributed to discrete control events such as on off signals. The discrete event system composed of system modes and transitions is modeled as finite state machine. Continuous process behaviour in the particular system modes is modeled with stochastic state space models, which incorporate neural networks. Fault detection is accomplished by evaluation of the underlying probability distribution model with a particle filter. In doing so both the hybrid system model and a linear observation model for noisy observations are taken into account. Experimental results show superior fault detection performance compared to the baseline method for observable process variables. The runtime of the proposed fault detection method has been significantly reduced by parallel implementation on a GPU. Abstract We present simple randomized algorithms for the fault detection problem : Given a specification in the form of a deterministic finite state machine A and an implementation machine B , determine whether B is equal to A . If A has n states and p inputs, then in randomized polynomial time we can construct with high probability a checking sequence of length O ( pn 4 log n ), i.e., a sequence that detects all faulty machines with at most n states. Better bounds can be obtained in certain cases. The techniques generalize to partially specified finite state machines. This paper introduces a framework for inference of timed temporal logic properties from data. The dataset is given as a finite set of pairs of finite-time system traces and labels, where the labels indicate whether the traces exhibit some desired behavior (e.g., a ship traveling along a safe route). We propose a decision-tree based approach for learning signal temporal logic classifiers. The method produces binary decision trees that represent the inferred formulae. Each node of the tree contains a test associated with the satisfaction of a simple formula, optimally tuned from a predefined finite set of primitives. Optimality is assessed using heuristic impurity measures, which capture how well the current primitive splits the data with respect to the traces' labels. We propose extensions of the usual impurity measures from machine learning literature to handle classification of system traces by leveraging upon the robustness degree concept. The proposed incremental construction procedure greatly improves the execution time and the accuracy compared to existing algorithms. We present two case studies that illustrate the usefulness and the computational advantages of the algorithms. The first is an anomaly detection problem in a maritime environment. The second is a fault detection problem in an automotive powertrain system. Deep convolutional neural networks take GPU days of compute time to train on large data sets. Pedestrian detection for self driving cars requires very low latency. Image recognition for mobile phones is constrained by limited processing resources. The success of convolutional neural networks in these situations is limited by how fast we can compute them. Conventional FFT based convolution is fast for large filters, but state of the art convolutional neural networks use small, 3x3 filters. We introduce a new class of fast algorithms for convolutional neural networks using Winograd's minimal filtering algorithms. The algorithms compute minimal complexity convolution over small tiles, which makes them fast with small filters and small batch sizes. We benchmark a GPU implementation of our algorithm with the VGG network and show state of the art throughput at batch sizes from 1 to 64.