Efficiency in embedded systems is paramount to achieve high performance while consuming less area and power. Processors in embedded systems have to be designed carefully to achieve such design constraints. Application Specific Instruction set Processors (ASIPs) exploit the nature of applications to design an optimal instruction set. Despite being not general to execute any application, ASIPs are highly preferred in the embedded systems industry where the devices are produced to satisfy a certain type of application domain s (either intra-domain or inter-domain). Typically, ASIPs are designed from a base-processor and functionalities are added for applications. This paper studies the multi-application ASIPs and their instruction sets, extensively analysing the instructions for inter-domain and intra-domain designs. Metrics analysed are the reusable instructions and the extra cost to add a certain application. A wide range of applications from various application benchmarks (MiBench, MediaBench and SPEC2006) and domains are analysed for two different architectures (ARM-Thumb and PISA). Our study shows that the intra-domain applications contain larger number of common instructions, whereas the inter-domain applications have very less common instructions, regardless of the architecture (and therefore the ISA).
One of the early work on methodologies to maximise performance of ASIP under design constraints, such as area, power consumption and NRE cost, is @cite_12 . The authors in @cite_12 proposed a rapid instruction selection approach from their library of pre-designed specific instructions to be mapped on a set of pre-fabricated co-processors functional units . As a result, the authors in @cite_12 were able to significantly increase application performance while satisfying area constraints. This methodology uses a combination of simulation, estimation and a pre-characterised library of instructions, to select the appropriate co-processors and instructions. @cite_9 proposed a new formalisation and an algorithm that considers the functional module sharing. This method allows designers to predict the performance of their designs before implementation, which is an important feature for producing a high quality design in reasonable time. In addition to that, an efficient algorithm for automatic selection of new application-specific instructions under hardware resources constraints is introduced in @cite_18 . The main drawback of this algorithm is the un-optimised Very-High-Speed Integrated circuits Hardware Description Language (VHDL) model.
@cite_9 @cite_18 @cite_12
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We present a methodology that maximizes the performance of Tensilica based Application Specific Instruction-set Processor (ASIP) through instruction selection when an area constraint is given. Our approach rapidly selects from a set of pre-fabricated coprocessors functional units from our library of pre-designed specific instructions (to evaluate our technology we use the Tensilica platform). As a result, we significantly increase application performance while area constraints are satisfied. Our methodology uses a combination of simulation, estimation and a pre-characterised library of instructions, to select the appropriate co-processors and instructions. We report that by selecting the appropriate coprocessors functional units and specific TIE instructions, the total execution time of complex applications (we study a voice encoder decoder), an application's performance can be reduced by up to 85 compared to the base implementation. Our estimator used in the system takes typically less than a second to estimate, with an average error rate of 4 (as compared to full simulation, which takes 45 minutes). The total selection process using our methodology takes 3-4 hours, while a full design space exploration using simulation would take several days. This paper describes a formal method that selects the instruction set of an ASIP (application specific integrated processor) that maximizes the chip performance under the constraints of chip area and power consumption. Our contribution includes a new formalization and algorithm that considers the functional module sharing in the problem of instruction set optimization. This problem was not addressed in the previous work and considering it leads to an efficient implementation of the selected instructions. The proposed method also enables designers to predict the performance of their designs before implementing them, which is an important feature for producing a high quality design in reasonable time. The design of application-specific instruction set processor(ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design, and instruction set mapping for the application. We present a method that unifies these three design problems with a single formulation: a modified scheduling allocation problem with an integrated instruction formation process. Micro-operations (MOPs) representing the application are scheduled into time steps. Instructions are formed and hardware resources are allocated during the scheduling process. The assembly code for the given application is obtained automatically at the end of the scheduling process. This approach considers MOP parallelism, instruction field encoding, delay load store branch, conditional execution of MOPs and the retargetability to various architecture templates. Experiments are presented to show the power and limitation of our approach. Performance improvement over our previous work is significant. In this paper we introduce a novel linear precoding technique. The approach used for the design of the precoding matrix is general and the resulting algorithm can address several optimization criteria with an arbitrary number of antennas at the user terminals. We have achieved this by designing the precoding matrices in two steps. In the first step we minimize the overlap of the row spaces spanned by the effective channel matrices of different users using a new cost function. In the next step, we optimize the system performance with respect to specific optimization criteria assuming a set of parallel single- user MIMO channels. By combining the closed form solution with Tomlinson-Harashima precoding we reach the maximum sum-rate capacity when the total number of antennas at the user terminals is less or equal to the number of antennas at the base station. By iterating the closed form solution with appropriate power loading we are able to extract the full diversity in the system and reach the maximum sum-rate capacity in case of high multi-user interference. Joint processing over a group of multi-user MIMO channels in different frequency and time slots yields maximum diversity regardless of the level of multi-user interference.