Three Dimensional Integrated Circuits (3D IC) offer lower power consumption, higher performance, higher bandwidth, and scalability over the conventional two dimensional ICs. Through-Silicon Via (TSV) is one of the fabrication mechanisms that connects stacked dies to each other. The large size of TSVs and the proximity between them lead to undesirable coupling capacitance. This interference causes mutual influences between adjacent TSVs and produces crosstalk noise. Furthermore, this effect threats the reliability of data during traversal between layers. This paper proposes a mechanism that efficiently reduces crosstalk noise between TSVs with lower area overhead as compared to previous works. This mechanism revolves around the fact that retaining TSV value in current state can reduce coupling in some cases. To evaluate the mechanism, gem5 simulator is used for data extraction and several benchmarks are taken from the SPEC2006 suite. The simulation results show that the proposed mechanism reduces crosstalk noise with only 30 imposed TSV overhead while delay decreased up to 25.7 as compared to a recent related work.
Increasing TSV distances from each other, shielding TSVs, inserting buffers at the victim side, inserting buffers, decreasing driver size at the aggressor side, and increasing load at the wires are the mechanisms examined in @cite_20 to mitigate TSVs crosstalk noise. According to their experiments, unlike 2D wires, increasing TSV distances is not an effective solution to TSV-to-TSV coupling problem and the other solutions either need high effort at post-design time or have negative impact on timing performance.
@cite_20
2133279383 2017619982 2043630110 2117549011
This paper studies TSV-to-TSV coupling in 3D ICs. A full-chip SI analysis flow is proposed based on the proposed coupling model. Analysis results show that TSVs cause significant coupling noise and timing problems despite that TSV count is much smaller com- pared with the gate count. Two approaches are proposed to alleviate TSV-to-TSV coupling, namely TSV shielding and buffer insertion. Analysis results show that both approaches are effective in reducing the TSV-caused-coupling and improving timing. In 3D VLSI, through-silicon vias (TSVs) are relatively large, and closely spaced. This results in a situation in which noise on one or more TSVs may deteriorate the delay and signal integrity of neighboring TSVs. In this paper, we first quantify the parasitics in contemporary TSVs, and then come up with a classification of crosstalk sequences as OC, 1C,... 8C sequences. Next, we present inductive approaches to quantify the exact overhead for 8C, 6C and 4C crosstalk avoidance codes (CACs) for a 3 x n mesh arrangement of TSVs. These overheads for different CACs for a 3 x n mesh arrangement of TSVs are used to calculate the lower bounds on the corresponding overheads for an n x n mesh arrangements of TSVs. We also discuss an efficient way to implement the coding and decoding (CODEC) circuitry for limiting the maximum crosstalk to 6C. Our experimental results show that for a TSV mesh arrangement driven by inverters implemented in a 22nm technology, the coding based approaches yields improvements which are in line with the theoretical predictions. As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays a dominant part in wire load, crosstalk interference becomes a serious problem for VLSI design. We focused on the delay increase caused by crosstalk. On-chip bus delay is maximized by the crosstalk effect when adjacent wires simultaneously switch for opposite signal transition directions. This paper proposes a bus delay reduction technique by intentional skewing signal transition timing of adjacent wires. An approximated equation of bus delay shows our delay reduction technique is effective for a repeater-inserted bus. The result of SPICE simulation shows that the total bus delay reduction by from 5 to 20 can be achieved. Placing shields around a victim signal line is a common way to enhance signal integrity while minimizing delay uncertainty. For two coupled interconnects with a shield between the lines, the coupling noise can produce a peak noise of 15 of V sub dd in a 0.18 spl mu m CMOS technology. A pseudo-2 spl pi RC model is used to develop an analytic estimate of the peak noise for shielded interconnects. The peak noise model is accurate within an average error of 4.4 as compared to SPICE. The effects of the shield width, length, separation between the shield and the signal, and the number of connections tieing the shield to ground on the overall crosstalk noise are described in this paper. Based on the peak noise model, a minimum number of ground connections for a target shield line with noise constraints is obtained. Inserting a shield line between two coupled interconnects is shown to be more effective in reducing crosstalk noise than increasing the physical separation.