Three Dimensional Integrated Circuits (3D IC) offer lower power consumption, higher performance, higher bandwidth, and scalability over the conventional two dimensional ICs. Through-Silicon Via (TSV) is one of the fabrication mechanisms that connects stacked dies to each other. The large size of TSVs and the proximity between them lead to undesirable coupling capacitance. This interference causes mutual influences between adjacent TSVs and produces crosstalk noise. Furthermore, this effect threats the reliability of data during traversal between layers. This paper proposes a mechanism that efficiently reduces crosstalk noise between TSVs with lower area overhead as compared to previous works. This mechanism revolves around the fact that retaining TSV value in current state can reduce coupling in some cases. To evaluate the mechanism, gem5 simulator is used for data extraction and several benchmarks are taken from the SPEC2006 suite. The simulation results show that the proposed mechanism reduces crosstalk noise with only 30 imposed TSV overhead while delay decreased up to 25.7 as compared to a recent related work.
In the context of (2D NoC), there are plenty of works that target power consumption @cite_5 @cite_2 @cite_25 , reliability @cite_5 , security @cite_17 , or performance @cite_5 of the interconnections. Particularly, crosstalk minimization methods can be classified in three categories: physical level, transistor level and, (RTL) techniques. Wire spacing @cite_4 , active and passive shielding @cite_9 , and buffer insertion @cite_11 are examples of physical level techniques. @cite_15 is a transistor level mechanism which reduces the crosstalk noise by skewing the simultaneous opposite transitions. Although this approach reduces the crosstalk, it requires timing adjustment between senders and receivers. Furthermore, this approach suffers from run-time management. The general idea behind RTL level techniques is to omit some undesirable transition patterns by using coding schemes. There are variety of works that focused on analytical aspect and coding concepts @cite_26 @cite_7 . Error detection codes and error correction codes @cite_0 , joint crosstalk avoidance mechanism @cite_7 , and CACs @cite_0 are examples of these coding schemes.
@cite_11 @cite_4 @cite_26 @cite_7 @cite_9 @cite_0 @cite_2 @cite_5 @cite_15 @cite_25 @cite_17
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Interconnect delay has become a limiting factor for circuit performance in deep sub-micrometer designs. As the crosstalk in an on-chip bus is highly dependent on the data patterns transmitted on the bus, different crosstalk avoidance coding schemes have been proposed to boost the bus speed and or reduce the overall energy consumption. Despite the availability of the codes, no systematic mapping of data words to codewords has been proposed for CODEC design. This is mainly due to the nonlinear nature of the crosstalk avoidance codes (CAC). The lack of practical CODEC construction schemes has hampered the use of such codes in practical designs. This work presents guidelines for the CODEC design of the ldquoforbidden pattern free crosstalk avoidance coderdquo (FPF-CAC). We analyze the properties of the FPF-CAC and show that mathematically, a mapping scheme exists based on the representation of numbers in the Fibonacci numeral system. Our first proposed CODEC design offers a near-optimal area overhead performance. An improved version of the CODEC is then presented, which achieves theoretical optimal performance. We also investigate the implementation details of the CODECs, including design complexity and the speed. Optimization schemes are provided to reduce the size of the CODEC and improve its speed. In 3D VLSI, through-silicon vias (TSVs) are relatively large, and closely spaced. This results in a situation in which noise on one or more TSVs may deteriorate the delay and signal integrity of neighboring TSVs. In this paper, we first quantify the parasitics in contemporary TSVs, and then come up with a classification of crosstalk sequences as OC, 1C,... 8C sequences. Next, we present inductive approaches to quantify the exact overhead for 8C, 6C and 4C crosstalk avoidance codes (CACs) for a 3 x n mesh arrangement of TSVs. These overheads for different CACs for a 3 x n mesh arrangement of TSVs are used to calculate the lower bounds on the corresponding overheads for an n x n mesh arrangements of TSVs. We also discuss an efficient way to implement the coding and decoding (CODEC) circuitry for limiting the maximum crosstalk to 6C. Our experimental results show that for a TSV mesh arrangement driven by inverters implemented in a 22nm technology, the coding based approaches yields improvements which are in line with the theoretical predictions. 3D integration is one of the promising solutions to overcome the interconnect bottleneck with vertical interconnect through-silicon vias (TSVs). This paper investigates the crosstalk in 3D IC designs, especially the capacitive crosstalk in TSV interconnects. We propose a novel ω-LAT coding scheme to reduce the capacitive crosstalk and minimize the power consumption overhead in the TSV array. Combining with the Transition Signaling, the LAT coding scheme restricts the number of transitions in every transmission cycle to minimize the crosstalk and power consumption. Compared to other 3D crosstalk minimization coding schemes, the proposed coding can provide the same delay reduction with more affordable overhead. The performance and power analysis show that when ω is 4, the proposed LAT coding scheme can achieve 38 interconnect crosstalk delay reduction compared to the data transmission without coding. By reducing the value of ω, further reduction can be achieved1. Capacitive crosstalk between adjacent signal wires has significant effect on performance and delay uncertainty of point-to-point on-chip buses in deep submicrometer (DSM) VLSI technologies. We propose a hybrid polarity repeater insertion technique that combines inverting and non-inverting repeater insertion to achieve constant average effective coupling capacitance per wire transition for all possible switching patterns. Theoretical analysis shows the superiority of the proposed method in terms of performance and delay uncertainty compared to conventional and staggered repeater insertion methods. Simulations at the 90-nm node on semi-global METAL5 layer show around 25 reduction in worst case delay and around 86 delay uncertainty minimization compared to standard bus with optimal repeater configuration. The reduction in worst case capacitive coupling reduces peak energy which is a critical factor for thermal regulation and packaging. Isodelay comparisons with standard bus show that the proposed technique achieves considerable reduction in total buffers area, which in turn reduces average energy and peak current. Comparisons with staggered repeater which is one of the simplest and most effective crosstalk reduction techniques in the literature show that hybrid polarity repeater offers higher performance, less delay uncertainty, and reduced sensitivity to repeater placement variation.