System self-tuning is a crucial task to lower the energy consumption of computers. Traditional approaches decrease the processor frequency in idle or synchronisation periods. However, in High-Performance Computing (HPC) this is not sufficient: if the executed code is load balanced, there are neither idle nor synchronisation phases that can be exploited. Therefore, alternative self-tuning approaches are needed, which allow exploiting different compute characteristics of HPC programs. The novel notion of application regions based on function call stacks, introduced in the Horizon 2020 Project READEX, allows us to define such a self-tuning approach. In this paper, we combine these regions with the Q-Learning typical state-action maps, which save information about available states, possible actions to take, and the expected rewards. By exploiting the existing processor power interface, we are able to provide direct feedback to the learning process. This approach allows us to save up to 15 energy, while only adding a minor runtime overhead.
Another example is given by Shen et. ,al. @cite_7 , who use Q-Learning to find a trade-off between temperature, performance, and energy. They define a state as a combination of instructions per second, stall cycles, the current processor frequency, and the current processor temperature. This state is captured and evaluated every 10 ,ms. Based on the observations, they calculate a reward, which is used to update the Q-value. Based on the information, an action is taken, i.e., the frequency is changed. Shen et. ,al. use models to evaluate the performance and energy impact of their decisions. However, these models can result in wrong predictions and have to be carefully chosen. By using well-defined program regions, we can measure the energy and performance impacts, which is more precise than a model evaluated every 10 ,ms.
@cite_7
2171195786 2474890436 2099961254 2133039052
The vast number of transistors available through modern fabrication technology gives architects an unprecedented amount of freedom in chip-multiprocessor (CMP) designs. However, such freedom translates into a design space that is impossible to fully, or even partially to any significant fraction, explore through detailed simulation. In this paper we propose to address this problem using predictive modeling, a well-known machine learning technique. More specifically we build models that, given only a minute fraction of the design space, are able to accurately predict the behavior of the remaining designs orders of magnitude faster than simulating them. In contrast to previous work, our models can predict performance metrics not only for unseen CMP configurations for a given application, but also for unseen configurations of a new application that was not in the set of applications used to build the model, given only a very small number of results for this new application. We perform extensive experiments to show the efficacy of the technique for exploring the design space of CMP's running parallel applications. The technique is used to predict both energy-delay and execution time. Choosing both explicitly parallel applications and applications that are parallelized using the thread-level speculation (TLS) approach, we evaluate performance on a CMP design space with about 95 million points using 18 benchmarks with up to 1000 training points each. For predicting the energy-delay metric, prediction errors for unseen configurations of the same application range from 2.4 to 4.6 and for configurations of new applications from 3.1 to 4.9 . The increasing popularity of micro-scale power-scavenging techniques for wireless sensor networks (WSNs) is paving the way to energy-autonomous sensing systems. To sustain perpetual operations, however, environmentally powered devices must adapt their workload to the stochastic nature of ambient sources. Energy prediction models, which estimate the future expected energy intake, are effective tools to support the development of proactive power management strategies. In this paper, we present profile energy prediction model (Pro-Energy), an energy prediction model for multi-source energy-harvesting WSNs that leverages past energy observations to forecast future energy availability. We then propose Pro-Energy with variable-length timeslots (Pro-Energy-VLT), an extension of Pro-Energy that combines our energy predictor with timeslots of variable lengths to adapt to the dynamics of the power source. To assess the performance of our proposed solutions, we use real-life solar and wind traces, as well as publicly available traces of solar irradiance and wind speed. A comparative performance evaluation shows that Pro-Energy significantly outperforms the state-of-the-art energy predictors, by improving the prediction accuracy of up to 67 . Moreover, by adapting the granularity of the prediction timeslots to the dynamics of the energy source, Pro-Energy-VLT further improves the prediction accuracy, while reducing the memory footprint and the energy overhead of energy forecasting. The energy usage of computer systems is becoming an important consideration, especially for battery-operated systems. Various methods for reducing energy consumption have been investigated, both at the circuit level and at the operating systems level. In this paper, we propose a simple model of job scheduling aimed at capturing some key aspects of energy minimization. In this model, each job is to be executed between its arrival time and deadline by a single processor with variable speed, under the assumption that energy usage per unit time, P, is a convex function, of the processor speed s. We give an off-line algorithm that computes, for any set of jobs, a minimum-energy schedule. We then consider some on-line algorithms and their competitive performance for the power function P(s)=s sup p where p spl ges 2. It is shown that one natural heuristic, called the Average Rate heuristic, uses at most a constant times the minimum energy required. The analysis involves bounding the largest eigenvalue in matrices of a special type. When peak performance is unnecessary, Dynamic Voltage Scaling (DVS) can be used to reduce the dynamic power consumption of embedded multiprocessors. In future technologies, however, static power consumption due to leakage current is expected to increase significantly. Then it will be more effective to limit the number of processors employed (i.e., turn some of them off), or to use a combination of DVS and processor shutdown. In this paper, leakage-aware scheduling heuristics are presented that determine the best trade-off between these three techniques: DVS, processor shutdown, and finding the optimal number of processors. Experimental results obtained using a public benchmark set of task graphs and real parallel applications show that our approach reduces the total energy consumption by up to 46 for tight deadlines (1.5× the critical path length) and by up to 73 for loose deadlines (8× the critical path length) compared to an approach that only employs DVS. We also compare the energy consumed by our scheduling algorithms to two absolute lower bounds, one for the case where all processors continuously run at the same frequency, and one for the case where the processors can run at different frequencies and these frequencies may change over time. The results show that the energy reduction achieved by our best approach is close to these theoretical limits.