Keypoint-based methods are a relatively new paradigm in object detection, eliminating the need for anchor boxes and offering a simplified detection framework. Keypoint-based CornerNet achieves state of the art accuracy among single-stage detectors. However, this accuracy comes at high processing cost. In this work, we tackle the problem of efficient keypoint-based object detection and introduce CornerNet-Lite. CornerNet-Lite is a combination of two efficient variants of CornerNet: CornerNet-Saccade, which uses an attention mechanism to eliminate the need for exhaustively processing all pixels of the image, and CornerNet-Squeeze, which introduces a new compact backbone architecture. Together these two variants address the two critical use cases in efficient object detection: improving efficiency without sacrificing accuracy, and improving accuracy at real-time efficiency. CornerNet-Saccade is suitable for offline processing, improving the efficiency of CornerNet by 6.0x and the AP by 1.0 on COCO. CornerNet-Squeeze is suitable for real-time detection, improving both the efficiency and accuracy of the popular real-time detector YOLOv3 (34.4 AP at 34ms for CornerNet-Squeeze compared to 33.0 AP at 39ms for YOLOv3 on COCO). Together these contributions for the first time reveal the potential of keypoint-based detection to be useful for applications requiring processing efficiency.
The efficiency of ConvNets is important to many mobile and embedded applications. Much attention @cite_27 @cite_37 @cite_59 @cite_10 @cite_46 @cite_22 @cite_28 has been given to the design of efficient network architectures.
@cite_37 @cite_22 @cite_28 @cite_27 @cite_59 @cite_46 @cite_10
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Designing accurate and efficient ConvNets for mobile devices is challenging because the design space is combinatorially large. Due to this, previous neural architecture search (NAS) methods are computationally expensive. ConvNet architecture optimality depends on factors such as input resolution and target devices. However, existing approaches are too expensive for case-by-case redesigns. Also, previous work focuses primarily on reducing FLOPs, but FLOP count does not always reflect actual latency. To address these, we propose a differentiable neural architecture search (DNAS) framework that uses gradient-based methods to optimize ConvNet architectures, avoiding enumerating and training individual architectures separately as in previous methods. FBNets, a family of models discovered by DNAS surpass state-of-the-art models both designed manually and generated automatically. FBNet-B achieves 74.1 top-1 accuracy on ImageNet with 295M FLOPs and 23.1 ms latency on a Samsung S8 phone, 2.4x smaller and 1.5x faster than MobileNetV2-1.3 with similar accuracy. Despite higher accuracy and lower latency than MnasNet, we estimate FBNet-B's search cost is 420x smaller than MnasNet's, at only 216 GPU-hours. Searched for different resolutions and channel sizes, FBNets achieve 1.5 to 6.4 higher accuracy than MobileNetV2. The smallest FBNet achieves 50.2 accuracy and 2.9 ms latency (345 frames per second) on a Samsung S8. Over a Samsung-optimized FBNet, the iPhone-X-optimized model achieves a 1.4x speedup on an iPhone X. Abstract Convolutional networks (ConvNets) have become a popular approach to computer vision. Here we consider the parallelization of ConvNet training, which is computationally costly. Our novel parallel algorithm is based on decomposition into a set of tasks, most of which are convolutions or FFTs. Theoretical analysis suggests that linear speedup with the number of processors is attainable. To attain such performance on real shared-memory machines, our algorithm computes convolutions converging on the same node of the network with temporal locality to reduce cache misses, and sums the convergent convolution outputs via an almost wait-free concurrent method to reduce time spent in critical sections. Benchmarking with multi-core CPUs shows speedup roughly equal to the number of physical cores. We also demonstrate 90x speedup on a many-core CPU (Xeon Phi Knights Corner). Our algorithm can be either faster or slower than certain GPU implementations depending on specifics of the network architecture, kernel sizes, and density and size of the output patch. In order to reduce high construction cost and energy consumption of distributed base stations in cellular networks, the centralized radio access Cellular network infrastructure with a Super BS(CSBS) architecture has been proposed in which the centralized processing resource can be flexibly organized. However, there is sill the problem of low processing resource efficiency in protocol processing. In this paper, based on a protocol processing resource management framework, distributed load diversity based processing resource allocation (D-LDA) as well as the improved hybrid load diversity based processing resource allocation(H-LDA) are proposed, which take load discrepancy into consideration in the situation that a large number of BSs are supported. Simulation results show that D-LDA and H-LDA algorithm significantly outperforms the conventional method respectively by more than 30 and 55 in the processing resource efficiency. This paper proposes CoNoC (Contention-free optical NoC) as a new architecture for on-chip routing of optical packets. CoNoC is built upon all-optical switches (AOSs) which passively route optical data streams based on their wavelengths. The key idea of the proposed architecture is the utilization of per-receiver wavelength in the data network to prevent optical contention at the intermediate nodes. Routing optical packets according to their wavelength eliminates the need for resource reservation at the intermediate nodes and the corresponding latency, power, and area overheads. Since passive architecture of the AOS confines the optical contention to the end-points, we propose an electrical arbitration architecture for resolving optical contention at the destination nodes. By performing a series of simulations, we study the efficiency of the proposed architecture, its power and energy consumption, and the data transmission latency. Moreover, we compare the proposed architecture with electrical NoCs and alternative ONoC architectures under various synthetic traffic patterns. Averaged across different traffic patterns, the proposed architecture reduces per-packet power consumption by 19 , 28 , 29 , and 91 and achieves per-packet energy reduction of 28 , 40 , 20 , and 99 over Columbia, Phastlane, @l-router, and electrical torus, respectively.