Accelerating inexact string matching procedures is of utmost importance when dealing with practical applications, where huge amount of data must be processed in real time, as usual in bioinformatics or cybersecurity. Inexact matching procedures can yield multiple shadow hits, which must be filtered according to some criterion, to obtain a concise and meaningful list of occurrences. The filtering procedures are often computationally demanding and are performed offline in a post-processing phase. This paper introduces a novel algorithm for Online Approximate String Matching (OASM) able to filter shadow hits on the fly, according to general purpose heuristic rules that greedily assign priorities to overlapping hits. An FPGA hardware implementation of OASM is proposed and compared with a serial software version, showing that even on entry level FPGAs the procedure can reach a high degree of parallelism, with a low usage of logic elements. This makes the proposed architecture very competitive in terms of both performances and cost of the overall computing system.
FPGA implementations of systolic architectures have been proposed for ASM @cite_67 @cite_36 and, in bioinformatics, for DNA sequence alignment @cite_66 @cite_47 @cite_78 . In the field of Music Information Retrieval (MIR), circuits implementing ASM with dynamic programming cannot retrieve fragments with different sizes @cite_68 and other architectures with higher flexibility only support symbol substitution @cite_28 . Better performance was achieved by Application-Specific Integrated Circuit and FPGA with a comparable computational time on different MIR approaches @cite_32 @cite_79 @cite_58 @cite_80 . An efficient FPGA implementation of ASM has been proposed for text mining, where a restricted class of regular expressions is used to define the patterns to search @cite_44 . A work closely related to this paper is a successful implementation of online ASM on FPGA for NIDS applications @cite_40 .
@cite_67 @cite_78 @cite_36 @cite_28 @cite_58 @cite_32 @cite_44 @cite_79 @cite_40 @cite_80 @cite_47 @cite_68 @cite_66
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This paper describes a novel approach of packing sparse convolutional neural networks for their efficient systolic array implementations. By combining subsets of columns in the original filter matrix associated with a convolutional layer, we increase the utilization efficiency of the systolic array substantially (e.g., 4x) due to the increased density of nonzeros in the resulting packed filter matrix. In combining columns, for each row, all filter weights but one with the largest magnitude are pruned. We retrain the remaining weights to preserve high accuracy. We demonstrate that in mitigating data privacy concerns the retraining can be accomplished with only fractions of the original dataset (e.g., 10 for CIFAR-10). We study the effectiveness of this joint optimization for both high utilization and classification accuracy with ASIC and FPGA designs based on efficient bit-serial implementations of multiplier-accumulators. We present analysis and empirical evidence on the superior performance of our column combining approach against prior arts under metrics such as energy efficiency (3x) and inference latency (12x). A novel field programmable gate array (FPGA) implementation of content-based music retrieval system is presented in this paper. The system adopts a novel hardware architecture for approximate string matching. The architecture is based on a simple shift-and-or algorithm. It has the advantages of low area cost and high throughput. Numerical results show that the proposed architecture has significantly lower CPU time over its software counterpart running on Pentium IV for large database and or edit distances. Industry is increasingly turning to reconfigurable architectures like FPGAs and CGRAs for improved performance and energy efficiency. Unfortunately, adoption of these architectures has been limited by their programming models. HDLs lack abstractions for productivity and are difficult to target from higher level languages. HLS tools are more productive, but offer an ad-hoc mix of software and hardware abstractions which make performance optimizations difficult. In this work, we describe a new domain-specific language and compiler called Spatial for higher level descriptions of application accelerators. We describe Spatial's hardware-centric abstractions for both programmer productivity and design performance, and summarize the compiler passes required to support these abstractions, including pipeline scheduling, automatic memory banking, and automated design tuning driven by active machine learning. We demonstrate the language's ability to target FPGAs and CGRAs from common source code. We show that applications written in Spatial are, on average, 42 shorter and achieve a mean speedup of 2.9x over SDAccel HLS when targeting a Xilinx UltraScale+ VU9P FPGA on an Amazon EC2 F1 instance. This paper presents efficient dataflow schemes for parallel string matching. Two subproblems known as the exact matching and the k-mismatches problems are covered. Three parallel algorithms based on multiple input (and output) streams are presented. Time complexities of these parallel algorithms are O((n d)+ spl alpha ), O spl les spl alpha spl les m, where n and m represent lengths of reference and pattern strings (n spl Gt m) and d represents the number of streams used (the degree of parallelism). We can control the degree of parallelism by using variable number (d) of input (and output) streams. These performances are better than those found in the literature. These algorithms present three different methods to design special purpose systolic array hardware for string matching. With linear systolic array architecture, m PEs are needed for serial design and d*m PEs are needed for parallel design.