We present a deep, fully convolutional neural network that learns to route a circuit layout net with appropriate choice of met al tracks and wire class combinations. Inputs to the network are the encoded layouts containing spatial location of pins to be routed. After 15 fully convolutional stages followed by a score comparator, the network outputs 8 layout layers (corresponding to 4 route layers, 3 via layers and an identity-mapped pin layer) which are then decoded to obtain the routed layouts. We formulate this as a binary segmentation problem on a per-pixel per-layer basis, where the network is trained to correctly classify pixels in each layout layer to be 'on' or 'off'. To demonstrate learnability of layout design rules, we train the network on a dataset of 50,000 train and 10,000 validation samples that we generate based on certain pre-defined layout constraints. Precision, recall and @math score metrics are used to track the training progress. Our network achieves @math on the train set and @math on the validation set. We use PyTorch for implementing our model. Code is made publicly available at this https URL .
The task of producing routes using orthogonal layers of parallel channels and vias at intersections is often tackled heuristically, since an optimal solution does not exist for this NP-complete problem @cite_11 @cite_0 @cite_18 @cite_5 . Previous work in this field @cite_22 @cite_16 @cite_6 @cite_19 @cite_27 @cite_24 mostly rely on explicit rule-based algorithms to tackle parts of this complex task. For instance, Zajc al @cite_24 proposed using hierarchical algorithms for automatic routing of interconnects in two layer channels. Rivest al @cite_16 show a "greedy" heuristic channel router assuming all pins and wiring sit on a common grid. The other class of routers, which have received attention lately, are objective function based. Alpert al @cite_20 proposed a combination of minimum spanning tree (Prim) and shortest path tree (Dijkstra) objectives for performance driven global routing. Constructing routing tree with different objectives was also explored, such as timing objective @cite_14 , buffer insertion @cite_17 and wire sizing objective @cite_4 , congestion and thermal objective @cite_2 @cite_1 . A completely different objective for diagonal routing as opposed to the orthogonal (Manhattan) routing was also proposed @cite_9 .
@cite_18 @cite_14 @cite_4 @cite_22 @cite_9 @cite_1 @cite_17 @cite_6 @cite_0 @cite_19 @cite_27 @cite_24 @cite_2 @cite_5 @cite_16 @cite_20 @cite_11
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The throughput of wireless networks can be significantly improved by multi-channel communications compared with single-channel communications since the use of multiple channels can reduce interference influence. In this paper, we study interference-aware topology control and QoS routing in IEEE 802.11-based multi-channel wireless mesh networks with dynamic traffic. Channel assignment and routing are two basic issues in such networks. Different channel assignments can lead to different network topologies. We present a novel definition of co-channel interference. Based on this concept, we formally define and present an effective heuristic for the minimum INterference Survivable Topology Control (INSTC) problem which seeks a channel assignment for the given network such that the induced network topology is interference-minimum among all K-connected topologies. We then formulate the Bandwidth-Aware Routing (BAR) problem for a given network topology, which seeks routes for QoS connection requests with bandwidth requirements. We present a polynomial time optimal algorithm to solve the BAR problem under the assumption that traffic demands are splittable. For the non-splittable case, we present a maximum bottleneck capacity path routing heuristic. Simulation results show that compared with the simple common channel assignment and shortest path routing approach, our scheme improves the system performance by 57 on average in terms of connection blocking ratio. Buffer insertion and wire sizing are critical in deep submicron VLSI design. This paper studies the problem of constructing routing trees with simultaneous buffer insertion and wire sizing in the presence of routing and buffer obstacles. No previous algorithms consider all these factors simultaneously. Previous dynamic programming based algorithm is first extended to solve the problem. However, with the size of routing graph increasing and with wire sizing taken into account, the time and space requirement increases enormously. Then a new approach is proposed to formulate the problem as a series of graph problems. The routing tree solution is obtained by finding shortest paths in a series of graphs. In the new approach, wire sizing can be handled almost without any additional time and space requirement, Moreover, the time and space requirement is only polynomial in terms of the size of routing graph. Our algorithm differs from traditional dynamic programming, and is capable of addressing the problem of inverter insertion and sink polarity. Both theoretical and experimental results show that the graph-based algorithm outperforms the DP-based algorithm by a large margin. We also propose a hierarchical approach to construct routing tree for a large number of sinks. Motivated by analysis of distributed RC delay in routing trees, a new tree construction is proposed for performance-driven global routing which directly trades off between Prim's minimum spanning tree algorithm and Dijkstra's shortest path tree algorithm. This direct combination of two objective functions and their corresponding optimal algorithms contrasts with the more indirect 'shallow-light' methods. The authors' method achieves routing trees which satisfy a given routing tree radius bound while using less wire than previous methods. Detailed simulations show that these wirelength savings translate into significantly improved delay over standard MST routing in both IC and multichip module (MCM) interconnect technologies. > This paper studies a multi-facility network synthesis problem, called the Two-level Network Design (TLND) problem, that arises in the topological design of hierarchical communication, transportation, and electric power distribution networks. We are given an undirected network containing two types of nodes---primary and secondary---and fixed costs for installing either a primary or a secondary facility on each edge. Primary nodes require higher grade interconnections than secondary nodes, using the more expensive primary facilities. The TLND problem seeks a minimum cost connected design that spans all the nodes, and connects primary nodes via edges containing primary facilities; the design can use either primary or secondary edges to connect the secondary nodes. The TLND problem generalizes the well-known Steiner network problem and the hierarchical network design problem. In this paper, we study the relationship between alternative model formulations for this problem (e.g., directed and undirected models), and analyze the worst-case performance for a composite TLND heuristic based upon solving embedded subproblems (e.g., minimum spanning tree and either Steiner tree or shortest path subproblems). When the ratio of primary to secondary costs is the same for all edges and when we solve the embedded subproblems optimally, the worst-case performance ratio of the composite TLND heuristic is 4 3. This result applies to the hierarchical network design problem with constant primary-to-secondary cost ratio since its subproblems are shortest path and minimum spanning tree problems. For more general situations, we express the TLND heuristic worst-case ratio in terms of the performance of any heuristic used to solve the embedded Steiner tree subproblem. A companion paper develops and tests a dual ascent procedure that generates tight upper and lower bounds on the optimal value of a multi-level extension of this problem.