With technology scaling down, hundreds and thousands processing elements (PEs) can be integrated on a single chip. Network-on-chip (NoC) has been proposed as an efficient solution to handle this distinctive challenge. In this thesis, we have explored the high performance NoC design for MPSoC and CMP structures from the performance modeling in the offline design phase to the routing algorithm and NoC architecture optimization. More specifically, we first deal with the issue of how to estimate an NoC design fast and accurately in the synthesis inner loop. For this purpose, we propose a machine learning based latency regression model to evaluate the NoC designs with respect to different configurations. Then, for high performance NoC designs, we tackle one of the most important problems, i.e., the routing algorithms design. For avoiding temperature hotspots, a thermal-aware routing algorithm is proposed to achieve an even temperature profile for application-specific Network-on-chips (NoCs). For improving the reliability, a routing algorithm to achieve maximum performance under fault is proposed. Finally, in the architecture level, we propose two new NoC structures using bi-directional links for the performance optimization. In particular, we propose a flit-level speedup scheme to enhance the network-on-chip(NoC) performance utilizing bidirectional channels. We also propose a flexible NoC architecture which takes advantage of a dynamic distributed routing algorithm and improves the NoC communication performance with moderate energy overhead. From the simulation results on both synthetic traffic and real workload traces, significant performance improvement in terms of latency and throughput can be achieved.
Since the power consumption of the routers is as significant as the processor core, the thermal constraint should also be addressed in the routing algorithm design. There have been a lot of works on NoC routing algorithms for various purposes including low power routing @cite_106 , fault-tolerant routing @cite_109 and congestion avoidance routing to improve latency @cite_52 . However, there are only a few works @cite_34 @cite_50 @cite_93 taking temperature issue into account.
@cite_109 @cite_52 @cite_106 @cite_50 @cite_93 @cite_34
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With the advent in technology and shrinking the transistor size down to nano scale, static power may become the dominant power component in Networks-on-Chip (NoCs). Powergating is an efficient technique to reduce the static power of under-utilized resources in different types of circuits. For NoC, routers are promising candidates for power gating, since they present high idle time. However, routers in a NoC are not usually idle for long consecutive cycles due to distribution of resources in NoC and its communication-based nature, even in low network utilizations. Therefore, power-gating loses its efficiency due to performance and power overhead of the packets that encounter powered-off routers. In this paper, we propose Turn-on on Turn (TooT) which reduces the number of wake-ups by leveraging the characteristics of deterministic routing algorithms and mesh topology. In the proposed method, we avoid powering a router on when it forwards a straight packet or ejects a packet, i.e., a router is powered on only when either a packet turns through it or its associated node injects a packet. Experimental results on PARSEC benchmarks demonstrate that, compared with the conventional power-gating, the proposed method improves static power and performance by 57.9 and 35.3 , respectively, at the cost of a negligible area overhead. This paper proposes CoNoC (Contention-free optical NoC) as a new architecture for on-chip routing of optical packets. CoNoC is built upon all-optical switches (AOSs) which passively route optical data streams based on their wavelengths. The key idea of the proposed architecture is the utilization of per-receiver wavelength in the data network to prevent optical contention at the intermediate nodes. Routing optical packets according to their wavelength eliminates the need for resource reservation at the intermediate nodes and the corresponding latency, power, and area overheads. Since passive architecture of the AOS confines the optical contention to the end-points, we propose an electrical arbitration architecture for resolving optical contention at the destination nodes. By performing a series of simulations, we study the efficiency of the proposed architecture, its power and energy consumption, and the data transmission latency. Moreover, we compare the proposed architecture with electrical NoCs and alternative ONoC architectures under various synthetic traffic patterns. Averaged across different traffic patterns, the proposed architecture reduces per-packet power consumption by 19 , 28 , 29 , and 91 and achieves per-packet energy reduction of 28 , 40 , 20 , and 99 over Columbia, Phastlane, @l-router, and electrical torus, respectively. The inefficiency of energy usage on the Internet has become a critical problem with its rapid growth, as all network devices operate at full capacity in spite of the real traffic load. Existing studies try to develop energy efficient routings by aggregating traffic and switching underutilized devices into sleep mode. However, most existing approaches do not address the problem of routing convergence well. Since traffic changes frequently in a network, routing convergence may be triggered frequently for an energy efficient routing, which may induce routing loops and black holes, resulting in severe packet loss. In this paper, we present a fast rerouting-based (FRR-based) energy efficient routing scheme, namely GreenFRR, which leverages the technique of fast rerouting to reduce the convergence time. We first study typical fast rerouting techniques and address the challenge of guaranteeing loop-free routing. Then, we formalize the FRR-based energy efficient routing problem and prove that the problem is NP-hard. In order to solve this problem, we design heuristic algorithms to maximize the number of sleeping links. In particular, we consider link utilization ratio and path stretch in our algorithms. We evaluate our scheme by simulations on real and synthetic topologies with real and synthetic traffic traces. The results show that the power consumed by line cards achieves a saving of 40 and the convergence time can be reduced by 95 . Hard real-time embedded systems impose a strict latency requirement on interconnection subsystems. In the case of network-on-chip (NoC), this means each packet of a traffic stream has to be delivered within a time interval. In addition, with the increasing complexity of NoC, it consumes a significant portion of total chip power, which boosts the power footprint of such chips. In this work, we propose a methodology to minimize the energy consumption of NoC without violating the pre-specified latency deadlines of real-time applications. First, we develop a formal approach based on network calculus to obtain the worst-case delay bound of all packets, from which we derive a safe estimate of the number of cycles that a packet can be further delayed in the network without violating its deadline---the worst-case slack. With this information, we then develop an optimization algorithm that trades the slacks for lower NoC energy. Our algorithm recognizes the distribution of slacks for different traffic streams, and assigns different voltages and frequencies to different routers to achieve NoC energy-efficiency, while meeting the deadlines for all packets.