The alignment of code in the flash memory of deeply embedded SoCs can have a large impact on the total energy consumption of a computation. We investigate the effect of code alignment in six SoCs and find that a large proportion of this energy (up to 15 of total SoC energy consumption) can be saved by changes to the alignment. A flexible model is created to predict the read-access energy consumption of flash memory on deeply embedded SoCs, where code is executed in place. This model uses the instruction level memory accesses performed by the processor to calculate the flash energy consumption of a sequence of instructions. We derive the model parameters for five SoCs and validate them. The error is as low as 5 , with a 11 average normalized RMS deviation overall. The scope for using this model to optimize code alignment is explored across a range of benchmarks and SoCs. Analysis shows that over 30 of loops can be better aligned. This can significantly reduce energy while increasing code size by less than 4 . We conclude that this effect has potential as an effective optimization, saving significant energy in deeply embedded SoCs.
Other software optimizations targeting energy have considered automatically inserting idle instructions @cite_24 , instruction scheduling @cite_22 , use of SIMD @cite_26 and exploiting differences in functional units @cite_4 .
@cite_24 @cite_26 @cite_4 @cite_22
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In this paper, we consider processors which provide an idle instruction to the user for powering down processor units which are not required during portions of program execution. We describe algorithms which can be implemented in an energy-aware compiler to make efficient use of such an instruction. These algorithms are based on program static analysis and a combinatorial optimization formulation of the problem. We assume as input an assembly language program of the processor in question. The problem is to insert the idle instruction at different places in the assembly language program such that energy saving is maximized and the execution time of the resulting program is not increased beyond a user-specified value. Reducing energy consumption has become an important issue in designing hardware and software systems in recent years. Although low power hardware components are critical for reducing energy consumption, the switching activity, which is the main source of dynamic power dissipation in electronic systems, is largely determined by the software running on these systems. In this paper we present and evaluate several instruction scheduling algorithms that reorder a given sequence of instructions taking into account the energy considerations. We first compare a performance-oriented scheduling technique with three energy-oriented instruction scheduling algorithms from both performance (execution cycles of the resulting schedules) and energy consumption points of view. Then, we propose three scheduling algorithms that consider energy and performance at the same time. The results obtained show that these techniques are quite successful in reducing energy consumption and their performance is comparable to that of a pure performance-oriented scheduling. Reducing energy consumption has become an important issue in designing hardware and software systems in recent years. Although low power hardware components are critical for reducing energy consumption, the switching activity, which is the main source of dynamic power dissipation in electronic systems, is largely determined by the software running on these systems. In this paper, we present and evaluate several instruction scheduling algorithms that reorder a given sequence of instructions taking into account the energy considerations. We first compare a performance-oriented scheduling technique with three energy-oriented instruction scheduling algorithms from both performance (execution cycles of the resulting schedules) and energy consumption points of view. Then, we propose three scheduling algorithms that consider energy and performance at the same time. Our experimentation with these scheduling techniques shows that the best scheduling from the performance perspective is not necessarily the best scheduling from the energy perspective. Further, scheduling techniques that consider both energy and performance simultaneously are found to be desirable, that is, these techniques are quite successful in reducing energy consumption and their performance (in terms of execution cycles) is comparable to that of a pure performance-oriented scheduling. We also illuminate the inherent approximations and difficulties in building energy models for enabling energy-aware instruction scheduling and explore alternative options using cycle-accurate energy simulator. The simulation results show that the energy-oriented scheduling reduces energy consumption by up to 30 compared to the performance-oriented scheduling. The increasing demand for portable computing has elevated power consumption to be one of the most critical embedded systems design parameters. In this paper, we present a qualitative study wherein we examine the impact of code transformations on the energy and power consumption. Three main categories of code transformations are investigated, namely data, loop and procedural oriented transformations. Moreover, we evaluate the influence of employing Single Instruction Multiple Data (SIMD) on energy and power dissipation via the utilization of compiler intrinsic C-functions. Results show that a trade-off between power and performance can be achieved by employing the intrinsic C-functions in conjunction with some transformations such as loop unrolling and procedure integration.