Advances in CMOS-compatible photonic elements have made it plausible to exploit nanophotonic communications to overcome the limitations of traditional NoCs. Amongst various proposed nanophotonic architectures, optical crossbars have been shown to provide high performance in terms of bandwidth and latency. In general, optical crossbars provide a vast volume of network resources that are shared among all the cores within the chip. In this paper, we present a fair and efficient admission control mechanism for shared wavelengths and buffer space in optical crossbars. We model buffer management and wavelength assignment as a utility-based convex optimization problem, whose solution determines the admission control policy. Thanks to efficient convex optimization techniques, we obtain the globally optimal solution of the admission control optimization problem by using simple and yet efficient iterative algorithms. We cast our solution procedure as an iterative algorithm to be implemented a central admission controller. Our experimental results corroborate the gain that can be obtained by using such an admission controller to manage the shared resources of the system. Furthermore, they confirm that the proposed admission control algorithm works well for various traffic patterns and parameters, and evinces a tractable scalability with increase in the number of cores of the crossbar.
Various approaches have been proposed to exploit nanophotonics for on-chip communication networks. Development of efficient optical data buffers is still a challenging problem, which makes it quite hard to construct a fully optical packet-switched network. As a result, @cite_9 propose a hybrid approach, in which large data packets are transferred using an optical circuit-switched network whereas the optical network is controlled by an electronic packet-switched network. @cite_43 consider the architecture proposed in @cite_9 and propose a predictive switching and reservation technique to reduce its path setup latency. In some other hybrid architectures such as @cite_10 , local communications are carried out by an electrical network, whereas long distance communications utilize optical links. @cite_13 exploit non-blocking photonic switches as well as light-weight electronic routers to decrease the latency and power overheads of hybrid architectures. Garc ' i a- @cite_4 propose a set of policies to manage hybrid networks consisting of ring-based photonic and electrical mesh sub-networks. The proposed policies use different criteria, such as message size, distance, and photonic ring availability, to decide which sub-network to be used for each message.
@cite_4 @cite_10 @cite_9 @cite_43 @cite_13
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In conventional hybrid PNoC systems, the end-to end optical data transfer is accompanied with electrical control functions including path-setup, acknowledgment, and tear-down. These functions directly a ect the performance and power characteristics of these circuit-switching based systems. In this paper, we propose a novel hybrid PNoC system, named PHENIC-II. 1 Thanks to the adopted non-blocking photonic switch and light-weight electronic router, PHENIC-II is capable of alleviating the congestion in the electronic control layer which is considered as the main source of latency and power overhead in hybrid PNoC systems. From the performance evaluation, we demonstrate that the proposed system has a better performance and low energy dissipation when compared to the previously proposed systems. The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic networks-on-chip (NoC) as a solution to reduce the impact of intra-chip and off-chip communication on the overall power budget. A photonic interconnection network can deliver higher bandwidth and lower latencies with significantly lower power dissipation. We explain why on-chip photonic communication has recently become a feasible opportunity and explore the challenges that need to be addressed to realize its implementation. We introduce a novel hybrid micro-architecture for NoCs combining a broadband photonic circuit-switched network with an electronic overlay packet-switched control network. We address the critical design issues including: topology, routing algorithms, deadlock avoidance, and path-setup tear-down procedures. We present experimental results obtained with POINTS, an event-driven simulator specifically developed to analyze the proposed idea, as well as a comparative power analysis of a photonic versus an electronic NoC. Overall, these results confirm the unique benefits for future generations of CMPs that can be achieved by bringing optics into the chip in the form of photonic NoCs. SUMMARY Nanophotonics promises to solve the scalability problems of current electrical interconnects thanks to its low sensitivity to distance in terms of latency and energy consumption. Before this technology reaches maturity, hybrid photonic-electronic networks will be a viable alternative. Ideally, ordinary electrical meshes and ring-based photonic networks should cooperate to minimize overall latency and energy consumption, but currently, we lack mechanisms to do this efficiently. In this paper, we present novel fine-grain policies to manage the photonic resources in a tiled chip multiprocessor (CMP) scenario. Our policies are dynamic and base their decisions on parameters such as message size, ring availability, and distance between endpoints, at the message level. The resulting network behavior is also fairer to all cores, reducing processor idle time thanks to faster thread synchronization. All these policies improve performance when compared to the same CMP without the photonic ring, and the most elaborate ones reduce the overall network latency by 50 , execution time by 36 , and network energy consumption by 52 on average, in a 16-core CMP for the PARSEC benchmark suite. Larger hybrid networks with 64 endpoints for 256-core CMPs, based on Corona and Firefly designs, also show far superior throughput and lower latency if managed by one of the proposed policies. Copyright © 2014 John Wiley & Sons, Ltd. The potential advantages of optics at high link speeds have led to significant interest in deploying optical switching technology in data-center networks. Initial efforts have focused on hybrid approaches that rely on millisecond-scale circuit switching in the core of the network, while maintaining the flexibility of electrical packet switching at the edge. Recent demonstrations of microsecond-scale optical circuit switches motivate considering circuit switching for more dynamic traffic such as that generated from a top-of-rack (ToR) switch. Based on these technology trends, we propose a prototype hybrid ToR, called REACToR, which utilizes a combination of packet switching and circuit switching to appear to end-hosts as a packet-switched ToR. In this paper, we describe a prototype REACToR control plane which synchronizes end host transmissions with end-to-end circuit assignments. This control plane can react to rapid, bursty changes in the traffic from end hosts on a time scale of 100s of microseconds, several orders of magnitude faster than previous hybrid approaches. Using the experimental data from a system of eight end hosts, we calibrate a hybrid network simulator and use this simulator to predict the performance of larger-scale hybrid networks. This paper proposes CoNoC (Contention-free optical NoC) as a new architecture for on-chip routing of optical packets. CoNoC is built upon all-optical switches (AOSs) which passively route optical data streams based on their wavelengths. The key idea of the proposed architecture is the utilization of per-receiver wavelength in the data network to prevent optical contention at the intermediate nodes. Routing optical packets according to their wavelength eliminates the need for resource reservation at the intermediate nodes and the corresponding latency, power, and area overheads. Since passive architecture of the AOS confines the optical contention to the end-points, we propose an electrical arbitration architecture for resolving optical contention at the destination nodes. By performing a series of simulations, we study the efficiency of the proposed architecture, its power and energy consumption, and the data transmission latency. Moreover, we compare the proposed architecture with electrical NoCs and alternative ONoC architectures under various synthetic traffic patterns. Averaged across different traffic patterns, the proposed architecture reduces per-packet power consumption by 19 , 28 , 29 , and 91 and achieves per-packet energy reduction of 28 , 40 , 20 , and 99 over Columbia, Phastlane, @l-router, and electrical torus, respectively. A range of new datacenter switch designs combine wireless or optical circuit technologies with electrical packet switching to deliver higher performance at lower cost than traditional packet-switched networks. These "hybrid" networks schedule large traffic demands via a high-rate circuits and remaining traffic with a lower-rate, traditional packet-switches. Achieving high utilization requires an efficient scheduling algorithm that can compute proper circuit configurations and balance traffic across the switches. Recent proposals, however, provide no such algorithm and rely on an omniscient oracle to compute optimal switch configurations. Finding the right balance of circuit and packet switch use is difficult: circuits must be reconfigured to serve different demands, incurring non-trivial switching delay, while the packet switch is bandwidth constrained. Adapting existing crossbar scheduling algorithms proves challenging with these constraints. In this paper, we formalize the hybrid switching problem, explore the design space of scheduling algorithms, and provide insight on using such algorithms in practice. We propose a heuristic-based algorithm, Solstice that provides a 2.9× increase in circuit utilization over traditional scheduling algorithms, while being within 14 of optimal, at scale. Future chip multi-processors (CMPs) will require high-performance yet low-energy networks-on-chip to provide scalable communication for the increasing number of cores. CMOS-compatible nanophotonic interconnects have recently emerged as a promising candidate for replacing traditional electrical network-on-chip, by providing high bandwidth chip-wide communication at low latency and power. In this paper, we utilize the emerging nanophotonic technology and propose RCBus, an optical network-on-chip topology in which multiple nanophotonic buses are uniformly distributed in each row and column of a two-dimensional torus network. Each bus employs a dense-wavelength-division-multiplexing optical waveguide to enable high-bandwidth express traversal along each dimension. We use multiple write single-read schemes and virtual channel based token protocol to implement light-speed arbitration and flow control. The optical-electrical interface is also studied in the paper. The proposed optical network-on-chip can exploit the advantages of both photonic bus and direct torus topology. Simulation results under synthetic and real-world application traffic show that RCBus is 2X better in terms of performance than the electrical mesh network-on-chip while saving nearly 30 power, and achieves on average 24 throughput improvement at much lower cost compared to the state-of-the-art optical network. DOI: http: dx.doi.org 10.5755 j01.eee.18.8.2633 We compare three optical transport network architectures—optical packet switching (OPS), optical flow switching (OFS), and optical burst switching (OBS)—based on a notion of network capacity as the set of exogenous traffic rates that can be stably supported by a network under its operational constraints. We characterize the capacity regions of the transport architectures, and show that the capacity region of OPS dominates that of OFS, and that the capacity region of OFS dominates that of OBS. We then apply these results to two important network topologies—bidirectional rings and Moore graphs—under uniform all-to-all traffic. Motivated by the incommensurate complexity cost of comparable transport architectures, we also investigate the dependence of the relative capacity performance of the switching architectures on the number of switch ports per fiber at core nodes. To meet energy-efficient performance demands, the computing industry has moved to parallel computer architectures, such as chip multiprocessors (CMPs), internally interconnected via networks-on-chip (NoC) to meet growing communication needs. Achieving scaling performance as core counts increase to the hundreds in future CMPs, however, will require high performance, yet energy-efficient interconnects. Silicon nanophotonics is a promising replacement for electronic on-chip interconnect due to its high bandwidth and low latency, however, prior techniques have required high static power for the laser and ring thermal tuning. We propose a novel nano-photonic NoC (PNoC) architecture, LumiNOC, optimized for high performance and power-efficiency. This paper makes three primary contributions: a novel, nanophotonic architecture which partitions the network into subnets for better efficiency; a purely photonic, in-band, distributed arbitration scheme; and a channel sharing arrangement utilizing the same waveguides and wavelengths for arbitration as data transmission. In a 64-node NoC under synthetic traffic, LumiNOC enjoys 50 lower latency at low loads and @math higher throughput per Watt on synthetic traffic, versus other reported PNoCs. LumiNOC reduces latencies @math versus an electrical 2-D mesh NoCs on the PARSEC shared-memory, multithreaded benchmark suite. Recent proposals have employed optical circuit switching (OCS) to reduce the cost of data center networks. However, the relatively slow switching times (10--100 ms) assumed by these approaches, and the accompanying latencies of their control planes, has limited its use to only the largest data center networks with highly aggregated and constrained workloads. As faster switch technologies become available, designing a control plane capable of supporting them becomes a key challenge. In this paper, we design and implement an OCS prototype capable of switching in 11.5 us, and we use this prototype to expose a set of challenges that arise when supporting switching at microsecond time scales. In response, we propose a microsecond-latency control plane based on a circuit scheduling approach we call Traffic Matrix Scheduling (TMS) that proactively communicates circuit assignments to communicating entities so that circuit bandwidth can be used efficiently. The basic building block of ever larger data centers has shifted from a rack to a modular container with hundreds or even thousands of servers. Delivering scalable bandwidth among such containers is a challenge. A number of recent efforts promise full bisection bandwidth between all servers, though with significant cost, complexity, and power consumption. We present Helios, a hybrid electrical optical switch architecture that can deliver significant reductions in the number of switching elements, cabling, cost, and power consumption relative to recently proposed data center network architectures. We explore architectural trade offs and challenges associated with realizing these benefits through the evaluation of a fully functional Helios prototype. Preface to the Second Edition. Preface to the First Edition. 1 Ray Optics. 2 Wave Optics. 3 Beam Optics. 4 Fourier Optics. 5 Electromagnetic Optics. 6 Ploarization Optics. 7 Photonic-Crystal Optics. 8 Guided-Wave Optics. 9 Fiber Optics. 10 Resonator Optics. 11 Statistical Optics. 12 Photon Optics. 13 Photon and Atoms. 14 Laser Amplifiers. 15 Lasers. 16 Semiconductor Optics. 17 Semiconductor Photon Sources. 18 Semiconductor Photon Detectors. 19 Acousto-Optics. 20 Electro-Optics. 21 Nonlinear Optics. 22 Ultrafast Optics. 23 Optical Interconnects and Switches. 24 Optical Fiber Communications. A Fourier Transform. B Linear Systems. C Modes of Linear Systems. Symbols and Units. Authors. Index. Optical networks-on-chip constitute a promising approach to tackle the power wall problem present in large-scale circuit design. In this paper, we propose Amon, an all-optical, mesh-like design based on passive microrings and wave-length division multiplexing, including the switch architecture and a contention-free routing algorithm. Amon provides power efficiency by decreasing the number of microrings, wavelengths and path lengths, which, in turn, reduces ring heater and laser power, and the required area. An analytic comparison of Amon against the state-of-the-art, low power, ring-based designs QuT and Spidergon shows that Amon significantly reduces network diameter and number of microrings. Our experimental results using DSENT show that Amon provides better scalability up to 256 nodes, significant power and area savings of up to 68 and 21 , respectively, while imposing only low wiring overhead and design complexity. Finally, Amon provides a tile-based structure which should facilitate VLSI integration. Routers built around a single-stage crossbar and a centralized scheduler do not scale, and (in practice) do not provide the throughput guarantees that network operators need to make efficient use of their expensive long-haul links. In this paper we consider how optics can be used to scale capacity and reduce power in a router. We start with the promising load-balanced switch architecture proposed by C-S. Chang. This approach eliminates the scheduler, is scalable, and guarantees 100 throughput for a broad class of traffic. But several problems need to be solved to make this architecture practical: (1) Packets can be mis-sequenced, (2) Pathological periodic traffic patterns can make throughput arbitrarily small, (3) The architecture requires a rapidly configuring switch fabric, and (4) It does not work when linecards are missing or have failed. In this paper we solve each problem in turn, and describe new architectures that include our solutions. We motivate our work by designing a 100Tb s packet-switched router arranged as 640 linecards, each operating at 160Gb s. We describe two different implementations based on technology available within the next three years. Chip multiprocessor (CMP) is becoming an attractive platform for applications seeking both high performance and high energy efficiency. In large-scale CMPs, the communication efficiency among cores is crucial for the overall system performance and energy consumption. In this article, we propose a ring-based optical network-on-chip, called SUOR, to fulfill the communication requirement of CMPs. SUOR effectively explores the distinctive properties of optical signals and photonic devices, and dynamically partitions each data channel into multiple sections. Each section can be utilized independently to boost performance as well as reduce energy consumption. We develop a set of distributed control protocols and algorithms for SUOR, but physically allocate the corresponding cluster agents close to each other to benefit from the strengths of optical interconnects at long distances as well as electrical interconnects at short distances. Simulation results show that SUOR outperforms the alternative optical networks under a wide range of traffic patterns. For example, compared with MWSR design, SUOR achieves 2.58× throughput as well as saves 64p energy consumption on average in a 256-core CMP. Compared with MWMR design, SUOR achieves 1.52× throughput and reduces 73p energy consumption on average. Communication systems with all-optical multicasting have better performance than those using optical electrical optical conversion. Multicast protocols assume that all nodes in the network can forward the signal from one input to several outputs. Since fabrication of an optical switch with splitting capability is an expensive technology, there are few switches that are multicast capable. The heuristics designed for all-optical networks have to handle this limitation. We introduce a shortest path based forest algorithm for all-optical networks. We propose a post-processing algorithm to reduce the number of wavelengths needed. The effect of this post-processing algorithm is also examined in a well-known approach. Input-Output buffered crossbars are popular building blocks for scalable high-speed switching because they require minimum speed-up of memory bandwidth. Scaling the design of crossbar switches to large capacities is limited by technology issues such as the reconfiguration of high-speed fabrics or power consumption. In addition, these crossbar architechtures typically schedule and transfer in terms of fixed size envelopes. Thus when they are used in the context of IP networks where packets are of variable size, the incoming packets need to be fragmented into fixed size envelopes. This fragmentation can lead to, possibly large [1], loss of bandwidth and even instability. This paper proposes a new method for switching variable sized packets over a crossbar switch that i) allows maximum utilization of switch bandwidth and avoids the fragmentation effect, and ii) allows designers to use much larger envelopes for transfering data over the fabric and thus minimizes the reconfiguration frequency of the fabric. Reducing the scheduling frequency makes implementation of complex schedulers practical and enables us to build ultra-fast switches incorporating optical technology that can provide bandwidth and delay guarantees. Hybrid circuit and packet switching for data center networking (DCN) has received considerable research attention recently. A hybrid-switched DCN employs a much faster circuit switch that is reconfigurable with a nontrivial cost, and a much slower packet switch that is reconfigurable with no cost, to interconnect its racks of servers. The research problem is, given a traffic demand matrix (between the racks), how to compute a good circuit switch configuration schedule so that the vast majority of the traffic demand is removed by the circuit switch, leaving a remaining demand matrix that contains only small elements for the packet switch to handle. In this paper, we propose two new hybrid switch scheduling algorithms under two different scheduling constraints. Our first algorithm, called 2-hop Eclipse, strikes a much better tradeoff between the resulting performance (of the hybrid switch) and the computational complexity (of the algorithm) than the state of the art solution Eclipse Eclipse++. Our second algorithm, called BFF (best first fit), is the first hybrid switching solution that exploits the potential partial reconfiguration capability of the circuit switch for performance gains. Hybrid analog digital multiple-input multiple-output architectures were recently proposed as an alternative for fully digital-precoding in millimeter wave wireless communication systems. This is motivated by the possible reduction in the number of RF chains and analog-to-digital converters. In these architectures, the analog processing network is usually based on variable phase shifters. In this paper, we propose hybrid architectures based on switching networks to reduce the complexity and the power consumption of the structures based on phase shifters. We define a power consumption model and use it to evaluate the energy efficiency of both structures. To estimate the complete MIMO channel, we propose an open-loop compressive channel estimation technique that is independent of the hardware used in the analog processing stage. We analyze the performance of the new estimation algorithm for hybrid architectures based on phase shifters and switches. Using the estimate, we develop two algorithms for the design of the hybrid combiner based on switches and analyze the achieved spectral efficiency. Finally, we study the tradeoffs between power consumption, hardware complexity, and spectral efficiency for hybrid architectures based on phase shifting networks and switching networks. Numerical results show that architectures based on switches obtain equal or better channel estimation performance to that obtained using phase shifters, while reducing hardware complexity and power consumption. For equal power consumption, all the hybrid architectures provide similar spectral efficiencies. Underwater wireless technologies demand to transmit at higher data rate for ocean exploration. Currently, large coverage is achieved by acoustic sensor networks with low data rate, high cost, high latency, high power consumption, and negative impact on marine mammals. Meanwhile, optical communication for underwater networks has the advantage of the higher data rate albeit for limited communication distances. Moreover, energy consumption is another major problem for underwater sensor networks, due to limited battery power and difficulty in replacing or recharging the battery of a sensor node. The ultimate solution to this problem is to add energy harvesting capability to the acoustic-optical sensor nodes. Localization of underwater sensor networks is of utmost importance because the data collected from underwater sensor nodes is useful only if the location of the nodes is known. Therefore, a novel localization technique for energy harvesting hybrid acoustic-optical underwater wireless sensor networks (AO-UWSNs) is proposed. AO-UWSN employs optical communication for higher data rate at a short transmission distance and employs acoustic communication for low data rate and long transmission distance. A hybrid received signal strength (RSS) based localization technique is proposed to localize the nodes in AO-UWSNs. The proposed technique combines the noisy RSS based measurements from acoustic communication and optical communication and estimates the final locations of acoustic-optical sensor nodes. A weighted multiple observations paradigm is proposed for hybrid estimated distances to suppress the noisy observations and give more importance to the accurate observations. Furthermore, the closed form solution for Cramer-Rao lower bound (CRLB) is derived for localization accuracy of the proposed technique.