Recently, it was shown that if multiplicative weights are assigned to the edges of a Tanner graph used in belief propagation decoding, it is possible to use deep learning techniques to find values for the weights which improve the error-correction performance of the decoder. Unfortunately, this approach requires many multiplications, which are generally expensive operations. In this paper, we suggest a more hardware-friendly approach in which offset min-sum decoding is augmented with learnable offset parameters. Our method uses no multiplications and has a parameter count less than half that of the multiplicative algorithm. This both speeds up training and provides a feasible path to hardware architectures. After describing our method, we compare the performance of the two neural decoding algorithms and show that our method achieves error-correction performance within 0.1 dB of the multiplicative approach and as much as 1 dB better than traditional belief propagation for the codes under consideration.
In @cite_11 , Zhang note that for irregular LDPC codes, OMS can incur a significant BER degradation compared to SPA decoding. To fight this effect, they suggest having each CN of degree @math use offset @math , rather than a global @math . The authors use a genetic algorithm to choose the offsets for each degree and, interestingly, find that this offsetting scheme not only matches the performance of SPA but can also lower the BER error floor exhibited by some codes.
@cite_11
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Two-dimensional (2-D) correction schemes are proposed to improve the performance of conventional min-sum (MS) decoding of irregular low density parity check codes. An iterative procedure based on parallel differential optimization is presented to obtain the optimal 2-D factors. Both density evolution analysis and simulation show that the proposed method provides a comparable performance as belief propagation (BP) decoding while requiring less complexity. Interestingly, the new method exhibits a lower error floor than that of BP decoding. With respect to conventional MS and 1-D normalized MS decodings, the 2-D normalized MS offers a better performance. The 2-D offset MS decoding exhibits a similar behavior. This paper introduces clockless stochastic decoding for high-throughput low-density parity-check (LDPC) decoders. Stochastic computation provides ultra-low-complexity hardware using simple logic gates. Clockless decoding eliminates global clocking, which eases the worst-case timing restrictions of synchronous stochastic decoders. The lack of synchronization might use outdated bits to update outputs in computation nodes; however, it does not significantly affect output probabilities. A timing model of clockless-computation behaviours under a 90 nm CMOS technology is used to simulate the BER performance of the proposed decoding scheme. Based on our models, the proposed decoding scheme significantly reduces error floors due to the "lock-up" problem and achieves superior BER performance compared with conventional synchronous stochastic decoders. The timing model includes metastability to verify the affect on BER performance. We present a new algorithm for joint detection and decoding of iteratively decodable codes transmitted over channels affected by a time-varying phase noise (PN) and a constant frequency offset. The proposed algorithm is obtained as an application of the sum-product algorithm to the factor graph representing the joint a posteriori distribution of the information symbols and the channel parameters given the channel output. The resulting algorithm employs the soft-output information on the coded symbols provided by the decoder and performs forward-backward recursions, taking into account the joint probability distribution of phase and frequency offset. We present simulation results for high-order coded modulation schemes based on low-density parity-check codes and serially concatenated convolutional codes, showing that, despite its low complexity, the algorithm is able to cope with a strong PN and a significant uncompensated frequency offset, thus avoiding the use of complicated data-aided frequency-estimation schemes operating on a known preamble. The robustness of the algorithm in the presence of a time-varying frequency offset is also discussed Several combinatorial properties of low-density parity-check (LDPC) codes, such as minimum distance, diameter, stopping number, girth and cycle-length distribution of the corresponding Tanner graph, are known to influence their performance under iterative decoding. Recently, a new class of combinatorial configurations, termed trapping sets, was shown to be of significant importance in determining the properties of LDPC codes in the error-floor region. Very little is known both about the existence parameters of trapping sets in structured LDPC codes and about possible techniques for reducing their negative influence on the code's performance. In this paper, we address both these problems from an algorithmic and combinatorial perspective. We first provide a numerical study of the trapping phenomena for the Margulis code, which exhibits a fairly high error-floor. Based on this analysis, conducted for two different implementations of iterative belief propagation, we propose a novel decoding process, termed averaged decoding. Averaged decoding provides for a significant reduction in the number of incorrectly decoded frames in the error-floor region of the Margulis code. Furthermore, based on the results of the algorithmic approach, we suggest a novel combinatorial characterizations of trapping sets in the class of LDPC codes based on finite geometries. Projective geometry LDPC codes are suspected to have extremely low error-floors, which is a property that we may attribute to the non-existence of certain small trapping sets in the code graph. A partially parallel low density parity check (LDPC) decoder compliant with the IEEE 802.3an standard for 100BASE-T Ethernet is presented. The design is optimized for minimum silicon area and is based on the layered offset-min-sum algorithm which speeds up the convergence of the message passing decoding algorithm. To avoid routing congestion the decoder architecture employs a novel communication scheme that reduces the critical number of global wires by 50 . The prototype LDPC decoder ASIC, fabricated in 90 nm CMOS, occupies only 5.35 mm2 and achieves a decoding throughput of 11.69 Gb s at 1.2 V with an energy efficiency of 133pJ bit. In this paper a physical-layer network coded two-way relay system applying Low-Density Parity-Check (LDPC) codes for error correction is considered, where two sources A and B desire to exchange information with each other by the help of a relay R. The critical process in such a system is the calculation of the network-coded transmit word at the relay on basis of the superimposed channel-coded words of the two sources. For this joint channel-decoding and network-encoding task a generalized Sum-Product Algorithm (SPA) is developed. This novel iterative decoding approach outperforms other recently proposed schemes as demonstrated by simulation results. Physical-layer network coding (PNC) is an attractive technique because it can significantly enhance the throughput of a wireless network with a relatively simple implementation, as compared with conventional network coding (NC) schemes. In this paper, the authors first investigate PNC with frequency shift keying (FSK) through the derivation of its bit-error rate (BER) and capacity, as well as the impact of imperfect synchronization to the overall performance. Based on the discussions on PNC with 2FSK, the authors then further expand the analysis to PNC with M -ary FSK (MFSK). Theoretical results indicate that the BER performance of PNC with 2FSK is a bit worse than that of PNC with 2PSK. As the constellation dimension M increases, the BER performance of PNC with M -ary FSK improves at the expense of bandwidth efficiency degradation. This paper proposes majority-based tracking forecast memories (MTFMs) for area efficient high throughput ASIC implementation of stochastic Low-Density Parity-Check (LDPC) decoders. The proposed method is applied for ASIC implementation of a fully parallel stochastic decoder that decodes the (2048, 1723) LDPC code from the IEEE 802.3an (10GBASE-T) standard. The decoder occupies a silicon core area of 6.38 mm2 in CMOS 90 nm technology, achieves a maximum clock frequency of 500 MHz, and provides a maximum core throughput of 61.3 Gb s. The decoder also has good decoding performance and error-floor behavior and provides a bit error rate (BER) of about 4 × 10-13 at Eb N0=5.15 dB. To the best of our knowledge, the implemented decoder is the most area efficient fully parallel soft -decision LDPC decoder reported in the literature. This work focuses on the decoding algorithm of the LDPC large block FEC codes for the packet erasure channel, also called AL-FEC (Application-Level Forward Error Correction). More specifically this work details the design and the performance of a hybrid decoding scheme, that starts with the Zyablov iterative decoding algorithm, a rapid but suboptimal algorithm in terms of erasure recovery capabilities, and, when required, continues with a Gaussian elimination algorithm. For practical reasons this work focuses on two LDPC codes for the erasure channel, namely LDPC-staircase and LDPC-triangle codes. Nevertheless the decoding scheme proposed can be used with other LDPC codes without any problem. The performance experiments carried out show that the erasure recovery capabilities of LDPC-triangle codes are now extremely close to that of an ideal code, even with small block sizes. This is all the more true with small code rates: whereas the Zyablov iterative decoding scheme becomes unusable as the code rate decreases, the Gaussian elimination makes the LDPC-triangle codes almost ideal. In all the tests, when carefully implemented, the LDPC-triangle codec featuring the proposed decoding scheme is fast, and in particular always significantly faster than the reference Reed-Solomon on GF( @math ) codec. The erasure recovery capabilities of LDPC-staircase codes are also significantly improved, even if they remain a little bit farther from an ideal code. Nevertheless, a great advantage is the fact that LDPC-staircase codes remain significantly faster than LDPC-triangle codes, which, for instance, enables their use with larger blocks. All these results make these codes extremely attractive for many situations and contradict the common belief that using Gaussian elimination is not usable because of a prohibitive processing load. Moreover the proposed approach offers an important flexibility in practice, and depending on the situation, one can either choose to favor erasure recovery capabilities or the processing time. This paper provides a technical overview of a newly added in-loop filtering technique, sample adaptive offset (SAO), in High Efficiency Video Coding (HEVC). The key idea of SAO is to reduce sample distortion by first classifying reconstructed samples into different categories, obtaining an offset for each category, and then adding the offset to each sample of the category. The offset of each category is properly calculated at the encoder and explicitly signaled to the decoder for reducing sample distortion effectively, while the classification of each sample is performed at both the encoder and the decoder for saving side information significantly. To achieve low latency of only one coding tree unit (CTU), a CTU-based syntax design is specified to adapt SAO parameters for each CTU. A CTU-based optimization algorithm can be used to derive SAO parameters of each CTU, and the SAO parameters of the CTU are inter leaved into the slice data. It is reported that SAO achieves on average 3.5 BD-rate reduction and up to 23.5 BD-rate reduction with less than 1 encoding time increase and about 2.5 decoding time increase under common test conditions of HEVC reference software version 8.0. Error-floors are the main reason for excluding LDPC codes from applications requiring very low bit-error rate. They are attributed to a particular structure in the codes' Tanner graphs, known as trapping sets, which traps the message-passing algorithms commonly used to decode LDPC codes, and prevents decoding from converging to the correct codeword. A technique is proposed to break trapping sets while decoding. Based on decoding results leading to a decoding failure, some bits are identified in a previous iteration and flipped and decoding is restarted. This backtracking may enable the decoder to get out of the trapped state. A semi-analytical method is also proposed to predict the error-floor after backtracking. Simulation results indicate the effectiveness of the proposed technique in lowering the error-floor. The technique, which has moderate complexity overhead, is applicable to any code without requiring a prior knowledge of the structure of its trapping sets. A key issue in physical-layer network coding (PNC) is how to deal with the asynchrony between signals transmitted by multiple transmitters. That is, symbols transmitted by different transmitters could arrive at the receiver with symbol misalignment as well as relative carrier-phase offset. A second important issue is how to integrate channel coding with PNC to achieve reliable communication. This paper investigates these two issues and makes the following contributions: 1) We propose and investigate a general framework for decoding at the receiver based on belief propagation (BP). The framework can effectively deal with symbol and phase asynchronies while incorporating channel coding at the same time. 2) For unchannel-coded PNC, we show that for BPSK and QPSK modulations, our BP method can significantly reduce the asynchrony penalties compared with prior methods. 3) For QPSK unchannel-coded PNC, with a half symbol offset between the transmitters, our BP method can drastically reduce the performance penalty due to phase asynchrony, from more than 6 dB to no more than 1 dB. 4) For channel-coded PNC, with our BP method, both symbol and phase asynchronies actually improve the system performance compared with the perfectly synchronous case. Furthermore, the performance spread due to different combinations of symbol and phase offsets between the transmitters in channel-coded PNC is only around 1 dB. The implication of 3) is that if we could control the symbol arrival times at the receiver, it would be advantageous to deliberately introduce a half symbol offset in unchannel-coded PNC. The implication of 4) is that when channel coding is used, symbol and phase asynchronies are not major performance concerns in PNC. This paper presents the first network-coded multiple access (NCMA) system prototype operated on high-order modulations up to 16-QAM. NCMA jointly exploits physical-layer network coding (PNC) and multiuser decoding (MUD) to boost throughput of multipacket reception systems. Direct generalization of the existing NCMA decoding algorithm, originally designed for BPSK, to high-order modulations, will lead to huge performance degradation. The throughput degradation is caused by the relative phase offset between received signals from different nodes. To circumvent the phase offset problem, this paper investigates an NCMA system with multiple receive antennas at the access point, referred to as MIMO-NCMA . We put forth a low-complexity symbol-level NCMA decoder that, together with MIMO, can substantially alleviate the performance degradation induced by relative phase offset. To demonstrate the feasibility and advantage of MIMO-NCMA for high-order modulations, we implemented our designs on software-defined radio. Our experimental results show that the throughput of QPSK MIMO-NCMA is double that of both BPSK NCMA and QPSK MUD at SNR = 10 dB. For higher signal-to-noise ratios at which 16-QAM can be supported, the throughput of MIMO-NCMA can be as high as 3.5 times that of BPSK NCMA. Overall, this paper provides an implementable framework for high-order modulated NCMA. We study the information reconciliation (IR) scheme for quantum key distribution (QKD) protocols. The IR for the QKD can be seen as the asymmetric Slepian-Wolf problem, which low-density parity-check (LDPC) codes can solve with efficient algorithms, i.e., the belief propagation. However, the LDPC codes are needed to be chosen properly from a collection of codes optimized for multiple key rates, which leads to complex decoder devices and performance degradation for unoptimized key rates. Therefore, it is desired that establish an IR scheme with a single LDPC code which supports multiple rates. To this end, in this paper, we propose an IR scheme with a rate-compatible non-binary LDPC code. Numerical results show the proposed scheme achieves IR efficiency comparable to the best know conventional IR scheme with lower decoding error rates. We address several implementation issues related to multi-user physical layer network coding, in which the symbol-synchronous collision of an arbitrary number of signals is decoded. In particular we study the effect of frequency and phase offsets, the imperfect symbol synchronization of the colliding signals and the estimation of frequency and phase offsets and amplitudes in the presence of more than two colliding signals. In this letter, we propose a new decoding algorithm based on a soft-input soft-output run-length limited (RLL) decoder in visible light communication (VLC) with on–off keying (OOK) modulation and Reed–Solomon (RS) codes. Conventional RLL codes are used for dimming adjustments in VLC; however, in our receiver model, the posterior probability matrix is produced by the new RLL decoder, and it can be matched as the input of the soft RS decoder to enhance the throughput in the VLC system. A significant advantage of our proposed method is that it leads to the enhancement of bit error rate (BER) and frame error rate (FER) performances without any change in the transmitter in VLC systems. The simulation results show that the majority of the BER and FER performances of our proposed method are better than those of hard-input hard-output RLL decoding and soft-input hard-output RLL decoding methods. Polar codes, as the first provable capacity-achieving error-correcting codes, have received much attention in recent years. However, the decoding performance of polar codes with traditional successive-cancellation (SC) algorithm cannot match that of the low-density parity-check or Turbo codes. Because SC list (SCL) decoding algorithm can significantly improve the error-correcting performance of polar codes, design of SCL decoders is important for polar codes to be deployed in practical applications. However, because the prior latency reduction approaches for SC decoders are not applicable for SCL decoders, these list decoders suffer from the long-latency bottleneck. In this paper, we propose a multibit-decision approach that can significantly reduce latency of SCL decoders. First, we present a reformulated SCL algorithm that can perform intermediate decoding of 2 b together. The proposed approach, referred as 2-bit reformulated SCL ( 2b-rSCL ) algorithm , can reduce the latency of SCL decoder from ( @math ) to ( @math ) clock cycles without any performance loss. Then, we extend the idea of 2-b-decision to general case, and propose a general decoding scheme that can perform intermediate decoding of any @math bits simultaneously. This general approach, referred as @math -bit reformulated SCL ( @math b-rSCL ) algorithm , can reduce the overall decoding latency to as short as @math cycles. Furthermore, on the basis of the proposed algorithms, very large-scale integration architectures for 2b-rSCL and 4b-rSCL decoders are synthesized. Compared with a prior SCL decoder, the proposed (1024, 512) 2b-rSCL and 4b-rSCL decoders can achieve 21 and 60 reduction in latency, 1.66 and 2.77 times increase in coded throughput with list size 2, and 2.11 and 3.23 times increase in coded throughput with list size 4, respectively. In iterative decoding of LDPC codes, trapping sets often lead to high error floors. In this work, we propose a two-stage iterative decoding to break trapping sets. Simulation results show that the error floor performance can be significantly improved with this decoding scheme. A coding scheme for the Gaussian wiretap channel based on low-density parity-check (LDPC) codes is presented. The messages are transmitted over punctured bits to hide data from eavesdroppers. It is shown by means of density evolution that the BER of an eavesdropper, who operates below the code's SNR threshold and has the ability to use a bitwise MAP decoder, increases to 0.5 within a few dB. It is shown how asymptotically optimized LDPC codes can be designed with differential evolution where the goal is to achieve high reliability between friendly parties and security against a passive eavesdropper while keeping the security gap as small as possible. The proposed coding scheme is also efficiently encodable in almost linear time. We study coding schemes for error correction in interactive communications. Such interactive coding schemes simulate any @math -round interactive protocol using @math rounds over an adversarial channel that corrupts up to @math transmissions. Important performance measures for a coding scheme are its maximum tolerable error rate @math , communication complexity @math , and computational complexity. We give the first coding scheme for the standard setting which performs optimally in all three measures: Our randomized non-adaptive coding scheme has a near-linear computational complexity and tolerates any error rate @math with a linear @math communication complexity. This improves over prior results which each performed well in two of these measures. We also give results for other settings of interest, namely, the first computationally and communication efficient schemes that tolerate @math adaptively, @math if only one party is required to decode, and @math if list decoding is allowed. These are the optimal tolerable error rates for the respective settings. These coding schemes also have near linear computational and communication complexity. These results are obtained via two techniques: We give a general black-box reduction which reduces unique decoding, in various settings, to list decoding. We also show how to boost the computational and communication efficiency of any list decoder to become near linear.