Recent studies highlighting the vulnerability of computer architecture to information leakage attacks have been a cause of significant concern. Among the various classes of microarchitectural attacks, cache timing channels are especially worrisome since they have the potential to compromise users' private data at high bit rates. Prior works have demonstrated the use of cache miss patterns to detect these attacks. We find that cache miss traces can be easily spoofed and thus they may not be able to identify smarter adversaries. In this work, we show that , which records the number of cache blocks owned by a specific process, can be leveraged as a stronger indicator for the presence of cache timing channels. We observe that the modulation of cache access latency in timing channels can be recognized through analyzing pairwise cache occupancy patterns. Our experimental results show that cache occupancy patterns cannot be easily obfuscated even by advanced adversaries that successfully evade cache miss-based detection.
@cite_9 propose a generic framework that detects cache covert timing channel using correlations between cache conflict misses. ReplayConfusion @cite_16 records and replays cache access traces from the trojan and spy, and detects cache timing attacks based on differences of cache misses under different cache slice hashing functions. @cite_3 have demonstrated novel use of hardware prefetchers to stop cache timing channels. These techniques require customized hardware for either fine-grained conflict miss tracking or cache design changes.
@cite_9 @cite_16 @cite_3
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Information security and data privacy have steadily grown into major concerns in computing, especially given the rapid transition into the digital age for all needs--from healthcare to national defense. Among the many forms of information leakage, covert timing channels can be dangerous primarily because they involve two parties intentionally colluding to exfiltrate sensitive data by subverting the underlying system security policy. The attackers establish an illegitimate communication channel between two processes and transmit information via resource timing modulation, which does not leave any physical activity trace for later forensic analysis. Recent studies have shown the vulnerability of many popular computing environments, such as cloud computing, to these covert timing channels. With the advancements in software confinement mechanisms, shared processor hardware structures will be natural targets for malicious attackers to exploit and implement their covert-timing-based channels. In this work, the authors present a microarchitecture-level framework that detects the possible presence of covert timing channels on shared hardware. Their experiments demonstrate their ability to successfully detect different types of covert timing channels on various hardware structures and communication patterns. Cache-based covert channel attacks use highly-tuned shared-cache conflict misses to pass information from a trojan to a spy process. Detecting such attacks is very challenging. State of the art detection mechanisms do not consider the general characteristics of such attacks and, instead, focus on specific communication protocols. As a result, they fail to detect attacks using different protocols and, hence, have limited coverage. In this paper, we make the following observation about these attacks: not only are the malicious accesses highly tuned to the mapping of addresses to the caches; they also follow a distinctive cadence as bits are being received. Changing the mapping of addresses to the caches substantially disrupts the conflict miss patterns, but retains the cadence. This is in contrast to benign programs. Based on this observation, we propose a novel, high-coverage approach to detect cache-based covert channel attacks. It is called ReplayConfusion, and is based on Record and deterministic Replay (RnR). After a program's execution is recorded, it is deterministically replayed using a different mapping of addresses to the caches. We then analyze the difference between the cache miss rate timelines of the two runs. If the difference function is both sizable and exhibits a periodic pattern, it indicates that there is an attack. This paper also introduces a new taxonomy of cache-based covert channel attacks, and shows that ReplayConfusion uncovers examples from all the categories. Finally, ReplayConfusion only needs simple hardware. Cache timing channels are a form of information leakage that operate through modulating cache access latencies and ultimately exfiltrate sensitive user information to adversaries. Among the many forms of timing channels, covert channels are particularly dangerous as they involve two insider processes (trojan and spy) colluding with each other to send out sensitive information, and are often difficult to detect or prevent. In this paper, we propose Prefetch-guard, an efficient and low-cost mitigation mechanism against cache-based timing channels. Prefetch-guard leverages hardware prefetchers to obfuscate the effect of timing modulation intentionally created by the trojan and spy. Our detection mechanism identifies the target cache sets that are being exploited for information leakage, and cache blocks are prefetched to fuzz the pattern of cache misses and hits created to construct timing channel between the trojan and the spy. With prefetch-guard, we observe that the cache timing channels suffer a 53 bit error rate which makes it very hard or impossible for the spy to decipher any useful information.