This paper presents the development of a new algorithm for Gaussian based color image enhancement system. The algorithm has been designed into architecture suitable for FPGA ASIC implementation. The color image enhancement is achieved by first convolving an original image with a Gaussian kernel since Gaussian distribution is a point spread function which smoothes the image. Further, logarithm-domain processing and gain offset corrections are employed in order to enhance and translate pixels into the display range of 0 to 255. The proposed algorithm not only provides better dynamic range compression and color rendition effect but also achieves color constancy in an image. The design exploits high degrees of pipelining and parallel processing to achieve real time performance. The design has been realized by RTL compliant Verilog coding and fits into a single FPGA with a gate count utilization of 321,804. The proposed method is implemented using Xilinx Virtex-II Pro XC2VP40-7FF1148 FPGA device and is capable of processing high resolution color motion pictures of sizes of up to 1600×1200 pixels at the real time video rate of 116 frames per second. This shows that the proposed design would work for not only still images but also for high resolution video sequences.
Hiroshi @cite_2 proposed an FPGA implementation of adaptive real-time video image enhancement based on variational model of the Retinex theory. The authors have claimed that the architectures developed in this scheme are efficient and can handle color picture of size @math pixels at the real time video rate of 60 frames per sec. The authors have not justified how high throughput has been achieved in spite of time consuming iterations to the tune of 30. Abdullah M. @cite_8 proposed a new approach for histogram equalization using FPGAs. Although efficient architectures were developed for histogram equalization, the restored images using this scheme are generally not satisfactory.
@cite_8 @cite_2
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This paper presents a novel design for real-time histogram equalization based on field programmable gate arrays (FPGAs). The design is implemented using non-conventional schemes to compute the histogram statistics and equalization in parallel. Counters are used in conjunction with a dedicated decoder specially designed for this purpose. The hardware is fast, simple, and flexible with reasonable development cost. The proposed system is implemented using Stratix II family chip type EP2S15F484C3. The maximum clock frequency can reach up to 250 MHz. In this case, the total time required to perform histogram equalization for an image of size 256 spl times 256 is 0.262 ms. In this paper, we present an FPGA implementation of real-time Retinex video image enhancement. Our implementation is based on the previously proposed architecture, which can handle the variational approach of the Retinex theory. In order to efficiently reduce the enormous computational cost required for image enhancement, processing layers and repeat counts of iterations are determined in accordance with software evaluation result. As for processing architecture, our pipelining architecture can handle high resolution pictures in real-time. Our FPGA implementation supports WUXGA (1,920×1,200) 60 fps as well as 1080p60.