In this paper, the NGDBF algorithm is implemented on a code that is deployed in the IEEE 802.3an Ethernet standard. The design employs a fully parallel architecture and operates in two-phases: start-up phase and decoding phase. The two phase operation keeps the high latency operations off-line, thereby reducing the decoding latency during the decoding phase. The design is bench-marked with other state-of-the-art designs on the same code that employ different algorithms and architectures. The results indicate that the NGDBF decoder has a better area efficiency and a better energy efficiency compared to other state-of-art decoders. When the design is operated in medium to high signal to noise ratios, the design is able to provide greater than the required minimum throughput of 10Gbps. The design consumes 0.81mm2 of area and has an energy efficiency of 1.7pJ bit, which are the lowest in the reported literature. The design also provides better error performance compared to other simplified decoder implementations and consumes lesser wire-length compared to a recently proposed design.
proposed a layered implementation of the offset MS algorithm @cite_10 . In this design, original parity check matrix of the @math GBASE-T code is split into six layers in which each layer has @math rows and @math columns. This enables the check node operation to be time multiplexed and the check node processor to be shared across layers. Since only @math check node processors are active at a time, only @math check node processors are needed to accomplish successful decoding. Another advantage of the layered implementation is that it provides faster convergence. This design was fabricated in a 90 CMOS and achieved a throughput close to the required specification. This design consumes more than a watt of power and is inferior to Zhang's offset MS decoder in terms of energy efficiency.
@cite_10
2170214997
A partially parallel low density parity check (LDPC) decoder compliant with the IEEE 802.3an standard for 100BASE-T Ethernet is presented. The design is optimized for minimum silicon area and is based on the layered offset-min-sum algorithm which speeds up the convergence of the message passing decoding algorithm. To avoid routing congestion the decoder architecture employs a novel communication scheme that reduces the critical number of global wires by 50 . The prototype LDPC decoder ASIC, fabricated in 90 nm CMOS, occupies only 5.35 mm2 and achieves a decoding throughput of 11.69 Gb s at 1.2 V with an energy efficiency of 133pJ bit.