In this paper, the ByoRISC (Build your own RISC) configurable application-specific instruction-set processor (ASIP) family is presented. ByoRISCs, as vendor-independent cores, provide extensive architectural parameters over a baseline processor, which can be customized by application-specific hardware extensions (ASHEs). Such extensions realize multi-input multi-output (MIMO) custom instructions with local state and load store accesses to the data memory. ByoRISCs incorporate a true multi-port register file, zero-overhead custom instruction decoding, and scalable data forwarding mechanisms. Given these design decisions, ByoRISCs provide a unique combination of features that allow their use as architectural testbeds and the seamless and rapid development of new high-performance ASIPs. The performance characteristics of ByoRISCs, implemented as vendor-independent cores, have been evaluated for both ASIC and FPGA implementations, and it is proved that they provide a viable solution in FPGA-based system-on-a-chip design. A case study of an image processing pipeline is also presented to highlight the process of utilizing a ByoRISC custom processor. A peak performance speedup of up to 8.5 @math can be observed, whereas an average performance speedup of 4.4 @math on Xilinx Virtex-4 targets is achieved. In addition, ByoRISC outperforms an experimental VLIW architecture named VEX even in its 16-wide configuration for a number of data-intensive application kernels.
A disciplined approach to CI generation for extensible processors is found in @cite_19 where the Xtensa processor http: www.tensilica.com is augmented with CIs that may combine VLIW, SIMD or fused (chained) operations. Although the Xtensa framework is highly automated and feature-rich, simultaneous generation of disjoint optimal MIMO CIs is not considered; instead the CI generation process is divided in distinct stages with different objectives. CI generation is also used for designing custom coprocessors (ARM OptimoDE @cite_27 ) or two-input one-output functional units (MIPS CorExtend @cite_2 ) with internal register storage @cite_16 .
@cite_19 @cite_27 @cite_16 @cite_2
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An application-specific instruction-set processor (ASIP) is ideally suited for embedded applications that have demanding performance, size, and power requirements that cannot be satisfied by a general purpose processor. ASIPs also have time-to-market and programmability advantages when compared to custom ASICs. The AutoTIE system simplifies the creation of ASIPs by automatically enhancing a base processor with application specific instruction set architecture (ISA) extensions, including instructions, operations, and register files. The new instructions, operations, and register files are automatically recognized and exploited by the entire software tool chain, including the C C++ compiler. Thus, taking advantage of the generated ASIP does not require any changes to the application or any assembly language coding. AutoTIE uses the C C++ compiler to analyze an application, and based on the analysis generates thousands, or even millions, of possible ISA extensions for the application. AutoTIE then uses performance and hardware estimation techniques to combine the ISA extensions into a large number of potential ASIPs, and for a range of hardware costs, chooses the ASIP that provides the maximum performance improvement. For example, for an application performing a radix-4 FFT, AutoTIE considers over 34,000 potential sets of ISA extensions. For hardware costs ranging from 7800 gates to 128,000 gates, AutoTIE combines these extensions to form 31 ASIPs, which provide performance improvements ranging from a factor of 1.12 to a factor of 11.3 compared to a general-purpose processor. Instruction set customization is an effective way to improve processor performance. Critical portions of applicationdata-flow graphs are collapsed for accelerated execution on specialized hardware. Collapsing dataflow subgraphs will compress the latency along critical paths and reduces the number of intermediate results stored in the register file. While custom instructions can be effective, the time and cost of designing a new processor for each application is immense. To overcome this roadblock, this paper proposes a flexible architectural framework to transparently integrate custom instructions into a general-purpose processor. Hardware accelerators are added to the processor to execute the collapsed subgraphs. A simple microarchitectural interface is provided to support a plug-and-play model for integrating a wide range of accelerators into a pre-designed and verified processor core. The accelerators are exploited using an approach of static identification and dynamic realization. The compiler is responsible for identifying profitable subgraphs, while the hardware handles discovery, mapping, and execution of compatible subgraphs. This paper presents the design of a plug-and-play transparent accelerator system and evaluates the cost performance implications of the design. Design tools for application specific instruction set processors (ASIPs) are an important discipline in systems-level design for wireless communications and other embedded application areas. Some ASIPs are still designed completely from scratch to meet extreme efficiency demands. However, there is also a trend, towards use of partially predefined, configurable RISC-like embedded processor cores that can be quickly tuned to given applications by means of instruction set extension (ISE) techniques. While the problem of optimized ISE synthesis has been studied, well from a theoretical perspective, there are still few approaches to an overall HW SW design flow for configurable cores that take all real-life constraints into account In this paper, we therefore present a novel procedure for automated ISE synthesis that accommodates both user-specified and processor-specific constraints in a flexible wary and that produces value optimized ISE solutions in-short time. Driven by an advanced application C code analysis profiling frontend, the ISE synthesis core algorithm is embedded into a complete, design flow, where the backend is formed by a state-of-the-art industrial tool for processor configuration, ISE IIW synthesis, and SW tool retargeting. The proposed, design flow, including ISE synthesis, is demonstrated, via several benchmarks for the MIPS CorExtend configurable RISC processor platform.