Hash functions like SHA-1 or MD5 are one of the most important cryptographic primitives, especially in the field of information integrity. Considering the fact that increasing methods have been proposed to break these hash algorithms, a competition for a new family of hash functions was held by the US National Institute of Standards and Technology. Keccak was the winner and selected to be the next generation of hash function standard, named SHA-3. We aim to implement and optimize Batch mode based Keccak algorithms on NVIDIA GPU platform. Our work consider the case of processing multiple hash tasks at once and implement the case on CPU and GPU respectively. Our experimental results show that GPU performance is significantly higher than CPU is the case of processing large batches of small hash tasks.
, @cite_2 implements a high speed hash function Keccak (SHA3-512) using the integrated development environment CUDA for GPU is proposed. In addition, the safety level of Keccak is also discussed at the point of Pre-Image Resistance especially. In order to implement a high speed hash function for password cracking, the special program is also developed for passwords up to 71 characters. Moreover, the throughput of 2-time hash is also evaluated in their work.
@cite_2
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In August 2015, SHA-3 Standard was published as the next generation of Secure Hashing Algorithm. Several optimized implementations of SHA-3 on a 24-core processor with software and hardware co-design are proposed in this paper. For software designs, a 4-core mapping scheme with shared-memory reduces the delay time by exploring the internal parallelism of the algorithm; the scheme of 5 cores with packet router improves flexibility; and 24-core mapping with circuit router fully explores the parallelism with higher energy efficiency. Hardware approaches: specific instructions and novel latch-based accelerators, are proposed to improve performance and energy efficiency. The three software mappings provide a speedup of 3.1, 3.6 and 19.6, respectively. Almost 2 times better performance and energy efficiency are obtained with three specific instructions. The implementation of 4 latch-based accelerators achieves a throughput of 81.9 Gbps at 850MHz with 3.7 pJ bit energy consumption per bit.