Data theft and tampering are serious concerns as attackers have aggressively begun to exploit weaknesses in current memory systems to advance their nefarious schemes. The storage industry is moving toward emerging non-volatile memories (NVM), including the spin-transfer torque magnetoresistive random access memory (STT-MRAM) and the phase change memory (PCM), owing to their high density and low power operation. The advent of novel memory technologies has led to new vulnerabilities including data sensitivity to magnetic field and temperature fluctuations and data persistence after power down. In this paper, we propose SMART: a Secure Magnetoelectric Antiferromagnet-Based Tamper-Proof memory, which leverages unique properties of antiferromagnetic materials and offers dense, on-chip non-volatile storage. SMART memory is not only resilient against data confidentiality attacks seeking to leak sensitive information but also protects data integrity and prevents Denial of Service (DoS) attacks on the memory. It is impervious to power side-channel attacks, which exploit asymmetric reads writes for 0 and 1 logic levels, and photonic side-channel attacks, which monitor photo-emission signatures from the chip backside. Further, the ultra-low power magnetoelectric switching coupled with the terahertz regime antiferromagnetic dynamics result in 4 orders lower energy-per-bit and 3 orders smaller latency for the SMART memory as compared to prior NVMs such as STT-MRAM and PCM.
Prior works on securing NVMs have focused mainly on memory encryption schemes, which are necessary to prevent attackers from exploiting data persistence in off-state. Chhabra proposed an incremental encryption scheme @cite_8 for NVMs where only inert memory pages, which have not been accessed for a while, are encrypted selectively. The working set of the memory (which is in current use) is in plaintext and, hence, incurs no encryption overhead on access. Such a selective encryption ensures that the majority of the main memory content (but not all) remains encrypted at all times, without overly compromising the performance. However, it requires dedicated hardware, inert page prediction, and scheduling for its implementation. A sneak path encryption scheme was demonstrated for memristor-based NVMs in @cite_37 , wherein sneak paths in the memristor crossbar array are exploited to apply encryption pulses to change the resistances of the memory cells, and hence, encrypt the stored data.
@cite_37 @cite_8
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Non-volatile memory devices such as phase change memories and memristors are promising alternatives to SRAM and DRAM main memories as they provide higher density and improved energy efficiency. However, non-volatile main memories (NVMM) introduce security vulnerabilities. Sensitive data such as passwords and keys residing in the NVMM will persist and can be probed after power down. We propose sneak-path encryption (SPE), for memristor-based NVMM. SPE exploits the physical parameters, multilevel cell (MLC) capability and the sneak paths in crossbar memories to encrypt the data stored in memristor-based NVMM. We investigate three attacks on NVMMs and show the resilience of SPE against them. We use a cycle accurate simulator to evaluate the security and performance impact of SPE based NVMM. SPE can secure the NVMM with a latency of 16 cycles and 1.5 performance overhead. Emerging technologies for building non-volatile main memory (NVMM) systems suffer from a security vulnerability where information lingers on long after the system is powered down, enabling an attacker with physical access to the system to extract sensitive information off the memory. The goal of this study is to find a solution for such a security vulnerability. We introduce i-NVMM, a data privacy protection scheme for NVMM, where the main memory is encrypted incrementally, i.e. different data in the main memory is encrypted at different times depending on whether the data is predicted to still be useful to the processor. The motivation behind incremental encryption is the observation that the working set of an application is much smaller than its resident set. By identifying the working set and encrypting remaining part of the resident set, i-NVMM can keep the majority of the main memory encrypted at all times without penalizing performance by much. Our experiments demonstrate promising results. i-NVMM keeps 78 of the main memory encrypted across SPEC2006 benchmarks, yet only incurs 3.7 execution time overhead, and has a negligible impact on the write endurance of NVMM, all achieved with a relatively simple hardware support in the memory module.