Side channels remain a challenge to information flow control and security in modern computing platforms. Resource partitioning techniques that minimise the number of shared resources among processes are often used to address this challenge. In this work, we focus on multi-core platforms and we demonstrate that even seemingly strong isolation techniques based on dedicated cores and memory can be circumvented through the use of thermal side channels. Specifically, we show that the processor core temperature can be used both as a side channel as well as a covert communication channel even when the system implements strong spatial and temporal partitioning. Our experiments on an x86-based platform demonstrate covert thermal channels that achieve up to 12.5 bps and a weak side channel that can detect processes executed on neighbouring cores. This work therefore shows a limitation in the isolation that can be achieved on existing multi-core systems.
More recently, it has been shown that it is possible to use temperature variations to induce processor faults @cite_21 which can in turn be also be used to extract sensitive information like RSA keys @cite_14 . Thermal information can also be used for coarse-grained data-exfiltration. For example, since temperature directly reflects the intensity of computation, it can be used to estimate the load or resource utilisation of a machine. This was illustrated by who computed the resource utilisation of servers in Amazon's EC2 although in a completely different context using the temperature data that is exposed to virtual machines @cite_67 .
@cite_14 @cite_67 @cite_21
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Due to a server's non-proportional energy consumption, it is highly desirable to increase server utilization in order to lower energy consumption and minimize environmental impact. To increase the utilization level, we must first understand the current utilization level in the state-of-the-art cloud environment. Towards that goal, we devise a new technique which can be used to measure the CPU utilization in a cloud. We sampled two different infrastructure cloud providers (IaaS or Infrastructure as a Service) on their server utilization. Surprisingly, our results show that there is a significant room for improvement. Variation in performance and power across manufactured parts and their operating conditions is an accepted reality in aggressive CMOS processes. This paper considers challenges and opportunities in identifying this variation and methods to combat it for improved computing systems. We introduce the notion of instruction-level vulnerability (ILV) to expose variation and its effects to the software stack for use in architectural compiler optimizations. To compute ILV, we quantify the effect of voltage and temperature variations on the performance and power of a 32-bit, RISC, in-order processor in 65nm TSMC technology at the level of individual instructions. Results show 3.4ns (68FO4) delay variation and 26.7x power variation among instructions, and across extreme corners. Our analysis shows that ILV is not uniform across the instruction set. In fact, ILV data partitions instructions into three equivalence classes. Based on this classification, we show how a low-overhead robustness enhancement techniques can be used to enhance performance by a factor of 1.1×-5.5×.