Calibration is an important step towards building reliable IoT systems. For example, accurate sensor reading requires ADC calibration, and power monitoring chips must be calibrated before being used for measuring the energy consumption of IoT devices. In this paper, we present ProCal, a low-cost, accurate, and scalable power calibration tool. ProCal is a programmable platform which provides dynamic voltage and current output for calibration. The basic idea is to use a digital potentiometer connected to a parallel resistor network controlled through digital switches. The resistance and output frequency of ProCal is controlled by a software communicating with the board through the SPI interface. Our design provides a simple synchronization mechanism which prevents the need for accurate time synchronization. We present mathematical modeling and validation of the tool by incorporating the concept of Fibonacci sequence. Our extensive experimental studies show that this tool can significantly improve measurement accuracy. For example, for ATMega2560, the ADC error reduces from 0.2 to 0.01 . ProCal not only costs less than 2 of the current commercial solutions, it is also highly accurate by being able to provide extensive range of current and voltage values.
Calibration can be performed multiple times after the device is fabricated. Therefore, it can be used to compensate for changes that occur over time and those influenced by environmental conditions. There are two types of calibrations: , and . Self-calibration performs the measurement-correction process within the device itself and does not require an external device. The calibration process that interrupts the ordinary data conversion process and is performed during device power up is referred to as foreground calibration or power up calibration @cite_25 @cite_9 @cite_3 @cite_23 . Although this technique results in significant error reduction, it cannot cope with temperature drift and other sources of inaccuracy such as sensor-to-ADC path loss. Alternatively, data converter can be calibrated while it is performing the regular conversion, and the result of conversion would not be affected by the calibration process. This is referred to as background calibration or runtime calibration @cite_19 @cite_1 . Background calibration encompasses temperature effect, which provides a higher absolute accuracy than foreground calibration.
@cite_9 @cite_1 @cite_3 @cite_19 @cite_23 @cite_25
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A self-calibrating analog-to-digital converter using binary weighted capacitors and resistor strings is described. Linearity errors are corrected by a simple digital algorithm. A folded cascode CMOS comparator resolves 30 spl mu V in 3 spl mu s. An experimental converter fabricated using a 6- spl mu m-gate CMOS process demonstrates 15-bit resolution and linearity at a 12-kHz sampling rate. A skip and fill algorithm is developed to digitally self-calibrate pipelined analog-to-digital converters (ADC's) in real time. The proposed digital calibration technique is applicable to capacitor-ratioed multiplying digital-to-analog converters (MDACs) commonly used in multistep or pipelined ADCs. This background calibration process can replace, in effect, a trimming procedure usually done in the factory with a hidden electronic calibration. Unlike other self-calibration techniques working in the foreground, the proposed technique is based on the concept of skipping conversion cycles randomly but filling in data later by nonlinear interpolation. This opens up the feasibility of digitally implementing calibration hardware and simplifying the task of self-calibrating multistep or pipelined ADCs. The proposed method improves the performance of the inherently fast ADCs by maintaining simple system architectures. To measure errors resulting from capacitor mismatch, of amp DC gain, offset, and switch feedthrough in real time, the calibration test signal is injected in place of the input signal using a split-reference injection technique. Ultimately, the missing signal within two-thirds of the Nyquist bandwidth is recovered with 16-b accuracy using a forty-fourth order polynomial interpolation, behaving essentially as an FIR filter,. A 15-b 1-Msample s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented. A radix 1.93, 1 b per stage design is employed. The digital self-calibration accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain, and capacitor nonlinearity contributing to DNL. A THD of -90 dB was measured with a 9.8756-kHz sine-wave input. The DNL was measured to be within +or-0.25 LSB at 15 b, and the INL was measured to be within +or-1.25 LSB at 15 b. The die area is 9.3 mm*8.3 mm and operates on +or-4-V power supply with 1.8-W power dissipation. The ADC is fabricated in an 11-V, 4-GHz, 2.4- mu m BiCMOS process. > A 100 MS s pipelined ADC is digitally calibrated by a slow SigmaDelta ADC using a least-mean-square (LMS) algorithm. Both linear and nonlinear memoryless residue gain errors of the pipeline stages are adaptively corrected. With a 411 kHz sinusoidal input, the peak SNDR improves from 28 dB to 59 dB and the SFDR improves from 29 dB to 68 dB. The complete 0.13 mu ADC SoC occupies a die size of 3.7 mm times 4.7 mm, and consumes a total power of 448 mW. A digital calibration method is presented for delta-sigma ADCs with focus on feedback DAC mismatch error correction. The DAC mismatch information is acquired, and then the nonlinearity is cancelled in the digital domain while the ADC operates. Unlike dynamic element matching which is commonly run between non-overlapping clock phases, the proposed method does not have the restriction and introduces no excess loop delay. The effectiveness of the proposed scheme was demonstrated with implementation of a third-order 15-level delta-sigma ADC. This study demonstrates for the first time the significant performance enhancement that calibration brings to folding-interpolating analog-to-digital converters (ADCs). The resulting 1.8-V ADC in 0.18- spl mu m CMOS achieves a conversion rate exceeding 1.6 GSample s, since the amplifier device sizes can be minimized to maximize speed without the restriction of device matching. At 1.6 GS s, the ADC achieves 0.15 LSB DNL, 0.35 LSB INL, 7.6 effective number of bits (ENOBs) at 100 MHz input, and 7.26 ENOB at Nyquist. At this speed, current consumption from a single 1.8-V supply is 245 mA analog, 185 mA digital, and 90 mA for the LVDS drivers. The ac performance is approximately 1.5 ENOBs higher compared to the same circuit with calibration disabled. The use of best design practices to optimize the ADC linearity prior to introducing calibration resulted in this small required dynamic calibration range, simplifying the calibrator circuitry and resulting in stable continuous performance over time without recalibration. Therefore, the fully on-chip calibration is performed automatically, just one time at power-up.