Criticality of Wafer Edge Inspection and Metrology Data to All Surface Defectivity Root Cause and Yield Analysis
As device sizes continue to increase on devices at 2x nm design rule and beyond and high wafer stress is worsening due to multi film stacking in the vertical memory process, we observe an increasing trend in edge yield issues worldwide. Wafer edge inspection and metrology become thus critical to drive root cause analysis for improving the yield during a new technology ramp. Nowadays, wafer defectivity correlation to edge is also key for production monitoring, but not without challenges due to the diverse sensitivity demands for the wafer front side, as compared to the wafer edge and back side. In this paper we are able to demonstrate that a cluster inspection platform with the proper balance of sensitivity and throughput is a key enabler for production monitoring. The study required high resolution imaging of the wafer front side, accurate metrology and defect binning capability at the wafer edge, and unique capability to isolate issues that matter in the wafer backside all in a single inspection cluster tool platform. This setup allows for faster time to decisions and eliminates the need to rely on other sources of inspection data. We present several examples of defectivity correlation between the wafer edge and both front and back side, with scanning electron microscope (SEM) examples showing same defect types captured. The root cause for edge defectivity is very often found to be in the crossover of edge bead removal (EBR) lines from successive steps. High quality and accurate EBR metrology is thus essential on many process steps including on backend layers where many EBR lines are found and need to be distinguished. Likewise, anomalies in metrology data of the edge profile can also act as an important indicator of possible defectivity on the wafer. Keywords Wafer Edge, Inspection, Metrology, Defect correlation, Root cause analysis