Rapid SOC prototyping utilizing quilt packaging technology for modular functional IC partitioning
A microchip integration technology called Quilt Packaging (QP) enables rapid prototyping of complex SoCs and microwave/RF systems, as well as optical, power, and DSP applications. QP is a direct edge to edge chip level interconnect technology that can be implemented in a variety of materials and/or process technologies, and has been demonstrated in both planar and non planar 3D architectures. Quilt Packaging technology can be applied to create a "Lego like" design kit for ultra fast prototyping and proof ofconcept chip level system verification. Partitioning subcomponents into small, inexpensive "chiplets" can allow for much faster design turns and greatly reduced first pass prototype verification. In addition, QP enables low loss, high throughput chip to chip I/O interconnects while reducing size, weight, and power requirements, lessening the burden of design trade offs for hardware system designers developing the next generation of microelectronic systems.
2016 International Symposium on Rapid System Prototyping (RSP)