Modeling and Optimization of Memristor and STT RAM Based Memory for Low Power Applications
Conventional charge based memory usage in low power applications is facing major challenges. Some of these challenges are leakage current for static random access memory (SRAM) and dynamic random access memory (DRAM) additional refresh operation for DRAM, and high programming voltage for Flash. In this paper, two emerging resistive random access memory (ReRAM) technologies are investigated, memristor and spin transfer torque (STT) RAM, as potential universal memory candidates to replace traditional ones. Both of these nonvolatile memories support zero leakage and low voltage operation during read access, which makes them ideal for devices with long sleep time. To date, high write energy for both memristor and STT RAM is one of the major inhibitors for adopting the technologies. The primary contribution of this paper is centered on addressing the high write energy issue by trading off retention time with noise margin. In doing so, the memristor and STT RAM power has been compared with the traditional six transistor SRAM based memory power and potential application in wireless sensor nodes is explored. This paper uses 45 nm foundry process technology data for SRAM and physics based mathematical models derived from real devices for memristor and STT RAM. The simulations are conducted using MATLAB and the results show a potential power savings of 87% and 77% when using memristor and STT RAM, respectively, at 1% duty cycle.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems