18.2 A 1.2V 20nm 307GB/s HBM DRAM with at speed wafer level I/O test scheme and adaptive refresh considering temperature distribution
Demand for higher bandwidth DRAM continues to increase, especially in high performance computing and graphics applications. However, conventional DRAM devices such as DDR4 DIMM and GDDR5 cannot satisfy these needs since they are bandwidth limited to less than 30GB/s. Also, if multiple GDDR DRAMs are used simultaneously for higher bandwidth, then high power consumption and routing congestion on PCBs become a big concern. In order to overcome these limitations, the high bandwidth memory (HBM) DRAM was recently introduced[1] HBM DRAM uses TSV and interposer technologies enabling multiple chip stacks and wide I/Os between the processor and memory: providing high capacity, low power and high bandwidth. This paper proposes the 2nd generation HBM to double the bandwidth from 128GB/s to more than 256GB/s and support pseudo channel mode and 8H stacks [2] In the pseudo channel mode, a legacy channel is divided into two pseudo channels and the two pseudo channels share the command address pins. Thus, one HBM has 16 pseudo channels instead of 8 legacy channels. To support various stack configurations including 8H stacks, a new architecture is adopted for flexible density ranging from 16Gb to 64Gb maintaining the same bandwidth. Finally, the bandwidth increase requires an active thermal solution to manage hotspots that develop from highly concentrated power consumption; we propose an adaptive refresh considering temperature distribution (ART) scheme as a solution.
2016 IEEE International Solid State Circuits Conference (ISSCC)