Pinatubo: A processing in memory architecture for bulk bitwise operations in emerging non volatile memories
Processing in memory (PIM) provides high bandwidth, massive parallelism, and high energy efficiency by implementing computations in main memory, therefore eliminating the overhead of data movement between CPU and memory. While most of the recent work focused on PIM in DRAM memory with 3D die stacking technology, we propose to leverage the unique features of emerging non volatile memory (NVM) such as resistance based storage and current sensing, to enable efficient PIM design in NVM. We propose Pinatubo1, a Processing In Non volatile memory ArchiTecture for bUlk Bitwise Operations. Instead of integrating complex logic inside the cost sensitive memory, Pinatubo redesigns the read circuitry so that it can compute the bitwise logic of two or more memory rows very efficiently, and support one step multi row operations. The experimental results on data intensive graph processing and database applications show that Pinatubo achieves a ~500 x speedup, ~28000x energy saving on bitwise operations, and 1.12x overall speedup, 1.11x overall energy saving over the conventional processor.
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)