Design of flip flops with clock gating and pull up control scheme for power constrained and speed insensitive applications
In this study, a novel power efficient implicit pulsed triggered flip flop with embedded clock gating and pull up control scheme (IPFF CGPC) is proposed. By applying an XOR based clock gating scheme in the pulse generating stage, which conditionally disables the inverter chain when the input keeps unchanged, IPFF CGPC is able to gain low power efficiency by eliminating redundant transitions of internal nodes. Meanwhile, a pull up control scheme is applied to enhance the discharging path and save short circuit power when D makes '0' '1' transition. To further improve the robustness of the proposed design, the XOR based comparator in the clock gating scheme is replaced by a transmission gate based comparator, which results in an enhanced version (IPFF ECGPC) Based on the SMIC 65 nm technology, extensive post layout simulation results show that IPFF CGPC exhibits excellent power characteristic with a reduction of 32.06 85.89% against its rival designs at 10% data switching activity. Due to its power efficiency, its power delay product (PDP) gains an improvement of up to 73.94% in the same condition. Moreover, IPFF ECGPC also enjoys outstanding total power and PDP efficiency at 10% data switching activity. Therefore, the proposed designs are suitable for power constrained applications in very large scale integration designs which are speed insensitive.
IET Comput. Digit. Tech.