Rigel: flexible multi rate image processing hardware
Image processing algorithms implemented using custom hardware or FPGAs of can be orders of magnitude more energy efficient and performant than software. Unfortunately, converting an algorithm by hand to a hardware description language suitable for compilation on these platforms is frequently too time consuming to be practical. Recent work on hardware synthesis of high level image processing languages demonstrated that a single rate pipeline of stencil kernels can be synthesized into hardware with provably minimal buffering. Unfortunately, few advanced image processing or vision algorithms fit into this highly restricted programming model. In this paper, we present Rigel, which takes pipelines specified in our new multi rate architecture and lowers them to FPGA implementations. Our flexible multi rate architecture supports pyramid image processing, sparse computations, and space time implementation tradeoffs. We demonstrate depth from stereo, Lucas Kanade, the SIFT descriptor, and a Gaussian pyramid running on two FPGA boards. Our system can synthesize hardware for FPGAs with up to 436 Megapixels/second throughput, and up to 297x faster runtime than a tablet class ARM CPU.
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