DW AES: A Domain Wall Nanowire Based AES for High Throughput and Energy Efficient Data Encryption in Non Volatile Memory
Big data storage poses significant challenges to anonymization of sensitive information against data sniffing. Not only will the encryption bandwidth be limited by the I/O traffic, the transfer of data between the processor and the memory will also expose the input output mapping of intermediate computations on I/O channels that are susceptible to semi invasive and non invasive attacks. Limited by the simplistic cell level logic, existing logic in memory computing architectures are incapable of performing the complete encryption process within the memory at reasonable throughput and energy efficiency. In this paper, a block level in memory architecture for advanced encryption standard (AES) is proposed. The proposed technique, called DW AES, maps all AES operations directly to the domain wall nanowires. The entire encryption process can be completed within a homogeneous, high density, and standby power free non volatile spintronic based memory array without exposing the intermediate results to external I/O interface. Domain wall nanowire based pipelining and multi issue pipelining methods are also proposed to increase the throughput of the baseline DW AES with an insignificant area overhead and negligible difference on leakage power and energy consumption. The experimental results show that DW AES can reduce the leakage power and area by the orders of magnitude compared with existing CMOS ASIC accelerators. It has an energy efficiency of 22 pJ/b, which is 5x and 3x better than the CMOS ASIC and memristive CMOL based implementations, respectively. Under the same area budget, the proposed DW AES achieves 4.6x higher throughput than the latest CMOS ASIC AES with similar power consumption. The throughput improvement increases to 11x for pipelined DW AES at the expense of doubling the power consumption.
IEEE Transactions on Information Forensics and Security