Substrate Trace Modeling for Package Warpage Simulation
Accurately predicting warpage using finite element simulation helps accelerate decision making in the early product development phase. With the ongoing trend of thinning the overall thickness of the microelectronics package as well as its substrate, copper with high modulus and coefficient of thermal expansion becomes more prominent compared to the rest of the non metallic material. Package warpage simulation may need to consider the copper trace pattern. Due to the complexity of the copper trace, simulation with high fidelity can be extremely expensive. This paper examines the substrate copper structural features and their impact to the mechanical behaviors of real substrates. Finite element analysis simulations compared three copper trace modeling approaches at different packaging levels of bare substrate, bare die package, and overmold package. Warpage measurements of test vehicle packages using the exact copper trace patterns as simulations confirmed the analyses. A practical and efficient approach for package simulation is identified.
2016 IEEE 66th Electronic Components and Technology Conference (ECTC)