A new approach to compact semiconductor device modelling with Qucs Verilog A analogue module synthesis
Since the introduction of SPICE non linear controlled voltage and current sources, they have become a central feature in the interactive development of behavioural device models and circuit macromodels. The current generation of SPICE based open source general public license circuit simulators, including Qucs, Ngspice and Xyce(c) implements a range of mathematical operators and functions for modelling physical phenomena and system performance. The Qucs equation defined device is an extension of the SPICE style non linear B type controlled source which adds dynamic charge properties to behavioural sources, allowing for example, voltage and current dependent capacitance to be easily modelled. Following, the standardization of Verilog A, it has become a preferred hardware description language where analogue models are written in a netlist format combined with more general computer programming features for sequencing and controlling model operation. In traditional circuit simulation, the generation of a Verilog A model from a schematic, with embedded non linear behavioural sources, is not automatic but is normally undertaken manually. This paper introduces a new approach to the generation of Verilog A compact device models from Qucs circuit schematics using a purpose built analogue module synthesizer. To illustrate the properties and use of the Qucs Verilog A module synthesiser, the text includes a number of semiconductor device modelling examples and in some cases compares their simulation performance with conventional behavioural device models. Copyright (c) 2016 John Wiley Sons, Ltd.