A 1 GHz Bandwidth 12 bit SC DAC for 60 GHz Radio in 65 nm CMOS
The proliferation of portable communication devices combined with the relentless demand for higher data rates has spurred the development of wireless communication standards which can support wide signal bandwidths. Benefits of the complementary metal oxide semiconductor (CMOS) process such as high device speeds and low manufacturing cost have rendered it the technology of choice for implementing wideband wireless transceiver integrated circuits (ICs) This dissertation addresses the key challenges encountered in the design of wideband wireless transceiver ICs. It is divided into two parts. Part I describes the design of crucial circuit blocks such as a highly selective wideband radio frequency (RF) front end and an on chip test module which are typically found in wireless receivers. The design of high speed, capacitive DACs for wireless transmitters is included in Part II.The first work in Part I is the design and implementation of a wideband RF frontend in 65 nm CMOS. To achieve blocker rejection comparable to surface acousticwave (SAW) filters, the highly selective and tunable RF receiver utilizes impedance transformation filtering along with a two stage architecture. It is well known that the low noise amplifier (LNA) which forms the first front end stage largely decides the receiver performance in terms of noise figure (NF) and linearity (IIP3/P1dB) The proposed LNA uses double cross coupling technique to reduce NF while complementary derivative superposition (DS) and resistive feedback are employed to achieve high linearity. The resistive feedback also enhances input matching. In measurements, the front end achieves performance comparable to SAW filters with blocker rejection greater than 38 dB, NF 3.2 5.2 dB, out of band IIP3 +17 dBm and blocker P1dB +5 dBm over a frequency range of 0.5 3 GHz.The second work in Part I is the design of an RF amplitude detector for on chip test. As the complexity of RF ICs continues to grow, the task of testing and debugging them becomes increasingly challenging. The degradation in performance or the drift from the optimal operation points may cause systems to fail. To prevent this effect and ensure acceptable performance in the presence of process, voltage and temperature variations (PVT) test and calibration of the RF ICs become indispensable. A wideband, high dynamic range RF amplitude detector design aimed at on chip test is proposed. Gain boosting and sub ranging techniques are applied to the detection circuit to increase the gain over the full range of input amplitudes without compromising the input impedance. A technique suitable for on chip third/second order intercept point (IP3/IP2) test by embedded RF detectors is also introduced.Part II comprises the design and analysis of high speed switched capacitor (SC) DACs for 60 GHz radio transmitters. The digital to analog converter (DAC) is one of the fundamental building blocks of transmitters. SC DACs offer several advantages over the current steering DAC architecture. Specifically, lower capacitor mismatch helps the SC DAC to achieve higher linearity. The switches in the SC DAC are realized by MOS transistors in the triode region which substantially relaxes the voltage headroom requirement. Consequently, SC DACs can be implemented using lower supply voltages in advanced CMOS process nodes compared to their currentsteering counterparts. The first work in Part II analyzes the factors limiting the performance of capacitive pipeline DACs. It is shown that the DAC performance is limited mainly by the clock feed through and settling effects in the SC arrays while the impact of capacitor mismatch and kT/C noise are found to be negligible. Based on this analysis, the second work in Part II proposes the split segmented SC array DAC to overcome the clock feed through problem since this topology eliminates pipelined charge propagation. Implemented in 65 nm CMOS, the 12 bit SC DAC achieves a Spurious Free Dynamic Range (SFDR) greater than 44 dB within the input signal bandwidth (BW) of 1 GHz with on chip memory embedded for digital data generation. Power dissipation is 50 mW from 1.2 V supply. Similar performance is achieved with a lower supply voltage (0.9 V) which shows the scalability of the SC DAC for more advanced CMOS technologies. Furthermore, the proposed SC DAC satisfies the spectral mask of the IEEE 802.11ad WiGig standard with a second order reconstruction filter and hence it can be used for the 60 GHz radio baseband.