Hardware accelerator for analytics of sparse data
Rapid growth of Internet led to web applications that produce large unstructured sparse datasets (e.g. texts, ratings) Machine learning (ML) algorithms are the basis for many important analytics workloads that extract knowledge from these datasets. This paper characterizes such workloads on a high end server for real world datasets and shows that a set of sparse matrix operations dominates runtime. Further, they run inefficiently due to low compute per byte and challenging thread scaling behavior. As such, we propose a hardware accelerator to perform these operations with extreme efficiency. Simulations and RTL synthesis to 14nm ASIC demonstrate significant performance and performance/Watt improvements over conventional processors, with only a small area overhead.
2016 Design, Automation Test in Europe Conference Exhibition (DATE)