Approximate 32 bit floating point unit design with 53% power area product reduction
The floating point unit is one of the most common building block in any computing system and is used for a huge number of applications. By combining two state of the art techniques of imprecise hardware, namely Gate Level Pruning and Inexact Speculative Adder, and by introducing a novel Inexact Speculative Multiplier architecture, three different approximate FPUs and one reference IEEE 754 compliant FPU have been integrated in a 65 nm CMOS process within a low power multi core processor. Silicon measurements show up to 27% power, 36% area and 53 power area product savings compared to the IEEE 754 single precision FPU. Accuracy loss has been evaluated with a high dynamic range image tone mapping algorithm, resulting in small but non visible errors with image PSNR value of 90 dB.
ESSCIRC Conference 2016: 42nd European Solid State Circuits Conference