11.7 A load aware pre emphasis column driver with 27% settling time reduction in 18% panel load RC delay variation for 240Hz UHD flat panel displays
In this paper, we present a column driver with load aware pre emphasis driving (LPD) as in Fig. 11.7.2. The LPD scheme calibrates the K value to the panel load resistance and capacitance to minimize the increase in the settling time due to the column to column and panel to panel R<sub>L</sub>C<sub>L</sub> delay variation. In addition, the self K calibration reduces fabrication cost because no trimming of the K is required during fabrication. Before the column driver starts its data driving operation, a K calibrator embedded in every column searches the K corresponding to the panel load R<sub>L</sub> and C<sub>L</sub> of each column and adjusts the K of a pre emphasis voltage generator (PVG) The K calibration searches for the K value where the voltage buffer supplies a proper amount of charge for the voltage step (V<sub>REF2</sub> V<sub>REF1</sub> to the panel load capacitance C<sub>L</sub> during the preemphasis duration T<sub>PRE</sub> To measure the amount of charge on C<sub>L</sub> the data line is detached from the voltage buffer after T<sub>PRE</sub> (ph<sub>DRV</sub> L) so that the charges on the data line are redistributed. After enough time elapses, the nodes on the data line (v<sub>1,2,,N</sub> are stabilized to one voltage, which is compared to the target data voltage (V<sub>REF2</sub> When there is an error, the K calibrator adjusts the K value to make the data line voltage close to the target data voltage V<sub>2</sub> For more precise matching between the amount of the injected charge of the K calibration and a real driving, the data lines can be disconnected a few hundred nanoseconds after T<sub>PRE</sub> to reflect the charge leaked during the pre emphasized output v<sub>O</sub> slewing down to V<sub>REF2</sub>
2016 IEEE International Solid State Circuits Conference (ISSCC)