CrossOver: Clock domain crossing under virtual channel flow control
Technology scaling, process variations, and/or 3D integration make the design of fully synchronous Systems on Chip (SoC) a challenging task. Partitioning the SoC into Globally Asynchronous, Locally Synchronous (GALS) islands aka clock domains partially alleviates the difficulties in clock distribution. Such partitioning of the SoC is also necessary when supporting Dynamic Voltage and Frequency Scaling (DVFS) across parts of the system to minimize power consumption. The Network on Chip (NoC) is an inherently distributed architecture that is physically spread over the entire chip; thus, it should readily support communication across multiple asynchronous clock domains. In this paper, we generalize the fundamental properties of Virtual Channel (VC) flow control across asynchronous clock domains. A new set of flow control rules is presented, which lead to efficient and deadlock free communication, while still respecting the properties of traditional (synchronous) VC based flow control. The derived flow control policy, called CrossOver, opens up a new design space, which is quantitatively explored in this paper. The goal of this investigation is to identify the configuration that maximizes throughput with the least cost, in terms of buffering requirements.
2016 Design, Automation Test in Europe Conference Exhibition (DATE)