Scheduler for Inhomogeneous and Irregular CGRAs with Support for Complex Control Flow
Coarse Grained Reconfigurable Arrays (CGRA) are more area and energy efficient compared to FPGAs, if we consider applications that are dominated by arithmetical operations. Enabling the user to employ CGRAs requires tools to create suitable CGRA instances and to program them on a high abstraction level. In this contribution we briefly explain a CGRA architecture generator and we focus on the scheduler that programs the generated CGRAs. This scheduler is able to work on in homogeneous (concerning the operations in the processing elements) and irregular (concerning the connections between processing elements) compositions. Additionally, the scheduler is able to map complex control flow onto the CGRA, which means nested loops, even containing control flow in the loop body. This significantly increases the mappability of application kernels.
2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)