A high efficiency reconfigurable cryptographic processor
With the significant attention to information security, mobile terminals such as smartphone always be demand for integrating cryptographic processor. In this paper, a high efficiency reconfigurable cryptographic processor is presented. Integrating small amounts of computing units designed by reconfigurable technology and developing instruction level parallelism of different operations in a block and among multiple blocks, the proposed architecture can improve the performance of cryptographic algorithm under the condition of limited resources. The processor was simulated and synthesized in 65nm CMOS process. Experimental results show that the processor is small area and high throughput, and outperforms the state of the art processors in area efficiency.
2016 International Conference on Integrated Circuits and Microsystems (ICICM)