An Analytical Model for Optimum Off Chip Memory Bandwidth Partitioning in Multi core Architectures
Multi core architectures have recently become a mainstream computing platform. These architectures along with excellent compute power, also facilitates sharing of expensive resources such as the last level cache and off chip memory bandwidth between the cores. Such sharing has produced interesting contention related performance phenomena, in which system throughput, as well as individual thread performance is highly volatile, depending on the mix of applications that share the resources and on how the resources are partitioned between the applications. If the sharing of these resources is made optimal, then the performance volatility of individual threads running in different cores can be reduced and obviously the overall system performance can be increased. Thus partitioning of resources shared by multi core architectures such as cache and off chip pin bandwidth, is necessary to a great extent. Applying cache partition alone, definitely improves the system performance. The proposed simple yet powerful analytical model shares the off chip memory bandwidth in such a way that it have a progressive impact over the performance of the system. The optimal bandwidth sharing in proposed model is achieved by exploiting the advantage of token bucket algorithm. The memory controller is modified in such a way that apart from normal memory request queuing, it also implements a token bucket system which controls memory requests from every core. The results are calculated based on weighted speedup which is a factor for measuring throughput in multi core architectures.