Design of an area efficient partial sum architecture for polar decoders based on new matrix generator
This paper proposes an area efficient partial sum generator (PSG) architecture for polar decoder implementation. High throughput PSG designs mainly consist of an encoding matrix generator and a partial sum update circuit. The matrix generator conventionally is built by cascading a series of D flip flops and XOR gates. By decomposing the target matrix into the Kronecker product of smaller matrices, this paper proposes a new multi level matrix generator architecture built by interconnection of several matrix generators of small sizes and additional arrays of AND gates. The additional AND gates incurred by our new matrix generator can be integrated with those AND gates required in the partial sum update circuit when forming PSG such that only two extra AND gates are required for the proposed PSG based on two level matrix generator architecture. The required number of D flip flops and XOR gates of two level matrix generator is only about 50% of the conventional one. Considering the entire PSG module, the overall reduction ratio is still more than 16% The proposed PSG design can be applied for various kinds of successive cancellation polar decoder architectures.
2016 14th IEEE International New Circuits and Systems Conference (NEWCAS)