Joint Modulo Scheduling and $V_{\mathrm{ dd} Assignment for Loop Mapping on Dual $V_{\mathrm{ dd} CGRAs
Coarse grained reconfigurable architecture (CGRA) is becoming an increasingly attractive platform because of its high performance and power (or energy) efficiency. To reduce energy consumption, the dual Vdd technique has been employed in CGRAs, and the modulo scheduling technique is widely used to improve performance of applications. To achieve both high performance and energy efficiency simultaneously, this paper formulates the solution as a biobjective optimization problem of energy consumption and initiation interval of loop pipelines on CGRAs, and proposes a joint modulo scheduling and dual Vdd assignment approach. The experimental results show that the proposed approach can bring a significant energy reduction of 24.8% and kernel energy efficiency acceleration of 1.41x on average, while the performance is maintained.
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems