Synapse Calibration on the HICANN DLS Neuromorphic Chip
HICANN DLS is a novel neuromorphic Application Specific Integrated Circuit (ASIC) developed in Heidelberg within the scope of the Human Brain Project. It consists of 32 neurons and a total of 1024 synapses that mimic their biological counterpart by means of full custom analog electronic circuits. The synapses contain individual circuitry designed to implement Spike Timing Dependent Plasticity (STDP) a synaptic mechanism that is believed to play a vital role in learning and memory. Because of inherent transistor mismatch, the parameters describing STDP (time constants and amplitudes) vary across synapses. In order to counteract this mismatch, each synapse contains four calibration bits which are intended to compensate parameter variation. Within this thesis, the synaptic circuits tailored for STDP are described and their functionality quantified. In particular, it has been tested to which degree transistor mismatch can be counteracted. The combinatorial problem of assigning calibration settings to synapses in order to reduce the Mean Absolute Deviation (MAD) of the parameter values is described using Mixed Integer Linear Programming (MILP) Using this approach on the tested chip, it is possible to reduce the spread of parameters by a factor of 1.4 to 2.1.