A 0.52/1 V Fast Lock in ADPLL for Supporting Dynamic Voltage and Frequency Scaling
In energy efficient processing platforms, such as wearable sensors and implantable medical devices, dynamic voltage and frequency scaling allows optimizing the energy efficiency under various modes of operation. The clock generator used in these platforms should be capable of achieving a faster settling time and has a wider operating voltage range. In this brief, a fast lock in all digital phase locked loop (ADPLL) with two operation modes (0.52/1 V) is presented. The proposed ADPLL can quickly compute the desired digitally controlled oscillator control code with high accuracy. Therefore, the proposed ADPLL can achieve a fast setting time with frequency errors ;5% within four clock cycles. The proposed ADPLL is implemented using a standard performance 90 nm CMOS process. The output frequency of the ADPLL ranges from 60 to 600 MHz at 1 V, and from 30 to 120 MHz at 0.52 V. The power consumption of the proposed ADPLL is 0.92 mW at (1 V, 600 MHz) and 37 mW at (0.52 V, 120 MHz)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems