A 12 Bit 10 MS/s SAR ADC With High Linearity and Energy Efficient Switching
A 12 bit 10 MS/s SAR ADC with enhanced linearity and energy efficiency is presented in this paper. A novel switching scheme (COSS) is proposed to reduce the power consumption and the matching requirement for capacitors in SAR ADCs. The switching energy (including switching energy and reset energy) total capacitance and static performance (INL DNL) of the proposed scheme are reduced by 98.08% 75% and 75% respectively, compared with the conventional architecture. Based on analysis of the non linear errors caused by comparator input parasitic capacitance, an improved comparator with push pull pre amplifier and output offset storage (OOS) strategy is proposed to diminish non linearity in the input parasitic capacitance. The offset cancellation signal for the comparator can be generated by asynchronous timing automatically, without any extra clock. Additionally, an SFDR enhancement bootstrap switch is proposed to eliminate the distortion induced by parasitic capacitance and threshold voltage that results in insufficient precision for mediumspeed 12 bit ADCs. The proposed ADC was fabricated in a 0.18 mm 1P6M CMOS process, and the measured results show that the ADC achieves an SNDR of 66.9 dB and an SFDR of 75.8 dB with a 10 MS/s sampling rate and consumes 0.82 mW, resulting in a figure of merit (FOM) of 44.2 fJ/conversion step. The peak DNL error is +0.36/ 0.33 LSB, and the peak INL error is +0.55 LSB/ 0.6 LSB. The ADC core occupies an active area of only 630 mmx570 mm2.
IEEE Transactions on Circuits and Systems I: Regular Papers