High Performance and Dynamically Updatable Packet Classification Engine on FPGA
High performance and dynamically updatable hardware architectures for multi field packet classification have regained much interest in the research community. For example, software defined networking requires 15 fields of the packets to be checked against a predefined rule set. Many algorithmic solutions for packet classification have been studied over the past decade. FPGA based packet classification engines can achieve very high throughput; however, supporting dynamic updates is yet challenging. In this paper, we present a two dimensional pipelined architecture for packet classification on FPGA; this architecture achieves high throughput while supporting dynamic updates. In this architecture, modular Processing Elements (PEs) are arranged in a two dimensional array. Each PE accesses its designated memory locally, and supports prefix match and exact match efficiently. The entire array is both horizontally and vertically pipelined. We exploit striding, clustering, dual port memory, and power gating techniques to further improve the performance of our architecture. The total memory is proportional to the rule set size. Our architecture sustains high clock rate even if we scale up (1) the length of each packet header, or/and (2) the number of rules in the rule set. The performance of the entire architecture does not depend on rule set features such as the number of unique values in each field. The PEs are also self reconfigurable; they support dynamic updates of the rule set during run time with very little throughput degradation. Experimental results show that, for a 1 K 15 tuple rule set, a state of the art FPGA can sustain a throughput of 650 Million Packets Per Second (MPPS) with 1 million updates/second. Compared to TCAM, our architecture demonstrates at least four fold energy efficiency while achieving two fold throughput.
IEEE Transactions on Parallel and Distributed Systems