SystemC link: Parallel SystemC simulation using time decoupled segments
Virtual platforms have become essential tools in the design process of modern embedded systems. Their accessibility and early availability make them ideal tools for design space exploration and debugging of target specific software. However, due to increasing platform complexity and the need to simulate more and more processors simultaneously, performance of virtual platforms degrades rapidly. This work presents SystemC Link, a segment based parallel simulation framework for SystemC simulators. It achieves high simulation performance by using a parallel and time decoupled simulation approach. Furthermore, it offers a virtual sequential environment for each simulation segment. This enables use of legacy models by allowing operation on global state without risking race conditions during parallel simulation. The approach is evaluated in a variety of scenarios, including a contemporary multi core platform based on the OpenRISC architecture running Linux. For this benchmark, a 3.2x higher simulation performance was achieved with SystemC Link compared to standard SystemC on a regular workstation PC.
2016 Design, Automation Test in Europe Conference Exhibition (DATE)