Low Power FPGA Design Using Memoization Based Approximate Computing
Field programmable gate arrays (FPGAs) are increasingly used as the computing platform for fast and energy efficient execution of recognition, mining, and search applications. Approximate computing is one promising method for achieving energy efficiency. Compared with most prior works on approximate computing, which target approximate processors and arithmetic blocks, this paper presents an approximate computing methodology for FPGA based design. It studies memoization as a method for approximation on FPGA and analyzes different architectural and design parameters that should be considered. The proposed design flow leverages on high level synthesis to enable memoization based microarchitecture generation, thus also facilitating a C to register transfer level synthesis. When compared with the previous approaches of bit width truncation and approximate multipliers, memoization based approximate computation on FPGA achieves a significant dynamic power saving (around 20% with very small area overhead ;5% and better power to signal noise ratio values for the studied image processing benchmarks.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems