Enabling high performance heterogeneous TFET/CMOS logic with novel circuits using TFET unidirectionality and low VDD operation
Tunneling FETs (TFETs) offer better low VDD performance than CMOS but lack performance above 0.5V VDD due to low drive current and VDD dependent parasitic leakages. At low VDD, TFET's higher energy efficiency enables 2X parallel performance for power constrained systems. For applications less amenable to parallelization, newly proposed circuits improve energy/op, performance and area by not only using TFET's steep sub threshold swing, but also utilizing its asymmetric IDS VDS characteristic. Design synthesis with sub 5nm node TFETs, MOSFETs and interconnects is used to assess trade offs in industry logic blocks. In addition to a 44% energy reduction over CMOS circuits, novel TFET circuits improve dynamic energy by 32% and performance by 13% at logic cell level (4% and 10% respectively at synthesized logic block) Even with these benefits, single threaded CPUs require CMOS logic's high performance. In this case, heterogeneous TFET/CMOS logic with low overhead level shifters improves performance 50% while reducing energy 42% for non critical performance logic.
2016 IEEE Symposium on VLSI Technology