A Wideband RF Mixing DAC Achieving IMD 82 dBc Up to 1.9 GHz
This paper presents a highly linear wideband Mixing DAC architecture. A current steering DAC core and a mixer are co integrated at a unit current cell level. A 1 bit DAC output stage is cascoded by a 1 bit mixer to form the Mixing DAC current cell. An array of such current cells and a system front end construct the Mixing DAC. The system front end includes digital signal processing and data synchronization, global LO driver and sort and combine calibration hardware. To reach high linearity, various techniques are used: digital dither, self measurement and calibration of amplitude and timing errors, local advanced cascoding scheme, bleeding currents, segmentation and accurate scaling of the LSB binary current cells. The proposed approach is validated by a 65 nm CMOS test chip of a dual 16 bit 2 GS/s 4 GHz Mixing DAC with IMD 82 dBc up to 1.9 GHz and output noise lower than 165 dBm/Hz.
IEEE Journal of Solid State Circuits