Highly Linear mm Wave CMOS Power Amplifier
A Ka band highly linear power amplifier (PA) is implemented in 28 nm bulk CMOS technology. Using a deep class AB PA topology with appropriate harmonic control circuit, highly linear and efficient PAs are designed at millimeter wave band. This PA architecture provides a linear PA operation close to the saturated power. Also elaborated harmonic tuning and neutralization techniques are used to further improve the transistor gain and stability. A two stack PA is designed for higher gain and output power than a common source (CS) PA. Additionally, average power tracking (APT) is applied to further reduce the power consumption at a low power operation and, hence, extend battery life. Both the PAs are tested with two different signals at 28.5 GHz; they are fully loaded long term evolution (LTE) signal with 16 quadrature amplitude modulation (QAM) a 7.5 dB peakto average power ratio (PAPR) and a 20 MHz bandwidth (BW) and a wireless LAN (WLAN) signal with 64 QAM, a 10.8 dB PAPR, and an 80 MHz BW. The CS/two stack PAs achieve power added efficiency (PAE) of 27%/25% error vector magnitude (EVM) of 5.17%/3.19% and adjacent channel leakage ratio (ACLRE UTRA) of 33/ 33 dBc, respectively, with an average output power of 11/14.6 dBm for the LTE signal. For the WLAN signal, the CS/2 stack PAs achieve the PAE of 16.5%/17.3% and an EVM of 4.27%/4.21% respectively, at an average output power of 6.8/11 dBm.
IEEE Transactions on Microwave Theory and Techniques