18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution
A 9Gb/s/pin 8Gb GDDR5 DRAM is implemented using a 20nm CMOS process. To cover operation up to 9Gb/s, which is the highest data rate among implemented GDDR5 DRAMs [1] this work includes an NBTI monitor, a WCK clock receiver with equalizing and duty cycle correction modes, CML to CMOS converters with wide range operation, active resonant loads at the end of WCK lane, and an on chip de emphasis circuit at a 4 to 1 multiplexer output as shown in Fig. 18.1.1. In addition, extra power pads improve the power distribution and release the frequency limitation at the memory core.
2016 IEEE International Solid State Circuits Conference (ISSCC)