Novel graph processor architecture, prototype system, and results
Graph algorithms are increasingly used in applications that exploit large databases. However, conventional processor architectures are inadequate for handling the throughput and memory requirements of graph computation. Lincoln Laboratory's graph processor architecture represents a rethinking of parallel architectures for graph problems. Our processor utilizes innovations that include a sparse matrix based graph instruction set, a cacheless memory system, accelerator based architecture, a systolic sorter, high bandwidth multidimensional toroidal communication network, and randomized communications. A field programmable gate array (FPGA) prototype of the new graph processor has been developed with significant performance enhancement over conventional processors in graph computational throughput.
2016 IEEE High Performance Extreme Computing Conference (HPEC)