The Comparative Study to Enhance Board Level Reliability Performance of Wafer Level Package At 0.25 mm Pitch Using Micro-Ball Drop and Electroplated Solder Technology
In this study, the board level reliability of WLP at 0.25mm pitch has been evaluated by employing board level reliability test following JEDEC include thermal cycling, drop shock and cyclic 4-point bend tests to verify the performance of shrunk bump size. The WLP test vehicle has been designed with 4-layer stack up structure, 4.0 × 4.0 mm die size and 15 × 15 ball array. The shrunk bumps of test vehicles were formed by using micro-ball drop and electroplated lead free solder bumping process after UBM plating completed. The shrunk bump size in WLP at 0.25mm ball pitch will enhance the risk of board level solder joint fatigue due to lower standoff height and smaller diameter of solder joint (higher bump stress concentration). In this work, we also evaluated different 4-layer WLP stack up structures for key design parameters including polyimide, RDL and UBM layers to reduce solder joint stress and thus enhance BLR performance All the study legs passed drop test with the 1st fail >100 drops and passed 200K times cyclic bend test without any failure. The TCT performance of micro-ball drop bumped legs showed better results with 1st fail passed 500X cycles. The drop, bend test and TCT performance are improved by new bump stack-up designs.
Studying the Effect of Stackup Structure of Large Die Size Fan-In Wafer Level Package at 0.35 mm Pitch With Varying Ball Alloy to Enhance Board Level Reliability Performance
In this study a four-layer fan-in wafer level package (WLP) structure (two passivation layers, one redistribution metal layer (RDL) and one under bump metallurgy layer (UBM) with die size 8 × 8 mm2 and ball pitch 0.35 mm is used for board level reliability (BLR) evaluation. The solder joint stress during BLR tests are highly related to the structure and solder ball alloy used in WLP bumping process based on simulation input. In this work, we evaluated different WLP structures with different stackup thickness including passivation layers, RDL layer, UBM layer and different solder ball alloy to reduce solder joint stress and thus enhance BLR performance. Besides, the impact of different die thickness post wafer grinding process was also included. All the different WLP structures have been evaluated by employing board level reliability test following JEDEC include thermal cycling test, drop test and cyclic 4-point bend test. From this work, an improved fan-in WLP stackup structure was demonstrated to pass board level TCT 500 cycles (include both corner chain balls/non-corner chain balls), drop test 150 times and cyclic bend test 200,000 cycles without any failure for 8× 8 mm2 die size at 0.35 mm pitch with doped SAC405 alloy.
Interconnect reliability prediction for wafer level packages (WLP) for temperature cycle and drop load conditions
Interconnect reliability of wafer level packages (WLP) is one of the major concerns because of the direct connection of die to board without any substrate interposer. The dominant failure modes due to temperature cycling and drop include cracks in bulk solder, crack at pad to IMC interface, and RDL cracking at UBM interface. A number of factors affect this reliability; such as UBM/Pad size, bump density, bump depopulation, and die size and thickness. In addition, WLPs come in different flavors (UBM vs. No UBM,) which also have implications on interconnect reliability. With increasing die size, it is becoming critical to investigate this reliability very early in the product design cycle using simulations. Although simulations are very helpful in performing relative comparison to investigate design options, their utility can be further enhanced by developing life prediction models to determine if a certain design will meet customer reliability requirements for the end use application. This paper discusses a finite element modeling based approach to establish such a life prediction model. Failure data on various test vehicles were collected using board level temperature cycle and drop test methods. This data covered a large range of WLP designs including various die sizes, bump pitches, bump densities, UBM/Pad sizes, fab nodes, and WLP structures. Each of these data points were then simulated using a detailed 3-D finite element modeling approach to compute strain energy density (SED) per cycle for temperature cycle conditions. Similarly, drop tests were simulated to determine drop damage parameters (Stress, Strain, Strain energy density) at various interfaces and RDL trace. The models incorporate every detail of package geometry including die size, solder bump dimensions from measurement, detailed structure below and above solder bump such as back end of line (BEOL), polymer layers, redistribution layers (RDL), UBM, and copper pad. Material properties were also measured of test boards to improve model accuracy and published creep constitutive equations were used for simulating non-linear behavior of solder joints due to temperature cycling and drop loading conditions. The values of damage parameters determined from finite element modeling were then plotted against the mean life (50% failure rate) to establish the fatigue life prediction model. A power law curve fitting with a correlation coefficient of greater than 95% resulted in fatigue life exponent of approximately -1 for solder fatigue, which is consistent with previous life prediction models. Since the intent was to use the model to predict first failures and 5% failure rate, Weibull analysis and test database was used to determine ratios of lower limits of 5% life at 90% confidence to mean life. The combined use of highly accurate finite element modeling and statistical analysis of test database provides greater confidence in predicting reliability and thus a useful tool for assessing and optimizing design very early in the design phase.