Complementary GaAs SIS FET inverter using selective crystal regrowth technique by MBE
A first complementary GaAs semiconductor-insulator-semiconductor (SIS) FET inverter has been fabricated by constructing n-channel and p-channel GaAs SIS FET's on a single LEC GaAs substrate using MBE selective crystal regrowth technique. The fabricated inverter shows an inverter operation as a really low-power complementary inverter.
p-channel FET based on p/n double-quantum-well heterostructure
An experimental demonstration of a p-channel FET based on a heterostructure having vertically integrated p- and n-type quantum-well channels is discussed. The AlGaAs/GaAs heterostructure consists of a quantum well with an underlying p-region positioned above a second quantum well with an underlying n-region. The p-FET is fabricated with self-aligned p/sup +/ regions formed by zinc diffusion. Electrical characteristics for 1.5- mu m gate lengths are nearly ideal in appearance with a maximum I/sub d/ of 90 mA/mm, a g/sub m/ of 80 mS/mm, and a g/sub m//g/sub d/ ratio of 140 at 77 K. The results demonstrate the viability of such stratified structures for the development of complementary integrated circuits or other circuits requiring integration of multiple device types.<<ETX>>
IIIA-3 modulation-doped field-effect transistors and logic gates based on two-dimensional hole gas
tance of SDHT's are well known, there have been no reports < 1 input capacitance for practical short-gate devices. The me8.surements reported here evaluate the intrinsic delay paramett I T~ = Cg/g, in such devices under realistic bias conditions. Tk e use of drain bias is important, because theory predicts thi t source resistance will suppress the intrinsic gate capacitancm.', just as intrinsic  transconductance  is uppressed.  Since tl-12 gates are short, the data can be used to infer the fundament.:l transport  parameter of effective  saturated  drift  velocity. , \ particular issue of interest is whether the large increases j, transconductance associated with reduced spacer thickness are due to increased velocity. Capacitance measurements were made as a function of gal 2 bias on SDHT's of 250-pm gate width and 1-pm nominal gal e length, operating at T = 300 K. Devices in stripline packagc: E; were tested at frequencies of 400 KHz and 4 Mhz, with draj 3 biases of 0 and 1.4 V. After capacitance and transconductance measurements were completed, the gate length was determine'fi by scanning electron microscopy. The resulting delays, plo .. ted as TO versus Vg, show a broad minimum about 0.5 V aboIie threshold for Vd = 1.4 V. Data taken at Vd = 0 V confirm that the source resistance correction, which reduces g, by 40 pe:'cent, also reduces C' by the same factor. For SDHT's of 6( 8 ,