Serial-bus based trigger timing distribution system
We have developed a serial-bus based trigger timing distribution system to handle the trigger and related timing signals over more than one thousand newly developed pipeline data acquisition modules for the Belle detector at the KEKB storage ring and for the SuperKEKB upgrade. The main idea is the use of 10-bit serial-bus lines over an inexpensive, compact and widely available enhanced category-5 shielded twist pair (STP) copper cable. The serial-bus is operated at 42.33 MHz, resulting in a 508 Mbps serial data transfer over the STP cable up to a distance of 15 m. The entire system consists of only three types of modules. The system is highly scalable by cascading switch modules over multiple stages: we use 4 stages to handle up to 4096 readout modules. We have proved that the basic technology is suitable for such an application. A two-step integration procedure before the full replacement is planned to integrate the system into the running Belle data acquisition system.
Belle DAQ system upgrade at 2001
Abstract We renewed the data acquisition system for the Belle experiment. Previous data acquisition system, which has been used since December 1998, did not have level 2 trigger facility. To improve the data reduction factor and total throughput, we replaced event builder, online computer farm and the storage system. The event builder and online computer farm are unified into one system. This event building farm uses commodity hardware and newly appended level 2 trigger functionality. This data acquisition system started its operation since last autumn and is very stable. We took 36 fb −1 with new DAQ system, it had already overtaken 30 fb −1 that is total amount of previous DAQ system.
Developments of a new TDC LSI and a VME module
A new TDC LSI and a TDC VME module have been developed. The TDC LSI (called AMT-2) will be used in muon precision trackers of the ATLAS experiment. The AMT-2 chip has 24 input channels and 280 ps RMS resolution. It is processed in a 0.3 /spl mu/m CMOS technology. The TDC module (called AMT-VME) has 64 channels and has wide timing range (/spl sim/100 /spl mu/sec) with a 0.78 ns/bit timing resolution. The module also contains a DSP for controlling data acquisition and manipulating data. Acquired data are read out via VME bus through a dual port memory. Designs of the chip and the module are presented, and preliminary test result is shown.