Fault Clearing Overvoltages on Long Transformer Terminated Lines
The results of Transient Network Analyzer (TNA) studies evaluating the feasibility of low-side switching long transformer terminated lines is reported. It is shown that overvoltages following line dropping and fault clearing can severely stress surge arresters and circuit brtakers exceeding capabilities specified in ANSI standards. These overvoltages are often not carefully considered in design studies, since the available literature on low-side switching of EHV transmission lines primarily deals with energizing the line and transformer.1,2,3,4
Parametric behavior of the dynamic period overvoltage on power transmission systems
A physical understanding of the dynamic period response of transformer terminated transmission lines is developed using a simplified single phase lumped model and time domain analysis. The sensitivity of the response to various circuit parameters is predicted based on this analysis and then verified using numerical techniques. Results are extended to three phase systems through studies performed on an analog transmission system simulator. It is shown that a weak source is the major factor leading to the generation of a dynamic period overvoltage.
Chip scale packaging using chip-on-flex technology
An increasing number of electronic designers, fabricators and users see Chip Scale Packaging (CSP) as a way to obtain the benefits foreseen in multichip packaging and Chip-on-Board (COB) without the problems and limitations currently associated with each. The Chip-on-Flex (COF) multichip packaging technology has been demonstrated to be applicable to single chip packages that meet chip scale packaging goals. This paper looks at the Chip-on-Flex Chip Scale technology and addresses issues including the process, structure, assembly, yields and reliability.