A 7000-gate microprocessor on SOS&#8212;PULCE
An n-channel MOS LSI microprocessor integrating 20 000 transistors on a chip has been realized on a sapphire substrate utilizing the Coplanar-II process. It contains ALU, shifters, and 44 registers which are combined to three 16-bit buses. By utilizing three types of threshold voltage for load transistors, 28-percent reduction in power dissipation is achieved. The minimum cycle time is 200 ns. By using the Coplanar-II process, anomalous leakage currents due to parasitic transistors at the sides of island are suppressed. It is found that the silicon-on-sapphire (SOS) version operates 2.3 times faster than the bulk-silicon version, which is mainly explained by the parasitic capacitance ratio. Parallel-plate approximation in calculating a wiring capacitance results in an underestimate by a factor of 60 compared with taking the two-dimensional effect into account. It is verified that a) the observed yield of a very large SOS chip is higher than the value predicted from a randomly distributed defects model, and b) the yield-sensitive active area of an SOS is so small that it can compensate for the yield degradation due to the very large defects density on an SOS wafer.
High-performance low-power CMOS memories using silicon-on-sapphire technology
Complementary MOS silicon-on-sapphire inverters fabricated using silicon-gate technology and 5-/spl mu/m channel-length devices has achieved nanosecond propagation delays and picojoule dynamic power-x delay products. In addition to high switching speed and low dynamic power, inverters with low leakage currents and therefore low quiescent power have been obtained. Two complex CMOS/SOS memories that realize the performance attributes of the individual inverters have been fabricated. An aluminium-gate 256-bit fully decoded static random-access memory features a typical access time of 50 ns at 10 V with a power dissipation of 0.4 /spl mu/W/bit (quiescent) and 10 /spl mu/W/bit (dynamic). The access time at 5 V is typically 95 ns. A silicon-gate 256-bit dynamic shift register features operation at clock signals of 200 MHz at 10 V and 75 MHz at 5 V. The dynamic power dissipation at 50 MHz and 5 V is typically 90 /spl mu/W/bit.
Diffused diodes in silicon-on-sapphire
Abstract The forward and reverse I–V characteristics of diffused diodes made in silicon grown epitaxially on sapphire have been measured. Silicon of doping density 4 × 10 15 to 6 × 10 17 /cm 3 p -type and 2 × 10 15 to 10 18 /cm 3 n -type have been used in these experiments. The forward conduction current of all diodes tested varied as exp ( qv /> nkT ) with n ≈ 1.7. Minority carrier lifetimes of the order 10 −10 sec have been inferred from the I–V data. The reverse currents were somewhat larger than predicted on the basis of currents generated in the space charge region but were reproducible from diode to diode. The temperature dependence of the diode currents was measured from room temperature to 200°C and followed the theoretical prediction. The variation of minority carrier lifetime with film thickness was measured, and the lifetime was found to increase as the silicon became thicker. Diodes produced by diffusion through the silicon to the silicon-sapphire interface were found to have minority carrier lifetimes about an order of magnitude lower than diodes not diffused to the bottom interface.