A New CD Measurement Method Linked with the Electrical Properties of Devices
This paper describes a new measurement method of a CD-SEM with nanometer-level precision and good correlation with electrical characteristics for an actual device of ultra-large-scale integration (ULSI). With the decrease in feature size, the pattern to be measured tends to become a curved shape. In order to measure such a pattern within measurement precision on the order of 5 nm, two-dimensional measurement is effective. Here we report a new measurement algorithm featuring that the critical dimension is derived from the value of the area of a measurement pattern. We apply this measurement method to actual device of 64-Mbit DRAM and confirm the reproducibility of 3.6 nm for the gate linewidth measurement, and that of 5.6 nm for the hole diameter measurement. Furthermore, we verify that the measurement values of the gate linewidth have a strong correlation with the threshold voltage and those of the hole diameter also have a strong correlation with the contact resistance, respectively. key words: CD SEM, metrology, curved structure, electrical
A precise and automatic very large scale integrated circuit pattern linewidth measurement method using a scanning electron microscope
This paper deals with an automatic linewidth measurement method of photoresist pattern linewidths with high accuracy, which we call ‘‘the linear regression method.’’ In the linear regression method, the secondary electron intensity profile at the photoresist pattern edge is approximated by two lines. One is the average line of the secondary electron intensity profile on the substrate and another is the slope line corresponding to the slope of the photoresist edge. The cross point of the two lines is defined as the pattern edge. The linewidths obtained by this method agree with the linewidths obtained by the cross sectional SEM images which are defined as true values, within 0.009 μm for various photoresist slope angles and within 0.002 μm for variation of the underlying materials. A practical pattern linewidth measuring apparatus which employs a high speed measurement time of 2.34 s is also described.
In-Process Linewidth Measurement Of Polysilicon Gates Using A Scanning Electron Microscope
SEM measurement of uncoated samples is not as easy as the salesmen would like us to believe! Despite the relatively "simple" sample, optimizing for reproducible submicron linewidth measurements of polysilicon gates was not trivial. Beam energy was shown to control both the signal-to-noise and the slope of the measurement signal, while beam exposure time was found to cause systematic linewidth changes. Optimized measurements utilized a 2.3 kV beam energy, controlled beam exposure times, and a 60% threshold level. No damage was measured on MOS devices exposed at 2.3 kV, at least when such measurements were followed by the anneals typical for MOS process flows.