Fabrication of Polycrystalline Ferroelectric Gate FET Memory with an Intermediate Electrode
We fabricated a new ferroelectric gate field-effect transistor memory (F-FET) with an intermediate electrode inserted between the ferroelectric capacitor (Cf) and the metal-oxide-semiconductor field-effect transistor (MOSFET) for writing data. The structure was a RuO2 top electrode/polycrystalline ferroelectric Pb(Zr0.52Ti0.48)O3 (PZT)/(Pt/RuO2) intermediate electrode/SiO2/Si substrate. The basic operation of the new memory was confirmed by a discrete circuit that the Cf was connected serially with the MOSFET. For data writing, two positive or negative square pulses applied between the top electrode and the intermediate electrode induced the positive (Pr+) and the negative (Pr-) remanent polarizations, respectively, for coding memory states. For data reading, an unipolar square pulse train was applied between the top electrode and the source of the MOSFET, and the drain of the MOSFET was biased by a DC voltage. When the memory state corresponded to the Pr+ or the P-, the drain current (ID) was small or large, respectively. In this study, we used a polycrystalline PZT film to deal with the difficult problems of an epitaxial PZT film such as complicated techniques and high cost of products for commercialization goal.
Retention and Read Endurance Characteristics of a Ferroelectric Gate Field Effect Transistor Memory with an Intermediate Electrode
Fundamental characteristics such as retention and read endurance of a ferroelectric gate field effect transistor (F-FET) memory with an intermediate electrode were investigated and reported. It was verified that the retention time of the new F-FET was longer than 98 h. By taking into account the leakage currents of both the ferroelectric capacitor Cf and the MOSFET used for data writing (W-FET), we found that, for positive reading voltage, the leakage currents of the ferroelectric capacitor and the W-FET are unfavorable for the Pr+ state and the Pr- state, respectively, in terms of read endurance. The overall read endurance is determined by a competition between the leakage currents of the Cf and the W-FET. The drain-connected configuration (DCC) was effective to minimize the unexpected influence of the leakage current of the W-FET.
Retention Characteristics of a Ferroelectric Memory Based on SrBi2(Ta, Nb)2O9
The polarization decay process in SrBi2(Ta, Nb)2O9 capacitors and retention characteristics of a 288-bit ferroelectric memory device fabricated from SrBi2(Ta, Nb)2O9 were studied. The remanent polarization decay at room temperature showed good linearity when plotted against logarithmic retention time over a wide range of 10-3–105 s. The distribution of times to failure of a 288-bit memory was fit to a model having a linear relationship between log (log t f) and 1/T for the period of infant failures and to the Arrhenius model having the form log t f vs 1/T for the period of random failures, where t f is the time to failure and T is the temperature. The activation energy was found to be 0.35 eV for infant failures and 1.15 eV for random failures. Possible causes for the difference in activation energies are discussed.