A planar transistor for the 32-nm node and beyond with an ultra-shallow junction fabricated using in-situ doped selective Si epitaxy
Shallower junctions must be formed to make transistors work for the 32-nm node. Many kinds of technologies, such as co-implantation, laser spike annealing (LSA), and flash lamp annealing, have been energetically studied to form ultra-shallow junctions. We focused on in-situ doped selective Si epitaxy, with which the short channel effect and the parasitic resistance can be made compatible. Using this epitaxy, ultra-shallow junctions (with effective junction depths (Xj,eff) under 9 nm@5E18) were formed, and 20-nm or shorter PMOS gate transistors were fabricated using the epitaxy
A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices
High performance 10 nm gate length CMOSFETs for hp22 nm node LOP is demonstrated for the first time. Key process, such as elevated source/drain extension combined with flash lamp annealing, fully silicided metal gate, novel SiON, and optimization method under high V/sub dd/ condition which taking care of SRAM performance is described. Record high transconductance of 1706 mS/mm and over 400 GHz f/sub i/ is achieved for nMOSFET. Bulk planar MOSFET structure can extend down to hp22 nm node.
Failure analysis for poor solderability of Au surface of PCB
Nonwetting is one of the common problems and is always rejected in electronic assemblies. ENIG pads of a PCBA exhibited nonwetting after lead-free reflow soldering. With the aid of stereomicroscope, SEM&EDS and XRF, a series of analysis was performed. And after visual inspection, surface and cross section analysis, thickness measurement and solderability test, it can be inferred that oxidation of plating surface was the main reason for nonwetting, and corrosion in Ni plating caused an adverse impact on solderalibity.