InGaAs-OI Substrate Fabrication on a 300 mm Wafer
In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs) wafer on insulator (InGaAs-OI) substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB) and Smart CutTM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 °C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM), scanning acoustic microscopy (SAM), and HR-XRD, to insure the crystalline quality of the post transferred layer.
The Phenomenology of Ion Implantation-Induced Blistering and Thin-Layer Splitting in Compound Semiconductors
Hydrogen and/or helium implantation-induced surface blistering and layer splitting in compound semiconductors such as InP, GaAs, GaN, AlN, and ZnO are discussed. The blistering phenomenon depends on many parameters such as the semiconductor material, ion fluence, ion energy, and implantation temperature. The optimum values of these parameters for compound semiconductors are presented. The blistering and splitting processes in silicon have been studied in detail, motivated by the fabrication of the widely used silicon-on-insulator wafers. Hence, a comparison of the blistering process in Si and compound semiconductors is also presented. This comparative study is technologically relevant since ion implantation-induced layer splitting combined with direct wafer bonding in principle allows the transfer of any type of semiconductor layer onto any foreign substrate of choice—the technique is known as the ion-cut or Smart-Cut™ method. For the aforementioned compound semiconductors, investigations regarding layer transfer using the ion-cut method are still in their infancy. We report feasibility studies of layer transfer by the ion-cut method for some of the most important and widely used compound semiconductors. The importance of characteristic values for successful wafer bonding such as wafer bow and surface flatness as well as roughness are discussed, and difficulties in achieving some of these values are pointed out.
Neutron Residual Stress Measurements on Rail Sections for Different Production Conditions
Rail sectioning with subsequent neutron diffraction experiments has been used to assess residual stresses in the rails. In this study we present the results of neutron stress measurements performed at the NIST Center for Neutron Research (NCNR) on rail sections from rails that were produced under various conditions. Specifically, these are air-cooled, air-cooled and roller-straightened, head-hardened and head-hardened and roller-straightened. More significantly, a head-hardened and roller-straightened rail was also studied after service to elucidate evolution of the service-induced residual stresses. In the latter case both a transverse-cut slice and the central region of a 0.53 m long piece were studied. Measurements on this piece are the first in which triaxial stresses have been determined for an intact rail. Neutron strain measurements with 3×3×3 mm3 spatial resolution were successfully employed for transversally cut slices to verify the difference in the stress state depending on the production process. Although examination of slices allows determination of only two-dimensional stresses in the plane of the slice, additional measurements on obliquely-cut slices, which were also carried out, and utilization of FEM gives the possibility of reconstructing the full triaxial stress distribution. Together, these approaches provide a better understanding of rail fabrication and the possibility of improving the durability and safety of rails in the future.Copyright © 2004 by ASME