Use of layout automation and design-based metrology for defect test mask design and verification
This paper studies the impact of shape and local environment (pattern layout) on the ability to detect defects on the reticle and the extent to which they affect the dimension of the printed image on the wafer. The authors have made extensive use of design information to perform a thorough evaluation. OPC software was used to generate mask data that was comparable to product mask data. Defects were placed on the post-OPC layout and OPC software was also used to simulate the dimension of the defective features as printed on the wafer. "Design Based Metrology" was used to create accurate metrology recipes to support wafer and mask metrology. Ultimately the procedures described in this paper allow a direct correlation to be made between reticle inspectability and the impact of the same defects on wafer CD. Data is presented for the case of the Contact Hole layer of a "65nm" Logic technology, though the methods described in the paper are applicable to all layers.
Mask Error Enhancement-Factor (MEEF) metrology using automated scripts in CATS
During the development of process generations with critical dimensions (CDs) around or even far below the wavelength used for printing, the wafer exposure step has become more and more complicated due to the non-linearities that occur within this sub-wavelength regime. These non-linearities give rise to a variety of optical-proximity effects (OPE) that must then be corrected for (optical-proximity correction, OPC). At the same time, the reticle errors are consuming a larger part of the total error budget on the wafer than we have seen in the past. As a consequence, detailed assessments of the reticle quality are gaining more importance and the average number of measurements for qualification of a high-end reticle is rapidly increasing. Within-die CD measurements are becoming common practice for such reticles. Quite often these measurement points are selected randomly. However, regions within the design with relatively low aerial-image contrast during imaging will be subject to the largest amplification of the mask-errors (highest Mask-Error-Enhancement Factor, MEEF). In this work a solution is presented in which measurement points with high MEEF-values can be selected from any given layout data. The method is embedded into the standard mask data preparation flow using CATS. Focus is on the automation necessary to generate set-up files for CD metrology tools, such as the Leica-MueTec M5k. The methodology has been applied in a CMOS volume production site.
Simulation-based defect printability analysis on attenuated phase-shifting masks
Simulated wafer images for Attenuated Phase Shift Mask (ATTPSM) features are performed by the Virtual Stepper System. The ATTPSM test reticles were prepared with programmed defects (hard defects and phase defects) on line/space patterns, contact hole patterns, and rectangle patterns for 150-nm design rules. Each defect area was inspected using KLA-Tencor's UV-HR365 and SLF27 inspection systems. Virtual Stepper simulations are compared with Aerial Image Measurement System (AIMSTM) simulation at best focus and at multiple defocus levels. In addition, simulation accuracy from different inspection images is compared.