High speed 15 ns 4 Mbit SRAM for space application
A high speed 15 ns 4 Mbit asynchronous SRAM, 500 /spl mu/A stand-by current, 300 krad total dose tolerant, has been developed for space applications, using a hardened 0.25 micron 4 layers metal full CMOS process. A hierarchical organisation per IO bits has been used to achieve high speed as well as low dynamic consumption, also suited for simple SEU (single event upset) induced error corrections, allowing mitigation with classical EDAC corrector. The product operates within 3 to 3.6 V, and ambient temperature from -55 to +125/spl deg/C. A high density die size of 68.3 mm/sup 2/ allows the use of a specific 36-pins dual in line flat pack package with a 500 mil width, making this product very competitive against SEU hardened chips. Successful silicon results are presented as well as radiation tests up to 300 krad.
A High Speed Wide Band SRAM Macro using Complementary Half-Swing Bus Architecture
A complementary half swing architecture is proposed for the high speed and low power bus operation. The bus is composed from a pair of lines. Each bus line within a pair utilizes the upper or lower half of the supply voltage exclusively. The architecture is applied to an embedded SRAM of the 0.5¿m CMOS ATM switch LSI. Simulation results indicate that it operates beyond 200MHz at the supply voltage of 3.0V. The worst case power dissipation is reduced by half and the peak current is reduced by 66%.
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