Ti/Ni(80%)Cr(20%) Thin-Film Resistor With a Nearly Zero Temperature Coefficient of Resistance for Integration in a Standard CMOS Process
A thin-film resistor out of Ni(80%)Cr(20%) for integration in a standard complementary metal-oxide-semiconductor process with a temperature coefficient of resistance (TCR) below 10 ppm/K was realized by applying a thin Ti layer underneath. The Ti-layer thickness and the temperature and duration of furnace annealing after deposition were optimized in different experiments. The combination of 5-nm Ti + 10-nm NiCr and a 30-min heat treatment at 350degC in a forming gas ambient was found to yield a sheet resistance of about 140 Omega/sq and a TCR of below 10 ppm/K. The long-term drift of the sheet resistance after 1000 h at 200degC was about 0.3%. A transmission electron microscopy analysis was conducted to investigate the structure of the film and a possible change during annealing. An Auger analysis was conducted for film surface analysis.
Design techniques for high-temperature analog and mixed-signal integrated circuits
Reliable high-temperature analog and mixed-signal CMOS circuits are required for several applications including aerospace, automotive control, oil field instrumentation, and pulp and paper digesters. In particular, in this work we focus on the design of key building blocks of a miniature sensor interface system that is intended to operate in a pulp and paper digester and collect and record sensory data such as pressure and temperature along its trajectory within the digester. The temperature inside the digester can be as high as 180 ◦C. Design considerations and techniques for implementing these building blocks both at componentand circuit-levels are presented. At the component level, techniques for designing monolithic resistors with a desired temperature coefficient (TC) are proposed, and an analysis on the effects of design parameters such as resistor length, width and the number of fingers on the TC of such multi-finger resistor structures is presented. Furthermore, since the foundry-provided transistor models are typically valid up to 125 ◦C, various NMOS and PMOS transistors with different sizes are implemented to study their behaviour at high temperature. Based on our observations, a suitable sizing for transistors is suggested for circuits operating up to 200 ◦C. At the circuit-level, several key building blocks such as bias circuits, voltage references and oscillators are designed and proof-of-concept prototypes are implemented in a standard 0.13 μm CMOS process. The operation of the circuits is experimentally validated over the temperature range of interest, namely, 25 to 200 ◦C .
Investigation of the segregation phenomenon in Ni-Cr layers with different compositions
Abstract Ni-Cr layers with different compositions were produced by sputtering and evaporation methods. The aim of the work was to investigate the effect of oxygen on the deposition of the layers. The layer compositions were investigated by Auger electron spectroscopy (AES) before and after carrying out different heat treatments. The results of AES, electrical measurements and electron diffraction investigations can be accounted for by the segregation of a nickel-rich metallic phase and a chromium-oxide-rich phase.