Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits
It is believed that the time-domain resolution of a digital signal edge transition is superior to the voltage resolution of an analog signal in advanced CMOS processes[1], [2]. The reasoning behind this is that operating voltage has been reducing, making the signal more vulnerable to noise power due to scaling. On the other hand, in time domain, scaling has resulted to increase in frequency and therefore design of faster circuits, while also contributing to reduction of jitter. However, this is a concept that has not yet been quantitatively examined. This paper aims at verifying the effectiveness of the time-domain circuits over voltage-domain circuits in terms of their dynamic range performances by simulations as well as by theoretical analysis, especially in the scaled nano-meter processes. It has been shown that for a given technology the time domain dynamic range is superior to the voltage domain dynamic range by a factor of (ωT /B)2 where ωT is the unity gain frequency and B is the bandwidth.
Delay-Line-Based Analog-to-Digital Converters
We will introduce a design of analog-to-digital converters (ADCs) based on digital delay lines. Instead of voltage comparators, they convert the input voltage into a digital code by delay lines and are mainly built on digital blocks. This makes it compatible with process scaling. Two structures are proposed, and tradeoffs in the design are discussed. The effects of jitter and mismatch are also studied. We will present two 4 bit, 1 GS/s prototypes in 0.13 mum and 65 nm CMOS processes, which show a small area (0.015 mm2) and small power consumption (<2.4 mW).
Signal folding in A/D converters
Signal folding appears in A/D converters (ADCs) in various ways. In this paper, the evolution of this technique is derived from the fundamentals of quantization to obtain systematic insights. We look upon folding as an automatic multiplexing of zero crossings, which simplifies hardware while preserving the high speed and low latency of a flash ADC. By appreciating similarities between the well-known pipeline ADCs, folding ADCs, and ripple through ADCs, this enables the circuit designer to more freely choose the best architecture to meet the specified performance goals.