Packaging technology by Liquid Mold-UnderFill (MUF) material for the advanced mobile devices
As one approach of advanced packaging technologies, high reliability Liquid Mold UnderFill (Liquid MUF) materials and unique process will be presented here. Liquid MUF materials have the features of high adhesion, low CTE and low modulus. It is possible to alleviate the stress of the solder of each device mounted in the package, and they have excellent reliability too. These materials are adjusted the workability depending on the application. Moreover, because of low viscosity, the Liquid MUF material could be mold-underfilled with relatively lower stress to large Flip Chip devices with small gap and narrow pitch compared to the conventional solid materials. As for the processes of the liquid materials, printing, dispensing and compression molding are applicable. In this paper, the printing process, especially vacuum printing encapsulation systems (VPES) and pressure curing systems, will be mainly discussed. In addition, module package structure that achieved by these material and process development will be also explained in detail.
New Encapsulation Process for the SIP (System in Package)
System-in-Package (SiP) is a promising concept of system integration. Different semiconductor technologies, integrated passives, and other components can be integrated into a single package, without compromising the performance of separate functional blocks. However, the increase of packaging density increases the complexity of structures. Therefore, new processes and materials are needed to achieve high reliable SiP module pkg. So in this test, we tried VPES (vacuum printing encapsulation system) as underfill and encapsulation process of SiP module. The size of SiP module package is 4.84(L) times 6.15(W) times 1.32(H) mm. It contains an IC chip and several passive components such as crystals, filters, register, capacitor, etc. IC chip size is 3.5 mm SQ, thickness 0.45 mm, and the standoff height is almost 0.06 mm. In this test we compared VPES and conventional underfill and molding process. During the VPES process we used pressure cure system to reduce the internal void size. SAT (scanning acoustic transmitter), 3D optical microscope, and shadow moire analysis were done. And reliability test such as MRT and T/C was performed.
New packaging of chip-on-board by unique printing method
A novel printing method which has been found to be successful in making the chip-on-board (COB) packaging for ICs has been developed. Using this technique, it has become possible to achieve less than mm height, uniform thickness, and all-in-one operation. This method is more economical than the transfer-molding method. In addition, the cost of packages is much reduced, and it is more suited to mass production. One-component epoxy-resin, called NPR-150, has been developed which is suitable for printing. Deformation of gold wires was not observed, and reliability test results showed excellent levels, comparable to the formal transfer-molding packaging.<<ETX>>