SOI pixel detector based on CMOS time-compression charge-injection
Concept and experimental results obtained from a pixel detector based on CMOS time-compression charge- injection-devices (TC-CID) with a huge internal photocurrent amplification (-104), fabricated in CMOS silicon-on-insulator (SOI) technology are presented. Here, the readout circuitry is fabricated on highly-doped, 200 nm thick SOI film, while the photogate (PG) detector is fabricated on higher-resistivity handle wafer. The latter, together with the 30 V biasing possibilities enhances the quantum efficiency, especially for irradiations with wavelengths in the near-infra-red (NIR) part of the spectra.
CHARGE-COUPLED DEVICES
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A low-voltage rail-to-rail CMOS V-I converter
This paper presents CMOS low-voltage rail to-rail voltage-to-current (V-I) converters which could be used as basic building blocks to construct low-voltage current-mode analog very large scale integration (VLSI) circuits. In the circuit, an n-type V-I converter cell is connected in parallel with its p-type counterpart to achieve common-mode rail to-rail operation. A linear differential relationship of the n-type V-I converter, or its p-type complement, is obtained using a new class-AB linearization technique. The constant transconductance value is obtained by manipulating the DC bias currents of n- and p-type V-I converter cells. The circuit can operate from rail to rail with a power supply of 3 V or less, depending on the VLSI technology and the DC bias current level.