A Full Factory Transient Simulation Model for the Analysis of Expected Performance in a Transition Period
Intel's Fab-18 is based in Israel, and has transitioned from producing 0.18-micron logic devices to producing 90 nM flash products. During this transition period, the factory has de-ramped in volume of logic while ramping-up flash. AutoSched AP software was utilized for the development of a transient simulation model of the Fab's behavior during this period. It is the first attempt, at Intel, to utilize a full factory simulation in order to analyze and support decisions that pertain to a transient period of parallel de-ramp and ramp-up of technologies. Unlike typical simulation models for the analysis of factory performance and behavior in steady-state, the transient model poses several modeling challenges and requires major adjustments in dealing with these challenges. In this paper, we discuss those aspects. The benefits and contribution of such a model to decision making and the improvement of factory performance are also presented
Integrating dynamic fab capacity and automation models for 300 mm semiconductor manufacturing
Semiconductor fabrication facilities (fabs) continue to expand in both complexity and volume. As a result, integrated models are required to determine even high level impacts to key success indicators. In order to gain insight into how the components of a factory impact performance metrics, Intel uses an integrated discrete event simulation modeling approach. Two models, one fab capacity and one automation model, are used. This paper discusses the methodology for building and integrating both models, and the results from using this method. Both the fab capacity and automation models have a variety of input parameters that are required to drive the simulation. In addition, each model produces output parameters, some of which are used as inputs to the other model. An iterative feedback technique eventually results in a convergence on the appropriate data to feed the fab capacity model, which enables Intel to determine the impact of automation on 300 mm wafer semiconductor manufacturing, and predict factory performance. Intel's approach provides the capability to use the models in stand-alone mode for specific fab-only or automation-only analyses, and also to take on any number of analyses via model communication. Intel continues to search for new applications for these merged models to answer strategic operational questions.
WIP evolution of a semiconductor factory after a bottleneck workcenter breakdown
In semiconductor fabrication facilities, an increase in work in progress (WIP) can be observed even weeks after the failure of the bottleneck workcenter. We develop a simple fab model that facilitates the study of this phenomenon. The simplified factory consists of a detailed model of the bottleneck workcenter and a delay unit that represents the rest of the factory. After passing the delay unit, the lots are fed back to the bottleneck to model the cyclic flow of lots of real wafer fabs. We study the behavior of this model for numerous scenarios, and it turns out that by means of the model, the WIP increase phenomenon can successfully be reproduced. In addition, we provide first results on how to avoid the unwanted increase in inventory.