InGaAs-OI Substrate Fabrication on a 300 mm Wafer
In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs) wafer on insulator (InGaAs-OI) substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB) and Smart CutTM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 °C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM), scanning acoustic microscopy (SAM), and HR-XRD, to insure the crystalline quality of the post transferred layer.
Metallization defect detection in 3D integrated components using scanning acoustic microscopy and acoustic simulations
Abstract In the context of More than Moore 3D integration concepts, the μm to nm sized failure detection and analysis represents a highly demanding task. In this work, micron sized artificially induced metallization defects in open TSVs are detected by scanning acoustic microscopy (SAM). Micro X-ray computed tomography (μXCT) and scanning electron microscopy (SEM) are used to validate the SAM results. Notably, the SAM results show that the failures for certain TSVs are located at a different position as illustrated by μXCT and SEM. In order to interpret these controversial results, 2D elastodynamic finite integration technique (EFIT) simulations are performed. We discuss the results by taking the excitation of surface acoustic waves (SAWs) or Rayleigh waves into account which are leading to characteristic interference patterns within the TSV. The simulation and understanding of such interference effects can be highly beneficial for the use of SAM with respect to modern failure detection and analyses.
Measuring Sheet Resistances of Dielectrics Using Co‐Planar Hydrogel Electrochemical Cells with Practical Applications to Characterize the Protective Quality of Paints on Sculptures
Electrical properties of thin dielectric films at the solid-liquid phase boundary are an important performance characteristic of many devices, coatings and sensors. In this paper, co-polymeric hydrogels of polyacrylic acid co-sulfonic acid, swollen with a salt solution to act as the solid electrolyte, were used to assess interfaces using electrochemical impedance spectroscopy (EIS) in a co-planar geometry. Silane-modified glasses were characterized by the co-planar hydrogel EIS cell and found to be distinguishable based on their surface monolayer chemistry. EIS measurements were also made on primed and painted metal substrates, using both test panels and an outdoor sculpture, Tony Smith's Stinger. The panels were then exposed to accelerated and outdoor weathering and showed degradation on the surface paint layers, which was observable electrochemically using EIS and confirmed visually by SEM. Electrochemical spectral features were compared between data from a standard paint-test cell versus this co-planar hydrogel cell; both cell types were able to measure coating capacitance, providing useful information about the condition of the bulk coating. Yet, sheet resistance (Rs) was a spectral feature seen only by the co-planar hydrogel cell. Thus, it can be concluded that the use of such co-planar hydrogel cells can provide an earlier warning sign to coating degradation and such cells provide a new type of spectral information that is not assessable by the standard geometry.