Dopant influence on polysilicon capacitor oxide failure
In this work, we investigate polysilicon capacitor oxide defectivity as a function of dopant contamination in a 0.5 /spl mu/m mixed signal process. Experiments show that shallow n and p type dopant implants, used to mimic a cross contamination problem discovered in a PECVD cluster tool, can significantly degrade oxide integrity. Various possible mechanisms of the increased defectivity are discussed.
The effect of gate doping on the electrical conduction and reliability of thick gate oxides
Previous investigations have shown that excessive gate oxide leakage currents at negative gate potentials observed in MOS power products are due to the presence of phosphorus in the gate oxide. During polysilicon gate doping some phosphorus atoms may pile up at the PSi/SiO2 interface and also may diffuse into the gate oxide due to high diffusion temperatures and longer soaking times. Subsequent high temperatures and plasma processing steps result in the ionization of these atoms. The neutralization of these ions during negative gate voltage testing gives rise to abnormal gate oxide leakage currents. It is shown that the presence of any Column V element in the gate oxide, if ionized, will result in excessive gate oxide leakage currents at negative potentials. The level of excessive leakage will depend on the amount of pile up of the impurity at the polysilicon gate/SiO2 interface. Data show that abnormally high gate oxide leakages due to the presence of these impurities in the gate oxide of MOS, IGBT and MCT devices may adversely affect the yield and the long term reliability.
Novel process and device technologies for submicron 4Mb CMOS EPROMs
High performance and reliable submicron EPROM technologies to realize 4Mb density and fast operation speed have been developed. The main key process technologies are (a) thin reliable inter-poly dielectrics, (b) SAC (Self Aligned Contact) using RTA (Rapid Thermal Annealing), and (c) low resistance polycide gate. The device uses 0.8µm N-well CMOS technology. Masked MLDD(Moderately Lightly Doped Drain) NMOS transistors are used in peripheral circuits. Submicron EPROM cell offers sufficiently fast write speed and soft-write endurance.