A New Isolation Process for VLSI Devices
In this paper we present a new zero-bird's beak process which, with an additional photolithographic step, substitutes the thermal fully-recessed field oxide for a CVD oxide. With this process we have fabricated devices which present a very small narrow channel effect. Moreover, the use of a reference mask increases the process reproductivity and reduces the probability of the double-threshold voltage effect. The cross-section and electrical results are presented.
Double threshold MOSFETs in bird's-beak free structures
Edge effects found in MOSFET channels fabricated by a new bird's-beak-free process are studied by two-dimensional simulation. Test devices are also fabricated using the side wall masked isolation (SWAMI) process, and electrical characristics are measured. At the sharp corners of active- to field region boundaries, threshold lowering occurs because of electric field concentration. The effective channel width associated with the threshold voltage is very narrow ranging from 0.05 um or less to 0.3 um. Both the threshold and the effective width depend on the shape of the corner, and have weaker dependence on the substrate and surface impurity concentrations and substrate bias, than those of the planar surface devices. The optimization of MOS devices with bird's-beak free structure for conventional applications with very tight design rules is discussed. A three-transistor static memory cell utilizing the double threshold (DT) MOST is proposed and analyzed.
SDW MOSFET static memory cell
The single device well (SDW) memory cell, including an access transistor, uses only two SDW MOSFETs, versus four-to-six transistors in conventional static memory cells and thus a great saving in silicon area results. Cell static and dynamic performance are discussed and simulated using an appropriate model implemented in the computer-aided circuit analysis program WATAND. The access time of the new cell is comparable to that of conventional MOSFET cells. Using 3 /spl mu/m technology, an SDW memory cell consumes an area of 600 /spl mu/m/SUP 2/ and has an average power consumption of 10 /spl mu/W at 5 V supply. Another version of the cell using a polyresistor is also discussed.