TiCl4 Barrier Process Engineering in Semiconductor Manufacturing
Titanium nitride (TiN) not only was utilized in the wear-resistant coatings industry but it was also adopted in barrier processes for semiconductor manufacturing. Barrier processes include the titanium (Ti) and TiN processes, which are commonly used as diffusion barriers in via/contact applications. However, engineers frequently struggle at the via/contact module in the beginning of every technology node. As devices shrink, barrier processes become more challenging to overcome the both the physical fill-in and electrical performance requirements of advanced small via/contact plugs. The aim of this paper is to investigate various chemical vapor deposition (CVD) TiCl4-based barrier processes to serve the application of advanced small via/contact plugs and the metal gate processes. The results demonstrate that the plasma-enhanced chemical vapor deposition (PECVD) TiCl4-based Ti process needs to select a feasible process temperature to avoid Si surface corrosion by high-temperature chloride flow. Conventional high step coverage (HSC) CVD TiCl4-based TiN processes give much better impurity performance than metal organic chemical vapor deposition (MOCVD) TiN. However, the higher chloride content in HSC film may degrade the long-term reliability of the device. Furthermore, it is evidenced that a sequential flow deposition (SFD) CVD TiCl4-based process with multiple cycles can give much less chloride content, resulting in faster erase speeds and lower erase levels than that of conventional HSC TiN.
Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices
This paper reports on the optimization of the device and wiring in a via structure applied to multilevel metallization (MLM) used in CMOS logic devices. A MLM via can be applied to the Tungsten (W) plug process of the logic device by following the most optimized barrier deposition scheme of RF etching 200 Å IMP Ti (ion metal plasma titanium) 200 Å CVD TiN (titanium nitride deposited by chemical vapor deposition) 2 × 50 Å. The resistivities of the glue layer and barrier, i.e., IMP Ti and CVD TiN, were 73 and 280 μΩ·cm, respectively, and the bottom coverages were 57% and 80%, respectively, at a 3.2:1 aspect ratio (A/R). The specific resistance of the tungsten film was approximately 11.5 μΩ·cm, and it was confirmed that the via filling could be performed smoothly. RF etching and IMP Ti should be at least 200 Å each, and CVD TiN can be performed satisfactorily with the existing 2 × 50 Å process. Tungsten deposition showed no difference in the via resistance with deposition temperature and SiH4 reduction time. When the barrier scheme of RF etching 200 Å IMP Ti 200 ÅCVD TiN 2 × 50 Å was applied, the via resistance was less than 20 Ω, even with a side misalignment of 0.05 μm and line-end misalignment of ~0.1 μm.
Finite Difference Modeling on the Temperature Field of Substrate in Friction Surfacing
Friction surfacing is an advanced process of great potential, especially in the field of repair and reclamation of worn and damaged components. As a kind of thermal processing technology, the temperature profile and changes of the substrate in friction surfacing are important factors to get coatings of high quality. In this paper, the temperature field of the substrate during the process is simulated by finite difference method. The results are consistent with experiments, reappearing the temperature change of the substrate during friction surfacing, allowing further study on figuration and quality of coatings.