Formation and microstructure of thin Ti silicide films for advanced technologies
We report on the solid-state reaction of thin PVD Ti films with in-situ doped Si & SiGe alloys using a combination of in-situ x-ray diffraction, sheet resistance, laser light scattering measurements and ex-situ x-ray pole figure analysis. Thin Ti films or thin bilayer films (Ni/Ti or NiPt/Ti) are found to be much more aligned with the underlying substrates. Millisecond laser anneals also lead to the introduction of strong in-plane texture.
High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization
We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4th generation deep trench embedded DRAM to provide an ultra-dense (0.0174um2) memory solution for industry leading `scale-out' processor design. A broad range of Vts is enabled on chip through a unique dual workfunction process applied to both NFETs and PFETs. This enables simultaneous optimization of both lowVt (HP) and HiVt (LP) devices without reliance on problematic approaches like heavy doping or Lgate modulation to create Vt differentiation. The SOI finFET's excellent subthreshold behavior allows gate length scaling to the sub 20nm regime and superior low Vdd operation. This leads to a substantial (>35%) performance gain for Vdd ~0.8V compared to the HP 22nm planar predecessor technology. At the same time, the exceptional FE/BE reliability enables high Vdd (>1.1V) operation essential to the high single thread performance for processors intended for `scale-up' enterprise systems. A hierarchical BEOL with 15 levels of copper interconnect delivers both high performance wire-ability as well as effective power supply and clock distribution for very large >600mm2 SoCs.
Nickel silicide encroachment formation and characterization
The stability of nickel-based silicides integrated in CMOS circuits has been studied. The evolution of transistor electrical failures is then reported, linked to Ni abnormal migration through different process steps. We have found in our studies that Ni encroachment is not only due to NiSi"2 clusters formation but also to NiSi precipitates formation. Silicon substrate doping, surface preparation, nickel film thickness and the thermal treatments were identified to modify occurrences of this randomly localized phenomenon. Ni-rich phase initial formation is preferable to prevent Ni encroachment even though other upstream process steps for CMOS integration are also key for Ni migration control.