Scalable high performance loop filter architecture for video codecs
There is continuous thrust on improved and innovative video solution to facilitate video conferencing, video surveillance, transcoding, streaming video and many more customer centric new solutions. Increasing frame rate and frame size demands high performance hardware accelerators (HWA) to enable efficient 16×16 pixels macroblock level (MB) pipelining inside video processing engine (IVAHD). Inloop de-blocking filter of H.264 codec reduces blocking artifacts in MB and it is very demanding in terms of cycles and resources (memory access and memory storage). Removal of blocking artifacts due to block-based video codecs takes around 20-25% of overall decoder complexity in current generation of standards (H.264) and trend will continue going forward in H.265. Higher adaptability of filter process, smaller block sizes (4×4), motion vector (MV) dependent boundary strength (BS) computation for each edge of 4×4 block, predefined order for doing filtering (vertical edge followed by horizontal edge) and data pixel loading of current and neighbor MB requires large number of accesses to shared memory of IVAHD (SL2), higher processing cycles and larger internal pixel buffer (IPB). This paper discusses novel approach of loop filter (LPF) operation to overcome above barriers and facilitate IVAHD to go up to 240fps frame rate in full HD processing of H.264 codec with leadership area and power. The final design in 28nm CMOS process is expected to take around 0.10 mm2 after actual place and route (consisting of 220 KGate with 5 KB of internal memory). Proposed design is capable of handling 4K@60fps and scalable to support H.265 inloop de-blocking filter.
Hardware-and-memory-sharing architecture of deblocking filter for VP8 and H.264/AVC
In this paper, a hardware sharing architecture is proposed to support multi-standards--VP8 and H.264/AVC. To achieve a common architecture, the deblocking filters of VP8 and H.264/AVC are reorganized, and the lossless sharing architecture (RO-DBK) is obtained. For the lossy application such as low-resolution display devices, the modified coefficients to derive a highly sharing architecture (LC-DBK) are further adapted. The experimental results show that the PSNR only drops 0.36% on average for LC-DBK. These two proposed architectures save 74.2% and 80.2% arithmetic logic units, respectively. To further reduce memory usage, we propose a new VLSI architecture. In this VLSI architecture, the deblocking filter and the interpolation result of motion compensation and inverse transform share the same SRAM. To achieve this, a rearranged filtering order is also proposed. This design only uses 32 bytes transpose buffer without any SRAM usage. To reach real-time processing, a 3-staged pipeline scheduling is also proposed. The proposed design is implemented within 0.18 μm process. The working frequency is 100 MHz and the overall gate count is 3.9K.
Mechanics of deformable directed surfaces
Abstract The paper develops a simple, yet complete and consistent non-linear dynamic thermo-elastic shell theory based on the concepts of a two-dimensional directed continuum. The constitutive equations are postulated in a general form. Stress-strain relations are derived using the equation of energy balance and the two entropy production inequalities, which are rewritten in a special form. The linear theory is discussed in detail. The structure of the stress-strain relations is presented in the most general form and then specialized to concrete examples, in particular, to the classical shell theory, using their invariance properties with respective to certain symmetry groups. The elastic moduli are determined by demanding the coincidence of the frequency dispersion surfaces obtained using the two-dimensional theory with the lowest foils of the corresponding surfaces resulting from the three-dimensional theory of elasticity.