High-Power High-Efficiency L-band Multiple-Beam Klystron Development at CPI
Communications and Power Industries, Inc., has designed and manufactured two versions of a 10-MW-peak high-efficiency multiple-beam klystron (MBK) operating at 1300 MHz. This type of klystron is favored for large particle accelerator projects such as the European X-ray Free-Electron Laser at the Deutsches Elektronen Synchrotron (DESY). Two klystrons have been made for DESY. The first-generation MBK was a vertically oriented prototype using a six-cavity design with higher order mode input and output cavities and conventional intermediate cavities. For cost and performance reasons, the second-generation MBK, designated VKL-8301B, utilized seven coaxial fundamental-mode cavities and is an “industrialized” horizontally oriented klystron. The klystron was designed and optimized using state-of-the-art multidimensional design codes to ensure that all performance requirements are exceeded. Agreement between the simulated and measured performances is good. The VKL-8301B prototype achieved a peak saturated RF output power of 10.4 MW and 67.8% efficiency. The data were measured at the full 1.5% duty and with 1.5-ms pulse width. The klystron satisfied all required operating conditions, including stable operation into an output mismatch of 1.2:1 voltage standing wave ratio at various phases. The prototype has been shipped to DESY and has been successfully tested by a customer.
Status of the 805-MHz pulsed klystrons for the Spallation Neutron Source
Communications and Power Industries, Inc (CPI) produced 81 klystrons for the Spallation Neutron Source at Oak Ridge National Laboratory. The klystrons are rated for 550 kW peak at 805 MHz. seventy units have accumulated 1,284,647 hours of filament operation and 820,429 hours of high voltage operation to date. A higher power 700 kW version has been developed and is now in production.
THE RF-STATION INTERLOCK FOR THE EUROPEAN X-RAY LASER
The RF-station interlock for the European X-ray laser will be based on a 19"- 3U crate incorporating a controller with the 32-bit RISC NIOS-processor (ALTERA). The main task of the interlock system is to guarantee safety of personnel and prevent any damage from the components of the RF station and connected cavities. The interlock system must also guarantee a maximum time of operation of the RF stations which implies the implementation of self diagnostics and repair strategies on a module basis. Additional tasks are: collection and temporary storage of status information of the individual channels of the interlock system, transfer of this information to the control system, slow control functions (e.g. HV setting and monitoring) and control of inputs and outputs from and to other subsystems. In this paper we present the implementation using an ALTERA-FPGA running a 32bit RISC NIOS-processor. Connection to the accelerator main control is provided by Ethernet using BSD-style socket routines based on ALTERA's plugs-library. The layout of the system is presented and first hardware components are shown.