Amplifier and Driver Circuits for Thin Film Memories with 15 Nanoseconds Read Cycle Time
Amplifier and driver circuit design principles for an experimental 4608-bit nondestructive thin film memory with 13.5-nsec read and 60-nsec write cycle times are given. The bit noise problems inherent in the common bit sense line concept are solved by using tunnel diodes in a nonlinear balancing circuit. A further improvement of the signal-to-noise ratio is achieved by employing a noise resistant sense amplifier with nonlinear negative feedback. The word driver described is capable of delivering 700 ma pulse amplitude at 50 mc repetition rate at a pulse width of 7 nsec.
A very-high-speed, nondestructive-read magnetic film memory
A very-high-speed thin magnetic film memory has been designed and built as a cross sectional test model for 140 000 bits. It can be operated in the NDRO mode with a 20-nsec read cycle time and a 30-nsec access time, and it can be read 65 nsec after the beginning of a write operation.
Transistor stages for wide-band amplifiers
The risk of instability when negative feedback is applied to a multistage amplifier is minimized by dividing the amplifier into sections, each with its own feedback. If there are not more than two 90° phase-shifts in each feedback loop, the circuit will be stable. Since the interaction between cascaded stages depends on their input and output impedances, various methods of controlling these impedances have been examined. Several practical wide-band amplifier circuits are described, and it is shown that such circuits can be made to accept wide variations in transistor characteristics.When operation is required near the cut-off frequency of the transistor, a transformer coupling is proposed. The relatively poor low-frequency response of this circuit is improved by the addition of an RC coupling.Bias currents in the transistor circuits are fixed by a d.c. feedback which is decoupled at signal frequencies. Operation at very low frequency (<1 c/s) is considered.