Apply Difference Analysis to Nano-Probing Technique for Reasoning Erratic Defect out in Integrated Circuits
The purpose of this paper is to present a novel deductive methodology, which is accomplished by applying difference analysis to nano-probing technique. This methodology would like to resolve the erratic device with a tailing failure or puzzling feature, but not only to check if the suspect had incorrect characteristic or mismatched transistor parameters
Electrical characterization by sub-micron probing technique on 90 nm CMOS technology for failure analysis
As the failure mechanisms become more complex with IC technology progression, the failure analysis (FA) needs electrical characterization of die internal transistors to fault identification and discrimination of various defect types. The sub-micron probing (SMP) with 4 needles allows all electrical characteristics measurements of a single transistor and leads to accurate results in FA with a best root cause understanding. This paper presents the effectiveness of the 4 needles-SMP technique and reports experimental results during the threshold voltage/BVDSS measurements of the 6 transistors of RAM cell on a 90 nm CMOS technology in the Nice Device Analysis Laboratory (NDAL) of Texas Instruments France.
Simplified impedance design and control for low-cost high-speed channels
Impedance design is the fundamentals of signal integrity at the very beginning, but controlled impedance is always costly or time-consuming for the high-speed channels. In this paper, many simulations of channel parasitics were taken and calculated that met with the specified impedances and correlated to the measurements very well. Selection of the different substrate stack-up without any layout modification in the BGA package reversed from the failed verification to pass the differential return loss. Adjustment of lead widths and spaces in the limited room of leadframe package improved 6 Ω of differential-mode impedance compared to the conventional leadframe packages. The differential pairs with wider traces routed on the 2-layer PCB are more robust for over-etching effects whose impedance errors are less than 5% without special impedance control. Moreover, those pairs inserted with a thin ground trace achieved 90 Ω differential-mode impedance and 28.2 Ω common-mode impedance simultaneously with 35% less routing area for MHL application and reserved a 10 Ω series resistor for ESD protection. With those diligent designs, the leadframe package and the 2-layer PCB can be still adopting in the consumer electronics for high-speed applications.