3D integration technologies for MEMS
This paper describes selected technologies for the 3D integration of MEMS devices. This comprises a Via Last approach for the formation of MEMS TSVs and a Cu based thermo-compression bonding method for the realization of small 3D-WLP devices. Moreover, the Aerosol Jet technique is discussed as method for the final assembly by means of printing conducting lines over 3D topography.
Research on Effect of Annealing on Copper Deposited by Electroplating in High Density TSV
Through silicon via (TSV) has proved to be a vital interconnection component in three dimensional circuit intergration and advanced packaging, for it has incomparable superiorities in device miniaturization, high density and multifunction. However, in TSV structure, the stress of thermal mismatch between silicon and electroplating deposition(ECD) copper and the accumulated residual stress in process make thermal-mechanical reliability become a main factor affecting the development of TSV technology, which may perhaps result in serious reliability problems once an appropriate destressing treatment is not taken. In order to improve the reliability of TSV, annealing is used to facilitate the recrystallization of ECD copper and reduce structure stress. In this article, a large size TSV in which the diameter is 30µm and the depth is 200µm with a high density of 0.59% was fabricated and then filled with ECD copper. After a pre-CMP process, annealing experiments at different conditions were designed to get a less residual stress structure. TSV pumping was measured by Step Profiler. Scanning Electronic Microscopy (SEM) and Electron Backscattered Diffraction (EBSD) were used to characterize ECD copper after annealing. Effect of annealing on ECD copper was studied and appropriate annealing parameters were acquired according to the measured results above.
Simplified impedance design and control for low-cost high-speed channels
Impedance design is the fundamentals of signal integrity at the very beginning, but controlled impedance is always costly or time-consuming for the high-speed channels. In this paper, many simulations of channel parasitics were taken and calculated that met with the specified impedances and correlated to the measurements very well. Selection of the different substrate stack-up without any layout modification in the BGA package reversed from the failed verification to pass the differential return loss. Adjustment of lead widths and spaces in the limited room of leadframe package improved 6 Ω of differential-mode impedance compared to the conventional leadframe packages. The differential pairs with wider traces routed on the 2-layer PCB are more robust for over-etching effects whose impedance errors are less than 5% without special impedance control. Moreover, those pairs inserted with a thin ground trace achieved 90 Ω differential-mode impedance and 28.2 Ω common-mode impedance simultaneously with 35% less routing area for MHL application and reserved a 10 Ω series resistor for ESD protection. With those diligent designs, the leadframe package and the 2-layer PCB can be still adopting in the consumer electronics for high-speed applications.