Advanced activation and stability of ultra-shallow junctions using flash-assisted RTP
Advanced-logic device technology for the 65 nm node and beyond requires highly-activated, shallow, and abrupt dopant profiles (Int. Technol. Roadmap for Semicond., 2003). The combination of ion implantation and an advanced annealing technology is expected to provide solutions for these requirements. In contrast to spike annealing, a diffusion-less but highly activating, high-temperature, flash-assisted RTP annealing approach for the formation of ultra-shallow junctions will be demonstrated. The flash-assisted RTP technique is a promising method for achieving junction depth and sheet resistance values low enough to meet the performance specifications for the 65 nm node and beyond (Gelpey, et al., 2002, McCoy, et al., 2004). The optimal process for high activation during flash-assisted RTP involves a temperature ramp-up to an intermediate temperature between 700degC and 900degC and, once the intermediate temperature is reached, a very short, intense flash on the front side of the wafer induces a temperature jump up to 1325degC with a peak width of approximately 1.6 ms in a 100 ppm oxygen in nitrogen gaseous ambient. In this paper, we will present some of our recent p+MOS and n+MOS results on the fabrication of ultra-shallow junctions using flash-assisted RTP in crystalline and pre-amorphized silicon. It will be shown that such junctions are suitable for future technology generations. The measured "mechanical/electrical" sheet resistance values of the junctions are compared to Hall measurements on the same samples to gain an insight into the reliability of the destructive four-point probe (4PP) method for such extremely shallow junctions. Deactivation studies will be presented to examine the stability of the process to the required subsequent thermal processes
Materials aspects, electrical performance, and scalability of Ni silicide towards sub-0.13 μm technologies
Ni-silicide phase formation with and without a Ti capping layer was studied by sheet resistance, x-ray diffraction and transmission electron microscopy. Ni monosilicide is found to be the stable phase in a temperature range from 400 to 600 °C. At lower temperatures the Ni2Si phase is found to be present. For temperatures higher than 700 °C NiSi is converted into NiSi2. Pyramidal NiSi2 precipitates were found to grow epitaxially along the Si〈111〉 planes for annealing temperatures as low as 310 °C. The epitaxial NiSi2 grains were found to disappear when the annealing temperature is increased. Stress buildup during Ni silicidation was measured in situ and could be correlated to the formation of the different Ni-silicide phases. The stress induced by Ni-monosilicide formation compares favorably to the stress induced by Co disilicide and Ti disilicide. The average silicon consumption required to obtain a certain sheet resistance was found to be 35% lower for Ni monosilicide compared for Co disilicide. It was f...
SR topography of plastically deformed Fe-Si bicrystals - observation in situ and post mortem
SR reflection topography was applied to study the interaction of slip dislocations with the grain boundaries in Fe-4at%Si bicrystals deformed by compression. Three experimental settings with either a white or monochromatic beam were used and the corresponding orientation contrast analysed. Dislocation transmission through the grain boundary was observed in bicrystals with favourable geometry of the slip systems.