Study on defect reduction for high aspect ratio etch process
Increasing data needs much larger memory capacity. One of the Flash Memory Solution is Vertical NAND (V-NAND) Flash Memory. In order to fabricate this device, a high aspect ratio hole must be made in the channel hole through the etching process after multilayer thin film deposition. In order to obtain high aspect ratio etch, process condition should have high RF power, high flow rate of polymer gas, and long process time. This harsh etch condition results in high ion energy and lots of polymer production. It can create defects like fluorocarbon polymer and arcing. In this study, we studied arcing mechanism. Here we defined various margins for arcing-free and optimized the focus ring. And we improved pumping conductance for polymer discharge. This study removed defects and obtained arcing-free during V-NAND etch process.
Backend dielectric etch induced wafer arcing mechanism and solution
A significant challenge for dielectric etching in advanced chip designs is a new plasma damage phenomenon called "wafer arcing." This randomly occurring problem is characterized by burned metal and "worm-like" arcing marks along the wafer's edge and the conducting wide metal lines around the die periphery. Arcing-induced particles also increase chamber contamination, requiring more maintenance and downtime. With the impact on yield per wafer, minimizing the frequency has become a key selection criterion for dielectric etch systems, especially for 300 mm manufacturing. Wafer arcing is a response to particular wafer surface structure conditions and plasma instability. Most conducive to this problem are dielectric etch process steps with a prior conductive layer beneath, such as pad and via etch. Arcing can be significantly reduced by a combination of cathode design to support better plasma stability, and electrostatic chuck and process kit design to minimize field gradients across the wafer. In addition, equipment operation parameter settings and process recipes can be optimized to reduce wafer arcing frequency. Providing an advanced chamber design has enabled us to achieve superior wafer arcing performance of less than 1 in 20,000 wafers.
Electrochemical detection of copper(II) at a gold electrode modified with a self-assembled monolayer of penicillamine
A penicillamine (PCA) self-assembled monolayer (SAM) was prepared on a gold electrode. It has been found that the modified electrode exhibited a selective response to copper ions. As demonstrated by cyclic voltammetric experiments, the SAM-based electrode showed an attractive ability to preconcentrate efficiently traces of copper(II) from solutions. Under optimum conditions, the anodic peak current was proportional to the concentration of Cu(II) in the range from 8.0 × 10−7 to 1.0 × 10−4 M with a detection limit of 4.0 × 10−7 M. Moreover, this modified gold electrode is also characterized by excellent repeatability, showing a relative standard deviation of 3.2% for nine successive measurements of 1.0 × 10−5 M Cu(II). The PCA/Au SAM gold electrode was used for the determination of Cu(II) in a tap water sample and the results showed a good agreement with the data obtained by atomic emission spectrometry.