Dynamic performance analyze of swing angle torque permanent magnet motor under different structure and winding parameters
A swing angle torque permanent magnet motor operating mechanism is presented which applied in the high voltage circuit breaker. The motor is a permanent magnet motor with limited angle and only working in the starting stage. Based on the operation requirement of high voltage circuit breaker, the dynamic performance of driving motor operating mechanism is achieved by employing the finite element method. The parameters behavior of driving motor is obtained under the different structure and winding parameters, such as the length to diameter ratio, turns and line width ratio, thickness of permanent magnet, pole arc coefficient, length of air-gap and operating voltage. The results indicate that the motor operating mechanism have a good mechanical characteristics and reach the operation of high voltage circuit breaker.
Rare Earth Permanent Magnet Synchronous Motor CAD System Based on Engineering Database
This paper states the development of a CAD system of the rare earth permanent magnetic synchronous motor(REPMSM) designed by using Borland C++Builder 6.0,the OPP,and database technology.The magnetic field in the motor is analysed by finite element method and hybrid particle swarm optimization(HPSO) is applied to optimum design.The CAD system runs under Chinese Windows and it is easy to operate with friendly interface.The CAD result is compared with the experimental data,the result is consented.
Design of a low power viterbi decoder for wireless communication applications
In this paper, a novel low-power Viterbi decoder with soft decision is proposed. For the branch metric of the Viterbi decoder, our design employs a soft-decision method to improve its correction capability. In order to find the survivor path efficiently, we modify the classical Viterbi decoding algorithm into a new one. This new algorithm is similar to the register-exchange method with lower latency, but using RAM instead of register banks for recording the output bit-stream of the survivor path. Hence, our design can provide a low-power design. Finally, the chip of this design consumes about 28.6K gates using TSMC 0.18 μm CMOS technology. The power consumption of our chip is about 19.5mW at 100MHz.