Comparative study of tri-gate flash memories with split and stack gates
The functional tri-gate flash memories with splitgate have been demonstrated for the first time, and its Vt variabilities before and after one P/E cycle have be systimetically compared with stack-gate ones. It was confirmed that split-gate shows smaller Vt distribution after erase and excellent over-erase immunity compared to those of stack-gate. Moreover, it was found that BVDS is higher than 3.2 V even Lgc was down to 76 nm. This indictes that tri-gate is useful for scaled NOR flash.
A simple and efficient self-limiting erase scheme for high performance split-gate flash memory cells
This paper presents a fast self-limiting erase scheme for split-gate flash EEPROMs. In this technique the conventional erasing is rapidly followed by an efficient soft programming to correct for over-erase within the given voltage pulsewidth. The typical erasing time is about 400 ms and the final erased threshold voltage is accurately controlled via the base level read mode voltage within 0.3 V. The proposed scheme can he used for high throughput erasing in low voltage, high density, multilevel operation split-gate flash memory cells.
A novel band-to-band tunneling induced convergence mechanism for low current, high density flash EEPROM applications
A new low current two-step erasing scheme for "repairing" over-erased flash EEPROM cells has been developed. The cell convergence is achieved with 10 V on the control gate and 5 V on the source and drain for 50 ms. The convergence current is kept to below 1 nA per cell. A substrate BTBT tunneling induced hot electron injection mechanism is proposed for convergence. No significant oxide degradation is seen in the method.<<ETX>>