Improving Three-Dimensional Semiconductor Modeling through Layout and Process Flow Analysis
Constructive Solid Geometry (CSG) is a solid modeling technique widely used for the design of semiconductor devices. With the simulation domain subdivision algorithm presented in this paper, the minimal number of solid modeling operations is required in order to build a three-dimensional (3D) device structure. The algorithm is based on a drawing method which combines information on photolithographic masks into a color raster. In this way, solid modeling operations are performed only once on regions having the same color.
Reliable solid modeling for three-dimensional semiconductor process and device simulation
Since general-purpose 3D process simulators are currently not available, solid modelers greatly help the designer in building geometries for device simulators. In this contribution, a solid modeler is presented that allows reliable geometrical operations. In order to avoid numerical errors occurring at the intersection of objects built with polygons, we have chosen a data structure based on a discretization of the x-y plane of the simulation domain.<<ETX>>
Grid generation for three-dimensional non-rectangular semiconductor devices
The current availability of powerful computers permits the development of useful simulators for design and optimization of semiconductor de¬ vices. The semiconductor device simulation requires the numerical so¬ lution of partial differential equations. The part of the device to be sim¬ ulated (domain) is partitioned into a finite number of elements (grid), in which the solution is approximated. Proper 1-D and 2-D domain discretizations for general device geometries can already be generated. Current 3-D grid generators still have had problems in handling general device geometries, in modeling properly the internal quantities such as the doping profiles, and in fulfilling the required mesh density in every region of the device with as few points as possible. This thesis characterizes proper 3-D spatial discretizations for the simulation of geometrically complex semiconductor devices using the volume integration method or box method as the numerical integration method, and describes the implementation of the automatic grid gen¬ erator Qme (fi with mixed elements). The box method imposes several restrictions on the shape of the grid elements. It is shown that these restrictions are stronger in elements that lie at the material interfaces or at the boundary than in elements that are inside a material region. The suitable meshes are a subclass of the class of Delaunay meshes. The implementation of the grid generator fime is based on gener¬ alization of modified octrees. Instead of only bricks, a set of proper 3-D elements is used. Traditional algorithms based on modified octrees require several refinements along the boundary and material interfaces in order to fit the device geometry properly. Bricks are refined at the edge midpoints and partitioned into eight similar elements. Elements with additional split edges are subdivided into tetrahedra to get a finite element mesh. The approach presented here starts by fitting exactly the device geometry with a set of 3-D elements. Subsequently, the de¬ sired mesh density in the interior of the device is obtained through the