Using DOE to improve COB bonbability
In recent years, the Chip-on-Board (COB) package technology has become popular in semiconductor industries. The COB technology, in which the dies are directly mounted onto a printed circuit board (PCB) with bonding wires connecting the die and leads. Besides solder bumps, wire bonding is still the most popular interconnect method. With the development of wire bonding technology in the COB package, we can realize advanced processes with good performance by new wire bonding equipment and more powerful software. However, there are still many challenges to be overcome in the bonding process. In this paper, we did experiments to optimize the bonding parameter using 1.0mil Au wire on COB and successfully found the optimal range of bonding parameters through DOE (Design Of Experiment). By the optimal solution, we further improved the bondability; the second bonding quality was also improved by using BSOB (Bond Stitch On Ball) bonding.
Optimizing process conditions using design of experiments - A wire bonding, semiconductor assembly process case study
The striking competitiveness of modern-day companies is more than ever a direct function of their ability to implement high yielding processes and continuous optimization. Such optimization, however, is becoming increasingly harder to realize, due to the growing complexities of processes, networks, manufacturing system structures as well as business processes. The limitation of optimization tools exacerbates the difficulties in achieving competitiveness. The objective of this work is to investigate the merits and demerits of integrating systems tools for optimizing breakthroughs in manufacturing or business processes using DMAIC and DOE. The application and power of process optimization are examined using the semiconductor manufacturing industry. We seek to demonstrate that “integrated methodology” application to process optimization can enable enterprises to achieve substantial innovation and contribute to their quality standards, lower their cost and boost their competitiveness irrespective of the limitations that current tools may have.
Improving the fine-pitch stencil printing capability using the Taguchi method and Taguchi fuzzy-based model
This paper presents industrial applications for improving the capability of the fine-pitch stencil printing process (SPP) based on the DMAIC framework and using Taguchi-based methodologies. SPP is widely recognized as the main contributor of soldering defects in a surface mount assembly (SMA). An inadequate volume of solder paste deposition or poor printing quality can cause soldering defects and lead to significant reworking and repairing costs. In practice, both the desired amount of solder paste volume (quantitative index) and printing quality (qualitative index) are preferably used to monitor the SPP for the reduction of soldering defects during the statistical control process (SPC), particularly for a fine-pitch solder paste printing operation. To continuously improve SPP capability, the DMAIC framework is followed and Taguchi-based methodologies are proposed under the considerations of single characteristic performance index (SCPI) and multiple characteristic performance indices (MCPI). The SCPI is optimized using the conventional Taguchi method. Then, a Taguchi fuzzy-based model is developed to optimize the SPP with the MCPI property. Optimizing a multi-response problem by the Taguchi method involves the engineer's judgment which tends to increase the degree of uncertainty. The performance of these two approaches is compared through the process capability metric, and the material and factors significantly affecting the fine-pitch SPP performance are reported.