Wear monitoring of single-point dresser in dry dressing operation based on neural models
Faculty of Engineering Department of Electrical and Mechanical Engineering UNESP State University, Av. Luiz Edmundo Carrijo Coube, 14-01
Time-domain Analysis Based on the Electromechanical Impedance Method for Monitoring of the Dressing Operation
Abstract Among the methods used in structural health monitoring (SHM), the electromechanical impedance technique (EMI), which uses piezoelectric transducers of lead zirconate titanate (PZT), stands out for its low cost. Then, this paper presents a new approach for monitoring of the dressing operation from the digital processing of voltage signals based on the time-domain response of a PZT transducer by EMI method. Experimental tests of the dressing process were performed by using a single-point dresser equipped with a natural diamond. The voltage signals in the time-domain were collected in different damage levels. By using temporal statistics, it was possible to qualify different damage levels that the diamond suffered during the dressing operation, observing variations from the magnitude of the signals. The dressing operation is of utmost importance for the grinding process and the dresser wear negatively affects the result of the process, which owns high added value. In this way, this work contributes with a new monitoring tool which aims ensuring a consistent dressing operation.
Design of a low power viterbi decoder for wireless communication applications
In this paper, a novel low-power Viterbi decoder with soft decision is proposed. For the branch metric of the Viterbi decoder, our design employs a soft-decision method to improve its correction capability. In order to find the survivor path efficiently, we modify the classical Viterbi decoding algorithm into a new one. This new algorithm is similar to the register-exchange method with lower latency, but using RAM instead of register banks for recording the output bit-stream of the survivor path. Hence, our design can provide a low-power design. Finally, the chip of this design consumes about 28.6K gates using TSMC 0.18 μm CMOS technology. The power consumption of our chip is about 19.5mW at 100MHz.