Novel Program Method of String Select Transistors for Layer Selection in Channel-Stacked NAND Flash Memory
In this paper, we propose new string select transistors (SSTs)/dummy SSTs (DSSTs) threshold voltage (Vth) setting methods in simplified channel-stacked array with layer selection by multilevel operation (SLSM). In these methods, SSTs/DSSTs on each layer are set to their targeted Vth values by incremental step pulse program/one erase with various erase voltages, respectively. In the fabricated pseudo-SLSM, the validity of the new methods is verified. As a result, it is confirmed that the Vth values of SSTs/DSSTs are set to the targeted Vth values by the new methods and SSTs with extremely narrow Vth distribution can be obtained in the consequence. Moreover, memory operations such as erase, program, and read are performed in the fabricated structure after setting the Vth values of all the SSTs/DSSTs by the new methods. Despite unique LSM operations, stable memory operations are obtained successfully without the interference between stacked layers.
Comprehensive analysis of retention characteristics in 3-D NAND flash memory cells with tube-type poly-Si channel structure
Retention characteristics of a 3-D NAND flash cell with tube-type poly-Si body are investigated at a high temperature (T) depending on program (P), neutral (N), and erase (E) states of adjacent cells. The trap density (N<sub>t</sub>) in the nitride storage layer of the cell is extracted by utilizing retention model and deriving related equations in cylindrical coordinate. By programming or erasing adjacent cells, we can separate laterally distributed charge component from the retention characteristics. The adjacent cells which are programmed suppress significantly the lateral diffusion at a high T so that we can extract accurate N<sub>t</sub> profile. Extracted peak of N<sub>t</sub> at P-P-P mode is ~1.2×10<sup>19</sup> cm<sup>-3</sup>eV<sup>-1</sup> at an E<sub>C</sub>-E<sub>T</sub> of 1.0 eV. Retention characteristics with effective gate length and word-line biasing are also investigated.
Novel 3-D structure for ultra high density flash memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the same PlanE)
A 3-D flash memory cell of VRAT (vertical-recess-array-transistor) has been fabricated using a unique and simple 3-D integration method of PIPE (planarized integration on the same plane), which allows for the successful implementation of ultra high density flash memory. In addition, procedures to increase the memory density further using another advanced structure, Zigzag-VRAT (Z-VRAT), are developed.