Achieving ultra low k dielectric constant for nanoelectronics interconnect systems
Air gaps are a promising alternative to porous low-k dielectrics to achieve ultra low k-values in Cu damascene interconnects. Two approaches of air gap formation using wet etch back of sacrificial PECVD SiO2 dielectrics were evaluated concerning their feasibility and preparation results are shown. Electrical measurements were verified by simulation and have shown a capacitance reduction of approximately 50 % compared to the SiO2 filled reference structures. Furthermore finite element method (FEM) simulations were performed to extract the effective k-value for different technology nodes. General k eff extraction procedure by FEM simulation is described. Furthermore the impact of variation of thickness and k-value of the functional layers applied for air gap formation was investigated. These functional layers are etch stop, cap and mask layers and currently consist of PECVD SiC:H films. It has been shown, that both parameters (thickness and k-value) considerably contribute to the effective k-value. For both investigated technology nodes, the 65 nm and 45 nm node, parameters can be found to fulfil the ITRS requirements for keff. Lower k-values of the functional layers are needed, if the thickness has to be increased for processing reasons. For example k=5.5 and thickness of 15 nm yield a keff of about 2.5 for the 45 nm node. Ultimate effective k-values of 2.0 and below could be achieved for lower k-value or thickness of the functional films
General review of issues and perspectives for advanced copper interconnections using air gap as ultra-low K material
The present paper deals with the different techniques investigated in the whole microelectronics community to integrate air cavities, usually known as air gaps, in-between copper lines for advanced interconnects. The different integration processes were split into two categories, i.e. (i) using a non-conformal CVD deposition inside patterned trenches and (ii) by removing a sacrificial material using a specific technological operation. Advantages and drawbacks of the different approaches will be discussed, including integration issues, manufacturability, and electrical performances. The aim of the paper is to sensitize the BEOL community on these specific approaches that now appear attractive considering the electrical performances required for 45 nm and below technological nodes.
A new cell-based performance metric for novel CMOS device architectures
This paper introduces, for the first time, a method for assessing the impact of CMOS technology choices on dynamic system level performance. The method is applied to the evaluation of five different device architectures, which include bulk, FDSOI, and multi-gate devices. Timing and power information at the standard cell level is extracted for each of the devices and used to simulate their performance embedded within a cell array of 230,400 cells.