Impact of Radiation-Induced Single-Event Transients on High Resolution Time to Digital Converter
The paper presents the analysis of radiation-induced Single-Event Transients (SET) in Delay-Locked Loop (DLL) and its impact in the digital output of Time-to-Digital Converter (TDC). The performance of the TDC such as Differential Non-Linearity (DNL),Integral Non- Linearity (INL), resolution etc. are degraded due propagation of the SET from the DLL. The use of improved pseudo differential current-starved delay cell structure in the Voltage Controlled Delay Line (VCDL) in DLL reduces the impact of radiation- induced SET in DLL, and enhances the robustness of DLL based TDC. This effort represents the first of its kind SET analysis on a DLL based TDC. The proposed DLL based TDC is designed in the AMS 180 nm CMOS technology and simulations show that the number of missing pulses on a SET strike in the modified pseudo differential delay cell is reduced to 50% than compared the conventional architectures.
Single event Simulation methodology for analog/mixed signal design hardening
We propose a single-event simulation methodology to characterize the upset/error window of vulnerability for analog/mixed signal circuits. A custom designed 8-b pipeline analog-to-digital converter (ADC) is characterized and hardened based on the results of the simulations.
Chip scale packaging using chip-on-flex technology
An increasing number of electronic designers, fabricators and users see Chip Scale Packaging (CSP) as a way to obtain the benefits foreseen in multichip packaging and Chip-on-Board (COB) without the problems and limitations currently associated with each. The Chip-on-Flex (COF) multichip packaging technology has been demonstrated to be applicable to single chip packages that meet chip scale packaging goals. This paper looks at the Chip-on-Flex Chip Scale technology and addresses issues including the process, structure, assembly, yields and reliability.