Analyzing the improvement in efficiency through the integration of class-F power amplifiers compared to class-AB in an envelope tracking architecture
This paper investigates the performance of a class-F mode power amplifier (PA) integrated in an envelope tracking (ET) environment, compared to the conventional class-AB mode of operation in the same setting. A 10W high voltage laterally diffused metal oxide semiconductor (HVLDMOS) device is used to perform the comparison at 900MHz using an active load pull system in an emulated ET environment at 900MHz. The analysis looks at three scenario of optimization: when the class-F and class-AB PA's are optimized at individual drain voltage within the ET range, optimized at peak drain voltage, and optimized at the average drain voltage. The challenges of maintaining the device in class-AB and class-F modes throughout the ET range due to the variation of the device output capacitance are also presented in terms of the trajectory of the fundamental and harmonic loads, as well as the degradation in drain efficiency.
Environmental friendly mobile radio networks: Approaches of the European OPERA-Net 2 project
Reducing the overall environmental impact of mobile radio networks is a central factor in achieving improved mobile services whilst at the same time enabling a growing telecommunications industry in emerging markets. The OPERA-Net-2 (Optimising Power Efficiency in Mobile Radio Networks 2) project concentrates on this challenge, addressing both energy and material efficiencies of 3G, 4G and heterogeneous networks, while also considering the use of renewable energy sources. This paper presents an insight into the project after its first year and discusses research trends in `green communications networks' for the future.
Simplified impedance design and control for low-cost high-speed channels
Impedance design is the fundamentals of signal integrity at the very beginning, but controlled impedance is always costly or time-consuming for the high-speed channels. In this paper, many simulations of channel parasitics were taken and calculated that met with the specified impedances and correlated to the measurements very well. Selection of the different substrate stack-up without any layout modification in the BGA package reversed from the failed verification to pass the differential return loss. Adjustment of lead widths and spaces in the limited room of leadframe package improved 6 Ω of differential-mode impedance compared to the conventional leadframe packages. The differential pairs with wider traces routed on the 2-layer PCB are more robust for over-etching effects whose impedance errors are less than 5% without special impedance control. Moreover, those pairs inserted with a thin ground trace achieved 90 Ω differential-mode impedance and 28.2 Ω common-mode impedance simultaneously with 35% less routing area for MHL application and reserved a 10 Ω series resistor for ESD protection. With those diligent designs, the leadframe package and the 2-layer PCB can be still adopting in the consumer electronics for high-speed applications.