Importance of heat-up ramp rate for palladium-silicide fully-silicided-gate structure formation
Silicidation process for fully-silicided (FUSI) Pd2Si gate formation has been investigated. Two types of heating equipment was used for siliciding palladium deposited on a poly-Si/SiO2/Si MOS structure. One is lamp heating in a sputtering chamber and another is hot-plate heating. The former provide slower heat-up ramp because of relatively large thermal capacity. In this case, metal-rich phase was formed in the first stage of silicidation and it changed to Pd2 Si phase by additional heating after completion of silicidation reaction. FUSI utilizes impurity pre-doping to poly-Si to modulate workfunction. Pre-doping to poly-Si sometimes resulted in needle structure formation on a top of silicided film and voids at the interface between silicide and SiO2. These defects were reduced by silicidation with hot plate heating. In addition, Pd2 Si phase was obtained at the early stage of silicidation. Palladium and silicon reacts even at temperatures lower than 250degC. Therefore, in the case of the lamp heating, silicidation during heating is not negligible. These results are explainable considering change of major diffusion species during silicidation
Low-temperature redistribution of As in Si during Pd2Si formation
We have investigated the change in depth compositional profiles of implanted As in Si due to Pd2Si formation by using anodic oxidation and neutron activation analysis. We found that a high concentration (∼1×1021/cm3) of implanted As was snowplowed by the moving silicide‐Si interface into the substrate Si during Pd2Si formation at 250 °C. In other words, we have found a very low temperature process of doping As into Si. The amount of snowplowed As was found to be greater in samples which were preannealed at 900 °C—30 min before silicide formation than those without the preannealing.
A note on current-voltage measurements of n-type and p-type Pd2Si Schottky diodes
On presente les caracteristiques I-V des diodes Schottky en Pd et Si type n et p. Des hauteurs de barrieres de 0,7 ± 0,002 et 0,356 eV pour zero polarisation sont determinees pour des barrieres type n et p respectivement. A l'aide de la barriere de polarisation nulle, et du facteur d'idealite (η) approprie on a calcule les hauteurs de barriere en bande plate (champ nul) de 0,713 ± 0,002 et 0,406 eV pour les diodes Schottky sur des substrats du type n et p respectivement