A New CD Measurement Method Linked with the Electrical Properties of Devices
This paper describes a new measurement method of a CD-SEM with nanometer-level precision and good correlation with electrical characteristics for an actual device of ultra-large-scale integration (ULSI). With the decrease in feature size, the pattern to be measured tends to become a curved shape. In order to measure such a pattern within measurement precision on the order of 5 nm, two-dimensional measurement is effective. Here we report a new measurement algorithm featuring that the critical dimension is derived from the value of the area of a measurement pattern. We apply this measurement method to actual device of 64-Mbit DRAM and confirm the reproducibility of 3.6 nm for the gate linewidth measurement, and that of 5.6 nm for the hole diameter measurement. Furthermore, we verify that the measurement values of the gate linewidth have a strong correlation with the threshold voltage and those of the hole diameter also have a strong correlation with the contact resistance, respectively. key words: CD SEM, metrology, curved structure, electrical
Technologies For Automated In-Process E-Beam Metrology
A new wafer metrology system, featuring high throughput, automation, and E-beam accuracy has been developed. Novel technologies were integrated into the system in order to meet the stringent requirements of in-process VLSI critical dimension control.
Low Voltage Sem Metrology For Pilot Line Applications
In this paper, we consider the application of low voltage scanning electron microscopy (SEM) to practical pilot line problems of critical dimension (CD) measurements and in-process wafer inspection of small geometry ( <2 pm) VLSI circuits . Two low voltage field emission CD measurement SEMs with automated wafer stages and computerized digital control CD systems were used. CD data from the SEM was compared with results from optical microscopy and electron probe metrology systems. Cross-calibration of CD data between the two SEMs was also analyzed using a variety of patterned layers. These included CD patterns measured after resist development and after etching of diffusion, poly Si gate, contact and metal layers in a 1.2 μm CMOS process. Examples of inprocess wafer inspection are presented. In addition, new applications of SEM metrology for sidewall spacer width and stepped contact CD measurements are demonstrated.