Multi-phase-driven split-word-line ferroelectric memory without plate line
A working methodology bypasses the conventional cell plate line (PL), mitigating its disadvantages. The methodology utilizes split word lines (SWLs), driven by multi-phased voltage signals. In this scheme there is no need for PL and additional elements, and fabrication is simple and compatible with downscaling of cell area.
A 256 kb nonvolatile ferroelectric memory at 3 V and 100 ns
One of the most important features for ferroelectric material is fast write at low voltage. This feature is used in a 256 kb nonvolatile memory that operates at 3 V power supply with a read/write time of 100 ns. Active current is 3 mA at 200 ns cycle time at 3 V for battery operation. The cell consists of 1 transistor and 1 capacitor per bit (1T1C) permitting a high level of integration. For low-voltage low-power operation, use is made of a preset reference-cell circuit, wordline boost circuits with a ferroelectric boosting capacitor and a divided-cell plate circuit.<<ETX>>
New approach to vision-based BGA package inspection
Ball grid array (BGA) techniques have developed very fast due to the advantages of more I/O ports, small size, and so on. In this paper, a vision-based algorithm for BGA package inspection is proposed to accurately estimate center and diameters of solder-balls of BGA packages, so that defects of BGA packages, such as missing or extra balls, oversize or undersize balls, over-height or under-height balls, and pitch can be detected for ensuring the quality of BGA packages.