A combined IEEE half and single precision floating point multipliers for deep learning
In deep learning, single precision floating point multipliers are widely used and the most power-hungry arithmetic operators. However, although multipliers are power intensive, they are necessary for applications that require multiplication. In this paper, we propose a novel combined IEEE half precision and single precision floating point multipliers for deep learning. Our design can be easily configured to run in the half precision mode for power saving or in the single precision mode for accuracy. Compared to conventional IEEE single precision multipliers, the combined multipliers require only a small amount of additional area and delay, while offer a significant reduction in power dissipation.
A Well-Equipped Implementation: Normal/Denormalized Half/Single/Double Precision IEEE 754 Floating-Point Adder/Subtracter
This paper shows the implementation and design of a completely IEEE 754-compliant floating-point adder and subtracter. This design focuses on maintaining low critical delay and power, while still containing hardware for full IEEE 754 compliance. A novel 64-bit prefix adder structure is used, where most of the performance benefits over a standard design come from parallelization. This adder and subtracter has full support for binary64, binary32, and binary16 operands. It also has the ability to convert integer values to the IEEE 754 standard. Integer conversion for binary64, binary32, and binary16 is supported, as well as conversion between any of the aforementioned IEEE 754 precisions. This design also has full support for denormalized operands. Synthesis results presented use a cmos32soi 32nm CMOS technology and ARM standard-cells.
Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support
The demand for improved SIMD floating-point performance on general-purpose x86-compatible microprocessors is rising. At the same time, there is a conflicting demand in the low-power computing market for a reduction in power consumption. Along with this, there is the absolute necessity of backward compatibility for x86-compatible microprocessors, which includes the support of x87 scientific floating-point instructions. The combined effect is that there is a need for low-power, low-cost floating-point units that are still capable of delivering good SIMD performance while maintaining full x86 functionality. This paper presents the design of an x86-compatible floating-point multiplier (FPM) that is compliant with the IEEE-754 Standard for Binary Floating-Point Arithmetic and is specifically tailored to provide good SIMD performance in a low-cost, low-power solution while maintaining full x87 backward compatibility. The FPM efficiently supports multiple precisions using an iterative rectangular multiplier. The FPM can perform two parallel single-precision multiplies every cycle with a latency of two cycles, one double-precision multiply every two cycles with a latency of four cycles, or one extended-double-precision multiply every three cycles with a latency of five cycles. The iterative FPM also supports division, square-root, and transcendental functions. Compared to a previous design with similar functionality, the proposed iterative FPM has 60 percent less area and 59 percent less dynamic power dissipation.