A combined IEEE half and single precision floating point multipliers for deep learning
In deep learning, single precision floating point multipliers are widely used and the most power-hungry arithmetic operators. However, although multipliers are power intensive, they are necessary for applications that require multiplication. In this paper, we propose a novel combined IEEE half precision and single precision floating point multipliers for deep learning. Our design can be easily configured to run in the half precision mode for power saving or in the single precision mode for accuracy. Compared to conventional IEEE single precision multipliers, the combined multipliers require only a small amount of additional area and delay, while offer a significant reduction in power dissipation.
A quadruple precision and dual double precision floating-point multiplier
Double precision floating-point arithmetic is inadequate for many scientific computations. This paper presents the design of a quadruple precision floating-point multiplier that also supports two parallel double precision multiplications. Since hardware support for quadruple precision arithmetic is expensive, a new technique is presented that requires much less hardware than a fully parallel quadruple precision multiplier. With this implementation, quadruple precision multiplication has a latency of three cycles and two parallel double precision multiplications have a latency of only two cycles. The design is pipelined so that two double precision multiplications can be started every cycle or a quadruple precision multiplication can be started every other cycle.
Dual-mode floating-point multiplier architectures with parallel operations
Although most modern processors have hardware support for double precision or double-extended precision floatingpoint multiplication, this support is inadequate for many scientific computations. This paper presents the architecture of a quadruple precision floating-point multiplier that also supports two parallel double precision multiplications. Since hardware support for quadruple precision arithmetic is expensive, a new technique is presented that requires much less hardware than a fully parallel quadruple precision multiplier. With this architecture, quadruple precision multiplication has a latency of three cycles and two parallel double precision multiplications have latencies of only two cycles. The multiplier is pipelined so that two double precision multiplications can begin every cycle or a quadruple precision multiplication can begin every other cycle. The technique used for the dual-mode quadruple precision multiplier is also applied to the design of a dual-mode double precision floating-point multiplier that performs a double precision multiplication or two single precision multiplications in parallel. Synthesis results show that the dual-mode double precision multiplier requires 43% less area than a conventional double precision multiplier. The correctness of all the multipliers presented in this paper is tested and verified through extensive simulation. 2006 Elsevier B.V. All rights reserved.