Simulation study on influence of interface trap position in Sii-xGex Gate-All-Around (GAA) field-effect transistor
In this paper, performance degradation of Si1−xGex gate-all-around (GAA) Field-Effect Transistor (FET) depending on interface trap position was investigated through TCAD simulations. Interface traps were located at three different points along the channel. Parameters such as hole mobility and energy band were analyzed to understand the effects of partially generated interface traps by unstable GeOx.
Selective GeOx-scavenging from interfacial layer on Si1−xGex channel for high mobility Si/Si1−xGex CMOS application
We demonstrate a technique for selective GeO<sub>x</sub>-scavenging which creates a GeO<sub>x</sub>-free IL on Si<sub>1-x</sub>Ge<sub>x</sub> substrates. This process reduces N<sub>it</sub> by >60% to 2e11 and increases high-field mobility at N<sub>inv</sub>=1e13 cm<sup>-2</sup> by ~1.3× in Si<sub>0.6</sub>Ge<sub>0.4</sub> pFETs with sub-nm EOT.
5.63 and 5.80 MeV levels of Ne20; de-excitation branching
Abstract The ratio Г γ /Г for the 5.63 and 5.80 MeV levels of Ne 20 has been determined to be 0.077 (±0.008) and −4 , respectively, by using the C 12 (C 12 , α)Ne 20 reaction and determining the fraction of the events in which the alpha-particle and the Ne 20 recoil are present in coincidence at the kinematically correct angles. In both cases these results in themselves are shown to imply radiative E1 transition (5.63→1.63 and 5.80→0, respectively) probabilities ⪡5 × 10 −5 Weisskopf units. When taken together with the life-time for the 5.63 MeV level measured by Evans et al . values of Г( E1 ) ≲ 5 × 10 −6 and Г α ≈ 6% of the particle estimate are obtained for this state.