The Comparative Study to Enhance Board Level Reliability Performance of Wafer Level Package At 0.25 mm Pitch Using Micro-Ball Drop and Electroplated Solder Technology
In this study, the board level reliability of WLP at 0.25mm pitch has been evaluated by employing board level reliability test following JEDEC include thermal cycling, drop shock and cyclic 4-point bend tests to verify the performance of shrunk bump size. The WLP test vehicle has been designed with 4-layer stack up structure, 4.0 × 4.0 mm die size and 15 × 15 ball array. The shrunk bumps of test vehicles were formed by using micro-ball drop and electroplated lead free solder bumping process after UBM plating completed. The shrunk bump size in WLP at 0.25mm ball pitch will enhance the risk of board level solder joint fatigue due to lower standoff height and smaller diameter of solder joint (higher bump stress concentration). In this work, we also evaluated different 4-layer WLP stack up structures for key design parameters including polyimide, RDL and UBM layers to reduce solder joint stress and thus enhance BLR performance All the study legs passed drop test with the 1st fail >100 drops and passed 200K times cyclic bend test without any failure. The TCT performance of micro-ball drop bumped legs showed better results with 1st fail passed 500X cycles. The drop, bend test and TCT performance are improved by new bump stack-up designs.
Studying the Effect of Stackup Structure of Large Die Size Fan-In Wafer Level Package at 0.35 mm Pitch With Varying Ball Alloy to Enhance Board Level Reliability Performance
In this study a four-layer fan-in wafer level package (WLP) structure (two passivation layers, one redistribution metal layer (RDL) and one under bump metallurgy layer (UBM) with die size 8 × 8 mm2 and ball pitch 0.35 mm is used for board level reliability (BLR) evaluation. The solder joint stress during BLR tests are highly related to the structure and solder ball alloy used in WLP bumping process based on simulation input. In this work, we evaluated different WLP structures with different stackup thickness including passivation layers, RDL layer, UBM layer and different solder ball alloy to reduce solder joint stress and thus enhance BLR performance. Besides, the impact of different die thickness post wafer grinding process was also included. All the different WLP structures have been evaluated by employing board level reliability test following JEDEC include thermal cycling test, drop test and cyclic 4-point bend test. From this work, an improved fan-in WLP stackup structure was demonstrated to pass board level TCT 500 cycles (include both corner chain balls/non-corner chain balls), drop test 150 times and cyclic bend test 200,000 cycles without any failure for 8× 8 mm2 die size at 0.35 mm pitch with doped SAC405 alloy.
Stability of planar PEMFC in Printed Circuit Board technology
Abstract The use of planar PEMFCs in printed circuit board (PCB) technology with a thickness of less than 3.5 mm are presented. This planar design consists of an open cathode side which allows a completely passive, self-breathing operation of the fuel cell. Power densities of 100 mW/cm 2 at 500 mV with hydrogen as a fuel were achieved. A steady operation with this type of fuel cell was demonstrated over a week without any cell flooding. Since the electrical conducting elements of PCBs usually are made of copper, corrosion in the wet environment of a PEMFC is expected. Thus, a significant degradation in performance of fuel cells made of plain copper PCBs was seen in long-term operation. In order to avoid corrosion, the copper layer has to be coated. Fuel cells in PCB design with diverse coatings were tested in long-term operations up to 1000 h under load. Moreover, corrosion currents have been determined by the use of potentiodynamic scans. Promising coatings are electroplated Cr and Ni and a combination of Ni/Au.