A combined IEEE half and single precision floating point multipliers for deep learning
In deep learning, single precision floating point multipliers are widely used and the most power-hungry arithmetic operators. However, although multipliers are power intensive, they are necessary for applications that require multiplication. In this paper, we propose a novel combined IEEE half precision and single precision floating point multipliers for deep learning. Our design can be easily configured to run in the half precision mode for power saving or in the single precision mode for accuracy. Compared to conventional IEEE single precision multipliers, the combined multipliers require only a small amount of additional area and delay, while offer a significant reduction in power dissipation.
Half-Precision Floating-Point Multiplier IP Core Based on 130 Nm CMOS ASIC Technology
Internet of things applications demand reusable modular designs with low-power consumption. Furthermore, many emerging applications, such as image recognition using machine learning, are low-accuracy tolerant. For these applications, the IEEE-754 half-precision arithmetic is becoming a relevant option for low-power, low-computational cost designs. This article presents a half-precision floating-point multiplier. It is implemented on 130 nm CMOS ASIC technology. The proposed multiplier IP core exhibits low-power consumption, small silicon area, and its accuracy is IEEE-754 compliant.
Simplified impedance design and control for low-cost high-speed channels
Impedance design is the fundamentals of signal integrity at the very beginning, but controlled impedance is always costly or time-consuming for the high-speed channels. In this paper, many simulations of channel parasitics were taken and calculated that met with the specified impedances and correlated to the measurements very well. Selection of the different substrate stack-up without any layout modification in the BGA package reversed from the failed verification to pass the differential return loss. Adjustment of lead widths and spaces in the limited room of leadframe package improved 6 Ω of differential-mode impedance compared to the conventional leadframe packages. The differential pairs with wider traces routed on the 2-layer PCB are more robust for over-etching effects whose impedance errors are less than 5% without special impedance control. Moreover, those pairs inserted with a thin ground trace achieved 90 Ω differential-mode impedance and 28.2 Ω common-mode impedance simultaneously with 35% less routing area for MHL application and reserved a 10 Ω series resistor for ESD protection. With those diligent designs, the leadframe package and the 2-layer PCB can be still adopting in the consumer electronics for high-speed applications.