Analysis of oxide bulk trapped charge distribution and densities from photo injection characteristics of oxide-nitride-oxide (ONO) structures
The thickness of ONO inter-poly dielectrics dominates the program and erase speed of a flash memory cell transistor with a stack gate structure. Therefore, as flash devices shrink, it is important to prevent the degradation in reliability while scaling down the thickness of the oxide. However, the thickness of the bottom oxide formed on a heavily doped poly-silicon cannot be easily reduced because of its high defect density due to a high concentration of dopants in the floating gate and an enhancement of the oxide thickness caused by oxidation of the doped polysilicon [1]. In order to overcome these problems, advanced LPCVD technology has been introduced, but the LPCVD oxide films still have many defect densities in comparison with thermal oxide films. In this work, the bulk trapped charges distribution and density in the bottom LPCVD oxide were quantitatively investigated by photocurrent-voltage characteristics. In addition, we found that the defect density and distribution in the bottom LPCVD oxide were remarkably decreased using post plasma oxidation.
Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices
This paper describes the scaling limitation factors of ONO interpoly dielectric thickness, mainly considering the charge retention capability and threshold voltage stability for nonvolatile memory cell transistors with a stacked-gate structure, based on experimental results. For good intrinsic charge retention capability, either the top- or bottom-oxide thickness should be greater than around 6 nm. On the other hand, a thicker top oxide structure is preferable to minimize degradation due to defects. It has been confirmed that a 3.2 nm bottom-oxide shows detectable threshold voltage instability, but 4 nm does not. Effective oxide thickness scaling down to around 13 nm should be possible for flash memory devices with a quarter-micron design rule.
Ultrathin Wafer Pre-Assembly and Assembly Process Technologies: A Review
Ultrathin silicon wafer technology is reviewed in terms of the semiconductor applications, critical challenges, and wafer pre-assembly and assembly process technologies and their underlying mechanisms. Mechanical backgrinding has been the standard process for wafer thinning in the semiconductor industry owing to its low cost and productivity. As the thickness requirement of wafers is reduced to below 100 μm, many challenges are being faced due to wafer/die bow, mechanical strength, wafer handling, total thickness variation (TTV), dicing, and packaging assembly. Various ultrathin wafer processing and assembly technologies have been developed to address these challenges. These include wafer carrier systems to handle ultrathin wafers; backgrinding subsurface damage and surface roughness reduction, and post-grinding treatment to increase wafer/die strength; improved wafer carrier flatness and backgrinding auto-TTV control to improve TTV; wafer dicing technologies to reduce die sidewall damage to increase die strength; and assembly methods for die pick-up, die transfer, die attachment, and wire bonding. Where applicable, current process issues and limitations, and future work needed are highlighted.