Back-side De-processing using CMP for bulk silicon 40-nm graphics processors
A back-side de-processing process by chemical mechanical polishing (CMP) is developed. The process has been optimized to produce repeatable results. The process is capable of exposing the circuitry of the die uniformly and is able to target more than one area for units with multiple defect locations; front-side de-processing process has difficulty achieving the same results due to the unevenness of the die
Effects of Mechanical Parameters on CMP Characteristics Analyzed by Two-Dimensional Frictional-Force Measurement
The effects of mechanical parameters on the characteristics of chemical mechanical polishing ~CMP! were evaluated by directly measuring frictional force acting on a wafer in terms of two components, i.e., the tangential and axial components of the platen’s rotation. It was found that, when the platen and the wafer were rotated at the same speed, the tangential component of the frictional force was dominant. Also, frictional force was in linear proportion with removal rate. Though frictional force increased in linear proportion to down force when mechanical-effect-dominant CMP for silicon ~Si! or silicon dioxide (SiO2) was carried out, it decreased gradually as platen rotational speed was increased. Copper ~Cu! polishing using abrasive-free polishing solutions, a typical example of chemical-effect-dominant CMP, showed much more complex behavior. Namely, dependence of frictional force on down force and on platen rotational speed showed nonlinear characteristics. Even when a nonlinear characteristic slurry was used, it was found that removal rate and frictional force were almost linearly correlated. It can thus be considered that frictional force is a basic parameter to determine CMP characteristics. From these results, an experimental equation was proposed to describe CMP characteristics by modifying Preston’s empirical equation.
Reliability issues and advanced failure analysis deprocessing techniques for copper/low-k technology
With technology continually scaling down, Cu/low-k technology has been introduced to reduce interconnect resistance, improve electromigration resistance and reduce cross talk effects. In this paper, we discuss new failure modes, reliability issues and failure analysis (FA) challenges for copper technology. Several FA deprocessing techniques are discussed: wet chemical etching, reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP) and a combination of these techniques. Specific details are given of RIE process characterization and optimization for several inter-level dielectrics to attain high etch selectivity, free of RIE grass. We find the combination of CMP and RIE deprocessing techniques works well in most situations for copper technologies. Cross-section analysis of copper devices is also discussed. The development of reproducible backside silicon sample preparation techniques has become increasingly important to accurately localize defects for Cu/low-k technology. Several backside sample preparation techniques are described including mechanical milling, RIE and wet chemical etching. Finally, some FA case studies of Cu/low-k devices are presented.