Effects of package and mold cavity structures on the wire sweep behavior during package array transfer molding
In order to maximize product throughput, an increasing number of electronic packages, such as Small Outline Transistor (SOT) package, are manufactured in a package array mold. Due to the complicated structure design of the package and mold cavity, wire sweep is becoming an increasingly severe problem. In this study, the numerical model which had been validated by experimental work was used for wire sweep analysis. Firstly, the leadframe structure was studied. Given the thin thickness of leadframe and the relative position to the bond wire loop, the leadframe structure has very limited influence on the wire sweep value. Besides, for fixed width and length of the die, the wire sweep behavior was simulated to examine the influence of the die height (thickness). The results show that the thinner the die, the smaller the wire sweep. Furthermore, the effect of cavity height on wire sweep value was also estimated. Based on the previous simulation and analyses, the ratio of the die height to that of the cavity was introduced as an index to optimize the flow pattern of epoxy molding compound (EMC) in order to find a guideline for package and cavity design to avoid the wire sweep issue. In addition, the influence of injection velocity and viscosity of EMC on wire sweep during transfer molding process were inspected and discussed according to the simulation results as well. It can be further concluded that the velocity plays the key role in resulting in the severe wire sweep in package array mold during transfer molding process.
Rheological characterization and full 3D mold flow simulation in multi-die stack CSP of chip array packaging
According as high density packaging options such as 2 or more die stacking or package stacking technologies are developed, the major mold process related quality concerns such as incomplete mold, exposed wires and wire sweeping are increased because of their narrow spaces between die top and mold surface and increased wiring density. So, to verify those concerns, full 3D rheokinetic simulation of mold flow has been investigated for 3 die stacking structure of 4 times 4 mold array, 294LD case. The rheological parameters of commercial epoxy molding compound (EMC) were acquired through the slit-die rheometer and DSC (differential scanning calorie-meter) analysis. It is found that the severe void problem is one of the challenging factors in the thin and multi-die stack packaging to determine its manufacturability. To investigate the effect of different gate types, the molding options with four different gates were evaluated. The center gate showed most severe voids but corner gate showed relatively better void performance. But in case of the wire sweeping experiment and prediction results, the center gate type had less wire sweeping than the corner gate type. In the rheological simulation results, the corner gate case indicated increased velocity, shear stress and mold pressure near to the gate inlet and final filling zone. The experimental case study and the mold filling simulation showed good match on the mold external void and wire sweeping related prediction
Failure analysis for poor solderability of Au surface of PCB
Nonwetting is one of the common problems and is always rejected in electronic assemblies. ENIG pads of a PCBA exhibited nonwetting after lead-free reflow soldering. With the aid of stereomicroscope, SEM&EDS and XRF, a series of analysis was performed. And after visual inspection, surface and cross section analysis, thickness measurement and solderability test, it can be inferred that oxidation of plating surface was the main reason for nonwetting, and corrosion in Ni plating caused an adverse impact on solderalibity.