Three dimensional packaging and interconnecting techniques for microwave modules
Three dimensional (3D) packaging and interconnecting techniques can greatly reduce the weight and volume of conventional planar microwave modules. The objective of this study was to employ a novel 3D structure with simple manufacturing process to develop 3D microwave modules. Many advanced 3D packaging and interconnecting methods, such as LTCC microwave multichip modules, vertical interconnects, and 3D electromagnetic field analyzing and optimizing, were applied to increase the package density and improve the electric performance. Test method and test results of 3D microwave modules were introduced. These techniques are very useful to many types of modern active phased array radar systems and communication systems.
Advanced interconnecting techniques of integrated T/R modules
The basic requirements for transmit/receive(T/R) modules of active phased array radar systems are small volume and light weight with excellent microwave performance and uniformity. The objective of this study was to employ new interconnecting techniques to develop high density, integrated T/R modules. Many advanced interconnecting methods were applied to increase the package density and improve the electric performance. High density, integrated T/R modules with good microwave performance and uniformity were manufactured successfully. These techniques are very useful to many types of modern active phased array radar systems.
Precision flip-chip solder bump interconnects for optical packaging
Solder bump flip chip technology is particularly well suited to the packaging of classes of devices, such as fine pitch LED (light emitting diode) array electrophotographic print heads, which place premiums on precision alignment, high electric interconnect density, close die placement, and low cost. The manufacturing feasibility of such an array was investigated, with particular emphasis on the quality of surface tension induced self-alignment associated with solder bump bonding. An array of LED diode array chips was fabricated employing 75 mu -dia. solder bumps on 156 mu m pitch. The chips were spaced 15 mu edge-to-edge, face down, on a glass substrate patterned with thin film metallization. Chip-to-substrate alignment errors in the X-Y plane were found to be under 1.5 mu m with a standard deviation of under 1.0 mu m, well below the 10-15 mu m error typical of the standard mechanical alignment method. Improvements in light output uniformity and a reduction in scattered light over arrays manufactured with conventional die placement and wire bonding were also observed.<<ETX>>