SOI pixel detector based on CMOS time-compression charge-injection
Concept and experimental results obtained from a pixel detector based on CMOS time-compression charge- injection-devices (TC-CID) with a huge internal photocurrent amplification (-104), fabricated in CMOS silicon-on-insulator (SOI) technology are presented. Here, the readout circuitry is fabricated on highly-doped, 200 nm thick SOI film, while the photogate (PG) detector is fabricated on higher-resistivity handle wafer. The latter, together with the 30 V biasing possibilities enhances the quantum efficiency, especially for irradiations with wavelengths in the near-infra-red (NIR) part of the spectra.
Analog CMOS peak detect and hold circuits. Part 2. The two-phase offset-free and derandomizing configuration
An analog CMOS peak detect and hold (PDH) circuit, which combines high speed and accuracy, rail-to-rail sensing and driving, low power, and buffering is presented. It is based on a configuration that cancels the major error sources of the classical CMOS PDH, including offset and common mode gain, by re-using the same amplifier for tracking, peak sensing, and output buffering. By virtue of its high absolute accuracy, two or more PDHs can be used in parallel to serve as a data-driven analog memory for derandomization. The first experimental results on the new peak detector and derandomizer (PDD) circuit, fabricated in 0.35mm CMOS technology, include a 0.2% absolute accuracy for pulses with 500 ns peaking time, 2.7 V linear input range, 3.3 mW power dissipation, 250 mV/s droop rate, and negligible dead time. The use of such a high performance analog PDD can greatly relax the requirements on the digitization in multi-channel systems. r 2002 Elsevier Science B.V. All rights reserved.
A pulse processing station
This is the first of two papers concerning the architecture, circuitry design and performance of a pulse processing system based on a digital signal processor. This multifunction system, implemented as a single PC module, incorporates a high performance 16-bit Pulse Height Analyser (PHA) a Multichannel Scaler (MCS), a Digital Oscilloscope (DSO) and also a Digital Pulse Processor (DPP). This paper presents the PHA architecture with emphasis on the baseline restorer and peak stretcher circuits. Differential nonlinearities (DNL) are corrected by a new implementation of the sliding scale technique and performance ranges from better than 2% (at 16-bit resolution) up to less than 0.2% for 12-bit operation. The DNL correction technique is assessed for different sliding-scale ranges.