HBM ESD EDA check method applied to complete smart power IC's — Functional initialization and implementation
A functional approach to check global IC ESD schematic network correctness and protected circuitry ESD compliance using Calibre® Mentor PERC is presented and applied to Smart Power IC product. Developed checker exploits an initialization method able to accurately define ESD paths. The project follows ESD Association EDA International Working Group guidelines.
An ESD design automation framework and tool flow for nano-scale CMOS technologies
We present a successfully implemented ESD design automation framework that evaluates and verifies the ESD protection methodology at all stages of a standard integrated circuit design flow. The tools used at each step of the flow and sample results showing excellent correlation to hardware test data is presented.
Solutions to mitigate parasitic NPN bipolar action in high voltage analog technologies
This is a study of the parasitic NPN premature turn-on for high voltage BiCMOS technologies. In this work, we will investigate several methods to suppress its turn-on. Using TCAD and TLP we will investigate solutions based on increased well spacing, offset of wells, self-protection and beta reduction through highly doped base implant. We will also investigate the limitations associated with each of these solutions.