Analyze of temporal and random variability of a 45nm SOI SRAM cell
This paper presents the analysis of a 45nm SOI SRAM cell variability including history effects and random variability. This leads to an accurate margin calculation.
Physical IP for SOI design infrastructure
ASIC design is today achieved by mixing different physical IP blocks including standard cells, memory compilers, IO and analog blocks when needed. The circuits are designed using a given EDA flow, starting from high-level functional description (RTL netlist) and going down to the physical implementation. This process involves logical synthesis to achieve the required functionality, timing analysis, power analysis and area optimization performed before and after routing of the different blocks. This process has become quite complex and necessitates many iterations to reach the expected result in term of speed, power consumption and area. As SOI processes become more popular and are now considered for use in ASIC beyond the traditional use for CPU, it has become crucial to put in place the corresponding physical IP libraries.
Circuit Performance Optimization in Advanced PD-SOI CMOS Development
Device optimization on partially-depleted silicon-on-insulator (PD-SOI) CMOS is systematically performed in terms of circuit switching speed and power consumption. The effects of several key factors, such as threshold voltage (Vth), pre-amorphization implantation (PAI), and silicon film thickness (Tsi), are fully investigated and optimized to achieve optimal ring-oscillator performance. We found that well-designed PAI improves circuit delay vs. leakage characteristics, while decreasing Tsi also reduces the propagation delay. We then present the optimized AC performance for a variety of circuits, as well as the DC performance, the SRAM characteristics, and the reliability assessment.