A combined IEEE half and single precision floating point multipliers for deep learning
In deep learning, single precision floating point multipliers are widely used and the most power-hungry arithmetic operators. However, although multipliers are power intensive, they are necessary for applications that require multiplication. In this paper, we propose a novel combined IEEE half precision and single precision floating point multipliers for deep learning. Our design can be easily configured to run in the half precision mode for power saving or in the single precision mode for accuracy. Compared to conventional IEEE single precision multipliers, the combined multipliers require only a small amount of additional area and delay, while offer a significant reduction in power dissipation.
Dual-mode double precision / two-parallel single precision floating point multiplier architecture
Floating point multiplication is an integral part of any contemporary computing system. This paper presents a configurable dual-mode double precision floating point multiplier architecture, which can also process two-parallel single precision multiplication. This unified, double precision dual (two-parallel) single precision, architecture is named as DPdSP multiplier. The proposed architecture is based on the standard state-of-the-art flow of floating point multiplication, which can process normal and sub-normal operands along with exceptional case handling. The proposed architecture is aimed for a ASIC (UMC 90nm) implementation. The key single-mode design units in the computational flow (like mantissa multiplier, dynamic right/left shifters, leading one detector, etc) are re-designed for configurable dual-mode operation to enable efficient resource sharing. The proposed architecture is compared with the best available literature in terms of area, period and area × period / throughput complexity metric. The proposed dual mode architecture shows a significant improvement in design metrics and also provides more computation support.
Frequency selective surface design for blinds applications
In this paper, the reconfigurable blind structure with frequency selective surfaces(FSS) for the building applications are presented. Frequency transmission characteristics for different angles of the proposed blind-FSSs are investigated and verified through simulation and measurement. The simulation results show that we can implement the reconfigurable blind-FSS for multiband wireless applications. To verify the proposed paper, two kinds of blind-FSSs, crossed dipole FSS and circular ring FSS are fabricated and measurements are performed for different angles. The proposed structure in this paper which is very simple, can be easily applied to any planar surface for wireless security applications at low cost.