Scalable, sub 2μm pitch, Cu/SiCN to Cu/SiCN hybrid wafer-to-wafer bonding technology
This paper presents a novel approach to face-to-face wafer-to-wafer (W2W) bonding using SiCN-to-SiCN dielectric bonding, in combination with direct Cu-Cu bonding using Cu pads of unequal size and surface topography for the top and bottom wafers. The use of SiCN dielectrics allows to obtain a high W2W bonding energy (> 2 J/m2) at low annealing temperature (250 °C). Excellent Cu-Cu bonding is obtained after annealing at 350 °C. A novel CMP process, resulting in a slightly protruding Cu top pad and a slightly recessed Cu bottom pad, is introduced. The difference in pad sizes, allows for the necessary W2W overlay bonding tolerances. Excellent resistivity and yield results are obtained across bonded 300 mm Si wafers for scaled 360 nm top pads bonded to 720 nm bottom pads at 1.44 μm pitch (25% bottom Cu density). Feasibility of smaller pitches has been demonstrated by successfully bonding 180 nm top pads to 540 nm bottom pads at 0.72 μm pitch.
The 3-D Interconnect Technology Landscape
This overview article sheds light into the diverse notions and terms associated with 3-D circuits. It categorizes and classifies the various technologies/techniques and helps the experienced researcher as well as a newcomer to find an orientation in the complex 3-D landscape.
Vertical device architecture for 5nm and beyond: Device & circuit implications
Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we compared the performance, layout efficiency, SRAM design, and parasitics between vertical (VFETs) gate-all-around (GAA) transistors with lateral (LFETs) targeting 5nm. We reviewed some of the unique considerations of VFET device and circuit influences.