Scalable, sub 2μm pitch, Cu/SiCN to Cu/SiCN hybrid wafer-to-wafer bonding technology
This paper presents a novel approach to face-to-face wafer-to-wafer (W2W) bonding using SiCN-to-SiCN dielectric bonding, in combination with direct Cu-Cu bonding using Cu pads of unequal size and surface topography for the top and bottom wafers. The use of SiCN dielectrics allows to obtain a high W2W bonding energy (> 2 J/m2) at low annealing temperature (250 °C). Excellent Cu-Cu bonding is obtained after annealing at 350 °C. A novel CMP process, resulting in a slightly protruding Cu top pad and a slightly recessed Cu bottom pad, is introduced. The difference in pad sizes, allows for the necessary W2W overlay bonding tolerances. Excellent resistivity and yield results are obtained across bonded 300 mm Si wafers for scaled 360 nm top pads bonded to 720 nm bottom pads at 1.44 μm pitch (25% bottom Cu density). Feasibility of smaller pitches has been demonstrated by successfully bonding 180 nm top pads to 540 nm bottom pads at 0.72 μm pitch.
Fine pitch 3D interconnections with hybrid bonding technology: From process robustness to reliability
This paper presents the description of direct hybrid bonding technology for the fabrication of vertical interconnects thanks to wafer-to-wafer bonding. Process robustness is analyzed through morphological and electrical results. The electrical characterizations are discussed versus hybrid bonding pad dimensions and pitches. Electromigration study is carried out on different test vehicles with hybrid bonding interconnect dimensions below 5 μm. Experimental tests provide the parameters for lifetime extrapolation and show that the hybrid bonding module is immune to electromigration failures. Finally perspectives and key challenges for 3D interconnects scalability are given.
Small Pitch, High Aspect Ratio Via-Last TSV Module
Current TSV integration schemes include via-first, via-middle and via-last process flows. In this paper, a low thermal budget, 10ìm pitch and aspect ratio 10 (5ìm diameter, 50ìm depth) via-last TSV module is presented. The proposed via-last module is plugged in after the thinning module, with 50ìm thinned device wafers temporary bonded to a Si carrier, using Brewer Science Zonebond® material. After the deposition of a thin back side passivation layer, the TSV lithography is performed with back-to-front alignment to the front side Metal1 pattern using a Dual Side Alignment (DSA) system, available on the Ultratech AP300. The overlay performance to Metal1, verified by dedicated software utilizing the DSA alignment system, is better than 750nm, fulfilling the requirements for a 5ìm diameter by 50ìm depth TSV module with a TSV pitch of 10ìm. The TSV deep-Si etch lands on the STI/PMD oxide stack. In order to prevent severe notching at the silicon to oxide interface, a soft landing etch step is introduced by tuning the etch process parameters. The soft landing accommodates as well for the total silicon thickness variation of the thinned wafers. Prior to the TSV resist strip, the STI and PMD oxide is etched, stopping just above the Metal1 landing pads. Next, a high conformal PEALD oxide liner is deposited at low temperature, avoiding local deformation of the thermoplastic temporary glue material. In order to enable electrical contact from the TSV to the Metal1 landing pads, the liner oxide is selectively removed at the bottom of the TSV by means of a directional dry etch step. To avoid any liner oxide recess at the top of the TSV, the liner is protected with a non-conformal PECVD low temperature SiN layer. This SiN layer deposits at the top part of the TSV, capping the oxide liner, but doesn't deposit deeper into the TSV. As a result, the oxide liner is cleared at the TSV bottom during the oxide liner etch, at the same time preserving this oxide liner at the top of the TSV which is protected by the PECVD SiN capping layer. Prior to the PVD Ta barrier deposition, a dedicated argon soft sputter etch with high RF bias power is applied to ensure the complete removal of any tantalum oxide interfacial layer. The PVD Cu seed is deposited in-situ with the barrier. ECD copper fill and CMP of the Cu overburden and Ta barrier material finishes the via-last module. Backside RDL, using a semi-additive process, provides the electrical contact to the TSV at the thinned wafer back side. Electrical results are shown, proving the maturity of this TSV last process scheme. The connectivity of the TSV, from wafer front to back side, has been checked by means of kelvin and daisy chain structures, showing 100% yield and low spread on the measured resistance values. Low leakage current and high breakdown voltage of the TSVs is obtained, demonstrating the integrity of the oxide liner all over the TSV sidewall.