A 7000-gate microprocessor on SOS&#8212;PULCE
An n-channel MOS LSI microprocessor integrating 20 000 transistors on a chip has been realized on a sapphire substrate utilizing the Coplanar-II process. It contains ALU, shifters, and 44 registers which are combined to three 16-bit buses. By utilizing three types of threshold voltage for load transistors, 28-percent reduction in power dissipation is achieved. The minimum cycle time is 200 ns. By using the Coplanar-II process, anomalous leakage currents due to parasitic transistors at the sides of island are suppressed. It is found that the silicon-on-sapphire (SOS) version operates 2.3 times faster than the bulk-silicon version, which is mainly explained by the parasitic capacitance ratio. Parallel-plate approximation in calculating a wiring capacitance results in an underestimate by a factor of 60 compared with taking the two-dimensional effect into account. It is verified that a) the observed yield of a very large SOS chip is higher than the value predicted from a randomly distributed defects model, and b) the yield-sensitive active area of an SOS is so small that it can compensate for the yield degradation due to the very large defects density on an SOS wafer.
Development of a high-performance universal computing element - PULCE
Since the first introduction of the microprocessor, various kinds of microprocessors have been developed. There have been remarkable achievements both in the level of integration and processing speed. However, most microprocessors develqped to date are oriented to device control applications or low class minicomputer replacement. It is true that some bit-sliced microprocessors can operate at very high speeds, but they are neither one-chip, nor do they have much functional capability. On the other hand, with the current state of the art in semiconductor technology, it seems possible to integrate considerable amounts of computing power in a chip and at the same time to achieve high speed operation comparable to existing discrete processors. The Electrotechnical Laboratory and Tokyo Shibaura Electric Co. (Toshiba) R&D center are engaged in a research effort in this area and have developed a new high-performance universal computing element-PULCE. This paper describes its architectural design, 1,2 as well as the semiconductor technology develped for its implementation.
A Short-Term and High-Resolution Distribution System Load Forecasting Approach Using Support Vector Regression With Hybrid Parameters Optimization
This paper proposes an approach for distribution system load forecasting, which aims to provide highly accurate short-term load forecasting with high resolution utilizing a support vector regression (SVR) based forecaster and a two-step hybrid parameters optimization method. Specifically, because the load profiles in distribution systems contain abrupt deviations, a data normalization is designed as the pretreatment for the collected historical load data. Then an SVR model is trained by the load data to forecast the future load. For better performance of SVR, a two-step hybrid optimization algorithm is proposed to determine the best parameters. In the first step of the hybrid optimization algorithm, a designed grid traverse algorithm (GTA) is used to narrow the parameters searching area from a global to local space. In the second step, based on the result of the GTA, particle swarm optimization is used to determine the best parameters in the local parameter space. After the best parameters are determined, the SVR model is used to forecast the short-term load deviation in the distribution system. The performance of the proposed approach is compared to some classic methods in later sections of this paper.