The importance of testing complex electronics
The increasing functionality of modern electronics systems is being achieved through more complex integrated circuits, dense surface mount assemblies and increasingly through the use of multiple complex ICs interconnected to form multi-chip modules, all of which have progressively increased the cost of testing and its share of production cost, so that test costs are dominant today. Initiatives taken in Europe by leading corporations and recently adopted as IEEE standards for logic circuit testability, are now enabling electronic access for in-circuit testing and diagnostics at IC and board and MCM level, thereby improving quality and throughput in the manufacture of electronics. various proprietary solutions are also being introduced very effectively for analogue circuits, and for specialised computing and telecommunications systems, some using expert systems to aid diagnostics and improving the quality and throughput of testing. The solutions are most cost-effectively introduced at the design stage when maximum impact can be achieved on subsequent life-cycle costs.
Cutting the high cost of testing
A modeling approach to the overly long testing of analog and mixed-signal devices that saves substantially on time and cost is described. The discussion focuses on the particular case of a 13 bit analog-to-digital converter (ADC). The problems that arise in testing ADCs are identified, showing that the success of the test method depends critically on the quality of the model. Two types of models are examined, physical-sensitivity-based models and empirical-learning-based models, and it is noted that the latter are especially attractive for performance-testing applications like the ADC example. An 18-parameter model of the 13 bit ADC was developed using a combination of physical and empirical modeling techniques and was highly successful. With an array process to speed up the computations, the computational overhead can be kept below 1 s per device, so the test time, which is reduced by a factor of 128, becomes negligible.<<ETX>>
Electronic Chip-In-Place Test
Electronic Chip-in-Place Test (ECIPT) is a design approach and a test methodology for VLSI packages containing multiple semi-conductor chips. Shift register latches are used in such a way that each chip on a package is accessible for testing from the package pins without in-circuit probing. A means is therefore provided, whereby tests generated for a chip can be reapplied at the package level. The ECIPT methodology additionally provides a mechanism for simplified tests of failures associated with interchip wiring and chip I/O connections.