HBM ESD EDA check method applied to complete smart power IC's — Functional initialization and implementation
A functional approach to check global IC ESD schematic network correctness and protected circuitry ESD compliance using Calibre® Mentor PERC is presented and applied to Smart Power IC product. Developed checker exploits an initialization method able to accurately define ESD paths. The project follows ESD Association EDA International Working Group guidelines.
Hierarchical verification of chip-level ESD design rules
Verification of net-oriented ESD rules is rapidly becoming critical for nanometer design. To meet chip-level complexity and size challenges, a novel approach using topology-aware net types is developed to enable fast, hierarchical verification. This is applied to ESD design rules for power/ground interfaces and successfully adopted in production verification flows.
The Invariance of the Vacuum is the Invariance of the World
The following theorem is demonstrated: If the vacuum is invariant under the group generated by the space integral of the time component of a local vector current, then the Hamiltonian is invariant also. A similar theorem holds for the group generated by the space integral of a space component of a local axial-vector current.