Novel Flip Chip Technologies for Ultra Thin Chip
Telecommunication equipment that supports high-level information networks is being made portable, small and lightweight. Thus, the miniaturization of semiconductor devices is necessary, and chip thinning and flip chip technologies are key in achieving it. The typical flip chip manufacturing steps for thin semiconductor devices are as follows. First, semiconductor elements are formed on a wafer. Surface protective tape is attached to the surface of the wafer and backside grinding is performed to make the wafer thin. Then, dicing tape is attached to the backside of the wafer and the wafer is diced from the surface side, using a diamond blade, and divided into chips. Then, the chips are picked up, using pick up needles and bumps are formed on the surface of the chip. Next, seal resin is attached to a substrate, then the surface of the chip is attached to the substrate with the seal resin and flip chip interconnection and sealing are performed to mount the chip. This manufacturing step has some problems. In this paper, a novel thin package manufacturing process is described.
Study on a novel bond head with proportional electromagnet in chip operation
This paper presents the electromagnetic model and the experimental results of a novel bond head for chip operation. The existing bond head with spring or mechanical connection is difficult to achieve the purpose of protecting chips. The pneumatic bond head can't timely feedback the force signal to control system. To increase the effective and safety of the die bonding, a bond head with the very fast response and steady bonding force is required. A constant-force bond head with proportion electromagnet is proposed. The magnetic force is studied using a FEM electromagnetic field model, and the structure parameters of bond head are optimized. A design is created that achieves a force error range of 1% in 0.3mm displacement. A prototype of the designed bond head is built. The bonding force measurements and system response time are tested to check the stability. The test results show that the calculated magnetic force agreed fairly well with the measured results, and the force error range of 1% is achieved.
Determination of silicon die strength
The purposes of this study are two folds: one is to attempt to develop a new, suitable test method for differentiating the factors that affect the variability of die strength, and the other is to investigate the failure and fatigue strength of silicon dies. In this study, a new test method, a plate-on-elastic-foundation test (PEFT) associated with point-or line-loading has been proposed and evaluated. It is found that the PEFT can provide not only a simple, chipping-free test for dummy or real IC chips without limitation of size, but also a stress field similar to the temperature loading. The test data obtained from the current test are presented for those failed on IC and ground surfaces in real IC chips. It is found that the good consistency of the die strength data with minor scatter from both the point- and line-load tests for the specimens failed on IC surfaces, but not for the ones failed on the ground surfaces. The reason for this is that the inconsistency of strength data from both tests for failure on ground surfaces is due to edge chipping involved, and the larger scatter is resulted from the combined factors of the angle of grinding marks, planes of weakness of material, and loading stress state. The surface roughness of the dies measured by atomic force microscopy is correlated with the failure mode and strength from the tests. It is found that the silicon die strength is dominated by the roughness on failure surface, and their failure modes always appear along the parallel and normal to the edges of the die, which might be the weak plane of the crystal lattice of silicon. The specimens with artificial cracks have been further tested. It has been proved that the die strength dominated by the crack initiation depends on the most severe defect and its failure mode is controlled by a special weak plane after the crack initiation. This study concludes that there are four factors to influence die strength: the surface conditions of the die (including grinding-line direction and surface roughness), the edge crack of the die (so-called edge chipping created during the cutting process), the weak planes of the crystal lattice of silicon, and, sometimes, the cause from different loading types. The fatigue strength of the dies is also determined to be about 25% lower than static one.