A planar transistor for the 32-nm node and beyond with an ultra-shallow junction fabricated using in-situ doped selective Si epitaxy
Shallower junctions must be formed to make transistors work for the 32-nm node. Many kinds of technologies, such as co-implantation, laser spike annealing (LSA), and flash lamp annealing, have been energetically studied to form ultra-shallow junctions. We focused on in-situ doped selective Si epitaxy, with which the short channel effect and the parasitic resistance can be made compatible. Using this epitaxy, ultra-shallow junctions (with effective junction depths (Xj,eff) under 9 nm@5E18) were formed, and 20-nm or shorter PMOS gate transistors were fabricated using the epitaxy
Overview of the prospects of ultra-rapid thermal process for advanced CMOSFETs
This paper presents ultra shallow junction with low resistance in 45-65nm technology node. Rapid thermal annealing is required to form ultra-shallow, low sheet resistance and lower dislocation density for satisfying the pn junction leakage specification of mobile LSIs. In order to minimize the annealing time at high temperatures, various kinds of ultra-rapid thermal annealing technology such as advanced spike RTA, laser annealing, SPE, flash lamp annealing are compared. Issues of this technology are simultaneously accomplishing ultrashallow Xj, lower sheet resistance and lower crystal damage density for fabricating advanced MOSFETs. By optimizing various process conditions, we can successfully obtain ultra shallow p+/n and n+/p junction of less than 10 nm. In this paper, we overview the prospects for ultra-rapid thermal process for advanced CMOSFETs.
A new 'shift and ratio' method for MOSFET channel-length extraction
A shift-and-ratio method for extracting MOSFET channel length is presented. In this method, channel mobility can be any function of gate voltage, and high source-drain resistance does not affect extraction results. It is shown to yield more accurate and consistent channel lengths for deep-submicrometer CMOS devices at room and low temperatures. It is also found that, for both nFET and pFET, the source-drain resistance is essentially independent of temperature from 300 to 77 K.<<ETX>>