Coding techniques for failure recovery in a distributive modular memory organization
This paper considers various coding techniques which could be applied to a memory organization to achieve detection and correction of failures. In this discussion, we define a fault as a malfunction of a systems component and a failure as a manifestation of a fault. Notice that a single fault can result in multiple failures. Thus, techniques such as error-detecting and correction codes, when used alone, are limited in that they operate on failures---not faults.
A model and implementation of a universal time delay simulator for large digital nets
Although simulation of logic circuits has been attempted in the past, only those which simulate completely combinational circuits have performed with any degree of success for various types of logic. This is primarily due to the number of simplifying assumptions that can be made for combinational circuits. For example, in combinational circuits, one need not consider timing of the signals, since any given input vector will always propagate to a stable state value. Also, since purely combinational circuits do not contain internal states, the user need not define or initialize these values, as must be done (and done meaningfully) for sequential circuits. A systems study of simulation and diagnosis for large digital computing systems has been performed. The results of that study have led to the implementation to be described. The model, which has been adopted, permits the user to select the level of detail most appropriate to his requirements, and thus not hamper him with overly restrictive assumptions. The advantages of this model are the following:
 1. It does not require the specification of feedback loops in sequential circuits.
 2. The ability to reset all feedback lines to any value at any time is not required.
 3. It provides for the detection of hazards and races.
 4. Simulation is not restricted to particular types of circuits.
 5. Besides having the capability of simulating gate level circuits, it can also simulate at a functional level. This results in a savings of time and storage, permitting the simulation of large circuits.
No. 1 ESS switching network frames and circuits
The switching network of no. 1 ESS is a space-separated network employing ferreed switches. The switches are organized into a few basic building blocks or frames from which all network configurations are realized. The frames are autonomous in operation and demonstrate the peripheral bus concept employed in no. 1 ESS. The presence of the high-speed digital processing center in the central office has had a marked effect upon the circuits of the switching network. Path hunting has become a central control task, which has freed the network of its traditional path memory functions. A combination of electronic and electromechanical devices is used to control the ferreed switches. Control duplication assures reliability.