Failure analysis on the standby current due to dislocation in STI structure of flash memory
The technology of increasing Internal Vcc without using memory tester is used to enhance the photon emission and the failure range is defined in detail by nano probing. With these methods, we found out that the leakage current was caused by dislocations of STI arranged in a row.
Application of three-dimensional dislocation dynamics simulation to the STI semiconductor structure
Abstract As the size of semiconductor devices continues to shrink, the control of dislocation nucleation is becoming a severe problem due to high accumulated stress. In this paper, we propose a method to infer the initiation points and slip systems of nucleated dislocations through a combination of TEM observation and dislocation dynamics simulation based on FEM calculation. In order to reproduce the behaviors of dislocations on the nanometer scale, we adopted the core splitting concept first proposed by Brown and employed by Schwarz. We applied our method to a shallow trench isolation (STI) structure. The initiation points and slip systems of four kinds of nucleated dislocations can be detected. It is found that the line tension of the dislocation strongly affects the loop’s final shape, unlike the macroscopic dislocations observed in wafer slip.
Dynamic Imaging of Current Conduction in Dielectric Films by Emission Microscopy
Real time images of the dielectric breakdown were shown in a movie produced by Emission Microscopy. We show that a faint light is emitted during current conduction through dielectric films. Current flows through a large area in an undamaged oxide. Upon breakdown the current flow immediately constricts into a tiny point. Current flow at asperities dances around between multiple asperities. This behavior can be understood as a result of electron trapping and detrapping in the vicinity of poly asperities. Emission Microscopy is the only known technique for viewing current localization at asperities. It is also the most sensitive and the fastest technique for locating oxide defects in VLSI products.