The origin of extended dislocations induced by high-dose ion implantation
The origin and the generation mechanism of ion implantation-induced dislocations is investigated with an Si/sub 3/N/sub 4/ band line/space pattern. The Si/sub 3/N/sub 4/ film-edge stress not only causes dislocation propagation but also causes the formation and deformation of extended dislocations at the initial stage of annealing. The behavior is clarified that the dislocation loops are deformed into pattern-edge dislocation half loops, which accumulate at the film edge and are punched out from the edge.
Si/SiGe heterostructures for advanced microelectronic devices
The permanent size reduction and increasing complexity of microelectronic structures is accompanied by drastic requirements on ultra-thin layer quality. This is the case for Si x Ge1− x ultra-shallow junctions and locally doped nanostructures such as quantum wells, wires or dots. For example, the new generation of Si/Si x Ge1− x -based micro- and optoelectronic devices, e.g. velocity modulation field effect transistor, resonant tunnelling diode, single electron transistor, requires accurate control of surface and interface roughness, almost 0-defect structures and very sharp doping profiles in both p- and n-type material. There exist several difficulties. The first one is the strain control and adjustment (from fully strained to fully relaxed 2D and 3D nanostructures), which also determines the morphological evolution of thin Si1− x Ge x layers and the development of growth instability. The second problem is the doping redistribution during growth, which combines thermodynamics (driving force) and kinetics (exchange rate) mechanisms. The third problem is the 0-defect requirement for ultra-thin doped junctions. In this article, we give an overview of the new insights obtained during the last years in these three domains and we present the physical properties of the structures realised.
Trade-offs in the integration of high performance devices with trench capacitor DRAM
This paper demonstrates it is possible to enhance the device performance of a standard DRAM process by 35% with only a moderate reduction in retention time. We have also merged high-performance logic devices and working DRAM at the cost of an appreciable degradation in retention behavior and a slightly larger cell. The device performance is 1.82/spl times/ the base process. This demonstrates that embedding DRAM in a high-performance technology is feasible although the optimum trade-off between performance, density, retention time, cost, and power depends on the application.