Scalable high performance loop filter architecture for video codecs
There is continuous thrust on improved and innovative video solution to facilitate video conferencing, video surveillance, transcoding, streaming video and many more customer centric new solutions. Increasing frame rate and frame size demands high performance hardware accelerators (HWA) to enable efficient 16×16 pixels macroblock level (MB) pipelining inside video processing engine (IVAHD). Inloop de-blocking filter of H.264 codec reduces blocking artifacts in MB and it is very demanding in terms of cycles and resources (memory access and memory storage). Removal of blocking artifacts due to block-based video codecs takes around 20-25% of overall decoder complexity in current generation of standards (H.264) and trend will continue going forward in H.265. Higher adaptability of filter process, smaller block sizes (4×4), motion vector (MV) dependent boundary strength (BS) computation for each edge of 4×4 block, predefined order for doing filtering (vertical edge followed by horizontal edge) and data pixel loading of current and neighbor MB requires large number of accesses to shared memory of IVAHD (SL2), higher processing cycles and larger internal pixel buffer (IPB). This paper discusses novel approach of loop filter (LPF) operation to overcome above barriers and facilitate IVAHD to go up to 240fps frame rate in full HD processing of H.264 codec with leadership area and power. The final design in 28nm CMOS process is expected to take around 0.10 mm2 after actual place and route (consisting of 220 KGate with 5 KB of internal memory). Proposed design is capable of handling 4K@60fps and scalable to support H.265 inloop de-blocking filter.
Generic transfer scheme for outputting video frame in Ultra-HD video Engine
Typically, industry video solutions does in-loop filtering on-the-fly (e.g. at Macro Block for H.264 or Coding Unit level for HEVC) and transfer YUV data to external memory using DMA engine. These transfers are un-aligned with processing unit (MB/CU) as well as variable sized due to loop filtering operation. This poses challenges in Loop filer and DMA engine on handling of such transfers. This paper proposes concept of “region” to handle such transfers for H.264 and previous generation standard. In case of H.264, the paper proposes division of video frame in to nine regions with common transfer attributes. In case of HEVC, there is additional complexity of TILES (with & without loop filtering) which creates variable numbers of regions in output frame. This paper also proposed flexible & generic scheme to handle output YUV transfers for handling of TILES in HEVC. The updated scheme is flexible enough to encompass previous generation of video standard e.g. H.264 with better performance.
A 242mW, 10mm2 1080p H.264/AVC high profile encoder chip
A 1080 p high profile H.264 encoder is designed by the robust reusable silicon IP methodology and fabricated in a 0.13 mum CMOS technology with an area of 10 mm2 and 242 mW at 145 MHz. Compared to the state-of-the-art design targeted at 720 p baseline, this design reduces 53.4% power and 46.7% area through parallelism enhanced throughput and cross stage sharing pipeline.