Wafer Inspection System: Calibration and Measurement
Wafer surface scanners are widely used in semiconductor industries to detect particle contamination on wafers. The performance characteristics of a PMS SAS-3600 wafer surface scanner have been evaluated using ideal polystyrene latex (PSL). It was also used to measure irregularly shaped silicon particles. Three sizes of PSL spheres (0.199μm, 0.3μm, and 0.426μm) were used to study the sizing accuracy and counting efficiency of this wafer scanner. The results show that this scanner sizes 0.199μm and 0.3μm PSL reasonably accurate. But it cannot size 0.426μm PSL very well. The background noise lever was so high that this scanner could not measure particles near its nominal lower detection limit: 0.1μm. It over-counted Si particles by 28%. An electrostatic enhanced wafer deposition chamber was used to prepare the test wafers. Both the theoretical calculations and experimental results show that electrostatic force increases the deposition velocity by 2 orders of magnitudes for particles smaller than 1μm. The sedimentation is the dominant mechanism for particles larger than 1μm.
Contamination-Free Manufacturing for Semiconductors and Other Precision Products
National Technology Roadmap for Semiconductors - basis and alignment off-wafer measurement of contaminants on-wafer measurement of molecular contaminants transport and deposition of aerosol particles particulate deposition in liquid systems deposition of molecular contaminants in gaseous environments contamination removal from surfaces deposition of metallic contaminants from liquids and their removal sources of contamination and their control.
Ultrathin Wafer Pre-Assembly and Assembly Process Technologies: A Review
Ultrathin silicon wafer technology is reviewed in terms of the semiconductor applications, critical challenges, and wafer pre-assembly and assembly process technologies and their underlying mechanisms. Mechanical backgrinding has been the standard process for wafer thinning in the semiconductor industry owing to its low cost and productivity. As the thickness requirement of wafers is reduced to below 100 μm, many challenges are being faced due to wafer/die bow, mechanical strength, wafer handling, total thickness variation (TTV), dicing, and packaging assembly. Various ultrathin wafer processing and assembly technologies have been developed to address these challenges. These include wafer carrier systems to handle ultrathin wafers; backgrinding subsurface damage and surface roughness reduction, and post-grinding treatment to increase wafer/die strength; improved wafer carrier flatness and backgrinding auto-TTV control to improve TTV; wafer dicing technologies to reduce die sidewall damage to increase die strength; and assembly methods for die pick-up, die transfer, die attachment, and wire bonding. Where applicable, current process issues and limitations, and future work needed are highlighted.