Critical Temperature to Dielectric Degradation of Printed Circuit Board
Dielectric degradation of printed circuit board based on the thermal properties in an open-air environment was investigated. With increase of the temperature, the copper electrodes were oxidized from Cu 2O to CuO; the base material of epoxy laminate was thermally affected to the change of molecular structure and degradation of dielectric properties. With increase of the temperature, the capacitance and surface resistance decreased, the thermal stimulated current increased and showed a valley value near 450 K and a peak value near 490 K
New high-density multilayer technology on PCB
We have developed a new high-density multilayer technology on PCB (Printed Circuit Board), named DSOL (Deposited Substrate On Laminate) technology. The first characteristic of the DSOL technology is the dielectric fabrication, which uses a new photosensitive material, a bulky fluorene unit bonded epoxy acrylate resin. The fluorene based resin has interesting properties such as good electrical properties, low curing temperature (160/spl deg/C) for a heat-resistant resin (glass transition temperature: 230/spl deg/C), low coefficient of thermal expansion (40 ppm), and high resolution. In particular, the dielectric formation process has the advantage that fine and high-aspect-ratio via holes are formed on FR-4 laminates through exactly the same process and manufacturing facilities as a conventional photosensitive epoxy resin. The second characteristic is the technology which patterns fine-pitch copper conductors using a semi-additive process with a sputtering method. This technology makes 40 /spl mu/m pitch lines on large-area laminates possible, as this process consists of flash wet etching of only 0.3 /spl mu/m thick sputtered thin-films. We have successfully developed a high-density packaging substrate for high-pin-count area array ASIC (Application Specific Integrated Circuit) chips (3828 pins). A high-density substrate based on the DSOL technology is the most suitable for achieving high-density packages (MCMs, CSPs, and BGAs) using fine-pitch and area array interconnection technologies.
Embedded capacitors and resistors within Low temperature co-fired ceramics on metal (DiPak) packages for millimeter wave applications
Dielectric Laboratories manufactures a family of ceramic packages that operate to 40+GHz, under the trade name DiPak , In 1996, Sarnoff Research Labs, under a Defense Advanced Research Projects Administration (DARPA) contract chose Dielectric Laboratories Inc. (DLI) to commercialize the manufacturer of ceramic packages using Low Temperature Co-fired Ceramic on Metal (LTCC-M) technology. The transfer of the basic technology from Sarnoff to DLI was completed in 1997. DiPak or LTCC-M is a method for manufacturing multilayer packages using low temperature ceramic tape and low-cost, high-conductivity thick film conductors, co-fired on a metal base. By laminating and firing the tape to the metal core, the shrinkage of the glass-ceramic is limited to the z-direction only. This means that there is zero shrinkage in the x- andy-directions. LTCC-M was developed to overcome (1) three dimensional shrinkage variations that results in fired distortion (2) surface feature location errors and (3) poor thermal conductivity of the glass-ceramic dielectric material, the major limitations of standard high temperature co-fired ceramics (HTCC) and L TCC technologies. Including buried passive components, such as resistors and capacitors, within a multilayer package is an enabling technology in attaining high and efficient circuit densities. The buried components are fabricated using thick film processing, again, lending itself to a low-cost package solution.