A high speed 16 kbit ECL RAM
A 16384 /spl times/ 1 bit ECL RAM (emitter coupled logic random access memory) with an access time of 15 ns and a power dissipation of 700 mW has been developed. The high packing density and performance were achieved by using a p-n-p load cell, a novel ECL circuit, and U-groove isolation. The test results proved that a p-n-p load cell is very effective in producing a fast high-density bipolar RAM having a capacity of over 64 Kbits.
A 20 ns 64K CMOS static RAM
A 64K-word by 1-bit CMOS static RAM with a 20-ns typical address access time and 70-mW active power dissipation is described. Third-generation CMOS (Hi-CMOSIII) technology is also described. In this technology, n-channel and p-channel MOS transistors having 1.3 /spl mu/m typical gate length and 1.3 /spl mu/m design rule are used. Good RAM performance is achieved by use of a pulsed-word-line technique and double p-well bipolar-CMOS circuitry.
A fast 1024-bit bipolar RAM using JFET load devices
IT HAS LONG BEEN recognized that the need for compact load devices is one of the main problems in building dense bipolar integrated circuits. In recent years several quite promising new approaches to this problem have been developed, including: (1) very high value P-type resistors made by ion implantation (2) the use of lateral PNP transistors to supply and limit the operating current ( 12L) and (3) various kinds of vacuumdeposited resistive materials. The JFET loads to be presented provide yet another way of achieving very compact load elements in bipolar integrated circuits. The JFET loads use the lightlydoped N-type channels which appear under the isolation oxide in an oxide-isolated structure employing an N-type epitaxial layer. These channels arise from the preferential segregation of the dopant during the growth of the isolation oxide’ and have been found to be stable and reproducible. The delineation of the load device is accomplished by a masked P type doping step made prior to epitaxial growth, with the P regions serving as channel stoppers between isolated devices. A load device is produced by simply omitting the channel stopper between two N regions to be connected to the load and thus is physically located in the isolation regions an aspect which substantially improves the circuit density by using space wasted in most bipolar structures; Figures 1 and 4. The load device is best described as a substrate-gate JFET (Figure 2) with many advantages: (1) it is very compact, equivalent resistances of 1 Mi?, being realized in 1 t o 2 mil2 area (including the channel stoppers), (2) i t behaves like a constant-current source, rather like the depletion loads u ed in MOS devices but without the need for gate metalization over it, (3) it connects readily to any part of a transistor collector region without the need for contacts or metalization, (4) its position under thick oxide minimizes parasitic capacitance and sensitivity to potentials of the overlying metalization, ( 5 ) the light doping level in substrate and load gives a low capacitance to substrate, and (6) the sheet resistance and nonlinear properties of these loads can be varied over a very broad range by adjusting process parameters. The process, which provides very shallow double-diffused NPN transistors with washed emitters, PtSi Schottky diodes, and high-beta vertical PNP transistors, lends itself particularly well to the use of a diode-coupled cell for the main storage flipflops in an all-TTL RAM design. As a result a 1024-bit TTL RAM was chosen for the initial design using the JFET load 1 Grove, A S . , Leistiko, 0. and Sah, C.T., “Redistribution of Acceptor and Donor Impurities During Thermal Oxidation of Silicon”, J. Applied Physics, Vol. 35, p. 2695; 1964. Lynes, D.J. and Hodges. D.A., “A Diode-Coupled Bipolar Transistor Memory Cell”, ISSCC Digest of Technical  Papers, p. 44-45; Feb., 1970. 2 devices. These loads allowed the use of a compact, low-powerdissipation diode-coupled cell which has only 2 emitters per bit, rather than the 4 emitters per bit used in the normal emitter-coupled cell. The resultant reduction in active emitter area gives an obvious yield advantage to this type of cell. Figure 3 shows the cell schematic. The JFET loads connect readily to the collector buried layer of Q1 and 42. The cell is insensitive to large variations in the loads since the load currents flow directly into the collectors and not through the writing resistances (R1 and R4). The Schottky coupling diodes add little capacitance to the bit line, allowing extremely fast sensing, the key to fast memory access. The non-linearity of the JFET load devices helps increase the ratio between active and standby cell currents to about 3:l . Typical cell current for this RAM is 14pA during standby and 40pA when addressed. This larger ratio allows sense current to increase and permits fast sensing2. Figure 4 shows the layout of the cell components. The load devices are located in the isolation area outside of the active devices and underneath the thick isolation oxide. The Schottky diode and the base are walled. The washed emitter is non-walled. The interconnection is made using a two-layer-metal process. The cell occupies a 4.7 mils2 area. With additional improvements, cells as small as 3 m i l s 2 can be made for design of larger static RAMS in the future. Careful internal circuit design using address buffers with active pull ups, Schottky diode decoding, differential sensing along with the elimination of the speed-robbing ECL to TTL level conversion has resulted in a device which exceeds the performance of available 1K TTL RAMS using ECL internal design. Table I shows some results;.typical numbers at room temperature and VCC = 5 V. Figure 5 shows a photomicrograph of the chip which measures 97x108 mils. , Nt , . . . . . . . . . @9 @\ o\ \@ . . . . . . . . ....................... . . . . . . . . . . . . . . . . . . . . . . . . ‘ ;, ...... ‘,:..si.o;:;; .‘:::::.: ; \_-.:::;:j:.;<;,: . . . . . . . ........ ........ . ............ . . . . .:::::!.:::::: NEPI :..::;::.:,.:.:.. ....... . . . . . . . . . . .. ... . 2,.:;;,:,, ;; .: 7 I ............... . : ................