The convergence of a PLL with variable parameters
A phase-locked loop with variable parameters is considered. In such a system it is possible to obtain a short convergence time together with a small bandwidth. It is supposed that the PLL's parameters cannot be switched and there is a restriction on the velocity of the parameter variation. 
 
 
 
An optimal strategy of parameter variation is obtained which gives an improvement in convergence time by a factor of about 30 in comparision to fixed parameter and small-bandwidth PLLs.
A 0.35-V 240-μW Fast-Lock and Low-Phase-Noise Frequency Synthesizer for Implantable Biomedical Applications
For implantable frequency synthesizers, realizing ultra-low voltage (ULV) and low power in addition to meeting PLL targets, fast lock and low phase noise, poses a difficult challenge. This paper presents techniques to achieve PLL targets as well as ULV and low power in the same chip through the use of a regular CMOS technology node. A curvature-PFD technique achieves both faster locking and lower jitter compared with conventional techniques. A two-step switching technique substantially reduces the power consumption in current mirrors and reduce noise when switching from a charge pump. Leakage analysis and subthreshold-leakage-reduction technique reduce reference spur and jitter to the voltage-controlled oscillator (VCO). A dither technique randomizes and averages reference spurs. The proposed chip was implemented in 90-nm CMOS technology; the 0.35-V medical-band frequency synthesizer consumes 238-μW power while generating output clock of 401.8 to 431.31-MHz and exhibiting a phase noise of −105.7 dBc/Hz at 1-MHz frequency offset with 20 μs locking time.
High- speed PLL and frequency synthesizer for low frequencies
Conventional phase-locked loops (PLL's) lack speed, because ordinary phase comparators cannot achieve time-continuous phase detection, introducing equivalent time delays into the loops. This paper presents a PLL reconstructed to derive time-optimal responses. First, VCO's and filters are replaced by time-discrete ones, eliminating the stability problem caused by the time delay. Second, period rather than frequency is employed as the controlled variable for utilizing digital phase comparators as linear time comparators. A prototype consisting of about 20 IC's is tested.