A front-end ASIC for use with large-pixel array detectors
An Integrated Circuit (IC) readout chip with four channels arranged so as to receive input charge from the corners of the chip was designed for use with 5- to 7-mm pixel detectors. This Application Specific IC (ASIC) can be used for cold neutron imaging, for study of structural order in materials using cold neutron scattering or for particle physics experiments. The ASIC is fabricated in a 0.5-/spl mu/m n-well AMI process. The design of the ASIC and the test measurements made will be reported. Noise measurements will also he reported.
TGLD: a 16 channel charge readout chip for the PHENIX Pad Chamber detector subsystem at RHIC
This paper describes the PHENIX Pad Chamber (PC) subsystem charge readout chip, TGLD. Due to the PC's high channel density, the TGLD and associated circuitry operate within the active detector region as permanent, zero access components during PHENIX operation and implement remote set-up, test and operation. Since the PC detector consists of three subassemblies (PC1, PC2 and PC3) that detect particles at three different distances from the PHENIX collision vertex, the TGLD design accommodates varying pad capacitance and charge gain for PC1, PC2 and PC3 and provides adjustable discrimination thresholds from MIP/10 to 2 MIP (minimum ionizing particle). Operation with a complimentary digital memory unit (DMU) to form low power, low mass, readout cards is described. Partitioning of readout electronics and address control for robust PC operation are discussed. Component and system test results are reported.
Tradeoffs in low-power CMOS analog circuits for pixel detectors
Abstract Tradeoffs in low-power (MOS analog circuits) are between size, noise, power and speed. Possible modes of operation, characterization and modelling of the MOS transistor at low current are discussed, along with noise and offset properties. A general description of the front and device and its speed requirement is followed by a calculation of optimum filtering and minimization of the fundamental source of equivalent noise charge at low current. The relative important of 1 f and parallel sources of noise is studied. Gain and area are considered and, finally, possible schemes for practical IC implementation are shown.