Impact of Radiation-Induced Single-Event Transients on High Resolution Time to Digital Converter
The paper presents the analysis of radiation-induced Single-Event Transients (SET) in Delay-Locked Loop (DLL) and its impact in the digital output of Time-to-Digital Converter (TDC). The performance of the TDC such as Differential Non-Linearity (DNL),Integral Non- Linearity (INL), resolution etc. are degraded due propagation of the SET from the DLL. The use of improved pseudo differential current-starved delay cell structure in the Voltage Controlled Delay Line (VCDL) in DLL reduces the impact of radiation- induced SET in DLL, and enhances the robustness of DLL based TDC. This effort represents the first of its kind SET analysis on a DLL based TDC. The proposed DLL based TDC is designed in the AMS 180 nm CMOS technology and simulations show that the number of missing pulses on a SET strike in the modified pseudo differential delay cell is reduced to 50% than compared the conventional architectures.
Single event Simulation methodology for analog/mixed signal design hardening
We propose a single-event simulation methodology to characterize the upset/error window of vulnerability for analog/mixed signal circuits. A custom designed 8-b pipeline analog-to-digital converter (ADC) is characterized and hardened based on the results of the simulations.
Phase averaging and interpolation using resistor strings or resistor rings for multi-phase clock generation
Circuit techniques using resistor strings (R-strings) and resistor rings (R-rings) for phase averaging and interpolation are described. Phase averaging can reduce phase errors, and phase interpolation can increase the number of available phases. In addition to the waveform shape, the averaging and the interpolation performances of the R-strings and R-rings are determined by the clock frequency normalized by a RC time constant of the circuits. To attain better phase accuracy, a smaller RC time constant is required, but at the expense of larger power dissipation. To demonstrate the resistor ring's capability of phase averaging and interpolation, a 125-MHz 8-bit digital-to-phase converter (DPC) was designed and fabricated using a standard 0.35-/spl mu/m SPQM CMOS technology. Measurement results show that the DPC attains 8-bit resolution using the proposed phase averaging and interpolation technique.