Study on defect reduction for high aspect ratio etch process
Increasing data needs much larger memory capacity. One of the Flash Memory Solution is Vertical NAND (V-NAND) Flash Memory. In order to fabricate this device, a high aspect ratio hole must be made in the channel hole through the etching process after multilayer thin film deposition. In order to obtain high aspect ratio etch, process condition should have high RF power, high flow rate of polymer gas, and long process time. This harsh etch condition results in high ion energy and lots of polymer production. It can create defects like fluorocarbon polymer and arcing. In this study, we studied arcing mechanism. Here we defined various margins for arcing-free and optimized the focus ring. And we improved pumping conductance for polymer discharge. This study removed defects and obtained arcing-free during V-NAND etch process.
Study of Plasma Arcing Mechanism in High Aspect Ratio Slit Trench Etching
The abnormal process issue, arcing, was met in recipe development of high aspect ratio (HAR) trench etching. The arcing mechanism is proposed by continuous growth of polymer upon hard-mask along pattern boundary during deep trench etching. It leads to excess charge trapped and high potential difference between polymer and substrate. Eventually, electrical field breakdown occurs and results in severe pattern damage. The arcing risk can be effectively monitored in advance by measuring the polymer thickness on bare-Si wafer. A critical thickness of polymer is observed because we seldom find out the occurrence of arcing on the wafer while the polymer thickness is less than 960nm. Low pressure, inert gas dilution and high ESC temperature provide the knobs to control the polymer thickness less than 960nm –the critical thickness, as well achieving acceptable vertical trench profile in HAR etching.
Edge and bevel automated defect inspection for 300mm production wafers in manufacturing
In this paper, we describe a solution for wafer edge and bevel apex defect inspection for a 300 mm semiconductor automated fab. Traditionally, we have used an advanced macro inspection solution for topside wafer inspection. The automated tool revealed that defects surfacing after the back end of line (BEOL) copper chemical mechanical polish planarization (Cu CMP) process were significantly impacting yields. We suspected that particles and film on the edge and bevel were flaking off on to the top of the wafers, causing the yield degradation. However, we needed more information from the edge to confirm our hypothesis. Since offline manual edge analysis was not cost-effective for larger wafer sampling, we sought to develop an inline bevel inspection at the CMP sector that was fast, cost-effective, and integrated with the advanced macro inspection tool. We also established a long-term goal of expanding the process into an all-surfaces inspection within one manufacturing operation step. This paper describes how we integrated the top-down macro and edge bevel inspection into a single automated operation, enhancing data collection and our ability to take corrective action. The process includes full top and complete edge bevel inspection of less than 10 percent of each lot. Although we ran sample tests to inspect edges after numerous processes, this paper focuses on BEOL Cu CMP inspection, including data collection and corrective actions. We also highlight the benefits of edge inspection, and the new level of automated process control. As a result of edge inspection, we have taken corrective actions that have reduced defects on the edge bevel, and improved wafer final test yields by 10 percent from the baseline