CMOS Dual-Work-Function Engineering by Using Implanted Ni-FUSI
For the first time, a simple CMOS fully silicided (FUSI) process achieving n/pMOS band-edge work function was demonstrated, which is fully compatible with conventional CMOS process. Dual-work-function CMOS FUSI, with a wide range of 800 mV, was achieved by implantation of Yb into the poly of the nMOS gate (4.1-eV work function) and Ga into the poly of the pMOS gate (4.9-eV work function), respectively. The placement of the tuning elements at the metal/dielectric interface was engineered with the thermal budget, as well as the implant dose and species.
integrations and challenges of novel high-k gate stacks in advanced cmos technology
Abstract Due to the limitations in conventional complementary metal–oxide–semiconductor (CMOS) scaling technology in recent years, innovation in transistor structures and integration of novel materials has been a key to enhancing the performance of CMOS field-effect transistors (FETs) of past technology generations. Tremendous progress of high dielectric constant (high-k) gate stacks has been made in recent years and some of them have come into application in CMOS devices. However, many challenges remain, such as: (a) suitable permittivity, band gap and band alignment for dielectrics, on Si, (b) thermodynamic stability and interface engineering at both high-k/Si interface and metal/metal interface, (c) depletion effect, high gate resistance and its incompatibility with high-k for metal gate, and (d) low performance attributed to threshold voltage instability. Based on current progress and fundamental considerations, we review the current status and challenges in novel high-k dielectrics and metal gates research for planar CMOS devices and alternative device technologies to provide insights for future research. Finally, this review concludes with perspectives towards the future gate stack technology and challenges in advanced CMOS devices.
Chip scale packaging using chip-on-flex technology
An increasing number of electronic designers, fabricators and users see Chip Scale Packaging (CSP) as a way to obtain the benefits foreseen in multichip packaging and Chip-on-Board (COB) without the problems and limitations currently associated with each. The Chip-on-Flex (COF) multichip packaging technology has been demonstrated to be applicable to single chip packages that meet chip scale packaging goals. This paper looks at the Chip-on-Flex Chip Scale technology and addresses issues including the process, structure, assembly, yields and reliability.