Undesirable citizens: Education, care and control of the “Feeble-minded” in the Swedish Province of Malmöhus, 1900–1950
This paper contains the main results of a recently completed historical research project about the situation of persons cate- gorized as“feeble-minded” in Sweden. In this study, the case of Malmohus province constitutes the microhistorical core. Here, educational and care institutions such as schools, asylums and working homes were particularly established in the first half of the 20th century. The motives behind these foundations will be discussed and the working routines in those institutions will be analysed in terms of teaching and after-care of the inmates and their exclusion justified by social constructs such as “uneducable” or “moral imbecile”. This paper aims at demonstrating how feeble-mindedness was perceived as a social problem, and how close the efforts of education and care were connected to eugenic ideology and control. Thereby, the history of the feeble-minded will be interpreted as a striking example of the contradictions of modernity. The coincidence of social inclusion and exclusion was a characteristic of the situation of an undesirable group of citizens in the Swedish society under the era of modernization. This outcome is of high relevance for understanding the early historical development of the Nordic welfare state.
"Asociala och imbecilla" : kvinnorna på Västra Mark 1931 - 1967
Vilka konsekvenser medforde det att under perioden 1931-1967 kategoriseras som sinnesslo kvinna i Sverige? Undersokningens kallmaterial ar i huvudsak patientjournaler fran Vastra Marks sjukhus for ...
Design of a low power viterbi decoder for wireless communication applications
In this paper, a novel low-power Viterbi decoder with soft decision is proposed. For the branch metric of the Viterbi decoder, our design employs a soft-decision method to improve its correction capability. In order to find the survivor path efficiently, we modify the classical Viterbi decoding algorithm into a new one. This new algorithm is similar to the register-exchange method with lower latency, but using RAM instead of register banks for recording the output bit-stream of the survivor path. Hence, our design can provide a low-power design. Finally, the chip of this design consumes about 28.6K gates using TSMC 0.18 μm CMOS technology. The power consumption of our chip is about 19.5mW at 100MHz.