Novel Flip Chip Technologies for Ultra Thin Chip
Telecommunication equipment that supports high-level information networks is being made portable, small and lightweight. Thus, the miniaturization of semiconductor devices is necessary, and chip thinning and flip chip technologies are key in achieving it. The typical flip chip manufacturing steps for thin semiconductor devices are as follows. First, semiconductor elements are formed on a wafer. Surface protective tape is attached to the surface of the wafer and backside grinding is performed to make the wafer thin. Then, dicing tape is attached to the backside of the wafer and the wafer is diced from the surface side, using a diamond blade, and divided into chips. Then, the chips are picked up, using pick up needles and bumps are formed on the surface of the chip. Next, seal resin is attached to a substrate, then the surface of the chip is attached to the substrate with the seal resin and flip chip interconnection and sealing are performed to mount the chip. This manufacturing step has some problems. In this paper, a novel thin package manufacturing process is described.
Ultrathin Wafer Pre-Assembly and Assembly Process Technologies: A Review
Ultrathin silicon wafer technology is reviewed in terms of the semiconductor applications, critical challenges, and wafer pre-assembly and assembly process technologies and their underlying mechanisms. Mechanical backgrinding has been the standard process for wafer thinning in the semiconductor industry owing to its low cost and productivity. As the thickness requirement of wafers is reduced to below 100 μm, many challenges are being faced due to wafer/die bow, mechanical strength, wafer handling, total thickness variation (TTV), dicing, and packaging assembly. Various ultrathin wafer processing and assembly technologies have been developed to address these challenges. These include wafer carrier systems to handle ultrathin wafers; backgrinding subsurface damage and surface roughness reduction, and post-grinding treatment to increase wafer/die strength; improved wafer carrier flatness and backgrinding auto-TTV control to improve TTV; wafer dicing technologies to reduce die sidewall damage to increase die strength; and assembly methods for die pick-up, die transfer, die attachment, and wire bonding. Where applicable, current process issues and limitations, and future work needed are highlighted.
Time for change in pre-assembly? The challenge of thin chips
One of the most challenging tasks in pre-assembly, coming up in recent years, is to produce thin chips. Lots of applications are standing on the horizon: Smart-cards (credit-card, telefon, security), tags and labels (tube-tickets, price-labels), memory applications (stacks of thin memory-chips). Power- and high-frequency devices are also getting thinner. Several procedures have been suggested and are in some cases already in production for manufacturing thin chips. Most promising are cluster-tools, combining several single processes in one equipment. We will look at the different process-flows and equipment-tools which are available or announced nowadays. Main aspect in judging these methods are compatibility between Front-End and Back-End, process-stability, quality and cost-effectiveness. According to product needs there will be different processes which are to be considered as best practice.