High speed 15 ns 4 Mbit SRAM for space application
A high speed 15 ns 4 Mbit asynchronous SRAM, 500 /spl mu/A stand-by current, 300 krad total dose tolerant, has been developed for space applications, using a hardened 0.25 micron 4 layers metal full CMOS process. A hierarchical organisation per IO bits has been used to achieve high speed as well as low dynamic consumption, also suited for simple SEU (single event upset) induced error corrections, allowing mitigation with classical EDAC corrector. The product operates within 3 to 3.6 V, and ambient temperature from -55 to +125/spl deg/C. A high density die size of 68.3 mm/sup 2/ allows the use of a specific 36-pins dual in line flat pack package with a 500 mil width, making this product very competitive against SEU hardened chips. Successful silicon results are presented as well as radiation tests up to 300 krad.
A 17 nS, 100 nA Stand-by Current Full CMOS 1 Mbit SRAM
A 17 ns, 100 nA stand-by current, full CMOS, 1 Mbit SRAM has been developed. It was fabricated using a 0.5 um, double poly, double metal technology. The use of a full bulk CMOS 6 T memory cell allows a very low stand-by consumption. The low operating power is obtained thanks to a hierarchical architecture. A full differential data path provides a good noise immunity and a fast access time. The memory cell area is 7.15 * 6.5 um2with a chip size of 5.41 * 15.85 mm2. The typical performances are a chip select access time of 16.5 ns, a stand-by current of less than 100 nA and an operating consumption of 120 mA for a 50 MHz cycle.
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