A new circuit configuration for a static memory cell with an area of 880 /spl mu/m/sup 2/
A new 5-transistor memory cell in double polysilicon technology with depletion-load elements and a minimum linewidth of 3 /spl mu/m is presented. The circuit configuration, based on a Schmitt trigger, leads to static memory cells having a bit density of 1100 bit/mm/SUP 2/ and an average power consumption of 5.5 /spl mu/W/cell. With the help of computer simulations the static and dynamic behavior of the basic circuit are calculated and discussed in detail as well as the two possible operation modes of the memory cell. These results compare favorably with the experimental results obtained on a realized 2/spl times/4 memory array. The performance of the proposed memory cell is the same as that of a conventional 6-transistor cell, but the area is reduced.
GaAs Schmitt trigger memory cell design
A GaAs five-transistor static memory cell is proposed. It is derived from nMOS Schmitt trigger. The memory cell overcomes the subthreshold leakage loss by using a self ground-shifting technique which limits the leakage current flow to the cell. Compared with conventional GaAs SRAM cells, it offers small design area and allows large memory arrays to be realized. A prototype was implemented in a 1 /spl mu/m non-self aligned GaAs MESFET technology with read and write access time of 1.0 ns and 1.25 ns, respectively.<<ETX>>
Laminar heat or mass transfer in rectangular channels and in cylindrical tubes for fully developed flow: comparison of solutions obtained for various boundary conditions
Abstract A comparison is made of results obtained with various boundary conditions at the wall of the channels. By comparing blood Sherwood numbers for finite wall resistance with those for constant concentration boundary condition only a small variation is found for various points along the blood channel.