Study of the packaging effect on blocking voltage of power devices during durability test
We investigated why the blocking voltages of a power device are lowered during a durability test through a device simulation called Technology Computer Aided Design (TCAD) and measurements using the optical beam induced current (OBIC) method. We found that the spread of the depletion layer caused by the bonding wire is what decreased the blocking voltage.
Increase of the Robustness of the junction terminations of power devices by a lateral variation of the Emitter Efficiency
A new diode technology called Emitter Controlled (EC)-HDR (High Dynamic Robustness) that allows a pronounced enhancement in switching safe-operating area has been developed. For the first time, the concept used for this drastic improvement is presented. The same principle has been applied to the Insulated Gate Bipolar Transistor (IGBT).
Anomalous Annealing Behavior of Arsenic Implanted Silicon as a Function of Dose and Energy
Anomalous annealing behavior of damage in As implanted Si has been investigated by channeling effect measurements. Room temperature As implants with doses from 1014 to 2 × 1016cm-2 at energies ranging from 50 to 250 keV into Si were annealed over the range of 600°C to 1100°C. Anneal temperatures ≥ 950°C reduce the disorder for ion doses of 0.5 to 1 × 1016 cm-2 at energies between 50 and 250 keV. Anomalously high residual disorder was found for the intermediate doses of 2 × 1014 to 2 × 10/cm2 implanted above 100 keV. For this intermediate dose, annealing of implants performed at liquid nitrogen temperatures did not show significant reduction in this damage. However implants at 200° to 300°C indicate a lower amount of damage compared to the room temperature implants.