Monolithic high voltage gated diode crosspoint array IC
A new gated diode crosspoint integrated circuit has been developed for telephone switching system applications. Central to the design of this high voltage device has been the extensive use of numerical modeling techniques. Two-dimensional simulation of the individual dielectrically isolated components that comprise the switch array has led to an improvement in their electrical parameters together with size reduction for each of their geometries. Additional calculations dealing with the routing of interconnect metalization about the perimeter of components has indicated how such runners may encroach upon these elements without degrading their performance so that higher density circuitry could be assembled onto a chip. The resulting IC therefore realizes substantial advances over its predecessors, including: increased scale of integration (9 vs. 4 crosspoint pairs), more compact design (2.1 vs, 3.6mm2per crosspoint pair), higher OFF state minimum blocking voltage (600 vs. 530 volts), and reduced ON state incremental resistance (10 vs. 18 ohms).
Process and design issues in a 600 V bonded wafer process
Describes a bipolar process which provides moderate voltage vertical devices and 600V lateral devices. High breakdown is achieved using relatively thin islands with no buried layer. Island thickness and bond oxide thickness are the two material parameters which have a large influence on breakdown when island doping has been optimized. Island thickness in this work was chosen to be greater than 20 microns so that there is enough island under the base of the vertical bipolars to provide a low collector resistance. The maximum thickness used was 40 microns which is about the maximum thickness through which it is practical to RIE etch to form the lateral isolation trenches. The bond and side oxide thicknesses were set at 4 microns to achieve 600V breakdown in the chosen island thickness.
A single-chip CMOS CODEC with switched-capacitor filters
PCM CODEC and filters integrated on a single chip (30.4mm2) using CMOS technology will be described. Chip consists of encoder/decoder, switched-capacitor filters and two PLL clock generators. Power dissipation is as low as 35mW.