High speed 15 ns 4 Mbit SRAM for space application
A high speed 15 ns 4 Mbit asynchronous SRAM, 500 /spl mu/A stand-by current, 300 krad total dose tolerant, has been developed for space applications, using a hardened 0.25 micron 4 layers metal full CMOS process. A hierarchical organisation per IO bits has been used to achieve high speed as well as low dynamic consumption, also suited for simple SEU (single event upset) induced error corrections, allowing mitigation with classical EDAC corrector. The product operates within 3 to 3.6 V, and ambient temperature from -55 to +125/spl deg/C. A high density die size of 68.3 mm/sup 2/ allows the use of a specific 36-pins dual in line flat pack package with a 500 mil width, making this product very competitive against SEU hardened chips. Successful silicon results are presented as well as radiation tests up to 300 krad.
A 17 nS, 100 nA Stand-by Current Full CMOS 1 Mbit SRAM
A 17 ns, 100 nA stand-by current, full CMOS, 1 Mbit SRAM has been developed. It was fabricated using a 0.5 um, double poly, double metal technology. The use of a full bulk CMOS 6 T memory cell allows a very low stand-by consumption. The low operating power is obtained thanks to a hierarchical architecture. A full differential data path provides a good noise immunity and a fast access time. The memory cell area is 7.15 * 6.5 um2with a chip size of 5.41 * 15.85 mm2. The typical performances are a chip select access time of 16.5 ns, a stand-by current of less than 100 nA and an operating consumption of 120 mA for a 50 MHz cycle.
A Low Power Complete Charge-Recycling Bus Architecture for Ultra-High Data Rate Ulsi's
The ultra-high data rate of 25Gbls and beyond is one of the most important design requirements in realizing the future ULSI's for super highdefiition (HD) moving pictures and graphics applications in consumer electronics. The most effective means to achieve such a data rate is to employ a large number of the buses interconnecting the embedded memory, the graphics controller, efc, on a ULSI system chip. For example, even at an operating frequency of SOMHz, parallel buses of more than 512 are required. However, a drastic increase of the power dissipation is inevitable due to the increased bus-capacitance. Even if suppressing the bus-swing to less than 1V[1], there still remains a bus-power dissipation of a far above 5OOmW, which is intolerable for battery operation as shown in Fig.1. Hence, this paper proposes a complete Charge-Recycling Bus(CRB) architecture that can reduce the bus-power dissipation to less than 15% of the conventional suppressed bus-swing scheme while realizing the data rate of 25Gbts. t of New Bus ( As shown in Fig. 2, even when using suppressed bus-swing (Vcc/k) scheme of Conv.Bq(k=4) coupled with a down converter, the power cannot be reduced adequately for battery operation. This is because there still remain a contribution from the total bus-capacitance nCd, where n and Cd are the number of total bus pairs and the capacitance of the individual bus, respectively. The key concept of the CRB architecture is virtual stacking of the individual buscapacitance Cd into a series configuration to reduce not only the bus-swing but also the total equivalent bus-capacitance. When the practical data-path layouts in ULSrs are considered, data buses are classified into a local bus (path width = 2 bit ) and a global bus (path width 2 4 bit) depending on the hierarchy of data-path. Hence, we propose the Local and Global CRB schemes for the local and global buses, respectively. The Local CRB scheme is virtual connection of two bus-capacitance Cd and a smaller dummy capacitance Cs in series while the Global CRB scheme is virtual stacking of numerous buscapacitance Cd in series. Regarding the i-th complementary bus pair in the two CBR schemes, the input INi and the equalization signal EQ establish not only the output signals, Di and XDi, but also the bus-level signals at nodes H and L as follows: 1)in former half of the clock cycle, the EQ signal synchronized with the system clock equalize Di and XDi of the complementary bus pair ; 2)in latter half of the clock cycle, the input signal INi switches higher (or lower) level of the bus-output pair Di and XDi to the node H (or L) according to the m t h table in Fig.3. In addition, the clocked altemating dummy Cs pair inserted between two pairs of complementary bus is an important element, especially when the number of the buses running in parallel is short as the case of the Local CRB scheme, where the clocked signal CLH of a half of the system clock frequency altemates the connections of the A and E) nodes of the dummy capacitor pair Cs with the nodes H and L as shown in Fig. 3. The series connection of the numerous bus capacitance Cd and the dummy capacitor Cs is realized by joining the node L of the i-lth bus (or capacitor) pair to the node H of the i-th bus (or capacitor) pair as shown in Fig.3. For example, in the Local CRB scheme, when IN1 = "1" and CLH = "0", D1 and XD1 are connected to Vcc and the node B of the Cs, respectively. On the other hand, in the Global CRB scheme, when INi-1 = "1". INi = "0" and M i + l = "0, Di and XDi are connected to XDitl of the lower adjacent bus pair and XDi-1 of the upper adjacent bus pair, respectively.