Back-side De-processing using CMP for bulk silicon 40-nm graphics processors
A back-side de-processing process by chemical mechanical polishing (CMP) is developed. The process has been optimized to produce repeatable results. The process is capable of exposing the circuitry of the die uniformly and is able to target more than one area for units with multiple defect locations; front-side de-processing process has difficulty achieving the same results due to the unevenness of the die
Backside failure analysis and case studies for Cu/low k technology
In this work, failure analysis (FA) challenges and new failure modes for devices of copper technology, especially for circuit-under-pad (CUP) devices are presented. Backside FA techniques including backside sample preparation, backside defect localization, backside physical analysis with both deprocessing and cross section analysis have been developed and applied to Cu/low k technology. For backside FA deprocessing, we present wet chemical etching, reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP) and combination of these techniques. For the backside FA cross-section analysis of copper/low k samples, focused ion beam (FIB) techniques that have been developed and studied are addressed. In addition, detailed characterization of backside silicon thinning using TMAH wet chemicals is presented.
Improved Cu CMP process for 0.13 /spl mu/m node multilevel metallization
A novel two-step CMP process combining improved Cu abrasive free polishing (AFP) solution with newly developed barrier metal CMP slurry for 0.13 /spl mu/m node Cu damascene process is demonstrated. This CMP process can minimize the erosion and the dishing of Cu wiring. Further, two types of Cu residues, random Cu residue, and systematic Cu residue on patterned wafer are eliminated with optimizing the total process design. Using these technologies, it is shown that 0.18 /spl mu/m node 7 level multilevel metallization structure is successfully formed.