A 7000-gate microprocessor on SOS&#8212;PULCE
An n-channel MOS LSI microprocessor integrating 20 000 transistors on a chip has been realized on a sapphire substrate utilizing the Coplanar-II process. It contains ALU, shifters, and 44 registers which are combined to three 16-bit buses. By utilizing three types of threshold voltage for load transistors, 28-percent reduction in power dissipation is achieved. The minimum cycle time is 200 ns. By using the Coplanar-II process, anomalous leakage currents due to parasitic transistors at the sides of island are suppressed. It is found that the silicon-on-sapphire (SOS) version operates 2.3 times faster than the bulk-silicon version, which is mainly explained by the parasitic capacitance ratio. Parallel-plate approximation in calculating a wiring capacitance results in an underestimate by a factor of 60 compared with taking the two-dimensional effect into account. It is verified that a) the observed yield of a very large SOS chip is higher than the value predicted from a randomly distributed defects model, and b) the yield-sensitive active area of an SOS is so small that it can compensate for the yield degradation due to the very large defects density on an SOS wafer.
Performance of downward scaled CMOS/SOS
MOS/SOS structures have been investigated which suppress various anomalous currents and also adjust threshold voltage to the desired value for downward scaled CMOS/ SOS devices. Furthermore, short channel CMOS/SOS device performance has been discussed in comparison with the CMOS/Bulk. A deeper, boron implant was used for n-channel MOSFET on SOS to suppress the back channel current and the punch through current between the source and drain. Also, deeper phosphorus implant was used for p-channel MOSFET on SOS to reduce the punch through current. Shallow boron implant was also used to adjust the threshold voltage to the desired value for both n- and p-channel devices. This design is especially beneficial for downward scaled CMOS/SOS devices. Using this device structure, short channel CMOS/SOS devices have been successfully fabricated. Comparison of the experimental results with CMOS/SOS ring oscillator computer simulation has made it clear that the wiring capacitance will play a predominant role in determining the speed of a device with shorter channel length. Superiority of SOS in speed should be emphasized in smaller feature size devices, due to its essentially smaller wiring capacitance than bulk devices.
MOS and vertical junction device characteristics of epitaxial silicon on low aluminum-rich spinel☆
Abstract Various devices have been fabricated using silicon films grown epitaxially on low aluminum-rich spinel substrates. The insulating substrate provides complete isolation of the semiconductor devices and eliminates the parasitic capacitances of the back-biased p−n junctions. The low aluminum-rich spinel offers the advantages of better thermal stability and easier surface preparation for silicon epitaxy over both the conventional high aluminum-rich (MgO:3Al2O3) and the stoichiometric (MgO:Al2O3) materials. MOS capacitors, MOS transistors, and vertical junction diodes were constructed and studied using films with mobilities equal to or near the bulk values. Information on MOS capacitance vs. bias behavior, transistor characteristics, diode junction properties, and minority carrier lifetime was obtained. The silicon-spinel composites were also characterized by physical methods, and the nature of the defect structures was examined.