Comparative study of tri-gate flash memories with split and stack gates
The functional tri-gate flash memories with splitgate have been demonstrated for the first time, and its Vt variabilities before and after one P/E cycle have be systimetically compared with stack-gate ones. It was confirmed that split-gate shows smaller Vt distribution after erase and excellent over-erase immunity compared to those of stack-gate. Moreover, it was found that BVDS is higher than 3.2 V even Lgc was down to 76 nm. This indictes that tri-gate is useful for scaled NOR flash.
Comparative Study of Charge Trapping Type SOI-FinFET Flash Memories with Different Blocking Layer Materials
The scaled charge trapping (CT) type silicon on insulator (SOI) FinFET flash memories with different blocking layer materials of Al2O3 and SiO2 have successfully been fabricated, and their electrical characteristics including short-channel effect (SCE) immunity, threshold voltage (Vt) variability, and the memory characteristics have been comparatively investigated. It was experimentally found that the better SCE immunity and a larger memory window are obtained by introducing a high-k Al2O3 blocking layer instead of a SiO2 blocking layer. It was also confirmed that the variability of Vt before and after one program/erase (P/E) cycle is almost independent of the blocking layer materials.
Two dimensionally inhomogeneous structure at gate electrode/gate insulator interface causing Fowler-Nordheim current deviation in nonvolatile memory
The gate electrode polycrystalline silicon (gate poly-Si)/gate insulator SiO/sub 2/ interface structure has been studied for obtaining reliable nonvolatile memory devices. The voltage deviation of Fowler-Nordheim tunneling current of the devices is discussed in terms of the SiO/sub 2/ surface roughness. High resolution scanning electron microscope (SEM) and atomic force microscope (AFM) measurements indicate that two dimensional nanometric oxide ridges are formed at the interface. It was found that a phosphorus dose below 2*10/sup 15/ cm/sup -2/, an annealing temperature below 900 degrees C, and the use of arsenic as a dopant resulted in the smooth SiO/sub 2/ surfaces. The reduction in the voltage deviation of the tunneling current is correspondingly obtained under these conditions. The oxide ridge growth can be explained by excess phosphorus distribution at grain boundaries and phosphorus-rich SiO/sub 2/ formation.<<ETX>>