Multi-phase-driven split-word-line ferroelectric memory without plate line
A working methodology bypasses the conventional cell plate line (PL), mitigating its disadvantages. The methodology utilizes split word lines (SWLs), driven by multi-phased voltage signals. In this scheme there is no need for PL and additional elements, and fabrication is simple and compatible with downscaling of cell area.
A 256 kb nonvolatile ferroelectric memory at 3 V and 100 ns
One of the most important features for ferroelectric material is fast write at low voltage. This feature is used in a 256 kb nonvolatile memory that operates at 3 V power supply with a read/write time of 100 ns. Active current is 3 mA at 200 ns cycle time at 3 V for battery operation. The cell consists of 1 transistor and 1 capacitor per bit (1T1C) permitting a high level of integration. For low-voltage low-power operation, use is made of a preset reference-cell circuit, wordline boost circuits with a ferroelectric boosting capacitor and a divided-cell plate circuit.<<ETX>>
A 16 kb ferroelectric nonvolatile memory with a bit parallel architecture
The authors describe an experimental 16-kb nonvolatile memory using two memory cells per bit with one transistor and one ferroelectric capacitor per memory cell. The RAM measures 5 mm*7 mm with 462 mu m/sup 2/ per bit. It is built in a 2- mu m CMOS n-well process and has a chip-enable access time of 200 ns. The authors also demonstrate a bit-parallel architecture in which the common plate of the capacitors runs parallel to the bit lines and connects all bits in a given column. The typical characteristics of the device are given.<<ETX>>