A high performance 0.12 /spl mu/m CMOS with manufacturable 0.18 /spl mu/m technology
High-performance 0.12 /spl mu/m CMOS devices with manufacturable 0.18 /spl mu/m technology are presented. A nominal I/sub dsat/N/P of 950/410 /spl mu/A//spl mu/m at an I/sub off/ of 12 nA//spl mu/m is achieved by reducing the body effect. The double-sidewall structure developed can reduce gate-fringe capacitance without increasing the junction leakage, and the inverter delay of 11 ps/stage is achieved at a nominal L/sub gate/ of 0.12 /spl mu/m. Small 6T-SRAM cells of 3.1 /spl mu/m/sup 2/ with 0.5 /spl mu/m gate pitch are implemented using a vertical well isolation and a self-aligned contact (SAC). In the SAC process, a blanket Si/sub 3/N/sub 4/ layer used as an etching stopper is optimized for the I/sub dsat/N/P ratio and the negative bias temperature instability (NBTI) reliability. The 9-level interconnection is optimized to reduce a long wire RC-delay.
MOSFET Performance Scaling—Part I: Historical Trends
A simple analytical model that describes MOSFET operation in saturation from subthreshold to strong inversion is used to derive a new formulation of the intrinsic switching delay of the transistor. The proposed model follows the scaling trend of experimental ring-oscillator data better than the conventional CV/I metric. The historical trend of MOSFET performance scaling is examined, and it is shown that the continuous increase of the carrier velocity in the channel has been the main driver for the improved transistor performance with scaling. The dependence of velocity and mobility in recent strain-engineered devices is studied based on published experimental data, and a theory is proposed to justify this dependence. It is shown that the virtual-source velocity depends on low-field mobility more strongly than what was previously believed, in spite of the fact that state-of-the-art MOSFETs operate at 60%-65% of their ballistic limit. These observations will be used in Part II of this paper to explore the tradeoffs between key device parameters in order for the commensurate scaling of the device performance with its dimensional scaling to continue in the future high-performance CMOS generations.
Microfiltration: Effect of retentate protein concentration on limiting flux and serum protein removal with 4-mm-channel ceramic microfiltration membranes.
The objective of our study was to determine if the limiting flux and serum protein (SP) removal were different at 8, 9, or 10% true protein (TP) in the microfiltration (MF) retentate recirculation loop using 0.1-µm ceramic graded permeability membranes with 4-mm-channel diameters operated at 50 °C using a diluted milk protein concentrate with 85% protein on a total solids basis (MPC85) as the MF feed. The limiting flux for the MF of diluted MPC85 was determined at 3 TP concentrations in the recirculation loop (8, 9, and 10%). The experiment was replicated 3 times for a total of 9 runs. On the morning of each run, MPC85 was diluted with reverse osmosis water to an MF feed TP concentration of 5.4%. In all runs, the starting flux was 55 kg/m(2) per hour, the flux was increased in steps until the limiting flux was reached. The minimum flux increase was 10 kg/m(2) per hour. The limiting flux decreased as TP concentration in the recirculation loop increased. The limiting flux was 154 ± 0.3, 133 ± 0.7, and 117 ± 3.3 kg/m(2) per hour at recirculation loop TP concentrations of 8.2 ± 0.07, 9.2 ± 0.04, and 10.2 ± 0.09%, respectively. No effect of recirculation loop TP concentration on the SP removal factor was detected. However, the SP removal factor decreased from 0.80 ± 0.02 to 0.75 ± 0.02 as flux was increased from the starting flux of 55 kg/m(2) per hour to the limiting flux, with a similar decrease seen at all recirculation loop TP concentrations.