A matched expansion probe card for high temperature LSI testing
This paper describes the fabrication process and mechanical properties of a novel probe card were described. To match the thermal expansion between the probe card and a silicon wafer in wafer-level burn-in test, a Pyrex glass substrate with feedthrough connections was used to support the probes. To make the slantwise probe contactors, spray coating was used to form a uniform photoresist film on a deeply-wet-etched silicon wafer. The fabricated probe card has 13185 p/sup +/ silicon probe contactors at a pitch of 150 /spl mu/m on an area of 44.0 mm /spl times/ 45.7 mm. The rigidity of the probes is approximately 91.45 N/m. The planarity of the probe tips is within /spl plusmn/ 1 /spl mu/m from the base level.
Fabrication technology of CMOS-MEMS probe chip compatible with electroless nickel plating process
In this study, we use the standard TSMC 0.35 μm 2P4M process to design CMOS-MEMS probe chip. MEMS technology involves the following steps such as lithography process, electroless nickel (EN) plating process, grinding process and dry etching process. The probe chip has through silicon via (TSV) package structure, and the combination of CMOS process within the multi-layer interconnections, which could assist the connection between the probes head the external devices, and reduce the difficulty of wiring layout. In addition, passive components or circuits could be integrated with the CMOS chip to improve the frequency bandwidth and measuring quality. So far, MEMS probe exist a shortcomings that are not able to be integrated with the CMOS process, and the testing cost. The finite element method was adapted to design of probe shapes and sizes. The LIGA-like thick photoresist process and EN plating technique was used in this study, Ni-P alloy to increase the thickness of the cantilever probe to strengthen its support strength were also applied. When the probe cantilever through the EN plating of deposition time, the uneven surface was appeared, each layer structure is used by polishing process to achieve the surface coplanarity. Finally, the probes structure were suspended by the dry etching process (RIE, ICP-RIE), and this study successfully fabricated chips forming one of the probe.
Improvement of solder joint reliability between multilayer ceramic package and printed wiring board by new ceramic material
Ball grid array (BGA) packages for MPU semiconductor device are considered as replacements of pin grid array packages. This is driven by the requirements for smaller size, thinner thickness, higher wiring density and higher performance. A thermal coefficient of expansion (TCE) mismatch between an Al/sub 2/O/sub 3/ ceramic BGA and a printed wiring board (PWB) causes a large stress in solder joints during a thermal fatigue test. Stress due to the TCE differences is also large in a leadless chip carrier (LCC) package, since this is the same surface mounting type package as BGA. By a finite element method (FEM) simulation, we found that a minimum stress value was obtained when the target TCE value was 9/spl sim/14ppm./spl deg/C. We developed a new ceramic material. The TCE and the Young's Modulus of this material are 11.5ppm//spl deg/C and 114GPa, respectively. By temperature cycling tests of BGA and LCC, we have confirmed that a relaxation of the thermal stress drastically increased solder joint reliabilities by using the high TCE new ceramic material.