Achieving ultra low k dielectric constant for nanoelectronics interconnect systems
Air gaps are a promising alternative to porous low-k dielectrics to achieve ultra low k-values in Cu damascene interconnects. Two approaches of air gap formation using wet etch back of sacrificial PECVD SiO2 dielectrics were evaluated concerning their feasibility and preparation results are shown. Electrical measurements were verified by simulation and have shown a capacitance reduction of approximately 50 % compared to the SiO2 filled reference structures. Furthermore finite element method (FEM) simulations were performed to extract the effective k-value for different technology nodes. General k eff extraction procedure by FEM simulation is described. Furthermore the impact of variation of thickness and k-value of the functional layers applied for air gap formation was investigated. These functional layers are etch stop, cap and mask layers and currently consist of PECVD SiC:H films. It has been shown, that both parameters (thickness and k-value) considerably contribute to the effective k-value. For both investigated technology nodes, the 65 nm and 45 nm node, parameters can be found to fulfil the ITRS requirements for keff. Lower k-values of the functional layers are needed, if the thickness has to be increased for processing reasons. For example k=5.5 and thickness of 15 nm yield a keff of about 2.5 for the 45 nm node. Ultimate effective k-values of 2.0 and below could be achieved for lower k-value or thickness of the functional films
Air gap integration for the 45nm node and beyond
First promising results including reliability and electromigration of an extendable air gap integration approach obtaining mechanically stable air cavities at the inter-metal dielectric (IMD) level are presented. Extraction of the effective dielectric constant (k/sub eff/) is demonstrated to be 1.45 for non-passivated single damascene structures. Using 45 nm node specifications and the proposed integration scheme, two metal levels are simulated showing a k/sub eff/ of less than 2.0 after full integration, fulfilling multiple future interconnect node requirements.
Air-gap formation during IMD deposition to lower interconnect capacitance
The use of air-gaps between interconnect metal lines to reduce interconnect capacitance has been explored. Simulations were performed to determine the reduction in capacitance obtainable using air-gaps. The formation of air-gaps in the isolation oxide between metal lines was simulated using Stanford Profile Emulator for Etching and Deposition in IC Engineering (SPEEDIE). The capacitance of the SPEEDIE profiles was then extracted using Raphael (an electrical analysis simulator from TMA). The feasibility of air-gaps was also demonstrated experimentally. Fabricated air-gap structures exhibited a 40% reduction in capacitance when compared to a HDP-CVD oxide gap-fill process with K=4.1. Additionally, the air-gap structures did not exhibit any appreciable leakage current.