InGaAs-OI Substrate Fabrication on a 300 mm Wafer
In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs) wafer on insulator (InGaAs-OI) substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB) and Smart CutTM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 °C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM), scanning acoustic microscopy (SAM), and HR-XRD, to insure the crystalline quality of the post transferred layer.
Direct Bonding Mechanism of ALD-Al2O3 Thin Films
Direct bonding mechanism of amorphous ALD alumina has been investigated from room temperature up to 1200◦C. By considering the evolution with temperature of free alumina surfaces and bonded configuration we highlight strong interaction between oxidant species and defect generation through interfacial oxidation. In the first case, the combination of internal stress and adhesion loss by dry O2 oxidation results in blister formations, whereas in the case of bonding structures, wet oxidation with H2 production at Silicon-Alumina interfaces explains void formation. Based on these established mechanisms we provide insights on alumina layer integration within a large temperature range. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any medium, provided the original work is properly cited. [DOI: 10.1149/2.0241505jss] All rights reserved.
UTBOX SOI Substrate with Composite Insulating Layer
Fully Depleted (FD) devices provide the electrostatic boost that is required to manufacture CMOS technology with printed gate lengths 25 nm and below, with the additional benefit of improved variability due to the ability of these devices to operate with undoped channel. Two embodiments of FD devices are developed: 3D Multi Gate 1 and planar FDSOI. 2,3 Both deliver on expectations with demonstration of great DIBL at extremely scaled gate lengths that translate into superior performance especially at reduced Vdd. SOI substrates will play a major role in these new technologies. They greatly simplify the 3D FET process and reduce device variability. Planar Fully-Depleted technology has already been demonstrated on SOI wafers with UltraThin Body and BOX (UTBB) with very high energy efficiency, 4 and is entering production at the 28 nm node. TheextremelythinBOXoptionprovidesadditionalcharacteristics: itfurtherimprovestheelectrostaticsofthedevices, 5 itallows dynamic change of the Vt through back biasing 6 and enables SOI/Bulk hybrid integration. 7 FurtherscalingtheFDSOItechnologyrequiresimprovingtheelectrostaticcontrol.Onerelevantknobtoreducetheshort-channeleffects is to increase the back-gate to channel coupling. This can be achieved by using a thinner BOX and/or by resorting to a high-k dielectric. The novel composite SiO2/Al2O3/SiO2 BOX SOI substrates studied in this paper have a higher BOX permittivity than pure SiO2 allowing for better capacitive coupling at the same physical thickness, while maintaining low DIT (Interface Trap Density) with good interface carrier mobility. Moreover,thepowerfuletchstopcapabilityofthealuminainserted in the BOX enables MESA isolation in a CMOS flow. This can be applied for planar or FinFET technologies. Combination of those two effects brings significant advantages in terms of integration, increasing the manufacturing process window. SOI with alumina BOX.— The use of alumina as buried insulating material in SOI has been widely investigated for thermal considerations. Indeed, the good thermal conductivity of alumina (20 W/m.K) suggests that the self heating of SOI devices, that comes from poor conductivity of buried silicon dioxide (1.5 W/m.K), can be significantly reduced by using an alumina BOX. This advantage is still valid for thin BOX SOI structure. 8,9 Furthermore, the high dielectric constant of alumina (three times higher than for silicon dioxide) allows a better coupling between front and back transistor gates in thin BOX SOI architecture with ground plane: the performance of a thin alumina BOX is equivalent to that of aS IO2 BOX three times thinner. 10 With such back-bias architecture, the drawback of having a high-K BOX dielectric for the short channel effects are reported to have very little effect on the final transistors. 11