Failure analysis on the standby current due to dislocation in STI structure of flash memory
The technology of increasing Internal Vcc without using memory tester is used to enhance the photon emission and the failure range is defined in detail by nano probing. With these methods, we found out that the leakage current was caused by dislocations of STI arranged in a row.
Case study of embedded memory failure analysis for dislocation issue
Embedded memory is an integrated on-chip memory that supports the logic core to accomplish intended functions. High-performance embedded memory is a key component in VLSI, because of its high-speed and wide bus-width capability, which eliminates inter-chip communication. In this paper, embedded memory device and CMOS logic is integrated on-chip and it is a more complex of process technology compared with stand-alone memory. For the process engineering, we are always confronted with many problems, especially, the dislocation that causes some failures.
Progress in device isolation technology
Abstract This contribution gives a brief overview on the current status of device isolation technology. Starting with conventional shallow-trench-isolation (STI), the challenges introduced by this approach are outlined. Based on this discussion, the concept of the recently developed extended trench isolation gate technology (EXTIGATE) is presented. It will be shown that EXTIGATE not only provides a relief from the drawbacks of conventional STI processing, but also offers promising alternatives for front-end process integration, device optimization and specific applications.