Optimization of fabrication processes of the mesa-type GaAs:Te blocked-impurity-band detector
In this work, the device structure of the mesa-type GaAs:Te blocked-impurity-band detector was designed. The fabrication processes were presented briefly, and optimization of the fabrication processes was investigated. A 3-micron-thick SiO2 film was deposited as resist to substitute for photoresist in the 50-micron-deep mesa etching process. In addition, a bi-layer photoresist lithography technique was adopted to optimize the process of electrode fabrication. It is demonstrated that the device quality can be improved significantly after optimization.
First results on GaAs blocked impurity band (BIB) structures for far-infrared detector arrays
We are developing a GaAs photoconductive detector for far-infrared (FIR) astronomy. A detector based on GaAs in the blocked impurity band (BIB) con.guration is expected to extend the long wavelegth limit of currently available stressed Ge:Ga photoconductors up to about 330 microns. Without the need of uniaxial stress applied to the crystal, this would furthermore allow the fabrication of single chip arrays with a large number of pixels. We are reporting results of the characterization of preliminary GaAs BIB test structures. The experimental work is supported by numerical modeling that includes all contact and space charge effects.
3D integration technology for sensor application using less than 5μm-pitch gold cone-bump connpdfection
Three-dimensional (3D) integrated circuit (IC) technology is an effective solution to reduce the manufacturing costs of advanced two-dimensional (2D) large-scale integration (LSI) while ensuring equivalent device performance and functionalities. This technology allows a new device architecture using stacked detector/sensor devices with a small dead sensor area and high-speed operation that facilitates hyper-parallel data processing. In pixel detectors or focal-plane sensor devices, each pixel area must accommodate many transistors without increasing the pixel size. Consequently, many methods to realize 3D-LSI devices have been developed to meet this requirement by focusing on the unit processes of 3D-IC technology, such as through-silicon via formation and electrical and mechanical bonding between tiers of the stack. The bonding process consists of several unit processes such as bump or metal contact formation, chip/wafer alignment, chip/wafer bonding, and underfill formation; many process combinations have been reported. Our research focuses on a versatile bonding technology for silicon LSI, compound semiconductor, and microelectromechanical system devices at temperatures of less than 200̂C for heterogeneous integration. A gold (Au) cone bump formed by nanoparticle deposition is one of the promising candidates for this purpose. This paper presents the experimental result of a fabricated prototype with 3-μm-diameter Au cone-bump connections with adhesive injection, and compares it with that of an indium microbump (μ-bump). The resistance of the 3-μm-diameter Au cone bump is approximately 6 Ω. We also investigated the influence of stress caused by the bump junction on the MOS characteristics.