A simple Flash memory cell model for transient circuit simulation
A simple Flash memory cell model for circuit simulation is presented. The proposed model gives an excellent fitting of dc and transient data and does not require additional simulation time comparing with that of a MOSFET transistor. Effective control-gate voltage method and ideal current-mirror technique are introduced to calculate floating-gate voltage. These allow macro modeling of a Flash memory cell in a circuit simulator.
A simple method for determination of Fowler–Nordheim tunnelling parameters
A simple technique for extracting the Fowler–Nordheim (FN) tunnelling parameters is proposed. It consists of measuring the Drain-Source current of a floating gate transistor while a linear ramp voltage is applied to a simple injector structure attached to the transistor's floating gate. Such a test device is fabricated using a standard CMOS process. The parameters obtained can be used in a freely available electrical simulator as SPICE3f5 (NGSPICE), but in general it can be easily adapted to other SPICE-like programs. We describe the technique step-by-step and a comparison is made of simulated and measured FN tunnelling parameters, for a floating gate transistor with tunnelling injectors. A good agreement has been found between experimental and simulated data.
Advanced electrical-level modeling of EEPROM cells
Conventional modeling of floating-gate electrically erasable programmable read-only memory (EEPROM) cells is shown to be inadequate to correctly evaluate the tunnel current flowing through the MOS injector during programming, essentially because of relevant quantum phenomena taking place at the cathode semiconductor-oxide interface. An electrical-level model incorporating numerical analysis of such effects is developed and discussed. The model is validated by comparing results of the simulations with experimental data obtained with EEPROM cells. The model of the MOS injector has been implemented in the circuit simulator SPICE. >