Upgrading the backend of the pipeline readout system for Belle II
The Belle II experiment at KEK will be a successor to the Belle experiment. Belle II will start operation from 2015, searching for subatomic particles beyond the standard model. The pipeline readout system for the Belle experiment will be unable to satisfy the requirements of Belle II, because the luminosity of the SuperKEKB accelerator will be about 40 times higher than that of KEKB. We have moved the digitizer to front-end electronics and upgraded the back-end part, as well as replacing the processor on the readout module. We report here the upgrade plan and the throughput of the back-end part.
Development of front-end electronics and TDC LSI for the ATLAS MDT
Abstract Architecture of the front-end electronics for the ATLAS muon precision chamber (MDT) is presented. Especially, test results of a prototype TDC chip are described in detail. The chip was fabricated in a 0.3 μm CMOS Gate-Array technology. Measurements of critical elements of the chip such as the PLL, and data buffering circuits demonstrated adequate performance. The effect of gamma-ray irradiation, using a 60 Co source, and neutron irradiation, were also examined. The test results revealed radiation tolerance adequate for the operation of the circuits in the environment of the ATLAS MDT. Mounting of the front-end electronics to the MDT is scheduled to start in the year 2001.
Serial-bus based trigger timing distribution system for SuperBelle
We have developed a high-speed serial-bus based trigger timing distribution system. Copper cables will distribute the trigger and related timing signals to more than one thousand newly developed pipeline data acquisition modules. These modules are needed for the SuperBelle upgrade to the Belle detector at an upgraded KEKB (SuperKEKB) storage ring. The main idea is to use a pair of serial-bus lines over a compact, low-cost and widely available enhanced category-5 shielded twisted pair (STP) cable. The entire system consists of three types of modules and is scalable by cascading switch modules over multiple stages. In this way four stages can interconnect up to 4096 readout modules. We have demonstrated that the basic technology is suitable for such an application. Before a full system replacement, a two-step integration procedure is planned to integrate the system into the running Belle data acquisition system.