Fault Location Using Sparse Wide Area Measurements
Transmission line fault location allows quick repair of the damage caused by the fault and timely restoration of the line affected by the fault. Accuracy of the fault location is quite important since it affects repair crew’s ability to physically locate the damage part quickly. Typically, the desirable accuracy is to be able to locate a fault within a span of the transmission line towers. This paper presents a new fault location scheme which uses synchronized phasor measurements from different substations sparsely located near the region where the fault has occurred. When fault occurs different Intelligent Electronic Devices (IEDs) such as Phasor Measurement Units (PMUs) and Digital Fault Recorders (DFRs) connected to Global Positioning System (GPS) receivers and installed in some of the substations in the region will be automatically triggered by the change in monitored signals and will record corresponding current, voltage and status signals. Apart from these sparse measurements, the proposed method also uses SCADA PI Historian data which is utilized for tuning the power system model data with the pre-fault condition in real time information. The paper presents how the technique is implemented and shows test results using actual power system model as well as actual field data from a utility company that supported demonstration of the technique. The results are quite encouraging since the sparse measurement problem for such unique transmission line configurations does not allow any other known techniques to produce accurate and reliable results while the proposed technique produces satisfactory results.
The Fundamental Concept of Unified Generalized Model and Data Representation for New Applications in the Future Grid
The concept of interoperability of data and model as presented in this paper is viewed as being very useful for implementing variety of future applications related to power system monitoring, protection, control and operation. To illustrate the proposed concept, two applications are used: state estimation and fault location. Generalized State Estimators (GSEs) consider both measurements and switching device statuses as variables to be estimated. We propose a unified generalized state estimator that uses only one class of network objects (node-breaker), which would avoid model conversions, enables unified topology processing, and supports flexible forms of generalized estimation. The proposed Fault Location (FL) application uses different types of measured data which utilizes power system static data modeled using bus-branch. Significant number of mappings is required to correlate the measured data and model. It is shown that both applications will be simplified if unified generalized representation of data and model as suggested in this paper is utilized.
Design of a low power viterbi decoder for wireless communication applications
In this paper, a novel low-power Viterbi decoder with soft decision is proposed. For the branch metric of the Viterbi decoder, our design employs a soft-decision method to improve its correction capability. In order to find the survivor path efficiently, we modify the classical Viterbi decoding algorithm into a new one. This new algorithm is similar to the register-exchange method with lower latency, but using RAM instead of register banks for recording the output bit-stream of the survivor path. Hence, our design can provide a low-power design. Finally, the chip of this design consumes about 28.6K gates using TSMC 0.18 μm CMOS technology. The power consumption of our chip is about 19.5mW at 100MHz.