The origin of extended dislocations induced by high-dose ion implantation
The origin and the generation mechanism of ion implantation-induced dislocations is investigated with an Si/sub 3/N/sub 4/ band line/space pattern. The Si/sub 3/N/sub 4/ film-edge stress not only causes dislocation propagation but also causes the formation and deformation of extended dislocations at the initial stage of annealing. The behavior is clarified that the dislocation loops are deformed into pattern-edge dislocation half loops, which accumulate at the film edge and are punched out from the edge.
Proposal of Prediction Method for Dislocation Generation in Silicon Substrate for Semiconductor Devices.
In semiconductor devices, stress in silicon substrates sometimes generates dislocations during the fabricating process at high temperatures. Although most of the dislocations are generated at the stress singularity fields, dislocation generation has been discussed without considering stress singularity problems. This paper shows that dislocation generation can be predicted by using stress singularity parameters. In the experiment, the specimens were silicon substrates with stressed thin film bands, at whose edges the stress singularity fields were formed. The strength of the singularity was controlled in order to change the bandwidth. Whether or not dislocations at the film edges appeared was compared with the value of the singularity parameter. This comparison was performed for two structures of thin films and at three temperatures, and the results show that the singularity parameter can be used to predict the generation of dislocations.
Comparative evaluation of gap-fill dielectrics in shallow trench isolation for sub-0.25 /spl mu/m technologies
The dielectric material used to fill trenches in Shallow Trench Isolation (STI) of transistors, is key to device performance. This paper (a) evaluates the integration of currently available dielectric technologies and (b) designs an optimized process scheme for 0.25 /spl mu/m node and beyond. A detailed study of LPCVD TEOS, SACVD oxide, Hydrogen-Silsesquioxane SOG (HSQ) and ICP (Inductively Coupled) HDP (High Density Plasma) CVD oxide, for STI, is presented for the first time. A novel ICP HDP-CVD process scheme is shown to have the advantages of single step, low thermal budget and high throughput as well as provide good gap-fill, low HF etch rate, low moisture uptake, low shrinkage with annealing, low diode reverse leakage and isolation at 0.3 /spl mu/m spacing.