Laser scanning of MOS IC's reveals internal logic states nondestructively
A laser scanning system has been used to observe the internal logic pattern in a MOS LSI device in a nondestructive manner. The laser scanner has also been used to selectively change logic states deep within the device. Pictures of the logic patterns revealed by the scanner are discussed.
A Flying‐Spot Scanner
A flying‐spot scanner used to study the electrical properties of semiconductor materials and devices is described. The instrument automatically deflects a collimated light beam in a raster pattern and focuses the raster on the photosensitive semiconductor surface. The electrical output from the semiconductor is amplified and used to form an image of the photoresponse of the sample on a cathode ray tube. The resolution of the system referred to the sample is about 5 μ.
Photoresponse Mapping of Semiconductors
Much work has been done investigating the effect of light on various semiconductor characteristics. An improved method for obtaining photoresponse measurements on semiconductor junctions has been developed whereby the entire junction topography of a semiconductor device may be displayed. Some of the results obtained using this technique and its usefulness as a possible screening tool are presented. The method used to obtain topological photoresponse displays is a modification of flying spot scanner techniques. A raster of variable fields per second as well as lines per field is generated and projected on the sample through suitable optical reductions. The photovoltage generated by the sample is amplified, processed and then used to intensity modulate a display raster scanning in synchronism with the original raster. This technique can be implemented using common laboratory equipment. Using the technique just described, the photoresponse characteristics of various samples have been studied. It has been possible to obsrve areas of enhanced multiplication on reverse biased devices (e.g. - microplasma locations) as well as mask defect locations and inverted areas including channels. It is possible to locate both inversions which are originally present in devices and those created by reverse bias stressing. This technique has also been applied to integrated circuits and the results obtained are as expected from work on discrete devices. Analysis of this data is, however, somewhat more complex due to the number of junction areas present.