Study of the packaging effect on blocking voltage of power devices during durability test
We investigated why the blocking voltages of a power device are lowered during a durability test through a device simulation called Technology Computer Aided Design (TCAD) and measurements using the optical beam induced current (OBIC) method. We found that the spread of the depletion layer caused by the bonding wire is what decreased the blocking voltage.
An analytic approach for optimal field ring spacing of a diode under punchthrough operation
The use of floating field limiting ring (FFRL) reduces the surface field due to junction curvature effect, and the breakdown voltage in planar devices can be increased. In this paper, a new analytic method is developed based on the combination of plane junction in the bulk and cylindrical junction at the surface. From these analysis, optimal space between main diffusion and FFLR can be obtained. The influences of concentration and width of lightly doped collector region and base diffusion junction depth are also investigated. The results are in good agreement with the two-dimensional numerical ones.
Source Side Thermal Runaway of Trench IGBTs, Dependence on Design Aspects
The high-current turn-off behaviour of trench IGBTs with dense shunting of the parasitic npn and with shallow p emitters was investigated both by simulation and experiment. In spite of current localization mechanisms (dynamic avalanche, npn transistor injection) there is no indication for a regenerative on-state under isothermal conditions, even at high temperatures up to 750K. Stable current filamentation and device destruction can only be obtained including thermal feedback. Deep trenches result in more stable behaviour, obviously from reduced maximum temperature in the source cell