A high performance 0.12 /spl mu/m CMOS with manufacturable 0.18 /spl mu/m technology
High-performance 0.12 /spl mu/m CMOS devices with manufacturable 0.18 /spl mu/m technology are presented. A nominal I/sub dsat/N/P of 950/410 /spl mu/A//spl mu/m at an I/sub off/ of 12 nA//spl mu/m is achieved by reducing the body effect. The double-sidewall structure developed can reduce gate-fringe capacitance without increasing the junction leakage, and the inverter delay of 11 ps/stage is achieved at a nominal L/sub gate/ of 0.12 /spl mu/m. Small 6T-SRAM cells of 3.1 /spl mu/m/sup 2/ with 0.5 /spl mu/m gate pitch are implemented using a vertical well isolation and a self-aligned contact (SAC). In the SAC process, a blanket Si/sub 3/N/sub 4/ layer used as an etching stopper is optimized for the I/sub dsat/N/P ratio and the negative bias temperature instability (NBTI) reliability. The 9-level interconnection is optimized to reduce a long wire RC-delay.
MOSFET Performance Scaling—Part I: Historical Trends
A simple analytical model that describes MOSFET operation in saturation from subthreshold to strong inversion is used to derive a new formulation of the intrinsic switching delay of the transistor. The proposed model follows the scaling trend of experimental ring-oscillator data better than the conventional CV/I metric. The historical trend of MOSFET performance scaling is examined, and it is shown that the continuous increase of the carrier velocity in the channel has been the main driver for the improved transistor performance with scaling. The dependence of velocity and mobility in recent strain-engineered devices is studied based on published experimental data, and a theory is proposed to justify this dependence. It is shown that the virtual-source velocity depends on low-field mobility more strongly than what was previously believed, in spite of the fact that state-of-the-art MOSFETs operate at 60%-65% of their ballistic limit. These observations will be used in Part II of this paper to explore the tradeoffs between key device parameters in order for the commensurate scaling of the device performance with its dimensional scaling to continue in the future high-performance CMOS generations.
Damage initiation and propagation in composite shells subjected to impact
Abstract The paper investigates the impact-induced damage initiation and propagation for laminated composite shells under low-velocity impact. A three-dimensional eight-node non-conforming element is described to analyze interlaminar stress distribution, and progressive failure. The damage analysis is performed by using Tsai–Wu quadratic failure criterion, Tsai’s damage modes and an additional delamination formula at all Gaussian points. The damage modes considered are matrix cracking, fiber breakage and delamination. The progressive failure is expressed by reducing stiffness of the material at all failed Gaussian points. Special attention is centered on curved laminates. Impact energy threshold for the onset of damage and transient damage size are predicted for composite shells. The analyses of the flat and curved laminates are compared for discussing their different damage mechanism. In addition, the influence of the stacking sequence, the thickness and the radius of curvature on damage behavior of composite shells are studied.