Simulation study on influence of interface trap position in Sii-xGex Gate-All-Around (GAA) field-effect transistor
In this paper, performance degradation of Si1−xGex gate-all-around (GAA) Field-Effect Transistor (FET) depending on interface trap position was investigated through TCAD simulations. Interface traps were located at three different points along the channel. Parameters such as hole mobility and energy band were analyzed to understand the effects of partially generated interface traps by unstable GeOx.
Selective GeOx-scavenging from interfacial layer on Si1−xGex channel for high mobility Si/Si1−xGex CMOS application
We demonstrate a technique for selective GeO<sub>x</sub>-scavenging which creates a GeO<sub>x</sub>-free IL on Si<sub>1-x</sub>Ge<sub>x</sub> substrates. This process reduces N<sub>it</sub> by >60% to 2e11 and increases high-field mobility at N<sub>inv</sub>=1e13 cm<sup>-2</sup> by ~1.3× in Si<sub>0.6</sub>Ge<sub>0.4</sub> pFETs with sub-nm EOT.
Reduction in Interface Trap Density of Al2O3/SiGe Gate Stack by Electron Cyclotron Resonance Plasma Post-nitridation
An electron cyclotron resonance (ECR) plasma post-nitridation method has been investigated for improving Al2O3/SiGe metal–oxide–semiconductor (MOS) interfaces. We evaluated the interface trap density (Dit) of Al/Al2O3/Si0.75Ge0.25/p-Si MOS capacitors by the conductance method, showing that Dit of the Al2O3/SiGe interfaces was reduced to 3×1011 cm-2 eV-1 at the minimum expense of equivalent oxide thickness (EOT). X-ray photoelectron spectroscopy (XPS) revealed that a SiGe–ON interfacial layer was formed between the Al2O3 and SiGe layers, which improved the interfacial properties through nitrogen passivation of SiGe interfaces. As a result, a superior Al2O3/SiGe MOS interface with a 0.2 nm EOT increase can be obtained by plasma post-nitridation.