HBM ESD EDA check method applied to complete smart power IC's — Functional initialization and implementation
A functional approach to check global IC ESD schematic network correctness and protected circuitry ESD compliance using Calibre® Mentor PERC is presented and applied to Smart Power IC product. Developed checker exploits an initialization method able to accurately define ESD paths. The project follows ESD Association EDA International Working Group guidelines.
HV latchup — Power analog ICs co-design with block level verification
Power Analog ICs which contain both high voltage and low voltages cells require a unique approach to achieve latchup robustness. A methodology was developed to allow both schematic and layout block level latchup verification automation as applied to HV Latchup in Power Analog ICs design. The methodology enables co-design between schematic design and layout design, improving silicon success as well as shortening the design cycle.
A DRC-based check tool for ESD layout verification
The growing complexity of IC designs makes verification for ESD correctness increasingly difficult. A useful verification tool, based on specific ESD layout rules and extended with layout connectivity, will be presented. The demonstrated approach is extendable with respect to checks and analysis options. Successful usage has been demonstrated on products.