A front-end ASIC for use with large-pixel array detectors
An Integrated Circuit (IC) readout chip with four channels arranged so as to receive input charge from the corners of the chip was designed for use with 5- to 7-mm pixel detectors. This Application Specific IC (ASIC) can be used for cold neutron imaging, for study of structural order in materials using cold neutron scattering or for particle physics experiments. The ASIC is fabricated in a 0.5-/spl mu/m n-well AMI process. The design of the ASIC and the test measurements made will be reported. Noise measurements will also he reported.
A discriminator with a current-sum multiplicity output for the PHENIX multiplicity vertex detector
A current output multiplicity discriminator for use in the front-end electronics (FEE) of the Multiplicity Vertex Detector (MVD) for the PHENIX detector at RHIC has been fabricated in the a 1.2-/spl mu/ CMOS, n-well process. The discriminator is capable of triggering on input signals ranging from 0.25 MIP to 5 MIP. The frequency response of the discriminator is such that the circuit is capable of generating an output for every bunch crossing (105 ns) of the RHIC collider. Channel-to-channel threshold matching was adjustable to /spl plusmn/4 mV. One channel of the multiplicity discriminator occupied an area of 85 /spl mu//spl times/630 /spl mu/ and consumed 515 /spl mu/W from a single 5-V supply. Details of the design and results from prototype device testing are presented.
Use of pixel detectors in elementary particle physics
Abstract Silicon pixel detectors allow measurement of charm and bottom decays, which have mean rest-frame decay lengths in the range 60–360 μm. Because of the high particle density which can be accommodated by detectors with pixel size 30 μm × 30 μm, direct measurement of decay paths should be possible in future fixed-target experiments. At high energy hadron colliders like the SSC and LHC and at e + e − colliders operating at the Z 0 resonance the two particle separation will be of order 70 μm at the inner barrel. Such a high track density can best be accommodated with pixel detectors. A prototype readout chip for a pixel detector has been submitted for fabrication by an SSC R&D collaboration. This chip contains a random access array of 32 × 64 cells of dimension 45 × 150 μm. Each cell has analog and digital storage. The performance goal is 300 electrons rms noise at 20°C and full charge collection in 50 ns.