HBM ESD EDA check method applied to complete smart power IC's — Functional initialization and implementation
A functional approach to check global IC ESD schematic network correctness and protected circuitry ESD compliance using Calibre® Mentor PERC is presented and applied to Smart Power IC product. Developed checker exploits an initialization method able to accurately define ESD paths. The project follows ESD Association EDA International Working Group guidelines.
A Study of HBM and CDM Layout Simulations Tools
The use of EDA ESD checking tools has grown considerably in the past few years in the semiconductor industry. This paper gives an overview of four different HBM and CDM layout simulation tools. For the first time, a full CDM analysis combining predictive CDM SPICE and Layout simulations are presented.
Conserved Quantities of a Class of Nonlinear Difference-Difference Equations
Higher-order conserved quantities of a class of nonlinear difference-difference equations which are related to the discrete-time Toda equation are obtained using the Miura transformations.