Quasistatic Bubble Propagation in 1.5 μm Period Ion-Implanted Tracks for 64 Mbit Magnetic Bubble Memory Devices
Ion-implanted tracks with a 1.5 μm period for use in 64 Mbit magnetic bubble memory devices have been fabricated and operated. The bubble material used was (BiSmLu)3 (FeAl)5O12 garnet film, supporting 0.45 μm bubbles. The resist mask patterns for implantation were formed using a 1/10 reduction projection aligner, using rectangular patterns on a reticle. The bubble propagation tracks were fabricated by double deuterium implantation and annealed at 400°C for 30 minutes, with an SiO2 layer deposited on the garnet surface to stabilize the implanted layer. An operating bias field margin in excess of 7% was stably obtained in quasistatic bubble propagation. This shows that the ion-implanted devices have great potential for use in 64 Mbit magnetic bubble memory devices.
Hydrogen out‐diffusion suppression effect of overlayers in H+2 ‐implanted magnetic bubble garnet
Hydrogen out‐diffusion suppression effect of overlayer deposited on H+2 ‐implanted magnetic bubble garnet has been investigated using gas mass spectroscopy and secondary ion mass spectroscopy. It has been found that oxide films such as SiO2, SiO, TiO2, and Al2O3 or nitride film such as Si3N4 effectively suppress out‐diffusion of hydrogen during annealing, keeping a large anisotropy field change induced by hydrogen implantation after the annealing. Hydrogen depth profiles have also been found to have a sharp peak at the boundary between overlayer and garnet which can suppress out‐diffusion of hydrogen. Metal films such as Au, Mo, and Ni–Fe alloy have been found not to act as suppressors of hydrogen out‐diffusion. Annealing hydrogen‐implanted garnet with an oxide overlayer on the surface is useful for ion‐implanted bubble device fabrication because of thermal stability of large anisotropy change induced by implantation.
4Mb on-chip-cache bubble memory chips with 4 µm period ion-implanted propagation patterns
4Mb ion-implanted bubble devices (IIBD) with on-chip-cache organization (OCCO) have been designed for 1μm bubbles, and characterized for all functional elements in the devices. The 4Mb memory chip with 9.5×11.8 mm chip size consists of the same two 2Mb units, each of which is divided into 1Mb even and odd sites with 300 strorage loops (s-loops) and cache loops (c-loops), whose bit lengths are 4160 bits and 130 bits, repectively. Basic bit cell size is 4 × 4 μm. The 4Mb chip has an OCCO structure with the following distinguishing functional elements: (1) Bidirectional N-shape transfer gates. (2) A major line replicator with 2 crossed hairpin conductors. (3) DRO detector with folded thin NiFe elements. (4) A hairpin nucleation generator in a 240° super track. (5) Even bit minor loops. Operating margins for the 4Mb IIBD fabricated on (YSmLuBiCa) 3 (FeGe) 5 O 12 are well balanced in all functional elements, and obtained as 25 Oe, sufficient for practical use. It has been found that in-plane holding field applied to stop/start (s/s) direction is necessary for s/s stabilization, and that anisotropy along pattern edges due to stress relief acts a significant role for bit instability and for c-s gate operation. LPE film thickness has been optimized as 1.1 μm for 100-120 keV He+ implantation.