In situ endpoint detection by pad temperature in chemical-mechanical polishing of copper overlay
As the number of metal levels and the wafer size increase, the global planarity and effective removal of metal overlay across the wafer becomes more crucial. Chemical-mechanical polishing (CMP) has been recognized essential to achieve this goal. Accurate in situ endpoint detection and monitoring method significantly improves the yield and throughput. Previous methods have been proposed, which either require the rearrangement of the machine set-up, or can only be implanted on certain types of machines. In this study, a model for pad temperature capable of predicting the endpoint of CMP in situ is established based on the total consumed kinematic energy between wafer and pad. Limited assumptions of thermal and kinematic conditions are made. The model of temperature rise uses the integral of the relative polishing speed and is verified by on-line measurement. Since the coefficient of friction between the pad and dielectric layer is distinguishably lower than that between the pad and the metal layer, the pad temperature increases milder than polishing the metal layer. In use of the proposed regression method applied to the measured temperature rise, the endpoint of the process can be detected.
Motor Power Signal Analysis for End-Point Detection of Chemical Mechanical Planarization
In the integrated circuit (IC) manufacturing, in-situ end-point detection (EPD) is an important issue in the chemical mechanical planarization (CMP) process. In the paper, we chose the motor power signal of the polishing platen as the monitoring object. We then used the moving average method, which was appropriate for in-situ calculation process and made it easy to code for software development, to smooth the signal curve, and then studied the signal variation during the actual CMP process. The results demonstrated that the motor power signal contained the end-point feature of the metal layer removal, and the processed signal curve facilitated the feature extraction and it was relatively steady before and after the layer transition stage. In addition, the motor power signal variation of the polishing head was explored and further analysis of time delay was performed.
Copper metallization for advanced IC: requirements and technological solutions
Due to the scaling down, the contribution of interconnects should become preponderant for the performance of IC. The use of low-k dielectrics and/or low resistivity metals in order to decrease the parasitic capacitance of interconnect is a technological requirement. Especially the use of copper, with mineral dielectric as IMD, instead of aluminium alloy is now commonly accepted. In this paper we compare the intrinsic performance of two damascene architectures. The planarization by metal CMP, which will determine the final metal thickness, may induce killer defects (shorts between lines) or degraded metal sheet resistance uniformity for multi-level metallization devices. The impact on electromigration of the damascene structure is presented: due to the reverse architecture, the grain sizes and orientations are found to be linewidth dependent. On the other hand, the life times extrapolated with different copper and barrier deposition processes vary on a large range: from similar to those obtained with aluminium for a full CVD metallization (barrier+copper) to more than one order of magnitude higher for a CVD barrier and a mixed CVD+PVD copper deposition.