A low-power third-order ΔΣ modulator using a single operational amplifier
An architecture for low-power ΔΣ modulators suitable for high-resolution portable sensor systems is presented. The circuit uses a single operational amplifier to achieve a third-order noise shaping. The two-stage op-amp employs a boosting technique that increases by 5 the slew-rate. The circuit, simulated at the transistor level using a conventional 0.18-µm CMOS technology, obtains a peak SNDR of 88 dB over an input signal bandwidth of 100 kHz. The simulated power consumption is 125 µW with a 1.5-V supply voltage. The achieved Figure of Merit (FoM) is 31 fJ/conversion-level.
Third-order ΣΔ modulator with 61-dB SNR and 6-MHz bandwidth consuming 6 mW
This low-power sigma-delta modulator targets the DVB-H requirements and achieves about 10 bit with 6-MHz signal band and a FoM of 0.59 pJ/conversion. The used scheme is a multi-bit third order modulator that, with suitable topological modification, enables using two op-amps and enjoying a swing reduction at the quantizer input. The area of the circuit, fabricated with a 0.18-mum analog CMOS technology, is 0.32 mum2. The nominal supply voltage is 1.8 V and the clock frequency is 96 MHz (OSR = 8). Experimental measurements confirm the behavioral study made accounting for the op-amps limitations.
A novel architecture for reducing the sensitivity of multibit sigma-delta ADCs to DAC nonlinearity
A novel first order sigma-delta architecture, which also shapes the nonlinearity of the DAC is proposed. Unlike other proposed solutions this topology consists of multibit quantisation noise only so offers enhanced stability and higher-order noise-shaping at the expense of a highly linear analog differentiator. The paper discusses some aspects of a practical realisation and possible extensions to higher order noise-shaping.