HBM ESD EDA check method applied to complete smart power IC's — Functional initialization and implementation
A functional approach to check global IC ESD schematic network correctness and protected circuitry ESD compliance using Calibre® Mentor PERC is presented and applied to Smart Power IC product. Developed checker exploits an initialization method able to accurately define ESD paths. The project follows ESD Association EDA International Working Group guidelines.
Schematic-Level and Layout-Level ESD EDA check methodology applied to smart power IC's - initialization and implementation
A functional methodology to fully check IC ESD network topology together with protected circuitry ESD compliance at Schematic-Level and metal interconnections at Layout-Level is developed and applied to Smart Power products. A common operational method is developed to simultaneously initialize different Schematic-Level and Layout-Level verification tools.
ESD design automation for a 90nm ASIC design system
Design tools for ESD are described that ensure robust protection at both the cell and chip level in a high-volume, highly automated ASIC design system. There are three primary components: Design Rule Checking (DRC) for ESD; transient CDM simulations on extracted netlists; and analysis of chip-level power supply net resistances.