InGaAs-OI Substrate Fabrication on a 300 mm Wafer
In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs) wafer on insulator (InGaAs-OI) substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB) and Smart CutTM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 °C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM), scanning acoustic microscopy (SAM), and HR-XRD, to insure the crystalline quality of the post transferred layer.
Direct Bonding Mechanism of ALD-Al2O3 Thin Films
Direct bonding mechanism of amorphous ALD alumina has been investigated from room temperature up to 1200◦C. By considering the evolution with temperature of free alumina surfaces and bonded configuration we highlight strong interaction between oxidant species and defect generation through interfacial oxidation. In the first case, the combination of internal stress and adhesion loss by dry O2 oxidation results in blister formations, whereas in the case of bonding structures, wet oxidation with H2 production at Silicon-Alumina interfaces explains void formation. Based on these established mechanisms we provide insights on alumina layer integration within a large temperature range. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any medium, provided the original work is properly cited. [DOI: 10.1149/2.0241505jss] All rights reserved.
Sub-30 nm InAs Quantum-Well MOSFETs with self-aligned metal contacts and Sub-1 nm EOT HfO2 insulator
Sub-30 nm III-V planar Quantum-Well (QW) n-type MOSFETs are fabricated through a self-aligned CMOS compatible front-end process. Good performance and short-channel effect mitigation are obtained through the use of a QW-channel that incorporates a thin pure InAs subchannel and extremely scaled HfO<sub>2</sub> gate dielectric on a very thin InP barrier (total barrier EOT<;1 nm). The devices also feature self-aligned metal contacts that are 20-30 nm away from the edge of the gate. At L<sub>g</sub>=30 nm, transconductance of 1420 ìS/ìm and subthreshold swing of 114 mV/dec at 0.5 V are obtained. 22-nm gate-length devices are demonstrated through this process. Long-channel devices exhibit nearly ideal subthreshold swing of 69 mV/dec, and high channel mobility of 4650 cm<sup>2</sup>V<sup>-1</sup>s<sup>-1</sup> at N<sub>s</sub>=4×10<sup>12</sup> cm<sup>-2</sup>.