Physical study of the dissipated power area in high electron mobility transistors for thermal modelling
The hot area in power transistors due to the power dissipation is determined from a 2D-hydrodynamic model. The power is calculated everywhere in the device from the knowledge of the physical quantities (current density, electric field). The hot area is determined accurately to be coupled to a thermal modelling giving the temperature everywhere in the device [J. Park, M.-W Shin, C.-C. Lee, Thermal modeling and measurement of GaN-based HFET devices, IEEE Electron Device Lett. 24(7) (2003) 424-426 [1]; J.-C Jacquet, R. Aubry, H. Gerard, E. Delos, N. Rolland, Y. Cordier, A. Bussutil, M. Rousseau, S.L. Delage, Analytical transport model of AlGaN/GaN HEMT based on electrical and thermal measurement, 12th GAAS Symposium, Amsterdam, 2004, pp. 235-238 [2].]. The method is applied to HEMTs (high electron mobility transistors) based on GaAs or GaN. It is shown that the hot area depends on the bias conditions and on the transistor gate recess topology.
Thermal Behavior Investigation of Cascode GaN HEMTs
This paper presents the evaluation of heat generation behavior and related thermal measurement analysis of packaged high-power AlGaN/GaN high electron mobility transistors (HEMTs) cascaded with low-voltage MOSFET and SiC SBD. Since thermal management is extremely important for high power packaging, a hybrid integration of the GaN HEMTs onto a DBC substrate and metal case is proposed. We investigate the temperature performance of cascode GaN HEMTs by thermal simulations in comparison to the experimental results by using infrared thermography.
Inclusion of carrier temperature effects in a thermionic-diffusion theory of the schottky barrier
Abstract Recent evidence indicates that thermionic emission is a more important process than conduction-diffusion for current limitation in many Schottky barriers. By choosing suitable momentum and energy conservation equations an expression for the thermionic-diffusion current is obtained where it is assumed that the carrier temperature in the space charge region of the metal-semiconductor interface does not differ substantially from the equilibrium temperature. When thermionic emission is the dominant process for current limitation it is shown that carrier temperature effects may still be important. A discussion is presented where the above solution is applied to a model Si-type diode. Carrier temperature effects reduce the current below its ‘thermal equilibrium’ value in all cases.