Novel Flip Chip Technologies for Ultra Thin Chip
Telecommunication equipment that supports high-level information networks is being made portable, small and lightweight. Thus, the miniaturization of semiconductor devices is necessary, and chip thinning and flip chip technologies are key in achieving it. The typical flip chip manufacturing steps for thin semiconductor devices are as follows. First, semiconductor elements are formed on a wafer. Surface protective tape is attached to the surface of the wafer and backside grinding is performed to make the wafer thin. Then, dicing tape is attached to the backside of the wafer and the wafer is diced from the surface side, using a diamond blade, and divided into chips. Then, the chips are picked up, using pick up needles and bumps are formed on the surface of the chip. Next, seal resin is attached to a substrate, then the surface of the chip is attached to the substrate with the seal resin and flip chip interconnection and sealing are performed to mount the chip. This manufacturing step has some problems. In this paper, a novel thin package manufacturing process is described.
Novel wafer dicing and chip thinning technologies realizing high chip strength
As telecommunication equipment that supports high-level information networks is being made portable, the requirements for telecommunication equipment to be small and lightweight are becoming stricter. Thus, miniaturization of semiconductor devices is necessary, and wafer dicing and chip thinning technologies are important key technologies to achieve it. Wafers are thinned by mechanical in-feed grinding using a grindstone containing diamond particles, and wafers are divided by mechanical blade dicing using a diamond blade. However, mechanical processes using diamond grits leave damage such as chipping, saw mark or residual strain on chip surfaces; thus, chip strength decreases. At chip thickness of 50 to 200 mum, such damage has to be avoided. In this study, the relationship between chip residue damage and chip strength is examined, and novel wafer dicing and thinning technologies that realize an average chip strength have increased from 253 MPa to 1312 MPa are described
New approach to vision-based BGA package inspection
Ball grid array (BGA) techniques have developed very fast due to the advantages of more I/O ports, small size, and so on. In this paper, a vision-based algorithm for BGA package inspection is proposed to accurately estimate center and diameters of solder-balls of BGA packages, so that defects of BGA packages, such as missing or extra balls, oversize or undersize balls, over-height or under-height balls, and pitch can be detected for ensuring the quality of BGA packages.