A New CD Measurement Method Linked with the Electrical Properties of Devices
This paper describes a new measurement method of a CD-SEM with nanometer-level precision and good correlation with electrical characteristics for an actual device of ultra-large-scale integration (ULSI). With the decrease in feature size, the pattern to be measured tends to become a curved shape. In order to measure such a pattern within measurement precision on the order of 5 nm, two-dimensional measurement is effective. Here we report a new measurement algorithm featuring that the critical dimension is derived from the value of the area of a measurement pattern. We apply this measurement method to actual device of 64-Mbit DRAM and confirm the reproducibility of 3.6 nm for the gate linewidth measurement, and that of 5.6 nm for the hole diameter measurement. Furthermore, we verify that the measurement values of the gate linewidth have a strong correlation with the threshold voltage and those of the hole diameter also have a strong correlation with the contact resistance, respectively. key words: CD SEM, metrology, curved structure, electrical
Reconstruction of LSI Microstructures from Secondary Electron Intensity Profiles
A best-fitting method and a slope-integrating method are proposed for the reconstruction of ISI (large scale integrated circuit) microstructures from secondary electron intensity profiles. In the former method, a rounded edge profile of the photoresist pattern is reconstructed by best-fitting the analytical secondary electron intensity profile for an assumed edge model to the experimental secondary electron intensity profile. The model is a hyperbola with fitting parameters which approximates the cross section of the photoresist pattern. In the latter method, the rounded edge profile is reconstructed by integrating the slope obtained, considering the dependence of the secondary electron yield on the primary electron incidence angle to the specimen
Improved Accuracy For SEM Linewidth Measurements
The diminishing size of VLSI features necessitates the use of a scanning electron microscope (SEM) for making inprocess CD measurements. The intent of this paper is to establish a methodology for improving the accuracy and precision of such measurements. In SEM metrology, the challenge lies in determining two points in the secondary electron line-scan corresponding to the feature edges. The systematic errors introduced by incorrect edge detection can be reduced greatly by optimizing the linescan with proper choice of SEM operating conditions. Experiments on two samples of interest in VLSI processing demonstrate the advantage of increased accelerating voltage for minimizing measuremental uncertainty. In addition, measuremental robustness, or sensitivity of linewidth measurement to SEM defocus, is shown to be strongly dependent upon the specific edge detection algorithm used.