Serial-bus based trigger timing distribution system
We have developed a serial-bus based trigger timing distribution system to handle the trigger and related timing signals over more than one thousand newly developed pipeline data acquisition modules for the Belle detector at the KEKB storage ring and for the SuperKEKB upgrade. The main idea is the use of 10-bit serial-bus lines over an inexpensive, compact and widely available enhanced category-5 shielded twist pair (STP) copper cable. The serial-bus is operated at 42.33 MHz, resulting in a 508 Mbps serial data transfer over the STP cable up to a distance of 15 m. The entire system consists of only three types of modules. The system is highly scalable by cascading switch modules over multiple stages: we use 4 stages to handle up to 4096 readout modules. We have proved that the basic technology is suitable for such an application. A two-step integration procedure before the full replacement is planned to integrate the system into the running Belle data acquisition system.
The Data acquisition system based on PMC bus
High energy physics experiments in KEK/Japan rush into over KHz trigger stage. Thus, we need a successor of the data acquisition(DAQ) system that replaces the CAMAC or FASTBUS systems. To meet these needs, we have developed a DAQ system which includes a crate, base-board modules, daughter cards for front-end A/D or T/D conversion, and back-end communication cards for data transfer and timing control. The size of the crate is for the 9U Euro-cards with the standard VME32 bus and extension connectors for power supply. The base-board comprises of a local bus with the sequencer connected to the front-end daughter cards via event buffering FIFOs, and the standard PMC (PCI mezzanine card) bus to be set a PMC processor unit to reduce data size from the front-end daughter cards. A data transfer module, which is connected to the event building system, and a trigger control unit, which communicates with the central timing controller are installed on the back-end communication card connected to the rear end of the base-board. We describe the design of this DAQ system and evaluate the performance of it.
A control and readout system for the BELLE silicon vertex detector
Abstract A newly developed system for the control and readout of the BELLE silicon vertex detector (SVD) is described. The system is designed to meet the mechanical, electrical, and thermal requirements imposed by the BELLE detector. Its primary purpose is the amplification of analog signals from the VA1 front-end integrated circuits, which are used to read the silicon-strip detectors. It also provides a number of analog and digital functions related to the control and monitoring of the SVD. Much of the circuitry is implemented using programmable logic and analog devices, which allow a degree a flexibility in the design. In total, eight crates will be installed to read out the 81 920 strips from the three-layer double-sided silicon-strip detector array.