A new circuit configuration for a static memory cell with an area of 880 /spl mu/m/sup 2/
A new 5-transistor memory cell in double polysilicon technology with depletion-load elements and a minimum linewidth of 3 /spl mu/m is presented. The circuit configuration, based on a Schmitt trigger, leads to static memory cells having a bit density of 1100 bit/mm/SUP 2/ and an average power consumption of 5.5 /spl mu/W/cell. With the help of computer simulations the static and dynamic behavior of the basic circuit are calculated and discussed in detail as well as the two possible operation modes of the memory cell. These results compare favorably with the experimental results obtained on a realized 2/spl times/4 memory array. The performance of the proposed memory cell is the same as that of a conventional 6-transistor cell, but the area is reduced.
Two static 4K clocked and nonclocked RAM designs
A detailed description of both a clocked and a nonclocked n-channel MOS 4K static RAM is presented. The clocked device is a three-supply (+12 V, +5 V, -5 V) RAM which uses bootstrapping circuitry for signal driving, and sustaining resistors for low memory array power dissipation and infinite chip select length. The nonclocked device is a single supply (+5 V) fully TTL compatible RAM with depletion load circuitry for speed and compactness. Emphasis is given to processing parameters and performances as well as circuit design considerations including internal signal timings and circuit schematics.
Design of short-channel ion-implanted mosfets with relatively deep junctions
This paper discusses design considerations for short-channel ion-implanted MOSFET devices with relatively deep junctions. Four device parameters are considered: threshold and transconductance reduction, sub-threshold turn-on, and punch-through. Channel-length variations affect power and performance tolerances of enhancement/ depletion logic NOR gates in two ways: first, down-level current is inversely proportional to channel length; second, short-channel physical effects cause variations in transconductance and threshold voltage. It will be demonstrated that threshold and transconductance variations in short-channel devices tend to offset one another so their net contributions to tolerances on such circuit parameters as switching speed, down-level power and down-level voltage are negligible. Dual-energy ion implantation is used in the channel regions — a shallow implant to control threshold voltage, and a deep implant to control punch-through voltage. Hence high-resistivity (15 ohm-cm) substrates can be used to reduce junction capacitance. These implants are shown to have little effect on short-channel properties other than punch-through because the doses are low. Low channel doping and the relatively deep junctions contribute to a desirable, steep device turn-on characteristic. We concluded that short-channel effects do not have to be avoided in the design of small MOSFET devices. Using ion implantation and careful design, circuit tolerances can be maintained allowing parameters such as junction depth to be optimized for other criteria such as metallurgy compatibility.