Analysis of oxide bulk trapped charge distribution and densities from photo injection characteristics of oxide-nitride-oxide (ONO) structures
The thickness of ONO inter-poly dielectrics dominates the program and erase speed of a flash memory cell transistor with a stack gate structure. Therefore, as flash devices shrink, it is important to prevent the degradation in reliability while scaling down the thickness of the oxide. However, the thickness of the bottom oxide formed on a heavily doped poly-silicon cannot be easily reduced because of its high defect density due to a high concentration of dopants in the floating gate and an enhancement of the oxide thickness caused by oxidation of the doped polysilicon [1]. In order to overcome these problems, advanced LPCVD technology has been introduced, but the LPCVD oxide films still have many defect densities in comparison with thermal oxide films. In this work, the bulk trapped charges distribution and density in the bottom LPCVD oxide were quantitatively investigated by photocurrent-voltage characteristics. In addition, we found that the defect density and distribution in the bottom LPCVD oxide were remarkably decreased using post plasma oxidation.
Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices
This paper describes the scaling limitation factors of ONO interpoly dielectric thickness, mainly considering the charge retention capability and threshold voltage stability for nonvolatile memory cell transistors with a stacked-gate structure, based on experimental results. For good intrinsic charge retention capability, either the top- or bottom-oxide thickness should be greater than around 6 nm. On the other hand, a thicker top oxide structure is preferable to minimize degradation due to defects. It has been confirmed that a 3.2 nm bottom-oxide shows detectable threshold voltage instability, but 4 nm does not. Effective oxide thickness scaling down to around 13 nm should be possible for flash memory devices with a quarter-micron design rule.
High speed sub-halfmicron flash memory technology with simple stacked gate structure cell
This paper describes the novel process/device technology for high speed sub-halfmicron flash memories with 0.4 /spl mu/m design rules. Some new structures and operating methods for future flash memories have been proposed. However, the most suitable structure to realize large memory capacity for magnetic disk replacement will be different from that for fast random access speed for EPROM replacement, flash-memory-embedded logic devices, and other high speed applications. To realize high speed random access operation, conventional NOR-type flash memory technology with CHE program and source erase scheme will be the most suitable because of its simple fabrication process, relatively small cell size, sufficiently high read current, and relatively low operation voltages for program and erase procedures. The low voltage program/erase operation results in high performance peripheral transistors. On the other hand, NAND flash EEPROM will be the most suitable for low-cost large memory capacity applications. This paper, for the first time, demonstrates the scalability of cell gate length down to 0.4 /spl mu/m for simple stacked gate NOR flash cell.<<ETX>>