A simple Flash memory cell model for transient circuit simulation
A simple Flash memory cell model for circuit simulation is presented. The proposed model gives an excellent fitting of dc and transient data and does not require additional simulation time comparing with that of a MOSFET transistor. Effective control-gate voltage method and ideal current-mirror technique are introduced to calculate floating-gate voltage. These allow macro modeling of a Flash memory cell in a circuit simulator.
An Overview and Simulation Study of Conventional Flash Memory Floating Gate Device Using Concept F-N Tunnelling Mechanism
The aim of this paper is to present an overview, simulation and modeling study to improve the performance of Flash Memory (FM) devices such as programming speed and programming voltage. To improve the performing of FM device, the tunnel barrier thickness scaling is a major challenge. In current flash devices or conventional flash memory, single silicon oxide (SiO2) was obtained as a tunnel barrier and the thickness is approximately in the 5–10 nm range. Reducing the tunnel barrier below this range, will achieve low programming speed and high programming speed but the charge loss through also large. In order to achieve this research, the basic of semiconductor memory firstly was study include the programming tunneling mechanism and programming operation. Then the both structure techniques were simulated used TCAD software and lastly were model to calculate the electrical behavior like programming speed and programming voltage. The programming speed is calculated from the shift data of threshold voltage by varying the thickness of tunnel barrier and also the size of tunnel window. The models result will be compared to simulation and fabrication process to test the validity and accuracy of the specific W/E with current model develop. KeywordsProgramming speed, F-N Tunneling, Flash Memory Device, Non-Volatile memory Introduction
A theoretical model for the current-voltage characteristics of a floating-gate EEPROM cell
A model for current-voltage characteristics of an EEPROM cell has been developed and used in the simulation of an EEPROM test structure. It provides an explanation for the observed strong drain-induced barrier lowering effect and the role of trapped charge in the floating gate. In this model, the surface potential is related to the terminal voltages through an equivalent electrical circuit. Charge sheet and depletion approximation are used to describe the charge distribution in the semiconductor. Gradual approximation is assumed in deriving the drain current equation. A simplified drain current equation under a strong inversion condition is derived. An expression defining the extrapolated threshold voltage is obtained. It is useful in parameter extraction. A new method for extracting the drain coupling ratio and the channel coupling ratio is proposed. Finally, it is shown that extrapolated threshold voltage is a convenient quantity for classifying the threshold voltage of an EEPROM cell. >