Advanced activation and stability of ultra-shallow junctions using flash-assisted RTP
Advanced-logic device technology for the 65 nm node and beyond requires highly-activated, shallow, and abrupt dopant profiles (Int. Technol. Roadmap for Semicond., 2003). The combination of ion implantation and an advanced annealing technology is expected to provide solutions for these requirements. In contrast to spike annealing, a diffusion-less but highly activating, high-temperature, flash-assisted RTP annealing approach for the formation of ultra-shallow junctions will be demonstrated. The flash-assisted RTP technique is a promising method for achieving junction depth and sheet resistance values low enough to meet the performance specifications for the 65 nm node and beyond (Gelpey, et al., 2002, McCoy, et al., 2004). The optimal process for high activation during flash-assisted RTP involves a temperature ramp-up to an intermediate temperature between 700degC and 900degC and, once the intermediate temperature is reached, a very short, intense flash on the front side of the wafer induces a temperature jump up to 1325degC with a peak width of approximately 1.6 ms in a 100 ppm oxygen in nitrogen gaseous ambient. In this paper, we will present some of our recent p+MOS and n+MOS results on the fabrication of ultra-shallow junctions using flash-assisted RTP in crystalline and pre-amorphized silicon. It will be shown that such junctions are suitable for future technology generations. The measured "mechanical/electrical" sheet resistance values of the junctions are compared to Hall measurements on the same samples to gain an insight into the reliability of the destructive four-point probe (4PP) method for such extremely shallow junctions. Deactivation studies will be presented to examine the stability of the process to the required subsequent thermal processes
Experimental and theoretical results of dopant activation by a combination of spike and flash annealing
The diffusion length of the flash anneal is lowest for all different implant conditions. For the arsenic implant similar diffusion length is seen for all the processes that include a spike anneal due to the fact that the overall thermal budget is mainly determined by the spike anneal. Boron implants into crystalline as well as pre-amorphized silicon show similarly low sheet resistance independent of whether they are annealed with spike + flash, flash or flash + spike. For the arsenic implant by far the lowest sheet resistance is seen with a combination of spike + flash anneal. For the boron and arsenic implants the defect density after the flash anneal and the spike + flash anneal is below the weak beam dark field detection limit of the transmission electron microscope therefore suggesting low leakage due to defects present. From the simulations of the arsenic and the boron concentration profiles it can be learned that the spike profile determines the position of the chemical profile and the activation is increased by the subsequent diffusion-less flash anneal. Thus junction depth can be easily adjusted by the spike anneal condition in a spike + flash scheme, while still maintaining a high degree of dopant activation. This offers great flexibility to next generation junction formation. Although in this study the spike and flash annealing were performed in different tools, a combination of spike + flash can be easily run in the Mattson fRTPtrade system. The combination of spike + flash anneals also has been shown to improve the transistor drive current significantly without undesirable shifts in the other transistor characteristics.
Influence of Damage Depth Profile on the Characteristics of Shallow p+/n Implanted Junctions
Shallow p+/n junctions are produced by 10 keV boron implantation into self-ion preamorphized silicon and furnace annealing in the temperature range 600 to 1000 °C for 30 min. The electrical characteristics of the junction improve with increasing temperature, the strongest reverse current density IR decrease occurring between 700 and 800 °C. This diode behaviour is correlated with the profiles of the residual lattice strain, determined by double crystal X-ray diffraction on samples implanted with silicon ions. It is shown that interstitial clusters, characterizing the tail of implantation damage and surviving for T ≦ 700 °C, are much more effective on IR than the commonly observed dislocation loops. The disappearance of the clusters at 800 °C is closely related to the sharp drop in IR at the same temperature. On the contrary, the dislocation loops, responsible for the lattice strain observed up to 900 °C, have a moderate influence on IR and only when located in the space charge region. 
 
 
 
Flache p+/n-Ubergange werden durch 10 keV-Borimplantation in durch Selbstionen voramorphisiertem Silizium und 30 min Ofenausheizung im Temperaturbereich 600 bis 1000 °C hergestellt. Die elektrischen Charakteristiken des Ubergangs werden mit steigender Temperatur verbessert, der starkste Abfall der Sperrstromdichte IR tritt zwischen 700 und 800 °C auf. Dieses Diodenverhalten ist korreliert mit den Profilen der Gitterrestspannung, die mit Doppelkristallrontgenbeugung an mit Siliziumionen implantierten Proben bestimmt werden. Es wird gezeigt, das Zwischengitterstorstellencluster, die den Auslaufer des Implantationsschadens bilden und fur T ≦ 700 °C uberdauern, fur IR viel effektiver sind als die gewohnlich beobachteten Versetzungsschleifen. Das Verschwinden der Cluster bei 800 °C ist eng verknupft mit dem scharfen Abfall in IR bei derselben Temperatur. Im Gegensatz dazu, haben die Versetzungsschleifen, die fur die Gitterverspannung verantwortlich sind, die bei 900 °C beobachtet werden, nur einen geringen Einflus auf IR und nur wenn sie im Raumladungsbereich lokalisiert sind.