MOS-only design automation and a simple agile MOS-only BP/LP filter design
In this work, a systematic of the automation in the result of the re-obtained small signal parameters based on SPICE is presented for MOS-Only circuits. Accuracy of the re-obtained parameters was improved by re-formulating in the basis of SPICE and CADENCE-SPECTRE. Moreover, piece-wise polynomial regressive models are presented for gds, gm and Ids-Also, performance of the models are compared with conventional expressions. Success of the given MOS-Only design automation based on re-obtained small signal parameters is verified with an examplary new agile filter.
A new VDTA based frequency agile filter
In this study, a new voltage mode frequency agile filter designed by voltage differencing trans-conductance amplifier (VDTA) is presented. A single VDTA and two capacitors are used to implement the designed frequency agile filter. The MOS capacitor technique is used instead of conventional capacitors to achieve high operating frequencies. The agility of the designed filter is implemented by selecting different size MOS capacitor. The performance parameters of the VDTA and agile filter structure are summarized. The suitability of the filter for different applications are given. AMS 0.18μm parameters are used for the designed frequency agile filter.
Analog-baseband architectures and circuits for multistandard and lowvoltage wireless transceivers
Analog-Baseband Architectures and Circuits reviews the fundamentals and studies the state-of-the-art multistandard transceivers before describing novel architectural and circuit techniques for implementing multimode and wideband (tens of MHz) baseband analog front-ends under low-voltage constraints. Techniques developed on architecture level for efficient system-in-package (SiP) integration, testability and multi-standardability; and on circuit level for reducing the required supply voltage, power and area, are generally applicable for most wireless systems, and are somewhat independent to technology scaling. Experimental 1-V baseband building blocks (i.e., double-quadrature-downconversion filter, programmable-gain amplifier and dc-offset canceler) and a 1-V fully-integrated receiver analog-baseband chain for IEEE 802.11a/b/g WLAN validate the techniques. The implementations are all in standard-VTH CMOS process, and no voltage boosting is required at any node. Analog-Baseband Architectures and Circuits will be relevant to system architects, circuit designers, professors and students engaged in wireless transceiver front-ends research and development.