Height-selective etching for regrowth of self-aligned contacts using MBE
Advanced III-V transistors require unprecedented low-resistance contacts in order to simultaneously scale bandwidth, f max and f t with the physical active region [M.J.W. Rodwell, M. Le, B. Brar, in: Proceedings of the IEEE, 96, 2008, p. 748]. Low-resistance contacts have been previously demonstrated using molecular beam epitaxy (MBE), which provides active doping above 4 x 10 19 cm -3 and permits in-situ metal deposition for the lowest resistances [U. Singisetti, M.A. Wistey, J.D. Zimmerman, B.J. Thibeault, M.J.W. Rodwell, A.C. Gossard, S.R. Bank, Appl. Phys. Lett., submitted]. But MBE is a blanket deposition technique, and applying MBE regrowth to deep-submicron lateral device dimensions is difficult even with advanced lithography techniques. We present a simple method for selectively etching undesired regrowth from the gate or mesa of a III-V MOSFET or laser, resulting in self-aligned source/drain contacts regardless of the device dimensions. This turns MBE into an effectively selective area growth technique.
Fabrication of HfO2 patterns by laser interference nanolithography and selective dry etching for III-V CMOS application
Nanostructuring of ultrathin HfO2 films deposited on GaAs (001) substrates by high-resolution Lloyd's mirror laser interference nanolithography is described. Pattern transfer to the HfO2 film was carried out by reactive ion beam etching using CF4 and O2 plasmas. A combination of atomic force microscopy, high-resolution scanning electron microscopy, high-resolution transmission electron microscopy, and energy-dispersive X-ray spectroscopy microanalysis was used to characterise the various etching steps of the process and the resulting HfO2/GaAs pattern morphology, structure, and chemical composition. We show that the patterning process can be applied to fabricate uniform arrays of HfO2 mesa stripes with tapered sidewalls and linewidths of 100 nm. The exposed GaAs trenches were found to be residue-free and atomically smooth with a root-mean-square line roughness of 0.18 nm after plasma etching.PACS: Dielectric oxides 77.84.Bw, Nanoscale pattern formation 81.16.Rf, Plasma etching 52.77.Bn, Fabrication of III-V semiconductors 81.05.Ea
Phase characterisation of simulated high burn-up UO2 fuel
Abstract To determine the lattice constant variation with burn-up and the oxidation behaviour at high temperatures, simulated UO2-spent fuels with burn-ups up to 200 GWd tM−1 were prepared by cold pressing and sintering and characterised by X-ray diffraction analysis and thermogravimetry. The fcc-lattice parameter of the sintered samples determined at room temperature, showed a continuous decrease with the simulated burn-up. During oxidation the conversion of the simulated fuels to the (U,FP)4O9 and (U,FP)3O8-type phases was strongly delayed when the simulated burn-up exceeded 80 GWd tM−1. Also, at high burn-ups (>100 GWd tM−1), large fractions of the (U,FP)4O9-type phase remained untransformed to (U,FP)3O8 after prolonged exposure to air at 950–1000°C. This suggests a marked widening of the (U,FP)4O9-phase field when the amount of substituted uranium atoms exceeds values of about 8%.