SOI pixel detector based on CMOS time-compression charge-injection
Concept and experimental results obtained from a pixel detector based on CMOS time-compression charge- injection-devices (TC-CID) with a huge internal photocurrent amplification (-104), fabricated in CMOS silicon-on-insulator (SOI) technology are presented. Here, the readout circuitry is fabricated on highly-doped, 200 nm thick SOI film, while the photogate (PG) detector is fabricated on higher-resistivity handle wafer. The latter, together with the 30 V biasing possibilities enhances the quantum efficiency, especially for irradiations with wavelengths in the near-infra-red (NIR) part of the spectra.
Theoretical modeling and experimental investigation of MIS radiation sensor with giant internal signal amplification
Abstract Theoretical model, experimental investigation and a discussion of novel, extremely simple metal–insulator–semiconductor (MIS) capacitor-based integrating photodetectors are presented. These sensors can be used both, as high-speed photometers and weak radiation source sensors with a giant internal amplification of an input signal. Theoretical modeling explains the giant value of the internal signal amplification (of order of 10 6 ), defined as the ratio of the readout current peak value and the instantaneous photo current mean value. The samples are fabricated on both, high resistive (2–5 kΩ cm) n-type (1 0 0) silicon substrate and on ultra high resistive (UHR) epitaxial ( Epi ) layer ( ρ >10 kΩ cm) on highly doped ( ρ ≈0.01 Ω cm) (1 1 1) n-type silicon substrate wafers. The fabrication process is completely compatible with the standard C-MOS.
CMOS operational transconductance amplifier for PRML read channel applications
A CMOS operational transconductance amplifier (OTA) for partial-response maximum-likelihood (PRML) read channel applications is presented. Using mismatched (or unbalanced) differential pairs to increase linear input range yields an additional benefit: a pole-zero cancellation, independent of tuning, which allows a high output impedance stage to be incorporated into the design. The OTA was designed using a standard 0.35 /spl mu/m 3.3 V CMOS process-all simulation results presented use a supply voltage of 2.5 V. The maximum available linear input range is 250 mV/sub p-p/ at a unity-gain frequency of 100 MHz. The power consumption of the transconductor core and its associated folded-cascode output stage is 3 mW.