Research on Force and Thermal Phenomena of Short Circuited Melted Mark in Electrical Fire
This paper mainly does a research on force and thermal phenomena of short circuited melted mark in electrical fire. The primary short circuited melted mark and secondary short circuited melted mark were prepared by the experiment, and were characterized by metallographic microscope, powder X-ray diffraction, scanning electron microscope and energy dispersive spectroscopy, the role of forces and heat in short circuited melted mark in electrical fire were demonstrated and investigated. It is found that they show a similar shape that the melted ball close to one side for anode melted marks, and their particles show the specific and uniform direction and the most particle size of anode melted marks are larger than the particle size of cathode melted marks, both below the copper wire grain size 64.2nm, similarly, it can be clearly seen that the ratio of O: Cu in deposit layer of all melted marks are below 0.5. Finally, these above special phenomena gave short circuited melted mark the primary statement from the theoretical point of view.
Interface-controlled Gd2O3/GaAs system for ferroelectric memory application☆
Abstract The formation of Gd 2 O 3 /substrate-GaAs structure was accomplished by two-step electron-beam (e-beam) deposition including ultra-thin Gd-metal and successive Gd 2 O 3 layers. The deposition was carried out on HCl-cleaned GaAs containing elemental As on it. The pre-deposition of Gd-metal removes elemental As state in GaAs surface and forms interfacial state free from GaAs-oxides. However, Gd-metal turns to be oxide during the deposition by absorbing oxygen from GaAs surface and atmosphere. The successive deposition of Gd 2 O 3 was performed with in situ anneal of the substrate and this permitted preferential growth of Gd 2 O 3 with oriental relationship with substrate GaAs as Gd 2 O 3 {1 1 1}〈1 1 0〉||GaAs{0 0 1}〈4 7 0〉 with less than 1.5% of lattice mismatching. Capacitance–voltage ( C – V ) and current density–voltage ( J – V ) measurements indicated that the interface was seriously degraded when the anneal temperature exceeded 600 °C. The feasibility of Gd 2 O 3 film as a buffer layer for ferroelectric-gate/GaAs structure was proved.
Measuring Sheet Resistances of Dielectrics Using Co‐Planar Hydrogel Electrochemical Cells with Practical Applications to Characterize the Protective Quality of Paints on Sculptures
Electrical properties of thin dielectric films at the solid-liquid phase boundary are an important performance characteristic of many devices, coatings and sensors. In this paper, co-polymeric hydrogels of polyacrylic acid co-sulfonic acid, swollen with a salt solution to act as the solid electrolyte, were used to assess interfaces using electrochemical impedance spectroscopy (EIS) in a co-planar geometry. Silane-modified glasses were characterized by the co-planar hydrogel EIS cell and found to be distinguishable based on their surface monolayer chemistry. EIS measurements were also made on primed and painted metal substrates, using both test panels and an outdoor sculpture, Tony Smith's Stinger. The panels were then exposed to accelerated and outdoor weathering and showed degradation on the surface paint layers, which was observable electrochemically using EIS and confirmed visually by SEM. Electrochemical spectral features were compared between data from a standard paint-test cell versus this co-planar hydrogel cell; both cell types were able to measure coating capacitance, providing useful information about the condition of the bulk coating. Yet, sheet resistance (Rs) was a spectral feature seen only by the co-planar hydrogel cell. Thus, it can be concluded that the use of such co-planar hydrogel cells can provide an earlier warning sign to coating degradation and such cells provide a new type of spectral information that is not assessable by the standard geometry.