Layer misregistration in PCB and its effects on signal propagation
Layer misregistration is one of the common issues in PCB manufacturing processes. In addition to physical limitations of manufacturability (large via pad/anti-pad), it may also have impact on the electrical performance of signal lines running through via fields with anti-pad openings. In order to quantify its effects on signal propagation, comprehensive test vehicles were designed, measured, and analyzed. Significant increases in layer-to-layer crosstalk and common-to-differential mode conversion were observed, when corresponding layers were misaligned. The results helped understand the mechanisms, validate modeling methodology, and define design rules.
Signal propagation over perforated reference planes
Voids on reference planes are commonly seen in organic chip packages and printed circuit boards. In this paper, the effects of these voids on the signal integrity of a high-density data bus will be studied. A generic FCPBGA chip package is used to illustrate the signal integrity concerns and perform sensitivity analysis on the key mechanisms including void size, adjacent plane interactions, and adjacent signal line interactions. The results show that proper design can mitigate the signal integrity impact of reference plane voids.
Characterizing and Modeling the Impact of Power/Ground Via Arrays on Power Plane Impedance
In this paper, the impact of power/ground via arrays on power plane impedance is studied. 8 x 8 via array structures are characterized and the results are compared to fullwave field simulation using HFSS. These results show that the impedance and effective inductance is a strong function of location within the array. The lowest impedance is found on the array perimeter and the impedance is several times higher in the array center. The impact antipad size and dielectric thickness on the plane impedance and inductance is examined using parameterized models. Author Biography Jason Miller is currently a Staff Engineer at Sun Microsystems where he works on ASIC IO cell development, ASIC packaging, interconnect modeling and characterization, and system simulation. Jason received his Ph.D. in Electrical Engineering from Columbia University. Istvan Novak is a signal-integrity senior Staff Engineer at Sun Microsystems. Besides signal integrity design of high-speed serial and parallel buses, he is engaged in the design and characterization of power-distribution networks and packages for Sun servers. He creates simulation models, and develops measurement techniques for power distribution. Istvan has twenty plus years of experience with high-speed digital, RF and analog circuits, and system design. He is a Fellow of IEEE for his contributions to the fields of signal-integrity, RF measurements, and simulation methodologies. Jim DeLap is an Applications Engineer specializing in the High Frequency products including HFSS and Ansoft Designer. Prior to working at Ansoft, he has designed many products ranging from millimeter-wave mixers and antennas to integrated radios in the 30-60 GHz range. He earned his BSEE from the University of Lowell, Lowell, MA, his MSEE from the University of Virginia, Charlottesville, VA, and has worked for companies such as Millitech Corporation, Raytheon, and Agilent Technologies. Introduction This paper examines the impact of via arrays on the electrical characteristics of power/ground planes. Via arrays can be found underneath a package where the power/ground connections to the printed circuit board (PCB) are made using multiple power and ground vias. Package designers often incorporate multiple parallel vias to minimize the inductance incurred in connecting to the board power planes. With increasingly tight ball pitches, this results in a very dense pin or ball grid array field. The antipads associated with these via connections will perforate the plane region underneath the package, often to such an extent that only a thin web of metal exists underneath the package. Smaller antipad diameters can help to mitigate this effect but multilayer boards require a certain minimum antipad diameter to be manufacturable. As a consequence of these perforations, the power plane pair impedance can be significantly altered by the via array [1]. It has also been shown that the effective inductance of a plane pair increases with the density of the via array [2]. In this paper, we study the impact of different physical parameters on the power plane impedance and effective inductance. There are three parts to this paper. In the first part, the impedance of a test board consisting of an 8 x 8 array of vias is measured. These results are then correlated to full-wave electromagnetic field solution using HFSS [3]. In this second section we examine the simulation environment and the validity of various simplifying assumptions (e.g. losses). Lastly, the model is parameterized and by sweeping some of the physical parameters of the array such as antipad diameter and dielectric thickness we study the impact of the array’s physical dimensions on the power plane impedance. 1. Measurement Results A number of test boards were designed and fabricated which all had in common a 8 x 8 via array of alternating power/ground vias centered on a 2.5” square plane pair. Figure 1 shows a top view of the array illustrating the staggered arrangement of the power/ground vias. Power vias are identified by filled circles inside the hollow via cylinders. The openings in the power-ground plane pair are created by overlapping antipads. Here the antipad diameter is 58 mils and the via center-to-center distance is 50 mils, respectively. Each via pair can be uniquely identified using the row and column identifiers shown in Figure 1. For example, (A1,B1) corresponds to the via pair located in the bottom left hand corner. The matrix is fully symmetric; thus, (A1,B1) has the same geometry and environment as (G8,H8). Figure 2 shows a cross section of the top portion of the structure. The via diameter is 22 mils and the plated through holes (PTH) have a wall thickness of about 1.3 mils. The dielectric thickness is 8 um. 1 2 3 4 5 6 7 8 H G F E D C B A Figure 1: Via matrix arrangement. The array is centered on a 2.5” square plane pair that is not shown. An HP 4396B vector network analyzer (VNA) was used to measure the self-impedance magnitude and phase from 100 kHz to 1.8 GHz. With the board secured on its side, semirigid coaxial probes were used to contact the via pairs from opposite sides of the board. A full-two port calibration was performed. The power/ground via pairs were then measured as a function of pair location. Real and imaginary S21 measurement data were processed and the corrected self-impedance magnitude and phase was obtained [3]. In this arrangement, the parasitics associated with the via are in series with the source and load impedances. If the via impedance is small compared to the 50 ohm environment, its contribution can safely be ignored.