Novel Program Method of String Select Transistors for Layer Selection in Channel-Stacked NAND Flash Memory
In this paper, we propose new string select transistors (SSTs)/dummy SSTs (DSSTs) threshold voltage (Vth) setting methods in simplified channel-stacked array with layer selection by multilevel operation (SLSM). In these methods, SSTs/DSSTs on each layer are set to their targeted Vth values by incremental step pulse program/one erase with various erase voltages, respectively. In the fabricated pseudo-SLSM, the validity of the new methods is verified. As a result, it is confirmed that the Vth values of SSTs/DSSTs are set to the targeted Vth values by the new methods and SSTs with extremely narrow Vth distribution can be obtained in the consequence. Moreover, memory operations such as erase, program, and read are performed in the fabricated structure after setting the Vth values of all the SSTs/DSSTs by the new methods. Despite unique LSM operations, stable memory operations are obtained successfully without the interference between stacked layers.
Analysis on New Read Disturbance Induced by Hot Carrier Injections in 3-D Channel-Stacked NAND Flash Memory
Read disturbance is analyzed in vertically channel-stacked NAND flash memory, which has string select transistors (SSTs) to access each channel layer independently. Additional read disturbance is observed at the cells adjacent to the selected cell in the unselected channel layers as well as typical read disturbance caused by repetitive Fowler–Nordheim tunneling (F-N) stress. Technology computer-aided design simulations and measurements are performed to investigate the disturbance mechanisms. It is found that bitline-side [common-source line-side] adjacent cell is disturbed by the hot carrier injection (HCI), which results from positively [negatively] boosted channel potential by the rising [falling] of the voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{\text {unsel}}$ </tex-math></inline-formula>) applied to unselected cells, respectively. A novel read operation, in which the selected cells are maintained in turned on state during the <inline-formula> <tex-math notation="LaTeX">${V}_{\text {unsel}}$ </tex-math></inline-formula> rising/falling and then are restored to their own states, is proposed to suppress the occurrence of the HCIs. As a result, it is revealed that the HCI-induced read disturbances are successfully suppressed by the proposed method.
Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node
For the first time, the 3 dimensionally stacked NAND Flash memory, is developed by implementing S3 (single-crystal Si layer stacking) technology, which was used to develop S3 SRAM previously. The NAND cell arrays are formed on the ILD as well as on the bulk to double the memory density without increasing the chip size. The feasibility of the technology was proven by the successful operation of 32 bit NAND flash memory cell strings with 63nm dimension and TANOS structures. The novel NAND cell operational scheme, so called SBT (source-body tied) scheme, is presented to maximize the advantages of 3 dimensionally stacked NAND cell structures