Implementation of 16x16 SRAM memory array
SRAM is a main part of cache and it is used in many applications like microprocessor, date storage which occupy significant portion of die area and consume large fraction of energy. Memories should consume less power to improve system performance, stability, and efficiency. In this paper we have designed a 16x16 SRAM array, to reduce leakage power and the die area to maximize the performance. This was achieved by relaxing the area considerations of the peripherals, to a limited extent by designing peripheral which has less area and consumes less power. Further power consumption can be reduced by forced transistor technique and sleep transistor technique. It is seen from the analysis that sleep transistor technique shows 56.92 less power dissipation compared to forced stack transistor technique but forced technique shows 99.94 less delay than sleep technique. The 16x16 SRAM memory has been designed, implemented analyzed in standard UMC 180nm technology library using Cadence tool.
2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)