PERFORMANCE ANALYSIS OF A LOW POWER HIGH SPEED HYBRID 1 BIT FULL ADDER CIRCUIT USING CMOS TECHNOLOGIES USING
2 Assistant Professor, Department of ECE, Rajeev Institute of Technology, Hassan 573201 ABSTRACT: The general objective of our work is to investigate the power and delay performances of lowvoltage full adder cells in different CMOS logic styles for the predominating tree structured arithmetic circuits. A new hybrid style full adder circuit is also presented. The sum and carry generation circuits of the proposed full adder are designed with hybrid logic styles. To operate at ultra low supply voltage, the pass logic circuit that cogenerates the intermediate XOR and XNOR outputs has been improved to overcome the switching delay problem. As full adders are frequently employed in a tree structured configuration for high performance arithmetic circuits, a cascaded simulation structure is introduced to evaluate the full adders in a realistic application environment. A systematic and elegant procedure to scale the transistor for minimal power delay product is proposed. The circuits being studied are optimized for energy efficiency at 180nm, 90nm and 45nm CMOS process technology. With the proposed simulation environment, it is shown that some survival cells in standalone operation at low voltage may fail when cascaded in a larger circuit, either due to the lack of drivability or unsatisfactory speed of operation. The proposed hybrid full adder exhibits not only the full swing logic and balanced outputs but also strong output drivability. The increase in the transistor count of its complementary CMOS output stage is compensated by its area efficient layout. Therefore, it remains one of the be st contenders for designing large tree structured arithmetic circuits with reduced energy consumption while keeping the increase in area to a minimum. In this report the 1 bit proposed full adder circuit is designed and also it is also extended to 4 bits and the results of power and delay were also tabulated.