Design of a CMOS Broadband Transimpedance Amplifier with Floating Active Inductor
This work presents the design and performance of a transimpedance amplifier (TIA) implemented in a 180nm CMOS technology. The introduced TIA uses a floating active inductor (FAI) based on gyrator C structure, which is why it can increase the bandwidth while occupying a smaller chip area. And we have explained the schematic and characteristics of the gyrator C structure and FAI. In addition, the proposed TIA also uses the combination of capacitive degeneration, broadband matching network, and the regulated cascode (RGC) input stage, which turns the transimpedance amplifier (TIA) design into a fifth order low pass filter with butterworth response, to enhance the bandwidth and the gain. The TIA is implemented in 0.18 m Rohm CMOS technology and a 1.8 V supply. The transimpedance amplifier achieves a transimpedance gain of 41dBO and 3 dB frequency of 10 GHz with 0.1pF total input capacitance. Layout size of the proposed TIA is 180 mm x 118 mm.
2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)