A Reconfigurable Architecture for Posit Arithmetic
Physical layer of modern communication systems involves several floating point computations that require higher numerical fidelity and dynamic range for achieving the maximum data rate. Posit number format is a promising alternative for floating point computation as it provides a better dynamic range and numerical fidelity for the same number of bits used for representation. However, the Posit number format has not yet been thoroughly studied in the context of signal processing algorithms in the physical layer. In addition, a configurable Posit arithmetic hardware is essential for adapting to the ever changing communication standards and to configure the dynamic range according to algorithmic demands. The main contributions in this paper are: 1) Performance analysis of common signal processing algorithms using the Posit number format in comparison with the IEEE Standard for Single Precision Floating Point arithmetic (IEEE 754) 2) A novel reconfigurable hardware accelerator for Posit arithmetic operations and comparison with the state of the art Posit and IEEE Floating Point arithmetic architectures. Although our proposed architecture consumes over 3X energy and area compared to IEEE Single Precision arithmetic, our results show that using the Posit number format for physical layer algorithms results in significant performance gain. We achieved over 15 dB and 25 dB gain for FFT and matrix multiplication algorithms. In addition, compared to state of the art Posit arithmetic architecture, our proposed architecture resulted in over 2X speedup in operating frequency and 35% savings in energy consumption.
2019 22nd Euromicro Conference on Digital System Design (DSD)