Generic Architecture with Efficient Memory Arrangement for QC LDPC Codes Decoding
In this paper,a generic architecture for QC LDPC codes decoding is proposed.The novel architecture can perform decoding of multi standard LDPC codes with multiple rates and variable lengths by introducing a special binding schedule and a scalable shuffle network.The new memory arrangement improves usage efficiency of memories as many as 13 times.A salable data exchange network is proposed to regularize wire connections,which efficiently reduces the interconnection complexity.Based on SMIC 0.18um standard CMOS process,the LDPC decoder for Chinese DTMB standard has an estimation area of 8mm2 with 8 bit quantization,and a throughput of 91Mbps with a frequency of 50MHz and maximum iteration number of 15.