Efficient Encoding of Quasi Cyclic Low Density Parity Check Codes
A compact encoding process with three phases is proposed for quasi cyclic low density parity check (QC LDPC) codes. A back substitution circuit is shared at the first and third phases. A high speed vector dense matrix multiplier is well designed for the second phase, which offers tradeoffs between speed and memory. The proposed encoding method just removes some nonzero circulants of a sparse parity check matrix \pmb{H} while the classical Richardson Urbanke (RU) approach splits \pmb{H} into multiple submatrices and destroys its integrity. It is shown that the proposed encoder runs fast, has low complexity, and is well compatible with multiple code rates.
2018 IEEE 3rd Advanced Information Technology, Electronic and Automation Control Conference (IAEAC)