A New10 bit SAR ADC with Energy Efficient Switching in 0.35mm Process
his paper presents a novel method based on the reducing switches and capacitors at the output voltage DAC (Vdac) node, by selecting and applying the resistor string taps with the new technique on the SAR ADC's structure, as well. Simply, in the proposed technique, by decreasing the switches and capacitors of the Vdac node, it is capable to achieve a low settling time and low power consumption of 10 bit SAR ADC compared to the conventional similar methods and works, as well. Therefore, it is noteworthy that, by utilizing the proposed method to achieve a 10 bit accuracy, it is required just 63 switches instead of 1024 switches at the Vdac node, noticeably. The total power consumption of the proposed 10 bit SAR ADC is 9.66mW at power supply of 3.3 volts. The ADC shows a Signal to Noise Distortion Ratio (SNDR) of 56.29 dB and an Effective Number of Bits (ENOBs) of 9.03bits at 2MS/s, respectively. Simulation results of the proposed SAR ADC are simulated using the HSPICE BSIM3 model of a standard 0.35mm CMOS process at power supply of 3.3 volts.