NACHOS: Software Driven Hardware Assisted Memory Disambiguation for Accelerators
Hardware accelerators have relied on the compiler to extract instruction parallelism but may waste significant energy in enforcing memory ordering and discovering memory parallelism. Accelerators tend to either serialize memory operations [43] or reuse power hungry load store queues (LSQs) [8] [27] Recent works [11] [15] use the compiler for scheduling but continue to rely on LSQs for memory disambiguation. NACHOS is a hardware assisted software driven approach to memory disambiguation for accelerators. In NACHOS, the compiler classifies pairs of memory operations as NO alias (i.e. independent memory operations) MUST alias (i.e. ordering required) or MAY alias (i.e. compiler uncertain) We developed a compiler only approach called NACHOS SW that serializes memory operations both when the compiler is certain (MUST alias) and uncertain (MAY alias) Our study analyzes multiple stages of alias analysis on 135 acceleration regions extracted from SPEC2K, SPEC2k6, and PARSEC. NACHOS SW is en ergy efficient, but serialization limits performance; 18% 100% slowdown compared to an optimized LSQ. We then proposed NACHOS a low overhead, scalable, hardware comparator assist that dynamically verifies MAY alias and executes independent memory operations in parallel. NACHOS is a pay as you go approach where the compiler filters out memory operations to save dynamic energy, and the hardware dynamically checks to find MLP. NACHOS achieves performance comparable to an optimized LSQ; in fact, it improved performance in 6 benchmarks(6% 70% by reducing load to use latency for cache hits. NACHOS imposes no energy overhead in 15 out of 27 benchmarks i.e. compiler accurately determines all memory dependencies; the average energy overhead is ?6% of total (accelerator and L1 cache) in comparison, an optimized LSQ consumes 27% of total energy. NACHOS is released as free and open source software. Github: https:/github.com/sfu arch/ nachos
2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)