TDV Cache: Organizing Off Chip DRAM Cache of NVMM from a Fusion Perspective
Emerging Non Volatile Memory (NVM) provides both larger memory capacity and higher energy efficiency, but has much longer access latency than traditional DRAM, thus DRAM can be used as an efficient cache to hide the long latency of Non Volatile Main Memory (NVMM) system. Transparent Off chip DRAM cache (TOD cache) is a new DRAM cache structure where off chip DRAM module is used as L4 cache and managed by hardware. The capacity and latency ratio of TOD cache over NVM are both quite different from those of traditional on chip SRAM or die stacked DRAM cache over off chip DRAM memory. All the factors including hit latency, miss latency and hit rate need to be re considered for TOD cache design. In this study, we first point out that three types of traditional cache schemes cannot be used directly for TOD cache, since set associative cache suffers from extra tag lookup latency, direct mapped cache has low hit rate and tag cache is too small to efficiently hold the working sets of tags for DRAM cache. Based on these observations, we propose a novel cache scheme, TDV, that fuses these three different types of cache together to take their advantages. In TDV, a direct mapped cache is used as the first level cache to achieve short access latency, a set associative victim cache is taken as the second level cache to obtain extra high hit rate, and a SRAM tag cache only serves for the victim cache rather than the whole DRAM cache and thus improves the hit rate of tag cache significantly. The simulation results show that, TDV cache has a performance improvement of 6.3% and 8.3% on average than state of the art direct mapped (Alloy cache) and set associative cache (ATCache) with same DRAM and SRAM capacity.
2017 IEEE International Conference on Computer Design (ICCD)