FPGA Implementation of Image Enhancement using Verilog HDL
Image enhancement is one of the challenging issues in low level image processing. This paper discusses basic image enhancement techniques with their implementation and results using a Hardware Description Language, Verilog. The use of HDLs to provide signal processing results is quite new technique replacing the classical simulations and operating a direct connection to hardware VLSI implementations. The purpose of this paper is designing, modeling, simulation and synthesis of four image enhancement techniques on FPGA. Image enhancement operations can be classified as a point processing techniques, in which operation is done on pixel level and Spatial Filtering Technique, in which operation is performed within neighborhood of a pixel.