Design and implementation of I2C interface on FPGA for space borne AIS receiver in embedded system
This paper concentrates on the Automatic Identification System (AIS receiver) and various interfaces on FPGA which is used in the satellite. The AIS is used to detect a collision of ships. Vessels equipped with AIS provide vessel navigation information like their speed, location etc. Satellites that are fitted with S AIS receivers, receives the information and transmits it to the on board computers. Transmission of information requires various interfaces. The paper presents the design and implementation of I2C and MIL STD 1553 bus protocol, which interfaces FPGA board and on board computers in satellite and synthesized on Virtex 5 FPGA in Xilinx ISE 14.2 platform. The functional simulation of the bus is also carried under different test cases. Small satellites make use of an I2C bus. For the purpose of interfacing low speed peripheral device on FPGA, I2C bus which is a multi master, the two wire bi directional serial bus is used. The MIL STD 1553 bus is a standard data bus, mostly use in spacecraft on board data handling subsystem in the military. In this, communication is in between one master terminal called bus controller and other slave terminals called remote terminal (RT) MIL 1553 bus can hold up to 30 RT.