A HIGH PERFORMANCE NETWORK ON CHIP SYSTEM WITH PATH CONGESTION AWARE ADAPTIVE ROUTING
Network on chip is an emerging concept for communication within large VLSI systems implemented on a single silicon chip. Routing is an important parameter. The routing algorithm should be implemented by simple logic and number of data buffers should be minimal. So selection of routing algorithm is critical. I am going to propose an adaptive routing technique that increases the effectiveness of routing path selection based on channel based information and switch based information simultaneously. Existing adaptive schemes uses only channel based information for traffic monitoring and routing path selection, but channel based information alone is not sufficient to predict path congestion accurately. So, I am going to remodel the path congestion information to show covert spatial congestion information considering all the latencies such as router latency, buffer latency, packet latency etc. by employing path congestion aware adaptive routing strategy and contention prediction scheme for path congestion prediction. Finally, the efficiency, power and area consumption and cost requirements are compared with respect to other similar popular implementation to get optimized results.