Implementation of Secure Hash Algorithm 256
Hash functions play a significant ro le in today's cryptographic applications. SHA (Secure Hash Algorithm) is famous message compress standard used in computer cryptography, it can compress a long message to become a short message abstract. In this paper, SHA256 is implemented using Verilog HDL (Hardware Description Language) The SHA 256 Verilog source code is divided into three modules, namely Init ial, Round and Top module. The Verilog code is synthesized on Spartan 3E FPGA using Xilinx Chipscope Pro software tool. The test vectors have been applied to verify the correctness of the SHA 256 functionality. A comparison between the proposed SHA 256 hash function implementation with other related works shows that it achieves the introduced system can working higher operation frequency and needs less silicon area resources. The achieved performance in t he term of throughput of the proposed system/architecture is much higher than the other hardware implementations. The proposed system could be used for the implementation of integrity units, and in many other sensitive cryptographic applications, such as, digital signatures, message authentication codes and random number generators.