Fault tolerant FSM on FPGA using SEC DED code algorithm
This paper focuses on the design of an automatic error detection and correction of FSMs for soft errors. Single Event Upsets (SEUs) due to radiation impose an increasing problem to the reliable operation of FPGA used in communication, mile aero, automotive and industrial designs. By developing safe case sequential logic and fault tolerant state machines with error mitigation circuitry logic, the FPGA design can be protected from SEUs. When a soft error occurs, these method ensures safe design operation by returning the design to a known safe or reset state of operation. This logic provides reliable system operation. The objective of this work is to implement automatic error detection and correction of FSMs for single event upsets is presented. We also analyze how bit errors within same clock cycle can be removed by the addition of error checking bits using SEC DED code algorithm. The SEC DED is commonly used as error detection and correction since it is more efficient t han p arity c hecker. T he S EC DED c ode c an be used as the error detection and correction circuitry behind the FSMs to improve the reliable operation. The proposed architecture is simulated in VCS. This structure is synthesized in Xilinx Virtex 7 for implementing on FPGA. The result of the proposed design is analyzed and compared to determine its performance in terms of reliability.
2017 International Conference on Technological Advancements in Power and Energy TAP Energy)