Threshold voltage drift aware scheduling for belief propagation decoding of LDPC coded NAND flash memory
With the continual increase of storage density, NAND flash memory cells are particularly vulnerable to channel noise, which significantly degrades the storage reliability. To overcome this issue, low density parity check (LDPC) codes have been considered as a preferable choice for flash memory systems. To further improve the efficiency of the decoder, the convergence speed and the error rate performance are the key performance indicators for LDPC coded NAND flash memory. In this study, a threshold voltage drift aware scheduling for belief propagation (BP) decoding of LDPC coded NAND flash memory is introduced to improve the convergence speed and the error rate performance. The basic idea of the proposed scheduling is to find an appropriate updated order of variable nodes according to their corresponding locations of threshold voltages. Since the proposed scheduling updates less reliable variable nodes with higher priority, it can improve the efficiency of BP decoding. Simulation results show that the proposed scheduling not only significantly improves the convergence speed, but also obtains better error rate performance than the conventional serial scheduling.
IET Commun.