Hardware design of multiclass SVM classification for epilepsy and epileptic seizure detection
An automatic detection system for distinguishing healthy, ictal, and inter ictal EEG signals plays an important role in medical practice. This paper presents a very large scale integration (VLSI) architecture of three class classification for epilepsy and seizure detection. In order to find out the most efficient three class classification scheme for hardware implementation, several multiclass non linear support vector machine (NLSVM) classifiers are compared and validated using software implementation. Finally, the one against one (OAO) multiclass NLSVM is selected due to its highest accuracy. The designed system consists of a discrete wavelet transform (DWT) based feature extraction module, a modified sequential minimal optimization (MSMO) training module, and an OAO multiclass classification module. A lifting structure of Daubechies order 4 wavelet is introduced in three level DWT to save circuit area and speed up the computational time. The MSMO is used for on chip training. The circuit of the largest absolute value decision is designed to avoid the unclassifiable problem in the OAO multiclass classification. The designed system is implemented on a field programmable gate array (FPGA) platform and evaluated using the publicly available epilepsy dataset. The experimental results demonstrate that the designed system achieves high accuracy with low dimensional feature vectors.
IET Circuits Devices Syst.