Design of Low Floor Quasi Cyclic IRA Codes and Their FPGA Decoders
Low density parity check (LDPC) codes have been intensively studied in past decade for their capacity approaching performance. LDPC code implementation complexity and the error rate floor are still two significant unsolved issues which prevent their application in some important communication systems. In this dissertation, we make efforts toward solving these two problems by introducing the design of a class of LDPC codes called structured irregular repeat accumulate (SIRA) codes. These S IRA codes combine several advantages of other types of LDPC codes, including low encoder and decoder complexities, flexibility in design, and good performance on different channels. It is also demonstrated in this dissertation that the S IRA codes are suitable for rate compatible code family design and a multi rate code family has been designed which may be implemented with a single encoder/decoder. The study of the error floor problem of LDPC codes is very difficult because simulating LDPC codes on a computer at very low error rates takes an unacceptably long time. To circumvent this difficulty, we implemented a universal quasi cyclic LDPC decoder on a field programmable gate array (FPGA) platform. This hardware platform accelerates the simulations by more than 100 times as compared to software simulations. We implemented two types of decoders with partially parallel architectures on the FPGA: a circulant based decoder and a protograph based decoder. By focusing on the protograph based decoder, different soft iterative decoding algorithms were implemented. It provides us with a platform for quickly evaluating and analyzing different quasi cyclic LDPC codes, including the S IRA