ASIC Implementation of Soft Input Soft Output MIMO Detection Using MMSE Parallel Interference Cancellation
Multiple input multiple output (MIMO) technology is the key to meet the demands for data rate and link reliability of modern wireless communication systems, such as IEEE 802.11n or 3GPP LTE. The full potential of MIMO systems can, however, only be achieved by means iterative MIMO decoding relying on soft input soft output (SISO) data detection. In this paper, we describe the first ASIC implementation of a SISO detector for iterative MIMO decoding. To this end, we propose a low complexity minimum mean squared error (MMSE) based parallel interference cancellation algorithm, develop a suitable VLSI architecture, and present a corresponding four stream 1.5 mm2 detector chip in 90 nm CMOS technology. The fabricated ASIC includes all necessary preprocessing circuitry and exceeds the 600 Mb/s peak data rate of IEEE 802.11n. A comparison with state of the art MIMO detector implementations demonstrates the performance benefits of our ASIC prototype in practical system scenarios.
IEEE Journal of Solid State Circuits