Design high bandwidth density, low latency and energy efficient on chip interconnect
For future high performance computing chips, on chip interconnect requires large bandwidth density, low latency, and high energy efficiency, which pose significant design challenges. This paper presents a design space exploration of transmission line based on chip interconnect. First, we conduct an optimization of on chip transmission lines to minimize the size, channel loss and inter symbol interference (ISI) hence to maximize the bandwidth density. Based on the result, differential coplanar waveguide (CPW) with 55 um pitch size is chosen as the transmission line topology. Next, channel capacities of channel lengths from 2 to 8 cm are characterized based on time domain pulse responses. Various equalizers are studied, which are used to increase the ISI limited channel capacity. To make better use of the large equalized channel capacity, pulse amplitude modulation (PAM) is employed instead of traditional non return to zero (NRZ) signaling. A link budget analysis is then conducted to find the optimal modulation format for each channel. To verify our analyses, several transceivers are designed in 28 nm CMOS technology. An 84 Gb/s PAM 8 transceiver achieves 1.5 Gb/s/mm bandwidth density over a 4 cm channel. The unrepeated bandwidth density is 6.1 Gb/s/mm*cm, which is almost 10 times larger compared to prior work.
2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)