A 0.5 nJ/Pixel 4 K H.265/HEVC Codec LSI for Multi Format Smartphone Applications
A 4 K x 2 K H.265/HEVC video codec chip supporting 14 video standard formats is implemented on a 1.49 x 1.45 mm 2 die in a 28 nm CMOS process. Several HEVC fast algorithms reduce the coding modes by analyzing the content features leading to over 68.5% and 83% of complexity reduction in intra and inter coding, respectively. A fully parallel processing element (PE) array is adopted in SAO and IP/ME, which reduce number of accesses to SRAM by 48.7% and 78.4% respectively. A shared memory management unit (MMU) including line store SRAM pool (LSSP) and data bus translation (DBT) techniques efficiently reuses and packs the neighboring pixels which contribute 71.6% of external bandwidth reduction. This chip achieves 4096 x 2160@30 fps HEVC encoding/decoding and consumes 126.73 mW, 0.5 nJ/pixel of energy efficiency, under 494 MHz and 350 MHz of clock frequency, enabling 4 K video services for smart phone applications.
IEEE Journal of Solid State Circuits