High Throughput and Low Power Integrated Direct/Inverse HEVC Quantization Hardware Design
This paper presents a high throughput and low power integrated HEVC direct/inverse quantization hardware design. The main focus of this design is to allow the evaluation of multiple coding modes during the residual encoding process of the HEVC for real time Ultra High Definition (UHD) video processing. The ASIC synthesis results, for a Nangate 45nm standard cell library, presented a maximum operational frequency of 1679.51MHz and a processing rate of 53.74 Gsps (giga samples per second) This throughput allows processing of real time up to 72 coding modes for UHD 4K@60fps or up to nine coding modes for the UHD 8K@120fps while dissipating 369.37mW.
2018 IEEE International Symposium on Circuits and Systems (ISCAS)