A 13.5 ENOB, 107 mW Noise Shaping SAR ADC With PVT Robust Closed Loop Dynamic Amplifier
This article presents a second order noise shaping (NS) successive approximation register (SAR) analog to digital converter (ADC) with a process, voltage, and temperature (PVT) robust closed loop dynamic amplifier. The proposed closed loop dynamic amplifier combines the merits of closed loop architecture and dynamic operation, realizing robustness, high accuracy, and high energy efficiency simultaneously. It is embedded in the loop filter of an NS SAR design, enabling the first fully dynamic NS SAR ADC that realizes sharp noise transfer function (NTF) while not requiring any gain calibration. Fabricated in 40 nm CMOS technology, the prototype ADC achieves an SNDR of 83.8 dB over a bandwidth of 625 kHz while consuming only $107~\mu \text{W} It results in an SNDR based Schreier figure of merit (FoM) of 181.5 dB.
IEEE Journal of Solid State Circuits