Design of Power and Area Efficient Approximate Multipliers
Approximate computing can decrease the design complexity with an increase in performance and power efficiency for error resilient applications. This brief deals with a new design approach for approximation of multipliers. The partial products of the multiplier are altered to introduce varying probability terms. Logic complexity of approximation is varied for the accumulation of altered partial products based on their probability. The proposed approximation is utilized in two variants of 16 bit multipliers. Synthesis results reveal that two proposed multipliers achieve power savings of 72% and 38% respectively, compared to an exact multiplier. They have better accuracy when contrasted with existing estimated multipliers. Mean relative blunder figures are as low as 7.6% and 0.02% for the proposed inexact multipliers, which are superior to the past works. Execution of the proposed multipliers is assessed with a picture handling application, where one of the proposed models accomplishes the most astounding pinnacle flag to commotion proportion.