IC laser trimming speed up through wafer level spatial correlation modeling
Laser trimming is used extensively to ensure accurate values of on chip precision resistors in the presence of process variations. Such laser resistor trimming is slow and expensive, typically performed in a closed loop, where the laser is iteratively fired and some circuit parameter (i.e. current) is monitored until a target condition is satisfied. Toward reducing this cost, we introduce a novel methodology for predicting the laser trim length, thereby eliminating the closed loop control and speeding up the process. Predictions are obtained from waferlevel spatial correlation models, learned from a sparse sample of die on which traditional trimming is performed. Effectiveness is demonstrated on an actual wafer of laser trimmed ICs.
2014 International Test Conference