Design of Power and Area Efficient Lower Part OR Approximate Multiplier
Approximate computing has been paid attention as a promising technique to decrease power and area for error tolerant applications by simplifying the internal operations with sacrificing their accuracy. In this paper, a new power and area efficient approximate multiplier is proposed using OR based compressor with no carry propagation for lower bit positions and a carry propagation compressor with inexact half adders and full adders for upper bit positions. The proposal is effective to reduce the critical path delay with almost the same precision with previous methods. Firstly, an inexact half adder and an inexact full adder are proposed and a construction method of 4x4 multiplier is shown. Then, a construction method of 8x8 multiplier is proposed using OR based compressor, approximate 4x4 multipliers and an accurate 4x4 multiplier. The proposed construction method can also be applied to 16x16 multiplier. The accuracy loss of proposed multipliers is evaluated using MATLAB simulation and that of the proposed 8x8 multiplier is low as 0.20% the effect of which is shown to be negligible by applying to discrete cosine transform (DCT) inverse DCT and convolutional neural networks for image classification. The proposed 8x8 multiplier reduces power and area by 50.78% and 53.19% respectively, compared with the accurate Wallace tree multiplier when evaluated using SMIC 40nm process.
TENCON 2018 2018 IEEE Region 10 Conference