FPGA Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems
Embedded DRAM (eDRAM) requires frequent power hungry refresh according to the worst case retention time across PVT variations to avoid data loss. Abandoning the error free paradigm, by choosing sub critical refresh rates that gracefully degrade the eDRAM content, unlocks considerable power saving opportunities, but requires to understand the effect of stochastic memory errors at the system/application level. We propose an FPGA based platform featuring faulty eDRAM emulation based on advanced retention time models and silicon measurements for statistical error resilience evaluation of applications in a complete embedded system. We analyze the statistical QoS for various benchmarks under different sub critical refresh rates and retention time distributions.
2019 56th ACM/IEEE Design Automation Conference (DAC)