A Novel Single/Double Precision Normalized IEEE 754 Floating Point Adder/Subtracter
This paper demonstrates the design of a fully IEEE 754 compliant floating point adder and subtractor. This design focuses on creating a high speed, low power design while still adhering completely to the IEEE 754 standard. This design's novelty comes in the form of it's 64 bit prefix adder structure, and the parallelization of it's subcomponents. The adder/subtractor has full support for 32 bit and 64 bit operands, as well as the ability to convert integer operands to the IEEE 754 standard. Synthesis results presented use a cmos32soi 32nm CMOS technology and ARM standard cells.
2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)