15986742
DEFUSE: a deterministic functional self-test methodology for processors
At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-test. However, due to their reliance on random patterns, current logic BIST techniques are not able to deal with large designs without adding high test overhead. In this paper, we propose a functional self-test technique that is deterministic in nature. By targeting the structural test need of manageable components with the aid of processor functionality, this technique has the fault coverage advantage of deterministic structural testing and the at-speed advantage of functional testing. Most importantly, by relieving testers from test application, it enables at-speed testing of GHz processors with low speed testers. We have demonstrated our methodology on a simple accumulator-based microprocessor. The results show that with the proposed technique, we are able to apply high-quality at-speed tests with no test overhead.
5124709
Embedded hardware and software self-testing methodologies for processor cores
At-speed testing of GHz processors using external testers may not be technically and economically feasible. Hence, there is an emerging need for low-cost, high-quality self-test methodologies, which can be used by processors to test themselves at-speed. Currently, Built-In Self-Test (BIST) is the primary self-test methodology available and is widely used for testing embedded memory cores. In this paper, we report our experiences in applying a commercial BIST methodology to two processor cores and analyze the problems associated with the current hardware-based BIST methodologies. We propose a new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests. The software tester consists of programs for test generation and test application. Prior to the test, structural tests are prepared for processor components in the form of self-test signatures. During the process of self-test, the test generation program expands the self-test signatures into test sets, and the test application program applies the tests to the components-under-test at the speed of the processor. Application of the novel software-based self-test method demonstrates its significant cost/fault coverage benefits and its ability to apply at-speed test while alleviating the need for high-speed testers.
9508574
Embedded Software-Based Self-Test for Programmable Core-Based Designs
The programmable cores on SoCs can perform on-chip test generation, measurement, response analysis, and even diagnosis. This software-based approach to self-testing enables at-speed testing and incurs low DFT overhead. We give an overview of the existing embedded software-based self-testing and self-diagnosis methods for core-based SoC designs, and we discuss the challenges to further developing this new testing paradigm.
8887048
Using a Soft Core in a SoC Design: Experiences with picoJava
Through our experience in synthesis, validation, test, and integration of the picoJava processor core in a system-on-chip (SoC) design we point out the challenges faced and issues to address in efficient reuse of a soft core.
14133000
Software-based diagnosis for processors
Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed test of high-speed microprocessors using low-cost testers. We explore the fault diagnosis capability of SBST, in which functional information can be used to guide and facilitate the generation of diagnostic tests. By using a large number of carefully constructed diagnostic test programs, the fault universe can be divided into fine-grained partitions, each corresponding to a unique pass/fail pattern. We evaluate the quality of diagnosis by constructing diagnostic-tree-based fault dictionaries. We demonstrate the feasibility of the proposed method by applying it to a processor example. Experimental results show its potential as an effective method for diagnosing larger processors.
12599093
A scalable software-based self-test methodology for programmable processors
Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) that contain them. While early work on SBST has proposed several promising ideas, many challenges remain in applying SBST to realistic embedded processors. We propose a systematic scalable methodology for SBST that automates several key steps. The proposed methodology consists of (i) identifying test program templates that are well suited for test delivery to each module within the processor, (ii) extracting input/output mapping functions that capture the controllability/observability constraints imposed by a test program template for a specific module-under-test, (iii) generating module-level tests by representing the input/output mapping functions as virtual constraint circuits, and (iv) automatic synthesis of a software self-test program from the module-level tests. We propose novel RTL simulation-based techniques for template ranking and selection, and techniques based on the theory of statistical regression for extraction of input/output mapping functions. An important advantage of the proposed techniques is their scalability, which is necessitated by the significant and growing complexity of embedded processors.To demonstrate the utility of the proposed methodology, we have applied it to a commercial state-of-the-art embedded processor (Xtensa™ from Tensilica Inc.). We believe this is the first practical demonstration of software-based self-test on a processor of such complexity. Experimental results demonstrate that software self-test programs generated using the proposed methodology are able to detect most (95.2%) of the functionally testable faults, and achieve significant simultaneous improvements in fault coverage and test length compared with conventional functional test.
2454682
Mining Association Rules from Structural Deltas of Historical XML Documents
Previous work on XML association rule mining focuses on mining from the data existing in XML documents at a certain time point. However, due to the dynamic nature of online information, an XML document typically evolves over time. Knowledge obtained from mining the evolvement of an XML document would be useful in a wide range of applications, such as XML indexing, XML clustering. In this paper, we propose to mine a novel type of association rules from a sequence of changes to XML structure, which we call XML Structural Delta Association Rule (XSD-AR). We formulate the problem of XSD-AR mining by considering both the frequency and the degree of changes to XML structure. An algorithm, which is derived from the FP-growth, and its optimizing strategy are developed for the problem. Preliminary experiment results show that our algorithm is efficient and scalable at discovering a complete set of XSD-ARs.
32197027
A hardware accelerator for video segmentation using programmable morphology PE array
Video segmentation is a key operation for MPEG-4 and MPEG-7. It is a computationally intensive task and cannot be afforded by general microprocessors. In this paper, we propose a hardware accelerator for video segmentation. Since most of the core operations of video segmentation algorithms can be mapped to morphological operations, the core of this accelerator is a programmable morphology PE array. With the programmable ability of each PE and the interconnection between them, this accelerator can achieve both high throughput and high flexibility. Simulation shows the proposed hardware accelerator can speed up the most important video segmentation algorithms 20 times to achieve realtime performance and has high programmability with a little hardware cost overhead.
8972258
Designing oscillators in synthetic gene networks based on multi-scale dynamics
Multistability, oscillations, and switching exist at various levels of biological processes and organizations and have been investigated on the basis of many theoretical models, such as circadian oscillations with the period protein (PER) and the timeless protein (TIM) in Drosophila, and multistable dynamics regulated by transcriptional factors. Considerable experimental evidence suggests that cellular processes are intrinsically rhythmic or periodic. Various periodic oscillations with different time scales ranging from less than a second to more than a year, which may allow for living organisms to adapt their behaviors to a periodically varying environment, have also been observed experimentally. On the other hand, in synthetic gene networks, both toggle switch and repressilator have been theoretically proposed and further confirmed by experiments. All of these works stress the importance of feedback regulation of transcriptional factors, which is a key in giving rise to oscillatory or multistable dynamical behaviors exhibited by biological genetic systems. In addition, it should be noted that many periodic behaviors do not simply oscillate smoothly; rather, they change rapidly or jump at certain states. In gene expression systems, many different time scales characterize the gene regulatory processes. For instance, the transcription and translation processes generally evolve on a time scale that is much slower than that of phosphorylation, dimerization or binding reactions of transcription factors. In genetic networks, the time scale for expression of some genes is much slower than that of others, depending on the length of the genes. We aim to design robust periodic oscillators in synthetic gene-protein systems by simple nonlinear models and to analyze the basic mechanism of limit cycles with jumping behaviors or relaxation oscillations by exploiting multiple time-scale properties [1, 2]. We show that periodic oscillations are mainly generated by nonlinear feedback loops in gene regulatory systems and the jumping dynamics caused by time scale differences among biochemical reactions. Moreover, effects of time delay are also examined. We show that time delay generally enlarges the stability region of oscillations, thereby making the oscillations more sustainable despite parameter changes or noise [1, 2]. The dynamics of the proposed models is robust in terms of stability and period length to the parameter perturbations or environment variations. Although we mainly analyze some specific models, the mechanisms identified in this work are likely to apply to a variety of genetic regulatory systems. These simple models may actually act as basic building block in synthetic gene-protein networks, such as genetic oscillators or switches because the dynamics is robust for parameter perturbations or environment variations. Several examples are also provided to demonstrate implementation of synthetic oscillators by using genes of the /spl lambda/ phage bacteria.
441449
A novel ant clustering algorithm based on cellular automata
Based on the principle of cellular automata in artificial life, an artificial ant sleeping model (ASM) and an ant algorithm for cluster analysis (A4C) are presented. Inspired by the behaviors of gregarious ant colonies, we use the ant agent to represent a data object. In ASM, each ant has two states: a sleeping state and an active state. The ant's state is controlled by a function of the ant's fitness to the environment it locates and a probability for the ants becoming active. The state of an ant is determined only by its local information. By moving dynamically, the ants form different subgroups adaptively, and hence the data objects they represent are clustered. Experimental results show that the A4C algorithm on ASM is significantly better than other clustering methods in terms of both speed and quality. It is adaptive, robust and efficient, achieving high autonomy, simplicity and efficiency.
8727184
Estimating Link Capacity in High Speed Networks
Knowledge of bottleneck capacity of an Internet path is critical for efficient network design, management, and usage. With emerging high speed Internet links, most traditional estimation techniques are limited in providing fast and accurate capacity estimations. In this paper, we propose a new technique, called PBProbe, to estimate high speed links. PBProbe is based on CapProbe; however, instead of solely relying on packet pairs, PBProbe employs a “packet bulk” technique and adapts the bulk length in order to overcome the well known problem with packet pair based approaches, namely the lack of accurate timer resolution. As a result, PBProbe not only preserves the simplicity and speed of CapProbe, but it also correctly estimates link capacities within a much larger range. Using analysis, we evaluate PBProbe with various bulk lengths and network configurations. We then perform emulation and Internet experiments to verify the accuracy and speed of PBProbe on high speed links. The results show that PBProbe is consistently fast and accurate in the great majority of test cases.