14946468
Address assignment in DSP code generation - an integrated approach
One of the important issues in embedded system design is to optimize program code for the microprocessor to be stored in ROM. In this paper, we propose an integrated approach to the DSP address-code generation problem for minimizing the number of addressing instructions. Unlike previous works, in which code scheduling and offset assignment are performed sequentially without any interaction between them, our work tightly couples offset assignment problem with code scheduling to exploit scheduling on minimizing addressing instructions more effectively. We accomplish this by developing a fast but accurate two-phase assignment procedure which, for a sequence of code schedules, finds a sequence of memory layouts with minimum addressing instructions. Experimental results with benchmark DSP programs show improvements an average of 5.8% in the whole code size over the existing methods.
195882206
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design
The delay of memory access is one of the major bottlenecks in embedded systems' performance. In software compilation, it is known that there are high variations in memory access delay depending on the ways of storing/retrieving the variables in code to/from the memories. In this paper, we propose an effective storage assignment technique for variables to maximize the use of memory bandwidth. Specifically, we study the problem of DRAM memory layout for storing the nonarray variables in code to achieve a maximum utilization of page and/or burst modes for the memory accesses. The contributions of our work are, for each of page and burst modes: (1) We prove that the problem is NP-hard; (2) We propose an exact formulation of the problem and efficient memory layout algorithms, called Solve-MLP for the page mode and Solve-MLB for the burst mode; From experiments with a set of benchmark programs, we confirm that our proposed techniques use on average 20.0% and 9.9% more page accesses and 54.0% and 86.6% more burst accesses than those by OFU (the order of first use) and the technique in P.R. Panda et al. (1997), respectively.
29679621
Binding Algorithm for Power Optimization Based on Network Flow Method
We propose an efficient binding algorithm for power optimization in behavioral synthesis. In prior work, it has been shown that several binding problems for low-power can be formulated as multi-commodity flow problems (due to an iterative execution of data flow graph) and be solved optimally. However, since the multi-commodity flow problem is NP-hard, the application is limited to a class of small sized problems. To overcome the limitation, we address the problem of how we can effectively make use of the property of efficient flow computations in a network so that it is extensively applicable to practical designs while producing close-to-optimal results. To this end, we propose a two-step procedure, which (1) determines a feasible binding solution by partially utilizing the computation steps for finding a maximum flow of minimum cost in a network and then (2) refines it iteratively. Experiments with a set of benchmark examples show that the proposed algorithm saves the run time significantly while maintaining close-to-optimal bindings in most practical designs.
15341580
Optimal register reassignment for register stack overflow minimization
Architectures with a register stack can implement efficient calling conventions. Using the overlapping of callers' and callees' registers, callers are able to pass parameters to callees without a memory stack. The most recent instance of a register stack can be found in the Intel Itanium architecture. A hardware component called the register stack engine (RSE) provides an illusion of an infinite-length register stack using a memory-backed process to handle overflow and underflow for a physically limited number of registers. Despite such hardware support, some applications suffer from the overhead required to handle register stack overflow and underflow. The memory latency associated with the overflow and underflow of a register stack can be reduced by generating multiple register allocation instructions within a procedure [Settle et al. 2003]. Live analysis is utilized to find a set of registers that are not required to keep their values across procedure boundaries. However, among those dead registers, only the registers that are consecutively located in a certain part of the register stack frame can be removed. We propose a compiler-supported register reassignment technique that reduces RSE overflow/underflow further. By reassigning registers based on live analysis, our technique forces as many dead registers to be removed as possible. We define the problem of optimal register reassignment, which minimizes interprocedural register stack heights considering multiple call sites within a procedure. We present how this problem is related to a path-finding problem in a graph called a sequence graph. We also propose an efficient heuristic algorithm for the problem. Finally, we present the measurement of effects of the proposed techniques on SPEC CINT2000 benchmark suite and the analysis of the results. The result shows that our approach reduces the RSE cycles by 6.4% and total cpu cycles by 1.7% on average.
34887568
Memory access driven storage assignment for variables in embedded system design
42109913
An efficient low-power binding algorithm in high-level synthesis
We propose an efficient binding algorithm for power optimization in high-level synthesis. In prior work, it has been shown that several binding problems for low-power can be formulated as multi-commodity flow problems (due to an iterative execution of data flow graph) and be solved optimally. However, since the multi-commodity flow problem is NP-hard, the application is limited to a class of small sized problems. To overcome the limitation, we address the problem of how we can effectively make use of the property of efficient flow computations in a network so that it is extensively applicable to practical designs while producing close-to-optimal results. To this end, we propose an efficient two-step algorithm, which (1) determines a feasible binding solution by partially utilizing the computation steps for finding a maximum flow of minimum cost in a network and then (2) refines it iteratively. Experiments with a set of benchmark examples show that the proposed algorithm saves the run time significantly while maintaining close-to-optimal bindings in most practical designs.
253336
Parameter Optimization by a Genetic Algorithm for a Pitch Tracking System
The emergence of multimedia data in databases requires adequate methods for information retrieval. In a music data retrieval system by humming, the first stage is to extract exact pitch periods from a flow of signals. Due to the complexity of speech signals, it is difficult to make a robust and practical pitch tracking system. We adopt genetic algorithm in optimizing the control parameters for note segmentation and pitch determination. We applied the results to HumSearch, a commercialized product, as a pitch tracking engine. Experimental results showed that the proposed engine notably improved the performance of the existing engine in HumSearch.
4649924
WAF: wireless-adaptive fair scheduling for multimedia stream in time division multiplexed packet cellular systems
Cellular systems are designed to support voice service over the wireless channel but nowadays data-only networks such as cdma2000 1x EV-DO and high speed downlink packet access (HSDPA) are being deployed in the midst of evolution to the next generation wireless networks. Such systems become important because data services are essential in future wireless networks that are supposed to adopt the concept of all-IP to support integrated services. To increase the data transmission rate at downlink in cdma2000 1x EV-DO and HSDPA, the base station (BS) uses only a channel multiplexed by time division, not by code division. These systems use proportional fair scheduling to maximize throughput. While it is useful for non real time traffic, it does not provide appropriate QoS for real time services such as voice and video. Therefore we need to incorporate the multimedia QoS requirements into the design of a new scheduling algorithm. Our proposed wireless-adaptive fair scheduling (WAF) tries to allocate time slots with fair share according to the stream requirements considering the varying channel conditions to achieve good throughput. The simulation results show that our scheme can guarantee fair service and increase throughput by up to 41% compared to the purely fair (PF) scheduling scheme.
12101738
OpinionFinder: A System for Subjectivity Analysis
OpinionFinder is a system that performs subjectivity analysis, automatically identifying when opinions, sentiments, speculations, and other private states are present in text. Specifically, OpinionFinder aims to identify subjective sentences and to mark various aspects of the subjectivity in these sentences, including the source (holder) of the subjectivity and words that are included in phrases expressing positive or negative sentiments.
6312845
Energy exploration and reduction of SDRAM memory systems
In this paper, we introduce a precise energy characterization of SDRAM main memory systems and explore the amount of energy associated with design parameters, leading to energy reduction techniques that we are able to recommend for practical use.We build an in-house energy simulator for SDRAM main memory systems based on cycle-accurate energy measurement and state-machine-based characterizations which independently characterize dynamic and static energy. We explore energy behavior of the memory systems by changing design parameters such as processor clock, memory clock and cache configuration. Finally we propose new energy reduction techniques for the address bus and practical mode control schemes for the SDRAM devices. We save 10.8mJ and 12mJ, 40.2% and 14.5% of the total energy, for 24M instructions of an MP3 decoder and a JPEG compressor, using a typical 32-bit, 64MB SDRAM memory system.
17089899
Delay-Sensitive Packet Scheduling for a Wireless Access Link
As the delay is a critical QoS factor, packet scheduling over a wireless access link that often becomes congested needs to have the objective of meeting each user's delay requirement. To incorporate the delay into the scheduler design, we consider the objective of maximizing the total utility (UT). However, since a utility-based scheduler that concerns delay requires high complexity, we introduce the concept of marginal utility. Representing the objective as minimizing the total marginal utility (mt), we develop some related properties for maximizing UT and minimizing MT. For the case with fixed service time, we show that the outcome of MT minimization becomes equivalent to that of UT maximization. For the more complicated case of varying service time, the MT minimization sheds light on the design of a simple scheduler. Overall, the marginal utility requires significantly low complexity for packet scheduling compared to the ordinary utility. Through simulations, we confirm that the marginal utility gives a way of flexible scheduling in meeting various delay requirements