899366
Genetic Beam Search For Gate Matrix Layout
The paper presents a novel implementation of the genetic algorithm in combination with beam search for gate matrix layout. This is a permutation problem, for which the traditional genetic crossover operator results in repetition of gates, and therefore the GA is not applicable without modification. However, the GA is a very efficient stochastic optimisation technique, and is easily parallelisable. To adapt it to the gate matrix layout problem, the principles of beam search have been used. The gates are ranked according to their connectivity with each other, and the ranks of the gates to be placed next to each other are picked by the GA. A beam value is used to restrict the ranks of the gates placed next to each other to a low value. This reduces the search space to be explored, and thus results in a more efficient search. The algorithm produces better results compared to a graph-theoretic approach on published netlists.
27804822
On the compaction of test sets produced by genetic optimization
A previously proposed test generation procedure based on genetic optimization proved to have several advantages in terms of fault coverage; however, it produced large test set sizes. We investigate a way to generate compact test sets using this procedure by embedding it into a test compaction procedure. The compaction procedure constructs a compact test set out of the best tests contained in several test sets produced by the genetic optimization based test generation procedure. Using this approach, it is possible to significantly reduce the test set sizes obtained.
16583629
Placement for large-scale floating-gate field-programable analog arrays
Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. Our goal in this paper is to develop the first placement algorithm for large-scale floating-gate-based FPAAs with a focus on the minimization of the parasitic effects on interconnects under various device-related constraints. Our FPAA clustering algorithm first groups analog components into a set of clusters so that the total number of routing switches used is minimized and all IO paths are balanced in terms of routing switches used. Our FPAA placement algorithm then maps each cluster to a computational analog block (CAB) of the target FPAA while focusing on routing switch usage and balance again. Experimental results demonstrate the effectiveness of our approach
37046746
On the detection of delay faults
The class of faults known as gate delay faults are investigated. A taxonomy of the classes of gate delay fault detecting tests is provided. Methods to derive robust and nonrobust tests to detect gate delay faults are proposed. A physically meaningful measure to assess the efficacy of test sequences is introduced, and used to report fault coverages. A nine-valued logic system was proposed and used for deriving these tests. A physically meaningful measure, in the form of the average detection size of a test sequence. An algorithm was devised and implemented to automate the process of test generation, and results of experimentation with the ATPG, as well as with a random-pattern simulator, on four ISCAS-85 circuits were reported.<<ETX>>
18173256
Hierarchical placement for large-scale FPAA
Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. Our goal in this paper is to develop the first hierarchical placement algorithm for large-scale floating-gate based FPAAs with a focus on the minimization of the parasitic effects on interconnects under various device-related constraints. In our hierarchical approach, our FPAA clustering algorithm first groups analog components into a set of clusters so that the total number of routing switches used is minimized and all IO paths are balanced in terms of routing switches used. Our FPAA placement algorithm then maps each cluster to a computational analog block (CAB) of the target FPAA while focusing on routing switch usage again. Experimental results demonstrate the effectiveness of our approach.
40226126
SOC test scheduling using simulated annealing
We propose an SOC test scheduling method based on simulated annealing. In our method, the test scheduling is formulated as a two-dimensional bin packing problem (rectangle packing) and a data structure called a sequence pair is used to represent the placement of the rectangles. Simulated annealing is used to find the optimal test schedule by altering an initial sequence pair and changing the width of the core wrapper. We also propose a method of wrapper design for cores without internal scan chains. Experiments are conducted on ITC'02 benchmarks, showing that overall the proposed method provides better solutions compared to earlier methods.
11514442
A test pattern ordering algorithm for diagnosis with truncated fail data
In this paper, we propose a test pattern ordering algorithm for fault diagnosis. Test pattern ordering is effective in situations where the fail log is truncated and contains a limited number of fail data. In such cases, higher diagnostic resolution can be achieved with the test set appropriately ordered. Test pattern ordering is independent of the diagnosis algorithm used. The higher resolution achieved by test pattern ordering is obtained at no additional cost once the test patterns have been appropriately ordered. Experimental results on two industrial designs are presented to demonstrate the effectiveness of the proposed method