2872153
2D-profiling: detecting input-dependent branches with a single input data set
Static compilers use profiling to predict run-time program behavior. Generally, this requires multiple input sets to capture wide variations in run-time behavior. This is expensive in terms of resources and compilation time. We introduce a new mechanism, 2D-profiling, which profiles with only one input set and predicts whether the result of the profile would change significantly across multiple input sets. We use 2D-profiling to predict whether a branch's prediction accuracy varies across input sets. The key insight is that if the prediction accuracy of an individual branch varies significantly over a profiling run with one input set, then it is more likely that the prediction accuracy of that branch varies across input sets. We evaluate 2D-profiling with the SPEC CPU 2000 integer benchmarks and show that it can identify input-dependent branches accurately.
1551402
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths
This paper proposes a new processor architecture for handling hard-to-predict branches, the diverge-merge processor (DMP). The goal of this paradigm is to eliminate branch mispredictions due to hard-to-predict dynamic branches by dynamically predicating them without requiring ISA support for predicate registers and predicated instructions. To achieve this without incurring large hardware cost and complexity, the compiler provides control-flow information by hints and the processor dynamically predicates instructions only on frequently executed program paths. The key insight behind DMP is that most control-flow graphs look and behave like simple hammock (if-else) structures when only frequently executed paths in the graphs are considered. Therefore, DMP can dynamically predicate a much larger set of branches than simple hammock branches. Our evaluations show that DMP out performs a baseline processor with an aggressive branch predictor by 19.3% on average over SPEC integer 95 and 2000 benchmarks, through a reduction of 38% in pipeline flushes due to branch mispredictions, while consuming 9.0% less energy. We also compare DMP with previously proposed predication and dual-path/multipath execution paradigms in terms of performance, complexity, and energy consumption, and find that DMP is the highest performance and also the most energy-efficient design
7488858
Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors
Dynamic predication has been proposed to reduce the branch misprediction penalty due to hard-to-predict branch instructions. A proposed dynamic predication architecture, the diverge-merge processor (DMP), provides large performance improvements by dynamically predicating a large set of complex control-flow graphs that result in branch mispredictions. DMP requires significant support from a profiling compiler to determine which branch instructions and control-flow structures can be dynamically predicated. However, previous work on dynamic predication did not extensively examine the tradeoffs involved in profiling and code generation for dynamic predication architectures. This paper describes compiler support for obtaining high performance in the diverge-merge processor. We describe new profile-driven algorithms and heuristics to select branch instructions that are suitable and profitable for dynamic predication. We also develop a new profile-based analytical cost-benefit model to estimate, at compile-time, the performance benefits of the dynamic predication of different types of control-flow structures including complex hammocks and loops. Our evaluations show that DMP can provide 20.4% average performance improvement over a conventional processor on SPEC integer benchmarks with our optimized compiler algorithms, whereas the average performance improvement of the best-performing alternative simple compiler algorithm is 4.5%. We also find that, with the proposed algorithms, DMP performance is not significantly affected by the differences in profile- and run-time input data sets
13287397
An analysis of the performance impact of wrong-path memory references on out-of-order and runahead execution processors
High-performance, out-of-order execution processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction algorithms. Although memory references generated on the wrong path do not change the architectural state of the processor, they affect the arrangement of data in the memory hierarchy. This paper examines the effects of wrong-path memory references on processor performance. It is shown that these references significantly affect the IPC (instructions per cycle) performance of a processor. Not modeling them leads to errors of up to 10 percent (4 percent on average) in IPC estimates for the SPEC CPU2000 integer benchmarks on an out-of-order processor and errors of up to 63 percent on a runahead-execution processor. In general, the error in the IPC increases with increasing memory latency and instruction window size. We find that wrong-path references are usually beneficial for performance because they prefetch data that is used by later correct-path references. L2 cache pollution is found to be the most significant negative effect of wrong-path references. Code examples are shown to provide insights into how wrong-path references affect performance. We also show that it is crucial to model wrong-path references to accurately estimate the performance improvement provided by runahead execution.
8295029
Cache filtering techniques to reduce the negative impact of useless speculative memory references on processor performance
High-performance processors employ aggressive speculation and prefetching techniques to increase performance. Speculative memory references caused by these techniques sometimes bring data into the caches that are not needed by correct execution. This paper proposes the use of the first-level caches as filters that predict the usefulness of speculative memory references. With the proposed technique, speculative memory references bring data only into the first-level caches rather than all levels in the cache hierarchy. The processor monitors the use of the cache blocks in the first-level caches and decides which blocks to keep in the cache hierarchy based on the usefulness of cache blocks. It is shown that a simple implementation of this technique usually outperforms inclusive and exclusive baseline cache hierarchies commonly used by today's processors and results in IPC performance improvements of up to 9.2% on the SPEC2000 integer benchmarks.
11226719
Understanding the effects of wrong-path memory references on processor performance
High-performance out-of-order processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction algorithms. Although memory references generated on the wrong path do not change the architectural state of the processor, they can affect the arrangement of data in the memory hierarchy. This paper examines the effects of wrong-path memory references on processor performance. It is shown that these references significantly affect the IPC (Instructions Per Cycle) performance of a processor. Not modeling them can lead to errors of up to 10% in IPC estimates for the SPEC2000 integer benchmarks; 7 out of 12 benchmarks experience an error of greater than 2% in IPC estimates. In general, the error in the IPC increases with increasing memory latency and instruction window size.We find that wrong-path references are usually beneficial for performance, because they prefetch data that will be used by later correct-path references. L2 cache pollution is found to be the most significant negative effect of wrong-path references. Code examples are shown to provide insights into how wrong-path references affect performance.
8017153
Predicting how ontologies for the semantic web will evolve
The first phase in the evolution of the semantic Web may be the development of decentralized, adaptive ontologies for software specification.
41825214
XKMS-Based Key Management for Open LBS in Web Services Environment
As the killer application of the wireless internet, the LBS (Location-based Services) has reconsidered technology about location determination technology, LBS middleware server for various application, and diverse contents processing technology. For this kind of LBS, the role of security service is very important in the LBS that store and manage the location information of mobile devices and support various application services using those location information. And in all phases of these functions that include acquisition of location information, storage and management of location information, user management including authentication and information security, and management of the large-capacity location information database, safe security service must be provided. This paper describes a key management architecture based on XML standards for securing access to location based information and services. The main characteristic of the approach is that it build on a number of XML-based standards.
1329357
Data Reduction in Support Vector Machines by a Kernelized Ionic Interaction Model
A major drawback of support vector machines is their high computational complexity. In this paper, we introduce a novel kernelized ionic interaction (IoI) model for data reduction in support vector machines. We also present a data reduction method based on the kernelized instance based (KIB2) algorithm. We show that the computation time can be significantly reduced without any significant decrease in the prediction accuracy.
16407614
Requirements-based dynamic metrics in object-oriented systems
Because early design decisions can have a major long term impact on the performance of a system, early evaluation of the high-level architecture can be an important risk mitigation technique. This paper proposes a technique for predicting the volume of data that will flow across a network in a distributed system. The prediction is based upon anticipated execution of scenarios and can be applied at an extremely early stage of the design. It is driven by requirements specifications and captures dynamic metrics by defining typical usage patterns in terms of scenarios. Scenarios are then mapped to architectural components, and dataflow across inter-partition links is estimated. The feasibility of the approach is demonstrated through an experiment in which predicted metrics are compared to runtime measurements.
6043201
MOQ: Web services ontologies for QoS and general quality evaluations
When describing web services, one of the obvious aspects that need representing is 'Quality of Service' (QoS), the capability of a web service to meet an acceptable level of service as per factors such as availability and accessibility. However, too much of a focus on developing functional QoS ontologies has led to an over-emphasis on representing solely QoS metrics and units of measurement. For instance, what does round trip time actually mean? Is the round trip time of every data item measured? Is it an average, or is every nth item measured? Is it the actual measure that is important or just the percentage of items that are beyond a certain range? Arguably existing QoS ontologies cannot readily answer many of these design questions because these questions have less to do with evaluating QoS and more to do with representing 'what is quality?' Therefore, there is an unmet need for web services ontologies that are designed at a higher level encompassing domain independent concepts, and generally applicable beyond QoS evaluations. The MOQ set of ontologies, designed from the premise that quality is 'conformance to requirements', aims to fill this need. Comprised of ontologies of requirement, measurement, traceability, and quality management systems, MOQ can be extended to encompass QoS metrics and measurement units or be designed to interoperate with existing QoS ontology. The use of MOQ minimises the ambiguity in QoS evaluations.