18281114
Performance and functional verification of microprocessors
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of the validation problem: (a) verifying the functional integrity of the model and (b) testing the model for timing accuracy at the architectural level. The latter area, that of performance verification, is of increasing importance in the design of server-class processor chips, with one or more high performance cores on a single die. We show how simulation-based test cases can be generated under a unified defect and coverage model to detect both performance and functional bugs. We present and discuss examples of such integrated validation methodologies used in real processor development projects.
14558888
An Adaptive Issue Queue for Reduced Power at High Performance
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue queue for a superscalar processor that leverages transmission gate insertion to provide dynamic low-cost configurability of size and speed. A novel circuit structure dynamically gathers statistics of issue queue activity over intervals of instruction execution. These statistics are then used to change the size of an issue queue organization on-the-fly to improve issue queue energy and performance. When applied to a fixed, full-size issue queue structure, the result is up to a 70% reduction in energy dissipation. The complexity of the additional circuitry to achieve this result is almost negligible. Furthermore, self-timed techniques embedded in the adaptive scheme can provide a 56% decrease in cycle time of the CAM array read of the issue queue when we change the adaptive issue queue size from 32 entries (largest possible) to 8 entries (smallest possible in our design).
44925839
MHPS-Driven Early Design and Analysis of VLSI CPU Chips
JVe present (1 noid appsoaclz to carry per/i,rinancc analysis arid tiiiiitig of VLSI processors, don(? in the context of higlt-lewl source Iceriicls. U7e illustrate our rnetliodology in 1Crt71.r of a small (exaniph?) super scalas RlSC J ~ S O C ~ S S I ~ S architecture. A pnrantetrized execution 17ic~cIeI is used fhr piforinance eslimniion. IJsing an iterative optimization techniqire, the parameter set can bc locally optiinizcd around a g i i w design point to genesare tlie ininii?itrtn cycles per. iiwtrttction ( V I ) . W e also iiicludc a ctirsory discussion on linking .rirclt a CI’I estiiizntor io an early jloorplanner jhr A f IPS-driven block layout for the processor chb.
39390134
Ensuring dependable processor performance: an experience report on pre-silicon performance validation
The focus of today's processor validation methodology is primarily on ensuring functional integrity. Increasingly, however, pre-silicon performance validation is becoming part of the design verification challenge. Identification and elimination of performance deficiencies and bugs in the design prior to tape-out is an important aspect of building robust and dependable hardware. Many performance bugs are caused by latent functional defects in the pre-silicon software model of the machine. Besides, robust performance can be a key determinant of quality of service in applications like Web-serving. The authors review the performance validation methodology that they have developed and experimented with over the past few years. They also present examples and experimental results illustrating the use of this methodology in high end PowerPC processor development projects. The scope of the paper is limited to architectural performance, measured by metrics like instructions per cycle (IPC) or its inverse, CPI.
26499349
Early performance estimation of super scalar machine models
A novel methodology and software tool for estimating the performance of high-performance machine models with concurrent, pipelined execution modes are presented. Such performance assessment is typically useful at early stages of the design cycle. Critical design decisions made with the aid of early estimators of the kind discussed can be expected to yield near-optimal final designs.<<ETX>>
2521753
A circuit level implementation of an adaptive issue queue for power-aware microprocessors
Increasing power dissipation has become a major constraint for future performance gains in the design of microproces sors In this paper we present the circuit design of an issue queue for a superscalar processor that leverages transmis sion gate insertion to provide dynamic low cost con gura bility of size and speed A novel circuit structure dynami cally gathers statistics of issue queue activity over intervals of instruction execution These statistics are then used to change the size of an issue queue organization on the y to improve issue queue energy and performance When applied to a xed full size issue queue structure the result is up to a reduction in energy dissipation The complexity of the additional circuitry to achieve this result is almost neg ligible Furthermore self timed techniques embedded in the adaptive scheme can provide a decrease in cycle time of the CAM array read of the issue queue when we change the adaptive issue queue size from entries largest possible to entries smallest possible in our design
37907632
Packing Two Disks into a Polygonal Environment
We consider the following problem. Given a polygon P, possibly with holes, and having n vertices, compute a pair of equal radius disks that do not intersect each other, are contained in P, and whose radius is maximized. Our main result is a simple randomized algorithm whose expected running time, on worst case input, is O(n log n). This is optimal in the algebraic decision tree model of computation.
10971393
Efficient Algorithms for Guarding or Illuminating the Surface of a Polyhedral Terrain
We present eecient polynomial time algorithms that place bn=2c vertex guards which cover the surface of an n-vertex polyhedral terrain, and similarly, bn=3c edge guards which cover the surface of an n-vertex polyhedral terrain. The time complexity of both algorithms, dominated by the cost of nding a maximum matching in a graph, is O(n 3=2).
8889883
Diamond Triangulations Contain Spanners of Bounded Degree
Given a triangulation G, whose vertex set V is a set of n points in the plane, and given a real number γ with 0<γ<π, we design an O(n)-time algorithm that constructs a connected spanning subgraph G′ of G whose maximum degree is at most 14+⌈2π/γ⌉. If G is the Delaunay triangulation of V, and γ= 2π/3, we show that G′ is a t-spanner of V (for some constant t) with maximum degree at most 17, thereby improving the previously best known degree bound of 23. If G is the graph consisting of all Delaunay edges of length at most 1, and γ= π/3, we show that G′ is a t-spanner (for some constant t) of the unit-disk graph of V, whose maximum degree is at most 20, thereby improving the previously best known degree bound of 25. Finally, if G is a triangulation satisfying the diamond property, then for a specific range of values of γ dependent on the angle of the diamonds, we show that G′ is a t-spanner of V (for some constant t) whose maximum degree is bounded by a constant dependent on γ.
2308145
On computing enclosing isosceles triangles and related problems
Given a set of n points in the plane, we show how to compute various enclosing isosceles triangles where different parameters such as area or perimeter are optimized. We then study a 3-dimensional version of the problem where we enclose a point set with a cone of fixed apex angle α.
12387977
Testing the Quality of Manufactured Balls
We consider the problem of testing the roundness of a manufactured ball, using the finger probing model of Cole and Yap [4]. When the center of the object is known, a procedure requiring O(n2) probes and O(n2) computation time is described. (Here n = |1/q|, where q is the quality of the object.) When the center of the object is not known, the procedure requires O(n2) probes and O(n4) computation time. We also give lower bounds that show that the number of probes used by these procedures is optimal.