9029444
Workload-driven floorplanning for MIPS optimization
An approach to early floorplanning in which optimization of a CPU chip floorplan is done in the context of a program benchmark (workload) is presented. The methodology integrates workload-driven cycles-per-instruction estimation into the traditional cycle-time evaluation process implied by an (early) floorplanning tool. This effectively adds an extra dimension to the floorplanning optimization cost function and search space, allowing superior MIPS-tuning of the VLSI chip.<<ETX>>
18281114
Performance and functional verification of microprocessors
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of the validation problem: (a) verifying the functional integrity of the model and (b) testing the model for timing accuracy at the architectural level. The latter area, that of performance verification, is of increasing importance in the design of server-class processor chips, with one or more high performance cores on a single die. We show how simulation-based test cases can be generated under a unified defect and coverage model to detect both performance and functional bugs. We present and discuss examples of such integrated validation methodologies used in real processor development projects.
26499349
Early performance estimation of super scalar machine models
A novel methodology and software tool for estimating the performance of high-performance machine models with concurrent, pipelined execution modes are presented. Such performance assessment is typically useful at early stages of the design cycle. Critical design decisions made with the aid of early estimators of the kind discussed can be expected to yield near-optimal final designs.<<ETX>>
31462412
Performance evaluation and validation of microprocessors
The domain of early performance analysis and microarchitecture definition is limited largely to a onedimensional perspective of net performance: that of cyclesper-instnrction (CPI). Traceor execution-driven cycle-bycycle simulators [l] are the most common toolsets used at this stage. These are often coded in a systems programming language (e.g. C, C++, PWl or Pascal). They are performance-only models in that the register and memory data values and their state changes are not modelled; only the complex pipeline flow and concurrent instruction processing semantics are simulated. The goal here is to assess CPIcentric performance and bottlenecks to aid early definition, not to ensure functional integrity. Such a simulator, which we call a CPI timer; can be implemented to run at speeds greater than 50,000 instructions per second [21. This is achieved in modelling a future processor with the simulator running on a current generation uniprocessor workstation.
2521753
A circuit level implementation of an adaptive issue queue for power-aware microprocessors
Increasing power dissipation has become a major constraint for future performance gains in the design of microproces sors In this paper we present the circuit design of an issue queue for a superscalar processor that leverages transmis sion gate insertion to provide dynamic low cost con gura bility of size and speed A novel circuit structure dynami cally gathers statistics of issue queue activity over intervals of instruction execution These statistics are then used to change the size of an issue queue organization on the y to improve issue queue energy and performance When applied to a xed full size issue queue structure the result is up to a reduction in energy dissipation The complexity of the additional circuitry to achieve this result is almost neg ligible Furthermore self timed techniques embedded in the adaptive scheme can provide a decrease in cycle time of the CAM array read of the issue queue when we change the adaptive issue queue size from entries largest possible to entries smallest possible in our design
9413783
Optimal Code Generation for Expressions on Super Scalar Machines
10971393
Efficient Algorithms for Guarding or Illuminating the Surface of a Polyhedral Terrain
We present eecient polynomial time algorithms that place bn=2c vertex guards which cover the surface of an n-vertex polyhedral terrain, and similarly, bn=3c edge guards which cover the surface of an n-vertex polyhedral terrain. The time complexity of both algorithms, dominated by the cost of nding a maximum matching in a graph, is O(n 3=2).
123658090
Simultaneous diagonal flips in plane triangulations
Simultaneous diagonal flips in plane triangulations are investigated. It is proved that every triangulation with n ≥ 6 vertices has a simultaneous flip into a 4-connected triangulation, and that the set of edges to be flipped can be computed in $\cal O$(n) time. It follows that every triangulation has a simultaneous flip into a Hamiltonian triangulation. This result is used to prove that for any two n-vertex triangulations, there exists a sequence of $\cal O$(logn) simultaneous flips to transform one into the other. Moreover, o(log n) simultaneous flips are needed for some pairs of triangulations. The total number of edges flipped in this sequence is $\cal O$(n). The maximum size of a simultaneous flip is then studied. It is proved that every triangulation has a simultaneous flip of at least ${{1}\over{3}}({n}-{2})$ edges. On the other hand, every simultaneous flip has at most n - 2 edges, and there exist triangulations with a maximum simultaneous flip of ${{6}\over{7}}({n}-{2})$ edges. © 2006 Wiley Periodicals, Inc. J Graph Theory 54: 307–330, 2007 
 
A preliminary version of this paper was published in the Proceedings of the 17th Annual ACM-SIAM Symposium on Discrete Algorithms (SODA'06). 
 
Research partially completed at Carleton University and McGill University (Montreal).
7055991
Feature-based cut detection with automatic threshold selection
There has been much work concentrated on creating accurate shot boundary detection algorithms in recent years. However a truly accurate method of cut detection still eludes researchers in general. In this work we present a scheme based on stable feature tracking for inter frame differencing. Furthermore, we present a method to stabilize the differences and automatically detect a global threshold to achieve a high detection rate. We compare our scheme against other cut detection techniques on a variety of data sources that have been specifically selected because of the difficulties they present due to quick motion, highly edited sequences and computer-generated effects.
1326368
Area-preserving approximations of polygonal paths
Let P be an x-monotone polygonal path in the plane. For a path Q that approximates P let W"A(Q) be the area above P and below Q, and let W"B(Q) be the area above Q and below P. Given P and an integer k, we show how to compute a path Q with at most k edges that minimizes W"A(Q)+W"B(Q). Given P and a cost C, we show how to find a path Q with the smallest possible number of edges such that W"A(Q)+W"B(Q)=
1804621
The Maximum Number of Edges in a Three-Dimensional Grid-Drawing
An exact formula is given for the maximum number of edges in a graph that admits a three-dimensional grid-drawing contained in a given bounding box. The first universal lower bound on the volume of threedimensional grid-drawings is obtained as a corollary. Our results generalise to the setting of multi-dimensional polyline grid-drawings.