153966
Compiling for the Impulse memory controller
The Impulse memory controller provides an interface for remapping irregular or sparse memory accesses into dense accesses in the cache memory. This capability significantly increases processor cache and system bus utilization, and previous work shows performance improvements from a factor of 1.2 to 5 with current technology models for hand-coded kernels in a cycle-level simulator. To attain widespread use of any specialized hardware feature requires automating its use in a compiler. We present compiler cost models using dependence and locality analysis that determine when to use Impulse to improve performance based on the reduction in misses, the additional cost for misses in Impulse, and the fixed cost for setting up a remapping. We implement the cost models and generate the appropriate Impulse system calls in the Scale compiler framework. Our results demonstrate that our cost models correctly choose when and when not to use Impulse. We also combine and compare Impulse with our implementation of loop permutation for improving locality. If loop permutation can achieve the same dense access pattern as Impulse, we prefer it, since it has no overheads, but we show that the combination can yield better performance.
9720590
Using the compiler to improve cache replacement decisions
Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with LRU replacement policies to combine fast access with relatively low miss rates. To improve replacement decisions in set-associative caches, we develop a new set of compiler algorithms that predict which data will and will not be reused and provide these hints to the architecture. We prove that the hints either match or improve hit rates over LRU. We describe a practical one-bit cache-line tag implementation of our algorithm, called evict-me. On a cache replacement, the architecture will replace a line for which the evict-me bit is set, or if none is set, it will use the LRU bits. We implement our compiler analysis and its output in the Scale compiler. On a variety of scientific programs, using the evict-me algorithm in both the level 1 and 2 caches improves simulated cycle times by up to 34% over the LRU policy by increasing hit rates. In addition, a combination of simple hardware prefetching and evict-me works together to further improve performance.
18764674
Image information restoration based on long-range correlation
A new class of image information restoration algorithms, virtually different from traditional techniques, is proposed. In comparison with other approaches, our methods use not only the information in local areas, but also that in the remote regions of the image. The methods originate from the idea that there exists abundant long-range correlation within natural images and the human vision system, composed of our eyes and brains, can sufficiently utilize such types of information redundancy to implement the functions of image interpretation, representation, restoration, enhancement and error concealment. Our general approach can be summarized as five basic steps: fetching, searching, matching, competing and recovering. The experimental results on several practical applications show that our methods perform substantially better than many other state-of-the-art methods.
28306753
Low hardware complexity parallel turbo decoder architecture
Turbo decoders inherently have low throughput and long latency because of iterative decoding. Parallel processing is a powerful technique for high-throughput applications but often comes with large hardware complexity penalties. In this paper, we present a generic low hardware complexity parallel turbo decoder architecture, which enables multiple soft-input soft-output (SISO) decoders to process one data frame simultaneously. It can achieve multiple times the throughput of a typical serial decoder with a small fraction of hardware overhead. The proposed architecture works for any type of random interleavers, which makes it extremely useful in practical applications where turbo interleave patterns are not free to design. Based on estimation, the illustrated low hardware complexity 2-level parallel turbo decoding architecture can achieve twice the throughput of a typical serial decoding architecture with less than 20% hardware overhead when applied to 3rd generation CDMA systems.
17971442
Exogenous connectors for software components
In existing component models, control originates in components, and connectors are channels for passing on the control to other components. This provides a mechanism for message passing, which allows components to invoke one another's operations by method calls (or remote procedure calls) either directly or indirectly via a channel such as a bus. Thus components in these models mix computation with control, since in performing their computation they also initiate method calls and manage their returns, via connectors. Consequently, in terms of control, components are not loosely coupled. In this paper, we propose exogenous connectors, and demonstrate their use in a small example. In contrast to connectors in existing component models, exogenous connectors initiate calls and manage their returns, and are used to encapsulate control in a component model we are working on. In the example, we demonstrate the feasibility of exogenous connectors, and compare them with connectors in closely related architecture description languages.
18979975
Integrated MicroPhotonic wideband RF interference mitigation filter
MicroPhotonic broadband RF signal processors utilize true-time-delay methods to perform processing functions that cannot be achieved by conventional electronic methods. In addition to their small physical size and immunity to EMI, Photonic signal processors offer the possibility of delaying broadband RF signals with almost no loss. In this paper, we present a novel MicroPhotonic structure that integrates a photoreceiver array, a Vertical Cavity Surface Emitting Laser (VCSEL) array, and a multi-cavity optical substrate to realize a low-cost adaptive wideband RF interference mitigation filter. Results show that for a 64-cavity MicroPhotonic structure, high-resolution, tunable interference mitigation filter with a shape factor as low as 2 and passband ripples less than 0.25 dB can be realised.
13893124
Lifetime Maximization of Sensor Networks Under Connectivity and k-Coverage Constraints
In this paper, we study the fundamental limits of a wireless sensor network's lifetime under connectivity and k-coverage constraints. We consider a wireless sensor network with n sensors deployed independently and uniformly in a square field of unit area. Each sensor is active with probability p, independently from others, and each active sensor can sense a disc area with radius rs. Moreover, considering the inherent irregularity of a sensor's sensing range caused by time-varying environments, we model the sensing radius rs as a random variable with mean r0 and variance r$_{\rm 0}^{\rm 2}$σ$_{s}^{\rm 2}$. Two active sensors can communicate with each other if and only if the distance between them is smaller than or equal to the communication radius rc. 
 
The key contributions of this paper are: (1) we introduce a new definition of a wireless sensor network's lifetime from a novel probabilistic perspective, called ω-lifetime (0 ≤ ω ≤ 1). It is defined as the expectation of the time interval during which the probability of guaranteeing connectivity and k-coverage simultaneously is at least ω; and (2) based on the analysis results, we propose a near-optimal scheduling algorithm, called PIS (Pre-planned Independent Sleeping), to achieve the network's maximum ω-lifetime, which is validated by simulation results, and present a possible implementation of the PIS scheme in the distributed manner.