16975527
Nonseparating Cycles in 4-Connected Graphs
We prove that given any fixed edge ra in a 4-connected graph G, there exists a cycle C through ra such that G-(V(C)-{r}) is 2-connected. This will provide the first step in a decomposition for 4-connected graphs. We also prove that, for any given edge e in a 5-connected graph G, there exists an induced cycle C through e in G such that G-V(C) is 2-connected. This provides evidence for a conjecture of Lovasz.
21169395
Small Circuit Double Covers of Cubic Multigraphs
Let G be a two-connected graph. A family F of circuits of G is called a circuit double cover (CDC) if each edge of G is contained in exactly two circuits of F. In this paper, we show that if a simple cubic graph G (G ? K4) of order n has a CDC, then G has a CDC containing at most n/2 circuits. This result establishes the equivalence of the circuit double cover conjecture (due to Szekeres, Seymour) and the small circuit double cover conjecture (due to Bondy) for any cubic graph. Actually, a stronger result is obtained in this paper for all loopless cubic graphs. Another result in this paper establishes an upper bound on the size of any CDC of a cubic graph.
8637971
Infinite paths in planar graphs II, structures and ladder nets
A graph is k-indivisible, where k is a positive integer, if the deletion of any finite set of vertices results in at most k − 1 infinite components. In 1971, NashWilliams conjectured that a 4-connected infinite planar graph contains a spanning 2-way infinite path if, and only if, it is 3-indivisible. In this paper, we prove a structural result for 2-indivisible infinite planar graphs. This structural result is then used to prove Nash-Williams conjecture for all 4-connected 2-indivisible infinite planar graphs. ∗Partially supported by NSF grants DMS-9531824 and DMS-9970527
122697425
Infinite paths in planar graphs I: Graphs with radial nets
Let G be an infinite 4-connected planar graph such that the deletion of any finite set of vertices from G results in exactly one infinite component. Dean et al. proved that either G admits a radial net or a special subgraph of G admits a ladder net, and they used these nets to show that G contains a spanning 1-way infinite path. In this paper, we show that if G admits a radial net, then G also contains a spanning 2-way infinite path. This is a step towards a conjecture of Nash-Williams. © 2004 Wiley Periodicals, Inc. J Graph Theory 47: 147–162, 2004
1160338
Graph Connectivity After Path
Removal
Let G be a graph and
u, v be two distinct vertices of
G. A u—v path P is called nonseparating if
G—V(P) is connected. The purpose of this
paper is to study the number of nonseparating
u—v path for two arbitrary
vertices u and
v of a given graph. For a
positive integer k, we will
show that there is a minimum integer α(k) so that if G is an α(k)-connected graph and
u and v are two arbitrary vertices in
G, then there exist
k vertex disjoint paths
P1[u,v], P2[u,v], . . ., Pk[u,v], such that G—V (Pi[u,v]) is connected for every
i (i = 1, 2, ..., k). In fact, we will prove that
α(k) ≤ 22k+2. It is known that α(1) = 3.. A
result of Tutte showed that α(2) = 3. We show that α(3) = 6. In
addition, we prove that if G
is a 5-connected graph, then for every pair of vertices
u and v there exists a path
P[u, v] such that G—V(P[u,
v]) is 2-connected.
11130888
On 3-connected graphs with contractible edge covers of size k
Abstract We consider 3-connected graphs whose contractible edges can be covered by k vertices and show that they can be divided into finitely many infinite classes of graphs.
1493351
Circuit Design Style for Energy Efficiency: LSDL and Compound Domino
Introduction of sub-90nm technology has made a profound impact on circuit designs. Thus, it requires understanding of existing design styles for desired energy-efficiency. We compare adder designs in the energy-delay space, implemented with Limited Switch Dynamic Logic (LSDL) and Compound Domino Logic (CD) in a 65nm SOI technology. Evaluation results show that LSDL can provide more than 35% energy savings than CD with 25% switching activity at relaxed cycle times greater than 10.5 F04.
1419192
Trading capacity for performance in a disk array
A variety of performance-enhancing techniques, such as striping, mirroring, and rotational data replication, exist in the disk array literature. Given a fixed budget of disks, one must intelligently choose what combination of these techniques to employ. In this paper, we present a way of designing disk arrays that can flexibly and systematically reduce seek and rotational delay in a balanced manner. We give analytical models that can guide an array designer towards optimal configurations by considering both disk and workload characteristics. We have implemented a prototype disk array that incorporates the configuration models. In the process, we have also developed a robust disk head position prediction mechanism without any hardware support. The resulting prototype demonstrates the effectiveness of the configuration models.
12758700
Distributed cache updating for the dynamic source routing protocol
On-demand routing protocols use route caches to make routing decisions. Due to mobility, cached routes easily become stale. To address the cache staleness issue, prior work in DSR used heuristics with ad hoc parameters to predict the lifetime of a link or a route. However, heuristics cannot accurately estimate timeouts because topology changes are unpredictable. In this paper, we propose proactively disseminating the broken link information to the nodes that have that link in their caches. We define a new cache structure called a cache table and present a distributed cache update algorithm. Each node maintains in its cache table the information necessary for cache updates. When a link failure is detected, the algorithm notifies all reachable nodes that have cached the link in a distributed manner. The algorithm does not use any ad hoc parameters, thus making route caches fully adaptive to topology changes. We show that the algorithm outperforms DSR with path caches and with Link-MaxLife, an adaptive timeout mechanism for link caches. We conclude that proactive cache updating is key to the adaptation of on-demand routing protocols to mobility.
1886676
Monitoring k-nearest neighbor queries over moving objects
Many location-based applications require constant monitoring of k-nearest neighbor (k-NN) queries over moving objects within a geographic area. Existing approaches to this problem have focused on predictive queries, and relied on the assumption that the trajectories of the objects are fully predictable at query processing time. We relax this assumption, and propose two efficient and scalable algorithms using grid indices. One is based on indexing objects, and the other on queries. For each approach, a cost model is developed, and a detailed analysis along with the respective applicability is presented. The object-indexing approach is further extended to multi-levels to handle skewed data. We show by experiments that our grid-based algorithms significantly outperform R-tree-based solutions. Extensive experiments are also carried out to study the properties and evaluate the performance of the proposed approaches under a variety of settings.
16035202
An efficient transistor optimizer for custom circuits
We present an equation-based transistor size optimizer that minimizes delay of custom circuits. Our method uses static timing analysis to find the critical paths and numerical methods to optimize transistor sizes continuously without using simulation. Consequently, it is faster than simulation-based optimizers, and more general than standard cell optimizers. We demonstrate its efficacy and accuracy on a complete dynamic adder presented, where we achieve a 54% speed-up, and final critical path delay that match Spice within 1%.