902904
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula
System design methodology is poised to become the next big enabler for highly sophisticated electronic products. Design verification continues to be a major challenge and simulation will remain an important tool for making sure that implementations perform as they should. In this paper we present algorithms to automatically generate C++ checkers from any formula written in the formal quantitative constraint language, Logic Of Constraints (LOC). The executable can then be used to analyze the simulation traces for constraint violation and output debugging information. Different checkers can be generated for fast analysis under different memory limitations. LOC is particularly suitable for specification of system level quantitative constraints where relative coordination of instances of events, not lower level interaction, is of paramount concern. We illustrate the usefulness and efficiency of our automatic trace analysis methodology with case studies on large simulation traces from various system level designs.
2109758
Case studies of model checking for embedded system designs
As modern embedded systems become more integrated and complex, it is crucial to be able to represent systems at multiple levels of abstraction, so that the design space can be effectively explored by successive refinements and abstractions. We present a formal verification methodology and case studies for property verification of designs represented at different abstraction levels. Utilizing Metropolis meta-model (MMM), Y-chart Application Programmer's Interface (YAPI), an automatic translator, and the model checker SPIN, we verify properties for both system level representations and refined representations.
1333400
Utilizing formal assertions for system design of network processors
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific designs. To make sure that the executable models behave as they should, the designers often have to "eye-ball" the simulation traces and at best, apply simple "assert" statements or write simple trace checkers in some scripting languages. The problem is the lack of a concise and formal method to specify and check desired properties, whether they be functional or performance in nature. In this paper, we apply assertion checking methodology to the system design of network processors. Functional and performance assertions, based on linear temporal logic and logic of constraints, are written during the design process. Trace checkers and simulation monitors are automatically generated to validate particular simulation runs or to analyze their performance characteristics. Several categories of assertions are checked throughout the design process, such as equivalence, functionality, transaction, and performance. We demonstrate that the assertion-based methodology is very useful for both system level verification and design exploration.
694287
Automatic trace analysis for logic of constraints
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present algorithms to automatically generate trace checkers from formulas written in the formal quantitative constraint language, Logic Of Constraints (LOC), to analyze the simulation traces for functional and performance constraint violations. For many interesting formulas, the checkers exhibit linear time complexity and constant memory usage. We illustrate the usefulness and efficiency of this approach with large designs and traces.
5884737
Logic of constraints: a quantitative performance and functional constraint formalism
In the era of billion-transistor design, it is critical to establish effective verification methodologies from the system level, all the way down to the implementations. In this paper, we introduce logic of constraints (LOC), a logic that is particularly suited to express quantitative performance constraints as well as functional constraints. We analyze the expressiveness of LOC and show that it is important and different from linear temporal logic, upon which traditional hardware assertion languages (e.g., PSL and OpenVera) are based. We propose an automatic simulation trace checking/runtime monitoring methodology that can be used to verify system designs very efficiently. Since a subset of LOC is decidable, we also discuss the formal verification approach for LOC formulas. Through several industrial case studies, we demonstrate the usefulness of the LOC formalism and the corresponding simulation and verification approach at the higher transaction level of abstraction.
3210423
Verification Approach of Metropolis Design Framework for Embedded Systems
In this paper, we focus on the verification approach of Metropolis, an integrated design framework for heterogeneous embedded systems. The verification approach is based on the formal properties specified in Linear Temporal Logic (LTL) or Logic of Constraints (LOC). Designs may be refined due to synthesis or be abstracted for verification. An automatic abstraction propagation algorithm is used to simplify the design for specific properties. A user-defined starting point may also be used with automatic propagation. Two main verification techniques are implemented in Metropolis the formal verification utilizing the model checker Spin and the simulation trace checking with automatic generated checkers. Translation algorithms from specification models to verification models, as well as algorithms of generated checkers are discussed. We use several case studies to demonstrate our approach for verification of system level designs at multiple levels of abstraction.
641995
An Admission Control Scheme for Predictable Server Response Time for Web Accesses
The diversity in web object types and their resource requirements contributes to the unpredictability of web service provisioning. In this paper, an eÆcient admission control algorithm, PACERS, is proposed to provide di erent levels of services based on the server workload characteristics. Service quality is ensured by periodical allocation of system resources based on the estimation of request rate and service requirements of prioritized tasks. Admission of lower priority tasks is restricted during high load periods to prevent denial-of-services to high priority tasks. A doublequeue structure is implemented to reduce the e ects of estimation inaccuracy and to utilize the spare capacity of the server, thus increasing the system throughput. Response delays of the high priority tasks are bounded by the length of the prediction period. Theoretical analysis and experimental study show that the PACERS algorithm provides desirable throughput and bounded response delay to the prioritized tasks, without any signi cant impact on the aggregate throughput of the system under various workload.
2743837
A hybrid classifier approach for Web retrieved documents classification
The paper presents a hybrid technique for the classification of Web returned hits into concept hierarchies. The technique involves a combination of manual and automatic classifiers. At first, all Web returned documents are assigned to human defined categories using manual classifiers, and then automatic classifiers are used to generate a concept hierarchy for each of these categories. The results of the evaluation reveal the following: (a) for polysemous queries, our system is able to generate meaningful categories corresponding to (but not limited to), the different semantic facets of the queries; (b) as expected, for non-polysemous queries the system generates fewer categories; (c) the hierarchy precision of the concept hierarchies generated for polysemous queries is found to be significantly better when compared to the one obtained using a baseline system.
15165209
A PCA-Based Vehicle Classification Framework
Due to its great practical importance, Intelligent Transportation System has been an active research area in recent years. In this paper, we present a framework that incorporates various aspects of an intelligent transportation system with its ultimate goal being vehicle classification. Given a traffic video sequence, the proposed system first proceeds to segment individual vehicles. Then the extracted vehicle objects are normalized so that all vehicles are aligned along the same direction and measured at the same scale. Following the preprocessing step, two classification algorithms - Eigenvehicle and PCA-SVM, are proposed and implemented to classify vehicle objects into trucks, passenger cars, vans, and pick-ups. These two methods exploit the distinguishing power of Principal Component Analysis (PCA) at different granularities with different learning mechanisms. Experiments are conducted to compare these two methods and the results demonstrate the effectiveness of the proposed framework.
9838630
Domination in Graphs of Minimum Degree Five
Let G=(V,E) be a simple graph. A subset D⊆V is a dominating set of G, if for any vertex x ∈ V−D, there exists a vertex y ∈ D such that xy ∈ E. By using the so-called vertex disjoint paths cover introduced by Reed, in this paper we prove that every graph G on n vertices with minimum degree at least five has a dominating set of order at most 5n/14.
10962331
PCA-Based Face Recognition in Infrared Imagery: Baseline and Comparative Studies
Techniques for face recognition generally fall into global and local approaches, with the principal component analysis (PCA) being the most prominent global approach. We use the PCA algorithm to study the comparison and combination of infrared and typical visible-light images for face recognition. We examine the effects of lighting change, facial expression change and passage of time between the gallery image and probe image. Experimental results indicate that when there is substantial passage of time (greater than one week) between the gallery and probe images, recognition from typical visible-light images may outperform that from infrared images. Experimental results also indicate that the combination of the two generally outperforms either one alone. This is the only study that we know of to focus on the issue of how passage of time affects infrared face recognition.