16103417
Designs in Additive Codes over GF(4)
The purpose of this paper is to study designs in additive codes over GF(4). There are two types of designs. One is a classical t-design with repeated blocks. In this case we have an analog of the Assmus–Mattson Theorem for additive codes over GF(4). The other is a generalized t-design first introduced by Delsarte [4]. As an example, we consider the dodecacode, which is the unique additive even self-dual (12, 212, 6) code. We show that there exists a 5-(12, 6, 3) design in the dodecacode with either 3 distinct blocks or 3 repeated blocks covering a 5-set. We also find a new simple 3-(11, 5, 4) design in the shortened dodecacode by a computer search. Additionally we show that any extremal additive even self-dual code over GF(4) is homogeneous.
14157019
Projections of Binary Linear Codes onto Larger Fields
We study certain projections of binary linear codes onto larger fields. These projections include the well-known projection of the extended Golay [24,12,8] code onto the hexacode over $\mbox{GF}(4)$ and the projection of the Reed--Muller code R(2,5) onto the unique self-dual [8,4,4] code over $\mbox{GF}(4)$. We give a characterization of these projections, and we construct several binary linear codes which have best known optimal parameters, for instance, [20,11,5], [40,22,8], [48,21,12], and [72,31,16]. We also relate the automorphism group of a quaternary code to that of the corresponding binary code.
12043862
A method and tool support for variant requirements analysis: goal and scenario based approach
Identifying and representing variant requirements among products in a product family are crucial activities for a successful software reuse. The variant requirements should be not only identified based on the business goal, which drives marketing plan, product plan, and differences among products, but also represented as familiar notations in order to support developing a particular product in the product family. Thus, our proposal is to identify the variant requirements through goals and scenarios, and represent them as variable use cases for a product family. Especially, for identification of the variant requirements, we propose four abstraction levels of requirements in the product family, and goal and scenario modeling. For representation of them, variable use case model is suggested, and also the use case transfer rules are proposed so as to bridge the gap between the identification and representation activity. The paper illustrates the application of the approach within a supporting tool, namely DREAM (Domain REquirements Analysis Method) using the ATM example.
3831285
Data Integration Hub for a Hybrid Paper Search
In this paper we describe the design of a hybrid search that combines simple metadata search with a traditional keyword search over unstructured context data. This paradigm provides the inquirer additional options to narrow the search with some semantic aspects through the XML metadata query. We demonstrate a paper search for a case study of the hybrid search, and describe a data integration hub to integrate those data dispersed on the Net.
214797856
Temporal Streaming of Shared Memory
Coherent read misses in shared-memory multiprocessors account for a substantial fraction of execution time in many important scientific and commercial workloads. We propose Temporal Streaming, to eliminate coherent read misses by streaming data to a processor in advance of the corresponding memory accesses. Temporal streaming dynamically identifies address sequences to be streamed by exploiting two common phenomena in shared-memory access patterns: (1) temporal address correlation � groups of shared addresses tend to be accessed together and in the same order, and (2) temporal stream locality � recently-accessed address streams are likely to recur. We present a practical design for temporal streaming. We evaluate our design using a combination of trace-driven and cycle-accurate full-system simulation of a cache-coherent distributed shared-memory system. We show that temporal streaming can eliminate 98% of coherent read misses in scientific applications, and between 43% and 60% in database and web server workloads. Our design yields speedups of 1.07 to 3.29 in scientific applications, and 1.06 to 1.21 in commercial workloads.
12505197
Dynamic mapping in a heterogeneous environment with tasks having priorities and multiple deadlines
In a distributed heterogeneous computing system, the resources have different capabilities and tasks have different requirements. To maximize the performance of the system, it is essential to assign resources to tasks (match) and order the execution of tasks on each resource (schedule in a manner that exploits the heterogeneity of the resources and tasks. The mapping (defined as matching and scheduling) of tasks onto machines with varied computational capabilities has been shown, in general, to be an NP-complete problem. Therefore, heuristic techniques to find a near-optimal solution to this mapping problem are required. Dynamic mapping is performed when the arrival of tasks is not known a priori. In the heterogeneous environment considered in this study, tasks arrive randomly, tasks are independent (i.e., no communication among tasks), and tasks have priorities and multiple deadlines. This research proposes, evaluates, and compares eight dynamic heuristics. The performance of the best heuristics is 83% of an upper bound.
11308682
Techniques for improving the accuracy of geometric-programming based analog circuit design optimization
We present techniques for improving the accuracy of geometric-programming (GP) based analog circuit design optimization. We describe major sources of discrepancies between the results from optimization and simulation, and propose several methods to reduce the error. Device modeling based on convex piecewise-linear (PWL) function fitting is introduced to create accurate active and passive device models. We also show that in selected cases GP can enable nonconvex constraints such as bias constraints using monotonicity, which help reduce the error. Lastly, we suggest a simple method to take the modeling error into account in GP optimization, which results in a robust design over the inherent errors in GP device models. Two-stage operational amplifier and on-chip spiral inductor designs are given as examples to demonstrate the presented ideas.