31462412
Performance evaluation and validation of microprocessors
The domain of early performance analysis and microarchitecture definition is limited largely to a onedimensional perspective of net performance: that of cyclesper-instnrction (CPI). Traceor execution-driven cycle-bycycle simulators [l] are the most common toolsets used at this stage. These are often coded in a systems programming language (e.g. C, C++, PWl or Pascal). They are performance-only models in that the register and memory data values and their state changes are not modelled; only the complex pipeline flow and concurrent instruction processing semantics are simulated. The goal here is to assess CPIcentric performance and bottlenecks to aid early definition, not to ensure functional integrity. Such a simulator, which we call a CPI timer; can be implemented to run at speeds greater than 50,000 instructions per second [21. This is achieved in modelling a future processor with the simulator running on a current generation uniprocessor workstation.
26499349
Early performance estimation of super scalar machine models
A novel methodology and software tool for estimating the performance of high-performance machine models with concurrent, pipelined execution modes are presented. Such performance assessment is typically useful at early stages of the design cycle. Critical design decisions made with the aid of early estimators of the kind discussed can be expected to yield near-optimal final designs.<<ETX>>
2521753
A circuit level implementation of an adaptive issue queue for power-aware microprocessors
Increasing power dissipation has become a major constraint for future performance gains in the design of microproces sors In this paper we present the circuit design of an issue queue for a superscalar processor that leverages transmis sion gate insertion to provide dynamic low cost con gura bility of size and speed A novel circuit structure dynami cally gathers statistics of issue queue activity over intervals of instruction execution These statistics are then used to change the size of an issue queue organization on the y to improve issue queue energy and performance When applied to a xed full size issue queue structure the result is up to a reduction in energy dissipation The complexity of the additional circuitry to achieve this result is almost neg ligible Furthermore self timed techniques embedded in the adaptive scheme can provide a decrease in cycle time of the CAM array read of the issue queue when we change the adaptive issue queue size from entries largest possible to entries smallest possible in our design
9413783
Optimal Code Generation for Expressions on Super Scalar Machines
44925839
MHPS-Driven Early Design and Analysis of VLSI CPU Chips
JVe present (1 noid appsoaclz to carry per/i,rinancc analysis arid tiiiiitig of VLSI processors, don(? in the context of higlt-lewl source Iceriicls. U7e illustrate our rnetliodology in 1Crt71.r of a small (exaniph?) super scalas RlSC J ~ S O C ~ S S I ~ S architecture. A pnrantetrized execution 17ic~cIeI is used fhr piforinance eslimniion. IJsing an iterative optimization techniqire, the parameter set can bc locally optiinizcd around a g i i w design point to genesare tlie ininii?itrtn cycles per. iiwtrttction ( V I ) . W e also iiicludc a ctirsory discussion on linking .rirclt a CI’I estiiizntor io an early jloorplanner jhr A f IPS-driven block layout for the processor chb.
18281114
Performance and functional verification of microprocessors
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of the validation problem: (a) verifying the functional integrity of the model and (b) testing the model for timing accuracy at the architectural level. The latter area, that of performance verification, is of increasing importance in the design of server-class processor chips, with one or more high performance cores on a single die. We show how simulation-based test cases can be generated under a unified defect and coverage model to detect both performance and functional bugs. We present and discuss examples of such integrated validation methodologies used in real processor development projects.
32119598
Location Oblivious Distributed Unit Disk Graph Coloring
We present the first location oblivious distributed unit disk graph coloring algorithm having a provable performance ratio of three (i.e. the number of colors used by the algorithm is at most three times the chromatic number of the graph). This is an improvement over the standard sequential coloring algorithm since we present a new lower bound of 10/3 for the worst-case performance ratio of the sequential coloring algorithm. The previous greatest lower bound on the performance ratio of the sequential coloring algorithm was 5/2. Using simulation, we also compare our algorithm with other existing unit disk graph coloring algorithms.
2484450
Traversing a set of points with a minimum number of turns
Given a finite set of points S in R<sup>d</sup>, consider visiting thepoints in S with a polygonal path that makes a minimum number ofturns, or equivalently, has the the minimum number of segments(links). We call this minimization problem the minimum linkspanning path problem. This natural problem has appeared severaltimes in the literature under different variants. The simplest oneis where the allowed paths are axis-aligned. Let L(S) be theminimum number of links of an axis-aligned path for S denote by G<sup>d</sup><sub>n</sub> the d-dimensional grid of size n. Kranakis, Krizanc andMeertens (Ars Combinatoria, vol. 38, pp. 177--192, 1994)showed that in 2-dimensions L(G<sup>2</sup><sub>n</sub>)=2n-1 and in three dimensions 4/3 n<sup>2</sup>-O(n)< L(G<sup>3</sup><sub>n</sub>) < 3/2 n<sup>2</sup>+O(n). Kranakiset al. conjectured that, for all d ≥ 3, L(G<sup>d</sup><sub>n</sub>)= d/d-1 n<sup>d-1</sup> ± O(n<sup>d-2</sup>). We prove theconjecture for d=3 by showing that L(G<sup>3</sup><sub>n</sub>) ≥ 3/2 n<sup>2</sup> -O(n). For d=4, we prove that 4/3 n<sup>3</sup> -O(n<sup>2</sup>) ≤ L(G<sup>4</sup><sub>n</sub>) ≤ 4/3 n<sup>3</sup> +O(n<sup>5/2</sup>).For general d, we give new estimates on L(G<sup>d</sup><sub>n</sub>), that bring usvery close to the conjectured value. The new lower bound of (1+ 1/d)n<sup>d-1</sup>-O(n<sup>d-2</sup>) improves previous result byCollins and Moret (Information Processing Letters, vol. 68,pp. 317--319, 1998), while the new upper bound of (1+ 1/d-1)n<sup>d-1</sup>+O(n<sup>d-3/2</sup>) differs from the conjecturedvalue only in the lower order terms. For arbitrary point sets, we give an exact bound on the minimumnumber of links needed in an axis-aligned path traversing any planar n-point set. We obtain similar tight estimates (within 1) in anynumber of dimensions d. For the general problem of traversing anarbitrary set of points in R<sup>d</sup> with an axis-aligned spanning pathhaving a minimum number of links, we present a constant ratio(depending on the dimension d) approximation algorithm.
5595756
Bounds for Frequency Estimation of Packet Streams
We consider the problem of approximating the frequency of frequently occurring elements in a stream of length n using only a memory of size m n. This models the process of gathering statistics on Internet packet streaming using a memory that is small relative to the number of classes (e.g. IP addresses) of packets. We show that when some data item a occurs αn times in a stream of length n, the FREQUENT algorithm of Demaine et al. [4], can approximate a’s frequency with an error of no more than (1−α)n/m. We also give a lower-bound of (1−α)n/(m+1) on the accuracy of any deterministic packet counting algorithm, which implies the FREQUENT algorithm is nearly optimal. Finally, we show that randomized algorithms can not be significantly more accurate since there is a lower bound of (1−α)Ω(n/m) on the expected accuracy of any randomized packet counting algorithm.
7215582
Light edges in degree-constrained graphs
Let @a denote the average degree, and @d denote the minimum degree of a graph. An edge is light if both its endpoints have degree bounded by a constant depending only on @a and @d. A graph is degree-constrained if @a<2@d. The primary result of this paper is that every degree-constrained graph has a light edge. Most previous results in this direction have been for embedded graphs. This result is extended in a variety of ways. First it is proved that there exists a constant c(@a,@d) such that for every 0=<@e
123081730
Simultaneous diagonal flips in plane triangulations
Simultaneous diagonal flips in plane triangulations are investigated. It is proved that every triangulation with at least six vertices has a simultaneous flip into a 4-connected triangulation, and that it can be computed in linear time. It follows that every triangulation has a simultaneous flip into a Hamiltonian triangulation. This result is used to prove that for any two n-vertex triangulations, there exists a sequence of O(log n) simultaneous flips to transform one into the other. The total number of edges flipped in this sequence is O(n). The maximum size of a simultaneous flip is then studied. It is proved that every triangulation has a simultaneous flip of at least 1/3(n − 2) edges. On the other hand, every simultaneous flip has at most n − 2 edges, and there exist triangulations with a maximum simultaneous flip of 6/7 (n − 2) edges.