16535706
An efficient architecture for two-dimensional discrete wavelet transform
This paper proposes an efficient architecture for the two-dimensional discrete wavelet transform (2-D DWT). The proposed architecture includes a transform module, a RAM module, and a multiplexer. In the transform module, we employ the polyphase decomposition technique and the coefficient folding technique to the decimation filters of stages 1 and 2, respectively. In comparison with other 2-D DWT architectures, the advantages of the proposed architecture are 100% hardware utilization, fast computing time (0.5-0.67 times of the parallel filters'), regular data flow, and low control complexity, making this architecture suitable for next generation image compression systems, e.g., JPEG-2000.
16730298
Efficient moving object segmentation algorithm using background registration technique
An efficient moving object segmentation algorithm suitable for real-time content-based multimedia communication systems is proposed in this paper. First, a background registration technique is used to construct a reliable background image from the accumulated frame difference information. The moving object region is then separated from the background region by comparing the current frame with the constructed background image. Finally, a post-processing step is applied on the obtained object mask to remove noise regions and to smooth the object boundary. In situations where object shadows appear in the background region, a pre-processing gradient filter is applied on the input image to reduce the shadow effect. In order to meet the real-time requirement, no computationally intensive operation is included in this method. Moreover, the implementation is optimized using parallel processing and a processing speed of 25 QCIF fps can be achieved on a personal computer with a 450-MHz Pentium III processor. Good segmentation performance is demonstrated by the simulation results.
32197027
A hardware accelerator for video segmentation using programmable morphology PE array
Video segmentation is a key operation for MPEG-4 and MPEG-7. It is a computationally intensive task and cannot be afforded by general microprocessors. In this paper, we propose a hardware accelerator for video segmentation. Since most of the core operations of video segmentation algorithms can be mapped to morphological operations, the core of this accelerator is a programmable morphology PE array. With the programmable ability of each PE and the interconnection between them, this accelerator can achieve both high throughput and high flexibility. Simulation shows the proposed hardware accelerator can speed up the most important video segmentation algorithms 20 times to achieve realtime performance and has high programmability with a little hardware cost overhead.
17373350
VLSI architecture design of MPEG-4 shape coding
This paper presents an efficient VLSI architecture design of MPEG-4 shape coding, which is the key technology for supporting the content-based functionality of the MPEG-4 video standard. The real-time constraint of MPEG-4 shape coding leads to a heavy computational bottleneck on today's computer architectures. To overcome this problem, design analysis and optimization of MPEG-4 shape coding are addressed. By utilizing the RISC-based model, computational behaviors of the MPEG-4 shape coding tool are carefully examined and analyzed. The characteristic of a large amount of bit-level data processing and data transfer of MPEG-4 shape coding motivates the optimization of bit-level data operations. Applying data-flow optimization and data reuse techniques, bit-level computation-efficient architectures, such as data-dispatch-based binary-shaped motion estimation, the delay-line model, and configurable context-based arithmetic coding, are designed to accelerate bit-level processing. These hardware blocks are integrated and scheduled in a very efficient data flow to achieve real-time performance for MPEG-4 CPL2 (core profile level 2) specification at 23.5 MHz clock rate. The system architecture is implemented using Verilog HDL and synthesized with a 0.35 /spl mu/m four-layer CMOS standard library.
4274853
Lifting based discrete wavelet transform architecture for JPEG2000
A lifting based 1-D discrete wavelet transform (DWT) core is proposed. It is re-configurable for 5/3 and 9/7 filters in JPEG2000. Folded architecture is adopted to reduce the hardware cost and achieve the higher hardware utilization. Multiplication is realized in hardwired multiplier with coefficients represented in canonic signed-digit (CSD) form. It is a compact and efficient DWT core for the hardware implementation of JPEG2000 encoder.
335267
VLSI implementation of shape-adaptive discrete wavelet transform
In this paper, several VLSI architectures and implementations of Shape-Adaptive Discrete Wavelet Transform (SA-DWT) with odd symmetric biorthogonal filters are presented. The hardware implementation issues of SA-DWT algorithm are first addressed, and one lifting scheme together with some appropriate shape information processing units is introduced for the 1-D SA-DWT architectures. These architectures can efficiently perform 1-D length-adaptive DWT on continuous line segments and solve the corresponding boundary extension and subsampling problems without any overhead. In addition to 1-D architectures, two 2-D SA-DWT architectures are also proposed. One is the direct method, which uses the 1-D SA-DWT architectures as basis to extend to 2-D SA-DWT by direct row-column approach. The other is the line-based method, which is an efficient and feasible architecture that uses internal line buffers rather than external frame memory. These two 2-D SA-DWT architectures are both VLSI implemented by using cell-based chip design flow. The Daubechies (9,7) filter is used for the implementation by direct method, and the Daubechies (9,3) filter is used for the line-based implementation. The proposed architectures can be applied both in arbitrarily shaped visual objects coding such as MPEG-4 still texture coding and rectangular region image coding such as JPEG2000 still image coding.
206952974
High throughput CORDIC-based systolic array design for the discrete cosine transform
In this paper, we propose a modified Malvar algorithm that can transfer the Discrete Hartley Transform (DHT) results to the Discrete Cosine Transform (DCT) by using a one additional CORDIC computing stage. A fast CORDIC-based systolic array is designed with four attractive features the single/double data folding feature; the constructive feature; the co-computing feature; and redundant path computation. Due to the existence of the redundant path, the proposed design also has the capability of error detection.<<ETX>>
11794423
An adaptive consistency maintenance approach for replicated continuous applications
Consistency maintenance is a key problem to replicated continuous applications and dead reckoning (DR) algorithm is widely used in this area. In order to eliminate short-term inconsistency caused by DR algorithm, local-lag approach was proposed. For the purpose of simplicity, fixed lag value is used by local-lag approach and the performance of the approach is greatly deteriorated. In this paper, an adaptive consistency maintenance approach, which is based on local-lag approach, is proposed. The new approach can adjust lag value according to the estimated typical network latency. In order to ensure the criterion of consistency correctness, a lag value adjustment method is also proposed. Through two experiments, the performance of the new approach is evaluated and the results indicate that it is feasible and can greatly improve the performance of the application.
1252625
Supporting self-adaptation in streaming data mining applications
There are many application classes where the users are flexible with respect to the output quality. At the same time, there are other constraints, such as the need for real-time or interactive response, which are more crucial. This paper presents and evaluates a runtime algorithm for supporting adaptive execution for such applications. The particular domain we target is distributed data mining on streaming data. This work has been done in the context of a middleware system called GATES (grid-based adaptive execution on streams) that we have been developing. The self-adaptation algorithm we present and evaluate in this paper has the following characteristics. First, it carefully evaluates the long-term load at each processing stage. It considers different possibilities for the load at a processing stage and its next stages, and decides if the value of an adaptation parameter needs to be modified, and if so, in which direction. To find the ideal new value of an adaptation parameter, it performs a binary search on the specified range of the parameter. To evaluate the self-adaptation algorithm in our middleware, we have implemented two streaming data mining applications. The main observations from our experiments are as follows. First, our algorithm is able to quickly converge to stable values of the adaptation parameter, for different data arrival rates, and independent of the specified initial value. Second, in a dynamic environment, the algorithm is able to adapt the processing rapidly. Finally, in both static and dynamic environments, the algorithm clearly outperforms the algorithm described in our earlier work and an obvious alternative, which is based on linear-updates.
206929170
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system software designers: how to best exploit the parallelism potential due to such multi-core architectures? In this paper, we report an in-depth study on such challenges based on our experience of optimizing the fast Fourier transform (FFT) on the IBM Cyclops-64 chip architecture - a large-scale multi-core chip architecture consisting 160 thread units, associated memory banks and an interconnection network that connect them together in a shared memory organization. We demonstrate how multi-core architectures like the C64 could be used to achieve a high performance implementation of FFT both in 1D and 2D cases. We analyze the optimization challenges and opportunities including problem decomposition, load balancing, work distribution, and data-reuse, together with the exploiting of the C64 architecture features such as the multi-level of memory hierarchy and large register files. Furthermore, the experience learned during the hand-tuned optimization process have provided valuable guidance in our compiler optimization design and implementation. The main contributions of this paper include: 1) our study demonstrates that successful optimization for C64-like large-scale multi-core architectures requires a careful analysis that can identify certain domain-specific features of a target application (e.g. FFT) and match them well with some key multi-core architecture features; 2) our optimization, assisted with hand-tuned process, provided quantitative evidence on the importance of each optimization identified in 1); 3) automatic optimization by our compiler, the design and implementation of which is guided by the feedbacks from 1) and 2), shows excellent results that are often comparable to the results derived from our time-consuming hand-tuned code.
9822806
Wavelet-based optical flow estimation
In this paper, a new algorithm for accurate optical flow estimation using discrete wavelet approximation is proposed. The proposed method takes advantages of the nature of wavelet theory, which can efficiently and accurately represent "things", to model optical flow vectors and image related functions. Each flow vector and image function are represented by linear combinations of wavelet basis functions. From such wavelet-based approximation, the leading coefficients of these basis functions carry the global information of the approximated "things". The proposed method can successfully convert the problem of minimizing a constraint function into that of solving a linear system of a quadratic and convex function of wavelet coefficients. Once all the corresponding coefficients are decided, the flow vectors can be determined accordingly. Experiments conducted on both synthetic and real image sequences show that our approach outperformed the existing methods in terms of accuracy.