5829860
Store-ordered streaming of shared memory
Coherence misses in shared-memory multiprocessors account for a substantial fraction of execution time in many important scientific and commercial workloads. Memory streaming provides a promising solution to the coherence miss bottleneck because it improves memory level parallelism and lookahead while using on-chip resources efficiently. We observe that the order in which shared data are consumed by one processor is correlated to the order in which they were produced by another. We investigate this phenomenon and demonstrate that it can be exploited to send store-ordered streams (SORDS) of shared data from producers to consumers, thereby eliminating coherent read misses. Using a trace-driven analysis of all user and OS memory references in a cache-coherent distributed shared-memory multiprocessor, we show that SORDS-based memory streaming can eliminate between 36% and 100% of all coherent read misses in scientific workloads and between 23% and 48% in online transaction processing workloads.
214797856
Temporal Streaming of Shared Memory
Coherent read misses in shared-memory multiprocessors account for a substantial fraction of execution time in many important scientific and commercial workloads. We propose Temporal Streaming, to eliminate coherent read misses by streaming data to a processor in advance of the corresponding memory accesses. Temporal streaming dynamically identifies address sequences to be streamed by exploiting two common phenomena in shared-memory access patterns: (1) temporal address correlation � groups of shared addresses tend to be accessed together and in the same order, and (2) temporal stream locality � recently-accessed address streams are likely to recur. We present a practical design for temporal streaming. We evaluate our design using a combination of trace-driven and cycle-accurate full-system simulation of a cache-coherent distributed shared-memory system. We show that temporal streaming can eliminate 98% of coherent read misses in scientific applications, and between 43% and 60% in database and web server workloads. Our design yields speedups of 1.07 to 3.29 in scientific applications, and 1.06 to 1.21 in commercial workloads.
6458402
METIS: multiple extraction techniques for informative sentences
SUMMARY
METIS is a web-based integrated annotation tool. From single query sequences, the PRECIS component allows users to generate structured protein family reports from sets of related Swiss-Prot entries. These reports may then be augmented with pertinent sentences extracted from online biomedical literature via support vector machine and rule-based sentence classification systems.


AVAILABILITY
http://umber.sbs.man.ac.uk/dbbrowser/metis/
6308143
Geometry of gene expression dynamics
MOTIVATION
A gene expression trajectory moves through a high dimensional space where each axis represents the mRNA abundance of a different gene. Genome wide gene expression has a dynamic structure, especially in studies of development and temporal response. Both visualization and analyses of such data require an explicit attention to the temporal structure.


RESULTS
Using three cell cycle trajectories from Saccharomyces cerevisiae to illustrate, we present several techniques which reveal the geometry of the data. We import phase-delay time plots from chaotic systems theory as a dynamic data visualization device and show how these plots capture important aspects of the trajectories. We construct an objective function to find an optimal two-dimensional projection of the cell cycle, demonstrate that the system returns to this plane after three different initial perturbations, and explore the conditions under which this geometric approach outperforms standard approaches such as singular value decomposition and Fourier analysis. Finally, we show how a geometric analysis can isolate distinct parts of the trajectories, in this case the initial perturbation versus the cell cycle.


CONTACT
junhyong.kim@yale.edu
3492450
A framework for data prefetching using off-line training of Markovian predictors
An important technique for alleviating the memory bottleneck is data prefetching. Data prefetching solutions ranging from pure software approach by inserting prefetch instructions through program analysis to purely hardware mechanisms have been proposed. The degrees of success of those techniques are dependent on the nature of the applications. The need for innovative approach is rapidly growing with the introduction of applications such as object-oriented applications that show dynamically changing memory access behavior In this paper, we propose a novel framework for the use of data prefetchers that are trained off-line using smart learning algorithms to produce prediction models which captures hidden memory access patterns. Once built, those prediction models are loaded into a data prefetching unit in the CPU at the appropriate point during the runtime to drive the prefetching. On average by using table size of about 8KB size, we were able to achieve prediction accuracy of about 68% through our own proposed learning method and performance was boosted about 37% on average on the benchmarks we tested. Furthermore, we believe our proposed framework is amenable to other predictors and can be done as a phase of the profiling-optimizing-compiler.
1994375
Effective Temporal Aggregation Using Point-Based Trees
Temporal databases introduce the concept of time into underlying data, and provide built-in facilities that allow users to store and retrieve time-varying data. The aggregation in temporal databases, that is, temporal aggregation is an extension of conventional aggregation on the domain and range of aggregates to include time concept. Temporal aggregation is important for various applications, but is very expensive. In this paper, we propose a new tree structure for temporal aggregation, called PA-tree, and aggregate processing method based on the PA-tree. We show that the time complexity of the proposed method is better than those of the existing methods. The time complexity of the proposed method is shown to be indeed the lower bound of the problem. We perform comparative experiments and show the performance advantage of our proposed method in practice.
27298271
The Rule-Based Approach to Reconfiguration of 2-D Processor Arrays
The authors propose to set up assignment rules based on the available interconnection resources of 2-D processor arrays. The reconfiguration of 2-D processor arrays is guided by the assignment rules, such that logical cells are always connected through the available interconnection resources. The advantage of the proposed approach is the easy adaptation to various system requirements, by adjusting assignment rules. The proposed reconfiguration algorithm can be extended to arrays with clustered faulty cells, overcoming the weakness of fixed domain approaches. >