8159144
Processor frequency selection for SoC platforms for multimedia applications
Of late, there has been a considerable interest in generic and configurable system-on-chip platforms specifically targeted towards implementing multimedia applications. A number of such platforms offer the possibility of including processor soft cores which are highly customizable. For voltage/frequency scaled processors, such customization includes the selection of appropriate voltage/frequency operating points which are tuned to the application set to be mapped onto the platform. In this context, we present an analytical framework that can guide a system designer in identifying the frequency ranges that should be supported by the different processors of a platform architecture. This framework can also be used to identify how such frequency ranges depend on the different parameters of the architecture (such as on-chip buffer sizes), and the performance impacts associated with selecting a particular frequency range. In the case of multimedia streaming applications, identifying such performance impacts and tradeoffs involved in customizing a platform architecture is especially difficult due to the bursty nature of on-chip traffic arising out of multimedia processing and the high variability in their execution requirements. The framework presented here is designed to precisely capture such characteristics and can be used in the design-space exploration of energy-aware platform architectures for multimedia processing.
2987131
Interface-Based Rate Analysis of Embedded Systems
Interface-based design is now considered to be one of the keys to tackling the increasing complexity of modern embedded systems. The central idea is that different components comprising such systems can be developed independently and a system designer can connect them together only if their interfaces match, without knowing the details of their internals. We use the concept of rate interfaces for compositional (correct-by-construction) design of embedded systems whose components communicate through data streams. Using the associated rate interface algebra, two components can be connected together if the output rate of one component is "compatible" with the input rate of the other component. We formalize this notion of compatibility and show that such an algebra is non-trivial because it has to accurately model the burstiness in the arrival rates of such data streams and the variability in their processing requirements. We discuss how rate interfaces simplify compositional design and at the same time help in functional and performance verification which would be difficult to address otherwise. Finally, we illustrate these advantages through a realistic case study involving a component-based design of a multiprocessor architecture running a picture-in-picture application
6222461
Approximate VCCs: a new characterization of multimedia workloads for system-level MpSoC design
System-level design methods specifically targeted towards multimedia applications have recently received a lot of attention. Multimedia workloads are known to have a high degree of variability. Therefore, designs based on a worst-case analysis of such workloads tend of be overly pessimistic. We address this issue by introducing a new concept called approximate variability characterization curves (or approximate VCCs), to characterize the "average-case" behavior of multimedia workloads in a parameterized fashion. Since most multimedia applications only have soft real-time constraints, it is often possible to tolerate a small amount of performance degradation. By allowing such small degradations in the performance, large amounts of resource savings are possible. The concept of approximate VCCs that we present in this paper allows a designer to quantitatively account for the performance degradation and the associated resource savings. We illustrate this using two typical system design cases.
16964204
Workload characterization and cost-quality tradeoffs in MPEG-4 decoding on resource-constrained devices
There has been a lot of interest in the embedded systems community on architectures and design methods that are targeted towards multimedia applications. This trend is pri marily motivated by the proliferation of resource and power-constrained portable devices (such as mobile phones and PDAs), a major portion of whose workload is made up of multimedia applications. In this paper, we investigate the tradeoffs between video quality and the processor cycle requirements in such resource-constrained devices, in the particular context of MPEG-4 decoding using an open source codec called XviD. The XviD codec implements a number of powerful coding tools from MPEG-4, which are organized as profiles and levels. Given the specification of an architecture on which an XviD decoder is implemented, the work presented here would guide a multimedia applications developer in selecting appropriate profiles and levels for the corresponding encoder application. While the selection of such profiles has so far been primarily influenced by the network bandwidth in the case of video streaming, our work stresses the importance of additionally taking into account the architecture of the device running the decoder application. Although the relevance of this observation is increasingly being realized, sufficient work has not yet been done to provide guidelines on how to systematically make such selections. This work attempts to address this shortcoming.
2728797
Generalized Rate Analysis for Media-Processing Platforms
In this paper we address the "rate analysis" problem for media-processing platforms consisting of multiple processor cores connected in a pipelined fashion. More precisely, we aim at determining fight bounds on the rates at which multimedia streams can be fed into such architectures. These bounds depend on architectural constraints (e.g. the available on-chip memory, bus arbitration policies, etc), as well as the application characteristics (e.g. application partitioning and mapping, workload rates generated by different tasks, etch The proposed framework for rate analysis can be used for fast design space exploration to determine how these bounds change with different architectural parameters, mapping of the application, or changing the QoS requirements associated with the input streams
18374506
Design-level performance prediction of component-based applications
Server-side component technologies such as Enterprise JavaBeans (EJBs), .NET, and CORBA are commonly used in enterprise applications that have requirements for high performance and scalability. When designing such applications, architects must select suitable component technology platform and application architecture to provide the required performance. This is challenging as no methods or tools exist to predict application performance without building a significant prototype version for subsequent benchmarking. In this paper, we present an approach to predict the performance of component-based server-side applications during the design phase of software development. The approach constructs a quantitative performance model for a proposed application. The model requires inputs from an application-independent performance profile of the underlying component technology platform, and a design description of the application. The results from the model allow the architect to make early decisions between alternative application architectures in terms of their performance and scalability. We demonstrate the method using an EJB application and validate predictions from the model by implementing two different application architectures and measuring their performance on two different implementations of the EJB platform.
737114
Building a Scalable Bipartite P2P Overlay Network
The peer-to-peer (P2P) model, being widely adopted in today's Internet computing, suffers from the problem of topology mismatch between the overlay networks and the underlying physical network. Traditional topology optimization techniques identify physically closer nodes to connect as overlay neighbors, but could significantly shrink the search scope. Efforts have been made to address the mismatch problem without sacrificing the search scope, but they either need time synchronization among peers or have a low convergent speed. In this paper, we propose a scalable bipartite overlay (SBO) scheme to optimize the overlay topology by identifying and replacing the mismatched connections. In SBO, we employ an efficient strategy for distributing optimization tasks in peers with different colors. We conducted comprehensive simulations to evaluate this design. The results show that SBO achieves approximately 85 percent of reduction on traffic cost and about 60 percent of reduction on query response time. Our comparisons with previous approaches to address the topology mismatch problem have shown that SBO can achieve a fast convergent speed, without the need of time synchronization among peers.
2056912
Performance and Scalability Measurement of COTS EJB Technology
Enterprise Java Bean (EJB) is the core technology of J2EE platform to provide the foundation for scalable enterprise applications. About 30 product vendors provide implementations of the J2EE/EJB specification. As each of these products is designed and implemented differently, they show radically different performance profiles. To complicate this technology space, product vendors of J2EE products typically provide different infrastructure options and tuning techniques to address the requirements of performance and scalability. Therefore it is essential for developers to understand the performance and scalability issues of COTS EJB technologies so that the system can meet the performance requirements. In this paper, we investigate an approach to measure the performance and scalability of COTS EJB technology based on its architecture and technology analysis. A benchmark application is developed and tested to measure the system's performance as both the client load and component infrastructure are scaled up. The empirical results are presented and analyzed to evaluate the performance and scalability of the EJB technology under study.
2269541
Principal component analysis for predicting transcription-factor binding motifs from array-derived data
BackgroundThe responses to interleukin 1 (IL-1) in human chondrocytes constitute a complex regulatory mechanism, where multiple transcription factors interact combinatorially to transcription-factor binding motifs (TFBMs). In order to select a critical set of TFBMs from genomic DNA information and an array-derived data, an efficient algorithm to solve a combinatorial optimization problem is required. Although computational approaches based on evolutionary algorithms are commonly employed, an analytical algorithm would be useful to predict TFBMs at nearly no computational cost and evaluate varying modelling conditions. Singular value decomposition (SVD) is a powerful method to derive primary components of a given matrix. Applying SVD to a promoter matrix defined from regulatory DNA sequences, we derived a novel method to predict the critical set of TFBMs.ResultsThe promoter matrix was defined to establish a quantitative relationship between the IL-1-driven mRNA alteration and genomic DNA sequences of the IL-1 responsive genes. The matrix was decomposed with SVD, and the effects of 8 potential TFBMs (5'-CAGGC-3', 5'-CGCCC-3', 5'-CCGCC-3', 5'-ATGGG-3', 5'-GGGAA-3', 5'-CGTCC-3', 5'-AAAGG-3', and 5'-ACCCA-3') were predicted from a pool of 512 random DNA sequences. The prediction included matches to the core binding motifs of biologically known TFBMs such as AP2, SP1, EGR1, KROX, GC-BOX, ABI4, ETF, E2F, SRF, STAT, IK-1, PPARγ, STAF, ROAZ, and NFκB, and their significance was evaluated numerically using Monte Carlo simulation and genetic algorithm.ConclusionThe described SVD-based prediction is an analytical method to provide a set of potential TFBMs involved in transcriptional regulation. The results would be useful to evaluate analytically a contribution of individual DNA sequences.
5373454
A Logic of Limited Belief for Reasoning with Disjunctive Information
The goal of producing a general purpose, semantically motivated, and computationally tractable deductive reasoning service remains surprisingly elusive. By and large, approaches that come equipped with a perspicuous model theory either result in reasoners that are too limited from a practical point of view or fall off the computational cliff. 
 
In this paper, we propose a new logic of belief called SL which lies between the two extremes. We show that query evaluation based on SL for a certain form of knowledge bases with disjunctive information is tractable in the propositional case and decidable in the first-order case. Also, we present a sound and complete axiomatization for propositional SL.