42278030
Hybrid knowledge-based architecture for building an intelligent nondestructive signal inspection system
The paper deals with the methods of implementing an intelligent inspection system for monitoring the health of any device or material using a nondestructive signal. A hybrid knowledge representation and processing architecture is proposed as a solution to problems encountered in the processes of the nondestructive inspection. In the proposed system, to modularize knowledge elicitation and to make knowledge processing reliable, the task of inspection is delegated to two subsystems each of which has a proper knowledge processing scheme to match the properties of its own task. The front-end subsystem which detects the signal patterns (events) for any harmful flaw is built by integrating a fuzzified syntactic pattern recognition concept and a neural network concept. The back-end subsystem which evaluates the characteristics of the events is based upon object-oriented rule base system concepts. The methods of integrating the approaches in the proposed architecture are also proposed in the paper. The proposed architecture is verified by developing and evaluating a prototype which automatically interprets eddy current Lissajous signals to inspect the state of tubes used in nuclear power plants.
12676174
Response to Comments on: A cohesion measure for object-oriented classes
The authors insist that monotonicity is a necessary property of a good cohesion metric and the violation of the monotonicity property limits the application of CBMC. They also state that the augmented CBMC can also be used as a guideline for quality evaluation and restructuring of poorly designed classes. This paper raises the question about the necessity of monotonicity by analyzing the reason that causes CBMC to violate the monotonicity property. In addition, we give a detailed description of the restructuring procedure based on CBMC.
6263618
Evaluation of mutation testing for object-oriented programs
The effectiveness of mutation testing depends heavily on the types of faults that the mutation operators are designed to represent. Thus, the quality of the mutation operators is key to mutation testing. Although, mutation operators for object-oriented languages have previously been presented, little research has been done to show the usefulness of the class mutation operators. To assess the usefulness of class mutation operators, we conducted two empirical studies. In the first study, we examine the number and kinds of mutants that are generated for object-oriented programs. In the second study, we investigate the way in which class mutation operators model faults that are not detected by traditional mutation testing. We conducted our studies using a well-known object-oriented system, BCEL.
31388642
Modeling and Testing Agent Systems Based on Statecharts
This paper presents a testing method for an agent system against its specification described with Statecharts. Here, an agent system means an implementation of an agent application. Its testing method generates test sequences from the specification and checks whether the agent system behaves in accordance with the specification by executing the test sequences. For specification-based testing, we have extended Statecharts in order to describe the behavior of an agent system according to the concept of Agent UML. Then, we propose an approach to generating test sequences from the extended Statecharts. Our approach makes effective use of partial order methods for considering representative sequences of equivalent classes divided from all possible sequences. Therefore, we can efficiently manage a large number of possible sequences caused by the agents’ autonomy. As a result, we can reduce the number of test sequences and the number of executions to be tested.
206016323
Specifying and verifying real-time systems with timing uncertainty
Modeling timing behaviors of systems and verifying timing constraints against the model are major tasks in developing real-time systems. However, it is recognized to be extremely difficult to predict the timing behavior of systems precisely in the requirements phase. Timing uncertainty, if not considered properly in the modeling and verifying steps, may incur subtle, yet critical errors in final products. We propose a method of dealing with such timing uncertainty using an extended duration calculus formalism. The extended duration calculus, named fuzzy duration calculus, allows us to specify uncertain timing behavior of the system using the fuzzy theory. Semantics and proof system of the duration calculus are redefined in order to accommodate fuzzy concepts. Based on the semantics and proof system, we can verify timing constraints against the system model. A portion of nuclear power plant (NPP) control system is employed to demonstrate the feasibility and the effectiveness of our approach.
8261294
Inter-class mutation operators for Java
The effectiveness of mutation testing depends heavily on the types of faults that the mutation operators are designed to represent. Therefore, the quality of the mutation operators is key to mutation testing. Mutation testing has traditionally been applied to procedural-based languages, and mutation operators have been developed to support most of their language features. Object-oriented programming languages contain new language features, most notably inheritance, polymorphism, and dynamic binding. Not surprisingly; these language features allow new kinds of faults, some of which are not modeled by traditional mutation operators. Although mutation operators for OO languages have previously been suggested, our work in OO faults indicate that the previous operators are insufficient to test these OO language features, particularly at the class testing level. This paper introduces a new set of class mutation operators for the OO language Java. These operators are based on specific OO faults and can be used to detect faults involving inheritance, polymorphism, and dynamic binding, thus are useful for inter-class testing. An initial Java mutation tool has recently been completed, and a more powerful version is currently under construction.
14599334
Communication-efficient hardware acceleration for fast functional simulation
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more time-consuming as design complexity increases. To accelerate functional simulation, hardware acceleration is used to offload calculation-intensive tasks from the software simulator. Hardware accelerated simulation dramatically reduces the simulation time. However, the communication overhead between the software simulator and hardware accelerator is becoming a new critical bottleneck. We reduce the communication overhead by exploiting burst data transfer and parallelism, which are obtained by splitting testbench and moving a part of testbench into hardware accelerator. Our experiments demonstrated that the proposed method reduces the communication overhead by a factor of about 40 compared to conventional hardware accelerated simulation while maintaining the cycle accuracy and compatibility with the original testbench.
13416160
Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation
As the processing capabilities and operating frequency of embedded system are growing, so is the needed data bandwidth to fully utilize the processing capability. The ability to transfer huge amount of data between the embedded core and external devices is required for efficient system operation. In this paper, the data communication architecture for the mixed-clock system is proposed. The dynamic priority adaptation algorithm for bus arbitration is proposed for bandwidth guarantee. The communication architecture that incorporates the proposed arbitration algorithm adapts the priority of communication components dynamically based on the information from FIFO. The experiments show that the measured bandwidth of each component traces the required bandwidth well compared to the other arbitration algorithms.
13194172
ActorNet: an actor platform for wireless sensor networks
We present actorNet, a mobile agent platform for wireless sensor networks (WSNs). WSNs are well-suited to multiagent systems: agent autonomy reduces the need for communication, saving precious energy. Mobile agents are also an intuitive technique for remotely reprogramming sensors deployed in the field. However, implementing agent programs directly on a WSN is complicated by the many limitations of sensor nodes, including limited memory, slow processors, low bandwidth and finite energy. ActorNet eases development by providing an abstract environment for lightweight concurrent object-oriented mobile code on WSNs. As such, it enables a wide range of new dynamic applications, including fully customizable queries and aggregation functions, in-network interactive debugging and high-level concurrent programming on the inherently parallel sensor network platform. Moreover, actorNet cleanly integrates all of these features into a fine-tuned, multi-threaded embedded Scheme interpreter that supports compact, maintainable programs---a significant advantage over primitive stack-based virtual machines.
19995952
ATOMi: an algorithm for circuit partitioning into multiple FPGAs using time-multiplexed, off-chip, multicasting interconnection architecture
Logic emulation is so far the fastest method to verify the system functionality in the gate level before chip fabrication. Field-programmable gate array (FPGA)-based logic emulator with large gate capacity generally comprises a large number of FPGAs or special processors connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. This paper first describes a new interconnection architecture called TOMi (Time-multiplexed, Off-chip, Multicasting interconnection) and proposes a circuit partitioning algorithm called ATOMi (Algorithm for TOMi) for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi. ATOMi reduces the number of off-chip signal transfers to optimize the performance for multi-FPGA system implemented by TOMi. Experimental results using Partitioning93 benchmarks show that, by adopting the proposed TOMi interconnection architecture along with ATOMi, the pin count is reduced to 14.4%-88.6% while the critical path delay is reduced to 66.1%-90.1% compared to traditional architectures including mesh, crossbar, and VirtualWire architecture.
3218907
Assignment Copy Detection Using Neuro-genetic Hybrids
It is difficult for teachers to find out copies in their program assignments. We propose a method which detects the similarity of assignments. We first transform a program into a sequence of tokens and provide it to an artificial neural network. The neural network is optimized by a hybrid genetic algorithm. Experimental results showed considerable improvement on artificial neural networks.