42859429
Hardware verification using symbolic state transition graphs
A new approach for hardware verification using symbolic state transition graphs (implemented in BDDs) is presented. We propose a novel idea, a symbolic state transition graph (STG), which can represent finite state machines FSM in terms of the relations between symbolic input variables, state variables, and output results, rather than the exact input-output bit patterns. Compared to conventional STG methods, the symbolic STG is more concise, higher-level, has fewer states and is easier to specify. Based on the transition relation method and an event-driven scheduling technique to compute the symbolic states, we propose two algorithms to verify the circuit implementation with respect to its symbolic STGs. The algorithms can be used to find out a necessary condition for the implementation to satisfy the specification, which can be used for the allocation of design errors.<<ETX>>
206952974
High throughput CORDIC-based systolic array design for the discrete cosine transform
In this paper, we propose a modified Malvar algorithm that can transfer the Discrete Hartley Transform (DHT) results to the Discrete Cosine Transform (DCT) by using a one additional CORDIC computing stage. A fast CORDIC-based systolic array is designed with four attractive features the single/double data folding feature; the constructive feature; the co-computing feature; and redundant path computation. Due to the existence of the redundant path, the proposed design also has the capability of error detection.<<ETX>>
8098811
Embedded software-based self-testing for SoC design
At-speed testing of high-speed circuits is becoming increasingly difficult with external testers due to the growing gap between design and tester performance, growing cost of high-performance testers and increasing yield loss caused by inherent tester inaccuracy. Therefore, empowering the chip to test itself seems like a natural solution. Hardware-based self-testing techniques have limitations due to performance and area overhead and problems caused by the application of non-functional patterns.Embedded software-based self-testing has recently become focus of intense research. In this methodology, the programmable cores are used for on-chip test generation, measurement, response analysis and even diagnosis. After the programmable core on a System-on-Chip (SoC) has been self-tested, it can be reused for testing on-chip buses, interfaces and other non-programmable cores. The advantages of this methodology include at-speed testing, low design-for-testability overhead and application of functional patterns in the functional environment. In this paper, we give a survey and outline the roadmap and challenges of this emerging embedded software-based self-testing paradigm.
8972258
Designing oscillators in synthetic gene networks based on multi-scale dynamics
Multistability, oscillations, and switching exist at various levels of biological processes and organizations and have been investigated on the basis of many theoretical models, such as circadian oscillations with the period protein (PER) and the timeless protein (TIM) in Drosophila, and multistable dynamics regulated by transcriptional factors. Considerable experimental evidence suggests that cellular processes are intrinsically rhythmic or periodic. Various periodic oscillations with different time scales ranging from less than a second to more than a year, which may allow for living organisms to adapt their behaviors to a periodically varying environment, have also been observed experimentally. On the other hand, in synthetic gene networks, both toggle switch and repressilator have been theoretically proposed and further confirmed by experiments. All of these works stress the importance of feedback regulation of transcriptional factors, which is a key in giving rise to oscillatory or multistable dynamical behaviors exhibited by biological genetic systems. In addition, it should be noted that many periodic behaviors do not simply oscillate smoothly; rather, they change rapidly or jump at certain states. In gene expression systems, many different time scales characterize the gene regulatory processes. For instance, the transcription and translation processes generally evolve on a time scale that is much slower than that of phosphorylation, dimerization or binding reactions of transcription factors. In genetic networks, the time scale for expression of some genes is much slower than that of others, depending on the length of the genes. We aim to design robust periodic oscillators in synthetic gene-protein systems by simple nonlinear models and to analyze the basic mechanism of limit cycles with jumping behaviors or relaxation oscillations by exploiting multiple time-scale properties [1, 2]. We show that periodic oscillations are mainly generated by nonlinear feedback loops in gene regulatory systems and the jumping dynamics caused by time scale differences among biochemical reactions. Moreover, effects of time delay are also examined. We show that time delay generally enlarges the stability region of oscillations, thereby making the oscillations more sustainable despite parameter changes or noise [1, 2]. The dynamics of the proposed models is robust in terms of stability and period length to the parameter perturbations or environment variations. Although we mainly analyze some specific models, the mechanisms identified in this work are likely to apply to a variety of genetic regulatory systems. These simple models may actually act as basic building block in synthetic gene-protein networks, such as genetic oscillators or switches because the dynamics is robust for parameter perturbations or environment variations. Several examples are also provided to demonstrate implementation of synthetic oscillators by using genes of the /spl lambda/ phage bacteria.
7815226
Peak Load Forecasting Using the Self-organizing Map
This paper aims to study the short-term load forecasting of electricity by using an extended self-organizing map. We first adopt a traditional Kohonen self-organizing map (SOM) to learn time-series load data with weather information as parameters. Then, in order to improve the accuracy of the prediction, an extension of SOM algorithm based on error-correction learning rule is used, and the estimation of the peak load is achieved by averaging the output of all the neurons. Finally, as an implementation example, data of electricity demand from New York Independent System Operator (ISO) are used to verify the effectiveness of the learning and prediction for the proposed methods.
6401713
Stability Analysis of Regional and National Voting Schemes by a Continuous Model
The previous discrete-model-based stability analysis of regional and national voting has been extended to a continuous-model-based analysis in the simultaneous presence of white and concentrated components of noise, reconfirming the previous conclusion that regional voting with smaller sized regions always demonstrates an improved stability over those with larger sized regions, including the national voting in its limiting case in particular. The conclusion remains valid as long as the weak distribution assumption is valid.
441449
A novel ant clustering algorithm based on cellular automata
Based on the principle of cellular automata in artificial life, an artificial ant sleeping model (ASM) and an ant algorithm for cluster analysis (A4C) are presented. Inspired by the behaviors of gregarious ant colonies, we use the ant agent to represent a data object. In ASM, each ant has two states: a sleeping state and an active state. The ant's state is controlled by a function of the ant's fitness to the environment it locates and a probability for the ants becoming active. The state of an ant is determined only by its local information. By moving dynamically, the ants form different subgroups adaptively, and hence the data objects they represent are clustered. Experimental results show that the A4C algorithm on ASM is significantly better than other clustering methods in terms of both speed and quality. It is adaptive, robust and efficient, achieving high autonomy, simplicity and efficiency.