32582887
Novel Design and Fpga Implementation of Da-rns Fir Filters
Field programmable gate array (FPGA)-based digital signal processing has been widely used in multimedia applications. By combining distributed arithmetic (DA) and residue number system (RNS) in such designs, efficient area, speed and power efficiency can be achieved. In this paper, we propose novel techniques for the design and FPGA implementation of DA-RNS finite impulse response (FIR) filters. By introducing a novel low-cost moduli set and its selection method, efficient modulo arithmetic units inside the subfilters are designed. Then, a new residue-to-binary conversion algorithm, a so-called modified DA Chinese remainder theorem, is derived to reduce the modulo operations and provide an efficient residue-to-binary converter suitable to FPGA implementation. Based on these proposed techniques, a seventh-order DA-RNS FIR filter is designed, implemented and tested by using Xilinx FPGA tools. The implementation results show that the proposed filter design consumes only 77% of the power that the existing filter12,13 requires, while maintaining the same speed (throughput).
15012785
An area-reduced scheme for modulo 2/sup n/-1 addition/subtraction
In this paper, we present a versatile area-reduced scheme for modulo 2/sup n/-1 adders and subtracters using a MUX-based increment/decrement algorithm. A FPGA-based comparison of the proposed modulo adder and the conventional modulo adder designs is carried out. The implementation results show that the proposed adder reduces the area close to 30% compared with the modulo adder of Bayoumi et al. The delay and the power are also reduced around 10%. In addition, it is also shown that the proposed design requires less hardware resources than the parallel-prefix modulo adder of Kalampoukas et al. while providing a comparable operation speed.
19122402
Moduli selection in RNS for efficient VLSI implementation
In this paper, we carry out a study on an important issue concerning the use of residue numbers in the design of digital systems, namely, the moduli selection. Based on a new formulation of the Chinese remainder theorem and the efficient residue-to-binary (R/B) converters designed therefrom, we propose a guideline for the selection of the low-cost moduli sets for different dynamic ranges. These sets consist of the low-cost moduli of the form 2/sup n/, ( 2/sup n/-1) or (2/sup n/ + 1), which can offer simplified modulo adders and multipliers. It is shown that for medium dynamic ranges (less than 22 bits), the three-moduli set {2/sup n/,2/sup n/ + 1,2/sup n/ - 1} is the most efficient one in terms of the design of a complete RNS system. On the other hand, for large dynamic ranges (equal to or larger than 22 bits), the general-moduli set in the form (2/sup n/, 2/sup n/ + 1,2/sup n/ - 1,2/sup n/ /spl plusmn/1,...,2/sup n/, /spl plusmn/1), with a length greater than three, is the most efficient one. These results provide the possibility of a wide range of applications of the residue number system in the design of DSP, telecommunication and cryptography systems.
31496165
Elliptic curves cryptosystem implementation based on a look-up table sharing scheme
Projective point elliptic curve cryptography (ECC) involves many look-up table-based field multiplications. In this paper, a novel lookup table sharing scheme is proposed to significantly reduce the number of the field multiplications and number of lookup tables. By requiring much less lookup table generation time, the proposed system offers high-speed performance for hardware realizations. Its application in a reconfigurable PC-FPGA platform is investigated, which can efficiently handle requests for different ECC key length and curves and is useful for many computer network applications
29715580
A high-speed residue-to-binary converter and a scheme for its VLSI implementation
In this paper, a high-speed residue-to-binary converter for the recently introduced moduli set (2/sup k/, 2/sup k/-1, 2/sup k-1/-1) is proposed. Compared to the previous converter based on this moduli set, the proposed one is 40% faster; also, the time-complexity product is improved by 20%. Following the VLSI design flow established by the Canadian Microelectronics Corporation, the proposed converter is implemented in 0.5-micron CMOS technology. Based on this moduli set, layouts of the 8-bit, 16-bit, 32-bit and 64-bit residue-to-binary converters which can be used in further RNS system designs, are generated and simulation results obtained.
16722632
A CRT-RSA Algorithm Secure against Hardware Fault Attacks
Chinese remainder theorem based RSA (CRT-RSA) digital signature has important applications in smart cards. Previous CRT-RSA algorithms such as CRT-2 and BOS are susceptible to practical hardware fault attacks. In this paper, a new CRT-RSA algorithm with countermeasures to hardware fault attacks is proposed. To our knowledge, the proposed algorithm is the first that can resist what we call the single-fault adversarial attacks. The proposed algorithm first computes the signature using CRT in a secret algebraic setting, then a set of fault-detection variables are computed to detect possible faults. Lastly, the signature is mapped from the secret algebraic setting to the intended setting. By using a random number and the fault detection variables, every step of the algorithm is protected from hardware faults. The output of the algorithm will be fully randomized in case of faults. The CRT's speed advantages are also maintained. The proposed algorithm is approximately two times as fast as the direct form RSA for the two-prime case, and about four times as fast for the three-prime case
3184000
Revealing true subspace clusters in high dimensions
Subspace clustering is one of the best approaches for discovering meaningful clusters in high dimensional space. One cluster in high dimensional space may be transcribed into multiple distinct maximal clusters by projecting onto different subspaces. A direct consequence of clustering independently in each subspace is an overwhelmingly large set of overlapping clusters which may be significantly similar. To reveal the true underlying clusters, we propose a similarity measurement of the overlapping clusters. We adopt the model of Gaussian tailed hyper-rectangles to capture the distribution of any subspace cluster. A set of experiments on a synthetic dataset demonstrates the effectiveness of our approach. Application to real gene expression data also reveals impressive meta-clusters expected by biologists.
26642486
Computing Repairs for Inconsistent XML Document Using Chase
An XML document is inconsistent if it violates predefined integrity constraints. In this paper, we consider how to compute repairs for an inconsistent XML document. Here repair is defined as the data consistent with the integrity constraints, and also minimally differs from the original document. Based on a repair framework by introducing a chase method, in this paper, we discuss the repairs computing problem and implement a prototype. First we discuss some key points about mends generation and repairs chasing. Next we give a cost model for this repair framework, which can be used to evaluate the cost of each repair. Finally we implement prototypes of our method, and evaluate our framework and algorithms in the experiment.
37619733
Taming Underlying Design for Energy Efficient Distributed Source Coding in Multirate Wireless Sensor Network
Signal processing applications such as Distributed Source Coding (DSC) in Wireless Sensor Network (WSN) are often multirate in nature, which provide additional significant opportunities in WSN design for achieving energy efficiency. In this paper, we analyze the DSC traffic for signal processing applications in multirate WSN and propose a novel rate oriented approach with MAC and PHY cross layer utilization to achieve high energy efficiency. Simulation results show that the proposed approach achieves significant energy efficiency by a factor of three while maintaining the transmission quality in WSN. This approach can be easily extended to other WSN MAC and PHY designs, providing multirate service to application layer to allow achieving higher energy efficiency
8653895
The Implementation of an Energy Balanced Routing Protocol with Dynamic Power Scaling in TinyOS
In this paper, we study an energy balanced routing protocol based on dynamic power scaling techniques for wireless sensor networks. In the proposed protocol, each node maintains a list of neighboring nodes and their corresponding statistical residual energy information. The energy balanced routing distributes the levels of residue energy evenly throughout the network, while the dynamic power scaling scheme achieves further energy savings by adjusting transmission power to meet signal strength requirement at the receiver. In order to demonstrate the increased energy efficiency of the proposed protocol, we have conducted an experimental study. The results of our experimental study clearly show that the proposed energy balanced routing scheme with dynamic power improves energy efficiency while achieving energy balance as well
12699114
WAR: Weighted association rules for item intensities
In this paper, we extend the traditional association rule problem by allowing a weight to be associated with each item in a transaction to reflect the interest/intensity of each item within the transaction. In turn, this provides us with an opportunity to associate a weight parameter with each item in a resulting association rule; we call them weighted association rules (WAR). One example of such a rule might be 80% of people buying more than three bottles of soda will also be likely to buy more than four packages of snack food, while a conventional association rule might just be 60% of people buying soda will be also be likely to buy snack food. Thus WARs cannot only improve the confidence of the rules, but also provide a mechanism to do more effective target marketing by identifying or segmenting customers based on their potential degree of loyalty or volume of purchases. Our approach mines WARs by first ignoring the weight and finding the frequent itemsets (via a traditional frequent itemset discovery algorithm), followed by introducing the weight during the rule generation. Specifically, the rule generation is achieved by partitioning the weight domain space of each frequent itemset into fine grids, and the identifying the popular regions within the domain space to derive WARs. This approach does not only support the batch mode mining, i.e., finding WARs for the dataset, but also supports the interactive mode, i.e., finding and refining WARs for a given (set) of frequent itemset(s).