12943655
Scan tests with multiple fault activation cycles for delay faults
In this paper we investigate methods to detect delay faults in circuits that use standard scan design. We demonstrate that delay faults at several sites in a circuit cannot be detected using standard launch off capture and launch off shift tests that use two test cycles. However, faults at these sites are detectable using tests that use more than two test cycles. Experimental results on benchmark and industrial circuits that use standard scan design show that substantial numbers of transition delay faults require tests using more than one fault activation cycles to detect them
18103085
Finite memory test response compactors for embedded test applications
This paper introduces a new class of finite memory compaction schemes called convolutional compactors (CCs). They provide compaction ratios of test responses in excess of 100/spl times/, even for a very small number of outputs. This is combined with the capability to detect multiple errors, handling of unknown states, and the ability to diagnose failing scan cells directly from compacted responses. The CCs can also be used to significantly enhance conventional multiple input signature registers. Experimental results presented in the paper demonstrate the efficiency of convolutional compaction for several industrial circuits.
14388558
Generation of Functional Broadside Tests for Transition Faults
Scan design allows a circuit to be tested using states that the circuit cannot enter during functional operation. It was observed that nonfunctional operation during testing may cause excessive currents that can cause a good chip to fail the test because of voltage droops caused by the excessive current demand. A good chip may also fail due to the propagation of signal transitions along nonfunctional long paths, especially during at-speed testing. This problem is studied in this paper in the context of tests for transition faults. A method for determining transition faults that are untestable under functional operation-conditions is described. Two procedures for generating transition-fault tests that use only functional operation conditions are also described. The first procedure accepts as input a broadside test set for transition faults. The second procedure accepts as input a test sequence for the nonscan circuit. Although such a test sequence is more complex to generate and simulate, it results in higher numbers of faults detected under functional operation conditions
11514442
A test pattern ordering algorithm for diagnosis with truncated fail data
In this paper, we propose a test pattern ordering algorithm for fault diagnosis. Test pattern ordering is effective in situations where the fail log is truncated and contains a limited number of fail data. In such cases, higher diagnostic resolution can be achieved with the test set appropriately ordered. Test pattern ordering is independent of the diagnosis algorithm used. The higher resolution achieved by test pattern ordering is obtained at no additional cost once the test patterns have been appropriately ordered. Experimental results on two industrial designs are presented to demonstrate the effectiveness of the proposed method
18173256
Hierarchical placement for large-scale FPAA
Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. Our goal in this paper is to develop the first hierarchical placement algorithm for large-scale floating-gate based FPAAs with a focus on the minimization of the parasitic effects on interconnects under various device-related constraints. In our hierarchical approach, our FPAA clustering algorithm first groups analog components into a set of clusters so that the total number of routing switches used is minimized and all IO paths are balanced in terms of routing switches used. Our FPAA placement algorithm then maps each cluster to a computational analog block (CAB) of the target FPAA while focusing on routing switch usage again. Experimental results demonstrate the effectiveness of our approach.
15140843
Mapping algorithm for large-scale field programmable analog array
Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. With these advances, analog circuits and systems can be programmable, reconfigurable, adaptive, implemented on standard CMOS to take advantage of scaled CMOS technology, and at a density comparable to digital memories. Our goal in this paper is to develop the first physical design automation toolset for floating-gate based FPAA with focus on minimization of parasitic effects on FPAA interconnect. We provide graph-based analog circuit and FPAA device modeling suitable for efficient mapping. Our FPAA clustering algorithm constructs Computational Analog Blocks (CAB) from analog circuit elements while improving the utilization of the device and reducing its impact on the total number of routing switches used. Experimental results demonstrate the effectiveness of our approach.
16583629
Placement for large-scale floating-gate field-programable analog arrays
Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. Our goal in this paper is to develop the first placement algorithm for large-scale floating-gate-based FPAAs with a focus on the minimization of the parasitic effects on interconnects under various device-related constraints. Our FPAA clustering algorithm first groups analog components into a set of clusters so that the total number of routing switches used is minimized and all IO paths are balanced in terms of routing switches used. Our FPAA placement algorithm then maps each cluster to a computational analog block (CAB) of the target FPAA while focusing on routing switch usage and balance again. Experimental results demonstrate the effectiveness of our approach
37046746
On the detection of delay faults
The class of faults known as gate delay faults are investigated. A taxonomy of the classes of gate delay fault detecting tests is provided. Methods to derive robust and nonrobust tests to detect gate delay faults are proposed. A physically meaningful measure to assess the efficacy of test sequences is introduced, and used to report fault coverages. A nine-valued logic system was proposed and used for deriving these tests. A physically meaningful measure, in the form of the average detection size of a test sequence. An algorithm was devised and implemented to automate the process of test generation, and results of experimentation with the ATPG, as well as with a random-pattern simulator, on four ISCAS-85 circuits were reported.<<ETX>>
20551694
"Challenges in Testing"
As technological advances in circuit design and manufacturing are made, testing procedures must accommodate diverse circuit description styles, large circuit sizes and new failure mechanisms. In this talk, we describe some of these challenges and how they are addressed in recent works in various areas of testing. In recent years, the formulations of testing problems have changed from “given a problem, find a solution” to “given a problem and quality measures, find a high-quality solution”. Quality guarantees provide ways to measure the distance between a given solution and an optimal solution. In addition they provide criteria for evaluating a new procedure that are more effective than for example comparison to previously proposed procedures. This is important when applying the procedures to very large circuits. Recent works address testing issues at increasingly higher levels of the design cycle and offer an integrated treatment of design and test. High-level failure models are considered as well as solutions that are completely independent of a failure model. At the same time, failure mechanisms at the transistor level gain importance as design features are reduced. We describe some of these works and the advantages of the two directions. Core or macro-based design consists of the incorporation of existing logic blocks (cores or macros) into a circuit. This design methodology reduces the time spent in designing the circuit. However, an embedded logic block may not be testable by a precomputed test set that ignores the environment where the block is embedded. Thus, macros-based design poses testing challenges that require existing testing methodologies to be reconsidered and new ones to be developed. Recently, testing techniques have been extended to the more general problems of design verification and validation. The approaches to hardware design verification and validation can be classified as simulation-based or formal methods. Simulation-based approaches are incomplete and do not guarantee the correctness of a design. Formal methods are not easily scalable to large circuits. + Research supported in part by NSF Grant No. MIP-9220549