29637234
A new architecture of RRNS error-correcting QC encoder/decoder and its FPGA implementation
In this paper, a new architecture of a redundant residue number system (RRNS) quasi-chaotic (QC) encoder/decoder with an error-correcting ability is proposed for secure communication and is tailored to FPGA implementation. In the proposed architecture, binary subencoders and subdecoders are used so that a number of modulo operations required in the existing design of D. R. Frey (IEEE Trans. Circuits Syst. II, vol. 40, pp. 660-666, Oct. 2000) are replaced by a simple truncation. Furthermore, a size-reduced design of the R/B (residue-to-binary) converter with error-correcting function, which is the crucial part of the system, is proposed. As a case study, the proposed architecture is implemented in FPGA for the case of the 16-bit input and some simulation results obtained.
16722632
A CRT-RSA Algorithm Secure against Hardware Fault Attacks
Chinese remainder theorem based RSA (CRT-RSA) digital signature has important applications in smart cards. Previous CRT-RSA algorithms such as CRT-2 and BOS are susceptible to practical hardware fault attacks. In this paper, a new CRT-RSA algorithm with countermeasures to hardware fault attacks is proposed. To our knowledge, the proposed algorithm is the first that can resist what we call the single-fault adversarial attacks. The proposed algorithm first computes the signature using CRT in a secret algebraic setting, then a set of fault-detection variables are computed to detect possible faults. Lastly, the signature is mapped from the secret algebraic setting to the intended setting. By using a random number and the fault detection variables, every step of the algorithm is protected from hardware faults. The output of the algorithm will be fully randomized in case of faults. The CRT's speed advantages are also maintained. The proposed algorithm is approximately two times as fast as the direct form RSA for the two-prime case, and about four times as fast for the three-prime case
29715580
A high-speed residue-to-binary converter and a scheme for its VLSI implementation
In this paper, a high-speed residue-to-binary converter for the recently introduced moduli set (2/sup k/, 2/sup k/-1, 2/sup k-1/-1) is proposed. Compared to the previous converter based on this moduli set, the proposed one is 40% faster; also, the time-complexity product is improved by 20%. Following the VLSI design flow established by the Canadian Microelectronics Corporation, the proposed converter is implemented in 0.5-micron CMOS technology. Based on this moduli set, layouts of the 8-bit, 16-bit, 32-bit and 64-bit residue-to-binary converters which can be used in further RNS system designs, are generated and simulation results obtained.
15012785
An area-reduced scheme for modulo 2/sup n/-1 addition/subtraction
In this paper, we present a versatile area-reduced scheme for modulo 2/sup n/-1 adders and subtracters using a MUX-based increment/decrement algorithm. A FPGA-based comparison of the proposed modulo adder and the conventional modulo adder designs is carried out. The implementation results show that the proposed adder reduces the area close to 30% compared with the modulo adder of Bayoumi et al. The delay and the power are also reduced around 10%. In addition, it is also shown that the proposed design requires less hardware resources than the parallel-prefix modulo adder of Kalampoukas et al. while providing a comparable operation speed.
32582887
Novel Design and Fpga Implementation of Da-rns Fir Filters
Field programmable gate array (FPGA)-based digital signal processing has been widely used in multimedia applications. By combining distributed arithmetic (DA) and residue number system (RNS) in such designs, efficient area, speed and power efficiency can be achieved. In this paper, we propose novel techniques for the design and FPGA implementation of DA-RNS finite impulse response (FIR) filters. By introducing a novel low-cost moduli set and its selection method, efficient modulo arithmetic units inside the subfilters are designed. Then, a new residue-to-binary conversion algorithm, a so-called modified DA Chinese remainder theorem, is derived to reduce the modulo operations and provide an efficient residue-to-binary converter suitable to FPGA implementation. Based on these proposed techniques, a seventh-order DA-RNS FIR filter is designed, implemented and tested by using Xilinx FPGA tools. The implementation results show that the proposed filter design consumes only 77% of the power that the existing filter12,13 requires, while maintaining the same speed (throughput).
15644746
RRNS quasi-chaotic coding and its FPGA implementation
In this paper, a new architecture of the redundant residue number system (RRNS) based quasi-chaotic coding is proposed for the secure telecommunication systems and networks. In the proposed architecture, a number of modulo operations required by the existing designs are replaced by binary coding operations to simplify the design. Also, a moduli selection method and a residue-to-binary converter with error-correction capability are proposed to further improve the efficiency of the design specifically for FPGA implementation. The proposed architecture is implemented and tested using Matlab and Xilinx FPGA hardware. The results show that compared to the existing design, the proposed design requires only 80% of the hardware resources while maintaining the same speed. The power consumption is also reduced by 25%.
29222863
An adaptive approach for image encryption and secure transmission over multirate wireless sensor networks
In this paper, we propose an innovative adaptive secure image delivery approach, to achieve effective and efficient image encryption based on an optimal transmission rate in terms of energy efficiency in wireless sensor networks (WSN). Our contribution is three folds—First, the proposed component based selective encryption scheme achieves high image security, while incurring little encryption overhead; furthermore, the proposed adaptive encryption scheme achieve the best security effort within delay bound; finally, the proposed transmission rate optimization improves energy efficiency, and feeds back effective path capacity parameters for adaptive encryption. Simulation results show a significant gain in both energy efficiency and security based on the proposed approach for image secure transmissions in WSN. Copyright # 2007 John Wiley & Sons, Ltd.
8256320
Fast computation with neural oscillators
This paper studies new spike-based models for winner-take-all computation and coincidence detection. In both cases, fast convergence is achieved independent of initial conditions, and network complexity is linear in the number of inputs. Fully distributed versions can be modelled based on groups of interneurons connected through electrical synapses.
6871628
REDUS: finding reducible subspaces in high dimensional data
Finding latent patterns in high dimensional data is an important research problem with numerous applications. The most well known approaches for high dimensional data analysis are feature selection and dimensionality reduction. Being widely used in many applications, these methods aim to capture global patterns and are typically performed in the full feature space. In many emerging applications, however, scientists are interested in the local latent patterns held by feature subspaces, which may be invisible via any global transformation.
 In this paper, we investigate the problem of finding strong linear and nonlinear correlations hidden in feature subspaces of high dimensional data. We formalize this problem as identifying reducible subspaces in the full dimensional space. Intuitively, a reducible subspace is a feature subspace whose intrinsic dimensionality is smaller than the number of features. We present an effective algorithm, REDUS, for finding the reducible subspaces. Two key components of our algorithm are finding the overall reducible subspace, and uncovering the individual reducible subspaces from the overall reducible subspace. A broad experimental evaluation demonstrates the effectiveness of our algorithm.
12878597
Pattern Mining for Information Extraction Using Lexical, Syntactic and Semantic Information: Preliminary Results
A method is being developed to mine a text corpus for candidate linguistic patterns for information extraction. The candidate patterns can be used to improve the quality of extraction patterns constructed by a pseudosupervised learning method--an automated method in which the system is provided with a high quality seed pattern or clue, which is used to generate a training set automatically. The study is carried out in the context of developing a system to extract disease-treatment information from medical abstracts retrieved from the Medline database. In an earlier study, the Apriori algorithm had been used to mine a sample of sentences containing a disease concept and a drug concept, to identify frequently occurring word patterns to see if these patterns could be used to identify treatment relations in text. Word patterns and statistical association measures alone were found to be insufficient for generating good extraction patterns, and need to be combined with syntactic and semantic constraints. In this study, we explore the use of syntactic, semantic and lexical constraints to improve the quality of extraction patterns.
90043
A new approach to design robust backstepping controller for MIMO nonlinear systems with input unmodeled dynamics
In this paper, a new scheme inspired by the idea of decentralized control methodology is proposed to design output feedback controllers for a class of MIMO nonlinear systems with input unmodeled dynamics. With dynamic normalization and backstepping approach, the destabilizing effects of unmodeled dynamics depending on inputs are compensated and global uniform boundedness of all the signals in the closed loop system is established for sufficiently weak input unmodeled dynamics.