14599334
Communication-efficient hardware acceleration for fast functional simulation
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more time-consuming as design complexity increases. To accelerate functional simulation, hardware acceleration is used to offload calculation-intensive tasks from the software simulator. Hardware accelerated simulation dramatically reduces the simulation time. However, the communication overhead between the software simulator and hardware accelerator is becoming a new critical bottleneck. We reduce the communication overhead by exploiting burst data transfer and parallelism, which are obtained by splitting testbench and moving a part of testbench into hardware accelerator. Our experiments demonstrated that the proposed method reduces the communication overhead by a factor of about 40 compared to conventional hardware accelerated simulation while maintaining the cycle accuracy and compatibility with the original testbench.
19995952
ATOMi: an algorithm for circuit partitioning into multiple FPGAs using time-multiplexed, off-chip, multicasting interconnection architecture
Logic emulation is so far the fastest method to verify the system functionality in the gate level before chip fabrication. Field-programmable gate array (FPGA)-based logic emulator with large gate capacity generally comprises a large number of FPGAs or special processors connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. This paper first describes a new interconnection architecture called TOMi (Time-multiplexed, Off-chip, Multicasting interconnection) and proposes a circuit partitioning algorithm called ATOMi (Algorithm for TOMi) for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi. ATOMi reduces the number of off-chip signal transfers to optimize the performance for multi-FPGA system implemented by TOMi. Experimental results using Partitioning93 benchmarks show that, by adopting the proposed TOMi interconnection architecture along with ATOMi, the pin count is reduced to 14.4%-88.6% while the critical path delay is reduced to 66.1%-90.1% compared to traditional architectures including mesh, crossbar, and VirtualWire architecture.
5951770
MetaCore: an application specific DSP development system
This paper describes the MetaCore system which is an ASIP (Application-Specific Instruction set Processor) development system targeted for DSP applications. The goal of MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost and design turnaround time.
MetaCore system consists of two major design stages: design exploration and design generation. In the design exploration stage, MetaCore system accepts a set of benchmark programs and a formal specification of ISA (Instruction Set Architecture), and estimates the hardware cost and performance for each hardware configuration being explored. Once a hardware configuration is chosen, the system helps generate a VLSI processor design in the form of HDL along with the application program development tools such as C compiler, assembler and instruction set simulator.
8120985
SCATOMi: scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multicasting interconnection architecture
FPGA-based logic emulator with large gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multiFPGA system incorporating several state-of-the-art FPGAs. We propose a circuit partitioning algorithm called SCATOMi(scheduling driven algorithm for TOMi) for multiFPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(time-multiplexed, off-chip, multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Experiments on architecture comparison show that, by adopting the proposed TOMi interconnection architecture along with SCATOMi, the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures including mesh, crossbar and VirtualWire architecture.
1823005
Functional coverage metric generation from temporal event relation graph
Functional coverage is a technique which can be used for checking the completeness of test vectors. In this paper, automatic generation of temporal events for functional coverage is proposed. The TERG (Temporal Event Relation Graph) is the graph where the nodes represent basic temporal property and the edges represent the time-shift value between two properties. Hierarchical temporal events are generated by traversing TERG such that invalid or irrelevant properties are eliminated. Concurrent edge groups in TERG make it possible to generate more comprehensive temporal properties.
13416160
Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation
As the processing capabilities and operating frequency of embedded system are growing, so is the needed data bandwidth to fully utilize the processing capability. The ability to transfer huge amount of data between the embedded core and external devices is required for efficient system operation. In this paper, the data communication architecture for the mixed-clock system is proposed. The dynamic priority adaptation algorithm for bus arbitration is proposed for bandwidth guarantee. The communication architecture that incorporates the proposed arbitration algorithm adapts the priority of communication components dynamically based on the information from FIFO. The experiments show that the measured bandwidth of each component traces the required bandwidth well compared to the other arbitration algorithms.
3218907
Assignment Copy Detection Using Neuro-genetic Hybrids
It is difficult for teachers to find out copies in their program assignments. We propose a method which detects the similarity of assignments. We first transform a program into a sequence of tokens and provide it to an artificial neural network. The neural network is optimized by a hybrid genetic algorithm. Experimental results showed considerable improvement on artificial neural networks.
39681972
Safety Verification of Ada95 Programs Using Software Fault Trees
Software fault tree is a graphical analysis technique that is based on the concept of axiomatic verification. A template-based approach to software fault tree analysis was proposed for Ada83 programs. For the past years since this approach, no noticeable extensions or revisions on the template-based software fault tree analysis have been proposed while the target language has been evolved into Ada95. In this paper, we examine the validness of the original Ada83 analysis templates to determine which of them are still applicable to Ada95 programs considering major changes from Ada83 to Ada95. In addition, we propose newly required templates as well as the necessary modification of the original Ada83 templates in order to cope with the changes. We demonstrate the use of our proposed templates with an example program.
206016323
Specifying and verifying real-time systems with timing uncertainty
Modeling timing behaviors of systems and verifying timing constraints against the model are major tasks in developing real-time systems. However, it is recognized to be extremely difficult to predict the timing behavior of systems precisely in the requirements phase. Timing uncertainty, if not considered properly in the modeling and verifying steps, may incur subtle, yet critical errors in final products. We propose a method of dealing with such timing uncertainty using an extended duration calculus formalism. The extended duration calculus, named fuzzy duration calculus, allows us to specify uncertain timing behavior of the system using the fuzzy theory. Semantics and proof system of the duration calculus are redefined in order to accommodate fuzzy concepts. Based on the semantics and proof system, we can verify timing constraints against the system model. A portion of nuclear power plant (NPP) control system is employed to demonstrate the feasibility and the effectiveness of our approach.
31388642
Modeling and Testing Agent Systems Based on Statecharts
This paper presents a testing method for an agent system against its specification described with Statecharts. Here, an agent system means an implementation of an agent application. Its testing method generates test sequences from the specification and checks whether the agent system behaves in accordance with the specification by executing the test sequences. For specification-based testing, we have extended Statecharts in order to describe the behavior of an agent system according to the concept of Agent UML. Then, we propose an approach to generating test sequences from the extended Statecharts. Our approach makes effective use of partial order methods for considering representative sequences of equivalent classes divided from all possible sequences. Therefore, we can efficiently manage a large number of possible sequences caused by the agents’ autonomy. As a result, we can reduce the number of test sequences and the number of executions to be tested.
6263618
Evaluation of mutation testing for object-oriented programs
The effectiveness of mutation testing depends heavily on the types of faults that the mutation operators are designed to represent. Thus, the quality of the mutation operators is key to mutation testing. Although, mutation operators for object-oriented languages have previously been presented, little research has been done to show the usefulness of the class mutation operators. To assess the usefulness of class mutation operators, we conducted two empirical studies. In the first study, we examine the number and kinds of mutants that are generated for object-oriented programs. In the second study, we investigate the way in which class mutation operators model faults that are not detected by traditional mutation testing. We conducted our studies using a well-known object-oriented system, BCEL.