5848822
Soft decoder architecture of LT codes
Luby transform (LT) codes, as the first class of efficient rateless codes, attract a lot of attention in the coding theory field. However, the VLSI implementation of LT codes is challenging due to its random code construction characteristic as well as the flexible output length. In this paper, we present an applicable architecture of a soft-decision LT decoder with a block length of 1024 bits and 100 iterations. Partly parallel input node processing and output node processing techniques are both adopted to accelerate decoding speed. An efficient router and reverse router are designed to indicate the graphic connectivity between input nodes and output nodes. The parallel architecture is prototyped on the target FPGA device.
1961988
An Area-Efficient LDPC Decoder Architecture and Implementation for CMMB Systems
This paper presents an area-efficient LDPC decoder architecture for the China Multimedia Mobile Broadcasting (CMMB) standard. Several techniques are adopted to reduce memory size, including the min-sum algorithm (MSA), optimal bit-width quantization of the iterative messages and reduced complexity for the interconnect network. The decoder for the rate-1/2 9216-bit code is implemented using the 90nm 1.0V CMOS technology. It achieves the decoding throughput of 48Mbps at 5 iterations when operating at 60MHz and the power dissipation is only 34mW.
15937167
High-throughput layered decoder implementation for quasi-cyclic LDPC codes
This paper presents a high-throughput decoder design for the Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. Two new techniques are proposed, including parallel layered decoding architecture (PLDA) and critical path splitting. PLDA enables parallel processing for all layers by establishing dedicated message passing paths among them. The decoder avoids crossbar-based large interconnect network. Critical path splitting technique is based on articulate adjustment of the starting point of each layer to maximize the time intervals between adjacent layers, such that the critical path delay can be split into pipeline stages. Furthermore, min-sum and loosely coupled algorithms are employed for area efficiency. As a case study, a rate-1/2 2304-bit irregular LDPC decoder is implemented using ASIC design in 90 nm CMOS process. The decoder can achieve the maximum decoding throughput of 2.2 Gbps at 10 iterations. The operating frequency is 950 MHz after synthesis and the chip area is 2.9 mm2.
34792854
A Component-Based Reflective Middleware Approach to Context-Aware Adaptive Systems
205396964
A distance-based separator representation for pattern classification
In pattern classification, Principle Component Analysis (PCA) and Linear Discriminate Analysis (LDA) are commonly used to reduce the dimensionality of input feature space. However, there exist some problems such that how many eigen vectors are needed to be the most effective in the transformation map as well as the lack of optimal separability in low dimensional data. In this paper, we present a new distance-based separator representation to solve these problems. The representation frame structure keeps adjustment pertaining to the problem complexity, and its dimensionality corresponds to the number of classes. Experimental results show that the new representation outperforms the PCA and LDA representations in multi-class classification and low-dimensional classification.
34929506
Adaptive Receive Antenna Selection for Orthogonal Space-Time Block Codes with Imperfect Channel Estimation
For coherent detection, decoding Orthogonal Space-Time Block Codes (OSTBC) requires full channel state information at the receiver, which basically is obtained by channel estimation. However, in practical systems, channel estimation errors are inevitable and may degrade the system performance more as the number of antennas increases. This letter shows that, using fewer receive antennas can enhance the performance of OSTBC systems in presence of channel estimation errors. Furthermore, a novel adaptive receive antenna selection scheme, which adaptively adjusts the number of receive antennas, is proposed. Performance evaluation and numerical examples show that the proposed scheme improves the performance obviously.
5878411
Density-Weighted Nystrm Method for Computing Large Kernel Eigensystems
The Nystrm method is a well-known sampling-based technique for approximating the eigensystem of large kernel matrices. However, the chosen samples in the Nystrm method are all assumed to be of equal importance, which deviates from the integral equation that defines the kernel eigenfunctions. Motivated by this observation, we extend the Nystrm method to a more general, density-weighted version. We show that by introducing the probability density function as a natural weighting scheme, the approximation of the eigensystem can be greatly improved. An efficient algorithm is proposed to enforce such weighting in practice, which has the same complexity as the original Nystrm method and hence is notably cheaper than several other alternatives. Experiments on kernel principal component analysis, spectral clustering, and image segmentation demonstrate the encouraging performance of our algorithm.
38683441
A Wordnet-Based Approach to Feature Selection in Text Categorization
This paper proposes a new feature selection method for text categorization. In this method, word tendency, which takes related words into consideration, is used to select best terms. Our experiments on binary classification tasks show that our method achieves better than DF and IG when the classes are semantically discriminative. Furthermore, our best performance is usually achieved in fewer features.