115245987
Object caching for performance in object-oriented systems
Object-oriented systems exhibit a very high rate of object creation, but most objects are short-lived. As a result, memory-management overhead is significant. An application-specific coprocessor architecture to speed up object creation and memory reclamation in object-oriented systems is described. The architecture supports a bit-vector approach to dynamic storage allocation and liberation. Novel created objects reside in a cache that is reference counted. Most objects are expected to die before they age out of the cache, drastically reducing the number of references to main memory. Many existing computer architectures would require only minor compiler modification to incorporate and benefit from this coprocessor.<<ETX>>
18001825
Architectural support for dynamic memory management
Recent advances in software engineering, such as graphical user interfaces and object-oriented programming, have caused applications to become more memory intensive. These applications tend to allocate dynamic memory prolifically. Moreover, automatic dynamic memory reclamation (garbage collection, GC) has become a popular feature in modern programming languages. As a result, the time consumed by dynamic storage management can be up to one-third of the program execution time. This illustrates the need for a high-performance memory management scheme. This paper presents a top-level design and evaluation of the proposed instruction extensions to facilitate heap management.
1021056
A performance perspective on the Active Memory System
Abstract One major problem of using Java in real-time and embedded devices is the non-deterministic turnaround time of dynamic memory management systems (memory allocation and garbage collection). For the allocation, the non-determinism is often contributed by the time to perform searching, splitting, and coalescing. For the garbage collection, the turnaround time is usually determined by the size of the heap, the number of live objects, the number of object collected, and the amount of garbage collected. Even with the current state-of-the-art garbage collectors (generational and incremental schemes), they may or may not guarantee the worst-case latency. Moreover, such schemes often prolong overall garbage collection time. In this paper, the performance analysis of the proposed Active Memory Module (AMM) for embedded systems is presented. Unlike the software counterparts, the AMM can perform a memory allocation in a predictable and bounded fashion (14 cycles). Moreover, it can also yield a bounded sweeping time regardless of the number of live objects or heap size. By utilizing the proposed system, the overall speedup can be as high as 23% compared to the garbage collection system of the JDK 1.2.2 running in classic mode.
12198410
Scalable hardware-algorithm for mark-sweep garbage collection
The memory-intensive nature of object-oriented languages such as C++ and Java has created the need for high-performance dynamic memory management. Object-oriented applications often generate higher memory intensity in the heap region. Thus, a high-performance memory manager is needed to cope with such applications. As today's VLSI technology advances, it becomes increasingly attractive to map software algorithms such as malloc(), free() and garbage collection into hardware. This paper presents a hardware design of a sweeping function (for mark-and-sweep garbage collection) that fully utilizes the advantages of combinational logic. In our scheme, the bit sweep can detect and sweep the garbage in a constant time. Bit-map marking in software can improve the cache performance and reduce number of page faults; however, it often requires several instructions to perform a single mark. In our scheme, only one hardware instruction is required per mark. Moreover, since the complexity of the sweeping phase is often higher than the marking phase, the garbage collection time may be substantially improved. The hardware complexity of the proposed scheme (bit-sweeper) is O(n), where n represents the size of the bit map.
46189070
Optimal use of timing resources: a crucial step in test program generation
A modified timing set priority strategy and a lookahead register-replacement algorithm is presented for automatic test program generation. These methodologies are introduced to satisfy the testing requirements in complex VLSI chips, and are made possible by the increasing timing flexibility of modern ATE (automatic test equipment). It is shown that by applying optimization algorithms in allocating timing resources and a published timing set determination algorithm, that testing capability of modern ATE can be greatly extended. Further enhancements to these approaches are contingent on further improvements from ATE manufacturers in the number and flexibility of timing resources. However, the development of test programs will be greatly aided by this enhanced hardware.<<ETX>>
39527990
FPGA-based reconfigurable computing
16368228
Color pattern recognition by quaternion correlation
It is popular to use the conventional correlation for pattern recognition. But when using the conventional correlation, the pattern should be the gray-level pattern. In this paper, we discuss how to use discrete quaternion correlation (DQCR) for the application of color pattern recognition. With the algorithm introduced here, we can detect the objects that have the same shape, color, and brightness as the reference pattern. Besides, we can also detect (a) the objects with the same shape, color, but different brightness, (b) the objects with the same shape, brightness, but different color, and (c) the objects just have the same shape as the reference. Our algorithm can classify the objects into 5 classes due to whether their shape, brightness, and color match those of the reference pattern. Besides, with our algorithm, the difference of the brightness and color can also be calculated at the same time.
34947079
On the powers of graphs with bounded asteroidal number
Abstract For an undirected graph G =( V , E ), the kth power G k is the graph with the same vertex set as G such that two vertices are adjacent in G k if and only if their distance in G is at most k. A set of vertices A ⊆ V is an asteroidal set if for every vertex a ∈ A , the set A ⧹{ a } is contained in one connected component of G − N G [ a ], where N G [ a ] is the closed neighborhood of a in G. The asteroidal number of a graph G is the maximum cardinality of an asteroidal set in G. The class of graphs with asteroidal number at most s is denoted by A (s) . In this paper, we show that if G k ∈ A (s) for s ⩾2, then so is G k +1 . This generalizes a previous result for the family of AT-free graphs. Moreover, we consider the forbidden configurations for the powers of graphs with bounded asteroidal number. Based on these forbidden configurations, we show that every proper power of AT-free graphs is perfect.
14591723
A Sliding Window Method for Finding Recently Frequent Itemsets over Online Data Streams
A data stream is a massive unbounded sequence of data elements continuously generated at a rapid rate. Consequently, the knowledge embedded in a data stream is likely to be changed as time goes by. However, most of miming algorithms or frequency approximation algorithms for a data stream do not able to extract the recent change of information in a data stream adaptively. This paper proposes a sliding window method of finding recently frequent itemsets over an online data stream. The size of a window defines a desired life-time of the information of a transaction in a data stream.
13312657
Feedback vertex sets in star graphs
In a graph G = (V, E), a subset F ⊂ V(G) is a feedback vertex set of G if the subgraph induced by V(G) \ F is acyclic. In this paper, we propose an algorithm for finding a small feedback vertex set of a star graph. Indeed, our algorithm can derive an upper bound to the size of the feedback vertex set for star graphs. Also by applying the properties of regular graphs, a lower bound can easily be achieved for star graphs.
17161223
Speculative incoherent cache protocols
Multiprocessing and multithreading are becoming ubiquitous even on single chips. With increasing cache sizes, coherence misses in such systems will account for a larger fraction of all cache misses. As communication latencies increase, this larger fraction of coherence misses will cause significant and increased performance losses. Tuning coherence protocols for specific communication patterns and applications can reduce communication latencies. However, these optimizations increase a protocol's design complexity, making the protocol difficult to verify. A competing approach requires parallel programmers to tune applications to work well with simpler protocols. Speculative execution has successfully improved performance in various scenarios. We propose a new type of load speculation, called coherence decoupling. Coherence decoupling is a microarchitectural mechanism that implements separate protocols for speculative use and for the eventual verification of values. The technique reduces the effect of long communication latencies while mitigating the burdens on the coherence protocol designer and the parallel programmer