13416160
Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation
As the processing capabilities and operating frequency of embedded system are growing, so is the needed data bandwidth to fully utilize the processing capability. The ability to transfer huge amount of data between the embedded core and external devices is required for efficient system operation. In this paper, the data communication architecture for the mixed-clock system is proposed. The dynamic priority adaptation algorithm for bus arbitration is proposed for bandwidth guarantee. The communication architecture that incorporates the proposed arbitration algorithm adapts the priority of communication components dynamically based on the information from FIFO. The experiments show that the measured bandwidth of each component traces the required bandwidth well compared to the other arbitration algorithms.
15346879
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool
The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing instances to be located and signals to be routed in 3-D space. Wire resource prediction is important for fast and accurate interconnection planning in 3-D FPGA. In this paper, we extend the existing analytic model shown in [13] with a new parameter for our 3-D FPGA which has cluster-based logic blocks. The proposed wire resource prediction model is applied to our 3-D FPGA using a Xilinx Virtex2 slice [18] and our 3-D routing architecture. We validate the effectiveness of the extended model by comparing the required number of channel wires predicted by the extended analytic equation with that of the placed and routed results using 3-D placement and routing algorithm designed for our 3-D FPGA for a number of benchmark circuits. The extended 3-D wire resource prediction model predicts the required channel capacity with an average of 11.1% error for 17 large circuits from LGSynth93 and ISPD2001 Verilog benchmarks.
8120985
SCATOMi: scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multicasting interconnection architecture
FPGA-based logic emulator with large gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multiFPGA system incorporating several state-of-the-art FPGAs. We propose a circuit partitioning algorithm called SCATOMi(scheduling driven algorithm for TOMi) for multiFPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(time-multiplexed, off-chip, multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Experiments on architecture comparison show that, by adopting the proposed TOMi interconnection architecture along with SCATOMi, the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures including mesh, crossbar and VirtualWire architecture.
6984911
A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics
17804982
Signal Scheduling Driven Circuit Partitioning for Multiple FPGAs with Time-multiplexed Interconnection
FPGA-based logic emulator with large gate capacity generally comprises a large number of FPGAs. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporating several stateof-the-art FPGAs. This paper proposes a circuit partitioning algorithm called SCATOMi(SCheduling driven Algorithm for TOMi) for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(Time-multiplexed, Off-chip, Multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Experiments on architecture comparison show that, by adopting the proposed TOMi interconnection architecture along with SCATOMi, the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures including mesh, crossbar and VirtualWire architecture.
14181871
Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus
Simulation is the most viable solution for the functional verification of system-on-chip (SoC). The acceleration of simulation with multi-field programmable gate array (multi-FPGA) emulator is a promising method to comply with the increasing complexity and large gate capacity of SoC. Time multiplexing of interconnection wires is the inevitable solution to solve the pin limitation problem that limits the gate utilization of FPGAs and speed of multi-FPGA simulation accelerators. The most time-consuming factor of multi-FPGA simulation acceleration is the synchronization time between a software simulator and a multi-FPGA system and the inter-FPGA synchronization time. This paper proposes a performance-driven signal synchronization mechanism for a simulation accelerator with multiple FPGAs using time-multiplexed interconnection. The event-based signal synchronization optimizes the synchronization time between a software simulator and the multi-FPGA system as well as the synchronization time among FPGAs. The synchronization time among FPGAs is optimized by circuit partitioning considering the signal probability, net dependency reduction, and efficient net clustering to reduce addressing overhead. The synchronization time between the software simulator and the multi-FPGA system is also optimized by exploiting the event probability of primary nets. Experiments show that the synchronization time is reduced to 6.2-9.8% of traditional mechanisms.
30685161
Extending MSC for reactive systems
Message Sequence Charts (MSC) is a visual language that illustrates the scenarios of system operations, offering user-friendly, easy-to-understand behavioral descriptions. Furthermore, High-level MSC (HMSC) provides composition mechanisms to deal with the complexity of the system. However, for MSC to be used to describe complex reactive systems, there should be ways to deal with reactive behaviors that require the system to respond immediately. In this paper, we propose extensions of MSC to describe complex reactive behaviors in a systematic way. We define the formal semantics of the extended features based on process algebra, as well as the visual and textual syntax. The extensions allow structured, systematic and succinct descriptions of complex reactive behaviors.
8261294
Inter-class mutation operators for Java
The effectiveness of mutation testing depends heavily on the types of faults that the mutation operators are designed to represent. Therefore, the quality of the mutation operators is key to mutation testing. Mutation testing has traditionally been applied to procedural-based languages, and mutation operators have been developed to support most of their language features. Object-oriented programming languages contain new language features, most notably inheritance, polymorphism, and dynamic binding. Not surprisingly; these language features allow new kinds of faults, some of which are not modeled by traditional mutation operators. Although mutation operators for OO languages have previously been suggested, our work in OO faults indicate that the previous operators are insufficient to test these OO language features, particularly at the class testing level. This paper introduces a new set of class mutation operators for the OO language Java. These operators are based on specific OO faults and can be used to detect faults involving inheritance, polymorphism, and dynamic binding, thus are useful for inter-class testing. An initial Java mutation tool has recently been completed, and a more powerful version is currently under construction.
16141068
Improving cohesion metrics for classes by considering dependent instance variables
The existing cohesion metrics for classes do not consider the characteristics of dependent instance variables that are commonly used in a class and, thus, do not properly reflect the cohesiveness of the class. This paper presents an approach for improving the cohesion metrics by considering the characteristics of the dependent instance variables in an object-oriented program.
1158464
Response to 'More comments on: A cohesion measure for object-oriented classes'
The authors insist that monotonicity is a necessary property of a good cohesion metric and the violation of the monotonicity property limits the application of CBMC. They also state that the augmented CBMC can also be used as a guideline for quality evaluation and restructuring of poorly designed classes. This paper raises the question about the necessity of monotonicity by analyzing the reason that causes CBMC to violate the monotonicity property. In addition, we give a detailed description of the restructuring procedure based on CBMC. Copyright c © 2003 John Wiley & Sons, Ltd.
7677555
Stock prediction based on financial correlation
In this paper, we propose a neuro-genetic stock prediction system based on financial correlation between companies. A number of input variables are produced from the relatively highly correlated companies. The genetic algorithm selects a set of informative input features among them for a recurrent neural network. It showed notable improvement over not only the buy-and-hold strategy but also the recurrent neural network using only the input variables from the target company.