38388612
Partial reset methodologies for improving random-pattern testability and BIST of sequential circuits
The use of partial reset has been shown to have significant impact on test generation in a stored-pattern test application environment for sequential circuits. In this paper, we explore the use of partial reset in fault-independent testing and its application to built-in self-test of nonscan sequential circuits. Switching activities of circuit nodes coupled with the node interconnection structure is used to select a subset of the circuit flip-flops to be reset to logic 0 or logic 1 during test application. An average improvement of 15% in fault-coverage is obtained for circuits resistant to random pattern testing over existing full reset methods. We also present a technique to insert observable test points based on activity propagation analysis. With the combined partial reset and observable test point insertion methodologies, high fault coverages were obtained for most of our benchmark circuits.
40322711
Hierarchical specification-driven analog fault modeling for efficient fault simulation and diagnosis
In this paper we discuss the capabilities of the MiST PROFIT (Mixed Signal Test Program for Fault Insertion and Testing) software for hierarchical fault modeling, tolerance modeling, fault clustering and fault diagnosis of complex mixed-signal systems. The software is designed to exploit the relationships between high level system specifications and module-level faults in complex and nonlinear mixed signal systems. Hierarchical simulation based methods are used to capture fault effects at different levels of circuit abstraction. The key features of our approach are: (a) the ability to compute tolerance effects from nonlinear behavioral models at different levels of circuit design hierarchy accurately using low-cost simulation based methods, (b) the ability to perform compaction of fault effects while transferring fault effects from the leaf cells to the highest level behavioral models, (c) the ability to capture parametric (soft) failure effects over the entire anticipated range of faulty parameter values and (d) the ability to construct fault dictionaries given a set of least replaceable units to diagnose.
31808942
A novel low-cost approach to MCM interconnect test
This paper describes a novel and low-cost technique for detecting process-related interconnect faults in MCMs. This method is an alternative to existing test methods such as TDR, TDT electron beam, and capacitance techniques which are either expensive in terms of test equipment, are cumbersome due to the requirement of multiple probes, or provide poor fault coverage. The proposed technique applies a stimulus through a tuned load and a single probe at one end of the interconnect. By measuring the attenuation of the test stimulus due to pole movement relative to known attenuation measurements, interconnect faults such as near-opens, near-shorts, opens, and shorts can be detected. The total test time is small and the hardware cost of test equipment is low. Extensive simulations have been performed to show the validity of the method.
27941486
Distributed probabilistic diagnosis of MCMs on large area substrates
This paper addresses the issue of testing MCMs on large-area substrates. The cost of testing each MCM may be as high as 40% of the total manufacturing cost. It is critical that the test process be parallelized in order that multiple MCMs may be tested for the cost of testing one MCM. With this objective in mind, we propose a distributed probabilistic diagnosis algorithm for MCMs on large-area substrates. Our algorithm performs better than the existing diagnosis algorithms and can correctly identify almost all MCMs even when the yield is very low (35%). Further it provides upto an order of magnitude reduction in test application time as opposed to serial MCM probe test.
407279
Signature analysis for analog and mixed-signal circuit test response compaction
While the design of signature analyzers for digital circuits has been well researched in the past, signature analyzers for analog signals are relatively unknown. The primary difficulty in analyzing signatures for analog signals is that the latter are imprecise in nature. Therefore, deterministic signature analysis schemes, such as those based on finite-field arithmetic using linear feedback shift registers, are unsuitable for analog circuits. In this paper, a novel signature analysis scheme for analog and mixed signal circuits is proposed. The signatures possess the interesting property that if the input analog signal is imprecise within certain bounds (an inherent property of analog signals), then the generated signature is also imprecise within certain bounds. A failure is indicated by the generated signature being different from the expected signature by a margin greater than a predetermined threshold; the larger the effects of the failure, the larger the difference between the generated signature and the expected signature. The probabilities of aliasing and false rejection are also derived. Results for an example filter circuit are presented.
11978875
Matching structural shape descriptions using genetic algorithms
Abstract This paper presents a genetic algorithm for solving the problem of structural shape matching. Both sequential and parallel versions of the algorithm have been presented. The genetic operators-reproduction, crossover and mutation-have been constructed for this specific problem. A new variation of the crossover operator, called the color crossover, is presented. This operator has resulted in significant improvement in runtime and algorithm efficiency. Parallelization has been achieved using an “island” model, with several subpopulations and occasional migration. A complete framework for an object recognition system using this genetic algorithm has been presented. Encouraging experimental results have been obtained.
45280262
Leveraging information in multi-echelon inventory systems
Abstract Decision-making in multi-echelon inventory systems is often facilitated by the availability of information. In this paper, we examine the effect of utilising demand information in a one-warehouse two-retailer system operating under periodic-review. A common and fixed replenishment interval is assumed for all stages. The lead times are deterministic, and are small compared to the replenishment interval. The warehouse does not maintain any cycle stock, i.e., as soon as replenishment arrives at the warehouse, retailers’ demands are fulfilled from the available stock. In the event of a shortage at the warehouse, two cases have been considered––emergency shipment and allocation. For both the cases, expected total cost (ETC) models have been developed, and it has been shown through numerical examples that the optimal ETC in the presence of demand information is always lower than that in the absence of demand information. It is also noted that the order-up-to level at the warehouse has to be dynamic to reap the benefits of availability of demand information.