16445226
Modal expansion of HRTFs: Continuous representation in frequency-range-angle
This paper proposes a continuous HRTF representation in both 3D spatial and frequency domains. The method is based on the acoustic reciprocity principle and a modal expansion of the wave equation solution to represent the HRTF variations with different variables in separate basis functions. The derived spatial basis modes can achieve HRTF near-field and far-field representation in one formulation. The HRTF frequency components are expanded using Fourier Spherical Bessel series for compact representation. The proposed model can be used to reconstruct HRTFs at any arbitrary position in space and at any frequency point from a finite number of measurements. Analytical simulated and measured HRTFs from a KEMAR are used to validate the model.
12929858
UWB Spatia - Frequency Channel Characterization
This paper investigates the spatial-frequency channel characterization of ultra-wideband (UWB) wireless communication systems. First, a novel frequency dependent UWB channel model is constructed based on the theory of electromagnetic diffraction mechanism, which causes the field strength to vary with the frequency in each multipath. Then, we build a space-frequency model, which includes spatial characteristics such as angular power spectrum, and physical sampling points in space. The space-frequency model has two special cases (i) discrete multipath model, and (ii) cluster model, which can be readily used to generate channel data for any arbitrary set of sensor locations. The reconstruction results from channel measurements show the accurateness of the novel frequency dependent model, with reconstruction error decreasing by 40%, compared to the traditional Turin model
32452076
Replica Victim Caching to Improve Reliability of In-Cache Replication
Soft error conscious cache design is a necessity for reliable computing. ECC or parity-based integrity checking techniques in use today either compromise performance for reliability or vice versa. The recently-proposed ICR (In-Cache Replication) scheme can enhance data reliability with minimal impact on performance, however, it can only exploit a limited space for replication and thus cannot solve the conflicts between the replicas and the primary data without compromising either performance or reliability. This paper proposes to add a small cache, called replica victim cache, to solve this dilemma effectively. Our experimental results show that a replica victim cache of 4 entries can increase reliability of L1 data caches 21.7% more than ICR without impacting performance, and the area overhead is within 10%.
14650134
Reducing branch predictor leakage energy by exploiting loops
With the scaling of technology, leakage energy will become the dominant source of energy consumption. Besides cache memories, branch predictors are among the largest on-chip array structures and consume nontrivial leakage energy. This paper proposes two cost-effective loop-based strategies to reduce the branch predictor leakage without impacting prediction accuracy or performance. The loop-based approaches exploit the fact that loops usually only contain a small number of instructions and, hence, even fewer branch instructions while taking a significant fraction of the execution time. Consequently, all the nonactive entries of branch predictors can be placed into the low leakage mode during the loop execution in order to reduce leakage energy. Compiler and circuit supports are discussed to implement the proposed leakage-reduction strategies. Compared to the recently proposed decay-based approach, our experimental results show that the loop-based approach can extract 16.2% more dead time of the branch predictor, on average, leading to more leakage energy savings without impacting the branch prediction accuracy and performance.
10278111
Compiler-directed instruction cache leakage optimization
Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consumed due to leaky memory cells in on-chip caches will constitute a significant portion of the processor's power budget. This work focuses on reducing the leakage energy consumed in the instruction cache using a compiler-directed approach.We present and analyze two compiler-based strategies termed as conservative and optimistic. The conservative approach does not put a cache line into a low leakage mode until it is certain that the current instruction in it is dead. On the other hand, the optimistic approach places a cache line in low leakage mode if it detects that the next access to the instruction will occur only after a long gap. We evaluate different optimization alternatives by combining the compiler strategies with state-preserving and state-destroying leakage control mechanisms.
12152152
Interprocedural optimizations for improving data cache performance of array-intensive embedded applications
As datasets processed by embedded processors increase in size and complexity, the management of higher levels of memory hierarchy (e.g., caches) is becoming an important issue. A major limitation of most of the cache locality optimization techniques proposed by previous research is that they handle a single procedure at a time. This prevents compilers from capturing the data access interactions between procedures and may result in poor performance. In this paper, we look at loop and data transformations from a different angle and use them in an interprocedural optimization framework. Employing the call graph representation of a given application, the proposed technique visits each node of this graph twice and uses loop and data transformations in a systematic way for optimizing array layouts whole program wide. Our experimental results show that this interprocedural locality optimization strategy is much more effective than the previous locality-based techniques that handle each procedure in isolation.