15526593
Low-energy off-chip SDRAM memory systems for embedded applications
Memory systems are dominant energy consumers, and thus many energy reduction techniques for memory buses and devices have been proposed. For practical energy reduction practices, we have to take into account the interaction between a processor and cache memories together with application programs. Furthermore, energy characterization of memory systems must be accurate enough to justify various techniques. In this article, we build an in-house energy simulator for memory systems that is accelerated by special hardware support while maintaining accuracy. We explore energy behavior of memory systems for various values of the processor and memory clock frequencies and cache configuration. Each experiment is performed with 24M instruction steps of real application programs to guarantee accuracy.The simulator is based on precise energy characterization of memory systems including buses, bus drivers, and memory devices by a cycle-accurate energy measurement technique. We characterize energy consumption of each component by an energy state machine whose states and transitions are associated with the dynamic and static energy costs, respectively. Our approach easily characterizes the energy consumption of complex SDRAMs. We divide and quantify energy components of main memory systems for high-level reduction. The energy simulator enables us to devise practical energy reduction schemes by providing the actual amount of reduction out of the total energy consumption in main memory systems. We introduce several practical energy reduction techniques for SDRAM memory systems and demonstrate energy reduction ratio over the SDRAM memory systems with commercial SDRAM controller chipsets. We classify the SDRAM memory systems into high-performance and mid-performance classes and achieve suitable system configurations for each class. For instance, a typical high-performance 32-bit, 64 MB SDRAM memory system consumes 19.6 mJ, 33.8 mJ, 35.4 mJ, and 37.0 mJ for 24M instructions of an MP3 decoder, a JPEG compressor, a JPEG decompressor, and an MPEG4 decoder, respectively. Our reduction scheme saves 12.7 mJ, 15.1 mJ, 15.5 mJ, and 14.8 mJ, and the reduction ratios are 64.8%, 44.6%, 43.8%, and 40.1%, respectively, without compromising execution speed.
1609683
Web-Based Energy Exploration Tool for Embedded Systems
We describe a Web-based energy estimation tool for embedded systems. An interesting feature of this tool is that it performs real-time cycle-accurate energy measurements on a hardware prototype of the processor. The authors describe the various steps involved in using the tool and present case studies to illustrate its utility.
1627364
DC-DC converter-aware power management for battery-operated embedded systems
Most digital systems are equipped with DC-DC converters to supply various levels of voltages from batteries to logic devices. DC-DC converters maintain legal voltage ranges regardless of the load current variation as well as battery voltage drop. Although the efficiency of DC-DC converters is changed by the output voltage level and the load current, most existing power management techniques simply ignore the efficiency variation of DC-DC converters. However, without a careful consideration of the efficiency variation of DC-DC converters, finding a true optimal power management is impossible. In this work, we solve the problem of energy minimization with the consideration of the characteristics of power consumption of DC-DC converter. Specifically, the contributions of our work are: (1) We analyze the effects of the efficiency variation of DC-DC converters on a single task execution in DVS (dynamic voltage scaling) scheme, and propose a technique, called DC/spl I.bar/DVS, of DC-DC converter-aware energy-minimal DVS; (2) DC/spl I.bar/DVS is then extended to combine the effects of DC-DC converters with the procedures of general DVS techniques with multiple tasks; (3) Conversely, we propose a technique, called DC/spl I.bar/CONF, of generating a DC-DC converter that is best suited, in terms of total energy efficiency, to the intended application, and (4) finally, we complete our integrated framework DC-lp, which is based on DC/spl I.bar/DVS and DC/spl I.bar/CONF, that attempts to solve the DC-DC converter configuration selection problem and the DVS problem simultaneously. To show the effectiveness of the proposed techniques, a set of experimental results is provided. In summary, it is shown that DC-lp is able to save 16.0% /spl sim/ 22.1% of energy on the average, which otherwise was dissipated in the previous power management schemes with no consideration of DC-DC converter efficiency variation.
195882206
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design
The delay of memory access is one of the major bottlenecks in embedded systems' performance. In software compilation, it is known that there are high variations in memory access delay depending on the ways of storing/retrieving the variables in code to/from the memories. In this paper, we propose an effective storage assignment technique for variables to maximize the use of memory bandwidth. Specifically, we study the problem of DRAM memory layout for storing the nonarray variables in code to achieve a maximum utilization of page and/or burst modes for the memory accesses. The contributions of our work are, for each of page and burst modes: (1) We prove that the problem is NP-hard; (2) We propose an exact formulation of the problem and efficient memory layout algorithms, called Solve-MLP for the page mode and Solve-MLB for the burst mode; From experiments with a set of benchmark programs, we confirm that our proposed techniques use on average 20.0% and 9.9% more page accesses and 54.0% and 86.6% more burst accesses than those by OFU (the order of first use) and the technique in P.R. Panda et al. (1997), respectively.
12101738
OpinionFinder: A System for Subjectivity Analysis
OpinionFinder is a system that performs subjectivity analysis, automatically identifying when opinions, sentiments, speculations, and other private states are present in text. Specifically, OpinionFinder aims to identify subjective sentences and to mark various aspects of the subjectivity in these sentences, including the source (holder) of the subjectivity and words that are included in phrases expressing positive or negative sentiments.
4649924
WAF: wireless-adaptive fair scheduling for multimedia stream in time division multiplexed packet cellular systems
Cellular systems are designed to support voice service over the wireless channel but nowadays data-only networks such as cdma2000 1x EV-DO and high speed downlink packet access (HSDPA) are being deployed in the midst of evolution to the next generation wireless networks. Such systems become important because data services are essential in future wireless networks that are supposed to adopt the concept of all-IP to support integrated services. To increase the data transmission rate at downlink in cdma2000 1x EV-DO and HSDPA, the base station (BS) uses only a channel multiplexed by time division, not by code division. These systems use proportional fair scheduling to maximize throughput. While it is useful for non real time traffic, it does not provide appropriate QoS for real time services such as voice and video. Therefore we need to incorporate the multimedia QoS requirements into the design of a new scheduling algorithm. Our proposed wireless-adaptive fair scheduling (WAF) tries to allocate time slots with fair share according to the stream requirements considering the varying channel conditions to achieve good throughput. The simulation results show that our scheme can guarantee fair service and increase throughput by up to 41% compared to the purely fair (PF) scheduling scheme.
4648734
Selective channel feedback mechanisms for wireless multichannel scheduling
Opportunistic scheduling can significantly improve wireless network performance by exploiting the feedback information that conveys the underlying channel condition. In emerging multichannel systems, the perchannel feedback induces a substantial amount of feedback overhead and requires high computational complexity. To reduce the feedback overhead, we consider an opportunistic feedback strategy that activates the channel feedback opportunistically according to the channel condition. Then, we combine the opportunistic feedback with the best-n channel feedback scheme where a mobile user chooses the best n channels and transfers this information to the base station. We analyze the throughput and the amount of channel feedback information for proportionally fair opportunistic scheduling under Rayleigh fading i.i.d. channels. The numerical results confirm that our partial feedback schemes achieve a remarkable reduction in the amount of feedback information without a significant throughput degradation, thereby saving the scarce wireless bandwidth and limited battery power
15341580
Optimal register reassignment for register stack overflow minimization
Architectures with a register stack can implement efficient calling conventions. Using the overlapping of callers' and callees' registers, callers are able to pass parameters to callees without a memory stack. The most recent instance of a register stack can be found in the Intel Itanium architecture. A hardware component called the register stack engine (RSE) provides an illusion of an infinite-length register stack using a memory-backed process to handle overflow and underflow for a physically limited number of registers. Despite such hardware support, some applications suffer from the overhead required to handle register stack overflow and underflow. The memory latency associated with the overflow and underflow of a register stack can be reduced by generating multiple register allocation instructions within a procedure [Settle et al. 2003]. Live analysis is utilized to find a set of registers that are not required to keep their values across procedure boundaries. However, among those dead registers, only the registers that are consecutively located in a certain part of the register stack frame can be removed. We propose a compiler-supported register reassignment technique that reduces RSE overflow/underflow further. By reassigning registers based on live analysis, our technique forces as many dead registers to be removed as possible. We define the problem of optimal register reassignment, which minimizes interprocedural register stack heights considering multiple call sites within a procedure. We present how this problem is related to a path-finding problem in a graph called a sequence graph. We also propose an efficient heuristic algorithm for the problem. Finally, we present the measurement of effects of the proposed techniques on SPEC CINT2000 benchmark suite and the analysis of the results. The result shows that our approach reduces the RSE cycles by 6.4% and total cpu cycles by 1.7% on average.