32286255
Hardware Organization to Achieve High-Speed Elliptic Curve Cryptography for Mobile Devices
Elliptic curve cryptography (ECC) is recognized as a fast cryptography system and has many applications in security systems. In this paper, a novel sharing scheme is proposed to significantly reduce the number of field multiplications and the usage of lookup tables, providing high speed operations for both hardware and software realizations.
29637234
A new architecture of RRNS error-correcting QC encoder/decoder and its FPGA implementation
In this paper, a new architecture of a redundant residue number system (RRNS) quasi-chaotic (QC) encoder/decoder with an error-correcting ability is proposed for secure communication and is tailored to FPGA implementation. In the proposed architecture, binary subencoders and subdecoders are used so that a number of modulo operations required in the existing design of D. R. Frey (IEEE Trans. Circuits Syst. II, vol. 40, pp. 660-666, Oct. 2000) are replaced by a simple truncation. Furthermore, a size-reduced design of the R/B (residue-to-binary) converter with error-correcting function, which is the crucial part of the system, is proposed. As a case study, the proposed architecture is implemented in FPGA for the case of the 16-bit input and some simulation results obtained.
29715580
A high-speed residue-to-binary converter and a scheme for its VLSI implementation
In this paper, a high-speed residue-to-binary converter for the recently introduced moduli set (2/sup k/, 2/sup k/-1, 2/sup k-1/-1) is proposed. Compared to the previous converter based on this moduli set, the proposed one is 40% faster; also, the time-complexity product is improved by 20%. Following the VLSI design flow established by the Canadian Microelectronics Corporation, the proposed converter is implemented in 0.5-micron CMOS technology. Based on this moduli set, layouts of the 8-bit, 16-bit, 32-bit and 64-bit residue-to-binary converters which can be used in further RNS system designs, are generated and simulation results obtained.
15012785
An area-reduced scheme for modulo 2/sup n/-1 addition/subtraction
In this paper, we present a versatile area-reduced scheme for modulo 2/sup n/-1 adders and subtracters using a MUX-based increment/decrement algorithm. A FPGA-based comparison of the proposed modulo adder and the conventional modulo adder designs is carried out. The implementation results show that the proposed adder reduces the area close to 30% compared with the modulo adder of Bayoumi et al. The delay and the power are also reduced around 10%. In addition, it is also shown that the proposed design requires less hardware resources than the parallel-prefix modulo adder of Kalampoukas et al. while providing a comparable operation speed.
31496165
Elliptic curves cryptosystem implementation based on a look-up table sharing scheme
Projective point elliptic curve cryptography (ECC) involves many look-up table-based field multiplications. In this paper, a novel lookup table sharing scheme is proposed to significantly reduce the number of the field multiplications and number of lookup tables. By requiring much less lookup table generation time, the proposed system offers high-speed performance for hardware realizations. Its application in a reconfigurable PC-FPGA platform is investigated, which can efficiently handle requests for different ECC key length and curves and is useful for many computer network applications
15644746
RRNS quasi-chaotic coding and its FPGA implementation
In this paper, a new architecture of the redundant residue number system (RRNS) based quasi-chaotic coding is proposed for the secure telecommunication systems and networks. In the proposed architecture, a number of modulo operations required by the existing designs are replaced by binary coding operations to simplify the design. Also, a moduli selection method and a residue-to-binary converter with error-correction capability are proposed to further improve the efficiency of the design specifically for FPGA implementation. The proposed architecture is implemented and tested using Matlab and Xilinx FPGA hardware. The results show that compared to the existing design, the proposed design requires only 80% of the hardware resources while maintaining the same speed. The power consumption is also reduced by 25%.
32534487
Image Segmentation That Merges Together Boundary and Region Information
Segmentation is a classical yet important problem in vision. Most of the previous works are either region-based or boundary-based. The two approaches own complementary merits - while the region-based one always produces closed boundaries, the boundary-based one involves primarily local operations and avoids the complexity of deciding how homogeneous a region and how inhomogeneous neighboring regions should be. In this paper, we propose a new solution mechanism that makes use of both cues. We use the boundary processing and a particular field model to come up with a number of coarse, initial closed boundaries about the image first. Such coarse boundaries will then, through an adaptation of the Four Color Theorem, serve as the initialization to a level-set method-based minimization that acts on the intensity distribution of the image, and allows the final crispy segmentation result to emerge. Compared with the existing solutions, our method requires no initialization from the user, and the automatically extracted closed contours do provide guidance to derive more optimal and smoother segmentation result. Experimental results with some benchmarking image-sets show that the proposed solution could deliver accurate segmentation boundary.
2629783
Optimal Rate-Based Image Transmissions via Multiple Paths in Wireless Sensor Network
Many sensor applications such as monitoring and surveillance may require image sensor array to conduct collaborative image transmissions in wireless sensor network (WSN). The large size image transmission in WSN is a bottleneck due to the limited energy resources. In this paper, we propose an optimal scheme for image sensors to utilize inter-sensor correlations to decide transmission patterns based on a multi-level rate-oriented routing (MLRR) routing scheme, which achieves high energy efficiencies and longer network lifetime. This optimization scheme allows each image sensor to transmit optimal fractions of the overlapped images through appropriate multiple rate-oriented routing paths. The simulation results by using GA algorithm show that the proposed image transmission scheme can achieve considerable gains in terms of the WSN energy efficiency and network lifetime extension.
5517318
Power Control for Distributed MAC Protocols in Wireless Ad Hoc Networks
In centralized wireless networks, reducing the transmission power normally leads to higher network transport throughput. In this paper, we investigate power control in a different scenario, where the network adopts distributed MAC layer coordination mechanisms. We first consider widely adopted RTS/CTS based MAC protocols. We show that an optimal power control protocol should use higher transmission power than the "just enough" power in order to improve spatial utilization. The optimal protocol has a minimal transmission floor area of Theta(dijdmax), where dmax is the maximal transmission range and dij is the link length. This surprisingly implies that if a long link is broken into several short links, then the sum of the transmission floors reserved by the short links is still comparable to that reserved by the long link. Thus, using short links does not necessarily lead to higher throughput. Another consequence of this is that, with the optimal RTS/CTS based MAC, rate control can at best provide a factor of 2 improvement in transport throughput. We then extend our results to other distributed MAC protocols which uses physical carrier sensing or busy-tone as the control signal. Our simulation results show that the optimal power controlled scheme outperforms other popular MAC layer power control protocols.
3069611
A General Framework for Fast Co-clustering on Large Datasets Using Matrix Decomposition
Simultaneously clustering columns and rows (co- clustering) of large data matrix is an important problem with wide applications, such as document mining, microarray analysis, and recommendation systems. Several co-clustering algorithms have been shown effective in discovering hidden clustering structures in the data matrix. For a data matrix of m rows and n columns, the time complexity of these methods is usually in the order of mtimesn (if not higher). This limits their applicability to data matrices involving a large number of columns and rows. Moreover, an implicit assumption made by existing co-clustering methods is that the whole data matrix needs to be held in the main memory. In this paper, we propose a general framework, CRD, for co-clustering large datasets utilizing recently developed sampling- based matrix decomposition methods. The time complexity of our approach is linear in m and n. And it does not require the whole data matrix be in the main memory. Experimental results show that CRD achieves competitive accuracy to existing co-clustering methods but with much less computational cost.
37619733
Taming Underlying Design for Energy Efficient Distributed Source Coding in Multirate Wireless Sensor Network
Signal processing applications such as Distributed Source Coding (DSC) in Wireless Sensor Network (WSN) are often multirate in nature, which provide additional significant opportunities in WSN design for achieving energy efficiency. In this paper, we analyze the DSC traffic for signal processing applications in multirate WSN and propose a novel rate oriented approach with MAC and PHY cross layer utilization to achieve high energy efficiency. Simulation results show that the proposed approach achieves significant energy efficiency by a factor of three while maintaining the transmission quality in WSN. This approach can be easily extended to other WSN MAC and PHY designs, providing multirate service to application layer to allow achieving higher energy efficiency