13164102
Worst-case-optimal algorithms for guarding planar graphs and polyhedral surfaces
We present an optimal Θ(n)-time algorithm for the selection of a subset of the vertices of an n-vertex plane graph G so that each of the faces of G is covered by (i.e., incident with) one or more of the selected vertices. At most ⌊n/2⌋ vertices are selected, matching the worst-case requirement. Analogous results for edge-covers are developed for two different notions of "coverage". In particular, our linear-time algorithm selects at most n - 2 edges to strongly cover G, at most ⌊n/3⌋ diagonals to cover G, and in the case where G has no quadrilateral faces, at most ⌊n/3⌋ edges to cover G. All these bounds are optimal in the worst-case. Most of our results flow from the study of a relaxation of the familiar notion of a 2-coloring of a plane graph which we call a face-respecting 2-coloring that permits monochromatic edges as long as there are no monochromatic faces. Our algorithms apply directly to the location of guards, utilities or illumination sources on the vertices or edges of polyhedral terrains, polyhedral surfaces, or planar subdivisions.
38367030
Partitions of complete geometric graphs into plane trees
Consider the following question: does every complete geometric graph K"2"n have a partition of its edge set into n plane spanning trees? We approach this problem from three directions. First, we study the case of convex geometric graphs. It is well known that the complete convex graph K"2"n has a partition into n plane spanning trees. We characterise all such partitions. Second, we give a sufficient condition, which generalises the convex case, for a complete geometric graph to have a partition into plane spanning trees. Finally, we consider a relaxation of the problem in which the trees of the partition are not necessarily spanning. We prove that every complete geometric graph K"n can be partitioned into at most n-n/12 plane trees. This is the best known bound even for partitions into plane subgraphs.
24680353
Facility Location Constrained to a Polygonal Domain
We develop efficient algorithms for locating an obnoxious facility in a simple polygonal region and for locating a desirable facility in a simple polygonal region. Many realistic facility location problems require the facilities to be constrained to lie in a simple polygonal region. Given a set S of m demand points and a simple polygon R of n vertices, we first show how to compute the location of an obnoxious facility constrained to lie in R, in O((m + n) logm + mlog n) time. We then show how to compute the location of a desirable facility constrained to lie in R, also in O((m + n) logm + mlog n) time. Both running times are an improvement over the known algorithms in the literature. Finally, our results generalize to the setting where the facility is constrained to lie within a set of simple polygons as opposed to a single polygon at a slight increase in complexity.
45018692
The Grid Placement Problem
We consider the problem of placing a regular grid over a set of points in order to minimize (or maximize) the number of grid cells not containing any points. We give an O(n log n) time and O(n) space algorithm for this problem. As part of this algorithm we develop a new data structure for solving a problem on intervals that is interesting in its own right and may have other applications.
1566102
On simplifying dot maps
Dot maps--drawings of point sets--are a well known cartographic method to visualize density functions over an area. We study the problem of simplifying a given dot map: given a set P of points in the plane, we want to compute a smaller set Q of points whose distribution approximates the distribution of the original set P.We formalize this using the concept of e-approximations, and we give efficient algorithms for computing the approximation error of a set Q of m points with respect to a set P of n points (with m ≤ n) for certain families of ranges, namely unit squares, arbitrary squares, and arbitrary rectangles.If the family R of ranges is the family of all possible unit squares, then we compute the approximation error of Q with respect to P in O(n log n) time. If R is the family of all possible rectangles, we present an O(mn log n) time algorithm. If R is the family of all possible squares, then we present a simple O(m2n + n log n) algorithm and an O(n2 √n log n) time algorithm which is more efficient in the worst case.Finally, we develop heuristics to compute good approximations, and we evaluate our heuristics experimentally.
5595756
Bounds for Frequency Estimation of Packet Streams
We consider the problem of approximating the frequency of frequently occurring elements in a stream of length n using only a memory of size m n. This models the process of gathering statistics on Internet packet streaming using a memory that is small relative to the number of classes (e.g. IP addresses) of packets. We show that when some data item a occurs αn times in a stream of length n, the FREQUENT algorithm of Demaine et al. [4], can approximate a’s frequency with an error of no more than (1−α)n/m. We also give a lower-bound of (1−α)n/(m+1) on the accuracy of any deterministic packet counting algorithm, which implies the FREQUENT algorithm is nearly optimal. Finally, we show that randomized algorithms can not be significantly more accurate since there is a lower bound of (1−α)Ω(n/m) on the expected accuracy of any randomized packet counting algorithm.
44925839
MHPS-Driven Early Design and Analysis of VLSI CPU Chips
JVe present (1 noid appsoaclz to carry per/i,rinancc analysis arid tiiiiitig of VLSI processors, don(? in the context of higlt-lewl source Iceriicls. U7e illustrate our rnetliodology in 1Crt71.r of a small (exaniph?) super scalas RlSC J ~ S O C ~ S S I ~ S architecture. A pnrantetrized execution 17ic~cIeI is used fhr piforinance eslimniion. IJsing an iterative optimization techniqire, the parameter set can bc locally optiinizcd around a g i i w design point to genesare tlie ininii?itrtn cycles per. iiwtrttction ( V I ) . W e also iiicludc a ctirsory discussion on linking .rirclt a CI’I estiiizntor io an early jloorplanner jhr A f IPS-driven block layout for the processor chb.
2688591
Interactive program improvement via EAVE: an expert adviser for vectorization
An example of a state-of-the-art high-end mainframe is the IBM 3090 VF; its associated compiler, the IBM VS Fortran (version 2) compiler, incorporates some of the latest techniques in automatic vectorization and code optimization. Advances in compiler technology not withstanding, a potential limitation is the “knowledge gap” which exists between the typical end user and the compiler/machine sub-system. In particular, the user often does not know how to write source code which will result in generation of efficient, high performance object code. In this paper, we address the issue of providing interactive aids for program development and transformation as a means to bridge this knowledge gap. We show how heuristic program changes, guided by the knowledge of a particular compiler-machine pair, help approach achievable peak performance through enhanced vectorization/parallelization. We present our techniques and results in terms of an implemented expert system, called EAVE, which has been designed to help users tune their programs for enhanced performance on the IBM 3090 VF.
37031042
Architectural timing verification and test for super scalar processors
We address the problem of verification and testing of super scalar processors, from the point of view of correctness of [Bprogram execution time. Trace-driven architectural si[Bmulation methods are commonly used in current industrial practice to estimate cycles-per-instruction performance of a candidate processor organization, prior to actual implementation. We present a novel set of strategies for testing the timing correctness of processors as represented in an architectural timing model ("timer"). We focus on two main aspects of the theory: (a) deriving architectural test sequences to cover possible failure modes, defined in the context of a pipeline flow state transition fault model; and (b) deriving loop test kernels to verify steady-state (periodic) behavior of pipeline flow, against analytically predicted signatures. We develop the theory in the context of an example super scalar processor and its timer model.<<ETX>>
18281114
Performance and functional verification of microprocessors
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of the validation problem: (a) verifying the functional integrity of the model and (b) testing the model for timing accuracy at the architectural level. The latter area, that of performance verification, is of increasing importance in the design of server-class processor chips, with one or more high performance cores on a single die. We show how simulation-based test cases can be generated under a unified defect and coverage model to detect both performance and functional bugs. We present and discuss examples of such integrated validation methodologies used in real processor development projects.
39390134
Ensuring dependable processor performance: an experience report on pre-silicon performance validation
The focus of today's processor validation methodology is primarily on ensuring functional integrity. Increasingly, however, pre-silicon performance validation is becoming part of the design verification challenge. Identification and elimination of performance deficiencies and bugs in the design prior to tape-out is an important aspect of building robust and dependable hardware. Many performance bugs are caused by latent functional defects in the pre-silicon software model of the machine. Besides, robust performance can be a key determinant of quality of service in applications like Web-serving. The authors review the performance validation methodology that they have developed and experimented with over the past few years. They also present examples and experimental results illustrating the use of this methodology in high end PowerPC processor development projects. The scope of the paper is limited to architectural performance, measured by metrics like instructions per cycle (IPC) or its inverse, CPI.