14558888
An Adaptive Issue Queue for Reduced Power at High Performance
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue queue for a superscalar processor that leverages transmission gate insertion to provide dynamic low-cost configurability of size and speed. A novel circuit structure dynamically gathers statistics of issue queue activity over intervals of instruction execution. These statistics are then used to change the size of an issue queue organization on-the-fly to improve issue queue energy and performance. When applied to a fixed, full-size issue queue structure, the result is up to a 70% reduction in energy dissipation. The complexity of the additional circuitry to achieve this result is almost negligible. Furthermore, self-timed techniques embedded in the adaptive scheme can provide a 56% decrease in cycle time of the CAM array read of the issue queue when we change the adaptive issue queue size from 32 entries (largest possible) to 8 entries (smallest possible in our design).
31462412
Performance evaluation and validation of microprocessors
The domain of early performance analysis and microarchitecture definition is limited largely to a onedimensional perspective of net performance: that of cyclesper-instnrction (CPI). Traceor execution-driven cycle-bycycle simulators [l] are the most common toolsets used at this stage. These are often coded in a systems programming language (e.g. C, C++, PWl or Pascal). They are performance-only models in that the register and memory data values and their state changes are not modelled; only the complex pipeline flow and concurrent instruction processing semantics are simulated. The goal here is to assess CPIcentric performance and bottlenecks to aid early definition, not to ensure functional integrity. Such a simulator, which we call a CPI timer; can be implemented to run at speeds greater than 50,000 instructions per second [21. This is achieved in modelling a future processor with the simulator running on a current generation uniprocessor workstation.
44925839
MHPS-Driven Early Design and Analysis of VLSI CPU Chips
JVe present (1 noid appsoaclz to carry per/i,rinancc analysis arid tiiiiitig of VLSI processors, don(? in the context of higlt-lewl source Iceriicls. U7e illustrate our rnetliodology in 1Crt71.r of a small (exaniph?) super scalas RlSC J ~ S O C ~ S S I ~ S architecture. A pnrantetrized execution 17ic~cIeI is used fhr piforinance eslimniion. IJsing an iterative optimization techniqire, the parameter set can bc locally optiinizcd around a g i i w design point to genesare tlie ininii?itrtn cycles per. iiwtrttction ( V I ) . W e also iiicludc a ctirsory discussion on linking .rirclt a CI’I estiiizntor io an early jloorplanner jhr A f IPS-driven block layout for the processor chb.
9413783
Optimal Code Generation for Expressions on Super Scalar Machines
26499349
Early performance estimation of super scalar machine models
A novel methodology and software tool for estimating the performance of high-performance machine models with concurrent, pipelined execution modes are presented. Such performance assessment is typically useful at early stages of the design cycle. Critical design decisions made with the aid of early estimators of the kind discussed can be expected to yield near-optimal final designs.<<ETX>>
32890897
A Novel Technique for Efficient Parallel Implementation of a Classical Logic/Fault Simulation Problem
A technique is presented for formulating the logic/fault simulation of VLSI array logic in terms of standard vector and matrix operation primitives that are well supported on all scientific supercomputers, high-end mainframes, and minisupercomputers that provide vector parallel hardware and software. The overall computing environment is assumed to be a scientific/engineering one, with Fortran as the primary coding medium and the hardware biased toward numerically intensive applications. >
121980294
Constructing Plane Spanners of Bounded Degree and Low Weight
Given a set S of n points in the plane, we give an O(n log n)- time algorithm that constructs a plane t-spanner for S, with t ? 10.02, such that the degree of each point of S is bounded from above by 27, and the total edge length is proportional to the weight of a minimum spanning tree of S. These constants are all worst case constants that are artifacts of our proofs. In practice, we believe them to be much smaller. Previously, no algorithms were known for constructing plane t-spanners of bounded degree.
287038
Efficient algorithms for Petersen's matching theorem
Petersen's theorem is a classic result in matching theory from 1891, stating that every 3-regular bridgeless graph has a perfect matching. Our work explores efficient algorithms for finding perfect matchings in such graphs. Previously, the only relevant matching algorithms were for general graphs, and the fastest algorithm ran in O(n3/2) time for 3-regular graphs. We have developed an O(nlog4n)-time algorithm for perfect matching in a 3-regular bridgeless graph. When the graph is also planar, we have as the main result of our paper an optimal O(n)-time algorithm. We present three applications of this result: terrain guarding, adaptive mesh refinement, and quadrangulation.
38150250
Pattern Matching for Permutations
Given a permutation T of 1 to n, and a permutation P of 1 to k, for k ≤ n, we wish to find a k-element subsequence of T whose elements are ordered according to the permutation P. For example, if P is (1,2,..., k), then we wish to find an increasing subsequence of length k in T; this special case can be done in time O(n log log n) [CW]. We prove that the general problem is NP-complete. We give a polynomial time algorithm for the decision problem, and the corresponding counting problem, in the case that P is separable—i.e. contains neither the subpattern (3,1,4,2) nor its reverse, the subpattern (2,4,1,3).
24680353
Facility Location Constrained to a Polygonal Domain
We develop efficient algorithms for locating an obnoxious facility in a simple polygonal region and for locating a desirable facility in a simple polygonal region. Many realistic facility location problems require the facilities to be constrained to lie in a simple polygonal region. Given a set S of m demand points and a simple polygon R of n vertices, we first show how to compute the location of an obnoxious facility constrained to lie in R, in O((m + n) logm + mlog n) time. We then show how to compute the location of a desirable facility constrained to lie in R, also in O((m + n) logm + mlog n) time. Both running times are an improvement over the known algorithms in the literature. Finally, our results generalize to the setting where the facility is constrained to lie within a set of simple polygons as opposed to a single polygon at a slight increase in complexity.
15081913
All Convex Polyhedra can be Clamped with Parallel Jaw Grippers
We study various classes of polyhedra that can be clamped using parallel jaw grippers. We show that all nvertex convex polyhedra can be clamped regardless of the gripper size and present an O(n + k) time algorithm to compute all positions of a polyhedron that allow a valid clamp where k is the number of antipodal pairs of features. We also observe that all terrain polyhedra and orthogonal polyhedra can be clamped and a valid clamp can be found in linear time. Finally we show that all polyhedra can be clamped with some size of gripper.