1804621
The Maximum Number of Edges in a Three-Dimensional Grid-Drawing
An exact formula is given for the maximum number of edges in a graph that admits a three-dimensional grid-drawing contained in a given bounding box. The first universal lower bound on the volume of threedimensional grid-drawings is obtained as a corollary. Our results generalise to the setting of multi-dimensional polyline grid-drawings.
24680353
Facility Location Constrained to a Polygonal Domain
We develop efficient algorithms for locating an obnoxious facility in a simple polygonal region and for locating a desirable facility in a simple polygonal region. Many realistic facility location problems require the facilities to be constrained to lie in a simple polygonal region. Given a set S of m demand points and a simple polygon R of n vertices, we first show how to compute the location of an obnoxious facility constrained to lie in R, in O((m + n) logm + mlog n) time. We then show how to compute the location of a desirable facility constrained to lie in R, also in O((m + n) logm + mlog n) time. Both running times are an improvement over the known algorithms in the literature. Finally, our results generalize to the setting where the facility is constrained to lie within a set of simple polygons as opposed to a single polygon at a slight increase in complexity.
5595756
Bounds for Frequency Estimation of Packet Streams
We consider the problem of approximating the frequency of frequently occurring elements in a stream of length n using only a memory of size m n. This models the process of gathering statistics on Internet packet streaming using a memory that is small relative to the number of classes (e.g. IP addresses) of packets. We show that when some data item a occurs αn times in a stream of length n, the FREQUENT algorithm of Demaine et al. [4], can approximate a’s frequency with an error of no more than (1−α)n/m. We also give a lower-bound of (1−α)n/(m+1) on the accuracy of any deterministic packet counting algorithm, which implies the FREQUENT algorithm is nearly optimal. Finally, we show that randomized algorithms can not be significantly more accurate since there is a lower bound of (1−α)Ω(n/m) on the expected accuracy of any randomized packet counting algorithm.
38367030
Partitions of complete geometric graphs into plane trees
Consider the following question: does every complete geometric graph K"2"n have a partition of its edge set into n plane spanning trees? We approach this problem from three directions. First, we study the case of convex geometric graphs. It is well known that the complete convex graph K"2"n has a partition into n plane spanning trees. We characterise all such partitions. Second, we give a sufficient condition, which generalises the convex case, for a complete geometric graph to have a partition into plane spanning trees. Finally, we consider a relaxation of the problem in which the trees of the partition are not necessarily spanning. We prove that every complete geometric graph K"n can be partitioned into at most n-n/12 plane trees. This is the best known bound even for partitions into plane subgraphs.
45018692
The Grid Placement Problem
We consider the problem of placing a regular grid over a set of points in order to minimize (or maximize) the number of grid cells not containing any points. We give an O(n log n) time and O(n) space algorithm for this problem. As part of this algorithm we develop a new data structure for solving a problem on intervals that is interesting in its own right and may have other applications.
1566102
On simplifying dot maps
Dot maps--drawings of point sets--are a well known cartographic method to visualize density functions over an area. We study the problem of simplifying a given dot map: given a set P of points in the plane, we want to compute a smaller set Q of points whose distribution approximates the distribution of the original set P.We formalize this using the concept of e-approximations, and we give efficient algorithms for computing the approximation error of a set Q of m points with respect to a set P of n points (with m ≤ n) for certain families of ranges, namely unit squares, arbitrary squares, and arbitrary rectangles.If the family R of ranges is the family of all possible unit squares, then we compute the approximation error of Q with respect to P in O(n log n) time. If R is the family of all possible rectangles, we present an O(mn log n) time algorithm. If R is the family of all possible squares, then we present a simple O(m2n + n log n) algorithm and an O(n2 √n log n) time algorithm which is more efficient in the worst case.Finally, we develop heuristics to compute good approximations, and we evaluate our heuristics experimentally.
42931174
Heuristic Rule-Based Program Transformations for Enhanced Vectorization
12711823
Parallel Simulation and Test of VLSI Array Logic
We consider the task of accelerating existing array logic CAD software by running them under parallel processing environments. We restrict our discussion to VLSI programmable logic arrays (PLAs); we present results based on fault simulation/test generation software implemented for PLAs. Due to the regular layout of such array logic, considerable parallelism is expected in any data processing problem involving these modules. However, depending on the underlying machine model, and the adopted programming model, varying levels of speed-up are exhibited. We first consider a typical pipelined, vector mainframe like the IBM 3090 VF. Through a combination of novel problem reformulation strategies, and educated coding guidelines for vector machines, we show how an original scalar program can be efficiently speeded up on such machines. The other machine model considered is that of a shared memory parallel processing system. Our results here are based on experiments run under an experimental multi-processor VM environment (VM/EPEX) which has been set up to predict the possible speed-up on a parallel processor such as RP3. The overall processing environment is assumed to be constrained to a scientific/engineering one, with Fortran as the primary coding medium and the hardware biased toward numerically-intensive applications.
2521753
A circuit level implementation of an adaptive issue queue for power-aware microprocessors
Increasing power dissipation has become a major constraint for future performance gains in the design of microproces sors In this paper we present the circuit design of an issue queue for a superscalar processor that leverages transmis sion gate insertion to provide dynamic low cost con gura bility of size and speed A novel circuit structure dynami cally gathers statistics of issue queue activity over intervals of instruction execution These statistics are then used to change the size of an issue queue organization on the y to improve issue queue energy and performance When applied to a xed full size issue queue structure the result is up to a reduction in energy dissipation The complexity of the additional circuitry to achieve this result is almost neg ligible Furthermore self timed techniques embedded in the adaptive scheme can provide a decrease in cycle time of the CAM array read of the issue queue when we change the adaptive issue queue size from entries largest possible to entries smallest possible in our design
32890897
A Novel Technique for Efficient Parallel Implementation of a Classical Logic/Fault Simulation Problem
A technique is presented for formulating the logic/fault simulation of VLSI array logic in terms of standard vector and matrix operation primitives that are well supported on all scientific supercomputers, high-end mainframes, and minisupercomputers that provide vector parallel hardware and software. The overall computing environment is assumed to be a scientific/engineering one, with Fortran as the primary coding medium and the hardware biased toward numerically intensive applications. >
18129017
Validation of Turandot, a fast processor model for microarchitecture exploration
We describe the results in validating the performance projections from a parameterized trace-driven simulation model of a speculative out-of-order superscalar processor which has been developed with the objective of acting as a microarchitecture exploration tool. Because of its objective, the model-called Turandot-has been designed to deliver much higher simulation speed than what is achieved from detailed (RTL) processor models. We summarize the validation methodology used, and present experimental data gathered in the calibration of one processor organization modeled with Turandot against a detailed reference model. The results indicate that, on the average for SPECint95 sampled traces, Turandot is within 5% of the results reported by the reference model while exhibiting a speed-up factor of about 70.