13829945
Detecting common mode failures in N-version software using weakest precondition analysis
An underlying assumption for N-version programming technique is that independently developed versions would fail in a statistically independent manner However empirical studies have demonstrated that common mode failures can occur even for independently developed versions, and that common mode failures degrade system reliability. In this paper, we demonstrate that the weakest precondition analysis is effective in determining input spaces leading to common mode failures. We applied the weakest precondition to the Launch Interceptor Programs which were used in several other experiments related to the N-version programming technique. We detected 13 out of 18 fault pairs which have been known to cause common mode failure. These faults were due to logical flaws in program design. Although the weakest precondition analysis may be labor-intensive since they are applied manually our results convincingly demonstrate that it is effective for identifying input spaces causing common mode failures and further improving the reliability of N-version software.
9037240
Empirical evaluation of a fuzzy logic-based software quality prediction model
Software inspection, due to its repeated success on industrial applications, has now become an industry standard practice. Recently, researchers began analyzing inspection data to obtain insights on how software processes can be improved. For example, project managers need to identify potentially error-prone software components so that limited project resource may be optimally allocated. This paper proposes an automated and fuzzy logic-based approach to satisfy such a need. Fuzzy logic offers significant advantages over other approaches due to its ability to naturally represent qualitative aspect of inspection data and apply flexible inference rules. In order to empirically evaluate the effectiveness of our approach, we have analyzed published inspection data and the ones collected from two separate inspection experiments which we had conducted. χ2 analysis is applied to statistically demonstrate validity of the proposed quality prediction model.
31388642
Modeling and Testing Agent Systems Based on Statecharts
This paper presents a testing method for an agent system against its specification described with Statecharts. Here, an agent system means an implementation of an agent application. Its testing method generates test sequences from the specification and checks whether the agent system behaves in accordance with the specification by executing the test sequences. For specification-based testing, we have extended Statecharts in order to describe the behavior of an agent system according to the concept of Agent UML. Then, we propose an approach to generating test sequences from the extended Statecharts. Our approach makes effective use of partial order methods for considering representative sequences of equivalent classes divided from all possible sequences. Therefore, we can efficiently manage a large number of possible sequences caused by the agents’ autonomy. As a result, we can reduce the number of test sequences and the number of executions to be tested.
15507852
Testing of concurrent programs based on message sequence charts
Most prior work on specification-based testing of concurrent programs have postulated an equivalence relation between specifications and programs. However the equivalence relation, which requires a specification and a program to encompass the same set of synchronization sequences, is not well-suited for resting concurrent programs against partial and nondeterministic specifications. We present a new specification-based approach to testing concurrent programs against Message Sequence Charts (MSCs) with partial and nondeterministic semantics. New conformance relations, named behavioral conformance and nondeterminacy conformance, are defined and the details of the proposed testing methodology based on the conformance relations are given. The effectiveness of our testing approach is investigated using a telephone switching system example.
12216769
Change impact analysis for a class hierarchy
Modified programs are required to be retested to determine whether changes have been made correctly and to investigate whether those cause any adverse effect on the program behavior. Then, the key issue is the extent of the retesting tasks. To save time and efforts, retesting should be done on only the parts that might be affected by changes. Change impact analysis is the activity which identifies the parts to be retested. Object-oriented paradigm is based on several concepts such as encapsulation, inheritance, polymorphism, and dynamic binding. Although these features contribute to the reusability and extensibility of systems, they produce complex dependencies between classes and attributes, which make it difficult to identify the affected components by changes. We propose an approach for analyzing change impact in a class hierarchy. Our approach is based on the class firewall method, but aims to reduce the retesting effort significantly by taking a member function as a test unit. We deal with the impacts of changes associated with various object-oriented features as well as types of changes which can occur at the level of a data member a member function, a class, and an inheritance relation.
16141068
Improving cohesion metrics for classes by considering dependent instance variables
The existing cohesion metrics for classes do not consider the characteristics of dependent instance variables that are commonly used in a class and, thus, do not properly reflect the cohesiveness of the class. This paper presents an approach for improving the cohesion metrics by considering the characteristics of the dependent instance variables in an object-oriented program.
15346879
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool
The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing instances to be located and signals to be routed in 3-D space. Wire resource prediction is important for fast and accurate interconnection planning in 3-D FPGA. In this paper, we extend the existing analytic model shown in [13] with a new parameter for our 3-D FPGA which has cluster-based logic blocks. The proposed wire resource prediction model is applied to our 3-D FPGA using a Xilinx Virtex2 slice [18] and our 3-D routing architecture. We validate the effectiveness of the extended model by comparing the required number of channel wires predicted by the extended analytic equation with that of the placed and routed results using 3-D placement and routing algorithm designed for our 3-D FPGA for a number of benchmark circuits. The extended 3-D wire resource prediction model predicts the required channel capacity with an average of 11.1% error for 17 large circuits from LGSynth93 and ISPD2001 Verilog benchmarks.
1823005
Functional coverage metric generation from temporal event relation graph
Functional coverage is a technique which can be used for checking the completeness of test vectors. In this paper, automatic generation of temporal events for functional coverage is proposed. The TERG (Temporal Event Relation Graph) is the graph where the nodes represent basic temporal property and the edges represent the time-shift value between two properties. Hierarchical temporal events are generated by traversing TERG such that invalid or irrelevant properties are eliminated. Concurrent edge groups in TERG make it possible to generate more comprehensive temporal properties.
61822837
Resilient Localization for Sensor Networks in Outdoor Environments
The process of computing the physical locations of nodes in a wireless sensor network is known as localization. Self-localization is critical for large-scale sensor networks because manual or assisted localization is often impractical due to time requirements, economic constraints or inherent limitations of deployment scenarios. We have developed a service for reliably localizing wireless sensor networks in environments conducive to ranging errors by using a custom hardware-software solution for acoustic ranging and a family of self-localization algorithms. The ranging solution improves on previous work, extending the practical measurement range threefold (20-30m) while maintaining a distance-invariant median measurement error of about 1% of maximum range (33cm). The localization scheme is based on least squares scaling with soft constraints. Evaluation using ranging results obtained from sensor network field experiments shows that the localization scheme is resilient against large-magnitude ranging errors and sparse range measurements, both of which are common in large-scale outdoor sensor network deployments
8120985
SCATOMi: scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multicasting interconnection architecture
FPGA-based logic emulator with large gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multiFPGA system incorporating several state-of-the-art FPGAs. We propose a circuit partitioning algorithm called SCATOMi(scheduling driven algorithm for TOMi) for multiFPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(time-multiplexed, off-chip, multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Experiments on architecture comparison show that, by adopting the proposed TOMi interconnection architecture along with SCATOMi, the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures including mesh, crossbar and VirtualWire architecture.
7677555
Stock prediction based on financial correlation
In this paper, we propose a neuro-genetic stock prediction system based on financial correlation between companies. A number of input variables are produced from the relatively highly correlated companies. The genetic algorithm selects a set of informative input features among them for a recurrent neural network. It showed notable improvement over not only the buy-and-hold strategy but also the recurrent neural network using only the input variables from the target company.