1817451
Automated path generation for software fault localization
Localizing the cause(s) of an observable error lies at the heart of program debugging. Fault localization often proceeds by comparing the failing program run with some "successful" run (a run which does not demonstrate the error). An issue here is to generate or choose a "suitable" successful run; this task is often left to the programmer. In this paper, we present an efficient technique where the construction of the successful run as well its comparison with the failing run is automated. Our method constructs a successful program run by toggling the outcomes of some conditional branch instances in the failing run. If such a successful run exists, program statements for these branches are returned as bug report. In our experiments with the Siemens benchmark suite, we found that the quality of our bug report compares well with those produced by existing fault localization approaches where the programmer manually provides or chooses a successful run.
12394125
Using compressed bytecode traces for slicing Java programs
Dynamic slicing is a well-known program debugging technique. Given a program P and input I, it finds all program statements which directly/indirectly affect the values of some variables' occurrences when P is executed with I. Dynamic slicing algorithms often proceed by traversing the execution trace of P produced by input I (or a dependence graph which captures control/data flow in the execution trace). Consequently, it is important to develop space efficient representations of the execution trace. In this paper, we use results from data compression to compactly represent bytecode traces of sequential Java programs. The major space savings come from the optimized representation of data (instruction) addresses used by memory reference (branch) bytecodes as operands. We give detailed experimental results on the space efficiency and time overheads for our compact trace representation. We then show how dynamic slicing algorithms can directly traverse our compact traces without resorting to costly decompression. We also develop an extension of dynamic slicing which allows us to explain omission errors (i.e. why some events did not happen during program execution).
42266951
TMO-structured cluster-based real-time management of location data on massive volume of moving items
A major challenge in the field of location based service (LBS) system engineering, is to establish a highly scalable system architecture which can be instantiated in moderate-size configurations handling thousands of moving items as well as in upper-end configurations handling millions of moving items. We are exploring an approach of using a cluster of database server nodes and effecting efficient distributed and parallel computing in both real-time update of location records of moving items and processing of location-related queries. The approach of developing efficient middleware which is layered on a cluster of nodes running commercial off-the-shelf database servers, has been adopted. The middleware design is substantially based on the TMO scheme for real-time distributed object programming and real-time distributed computing system design, which enables low-overhead coordination of distributed computations and highly abstract distributed programming styles.
16865574
On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction
Uses data collected from benchmark circuit simulations to examine the relationship between the tests which detect stuck-at faults and those which detect bridging surrogates. We show that the coefficient of correlation between these tests approaches zero as the stuck-at fault coverage approaches 100%. An enhanced version of the MPG-D model, which is based upon the number of detections of each site in a logic circuit, is shown to be superior to stuck-at fault coverage-based defective part level prediction. We then compare the accuracy of both predictors for an industrial circuit tested using two different test pattern sequences.
207130153
A Software Test and Evaluation Environment Based on Longitudinal Database
To assure the quality of software by running test cases and evaluating the results is one of the difficult parts of the entire software development project. The difficulty usually comes from the lack of appropriate supporting tools and the complexity of the software. In the past ad hoc supporting tools were made for each project and test results were usually not used across projects. This conventional way of test and evaluation (T&E) is time consuming, and the most important decision "When is this software ready to ship?" is left to the engineers depending on their experiences. Our objective is to build a knowledge-based T&E environment such that tests cases, test results, object snapshots and other information are accumulated in a database. These longitudinal data can be automatically tracked and analyzed to provide decision support information. As a result, test results can be reviewed repeatedly and software quality can be assured by analyzing these data from various perspectives.
47136995
Routing for symmetric FPGAs and FPICs
A new class of routing structures with fixed orthogonal wire segments and field programmable switches at the intersections of the wire segments is proposed. In comparison with the conventional two-dimensional field-programmable gate array (FPGA) routing structure, this class of routing structures has the advantage of using a smaller number of active programmable switches. An existing field-programmable interconnect chip (FPIC) routing structure can be included as a special case in our class of routing structures. Using a probabilistic model, we prove that complete routing can be achieved with a high degree of probability in a routing structure of this class in which the number of tracks in each channel approaches the lower bound asymptotically. We present a sequential routing algorithm based on the solution of the single net routing problem. We take into account the delay introduced by the active programmable switches on a routing path and formulate the single net routing problem as a node-weighted Steiner minimum tree (NWSMT) problem in a bipartite graph G. Since our single net routing problem is NP-complete, a polynomial time approximate algorithm is proposed. We prove that our single net routing algorithm produces an optimal solution for some special classes of bipartite graphs. In general, the solution obtained by our algorithm bas a performance bound of min{/spl Delta/(V/Z), |Z|-1}. Experimental results for several industrial circuits show a reduction of up to 41% in the number of active programmable switches when compared with corresponding results for the conventional FPGA routing structure.
39372956
An Inequality on Connected Domination Parameters