17187148
Design of instruction set architectures for support of high-level languages
Conventional instruction sets or directly interpretable languages (DILs) have not been designed with high-level languages (HLLs) in mind. The modern design problem is to derive a space-time efficient DIL for a HLL processing system. In this paper, we present our approach to the problem of designing well-matched, space-time efficient DILs. A systematic, syntax- and semantics-directed DIL design methodology is presented. It calls for an incremental transformation of the source HLL, until a suitable target DIL is obtained. At the heart of the methodology is a canonic set of language transformations. An experimental study, involving several systematically derived DILs is carried out in order to characterize the relative merits and disadvantages of various sequences of transformations. Various space, time and interpretability trade-offs implied by the transformations are studied.
2521753
A circuit level implementation of an adaptive issue queue for power-aware microprocessors
Increasing power dissipation has become a major constraint for future performance gains in the design of microproces sors In this paper we present the circuit design of an issue queue for a superscalar processor that leverages transmis sion gate insertion to provide dynamic low cost con gura bility of size and speed A novel circuit structure dynami cally gathers statistics of issue queue activity over intervals of instruction execution These statistics are then used to change the size of an issue queue organization on the y to improve issue queue energy and performance When applied to a xed full size issue queue structure the result is up to a reduction in energy dissipation The complexity of the additional circuitry to achieve this result is almost neg ligible Furthermore self timed techniques embedded in the adaptive scheme can provide a decrease in cycle time of the CAM array read of the issue queue when we change the adaptive issue queue size from entries largest possible to entries smallest possible in our design
31462412
Performance evaluation and validation of microprocessors
The domain of early performance analysis and microarchitecture definition is limited largely to a onedimensional perspective of net performance: that of cyclesper-instnrction (CPI). Traceor execution-driven cycle-bycycle simulators [l] are the most common toolsets used at this stage. These are often coded in a systems programming language (e.g. C, C++, PWl or Pascal). They are performance-only models in that the register and memory data values and their state changes are not modelled; only the complex pipeline flow and concurrent instruction processing semantics are simulated. The goal here is to assess CPIcentric performance and bottlenecks to aid early definition, not to ensure functional integrity. Such a simulator, which we call a CPI timer; can be implemented to run at speeds greater than 50,000 instructions per second [21. This is achieved in modelling a future processor with the simulator running on a current generation uniprocessor workstation.
18281114
Performance and functional verification of microprocessors
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of the validation problem: (a) verifying the functional integrity of the model and (b) testing the model for timing accuracy at the architectural level. The latter area, that of performance verification, is of increasing importance in the design of server-class processor chips, with one or more high performance cores on a single die. We show how simulation-based test cases can be generated under a unified defect and coverage model to detect both performance and functional bugs. We present and discuss examples of such integrated validation methodologies used in real processor development projects.
26499349
Early performance estimation of super scalar machine models
A novel methodology and software tool for estimating the performance of high-performance machine models with concurrent, pipelined execution modes are presented. Such performance assessment is typically useful at early stages of the design cycle. Critical design decisions made with the aid of early estimators of the kind discussed can be expected to yield near-optimal final designs.<<ETX>>
9413783
Optimal Code Generation for Expressions on Super Scalar Machines
11284721
Characterizing proximity trees
Complete characterizations are given for those trees that can be drawn as either the relative neighborhood graph, relatively closest graph, Gabriel graph, or modified Gabriel graph of a set of points in the plane. The characterizations give rise to linear-time algorithms for determining whether a tree has such a drawing; if such a drawing exists one can be constructed in linear time in the real RAM model. The characterization of Gabriel graphs settles several conjectures of Matula and Sokal [17].
45018692
The Grid Placement Problem
We consider the problem of placing a regular grid over a set of points in order to minimize (or maximize) the number of grid cells not containing any points. We give an O(n log n) time and O(n) space algorithm for this problem. As part of this algorithm we develop a new data structure for solving a problem on intervals that is interesting in its own right and may have other applications.
7768982
Station Layouts in the Presence of Location Constraints
In wireless communication, the signal of a typical broadcast station is transmited from a broadcast center p and reaches objects at a distance, say, R from it. In addition there is a radius r, r < R, such that the signal originating from the center of the station is so strong that human habitation within distance r from the center p should be avoided. Thus every station determines a region which is an "annulus of permissible habitation". We consider the following station layout (SL) problem: Cover a given (say, rectangular) planar region which includes a collection of orthogonal buildings with a minimum number of stations so that every point in the region is within the reach of a station, while at the same time no building is within the dangerous range of a station. We give algorithms for computing such station layouts in both the one-and two-dimensional cases.
28758085
Data Structures for Halfplane Proximity Queries and Incremental Voronoi Diagrams
We consider preprocessing a set S of n points in the plane that are in convex position into a data structure supporting queries of the following form: given a point q and a directed line l in the plane, report the point of S that is farthest from (or, alternatively, nearest to) the point q subject to being to the left of line l. We present two data structures for this problem. The first data structure uses O(n1+e) space and preprocessing time, and answers queries in O(21/e log n) time. The second data structure uses O(n log3n) space and polynomial preprocessing time, and answers queries in O(log n) time. These are the first solutions to the problem with O(log n) query time and o(n2) space. 
 
In the process of developing the second data structure, we develop a new representation of nearest-point and farthest-point Voronoi diagrams of points in convex position. This representation supports insertion of new points in counterclockwise order using only O(log n) amortized pointer changes, subject to supporting O(log n)-time point-location queries, even though every such update may make Θ(n) combinatorial changes to the Voronoi diagram. This data structure is the first demonstration that deterministically and incrementally constructed Voronoi diagrams can be maintained in o(n) pointer changes per operation while keeping O(log n)-time point-location queries.
9135721
Fast approximations for sums of distances, clustering and the Fermat-Weber problem
We describe two data structures that preprocess a set S of n points in Rd (d constant) so that the sum of Euclidean distances of points in S to a query point q can be quickly approximated to within a factor of e. This preprocessing technique has several applications in clustering and facility location. Using it, we derive an O(n log n) time deterministic and O(n) time randomized e-approximation algorithm for the so called Fermat-Weber problem in any fixed dimension.