39390134
Ensuring dependable processor performance: an experience report on pre-silicon performance validation
The focus of today's processor validation methodology is primarily on ensuring functional integrity. Increasingly, however, pre-silicon performance validation is becoming part of the design verification challenge. Identification and elimination of performance deficiencies and bugs in the design prior to tape-out is an important aspect of building robust and dependable hardware. Many performance bugs are caused by latent functional defects in the pre-silicon software model of the machine. Besides, robust performance can be a key determinant of quality of service in applications like Web-serving. The authors review the performance validation methodology that they have developed and experimented with over the past few years. They also present examples and experimental results illustrating the use of this methodology in high end PowerPC processor development projects. The scope of the paper is limited to architectural performance, measured by metrics like instructions per cycle (IPC) or its inverse, CPI.
12711823
Parallel Simulation and Test of VLSI Array Logic
We consider the task of accelerating existing array logic CAD software by running them under parallel processing environments. We restrict our discussion to VLSI programmable logic arrays (PLAs); we present results based on fault simulation/test generation software implemented for PLAs. Due to the regular layout of such array logic, considerable parallelism is expected in any data processing problem involving these modules. However, depending on the underlying machine model, and the adopted programming model, varying levels of speed-up are exhibited. We first consider a typical pipelined, vector mainframe like the IBM 3090 VF. Through a combination of novel problem reformulation strategies, and educated coding guidelines for vector machines, we show how an original scalar program can be efficiently speeded up on such machines. The other machine model considered is that of a shared memory parallel processing system. Our results here are based on experiments run under an experimental multi-processor VM environment (VM/EPEX) which has been set up to predict the possible speed-up on a parallel processor such as RP3. The overall processing environment is assumed to be constrained to a scientific/engineering one, with Fortran as the primary coding medium and the hardware biased toward numerically-intensive applications.
14558888
An Adaptive Issue Queue for Reduced Power at High Performance
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue queue for a superscalar processor that leverages transmission gate insertion to provide dynamic low-cost configurability of size and speed. A novel circuit structure dynamically gathers statistics of issue queue activity over intervals of instruction execution. These statistics are then used to change the size of an issue queue organization on-the-fly to improve issue queue energy and performance. When applied to a fixed, full-size issue queue structure, the result is up to a 70% reduction in energy dissipation. The complexity of the additional circuitry to achieve this result is almost negligible. Furthermore, self-timed techniques embedded in the adaptive scheme can provide a 56% decrease in cycle time of the CAM array read of the issue queue when we change the adaptive issue queue size from 32 entries (largest possible) to 8 entries (smallest possible in our design).
9413783
Optimal Code Generation for Expressions on Super Scalar Machines
32890897
A Novel Technique for Efficient Parallel Implementation of a Classical Logic/Fault Simulation Problem
A technique is presented for formulating the logic/fault simulation of VLSI array logic in terms of standard vector and matrix operation primitives that are well supported on all scientific supercomputers, high-end mainframes, and minisupercomputers that provide vector parallel hardware and software. The overall computing environment is assumed to be a scientific/engineering one, with Fortran as the primary coding medium and the hardware biased toward numerically intensive applications. >
31462412
Performance evaluation and validation of microprocessors
The domain of early performance analysis and microarchitecture definition is limited largely to a onedimensional perspective of net performance: that of cyclesper-instnrction (CPI). Traceor execution-driven cycle-bycycle simulators [l] are the most common toolsets used at this stage. These are often coded in a systems programming language (e.g. C, C++, PWl or Pascal). They are performance-only models in that the register and memory data values and their state changes are not modelled; only the complex pipeline flow and concurrent instruction processing semantics are simulated. The goal here is to assess CPIcentric performance and bottlenecks to aid early definition, not to ensure functional integrity. Such a simulator, which we call a CPI timer; can be implemented to run at speeds greater than 50,000 instructions per second [21. This is achieved in modelling a future processor with the simulator running on a current generation uniprocessor workstation.
15273479
Experimental results on quadrangulations of sets of fixed points
We consider the problem of obtaining "nice" quadrangulations of planar sets of points. For many applications "nice" means that the quadrilaterals obtained are convex if possible and as "fat" or squarish as possible. For a given set of points a quadrangulation, if it exists, may not admit all its quadrilaterals to be convex. In such cases we desire that the quadrangulations have as many convex quadrangles as possible. Solving this problem optimally is not practical. Therefore we propose and experimentally investigate a heuristic approach to solve this problem by converting "nice" triangulations to the desired quadrangulations with the aid of maximum matchings computed on the dual graph of the triangulations. We report experiments on several versions of this approach and provide theoretical justification for the good results obtained with one of these methods. The results of our experiments are particularly relevant for those applications in scattered data interpolation which require quadrangulations that should stay faithful to the original data.
2488122
Detection of text-line orientation
5059195
Competitive Online Routing in Geometric Graphs
We consider online routing algorithms for finding paths between the vertices of plane graphs. Although it has been shown in Bose et al. (Internat. J. Comput. Geom. 12(4) (2002) 283) that there exists no competitive routing scheme that works on all triangulations, we show that there exists a simple online O(1)-memory c-competitive routing strategy that approximates the shortest path in triangulations possessing the diamond property, i.e., the total distance travelled by the algorithm to route a message between two vertices is at most a constant c times the shortest path. Our results imply a competitive routing strategy for certain classical triangulations such as the Delaunay, greedy, or minimum-weight triangulation, since they all possess the diamond property. We then generalize our results to show that the O(1)-memory c-competitive routing strategy works for all plane graphs possessing both the diamond property and the good convex polygon property.
27926826
Optimizing Constrained Offset and Scaled Polygonal Annuli
Aicholzer et al. recently presented a new geometric construct called the straight skeleton of a simple polygon and gave several combinatorial bounds for it. Independently, the current authors defined in companion papers a distance function based on the same offsetting function for convex polygons. In particular, we explored the nearest- and furthest-neighbor Voronoi diagrams of this function and presented algorithms for constructing them. In this paper we give solutions to some constrained annulus placement problems for offset polygons. The goal is to find the smallest annulus region of a polygon containing a set of points. We fix the inner (resp., outer) polygon of the annulus and minimize the annulus region by minimizing the outer offset (resp., maximizing the inner offset). We also solve a a special case of the first problem: finding the smallest translated offset of a polygon containing an entire point set. We extend our results for the standard polygon scaling function as well.
2329490
Asymmetric Communication Protocols via Hotlink
 Assignments
Abstract
We exhibit a relationship between the asymmetric communication problem
of Adler and Maggs and the hotlink assignment problem of Bose
et al. By generalizing previous results on the hotlink problem
and then exploiting this relationship we present a new asymmetric
communication protocol with different performance bounds than previous
protocols.

