44925839
MHPS-Driven Early Design and Analysis of VLSI CPU Chips
JVe present (1 noid appsoaclz to carry per/i,rinancc analysis arid tiiiiitig of VLSI processors, don(? in the context of higlt-lewl source Iceriicls. U7e illustrate our rnetliodology in 1Crt71.r of a small (exaniph?) super scalas RlSC J ~ S O C ~ S S I ~ S architecture. A pnrantetrized execution 17ic~cIeI is used fhr piforinance eslimniion. IJsing an iterative optimization techniqire, the parameter set can bc locally optiinizcd around a g i i w design point to genesare tlie ininii?itrtn cycles per. iiwtrttction ( V I ) . W e also iiicludc a ctirsory discussion on linking .rirclt a CI’I estiiizntor io an early jloorplanner jhr A f IPS-driven block layout for the processor chb.
39390134
Ensuring dependable processor performance: an experience report on pre-silicon performance validation
The focus of today's processor validation methodology is primarily on ensuring functional integrity. Increasingly, however, pre-silicon performance validation is becoming part of the design verification challenge. Identification and elimination of performance deficiencies and bugs in the design prior to tape-out is an important aspect of building robust and dependable hardware. Many performance bugs are caused by latent functional defects in the pre-silicon software model of the machine. Besides, robust performance can be a key determinant of quality of service in applications like Web-serving. The authors review the performance validation methodology that they have developed and experimented with over the past few years. They also present examples and experimental results illustrating the use of this methodology in high end PowerPC processor development projects. The scope of the paper is limited to architectural performance, measured by metrics like instructions per cycle (IPC) or its inverse, CPI.
26499349
Early performance estimation of super scalar machine models
A novel methodology and software tool for estimating the performance of high-performance machine models with concurrent, pipelined execution modes are presented. Such performance assessment is typically useful at early stages of the design cycle. Critical design decisions made with the aid of early estimators of the kind discussed can be expected to yield near-optimal final designs.<<ETX>>
9029444
Workload-driven floorplanning for MIPS optimization
An approach to early floorplanning in which optimization of a CPU chip floorplan is done in the context of a program benchmark (workload) is presented. The methodology integrates workload-driven cycles-per-instruction estimation into the traditional cycle-time evaluation process implied by an (early) floorplanning tool. This effectively adds an extra dimension to the floorplanning optimization cost function and search space, allowing superior MIPS-tuning of the VLSI chip.<<ETX>>
18129017
Validation of Turandot, a fast processor model for microarchitecture exploration
We describe the results in validating the performance projections from a parameterized trace-driven simulation model of a speculative out-of-order superscalar processor which has been developed with the objective of acting as a microarchitecture exploration tool. Because of its objective, the model-called Turandot-has been designed to deliver much higher simulation speed than what is achieved from detailed (RTL) processor models. We summarize the validation methodology used, and present experimental data gathered in the calibration of one processor organization modeled with Turandot against a detailed reference model. The results indicate that, on the average for SPECint95 sampled traces, Turandot is within 5% of the results reported by the reference model while exhibiting a speed-up factor of about 70.
45287
Early-Stage Definition of LPX: A Low Power Issue-Execute Processor
We present the high-level microarchitecture of LPX: a low-power issue-execute processor prototype that is being designed by a joint industry-academia research team. LPX implements a very small subset of a RISC architecture, with a primary focus on a vector (SIMD) multimedia extension. The objective of this project is to validate some key new ideas in power-aware microarchitecture techniques, supported by recent advances in circuit design and clocking.
10971393
Efficient Algorithms for Guarding or Illuminating the Surface of a Polyhedral Terrain
We present eecient polynomial time algorithms that place bn=2c vertex guards which cover the surface of an n-vertex polyhedral terrain, and similarly, bn=3c edge guards which cover the surface of an n-vertex polyhedral terrain. The time complexity of both algorithms, dominated by the cost of nding a maximum matching in a graph, is O(n 3=2).
122008563
Optimal Algorithms to Embed Trees in a Point Set
319438
Approximating geometric bottleneck shortest paths
In a geometric bottleneck shortest path problem, we are given a set S of n points in the plane, and want to answer queries of the following type: given two points p and q of S and a real number L, compute (or approximate) a shortest path between p and q in the subgraph of the complete graph on S consisting of all edges whose lengths are less than or equal to L. We present efficient algorithms for answering several query problems of this type. Our solutions are based on Euclidean minimum spanning trees, spanners, and the Delaunay triangulation. A result of independent interest is the following. For any two points p and q of S, there is a path between p and q in the Delaunay triangulation, whose length is less than or equal to 2π/(3 cos(π/6)) times the Euclidean distance |pq| between p and q, and all of whose edges have length at most |pq|.
100844
Computing constrained minimum-width annuli of point sets
We study the problem of determining whether a manufactured disk of certain radius r is within tolerance. More precisely, we present algorithms that, given a set of n probe points on the surface of the manufactured object, compute the thinnest annulus whose outer (or inner, or median) radius is r and that contains all the probe points. Our algorithms run in O(nlogn) time.
15872429
Characterizing and efficiently computing quadrangulations of planar point sets
Abstract Given a set S of n points in the plane, a quadrangulation of S is a planar subdivision whose vertices are the points of S, whose outer face is the convex hull of S, and every face of the subdivision (except possibly the outer face) is a quadrilateral. We show that S admits a quadrangulation if and only if S does not have an odd number of extreme points. If S admits a quadrangulation, we present an algorithm that computes a quadrangulation of S in O(nlogn) time even in the presence of collinear points. If S does not admit a quadrangulation, then our algorithm can quadrangulate S with the addition of one extra point, which is optimal. We also provide an Ω(n log n) time lower bound for the problem. Our results imply that a k-angulation of a set of points can be achieved with the addition of at most k − 3 extra points within the same time bound. Finally, we present an experimental comparison between three quadrangulation algorithms which shows that the Spiraling Rotating Calipers (SRC) algorithm produces quadrangulations with the greatest number of convex quadrilaterals as well as those with the smallest difference between the average minimum and maximum angle over all quadrangles.