18129017
Validation of Turandot, a fast processor model for microarchitecture exploration
We describe the results in validating the performance projections from a parameterized trace-driven simulation model of a speculative out-of-order superscalar processor which has been developed with the objective of acting as a microarchitecture exploration tool. Because of its objective, the model-called Turandot-has been designed to deliver much higher simulation speed than what is achieved from detailed (RTL) processor models. We summarize the validation methodology used, and present experimental data gathered in the calibration of one processor organization modeled with Turandot against a detailed reference model. The results indicate that, on the average for SPECint95 sampled traces, Turandot is within 5% of the results reported by the reference model while exhibiting a speed-up factor of about 70.
18281114
Performance and functional verification of microprocessors
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of the validation problem: (a) verifying the functional integrity of the model and (b) testing the model for timing accuracy at the architectural level. The latter area, that of performance verification, is of increasing importance in the design of server-class processor chips, with one or more high performance cores on a single die. We show how simulation-based test cases can be generated under a unified defect and coverage model to detect both performance and functional bugs. We present and discuss examples of such integrated validation methodologies used in real processor development projects.
9413783
Optimal Code Generation for Expressions on Super Scalar Machines
2521753
A circuit level implementation of an adaptive issue queue for power-aware microprocessors
Increasing power dissipation has become a major constraint for future performance gains in the design of microproces sors In this paper we present the circuit design of an issue queue for a superscalar processor that leverages transmis sion gate insertion to provide dynamic low cost con gura bility of size and speed A novel circuit structure dynami cally gathers statistics of issue queue activity over intervals of instruction execution These statistics are then used to change the size of an issue queue organization on the y to improve issue queue energy and performance When applied to a xed full size issue queue structure the result is up to a reduction in energy dissipation The complexity of the additional circuitry to achieve this result is almost neg ligible Furthermore self timed techniques embedded in the adaptive scheme can provide a decrease in cycle time of the CAM array read of the issue queue when we change the adaptive issue queue size from entries largest possible to entries smallest possible in our design
26499349
Early performance estimation of super scalar machine models
A novel methodology and software tool for estimating the performance of high-performance machine models with concurrent, pipelined execution modes are presented. Such performance assessment is typically useful at early stages of the design cycle. Critical design decisions made with the aid of early estimators of the kind discussed can be expected to yield near-optimal final designs.<<ETX>>
31462412
Performance evaluation and validation of microprocessors
The domain of early performance analysis and microarchitecture definition is limited largely to a onedimensional perspective of net performance: that of cyclesper-instnrction (CPI). Traceor execution-driven cycle-bycycle simulators [l] are the most common toolsets used at this stage. These are often coded in a systems programming language (e.g. C, C++, PWl or Pascal). They are performance-only models in that the register and memory data values and their state changes are not modelled; only the complex pipeline flow and concurrent instruction processing semantics are simulated. The goal here is to assess CPIcentric performance and bottlenecks to aid early definition, not to ensure functional integrity. Such a simulator, which we call a CPI timer; can be implemented to run at speeds greater than 50,000 instructions per second [21. This is achieved in modelling a future processor with the simulator running on a current generation uniprocessor workstation.
13164102
Worst-case-optimal algorithms for guarding planar graphs and polyhedral surfaces
We present an optimal Θ(n)-time algorithm for the selection of a subset of the vertices of an n-vertex plane graph G so that each of the faces of G is covered by (i.e., incident with) one or more of the selected vertices. At most ⌊n/2⌋ vertices are selected, matching the worst-case requirement. Analogous results for edge-covers are developed for two different notions of "coverage". In particular, our linear-time algorithm selects at most n - 2 edges to strongly cover G, at most ⌊n/3⌋ diagonals to cover G, and in the case where G has no quadrilateral faces, at most ⌊n/3⌋ edges to cover G. All these bounds are optimal in the worst-case. Most of our results flow from the study of a relaxation of the familiar notion of a 2-coloring of a plane graph which we call a face-respecting 2-coloring that permits monochromatic edges as long as there are no monochromatic faces. Our algorithms apply directly to the location of guards, utilities or illumination sources on the vertices or edges of polyhedral terrains, polyhedral surfaces, or planar subdivisions.
41075596
Recovering lines with fixed linear probes
• A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers.
15273479
Experimental results on quadrangulations of sets of fixed points
We consider the problem of obtaining "nice" quadrangulations of planar sets of points. For many applications "nice" means that the quadrilaterals obtained are convex if possible and as "fat" or squarish as possible. For a given set of points a quadrangulation, if it exists, may not admit all its quadrilaterals to be convex. In such cases we desire that the quadrangulations have as many convex quadrangles as possible. Solving this problem optimally is not practical. Therefore we propose and experimentally investigate a heuristic approach to solve this problem by converting "nice" triangulations to the desired quadrangulations with the aid of maximum matchings computed on the dual graph of the triangulations. We report experiments on several versions of this approach and provide theoretical justification for the good results obtained with one of these methods. The results of our experiments are particularly relevant for those applications in scattered data interpolation which require quadrangulations that should stay faithful to the original data.
19459070
Approximating Geometric Bottleneck Shortest Paths
In a geometric bottleneck shortest path problem, we are given a set S of n points in the plane, and want to answer queries of the following type: Given two points p and q of S and a real number L, compute (or approximate) a shortest path in the subgraph of the complete graph on S consisting of all edges whose length is less than or equal to L. We present efficient algorithms for answering several query problems of this type. Our solutions are based on minimum spanning trees, spanners, the Delaunay triangulation, and planar separators.
20313387
Algorithms for Packing Two Circles in a Convex Polygon
We consider algorithms for packing two circles in a given n-vertex convex polygon. The first algorithm outputs a pair of equal non-overlapping circles of maximum radius and has running time O(n). The second algorithm outputs a pair of non-overlapping circles whose sum of radii is maximum and has running time O(n 2).