2930338
Testing for interconnect crosstalk defects using on-chip embedded processor cores
Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during production testing. External testing for crosstalk is expensive due to the need for high-speed testers. Built-in self-test, while eliminating the need for a high-speed tester, may lead to excessive test overhead as well as overly aggressive testing. To address this problem, we propose a new software-based self-test methodology for system-on-chip (SoC) devices based on embedded processors. It enables an on-chip embedded processor core to test for crosstalk in system-level interconnects by executing a self-test program in the normal operational mode of the SoC. We have demonstrated the feasibility of this method by applying it to test the interconnects of a processor-memory system. The defect coverage was evaluated using a system-level crosstalk defect simulation method.
15986742
DEFUSE: a deterministic functional self-test methodology for processors
At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-test. However, due to their reliance on random patterns, current logic BIST techniques are not able to deal with large designs without adding high test overhead. In this paper, we propose a functional self-test technique that is deterministic in nature. By targeting the structural test need of manageable components with the aid of processor functionality, this technique has the fault coverage advantage of deterministic structural testing and the at-speed advantage of functional testing. Most importantly, by relieving testers from test application, it enables at-speed testing of GHz processors with low speed testers. We have demonstrated our methodology on a simple accumulator-based microprocessor. The results show that with the proposed technique, we are able to apply high-quality at-speed tests with no test overhead.
14133000
Software-based diagnosis for processors
Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed test of high-speed microprocessors using low-cost testers. We explore the fault diagnosis capability of SBST, in which functional information can be used to guide and facilitate the generation of diagnostic tests. By using a large number of carefully constructed diagnostic test programs, the fault universe can be divided into fine-grained partitions, each corresponding to a unique pass/fail pattern. We evaluate the quality of diagnosis by constructing diagnostic-tree-based fault dictionaries. We demonstrate the feasibility of the proposed method by applying it to a processor example. Experimental results show its potential as an effective method for diagnosing larger processors.
12599093
A scalable software-based self-test methodology for programmable processors
Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) that contain them. While early work on SBST has proposed several promising ideas, many challenges remain in applying SBST to realistic embedded processors. We propose a systematic scalable methodology for SBST that automates several key steps. The proposed methodology consists of (i) identifying test program templates that are well suited for test delivery to each module within the processor, (ii) extracting input/output mapping functions that capture the controllability/observability constraints imposed by a test program template for a specific module-under-test, (iii) generating module-level tests by representing the input/output mapping functions as virtual constraint circuits, and (iv) automatic synthesis of a software self-test program from the module-level tests. We propose novel RTL simulation-based techniques for template ranking and selection, and techniques based on the theory of statistical regression for extraction of input/output mapping functions. An important advantage of the proposed techniques is their scalability, which is necessitated by the significant and growing complexity of embedded processors.To demonstrate the utility of the proposed methodology, we have applied it to a commercial state-of-the-art embedded processor (Xtensa™ from Tensilica Inc.). We believe this is the first practical demonstration of software-based self-test on a processor of such complexity. Experimental results demonstrate that software self-test programs generated using the proposed methodology are able to detect most (95.2%) of the functionally testable faults, and achieve significant simultaneous improvements in fault coverage and test length compared with conventional functional test.
8887048
Using a Soft Core in a SoC Design: Experiences with picoJava
Through our experience in synthesis, validation, test, and integration of the picoJava processor core in a system-on-chip (SoC) design we point out the challenges faced and issues to address in efficient reuse of a soft core.
5124709
Embedded hardware and software self-testing methodologies for processor cores
At-speed testing of GHz processors using external testers may not be technically and economically feasible. Hence, there is an emerging need for low-cost, high-quality self-test methodologies, which can be used by processors to test themselves at-speed. Currently, Built-In Self-Test (BIST) is the primary self-test methodology available and is widely used for testing embedded memory cores. In this paper, we report our experiences in applying a commercial BIST methodology to two processor cores and analyze the problems associated with the current hardware-based BIST methodologies. We propose a new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests. The software tester consists of programs for test generation and test application. Prior to the test, structural tests are prepared for processor components in the form of self-test signatures. During the process of self-test, the test generation program expands the self-test signatures into test sets, and the test application program applies the tests to the components-under-test at the speed of the processor. Application of the novel software-based self-test method demonstrates its significant cost/fault coverage benefits and its ability to apply at-speed test while alleviating the need for high-speed testers.
10243856
A new LDA-based face recognition system which can solve the small sample size problem
A new LDA-based face recognition system is presented in this paper. Linear discriminant analysis (LDA) is one of the most popular linear projection techniques for feature extraction. The major drawback of applying LDA is that it may encounter the small sample size problem. In this paper, we propose a new LDA-based technique which can solve the small sample size problem. We also prove that the most expressive vectors derived in the null space of the within-class scatter matrix using principal component analysis (PCA) are equal to the optimal discriminant vectors derived in the original space using LDA. The experimental results show that the new LDA process improves the performance of a face recognition system signi"cantly. ( 2000 Pattern Recognition Society. Published by Elsevier Science Ltd. All rights reserved.
4781375
SERFing the web: The Re-Web approach for web re-structuring
In our emerging digital paper-less society, massive amount of information is being maintained in on-line repositories and diverse web site representations of this information must be served over the Internet to different user groups. E-commerce and digital libraries are two representative sample applications with such needs. In this paper we present a database-centric approach called Re-Web that addresses this need for flexible web site generation, re-structuring, and maintenance. Re-Web is based on two key ideas. First, we exploit the web site structure by associating web semantics (XML equivalents) with the modeling constructs of the ODMG object model to aid the web site generation process. By capturing the logical structure of web views within the OODB system, we can efficiently maintain the web views using standard database techniques. Secondly, to ease the process of specification and construction of multiple customized web view sites, we also propose the notion of generic web view transformations that are encapsulated into re-usable templates. Thus desired new web view sites can be generated simply by applying the corresponding transformations on the underlying database to produce web view classes and then by applying the web semantics on the newly built view classes. The Re-Web system has been implemented using PSE by Object Design Inc. as object repository, ODMG as object model, OQL as transformation language, SERF as OODB evolution facility and IBM XML parser and LotusXSL processor to aid the web site generation. A case study using Re-Web is also presented to illustrate the working of the system. To the best of our knowledge, Re-Web is the first web site management system focusing on the issue of re-usable view generation templates at the content and not at the presentation style level of abstraction.
206929170
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system software designers: how to best exploit the parallelism potential due to such multi-core architectures? In this paper, we report an in-depth study on such challenges based on our experience of optimizing the fast Fourier transform (FFT) on the IBM Cyclops-64 chip architecture - a large-scale multi-core chip architecture consisting 160 thread units, associated memory banks and an interconnection network that connect them together in a shared memory organization. We demonstrate how multi-core architectures like the C64 could be used to achieve a high performance implementation of FFT both in 1D and 2D cases. We analyze the optimization challenges and opportunities including problem decomposition, load balancing, work distribution, and data-reuse, together with the exploiting of the C64 architecture features such as the multi-level of memory hierarchy and large register files. Furthermore, the experience learned during the hand-tuned optimization process have provided valuable guidance in our compiler optimization design and implementation. The main contributions of this paper include: 1) our study demonstrates that successful optimization for C64-like large-scale multi-core architectures requires a careful analysis that can identify certain domain-specific features of a target application (e.g. FFT) and match them well with some key multi-core architecture features; 2) our optimization, assisted with hand-tuned process, provided quantitative evidence on the importance of each optimization identified in 1); 3) automatic optimization by our compiler, the design and implementation of which is guided by the feedbacks from 1) and 2), shows excellent results that are often comparable to the results derived from our time-consuming hand-tuned code.
42859429
Hardware verification using symbolic state transition graphs
A new approach for hardware verification using symbolic state transition graphs (implemented in BDDs) is presented. We propose a novel idea, a symbolic state transition graph (STG), which can represent finite state machines FSM in terms of the relations between symbolic input variables, state variables, and output results, rather than the exact input-output bit patterns. Compared to conventional STG methods, the symbolic STG is more concise, higher-level, has fewer states and is easier to specify. Based on the transition relation method and an event-driven scheduling technique to compute the symbolic states, we propose two algorithms to verify the circuit implementation with respect to its symbolic STGs. The algorithms can be used to find out a necessary condition for the implementation to satisfy the specification, which can be used for the allocation of design errors.<<ETX>>
43431226
Wavelet-based optical flow estimation
A new algorithm for accurate optical flow (OF) estimation using discrete wavelet approximation is proposed. The computation of OF depends on minimizing the image and smoothness constraints. The proposed method takes advantages of the nature of wavelet theory, which can efficiently and accurately approximate any function. OF vectors and image functions are represented by means of linear combinations of scaling basis functions. Based on such wavelet-based approximation, the leading coefficients of these basis functions carry global information about the approximated functions. The proposed method can successfully convert the problem of minimizing a constraint function into that of solving a linear system of a quadratic and convex function of scaling coefficients. Once all the corresponding coefficients are determined, the flow vectors can be obtained accordingly. Experiments have been conducted on both synthetic and real image sequences. In terms of accuracy, the results show that our approach outperforms the existing methods which adopted the same objective function as ours.