15507852
Testing of concurrent programs based on message sequence charts
Most prior work on specification-based testing of concurrent programs have postulated an equivalence relation between specifications and programs. However the equivalence relation, which requires a specification and a program to encompass the same set of synchronization sequences, is not well-suited for resting concurrent programs against partial and nondeterministic specifications. We present a new specification-based approach to testing concurrent programs against Message Sequence Charts (MSCs) with partial and nondeterministic semantics. New conformance relations, named behavioral conformance and nondeterminacy conformance, are defined and the details of the proposed testing methodology based on the conformance relations are given. The effectiveness of our testing approach is investigated using a telephone switching system example.
42278030
Hybrid knowledge-based architecture for building an intelligent nondestructive signal inspection system
The paper deals with the methods of implementing an intelligent inspection system for monitoring the health of any device or material using a nondestructive signal. A hybrid knowledge representation and processing architecture is proposed as a solution to problems encountered in the processes of the nondestructive inspection. In the proposed system, to modularize knowledge elicitation and to make knowledge processing reliable, the task of inspection is delegated to two subsystems each of which has a proper knowledge processing scheme to match the properties of its own task. The front-end subsystem which detects the signal patterns (events) for any harmful flaw is built by integrating a fuzzified syntactic pattern recognition concept and a neural network concept. The back-end subsystem which evaluates the characteristics of the events is based upon object-oriented rule base system concepts. The methods of integrating the approaches in the proposed architecture are also proposed in the paper. The proposed architecture is verified by developing and evaluating a prototype which automatically interprets eddy current Lissajous signals to inspect the state of tubes used in nuclear power plants.
8261294
Inter-class mutation operators for Java
The effectiveness of mutation testing depends heavily on the types of faults that the mutation operators are designed to represent. Therefore, the quality of the mutation operators is key to mutation testing. Mutation testing has traditionally been applied to procedural-based languages, and mutation operators have been developed to support most of their language features. Object-oriented programming languages contain new language features, most notably inheritance, polymorphism, and dynamic binding. Not surprisingly; these language features allow new kinds of faults, some of which are not modeled by traditional mutation operators. Although mutation operators for OO languages have previously been suggested, our work in OO faults indicate that the previous operators are insufficient to test these OO language features, particularly at the class testing level. This paper introduces a new set of class mutation operators for the OO language Java. These operators are based on specific OO faults and can be used to detect faults involving inheritance, polymorphism, and dynamic binding, thus are useful for inter-class testing. An initial Java mutation tool has recently been completed, and a more powerful version is currently under construction.
18707877
An efficient debugging method for message-based parallel programs using static analysis information
Guaranteeing reproducibility and minimizing probe effects are major issues in the parallel program debugging. The paper suggests a new debugging method, called the Detect and Reproduce method, for message-based parallel programs. The proposed method is designed to guarantee the reproducible behaviors of a target program and to alleviate probe effects by reducing both the number of the probes to be inserted into a program and the amount of information gathered by those probes. The proposed method achieves such effects by employing a static analysis technique to detect nondeterminacy. By detecting nondeterminacy before running the program, only a small number of probes are required to assure reproducibility. To analyze message-based programs statically, an MHB (minimal happened before) model is designed to catch the synchronization structures and algorithms have been developed to locate nondeterminacy based on the MHB model. Utilizing the analysis results, probes are inserted only into the places where nondeterminacy is likely to take place.
16141068
Improving cohesion metrics for classes by considering dependent instance variables
The existing cohesion metrics for classes do not consider the characteristics of dependent instance variables that are commonly used in a class and, thus, do not properly reflect the cohesiveness of the class. This paper presents an approach for improving the cohesion metrics by considering the characteristics of the dependent instance variables in an object-oriented program.
31388642
Modeling and Testing Agent Systems Based on Statecharts
This paper presents a testing method for an agent system against its specification described with Statecharts. Here, an agent system means an implementation of an agent application. Its testing method generates test sequences from the specification and checks whether the agent system behaves in accordance with the specification by executing the test sequences. For specification-based testing, we have extended Statecharts in order to describe the behavior of an agent system according to the concept of Agent UML. Then, we propose an approach to generating test sequences from the extended Statecharts. Our approach makes effective use of partial order methods for considering representative sequences of equivalent classes divided from all possible sequences. Therefore, we can efficiently manage a large number of possible sequences caused by the agents’ autonomy. As a result, we can reduce the number of test sequences and the number of executions to be tested.
5951770
MetaCore: an application specific DSP development system
This paper describes the MetaCore system which is an ASIP (Application-Specific Instruction set Processor) development system targeted for DSP applications. The goal of MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost and design turnaround time.
MetaCore system consists of two major design stages: design exploration and design generation. In the design exploration stage, MetaCore system accepts a set of benchmark programs and a formal specification of ISA (Instruction Set Architecture), and estimates the hardware cost and performance for each hardware configuration being explored. Once a hardware configuration is chosen, the system helps generate a VLSI processor design in the form of HDL along with the application program development tools such as C compiler, assembler and instruction set simulator.
1673424
Pyramid texture compression and decompression using interpolative vector quantization
Texture mapping is a common technique used to increase the visual quality of 3D scenes. As texture mapping requires a large amount of memory to deal with large textures generally required in the current visual systems, we propose an algorithm for compressing a pyramid texture used for mipmapping. Vector quantization is used to compress all levels of the pyramid texture to one representative value databook, one residual codebook and one index map. The proposed compression scheme uses interpolative texel difference vector quantization that compresses the difference between the interpolated surfaces generated by the representative value and the correct uncompressed texels of the texture at each level. The compressed pyramid texture can be accessed randomly and decompressed without loss of visual quality. We also propose a hardware architecture that performs the trilinear filtering with the compressed pyramid texture.
2254400
iLTLchecker: a probabilistic model checker for multiple DTMCs
iLTL is a probabilistic temporal logic that can specify properties of multiple discrete time Markov chains (DTMCs). In this paper, we describe two related tools: MarkovEstimator a tool to estimate a Markov transition matrix, and iLTLChecker, a tool to model check iLTL properties of DTMCs. These tools work together to verify iLTL properties of DTMCs.
7677555
Stock prediction based on financial correlation
In this paper, we propose a neuro-genetic stock prediction system based on financial correlation between companies. A number of input variables are produced from the relatively highly correlated companies. The genetic algorithm selects a set of informative input features among them for a recurrent neural network. It showed notable improvement over not only the buy-and-hold strategy but also the recurrent neural network using only the input variables from the target company.
14181871
Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus
Simulation is the most viable solution for the functional verification of system-on-chip (SoC). The acceleration of simulation with multi-field programmable gate array (multi-FPGA) emulator is a promising method to comply with the increasing complexity and large gate capacity of SoC. Time multiplexing of interconnection wires is the inevitable solution to solve the pin limitation problem that limits the gate utilization of FPGAs and speed of multi-FPGA simulation accelerators. The most time-consuming factor of multi-FPGA simulation acceleration is the synchronization time between a software simulator and a multi-FPGA system and the inter-FPGA synchronization time. This paper proposes a performance-driven signal synchronization mechanism for a simulation accelerator with multiple FPGAs using time-multiplexed interconnection. The event-based signal synchronization optimizes the synchronization time between a software simulator and the multi-FPGA system as well as the synchronization time among FPGAs. The synchronization time among FPGAs is optimized by circuit partitioning considering the signal probability, net dependency reduction, and efficient net clustering to reduce addressing overhead. The synchronization time between the software simulator and the multi-FPGA system is also optimized by exploiting the event probability of primary nets. Experiments show that the synchronization time is reduced to 6.2-9.8% of traditional mechanisms.