19972547
A high SFDR direct digital synthesizer with frequency error free output
In this paper, an error-compensation method is proposed to achieve high spurious free dynamic range (SFDR) in direct digital synthesizers (DDS) design. This method allows very small ROM storage, while leaving the resultant errors corrected by the error-compensation circuits. An extended phase accumulator (EPA) is also adopted to provide arbitrary output frequency, thus can achieve frequency error free output. Experimental results show that the DDS using only 256 bits of ROM can achieve 104 dBc SFDR for output signal at 20 MHz with a clock frequency of 100 MHz. The effect of EPA is also demonstrated in the design.
15937167
High-throughput layered decoder implementation for quasi-cyclic LDPC codes
This paper presents a high-throughput decoder design for the Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. Two new techniques are proposed, including parallel layered decoding architecture (PLDA) and critical path splitting. PLDA enables parallel processing for all layers by establishing dedicated message passing paths among them. The decoder avoids crossbar-based large interconnect network. Critical path splitting technique is based on articulate adjustment of the starting point of each layer to maximize the time intervals between adjacent layers, such that the critical path delay can be split into pipeline stages. Furthermore, min-sum and loosely coupled algorithms are employed for area efficiency. As a case study, a rate-1/2 2304-bit irregular LDPC decoder is implemented using ASIC design in 90 nm CMOS process. The decoder can achieve the maximum decoding throughput of 2.2 Gbps at 10 iterations. The operating frequency is 950 MHz after synthesis and the chip area is 2.9 mm2.
4025720
Pricing options under jump diffusion processes with fitted finite volume method
This paper develops a numerical method for a partial integro-differential equation and a partial integro-differential complementarity problem arising from European and American options valuations respectively when the underlying assets are driven by a jump diffusion process. The method is based on a fitted finite volume scheme for the spatial discretization and the Crank–Nicolson scheme for the time discretization. The fully discretized system is solved by an iterative method coupled with an FFT for the evaluation of the discretized integral term, while the constraint in the American option model is imposed by adding a penalty term to the original partial integro-differential complementarity problem. We show that the system matrix of the discretized system is an M-matrix and propose an algorithm for solving the discretized system. Numerical experiments are implemented to show the efficiency and robustness of this method.
5848822
Soft decoder architecture of LT codes
Luby transform (LT) codes, as the first class of efficient rateless codes, attract a lot of attention in the coding theory field. However, the VLSI implementation of LT codes is challenging due to its random code construction characteristic as well as the flexible output length. In this paper, we present an applicable architecture of a soft-decision LT decoder with a block length of 1024 bits and 100 iterations. Partly parallel input node processing and output node processing techniques are both adopted to accelerate decoding speed. An efficient router and reverse router are designed to indicate the graphic connectivity between input nodes and output nodes. The parallel architecture is prototyped on the target FPGA device.
1961988
An Area-Efficient LDPC Decoder Architecture and Implementation for CMMB Systems
This paper presents an area-efficient LDPC decoder architecture for the China Multimedia Mobile Broadcasting (CMMB) standard. Several techniques are adopted to reduce memory size, including the min-sum algorithm (MSA), optimal bit-width quantization of the iterative messages and reduced complexity for the interconnect network. The decoder for the rate-1/2 9216-bit code is implemented using the 90nm 1.0V CMOS technology. It achieves the decoding throughput of 48Mbps at 5 iterations when operating at 60MHz and the power dissipation is only 34mW.
13407923
The Application of Two-Dimensional Image Reconstruction for Relics' Preservation and Administration
The purpose of this paper is to build a relics database using for preservation and administration for relics. The paper research on the two-dimensional reconstruction images store in the relics database. The reconstruction images of relics can be used to observe and analyze the antique inside that the eye has no way to distinguish without disruption. This paper have make experiments with six relic samples. By using the industrial computed-tomography (CT) obtain the CT scan data of the six relics samples of different materials and after handling the real data, the experiment and analysis of CT image reconstruction have been carried out. The reconstruction images by SIRT algorithm can clearly indicate the internal structure of the relics. This paper accomplished the comparison of image reconstruction by SIRT algorithm with different iterative relaxation coefficient λ values. This job can provide the CT images data of relics for the relics database. The experiments can provide support for preservation and administration of relics and provide information for teaching and learning activities of cultural studies.
10126460
Mining common topics from multiple asynchronous text streams
Text streams are becoming more and more ubiquitous, in the forms of news feeds, weblog archives and so on, which result in a large volume of data. An effective way to explore the semantic as well as temporal information in text streams is topic mining, which can further facilitate other knowledge discovery procedures. In many applications, we are facing multiple text streams which are related to each other and share common topics. The correlation among these streams can provide more meaningful and comprehensive clues for topic mining than those from each individual stream. However, it is nontrivial to explore the correlation with the existence of asynchronism among multiple streams, i.e. documents from different streams about the same topic may have different timestamps, which remains unsolved in the context of topic mining. In this paper, we formally address this problem and put forward a novel algorithm based on the generative topic model. Our algorithm consists of two alternate steps: the first step extracts common topics from multiple streams based on the adjusted timestamps by the second step; the second step adjusts the timestamps of the documents according to the time distribution of the discovered topics by the first step. We perform these two steps alternately and a monotone convergence of our objective function is guaranteed. The effectiveness and advantage of our approach were justified by extensive empirical studies on two real data sets consisting of six research paper streams and two news article streams, respectively.
32825768
Compilation and Runtime-Optimizations for Software Distributed Shared Memory
We present two novel optimizations for compiling High Performance Fortran (HPF) to page-based software distributed shared memory systems (SDSM). One technique, compiler-managed restricted consistency, uses compiler-derived knowledge to delay the application of memory consistency operations to data that is provably not shared in the current synchronization interval, thus reducing false sharing. The other technique, compiler-managed shared buffers, when combined with the previous optimization, eliminates fragmentation. Together, the two techniques permit compiler-generated code to efficiently apply multi-dimensional computation partitioning and wavefront parallelism to execute efficiently on SDSM systems.
2688754
A method for evaluating upper bound of simultaneous switching gates using circuit partition
This paper presents a method for evaluating an upper bound of simultaneous switching gates in combinational circuits. In this method, the original circuit is partitioned into subcircuits, and the upper bound is approximately computed as the sum of maximum switching gates for all subcircuits. In order to increase the accuracy, we adopted an evaluation function that takes account of both the interconnections among subcircuits and the number of generated subcircuits. Experimental results for ISCAS circuits show that the method efficiently evaluates the upper bounds of switching gates.
4300632
Keyword Extraction Using Support Vector Machine
This paper is concerned with keyword extraction. By keyword extraction, we mean extracting a subset of words/phrases from a document that can describe the ‘meaning' of the document. Keywords are of benefit to many text mining applications. However, a large number of documents do not have keywords and thus it is necessary to assign keywords before enjoying the benefit from it. Several research efforts have been done on keyword extraction. These methods make use of the ‘global context information', which makes the performance of extraction restricted. A thorough and systematic investigation on the issue is thus needed. In this paper, we propose to make use of not only ‘global context information', but also ‘local context information' for extracting keywords from documents. As far as we know, utilizing both ‘global context information' and ‘local context information' in keyword extraction has not been sufficiently investigated previously. Methods for performing the tasks on the basis of Support Vector Machines have also been proposed in this paper. Features in the model have been defined. Experimental results indicate that the proposed SVM based method can significantly outperform the baseline methods for keyword extraction. The proposed method has been applied to document classification, a typical text mining processing. Experimental results show that the accuracy of document classification can be significantly improved by using the keyword extraction method.