16141068
Improving cohesion metrics for classes by considering dependent instance variables
The existing cohesion metrics for classes do not consider the characteristics of dependent instance variables that are commonly used in a class and, thus, do not properly reflect the cohesiveness of the class. This paper presents an approach for improving the cohesion metrics by considering the characteristics of the dependent instance variables in an object-oriented program.
31388642
Modeling and Testing Agent Systems Based on Statecharts
This paper presents a testing method for an agent system against its specification described with Statecharts. Here, an agent system means an implementation of an agent application. Its testing method generates test sequences from the specification and checks whether the agent system behaves in accordance with the specification by executing the test sequences. For specification-based testing, we have extended Statecharts in order to describe the behavior of an agent system according to the concept of Agent UML. Then, we propose an approach to generating test sequences from the extended Statecharts. Our approach makes effective use of partial order methods for considering representative sequences of equivalent classes divided from all possible sequences. Therefore, we can efficiently manage a large number of possible sequences caused by the agents’ autonomy. As a result, we can reduce the number of test sequences and the number of executions to be tested.
1967679
On the concurrent behaviour of SCR specifications
The SCR method models a system using a set of variables and state machines whose behaviour is described by tabular notations. This paper proposes an interleaving semantics for SCR specifications in terms of timed transition systems. The semantics is given by identifying each of the components of a timed transition system from a given SCR specification. The concurrent behaviour of a SCR specification is defined as a set of computations of the resulting timed transition system.
42278030
Hybrid knowledge-based architecture for building an intelligent nondestructive signal inspection system
The paper deals with the methods of implementing an intelligent inspection system for monitoring the health of any device or material using a nondestructive signal. A hybrid knowledge representation and processing architecture is proposed as a solution to problems encountered in the processes of the nondestructive inspection. In the proposed system, to modularize knowledge elicitation and to make knowledge processing reliable, the task of inspection is delegated to two subsystems each of which has a proper knowledge processing scheme to match the properties of its own task. The front-end subsystem which detects the signal patterns (events) for any harmful flaw is built by integrating a fuzzified syntactic pattern recognition concept and a neural network concept. The back-end subsystem which evaluates the characteristics of the events is based upon object-oriented rule base system concepts. The methods of integrating the approaches in the proposed architecture are also proposed in the paper. The proposed architecture is verified by developing and evaluating a prototype which automatically interprets eddy current Lissajous signals to inspect the state of tubes used in nuclear power plants.
18311049
Testing of concurrent programs after specification changes
This paper describes a specification-based regression testing technique that can be applied for revalidating concurrent programs after specification changes. This kind of regression testing technique requires sequencing constraints which specify the precedence relations among synchronization events. In our method, the sequencing constraints are extracted automatically from Message Sequence Charts (MSCs) that are considered to be partial and nondeterministic specifications. We show how to identify the sequencing constraints affected by the modifications of a specification rather than creating new sequencing constraints from scratch to reduce the cost of regression testing. We also describe how to determine whether the affected sequencing constraints are satisfied by the program being tested.
8261294
Inter-class mutation operators for Java
The effectiveness of mutation testing depends heavily on the types of faults that the mutation operators are designed to represent. Therefore, the quality of the mutation operators is key to mutation testing. Mutation testing has traditionally been applied to procedural-based languages, and mutation operators have been developed to support most of their language features. Object-oriented programming languages contain new language features, most notably inheritance, polymorphism, and dynamic binding. Not surprisingly; these language features allow new kinds of faults, some of which are not modeled by traditional mutation operators. Although mutation operators for OO languages have previously been suggested, our work in OO faults indicate that the previous operators are insufficient to test these OO language features, particularly at the class testing level. This paper introduces a new set of class mutation operators for the OO language Java. These operators are based on specific OO faults and can be used to detect faults involving inheritance, polymorphism, and dynamic binding, thus are useful for inter-class testing. An initial Java mutation tool has recently been completed, and a more powerful version is currently under construction.
14599334
Communication-efficient hardware acceleration for fast functional simulation
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more time-consuming as design complexity increases. To accelerate functional simulation, hardware acceleration is used to offload calculation-intensive tasks from the software simulator. Hardware accelerated simulation dramatically reduces the simulation time. However, the communication overhead between the software simulator and hardware accelerator is becoming a new critical bottleneck. We reduce the communication overhead by exploiting burst data transfer and parallelism, which are obtained by splitting testbench and moving a part of testbench into hardware accelerator. Our experiments demonstrated that the proposed method reduces the communication overhead by a factor of about 40 compared to conventional hardware accelerated simulation while maintaining the cycle accuracy and compatibility with the original testbench.
18194762
Daily Stock Prediction Using Neuro-genetic Hybrids
We propose a neuro-genetic daily stock prediction model. Traditional indicators of stock prediction are utilized to produce useful input features of neural networks. The genetic algorithm optimizes the neural networks under a 2D encoding and crossover. To reduce the time in processing mass data, a parallel genetic algorithm was used on a Linux cluster system. It showed notable improvement on the average over the buy-and-hold strategy. We also observed that some companies were more predictable than others.
8120985
SCATOMi: scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multicasting interconnection architecture
FPGA-based logic emulator with large gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multiFPGA system incorporating several state-of-the-art FPGAs. We propose a circuit partitioning algorithm called SCATOMi(scheduling driven algorithm for TOMi) for multiFPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(time-multiplexed, off-chip, multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Experiments on architecture comparison show that, by adopting the proposed TOMi interconnection architecture along with SCATOMi, the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures including mesh, crossbar and VirtualWire architecture.
53222699
Simulation acceleration of transaction-level models for SoC with RTL sub-blocks
7677555
Stock prediction based on financial correlation
In this paper, we propose a neuro-genetic stock prediction system based on financial correlation between companies. A number of input variables are produced from the relatively highly correlated companies. The genetic algorithm selects a set of informative input features among them for a recurrent neural network. It showed notable improvement over not only the buy-and-hold strategy but also the recurrent neural network using only the input variables from the target company.