33403859
Area-power-time efficient pipeline-interleaved architectures for wave digital filters
Various forms of pipelining are explored for low power implementation of lattice wave digital filters realized with 3-port adaptors. In these filters, the time performance of pipelining is constrained by recursion. Using the fastest, block pipelined architecture as a reference point, it is shown that additional levels of pipelining can be applied to reduce the power consumption, at the expense of slightly changing the maximum sample rate. In one case power is reduced by 65% with only a modest speed penalty. Area increases due to additional pipeline registers can be more than offset if the consequent interleaving capability is utilized.
26353125
On the better protection of short-frame turbo codes
Protecting short data frames by turbo coding is a challenging task because of the small interleaver size and the need for transmission efficiency. In this letter, turbo-decoding-metrics aided short cyclic redundancy check codes are applied to novel tailbiting encoded trellis codes with a twofold purpose: to stop the iterative decoding processes to achieve low-power design and to reduce fractional coding-rate loss. Significant coding gains can be achieved by actually increasing the transmission rate with a negligible increase in power consumption. Performance improvement is demonstrated over additive white Gaussian noise channels. The savings is up to 21.4% for the transmission throughput and 21.5% for the energy consumption of the turbo decoder when frame size 49 is used.
14687819
On finite precision implementation of low density parity check codes decoder
In this paper, we analyze the finite precision effects on the decoding performance of Gallager's low density parity check (LDPC) codes and develop optimal finite word lengths of variables as far as the tradeoffs between the performance and hardware complexity are concerned. We have found that 4 bits and 6 bits are adequate for representing the received data and extrinsic information, respectively. Simulation results indicate that the quantization scheme we have developed for the LDPC decoder is effective in approximating the infinite precision implementation.
28306753
Low hardware complexity parallel turbo decoder architecture
Turbo decoders inherently have low throughput and long latency because of iterative decoding. Parallel processing is a powerful technique for high-throughput applications but often comes with large hardware complexity penalties. In this paper, we present a generic low hardware complexity parallel turbo decoder architecture, which enables multiple soft-input soft-output (SISO) decoders to process one data frame simultaneously. It can achieve multiple times the throughput of a typical serial decoder with a small fraction of hardware overhead. The proposed architecture works for any type of random interleavers, which makes it extremely useful in practical applications where turbo interleave patterns are not free to design. Based on estimation, the illustrated low hardware complexity 2-level parallel turbo decoding architecture can achieve twice the throughput of a typical serial decoding architecture with less than 20% hardware overhead when applied to 3rd generation CDMA systems.
9720590
Using the compiler to improve cache replacement decisions
Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with LRU replacement policies to combine fast access with relatively low miss rates. To improve replacement decisions in set-associative caches, we develop a new set of compiler algorithms that predict which data will and will not be reused and provide these hints to the architecture. We prove that the hints either match or improve hit rates over LRU. We describe a practical one-bit cache-line tag implementation of our algorithm, called evict-me. On a cache replacement, the architecture will replace a line for which the evict-me bit is set, or if none is set, it will use the LRU bits. We implement our compiler analysis and its output in the Scale compiler. On a variety of scientific programs, using the evict-me algorithm in both the level 1 and 2 caches improves simulated cycle times by up to 34% over the LRU policy by increasing hit rates. In addition, a combination of simple hardware prefetching and evict-me works together to further improve performance.
27330707
Some recent advances on the possibility measure theory
5251967
Foveation scalable video coding with automatic fixation selection
Image and video coding is an optimization problem. A successful image and video coding algorithm delivers a good tradeoff between visual quality and other coding performance measures, such as compression, complexity, scalability, robustness, and security. In this paper, we follow two recent trends in image and video coding research. One is to incorporate human visual system (HVS) models to improve the current state-of-the-art of image and video coding algorithms by better exploiting the properties of the intended receiver. The other is to design rate scalable image and video codecs, which allow the extraction of coded visual information at continuously varying bit rates from a single compressed bitstream. Specifically, we propose a foveation scalable video coding (FSVC) algorithm which supplies good quality-compression performance as well as effective rate scalability. The key idea is to organize the encoded bitstream to provide the best decoded video at an arbitrary bit rate in terms of foveated visual quality measurement. A foveation-based HVS model plays an important role in the algorithm. The algorithm is adaptable to different applications, such as knowledge-based video coding and video communications over time-varying, multiuser and interactive networks.
17592799
Blind separation of slow waves and spikes from gastrointestinal myoelectrical recordings
Myoelectrical recordings of the gut contain slow waves (slow rhythmicity) and spikes (fast rhythmicity). While the slow wave determines the frequency and propagation of gastrointestinal contractions, spike activities are directly associated with the contractions. Traditionally, spikes are extracted from the myoelectrical recording using high-pass/bandpass filters. Due to the sharp rising edge (high-frequency component) of the slow wave, the conventional method is not accurate in the separation of the slow wave and spikes, although it has been used for years. In this paper, a novel and fast blind source separation algorithm is developed. Experimental results show that the proposed method was able to accurately extract spike activities from the myoelectrical recordings obtained in dogs and that its performance was not affected by the high-frequency components of the slow wave.
2647804
Extended DBP for (m, k)-Firm Based QoS
In this paper, an extended DBP (E_DBP) scheme is studied for (m,k)-firm constraint. The basic idea of the proposed algorithm takes into account the distance to exit a failure state, which is a symmetrical notion of distance to fall into a failure state in DBP. Quality of Service (QoS) in terms of dynamic failure and delay is evaluated. Simulation results reveal the effectiveness of E_DBP to provide better QoS.