38112853
Low power full-search block-matching motion estimation chip for H.263+
In this paper, a low power full-search block matching (FSBM) motion estimation design for the H.263+ low bit rate video coding was proposed. The features of H.263+ such as half-pixel precision and some advanced modes (advance prediction mode, PB-frame mode and reduced resolution update mode) are taken into consideration. This architecture can deal with different block size and searching range in a single chip without any latency. We use a 1-D and 2-D mixed architecture to fulfill this goal. To achieve the purpose of low power and reduce the design period, we use dual supply voltage levels in this chip. This chip is realized by TSMC 0.6 /spl mu/m single-poly triple-metal CMOS technology. The operation frequency is set at 60 MHz to meet the requirement of the real time processing in the reduced resolution update mode in H.263+. The power consumption is 424 mW at 60 MHz and the throughput is 36 frames per second with CIF format at 60 MHz.
4181067
Error-propagation analysis and concealment strategy for MPEG-4 video bitstream with data partitioning
Data partitioning, one of the MPEG-4 video error resilience tools, enables better error robustness. However, it suffers from serious error propagation problem. In this paper, we use an experimental approach to model the error propagation with several commonly used error detection conditions. It is shown that errors detected in forward section of texture data may be propagated from motion data, while those in DCT coefficients mostly result from themselves. Furthermore, the motion marker is the major error source for several error conditions detected in motion part. According to these characteristics, motion marker assumption and backtracking-based concealment strategies are proposed to achieve more accurate error localization in bitstream domain.
16022661
Monitoring access link capacity using TFRC probe
Accurate estimation of network characteristics based on end-to-end measurements is an important and challenging problem. With the increasing variety and sophistication of Internet access methods, the mobility of the users and the need for seamless handoff across them, monitoring access link capacity becomes critical for efficient multimedia delivery. In fact, this allows the multimedia server to properly adjust its sending rate to the rapidly changing access speed of the mobile client. This problem is challenging because most of the existing capacity monitoring schemes are active, like Pathrate (and therefore, introduce extra overhead on the bandwidth limited access link). Moreover, the access link is often asymmetric (e.g. ADSL, 1xRTT, etc.) thus preventing the use of round-trip monitoring schemes such as Pathchar and CapProbe. In this study, we propose and evaluate a passive, one-way link capacity monitoring tool called TFRC Probe. With TFRC Probe the source can monitor the forward direction capacity of both asymmetric and symmetric access links, and can rapidly and accurately adapt its transmissions rate accordingly. We validate TFRC Probe with both simulation and testbed experiments, and show that TFRC Probe is a very flexible tool that can accurately track frequent changes in access capacity.
8895078
An Adaptive-Filtering Policy for Distributed Virtual Environments
In this paper, an adaptive-filtering policy for distributed virtual environments (DVEs) was brought forward. It took advantages of two traditional filtering policies (static-filtering policy and equidistance-transmission policy) and could adaptively select the fittest filtering policy corresponding to current motion characteristic of the virtual object in DVEs. An experiment was designed to compare this filtering policy with the two traditional filtering policies on task performance. Objective (task completion time, state updates transmitted and state updates per second) and subjective (filtering quality) evaluations were recorded in the experiment. The experiment results show that if mean state updates per second is equal or greater than 20 in the task, SUT and SUPS can be decreased by adaptive-filtering policy without task performance affected obviously. However, if mean state updates per second is around 10 in the task, accompanied with SUT and SUPS decreased by adaptive-filtering policy, task performance also deteriorated badly
18494182
Improving Bluetooth EDR Data Throughput Using FEC and Interleaving
Wireless communication is inherently vulnerable to errors from the dynamic wireless environment. Link layer packets discarded due to these errors impose a serious limitation on the maximum achievable throughput in the wireless channel. To enhance the overall throughput of wireless communication, it is necessary to deploy link layer transmission schemes that is robust to the errors intrinsic to the wireless channel. In this paper, we investigated the impact of three link layer enhancement techniques on the new Enhanced Data Rate (EDR) mode detailed in the new Bluetooth spec v2.0. We first studied the APT algorithm, and used it to obtain the optimal packet type for different bit error rates. We then evaluated FEC/IFEC coding schemes for the new EDR packet types, assessed their ability to alleviate the impact of burst errors, and discussed the tradeoffs. Using analysis and simulation, we show that the performance of the new Bluetooth EDR mode can be significantly improved when FEC and/or IFEC techniques are employed.
8098811
Embedded software-based self-testing for SoC design
At-speed testing of high-speed circuits is becoming increasingly difficult with external testers due to the growing gap between design and tester performance, growing cost of high-performance testers and increasing yield loss caused by inherent tester inaccuracy. Therefore, empowering the chip to test itself seems like a natural solution. Hardware-based self-testing techniques have limitations due to performance and area overhead and problems caused by the application of non-functional patterns.Embedded software-based self-testing has recently become focus of intense research. In this methodology, the programmable cores are used for on-chip test generation, measurement, response analysis and even diagnosis. After the programmable core on a System-on-Chip (SoC) has been self-tested, it can be reused for testing on-chip buses, interfaces and other non-programmable cores. The advantages of this methodology include at-speed testing, low design-for-testability overhead and application of functional patterns in the functional environment. In this paper, we give a survey and outline the roadmap and challenges of this emerging embedded software-based self-testing paradigm.
335267
VLSI implementation of shape-adaptive discrete wavelet transform
In this paper, several VLSI architectures and implementations of Shape-Adaptive Discrete Wavelet Transform (SA-DWT) with odd symmetric biorthogonal filters are presented. The hardware implementation issues of SA-DWT algorithm are first addressed, and one lifting scheme together with some appropriate shape information processing units is introduced for the 1-D SA-DWT architectures. These architectures can efficiently perform 1-D length-adaptive DWT on continuous line segments and solve the corresponding boundary extension and subsampling problems without any overhead. In addition to 1-D architectures, two 2-D SA-DWT architectures are also proposed. One is the direct method, which uses the 1-D SA-DWT architectures as basis to extend to 2-D SA-DWT by direct row-column approach. The other is the line-based method, which is an efficient and feasible architecture that uses internal line buffers rather than external frame memory. These two 2-D SA-DWT architectures are both VLSI implemented by using cell-based chip design flow. The Daubechies (9,7) filter is used for the implementation by direct method, and the Daubechies (9,3) filter is used for the line-based implementation. The proposed architectures can be applied both in arbitrarily shaped visual objects coding such as MPEG-4 still texture coding and rectangular region image coding such as JPEG2000 still image coding.