1367636
Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery
Control and data speculation are widely used to improve processor performance. Correct speculation can reduce execution time, but incorrect speculation can lead to increased execution time and greater energy consumption. This paper proposes a mechanism to leverage unexpected program behavior, called wrong-path events, that occur during periods of incorrect speculation. A wrong-path event is an instance of illegal or unusual program behavior that is more likely to occur on the wrong path than on the correct path, such as a NULL pointer dereference. When a wrong-path event occurs, the processor can predict that it is on the wrong path and speculatively initiate misprediction recovery. The purpose of the proposed mechanism is to improve the effectiveness of speculative execution in a processor by helping to insure that the processor remain "on the correct path" throughout periods of speculative execution. We describe a set of wrong-path events which can be used as strong indicators of misprediction. We find that on average 5% of the mispredicted branches in the SPEC2000 integer benchmarks produce a wrong-path event an average of 51 cycles before the branch is executed. We show that once a wrong-path event occurs, it is possible to accurately predict which unresolved branch in the processor is mispredicted using a simple, novel prediction mechanism. We discuss the advantages and shortcomings of wrong-path events and propose new areas for future research.
13287397
An analysis of the performance impact of wrong-path memory references on out-of-order and runahead execution processors
High-performance, out-of-order execution processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction algorithms. Although memory references generated on the wrong path do not change the architectural state of the processor, they affect the arrangement of data in the memory hierarchy. This paper examines the effects of wrong-path memory references on processor performance. It is shown that these references significantly affect the IPC (instructions per cycle) performance of a processor. Not modeling them leads to errors of up to 10 percent (4 percent on average) in IPC estimates for the SPEC CPU2000 integer benchmarks on an out-of-order processor and errors of up to 63 percent on a runahead-execution processor. In general, the error in the IPC increases with increasing memory latency and instruction window size. We find that wrong-path references are usually beneficial for performance because they prefetch data that is used by later correct-path references. L2 cache pollution is found to be the most significant negative effect of wrong-path references. Code examples are shown to provide insights into how wrong-path references affect performance. We also show that it is crucial to model wrong-path references to accurately estimate the performance improvement provided by runahead execution.
11226719
Understanding the effects of wrong-path memory references on processor performance
High-performance out-of-order processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction algorithms. Although memory references generated on the wrong path do not change the architectural state of the processor, they can affect the arrangement of data in the memory hierarchy. This paper examines the effects of wrong-path memory references on processor performance. It is shown that these references significantly affect the IPC (Instructions Per Cycle) performance of a processor. Not modeling them can lead to errors of up to 10% in IPC estimates for the SPEC2000 integer benchmarks; 7 out of 12 benchmarks experience an error of greater than 2% in IPC estimates. In general, the error in the IPC increases with increasing memory latency and instruction window size.We find that wrong-path references are usually beneficial for performance, because they prefetch data that will be used by later correct-path references. L2 cache pollution is found to be the most significant negative effect of wrong-path references. Code examples are shown to provide insights into how wrong-path references affect performance.
8295029
Cache filtering techniques to reduce the negative impact of useless speculative memory references on processor performance
High-performance processors employ aggressive speculation and prefetching techniques to increase performance. Speculative memory references caused by these techniques sometimes bring data into the caches that are not needed by correct execution. This paper proposes the use of the first-level caches as filters that predict the usefulness of speculative memory references. With the proposed technique, speculative memory references bring data only into the first-level caches rather than all levels in the cache hierarchy. The processor monitors the use of the cache blocks in the first-level caches and decides which blocks to keep in the cache hierarchy based on the usefulness of cache blocks. It is shown that a simple implementation of this technique usually outperforms inclusive and exclusive baseline cache hierarchies commonly used by today's processors and results in IPC performance improvements of up to 9.2% on the SPEC2000 integer benchmarks.
7488858
Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors
Dynamic predication has been proposed to reduce the branch misprediction penalty due to hard-to-predict branch instructions. A proposed dynamic predication architecture, the diverge-merge processor (DMP), provides large performance improvements by dynamically predicating a large set of complex control-flow graphs that result in branch mispredictions. DMP requires significant support from a profiling compiler to determine which branch instructions and control-flow structures can be dynamically predicated. However, previous work on dynamic predication did not extensively examine the tradeoffs involved in profiling and code generation for dynamic predication architectures. This paper describes compiler support for obtaining high performance in the diverge-merge processor. We describe new profile-driven algorithms and heuristics to select branch instructions that are suitable and profitable for dynamic predication. We also develop a new profile-based analytical cost-benefit model to estimate, at compile-time, the performance benefits of the dynamic predication of different types of control-flow structures including complex hammocks and loops. Our evaluations show that DMP can provide 20.4% average performance improvement over a conventional processor on SPEC integer benchmarks with our optimized compiler algorithms, whereas the average performance improvement of the best-performing alternative simple compiler algorithm is 4.5%. We also find that, with the proposed algorithms, DMP performance is not significantly affected by the differences in profile- and run-time input data sets
1551402
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths
This paper proposes a new processor architecture for handling hard-to-predict branches, the diverge-merge processor (DMP). The goal of this paradigm is to eliminate branch mispredictions due to hard-to-predict dynamic branches by dynamically predicating them without requiring ISA support for predicate registers and predicated instructions. To achieve this without incurring large hardware cost and complexity, the compiler provides control-flow information by hints and the processor dynamically predicates instructions only on frequently executed program paths. The key insight behind DMP is that most control-flow graphs look and behave like simple hammock (if-else) structures when only frequently executed paths in the graphs are considered. Therefore, DMP can dynamically predicate a much larger set of branches than simple hammock branches. Our evaluations show that DMP out performs a baseline processor with an aggressive branch predictor by 19.3% on average over SPEC integer 95 and 2000 benchmarks, through a reduction of 38% in pipeline flushes due to branch mispredictions, while consuming 9.0% less energy. We also compare DMP with previously proposed predication and dual-path/multipath execution paradigms in terms of performance, complexity, and energy consumption, and find that DMP is the highest performance and also the most energy-efficient design
3140924
Binary halftone image resolution increasing by decision tree learning
This paper presents a new, accurate, and efficient technique to increase the spatial resolution of binary halftone images. It makes use of a machine learning process to automatically design a zoom operator starting from pairs of input-output sample images. To accurately zoom a halftone image, a large window and large sample images are required. Unfortunately, in this case, the execution time required by most of the previous techniques may be prohibitive. The new solution overcomes this difficulty by using decision tree (DT) learning. Original DT learning is modified to obtain a more efficient technique (WZDT learning). It is useful to know, a priori , sample complexity (the number of training samples needed to obtain, with probability 1-/spl delta/, an operator with accuracy /spl epsiv/): we use the probably approximately correct (PAC) learning theory to compute the sample complexity. Since the PAC theory usually yields an overestimated sample complexity, statistical estimation is used to evaluate, a posteriori, a tight error bound. Statistical estimation is also used to choose an appropriate window and to show that DT learning has good inductive bias. The new technique is more accurate than a zooming method based on simple inverse halftoning techniques. The quality of the proposed solution is very close to the theoretical optimal obtainable quality for a neighborhood-based zooming process using the Hamming distance to quantify the error.
17092169
Robust anisotropic diffusion to produce enhanced statistical parametric map from noisy fMRI
This paper presents a new, simple, and elegant technique to obtain enhanced statistical parametric maps (SPMs) from noisy functional magnetic resonance imaging (fMRI) data. This technique is based on the robust anisotropic diffusion (RAD), a technique normally used as an edge-preserving filter. A direct application of the RAD to the fMRI data does not work, because in this case RAD would perform an edge-preserving filtering of the fMRI structural information, instead of enhancing its functional information. The RAD can be applied directly to SPM but, in this case, only a small improvement of the SPM quality can be achieved, because the originating fMRI is not taken into account. To overcome these difficulties, we propose to estimate the SPM from the noisy fMRI, compute the diffusion coefficients in the SPM space, and then perform the diffusion in the structural information-removed fMRI data using the coefficients previously computed. These steps are iterated until convergence. We have tested the new technique in both simulated and real fMRI images, yielding surprisingly sharp and noiseless SPMs with increased statistical significance. We also describe how to automatically estimate an appropriate scale parameter.
9030536
Using enterprise reference models for automated ISO 9000 compliance evaluation
A computational enterprise model representing key facets of are organization care be are effective tool to consider where planning are enterprise information architecture. For example, a specific organization's quality management business processes and organizational structures can be represented using such a model, and then compared to a reference model of "good" processes and structures, such as the ISO 9000 standards. The specific and reference models can be represented using common entities, attributes, and relationships-comprising general schema or data model-which are then formally defined and constrained. These definitions and constraints can be used as inference rules applied to the models. Hence identification of differences between the models as quality problems can be automatically inferred, as can the analysis and correction of problems. In this paper; the TOTE ISO 9000 Micro-Theory is presented as a formal reference model of quality goodness. ISO 9000 requirements represented as inference rules in the micro-theory are applied to facts about an organization's quality management processes and structures, and conformance or nonconformance to requirements is automatically inferred. TOTE Ontologies for Quality Modeling are the common data and logical (formal definitions and constraints) models of the reference and specific organization's models. The example use of the micro-theory demonstrates enterprise model use for a pre-audit, which lowers the cost and time for improving quality through achieving ISO 9000 compliance. Since these enterprise models are constructed using ontologies, benefits of using ontologies such as model re-usability and sharability can be reaped.
5469426
Unraveling condition specific gene transcriptional regulatory networks in Saccharomyces cerevisiae
BackgroundGene expression and transcription factor (TF) binding data have been used to reveal gene transcriptional regulatory networks. Existing knowledge of gene regulation can be presented using gene connectivity networks. However, these composite connectivity networks do not specify the range of biological conditions of the activity of each link in the network.ResultsWe present a novel method that utilizes the expression and binding patterns of the neighboring nodes of each link in existing experimentally-based, literature-derived gene transcriptional regulatory networks and extend them in silico using TF-gene binding motifs and a compendium of large expression data from Saccharomyces cerevisiae. Using this method, we predict several hundreds of new transcriptional regulatory TF-gene links, along with experimental conditions in which known and predicted links become active. This approach unravels new links in the yeast gene transcriptional regulatory network by utilizing the known transcriptional regulatory interactions, and is particularly useful for breaking down the composite transcriptional regulatory network to condition specific networks.ConclusionOur methods can facilitate future binding experiments, as they can considerably help focus on the TFs that must be surveyed to understand gene regulation.(Supplemental material and the latest version of the MATLAB implementation of the United Signature Algorithm is available online at [1] or [see Additional files 1, 2, 3, 4, 5, 6, 7, 8, 9, 10])
8273227
Mapping from BPMN-Formed Business Processes to XPDL Business Processes
In the business process management, many business process execution languages such as XPDL, BPML, BPEL4WS have been specified with different origins and goals. Most of all, XPDL proposed by WfMC has been widely used in the related applications, especially workflows whose concepts are currently interchangeable with those of business processes. On the other hand, Business Process Modeling Notation (BPMN) driven by BPMI has recently been specified as a standardized graphical notation for a business process. We can therefore commonly design and analyze various business processes using the design tools to support BPMN. Notice that a BPMN-formed business process should be converted to its semantically equivalent business process languages such as XPDL which can consequently be executed by business process engines. In this regard, we propose a transformation mechanism from BPMN-formed business processes to corresponding XPDL processes.