32890897
A Novel Technique for Efficient Parallel Implementation of a Classical Logic/Fault Simulation Problem
A technique is presented for formulating the logic/fault simulation of VLSI array logic in terms of standard vector and matrix operation primitives that are well supported on all scientific supercomputers, high-end mainframes, and minisupercomputers that provide vector parallel hardware and software. The overall computing environment is assumed to be a scientific/engineering one, with Fortran as the primary coding medium and the hardware biased toward numerically intensive applications. >
18281114
Performance and functional verification of microprocessors
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of the validation problem: (a) verifying the functional integrity of the model and (b) testing the model for timing accuracy at the architectural level. The latter area, that of performance verification, is of increasing importance in the design of server-class processor chips, with one or more high performance cores on a single die. We show how simulation-based test cases can be generated under a unified defect and coverage model to detect both performance and functional bugs. We present and discuss examples of such integrated validation methodologies used in real processor development projects.
26499349
Early performance estimation of super scalar machine models
A novel methodology and software tool for estimating the performance of high-performance machine models with concurrent, pipelined execution modes are presented. Such performance assessment is typically useful at early stages of the design cycle. Critical design decisions made with the aid of early estimators of the kind discussed can be expected to yield near-optimal final designs.<<ETX>>
2521753
A circuit level implementation of an adaptive issue queue for power-aware microprocessors
Increasing power dissipation has become a major constraint for future performance gains in the design of microproces sors In this paper we present the circuit design of an issue queue for a superscalar processor that leverages transmis sion gate insertion to provide dynamic low cost con gura bility of size and speed A novel circuit structure dynami cally gathers statistics of issue queue activity over intervals of instruction execution These statistics are then used to change the size of an issue queue organization on the y to improve issue queue energy and performance When applied to a xed full size issue queue structure the result is up to a reduction in energy dissipation The complexity of the additional circuitry to achieve this result is almost neg ligible Furthermore self timed techniques embedded in the adaptive scheme can provide a decrease in cycle time of the CAM array read of the issue queue when we change the adaptive issue queue size from entries largest possible to entries smallest possible in our design
31462412
Performance evaluation and validation of microprocessors
The domain of early performance analysis and microarchitecture definition is limited largely to a onedimensional perspective of net performance: that of cyclesper-instnrction (CPI). Traceor execution-driven cycle-bycycle simulators [l] are the most common toolsets used at this stage. These are often coded in a systems programming language (e.g. C, C++, PWl or Pascal). They are performance-only models in that the register and memory data values and their state changes are not modelled; only the complex pipeline flow and concurrent instruction processing semantics are simulated. The goal here is to assess CPIcentric performance and bottlenecks to aid early definition, not to ensure functional integrity. Such a simulator, which we call a CPI timer; can be implemented to run at speeds greater than 50,000 instructions per second [21. This is achieved in modelling a future processor with the simulator running on a current generation uniprocessor workstation.
44925839
MHPS-Driven Early Design and Analysis of VLSI CPU Chips
JVe present (1 noid appsoaclz to carry per/i,rinancc analysis arid tiiiiitig of VLSI processors, don(? in the context of higlt-lewl source Iceriicls. U7e illustrate our rnetliodology in 1Crt71.r of a small (exaniph?) super scalas RlSC J ~ S O C ~ S S I ~ S architecture. A pnrantetrized execution 17ic~cIeI is used fhr piforinance eslimniion. IJsing an iterative optimization techniqire, the parameter set can bc locally optiinizcd around a g i i w design point to genesare tlie ininii?itrtn cycles per. iiwtrttction ( V I ) . W e also iiicludc a ctirsory discussion on linking .rirclt a CI’I estiiizntor io an early jloorplanner jhr A f IPS-driven block layout for the processor chb.
14371068
Filling polyhedral molds
In manufacturing industry, finding an orientation for a mold that eliminates surface defects and ensures a complete fill after termination of the gravity casting process is an important and difficult problem. We study the problem of determining a favorable position of a mold (modeled as a polyhedron) such that, when it is filled, no air pockets and ensuing surface defects arise. Given a polyhedron in a fixed orientation, we present a linear time algorithm that determines whether the mold can be filled from that orientation without forming air pockets. We also present an algorithm that determines the most favorable orientation for a polyhedral mold in O(n2) time. A reduction from a well-known problem indicates that improving the O(n2) bound is unlikely for general polyhedral molds. We relate fillability to some well known classes of polyhedra. For some of these classes of objects, an optimal direction of fillability can be determined in linear time. Finally, for molds that satisfy a local regularity condition, we give an improved algorithm that runs in time O(nklog2 nlog log(nk)), where k is the number of venting holes needed to avoid air pockets in an optimal orientation.
11371450
Geometric and computational aspects of gravity casting
In the manufacturing industry, finding an orientation for a mould that eliminates surface defects and ensures a complete fill after the termination of the gravity casting process is an important and difficult problem which has not previously been investigated formally. The paper initiates the study of the gravity casting process from a geometric perspective and presents an optimal θ(n log n) time algorithm that solves this problem in 2D given an object of size n. The paper also characterizes the object shapes (modelled as simple polygons) that can be 1-filled and relate fillability to well known classes of polygons. For certain classes of objects, an optimal direction of fillability can be determined in linear time.
18853139
K-Guarding Polygons on the Plane
Let P be a simple polygon with n vertices. We say that P is k-guardable if it is possible to find a set of points Q consisting of interior points of edges of P such that every point of P is visible from at least k elements in Q and no edge of P has more than one element in Q. The following question was asked by A. Lubiw at the open problem session of the Fourth Canadian Conference in Computational Geometry: For what values of k, is every simple polygon k-guardable? It has been observed by T. Shermer that comb polygons [Chv75, O'R87] are not 3-guardable; such a polygon is shown in Figure 1.
1566102
On simplifying dot maps
Dot maps--drawings of point sets--are a well known cartographic method to visualize density functions over an area. We study the problem of simplifying a given dot map: given a set P of points in the plane, we want to compute a smaller set Q of points whose distribution approximates the distribution of the original set P.We formalize this using the concept of e-approximations, and we give efficient algorithms for computing the approximation error of a set Q of m points with respect to a set P of n points (with m ≤ n) for certain families of ranges, namely unit squares, arbitrary squares, and arbitrary rectangles.If the family R of ranges is the family of all possible unit squares, then we compute the approximation error of Q with respect to P in O(n log n) time. If R is the family of all possible rectangles, we present an O(mn log n) time algorithm. If R is the family of all possible squares, then we present a simple O(m2n + n log n) algorithm and an O(n2 √n log n) time algorithm which is more efficient in the worst case.Finally, we develop heuristics to compute good approximations, and we evaluate our heuristics experimentally.
1023852
Coarse grained parallel maximum matching in convex bipartite graphs
We present a coarse grained parallel algorithm for computing a maximum matching in a convex bipartite graph G=(A,B,E). For p processors with N/p memory per processor, N=|A|+|B|,N/p/spl ges/p, the algorithm requires O(log p) communication rounds and O(T/sub sequ/(n/p,m/p)+n/p log p) local computation, where n=|A|,m=|B| and T/sub sequ/(n,m) is the sequential time complexity for the problem. For the BSP model, this implies O(log p) supersteps with O(gN+gn/p log p) communication cost and O(T/sub sequ/(n/p,m/p)+n/p log p) local computation.