19995952
ATOMi: an algorithm for circuit partitioning into multiple FPGAs using time-multiplexed, off-chip, multicasting interconnection architecture
Logic emulation is so far the fastest method to verify the system functionality in the gate level before chip fabrication. Field-programmable gate array (FPGA)-based logic emulator with large gate capacity generally comprises a large number of FPGAs or special processors connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. This paper first describes a new interconnection architecture called TOMi (Time-multiplexed, Off-chip, Multicasting interconnection) and proposes a circuit partitioning algorithm called ATOMi (Algorithm for TOMi) for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi. ATOMi reduces the number of off-chip signal transfers to optimize the performance for multi-FPGA system implemented by TOMi. Experimental results using Partitioning93 benchmarks show that, by adopting the proposed TOMi interconnection architecture along with ATOMi, the pin count is reduced to 14.4%-88.6% while the critical path delay is reduced to 66.1%-90.1% compared to traditional architectures including mesh, crossbar, and VirtualWire architecture.
13416160
Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation
As the processing capabilities and operating frequency of embedded system are growing, so is the needed data bandwidth to fully utilize the processing capability. The ability to transfer huge amount of data between the embedded core and external devices is required for efficient system operation. In this paper, the data communication architecture for the mixed-clock system is proposed. The dynamic priority adaptation algorithm for bus arbitration is proposed for bandwidth guarantee. The communication architecture that incorporates the proposed arbitration algorithm adapts the priority of communication components dynamically based on the information from FIFO. The experiments show that the measured bandwidth of each component traces the required bandwidth well compared to the other arbitration algorithms.
14181871
Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus
Simulation is the most viable solution for the functional verification of system-on-chip (SoC). The acceleration of simulation with multi-field programmable gate array (multi-FPGA) emulator is a promising method to comply with the increasing complexity and large gate capacity of SoC. Time multiplexing of interconnection wires is the inevitable solution to solve the pin limitation problem that limits the gate utilization of FPGAs and speed of multi-FPGA simulation accelerators. The most time-consuming factor of multi-FPGA simulation acceleration is the synchronization time between a software simulator and a multi-FPGA system and the inter-FPGA synchronization time. This paper proposes a performance-driven signal synchronization mechanism for a simulation accelerator with multiple FPGAs using time-multiplexed interconnection. The event-based signal synchronization optimizes the synchronization time between a software simulator and the multi-FPGA system as well as the synchronization time among FPGAs. The synchronization time among FPGAs is optimized by circuit partitioning considering the signal probability, net dependency reduction, and efficient net clustering to reduce addressing overhead. The synchronization time between the software simulator and the multi-FPGA system is also optimized by exploiting the event probability of primary nets. Experiments show that the synchronization time is reduced to 6.2-9.8% of traditional mechanisms.
53222699
Simulation acceleration of transaction-level models for SoC with RTL sub-blocks
1673424
Pyramid texture compression and decompression using interpolative vector quantization
Texture mapping is a common technique used to increase the visual quality of 3D scenes. As texture mapping requires a large amount of memory to deal with large textures generally required in the current visual systems, we propose an algorithm for compressing a pyramid texture used for mipmapping. Vector quantization is used to compress all levels of the pyramid texture to one representative value databook, one residual codebook and one index map. The proposed compression scheme uses interpolative texel difference vector quantization that compresses the difference between the interpolated surfaces generated by the representative value and the correct uncompressed texels of the texture at each level. The compressed pyramid texture can be accessed randomly and decompressed without loss of visual quality. We also propose a hardware architecture that performs the trilinear filtering with the compressed pyramid texture.
13829945
Detecting common mode failures in N-version software using weakest precondition analysis
An underlying assumption for N-version programming technique is that independently developed versions would fail in a statistically independent manner However empirical studies have demonstrated that common mode failures can occur even for independently developed versions, and that common mode failures degrade system reliability. In this paper, we demonstrate that the weakest precondition analysis is effective in determining input spaces leading to common mode failures. We applied the weakest precondition to the Launch Interceptor Programs which were used in several other experiments related to the N-version programming technique. We detected 13 out of 18 fault pairs which have been known to cause common mode failure. These faults were due to logical flaws in program design. Although the weakest precondition analysis may be labor-intensive since they are applied manually our results convincingly demonstrate that it is effective for identifying input spaces causing common mode failures and further improving the reliability of N-version software.
8261294
Inter-class mutation operators for Java
The effectiveness of mutation testing depends heavily on the types of faults that the mutation operators are designed to represent. Therefore, the quality of the mutation operators is key to mutation testing. Mutation testing has traditionally been applied to procedural-based languages, and mutation operators have been developed to support most of their language features. Object-oriented programming languages contain new language features, most notably inheritance, polymorphism, and dynamic binding. Not surprisingly; these language features allow new kinds of faults, some of which are not modeled by traditional mutation operators. Although mutation operators for OO languages have previously been suggested, our work in OO faults indicate that the previous operators are insufficient to test these OO language features, particularly at the class testing level. This paper introduces a new set of class mutation operators for the OO language Java. These operators are based on specific OO faults and can be used to detect faults involving inheritance, polymorphism, and dynamic binding, thus are useful for inter-class testing. An initial Java mutation tool has recently been completed, and a more powerful version is currently under construction.
8907079
An empirical study on software error detection: voting, instrumentation and Fagan inspection
The paper presents the results of an experiment that compared error detection capability of voting, instrumentation, and Fagan inspection methods. Several experiments have measured effectiveness of various error detection methods. However, most experiments have used different programs; consequently, the results are generally incompatible and do not allow one to make objective comparison on the cost-effectiveness of various approaches. Software cannot be developed using an unlimited amount of resources, and practitioners need empirical and objective data on the cost-effectiveness of various error detection methods to decide which methods to use during software development. Results of this experiment is significant because these methods have been applied to the same program. Furthermore, the participant's educational and industrial experience are comparable to that of the previous experiments. We confirmed the previous finding that detecting errors in reliable programs is difficult; none of the three methods detected more than half of all the known errors in the programs. Of the three methods employed, participants detected more errors by using Fagan inspection method than they did by voting or instrumentation. When the average number of hours needed to detect an error was compared, Fagan inspection method was shown to be more cost-effective than instrumentation method.
5100963
Scalable Modeling and Performance Evaluation of Wireless Sensor Networks
A notable features of many proposed Wireless Sensor Networks (WSNs) deployments is their scale: hundreds to thousands of nodes linked together. In such systems, modeling the state of the entire system as a cross-product of the states of individual nodes results in the well-known state explosion problem. Instead, we represent the system state by the probability distribution on the state of each node. In other words, the system state represents the probability that a randomly picked node is in a certain state. Although such statistical abstraction of the global state loses some information, it is nevertheless useful in determining many performance metrics of systems that exhibit Markov behavior. We have previously developed a method for specifying the performance metrics of such systems in a probabilistic temporal logic called iLTL and for evaluating the behavior through a novel method for model checking iLTL properties. In this paper, we describe a method for estimating the probabilities in a Discrete Time Markov Chain (DTMC) model of a large-scale system. We also provide a statistical test so that we can reject estimated DTMCs if the actual system does not have Markov behavior. We describe results of experiments applying our method toWSNs in an experimental test-bed, as well as using simulations. The results of our experiments suggest that our model estimation and model checking method provides a systematic, precise and easy way of evaluating performance metrics of some large-scale WSNs.
1158464
Response to 'More comments on: A cohesion measure for object-oriented classes'
The authors insist that monotonicity is a necessary property of a good cohesion metric and the violation of the monotonicity property limits the application of CBMC. They also state that the augmented CBMC can also be used as a guideline for quality evaluation and restructuring of poorly designed classes. This paper raises the question about the necessity of monotonicity by analyzing the reason that causes CBMC to violate the monotonicity property. In addition, we give a detailed description of the restructuring procedure based on CBMC. Copyright c © 2003 John Wiley & Sons, Ltd.