Electrical stressing effects in solid-phase crystallized polysilicon thin film transistors
The evolution of the electrical parameters of solid-phase crystallized polysilicon thin film transistors under various stressing-gate and drain-bias values was studied. Under VGS stressing, the threshold voltage Vth exhibits an initial negative shift attributed to hole trapping and a subsequent turnaround, occurring sooner for larger stressing VGS, towards positive shifts with a logarithmic time dependence, indicating an electron trapping process occurring in the oxide and at the polysilicon/SiO2 interface. The subthreshold swing, the midgap trap state density and the transconductance exhibit a concomitant logarithmic degradation, attributed to a stress-induced acceptor trap creation at the interface and in the polysilicon active layer, corroborating the electron trapping process inferred from the Vth data. The simultaneous application of a small VDS stressing in combination with the VGS stressing suppresses this Vth turnaround effect and enhances the degradation of all parameters. The reduction of the turnaround stressing time as well as the increase in the subthreshold swing and the midgap trap state density correlated with the increase of the stressing current IDS, indicating a concomitant increase of the stress-induced trap creation and the electron trapping.