A Review of Different Types of Digital Delay-Locked Loop in 65nm CMOS technology
A review of wide-range all-digital delay-locked loop is proposed in this paper . Based on the binary search scheme, the locking time can be reduced. Besides, the proposed leakage delay unit (LDU) can easily generate a large delay to reduce the difficulties to build up the high-speed digital counter in the cycle-controlled delay unit (CCDU) for a very low frequency operation. By using the cycle-controlled delay unit (CCDU), it reuses the delay units to enlarge the operating frequency range rather than cascading a large amount of delay units. Thus, the chip area can be reduced, too. A 600 kHz to 1.3 GHz all-digital delay-locked loop has been fabricated in UMC 65nm CMOS technology. The proposed DLL consumes a maximum power of 2.6 mW at 1.2 GHz. When the operating frequency is 1.2 GHz, the measured rms jitter and peak-to-peak jitter is 3.38 ps and 39.29 ps, respectively. In the current era of technological progress, with the fast evolution of the semiconductor manufacturing process entering the VLSI system. As the rapid grow up of high-speed circuits, the complexity of the chip and the clock frequency increases with time. Therefore, requirements for clock signal quality for the on-chip modules becoming more and more important now. How to eliminate the clock skew in high-speed, high-performance VLSI and System-On-Chip (SoC) becomes a very important issue. Most of the sequential systems use the clock signal for entire system synchronization. However, many circuits need an external oscillator due to design consideration, process factor and other reasons such like chip co-works with a synchronized clock. There are many problems in signal transmission from off-chip clock source. The wire-mismatch causes the clock rising edge does not transit at the same time in all modules. The clock signal arrives to different components at different times is called clock skew. With the complexity of VLSI system increases rapidly, the clock skew is also a phenomenon in a single chip. In order to distribute the clock for large clock loading nets, clock tree synthesis is needed. Thus how to minimize the clock skew among all modules is very important. Clock skew causes setup time and hold time violations, thus it may destroy the correctness of latched data. Both Phase-Locked Loops (PLL's) and Delay-Locked Loops (DLL's) can be used to solve the clock skew problems in microprocessors and high-speed I/O interfaces. However, PLL accumulates phase error or clock jitter, makes jitter performance worse than DLL. If the frequency multiplication is not required, the DLLs are preferred for its unconditional stability, faster locking time and better jitter performance.