Low cost fault tolerance against kc-cycle and km-unit transient for loop based control data flow graphs during physically aware high level synthesis
Abstract Recent literatures have proved that current technologies pose grave reliability concern for digital devices due to possibility of multiple (k m )-unit transient fault (MTF) and multi (k c )-cycle transient fault (MCT) emanating from particle strike with moderate linear energy transfer (LET). This has arisen due to massive scaling in device dimensions and surge in device frequency happening so far. In the literature solutions for fault tolerant design, that can address MTF and MCT simultaneously during high level synthesis (HLS) for both loop based and non-loop based applications, does not exist. This paper presents the following novel contributions: (a) novel fault tolerant HLS methodology for simultaneously providing multi-cycle (control step) and multi-unit transient fault tolerance for loop based control data flow graphs (b) novel HLS methodology for low cost design solution through exploration of fault tolerant hardware configuration and loop unrolling factor. Results of the proposed approach on standard benchmarks yielded fault tolerant solutions with significantly reduced design cost (average ~ 27%) and power consumption (average ~ 61%) when compared to a recent similar approach.