Design and analysis of the Stacked-Banyan ATM switch fabric
Abstract ATM switches in future broadband networks will be required to support multigigabits/sec port speeds. At such high switching speeds, space-division switch architectures are more competitive than currently implemented shared-memory switch architectures. In this paper, we present the design and analysis of a new switch architecture, named Stacked-Banyan (SB), which utilizes parallel Banyan planes and supports K QoS levels with output queuing. The Banyans are composed of 2 × 4 switching elements (SEs). The SE is implemented by 0.35 μ CMOS logic gates. Circuit simulations of the SE show satisfactory performance at 1 Gbps. The non-blocking behavior of the SB fabric is verified by VHDL. The proposed fabric uses output queuing to resolve contention. In general, the output buffer handles K QoS levels by K virtual queues. Focusing on the case K=2, we propose a buffer management and channel allocation strategy that can be adjusted to meet the delay and loss requirements of the two types of traffic. The output buffer is managed as two virtual queues, each handling a different traffic type. To meet the delay QoS of one traffic type, the channel is allocated to the respective queue with a probability that depends on the congestion level in that queue. We present a model and analysis of the output queues and calculate the waiting time and loss performance under two specific allocation strategies. The results indicate that the proposed channel allocation strategy is quite effective in maintaining a balance between the QoS objectives of the two traffic types.