System ESD robustness by co-design of on-chip and on-board protection measures
System-level ESD robustness is a crucial feature for any electronic system. However, a consistent design methodology including IC-level protection, on-board protection and physical design of the module is still missing. The idea of a simple correlation between IC-level and system-level ESD robustness levels is misleading. A thorough characterization of the high current behaviour of IO circuit and on-board protection elements provides the necessary data for a simulation based co-design of on-chip and on-board protection measures. The constraints for characterization and modelling are discussed and the various protection measures for improved system-level ESD robustness are presented. Applying this methodology allows the development of a cost optimized system-level ESD protection throughout the stages of a system design.