Bias temperature reliability of p-channel high-voltage devices
Abstract Important shifts in the threshold voltage of high voltage p-channel DMOS transistors have been observed. These shifts are strongly dependent on the stress conditions. An empirical degradation model is derived from measurement data. For a given allowed shift in threshold voltage, this model can determine the safe operating area of the device. The shift in threshold voltage in the p-channel DMOS transistors is explained by excitation and trapping of holes at the oxide-silicon interface at the drain side.