Investigation of degradation mechanisms in low-voltage p-channel power MOSFETs under High Temperature Gate Bias stress
Abstract In this work we investigate the degradation mechanisms occurring in a p-channel trench-gate power MOSFET under High Temperature Gate Bias (HTGB) stress. The impact of negative bias temperature stress is analysed by evaluating relevant figures of merit for the considered device: threshold voltage, transconductance and on-resistance. Temperatures and gate voltages as large as 175 °C and −24 V, respectively, are adopted to accelerate the degradation in the device. Moreover, in order to investigate the origin of degradation mechanisms we analyse the interface states generation and the charge trapping processes, the impact of a switching gate voltage during the stress phase and the recovery phase after HTGB stress.