Non-trivial GR and 1/f noise generated in the p-Si layer of SOI and SOS MOSFETs near the inverted front or buried p-Si/SiO2 interface
The nature of the non-trivial low-frequency (LF) current noise of both generation-recombination (GR) and 1/f type observed in accumulation and depletion mode (AM/DM) p-MOSFETs and enhancement mode (EM) n-MOSFETs fabricated in silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) substrates is investigated, for gate biasing conditions where either the front or the back p-Si/SiO2 interface is in weak or strong inversion. The noise considered increases sharply with increasing positive gate voltage near the inversion threshold and is very high under strong inversion conditions. For the GR noise, it has been shown that both the noise relaxation time and the spectral density SI(0) at the low frequency plateau of the corresponding Lorentzians are only determined by the inverting front (back) voltage UGf,b in AM/DM p-MOSFETs, while the drain current is the main factor determining and SI(0) in EM n-MOSFETs. As to the 1/f noise, a high scatter in the data obtained in different samples has been observed in SOS DM p-MOSFETs and a correlation between the level of this noise and the behaviour of the current has been revealed. Arguments are presented that the GR and 1/f noise at stake are of a similar physical nature and are typical for devices with an inverted p-Si/SiO2 interface. It is shown that the responsible noise centres are located in a narrow layer of the p-type silicon film in the close vicinity of the p-Si/SiO2 interface. A model to explain all non-trivial features of both the noise and the current is proposed and validated.