Design for built-in FPGA reliability via fine-grained 2-D error correction codes
Abstract Radiation-induced multiple bit upsets (MBUs) degrade the reliability of scaled static random access memory (SRAM)-based field programmable gate arrays (FPGAs). Reducing the correction time for MBU and preventing the error accumulation are the challenges faced by error correction code (ECC) integrated FPGAs. In this paper, a novel built-in ECC using encode-and-compare of the data and parity bits is proposed to reduce the correction time and improve the reliability of FPGA. Implementation has been carried out in FPGA to confirm its effectiveness. The proposed method is 5 times faster than existing CRC based inbuilt error mitigation solution. This work opens a door for 2-D ECC to be universally used in FPGAs for safety-critical applications.