Design and Analysis of Low offset High speed Dynamic Comparator
Ratansang S Vaghela1 and Priyesh P. Ghandhi2 1,2 Electronics and Communication Dept, LCIT, Bhandu, North Gujarat, India Abstract ___ This paper contain a low voltage, low offset and high speed proposed cmos voltage comparator. It has application in mainly flash and pipeline ADC. It has been characterized with features like propagation delay, offset voltage, input common mode range, slew rate and speed etc. Simulation is done with the help of mentor graphics using TSMC 180nm and Generic 90nm technology. Comparative analysis of proposed comparator with previous dynamic Comparator using both technologies has been shown.