From substrate to VLSI
SOI is a promising technique to achieve both high-speed and high-level hardened VLSI-ULSI circuits. However, such aims still need a full demonstration. The purpose of this paper is to present a SOI technology with a hardened variant, and to focus on some of the weakest points that could impede the progress of SOI towards high speed hardened VLSI. The peculiarities of the devices described here are: the LOCOS isolation method instead of the commonly used MESA, and the use of a thin active silicon layer, on which no epitaxy takes place. Dose and dose rate tests have been performed on both technologies and on various circuits and special-purpose devices. An analysis of the circuits sensitivity to SEU has been performed and a hardness limitation coming from ion-induced transient caused by substrate-related phenomenon was found. Dose, dose rate and SEU behaviours are related to the structure peculiarities mentioned above.