Efficient statistical capacitance extraction of nanometer interconnects considering the on-chip line edge roughness
In this paper, efficient techniques are presented to extract the statistical interconnect capacitance due to random geometric variations, especially the line-edge roughness (LER). Based on the continuous-surface variation (CSV) model depicting wire thickness and width variations, an efficient approach is presented to calculate the capacitance sensitivity with respect to geometric variable, and further the statistical capacitance variance. The Hermite polynomial collocation (HPC) technique with variable reduction is also presented to generate the linear statistical capacitance model. Numerical experiments are carried out on structures in the 45 nm down to the 19 nm technologies. The results demonstrate the presented approaches are several orders of magnitude faster than the MC simulation with 5000 samples. The error of the sensitivity-based approach is less than 10% for the 45 nm structures, while the HPC-based technique exhibits better accuracy, even for the 19 nm structures with strong LER effect.