An Effective Method for Interconnect Delay Optimization of ASIC’s
With the development of integrated circuit design into 65nm process, interconnect delay has become one of the key factors that hinder the convergence of time sequence. Firstly, the determinants of interconnect delay are analyzed by Elmore delay model, and then experiments are carried out at the stage of circuit physical design. Verify the metal layer, metal width, buffer driving ability and buffer number can effectively optimize the interconnect delay. Introduction With the design of integrated circuits entering the nanometer stage, especially the process nodes of 65nm and below, the chip integration is getting higher and higher, and the chip scale is gradually increasing, reaching tens of millions or even hundreds of millions of gates.At the same time, the size of transistors and interconnects are scaled down, and the resistance and coupling capacitance of the interconnects are constantly increasing due to the scaled reduction of the width and spacing of the interconnects. As a result, the delay of the interconnects is constantly increasing, which has become a key consideration in the back-end physical design.With the increase of chip area, there will inevitably be a large number of long-distance interconnects, which will cause great restrictions on timing convergence, especially for critical paths, thus affecting the timing, resulting in functional errors. The basic way to reduce interconnect delay is to use better interconnect materials.Silicide and copper interconnects help to reduce the resistance of polycrystalline silicon and metal wires, respectively, and insulation layers with low-K dielectric can reduce capacitance[1].Copper and low-K dielectric insulators have been widely used in nanoscale CMOS processes, but new materials can only be temporarily maintained for one or two generations, which can not solve the fundamental problem of long wire delay.Updating design technology is the only way to solve this problem.On this basis, the interconnect delay optimization experiment is carried out by optimizing the line width spacing and inserting buffer in the circuit physical design stage.The results show that the method can effectively reduce the delay of interconnection. Interconnect Delay Estimation Interconnect Delay Estimation To analyze long interconnect wire, we first need to establish an analytical model for them. Because the parasitic parameter of a wire is distribute along its length rather than concentrating on one point. Therefore, for a longer wire, it can be expressed as a lumped n section RC structure[2],as shown in Figure 1.Then the approximate model Elmore delay model is used to calculate the delay of the wire. Figure 1. Elmore delay computation model. Let the length of the wire be L, the equivalent resistance of the long wire be Rwire , nd the equivalent 255 capacitance be Cwire . Divide the wire into n segments, and the length of each segment be l=L/n.Let r and c be the resistance and capacitance of the per unit length, so that each resistance and capacitance is rL/n and cL/n, respectively. Using the Elmore delay formula, the delay time of the whole wire can be calculated TD: TD= R1 C1+( R1+ R2)C2+( R1+ R2+ R3)C3 ...( R1+ R2+...+ Rn)Cn =(L/n) 2 (rc+2rc+...+nrc)=rcL 2 (n+1)/(2n) (1) When the n value tends to infinity, the Eq.1 is simplified as follows: TD= rcL 2 /2= Rwire Cwire /2 (2) Delay Optimization Clock routing usually has the highest priority of cabling due to its importance and particularity. As far as possible, avoid the clock deviation and control the total length and delay of the interconnect.The clock subtree topology is generated by minimizing the clock bias and the total routing length.When the clock line is routed, the length of the connection is optimized and the delay balance is guaranteed. According to Eq.2, the interconnect delay can be optimized by three points: equivalent resistance Rwire, equivalent capacitance Cwire and interconnect length L. Firstly, The increase of resistance is the main reason for the sharp increase of RC delay in interconnects. To reduce the resistance, the cross-sectional area of the interconnect can be increased, such as increasing the width and thickness of the interconnect. Because the resistance of the interconnect is proportional to the length of the interconnect, it is inversely proportional to the cross-sectional area of the interconnect.Therefore, on the premise of the continuous increase of interconnects, increasing the thickness of the interconnects properly can reduce the resistance of the interconnects, thereby reducing the overall resistance. Secondly, the capacitance is mainly composed of the coupling capacitance of metal to substrate and the coupling capacitance of the interconnects around the metal.As the chip size continues to shrink, the distance between adjacent interconnects is also decreasing, and the coupling capacitance between interconnects is inversely proportional to their spacing, so the capacitance of interconnects is also increasing.To reduce capacitance, a higher metal can be used to connect or reduce the side area of the metal. Multiply line width metal can reduce the resistance of the metal itself, and multiple spacing can reduce the coupling capacitance of the metal.Thus, the delay of interconnection can be effectively reduced, the reliability of clock network can be increased, and the sensitivity of clock deviation can be reduced[3]. Then we can reduce the interconnect length L.The insertion buffer can split the interconnect into segments, but the insertion buffer also introduces additional delay.And different numbers, types and driving capacity will result in different optimization results. The interconnect is divided into several segments to calculate the delay of each segment separately, and then the total delay of the whole segment is calculated by adding the delay of each segment. Figure 2. Delay calculation model after inserting m buffers[4]. As shown in Figure 2, when the m buffer is inserted, the interconnect is divided into m+1 segments, and the delay of each conductor is t: t=rcL 2 /[2(m+1) 2 ] (3) Assuming that the delay of the buffer is fixed to t_b , the total delay T of the interconnect is m after the insertion of the buffer is T: