Two effective methods to mitigate soft error effects in SRAM-based FPGAs
Abstract This paper proposes an effective architecture that can mitigate Single Event Upset (SEU) effects in SRAM-based FPGAs. The architecture employs two different methods in both logic and interconnection resources. The logic resources utilize a new function generator that can tolerate 100% of single faults in its configuration memory while it can generate all the k -input Boolean functions. In the interconnection resources, a kind of formation redundancy that can detect 94% of single faults in its configuration memory is applied. Both methods are based on an interesting relation in Boolean functions, identified as mapping. By this concept, a Boolean function is generated by modifying the inputs of other Boolean functions. The effectiveness of the proposed architecture is procured by a standard fault injection tool; moreover, different parameters such as required area, power, and delay are achieved by using synopsis® synthesis tool. The results show that the area, power, and delay overheads are respectively 179%, 94%, and 60% in comparison with the simple architecture.