Investigations on the physical limitation and electrostatic improvement of a gate-all-around silicon nanowire transistor with Schottky barrier source/drain
The electrostatics of Schottky barrier (SB) source/drain (S/D) silicon nanowire transistors (SB-NWTs) are investigated in comparison with the conventional silicon nanowire transistors (SNWTs). The SB-NWTs are found to have degraded transfer/output properties, unacceptably large linear-region resistance (Rlin) and non-uniform gate controllability in the sub-threshold region. With low S/D Schottky barrier height and effective tunneling mass, the electrostatic properties of SB-NWTs can be enhanced. However, quantitative assessment shows that the enhancement is limited by the fact that the sub-threshold swing of SB-NWTs cannot prevail over that of SNWTs, and unexpected degradation in drain-induced barrier lowering (DIBL) as well as device scalability can be induced. It is also shown that, even under the most optimized condition, the Rlin of SB-NWTs is still larger than that of SNWTs, if the S/D extension (SDE) length of the standard SNWTs is designed to be short enough. It is shown that, from the point of electrostatic improvement, the replacement of SNWTs by SB-NWTs cannot be promising. The physics and effectiveness of Schottky barrier modulation approaches, such as dopant segregation and Fermi-level depinning, are also discussed.