The yield models and defect density monitors for integrated circuit diagnosis
Abstract In IC manufacturing, the yield of a product is of important consideration. The yield of a circuit is governed by the defects developed in the circuit during fabrication. The accurate identification of the fault and its location helps in improving yield and in reducing development time. This paper reviews the yield models used in predicting the IC yield in semiconductor manufacturing and discusses the practical approach to yield analysis. An approach to systematic process diagnosis by IC structural decomposition is discussed. The design method and layout of some of the defect density test structure monitors are discussed. An example of the process problem analysis is also given.