The reliability modelling of RAM/ROM fault tolerant memories
Abstract This paper defines two classes of RAM/ROM chip-pin failures which are then taken into consideration in the reliability analysis of single error correcting random access memories (SEC-RAMs), designed with memory chips having a specified word-length. The analysis is based on three memory-chip failure models which take into account the impact of memory-cell failures on the bit, sub-array and chip-array levels. The analytical expression developed are used in the reliability analysis of various memory designs with single-error correcting capabilities.