DWarn+:An Enhanced Fetch Policy for SMT Processors
Simultaneous Multithreading (SMT) processors improve performance by allowing running instructions from several threads simultaneously at a single cycle. These threads executing simultaneously share the processor′s resources, but at the same time compete for them. A thread missing in L2 cache may occupy most of available resources for a long time, causing other threads run slower than they could or even stall because of lack of resources. As a result, the overall performance of SMT processors is degraded. To prevent this situation, many instruction fetch policies are proposed. DWarn is among the most efficient fetch policies to handle L2 cache misses. In this paper, an enhanced version of the DWarn policy called DWarn+ is presented. Results show that our policy significantly improves the original one when not more than four threads run, whether using IPC as a metric or using Hmean as a metric. When the number of threads running is higher than 4, DWarn+ enhances the original one mainly for memory bounded workloads, and the average improvement for all types of workloads is very limited.