Performance Analysis of a Nonblocking ATM Switch with a Bufferless Internal Speedup Fabric
Abstract In this paper, we study a non-blocking ATM switch with internal speedup. Modifying the model developed in [X.R. Cao, The maximum throughput of a nonblocking space-division packet switch with correlated destinations, IEEE Transactions on Communications, 43 (5) (1995) 1898–1901], we can obtain the maximum throughput of such a switch; approximating the output process by a discrete-time Markov modulated arrival, we can calculate the cell loss probability at the output buffers. Our approach can be applied to switches with arrival traffic having correlated destinations and asymmetric routing probabilities. Simulation results illustrate that the approach is very accurate under various traffic conditions.