Impact of NBTI and HCI on PMOSFET threshold voltage drift
Abstract Negative bias temperature instability (NBTI) induced PMOSFET parameter degradation is a serious reliability concern in advanced analog and mixed signal technologies. In this paper, Vt-mismatch shift due to NBTI in a cascode current mirror is examined. The impact of NBTI and hot-carrier injection (HCI) on threshold voltage degradation and subsequent damage recovery during annealing is also studied. Finally the influence of channel length, gate voltage, drain voltage and damage recovery on conventional NBTI and HCI DC lifetime extrapolation is characterized with the impact on analog applications highlighted.