Material property, compatibility, and reliability issues in diamond-enhanced, GaAs-based plastic packages
GaAs MESFET (chipw minimum principal stress, S1, in the GaAs) to consist of (1), a leadframe-substrate (CVDD) ‘overlap’ configuration, (2), an all-metallic assembly process (die attach + leadframe attach) and (3), a ‘compliant’ metal interlayer between GaAs and CVDD. Additionally, oxidative chemical treatment of the CVDD surface provided a strong affinity between the polymer encapsulant and CVDD, resisting over 50 cycles of 15 min boiling water immersion and peel-adhesion tests before exceeding the criterion for failure. Employing these considerations in the fabrication of CVDD-enhanced GaAs plastic packages provided for significant improvements over the conventional package design with a Cu leadframe substrate. The GaAs/CVDD plastic package performance milestones were: (a) greater than 50% reductions in Θj relative to the Cu die-paddle package (Θj chipw (b) 20 W continuous operation for 96 h with Θj chipw (c) passed MIL STD 883 1000 cycle, −55 to 125°C temperature exposure; (d) passed highly accelerated stress testing, HAST, (110°C, 200 h, 85% RH, 3.1 atm). Electrical performance testing (S-parameter) on metallized CVDD coplanar transmission lines and diamond-enhanced, coplanar GaAs flip-chip MESFET packages showed: (a), transmission line performance equivalent to Al2O3 (<1.5 dB at 20 GHz, VSWR = 1.2 : 1) and (b), near identical performance of devices (no package) and diamond-enhanced, plastic encapsulated packages. These results illustrate that diamond can be processed/packaged using conventional electronics manufacturing techniques and provide superior performance with high reliability for plastic packages.