A self-aligned gate GaN MOSFET using an ICP-assisted low-temperature Ohmic process
We report a new approach in fabricating a self-aligned gate GaN MOSFET. The fabrication technique is based on a double-layer photoresist (PR) and low-temperature-Ohmic formation process assisted by an inductively coupled plasma (ICP) dry etching process. In this process, the active region was automatically defined by the combination of a subsequently developed positive PR and the existing negative PR pattern. The Al Ohmic electrodes on the ICP-treated active region were formed by a lift-off process followed by 500 °C N2 1 min annealing. The specific contact resistance of 4.8 × 10−6 Ω cm2 was obtained in this process. Operation up to a gate bias of 30 V was confirmed. The maximum output current of 98 mA mm−1 and field-effect mobility of 110 cm2 V−1 s−1 were observed in the device with a gate length of 4 μm. Some non-ideal effects in this device, including the negative threshold voltage, larger off-state leakage and unsaturated on-state drain current, were also observed and analyzed. Some possible ways to improve the performance of the device were proposed.