Enhanced performance virtual substrate heterojunction bipolar transistor using strained-Si/SiGe emitter
We have investigated the influence of strained-Si cap layers on n–p–n heterojunction bipolar transistors (HBTs) fabricated on virtual substrates. Using an approximate theoretical model, it is found that the presence of a strained-Si/SiGe (relaxed) heterojunction barrier in the emitter can substantially improve the HBT's current gain, relaxing the need for a high Ge content in the strained base. Furthermore, two-dimensional numerical simulations of a virtual substrate HBT with a realistic geometry demonstrate that, besides the current gain enhancement, a three times improvement in ft and fmax can be realized when a strained-Si/SiGe emitter is incorporated.