Current challenges in traditional design verification and its application in flip-chip devices
The acceleration of new developments in semiconductor design and manufacturing technology in keeping up with Moore's Law has introduced significant new challenges for device designers as well as manufacturing organizations. Short channel effects, multi-level interconnect cross talk problems, and new materials such as low K dielectric, copper, and silicon on insulator have made modeling and simulation of semiconductor devices and processes extremely difficult. Many times this results in failure to meet performance targets in first silicon introduction. The high cost of mask sets, together with the opportunity costs related to time-to-market, drives the need for shorter and fewer redesign cycles, making effective transistor level design debug a necessity. To make things even more difficult, the transition to flip chip packaging and multiple interconnect metal layers makes backside probing the only effective way to perform node level analysis. This paper describes these new challenges in detail, and the use of photon probing technology as an effective way to address them. The use of a time resolved photon emission microscope allows measuring performance at the critical node level. This is done by collecting the photons, emitted by carriers that are accelerated in the pinch off region during CMOS transistor switching. This enables optimization of device speed paths, and resolution of problems such as race conditions and contentions, encountered during design debug and failure analysis cycles.