Properties of Self Timed Ring Architectures for Deadlock Free and Consistent Configuration Reaching Maximum Throughput
Multiprocessor System on Chip with self ti med design becomes increasingly attractive due to its ability to exploit high parallelism of applications. Previous research efforts on self timed techniques mostly focused on hardware layer. However, the problem of correctly synthesizing self timed systems remains to be difficult. In particular, the problem of how to configure a self timed ring structure to achieve the maximal throughput with no deadlock is still unsolved. Self timed ring (STR) is composed of a ring of connected "stages" each consisting of a processing element, communication units and its current state. The correct configuration of STR is determined by the initial state of each stage and a number of inserted buffers into the ring to maintain correct behavior of applications on an STR. This paper establishes a series of theorems based on the understanding of properties of self timed structures. Based on the theorems, the setting of initial states and buffers can be decided to guarantee correct configuration. Our theorem also establishes mathematical formulas to calculate throughput of an STR. The algorithms presented in the paper find the optimal initial configuration of an STR that achieves the maximum throughput with the minimum number of inserted buffers. The experimental results show that the throughput of applications mapped on STR with the optimal configuration is improved by 64.99 on average compared with synchronous system.
J. Signal Process. Syst.