MASI: An eviction aware cache coherence protocol for CMPs
This work proposes a novel 4 state cache coherence protocol that ensures better efficiency in Chip Multiprocessors (CMPs) compared to that of conventional 4 and 5 state protocols, e.g. MESI/MOESI. The proposed MASI coherence protocol realizes judicious cache line state transition that has considerable impact on the reduction in number of data block forwarding. Its feature is to keep trace of the eviction of data block from the upper level cache. It further brings down the overhead of writeback. The simulation results establish the effectiveness of the MASI protocol for a directory based system that is conventionally employed for large scale CMPs.
2016 Sixth International Symposium on Embedded Computing and System Design (ISED)