Low complexity hardware architecture of traffic sign recognition with IHSL color space for advanced driver assistance systems
This paper presents novel hardware architecture with low complexity color conversion scheme and parallel processing of red region detection for the applications of automatic traffic sign detection system. By the inherent parallelism of the various red region detections, we designed a fully pipelined architecture implemented on the FPGA platform. The proposed architecture enables a real time traffic sign recognition (TSR) processing for a full HD video (2 Mega pixels) at 60 frames per second.
2016 IEEE International Conference on Consumer Electronics Asia (ICCE Asia)