Vertically stacked NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain
We report on vertically stacked horizontal Si NanoWires (NW) MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked NWs transistors are integrated with inner spacers and SiGe source drain (S/D) stressors. Recessed and epitaxially re grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si/ channels. The Precession Electron Diffraction (PED) technique, with a nm scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short channel characteristics are demonstrated in stacked NWs FETs.
2016 IEEE International Electron Devices Meeting (IEDM)