HDL Implementation of an Efficient Partial Parallel LDPC Decoder Using Soft Bit Flip Algorithm
Nowadays Low Density Parity Check Codes (LDPC) is more in demand in Wireless Communication Systems due to its excellent performance. Use of LDPC code for encoding and decoding purposes found to be more reliable and highly efficient data transfer over wide bandwidth in presence of corrupting noise. Various Algorithms were used to interpret LDPC codes. Out of which Sum Product Algorithm and Min Sum Algorithm are very much complicated because of their high interconnection complexity, high memory requirement, high variable and check node column degree but their error correcting performance is best as compared to other decoding algorithms. Bit flipping algorithms have lower interconnection complexity because it require only small amount of simple computations. We have used soft bit flip algorithm for decoding which uses advantages of both sum product algorithm and bit flip algorithm. Therefore, soft bit flip algorithm reduces the interconnection complexity and its error correction performance is near to min sum and sum product decoding algorithms. VLSI architecture of Soft Bit Flip Algorithm based Decoder is proposed which uses the value reuse property of Bit Flip Algorithm results in high throughput. The 64 bits half code rate LDPC decoder is designed using Xilinx xc5vlx110t 2ff1136 FPGA device. The calculated decoding throughput is 1.13 Gbps. The pipelining system used in LDPC decoder architecture results in enhanced decoding throughput.The proposed work has been implemented and synthesized using Xilinx ISE 14.7 and Virtex 5 Field Programming Gate Array.