7.2 4Mb STT MRAM based cache with memory access aware power optimization and write verify write read modify write scheme
Two performance gaps in the memory hierarchy, between CPU cache and main memory, and main memory and mass storage, will become increasingly severe bottlenecks for computing system performance. Although it is necessary to increase memory capacity to fill these gaps, power also increases when conventional volatile memories are used. A new nonvolatile memory for this purpose has been anticipated. Storage class memory is used to fill the second gap. Many candidates exist: ReRAM, PRAM, and 3D cross point type with resistive change RAM. However, nonvolatile last level cache (LLC) is used to fill the first gap. Advanced STT MRAM has achieved sub 4ns read and write accesses with perpendicular magnetic tunnel junctions (p MTJ) [1 2] Furthermore, mature integration processes have been developed and 8Mb STT MRAM with sub 5ns operation has shown high reliability [3] Moreover, because of its non volatility, STT MRAM can reduce operation energy by more than 81% compared to SRAM for cache [1] This paper presents STT MRAM based last level cache memory (LLC) including MRAM memory core, peripherals and cache logic circuits, using novel power optimization with high speed power gating (HS PG),considering processor architectures and cache memory accesses. The STT MRAM based cache has high reliability to reduce the write error rate with novel write verify write. Furthermore, a read modify write scheme is implemented to reduce active power without penalty. Figure 7.2.1 presents a block diagram of a 4Mb STT MRAM based cache.
2016 IEEE International Solid State Circuits Conference (ISSCC)