Vertical architecture for enhancement mode power transistors based on GaN nanowires
The demonstration of vertical GaN wrap around gated field effect transistors using GaN nanowires is reported. The nanowires with smooth a plane sidewalls have hexagonal geometry made by top down etching. A 7 nanowire transistor exhibits enhancement mode operation with threshold voltage of 1.2 V, on/off current ratio as high as 108, and subthreshold slope as small as 68 mV/dec. Although there is space charge limited current behavior at small source drain voltages (Vds) the drain current (Id) and transconductance (gm) reach up to 314 mA/mm and 125 mS/mm, respectively, when normalized with hexagonal nanowire circumference. The measured breakdown voltage is around 140 V. This vertical approach provides a way to next generation GaN based power devices.