On the effectiveness of accelerating MapReduce functions using the Xilinx Vivado HLS tool
Programming FPGAs requires advanced hardware design skills which limits their adoption in data centres. FPGA vendors have provided high level synthesis HLS tools to build register transfer level RTL specifications from designs provided in high level languages. We present a suite of C and C+ based hardware accelerators for the Purdue MapReduce benchmark suite and use the Xilinx Vivado HLS tool to compare their performance and resource efficiency to hand coded RTL code. We show that simple design changes in the high level language based accelerators can improve results. Using Vivado HLS, five benchmarks match the performance of hand optimised RTL while sort, self join, adjacency list and word count algorithms are about 4.7x, 3x, 2x and 1.3x slower, respectively.
Int. J. High Perform. Syst. Archit.