Glitch Energy Reduction and SFDR Enhancement Techniques for Low Power Binary Weighted Current Steering DAC
This brief proposes a glitch reduction approach by dynamic capacitance compensation of binary weighted current switches in a current steering digital to analog converter (DAC) The method was proved successfully by a 10 bit 400 MHz pure binary weighted current steering DAC with a minimum number of retiming latches. The experiment results yield very low glitch energy during major carry transitions at output, which is ;1 pVs. This brief utilizes a layout structure to improve the spurious free dynamic range at high signal frequencies. This chip was implemented in a standard 0.18 mm CMOS technology and consumes 20.7 mW at 400 MS/s.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems