Single Ended Schmitt Trigger Based Robust Low Power SRAM Cell
This paper presents a Schmitt trigger based single ended 11T SRAM cell, which significantly improves read and write static noise margin (SNM) and consumes low power. Simulation results show that the cell also achieves the lowest leakage power dissipation among the cells considered for comparison. We also investigate the impact of process, voltage, and temperature variations on various performance parameters, such as hold SNM, read SNM, write margin, immunity to half select issue, ION/IOFF ratio of read path, and leakage power of the cell; Monte Carlo simulation results confirm the robustness of the proposed cell toward these issues. Layout drawn in a 45 nm technology rule shows that the proposed cell occupies 2.02x greater area as compared with 6T SRAM cells. However, 6.9x higher ION/IOFF ratio of the read path of the proposed cell as compared with 6T cell holds potential to significantly subside the area overhead. A new figure of merit that comprehensively captures stability, delay, power dissipation, and area of an SRAM cell is also proposed. Based on the proposed metric, we observe that the proposed cell outperforms all, but one of the SRAM cells considered in this paper.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems