Vivado HLS based implementation of a fall detection decision core on an FPGA platform
New ultra low power FPGAs provide system designers the flexibility to create completely customizable low power solutions to bring new classes of applications to life. Fall detection is one of the major problems the elderly population is facing. This paper aims to present the design of an heterogeneous wearable system built with Zynq System On Chip (SoC) for fall detection. The design has been validated on ARM A9 processor for the software side and using Vivado High Level Synthesis (HLS) for hardware implementation on a Zynq 7010 SoC. The implementation results of the fall detection core showed less power consumed and 50% less on chip logic resources used compared to the software implementation.
2016 11th International Design Test Symposium (IDT)