Digital LDO modeling for early design space exploration
Digital low dropout (LDO) voltage regulators have been widely used in the latest low power circuits that involve fine grain power management. Due to the mixture of discrete and continuous time operation as well as the nonlinear comparator gain, it is difficult to derive the closed loop transfer function for a digital LDO. The use of its open loop transfer function is also limited due to the non constant feedback factor. Thus, it is not easy to predict digital LDO performance in the early design stage, which limits designer's capability to effectively explore the design space. This paper presents closed form expressions for estimating critical performance parameters of digital LDO circuits, such as settling time and peak control error. The accuracy of the predictions is validated by comparing with circuit simulation results. The derived formulas can be used by designers or integrated into design automation tools.
2016 29th IEEE International System on Chip Conference (SOCC)