Next generation copper pillar plating technologies
s t h e i n d u s t r y m o v e s t owards sma l l e r, f a s t e r devices, there is mounting pressure on all members of the supply chain to enable higher performance at lower cost. The limitations of Moore's Law are becoming more evident as advanced technology nodes are no longer providing a significant cost benefit. R&D investments in next generation sub 10nm node lithography tools are becoming increasingly expensive and perhaps are no longer the viable solution for improving cost effectiveness. As a result, the industry has shifted its focus to advanced packaging as a means for providing better performance and lowering costs, following the socalled "More than Moore" approach. There are three primary drivers for this shift: improved performance, more functionality, and cost reduction. This article will discuss how these three drivers have led to the emergence of flip chip packaging using pillars and the current and future challenges for Cu pillar technology. Various packaging technologies have been tested for their ability to provide substantial technical advantages while reducing the overall production flow and minimizing manufacturing costs. Currently, the preferred packaging t e c h n o l o g y f o r s u b 4 5 n m n o d e technologies is flip chip because of its ability to offer a significantly improved I/O density and minimized footprint compared to standard wire bonding, as well as better thermal and electrical performance. Flip chip technology is relatively inexpensive compared to other emerging packaging technologies and currently accounts for approximately 16% of the 200mm packaging market, according to industry reports. Many of the key players in the packaging industry already utilize flip chip in high volume manufacturing and the five year forecast is promising, showing steady growth for flip chip across all market segments with the most substantial growth in the consumer electronics sector. During the flip chip process, the die is flipped over and connected to the substrate prior to being packaged. Connect ion is possible by var ious applications but the primary two are soldering or using pillars. Flip chip ball grid array (BGA) which used SnAg solder balls to connect the chip to the substrate, has been the preferred method in the past but is slowly being surpassed by Cu pillar. The two methods of soldering, paste printing and micro ball placement, have their own set of limitations, namely the resolution of the printing equipment and the slow and costly micro ball placement process. For the most advanced technology nodes, Cu pillar is the preferred application for the first layer interconnect process and will account for the majority of future growth in the flip chip market segment.