Finite State Machines
Finite state machine (FSM) is source synchronous sequential designs where every register is triggered on the active edge of clock. The two types of state machines are Moore and Mealy. This chapter discusses about the efficient and synthesizable FSM coding using Verilog RTL. The key differences between the Moore and Mealy machines as well as different FSM encoding styles are discussed in detail. This chapter illustrates the Verilog RTL examples with the multiple 'always' blocks to represent the efficient state machines. This chapter also focuses on the do's and don'ts while coding FSM. The FSM design performance improvement with the key guidelines is also described in this chapter.