Integer N phase locked loop for bluetooth receiver in CMOS 130 nm technology
The paper presents an Integer N phase locked loop (PLL) for Bluetooth receiver implemented in CMOS 130 nm technology. The presented phase locked loop consists of an LC quadrature voltage controlled oscillator with capacitor bank, a tri state phase frequency detector with charge pump, a third order passive filter and a programmable divider. The PLL has a supply voltage of 1.2 V and dissipates 2.4 mW. The output frequency range of the phase locked loop is from 2.2 GHz to 2.8 GHz and phase noise is equal 124 dBm/Hz at 3 MHz from carrier frequency.
2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS)