Taming Non Blocking Caches to Improve Isolation in Multicore Real Time Systems
In this paper, we show that cache partitioning does not necessarily ensure predictable cache performance in modern COTS multicore platforms that use non blocking caches to exploit memory level parallelism (MLP) Through carefully designed experiments using three real COTS multicore platforms (four distinct CPU architectures) and a cycle accurate full system simulator, we show that special hardware registers in non blocking caches, known as Miss Status Holding Registers (MSHRs) which track the status of outstanding cache misses, can be a significant source of contention; we observe up to 21X WCET increase in a real COTS multicore platform due to MSHR contention. We propose a hardware and system software (OS) collaborative approach to efficiently eliminate MSHR contention for multicore real time systems. Our approach includes a low cost hardware extension that enables dynamic control of per core MLP by the OS. Using the hardware extension, the OS scheduler then globally controls each core's MLP in such a way that eliminates MSHR contention and maximizes overall throughput of the system. We implement the hardware extension in a cycle accurate fullsystem simulator and the scheduler modification in Linux 3.14 kernel. We evaluate the effectiveness of our approach using a set of synthetic and macro benchmarks. In a case study, we achieve up to 19% WCET reduction (average: 13% for a set of EEMBC benchmarks compared to a baseline cache partitioning setup.
2016 IEEE Real Time and Embedded Technology and Applications Symposium (RTAS)