Bidirectional multi level spatial coded exposure CMOS capacitive TIA pixel design
Over the last decade, computational cameras have demonstrated superior performance in a variety of applications. Currently, optical encoding is implemented using components that are typically not integrated on the image sensor chip. This results in camera systems with large physical sizes, performance compromises, and implementation challenges, particularly in applications where size and power are constrained. In this paper, we propose a complementary metal oxide semiconductor (CMOS) pixel structure with bidirectional multi level spatial coded exposure encoding capability for computational imaging. Based on a capacitive transimpedance amplifier (CTIA) core, the proposed pixel architecture achieves bidirectional multi level optical encoding, and is compatible with monolithic CMOS implementation. Designed and laid out in a standard 0.13 pm CMOS process, the pixel occupies an area of 13.8 pm x 13.8 pm with a fill factor of 30%
2016 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC)