A delay variation and floorplan aware high level synthesis algorithm with body biasing
In this paper, we propose a delay variation and floorplan aware high level synthesis algorithm with body biasing, which minimizes the average leakage energy of manufactured chips. To realize a floorplan oriented high level synthesis, we utilize a huddle based distributed register architecture (HDR architecture) one of the DR architectures. HDR architecture divides the chip area into small partitions called a huddle and we can control a body bias voltage for every huddle. During high level synthesis, we iteratively obtain expected leakage energy for every huddle when applying a body bias voltage. A huddle with smaller expected leakage energy contributes to reducing expected leakage energy of the entire circuit but can increase the latency. We assign CDFG nodes in critical paths to the huddles with larger expected leakage energy and those in non critical paths to the huddles with smaller expected leakage energy. We expect to minimize the entire leakage energy in a manufactured chip without increasing its latency. Experimental results show that our algorithm reduces the average leakage energy by up to 38.9% without latency and yield degradation compared with typical case design with body biasing.
2016 17th International Symposium on Quality Electronic Design (ISQED)