Analysis and improvement of ramp gain error in single ramp single slope ADCs for CMOS image sensors
Abstract The single ramp single slope (SRSS) analog to digital converter (ADC) is a promising candidate for column parallel architectures. This paper, for the first time, quantitatively analyzes the ramp gain error in the ramp input stage (RIS) that is the crucial component in such ADC, and verifies it using behavior model simulation. Then, a novel active RIS is proposed to alleviate the ramp gain error. With an active feedback loop, the ramp gain becomes a product of two reciprocal ratios of capacitance, whose departure from unity is attributed to the relative deviations rather than the absolute values in the conventional passive RIS. The proposed concept is designed and verified by simulations in a 0.18 mm CMOS process.
Microelectron. J.