Assessing CPA resistance of AES with different fault tolerance mechanisms
Countermeasures for Advanced Encryption Standard (AES) to thwart side channel attack and fault attack are typically investigated in a separate fashion. There is lack of thorough investigation on how one countermeasure specifically for one attack affects the efficiency of another attack. In this work, we consider three different fault detection (FD) methods double modular redundancy (DMR) inverse function (inverse) and even parity check code (parity) We perform FPGA based systematic analysis to investigate the impact of FD schemes on the correlation power analysis (CPA) resistance of a complete AES implementation. Moreover, the power model used in the existing work is Hamming weight rather than the powerful Hamming distance one. Our experimental results show that, in some scenarios, the use of fault detection mechanisms in AES improves the resistance against CPA. For instance, applying a parity FD to the AES's S Box makes it harder to retrieve the key than the case without any FD protection.
2016 21st Asia and South Pacific Design Automation Conference (ASP DAC)