A 12 Bit 2 GS/s Dual Rate Hybrid DAC With Pulse Error Pre Distortion and In Band Noise Cancellation Achieving 74 dBc SFDR and 80 dBc IM3 up to 1 GHz in 65 nm CMOS
This paper presents a 12 bit 2 GS/s dual rate hybrid DAC using bandwidth and linearity enhancement techniques. The proposed pulsed error pre distortion scheme enhances DAC linearity at both low and high signal frequencies by leveraging the fine time and voltage resolution from the oversampling path of the hybrid DAC structure. To further widen the DAC bandwidth, a noise cancellation scheme is proposed to suppress the quantization noise of the delta sigma modulator within DC to the 1 GHz band without increasing modulator complexity. The analytical derivations and numerical simulations of the proposed techniques are provided to demonstrate the technique's effectiveness, as well as its practical design constraints. A proof of concept silicon prototype is implemented in 65 nm standard CMOS that achieves SFDR of 74 98 dBc over the DC 1GHz Nyquist band. In a two tone measurement, the IM3 product is measured from 101 dBc to 80 dBc across the Nyquist band. The SFDR improvement after enabling the proposed pulsed pre distortion scheme measures from 67.5 to 74.4dBc, while the in band noise floor demonstrates 6 dB suppression at the Nyquist band edge after enabling the noise cancellation scheme.
IEEE Journal of Solid State Circuits