27.2 an oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS
The successive approximation register (SAR) architecture is well known for its high power efficiency in medium resolution A/D conversions. Together with time interleaving, it can challenge the regime of flash ADCs in high speed, low resolution applications [1] However, when considered for high precision, low speed sensor readout interfaces, SAR ADCs suffer from nonlinearity resulting from capacitor mismatch and limited dynamic range due to comparator noise. Previous works [2 3] adopt oversampling to shift noise and nonlinearity into high frequencies. Dithering and chopping are used in [2] to modulate harmonic distortion and flicker noise out of signal bandwidth, achieving an in band SFDR of 87.1dB and an SNDR of 79.1dB along with data driven noise reduction. Noise shaping proposed in [3] suppresses the in band noise around 10dB at a low oversampling ratio (OSR) of 4 with no linearity improvement. DAC nonlinearity can also be calibrated digitally, but to achieve an INL down to 2ppm [4] calibration of capacitor 2nd order voltage coefficients is required. This work presents a DAC mismatch error shaping (MES) scheme for oversampling SAR ADCs to achieve a 105dB in band SFDR without calibration. The DAC mismatch errors are 1st order high pass filtered by simply inserting one extra phase into the SAR operation. Noise shaping is adopted to suppress the comparator thermal and flicker noise. The prototype achieves a peak SNDR of 101dB over 1kHz bandwidth with a Schreier FOM of 178.9dB and can be configured to conventional SAR mode up to 5MS/s. The proposed techniques enable the application of power efficient SAR ADCs for high precision, multi purpose sensor readout interfaces.
2016 IEEE International Solid State Circuits Conference (ISSCC)