Hybrid CMOS OxRAM based 4T 2R NVSRAM with efficient programming scheme
In this paper, we present an OxRAM based compact 4T 2R NVSRAM design with a novel efficient programming scheme to achieve low power and low area footprint. 3 nm thick HfOx based OxRAM devices and 90 nm CMOS technology node were used for all simulations. Our proposed 4T 2R NVSRAM is programmed using a two cycle write process and is implemented for real time non volatility rather than last bit, or power down non volatility. We also show that by carefully choosing the OxRAM programmed resistance levels the pull down NMOS transitor size, and NVSRAM programming energy can be further reduced by a factor of 3x and 4x respectively.
2016 16th Non Volatile Memory Technology Symposium (NVMTS)