The runahead network on chip
With increasing core counts and higher memory demands from applications, it is imperative that networks on chip (NoCs) provide low latency, power efficient communication. Conventional NoCs tend to be over provisioned for worst case bandwidth demands leading to ineffective use of network resources and significant power inefficiency; average channel utilization is typically less than 5% in real world applications. In terms of performance, low latency techniques often introduce power and area overheads and incur significant complexity in the router microarchitecture. We find that both low latency and power efficiency are possible by relaxing the constraint of lossless communication. This is inspired from internetworking where best effort delivery is commonplace. We propose the Runahead NoC, a lightweight, lossy network that provides single cycle hops. Allowing for lossy delivery enables an extremely simple bufferless router microarchitecture that performs routing and arbitration within the same cycle as link traversal. The Runahead NoC operates either as a power saver that is integrated into an existing conventional NoC to improve power efficiency, or as an accelerator that is added on top to provide ultra low latency communication for select packets. On a range of PAR SEC and SPLASH 2 workloads, we find that the Runahead NoC reduces power consumption by 1.81 as a power saver and improves runtime and packet latency by 1.08x and 1.66x as an accelerator.
2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)