Threshold Voltage Instabilities of Present SiC Power MOSFETs under Positive Bias Temperature Stress
We study the threshold voltage (Vth) instability of commercially available silicon carbide (SiC) power MOSFETs or prototypes from four different manufacturers under positive bias temperature stress (PBTS) A positive bias near the Vth causes a threshold voltage shift of 0.7 mV per decade in time per nanometer oxide thickness in the temperature range between 50 degC and 150 degC. Recovery at +5 V after a 100 s +25 V gate pulse causes a recovery between 1.5 mV/dec/nm and 1.0 mV/dec/nm at room temperature and is decreasing with temperature. All devices show similar stress, recovery and temperature dependent behavior indicating that the observed Vth instabilities are likely a fundamental physical property of the SiC SiO2 system caused by electron trapping in near interface traps. It is important to note that the trapping is not causing permanent damage to the interface like H bond breakage in silicon based devices and is nearly fully reversible via a negative gate bias.