An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS
The successive approximation register (SAR) architecture is well known for its high power efficiency in medium resolution analog to digital converters (ADCs) However, when considered for high precision applications, SAR ADCs suffer from non linearity resulting from capacitor mismatch and limited dynamic range due to comparator noise. This work presents a mismatch error shaping (MES) technique for oversampling SAR ADCs to achieve 105 dB in band SFDR without calibration. The capacitor mismatch error is first order high pass filtered by simply delaying the reset of LSB capacitor array after sampling. The comparator thermal and flicker noise are also first order shaped to high frequencies by noise shaping. The prototype in 55 nm CMOS occupies 0.072 mm2 and achieves a peak SNDR of 101 dB over 1 kHz bandwidth. It consumes 15.7 mW from a 1.2 V supply at 1 MS/s and can be configured to Nyquist mode up to 5 MS/s. These features enable the application of SAR ADCs in high precision, multi purpose sensor readout interfaces.
IEEE Journal of Solid State Circuits