Energy efficient FPGA Implementation of the k Nearest Neighbors Algorithm Using OpenCL
Modern SoCs are getting increasingly heterogeneous with a combination of multi core architectures and hardware accelerators to speed up the execution of computeintensive tasks at considerably lower power consumption. Modern FPGAs, due to their reasonable execution speed and comparatively lower power consumption, are strong competitors to the traditional GPU based accelerators. High level Synthesis (HLS) simplifies FPGA programming by allowing designers to program FPGAs in several high level languages e.g. C/C+ OpenCL and SystemC. This work focuses on using an HLS based methodology to implement a widely used classification algorithm i.e. k nearest neighbor on an FPGA based platform directly from its OpenCL code. Multiple fairly different implementations of the algorithm are considered and their performance on FPGA and GPU is compared. It is concluded that the FPGA generally proves to be more power efficient as compared to the GPU. Furthermore, using an FPGA specific OpenCL coding style and providing appropriate HLS directives can yield an FPGA implementation comparable to a GPU also in terms of execution time. Keywords kNN; FPGA; High Level Synthesis; Hardware Acceleration; low power low energy computation; Parallel Computing; OpenCL.
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