A machine learning classifier implemented in a standard 6T SRAM array
This paper presents a machine learning classifier where the computation is performed within a standard 6T SRAM array. This eliminates explicit memory operations, which otherwise pose energy/performance bottlenecks, especially for emerging algorithms (e.g. from machine learning) that result in high ratio of memory accesses. We present an algorithm and prototype IC (in 130nm CMOS) where a 128x128 SRAM array performs storage of classifier models and complete classifier computations. We demonstrate a real application, namely digit recognition from MNIST database images. The accuracy is equal to a conventional (ideal) digital/SRAM system, yet with 113x lower energy. The approach achieves accuracy >95% with a full feature set (i.e. 28x28=784 image pixels) and 90% when reduced to 82 features (as demonstrated on the IC due to area limitations) The energy per 10 way digit classification is 633pJ at a speed of 50MHz.
2016 IEEE Symposium on VLSI Circuits (VLSI Circuits)