Low power data aware STT RAM based hybrid cache architecture
Static Random Access Memories (SRAMs) occupy a large area of today's microprocessors, and are a prime source of leakage power in highly scaled technologies. Low leakage and high density Spin Transfer Torque RAMs (STT RAMs) are ideal candidates for a power efficient memory. However, STT RAM suffers from high write energy and latency, especially when writing `one' data. In this paper we propose a novel data aware hybrid STT RAM/SRAM cache architecture which stores data in the two partitions based on their bit counts. To exploit the new resultant data distribution in the SRAM partition, we employ an asymmetric low power 5T SRAM structure which has high reliability for majority `one' data. The proposed design significantly reduces the number of writes and hence dynamic energy in both STT RAM and SRAM partitions. We employed a write cache policy and a small swap memory to control data migration between cache partitions. Our evaluation on UltraSPARC III processor shows that utilizing STT RAM/6T SRAM and STT RAM/5T SRAM architectures for the L2 cache results in 42% and 53% energy efficiency, 9.3% and 9.1% performance improvement and 16.9% and 20.3% area efficiency respectively, with respect to SRAM based cache running SPEC CPU 2006 benchmarks.
2016 17th International Symposium on Quality Electronic Design (ISQED)