Ultra Low Energy Relaxation Oscillator With 230 fJ/cycle Efficiency
An ultra low energy oscillator circuit is presented for use in picowatt level systems. The core oscillator uses an 18 transistor 3 stage architecture designed to minimize short circuit current. In addition, a transistor threshold is used to set the trip point as opposed to a voltage reference and comparator scheme, leading to overall energy savings. While operating across a wide range of low frequencies from 18 to 1000 Hz, the oscillator core consumes 110 fJ/cycle at 0.6 V. The circuit is demonstrated alongside an integrated current source to set the reference frequency. The combined system consumes a total power of 4.2 pW at 18 Hz, resulting in 230 fJ/cycle at 0.6 V.
IEEE Journal of Solid State Circuits