Low power design practices for power optimization at the logic and architecture levels for VLSI system design
Reduction of power consumption in battery powered and portable VLSI systems has become an important aspect in system design. The various sources of power dissipation have been discussed in this paper. Opportunities for power optimization and tradeoffs emphasizing low power are available across the entire design hierarchy through different levels including technology, layout, circuit, logic, architecture, software and system levels. A review of low power techniques applied at logic and architecture levels of the design hierarchy has been presented in detail in this paper, with some of the design decisions made for the implementation of VLSI system.
2016 International Conference on Energy Efficient Technologies for Sustainability (ICEETS)