A bitline driven 1T 1C DRAM readout scheme
In this paper, a novel readout scheme for the one transistor one capacitor (1T 1C) DRAM will be introduced. The scheme depends on charging the bitline as well as the cell storage capacitance to a certain level and comparing the charging current with a reference current to disclose the stored data. The factors affecting the sense margin will be discussed. The proposed readout scheme will be verified with simulation using the 45 nm CMOS technology. The proposed scheme achieves 80% and 67% reductions in the average read cycle time and the average power delay product, respectively.
2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)