Dynamically reconfigurable system for LVQ based on chip learning and recognition
Artificial neural networks implement a simplified model of the human brain and thus specialize on pattern recognition. As an alternative to conventional single instruction multiple data (SIMD) solutions with massive parallelism for self organizing map (SOM) neural network models, we report resource efficient hardware architecture for 1 chip implementation of the learning vector quantization (LVQ) neural network algorithm, which is a variant of SOM. Dynamic configurability for two operation modes is realized through the same circuitry for recognition based on nearest neighbor matching and on chip learning based on error back propagation. Switching between learning and recognition modes is carried out by a pipeline with multiplexers and parallel p word input (P MPPI) The multiplexers enable data flow path reconfiguration, resulting in a significant reduction of area and power consumption. Thus, the P MPPI architecture achieves time domain multiplexing between operation modes as well as area/energy efficiency by reusing both memory arrays and arithmetic or logic units. Additionally, high flexibility for feature vector dimension and reference vector number allows the implementation of many different applications, including continuously adaptive neural systems, on the same hardware platform. A test chip in TSMC 65 nm CMOS has parallel 32 word inputs, 585 K bit on chip memory, and achieves high processing throughput of 76.8 Gbps and low power consumption of 27.92 mW (at 150 MHz, 1.0 V supply voltage)
2016 IEEE International Symposium on Circuits and Systems (ISCAS)