High Frequency Unity Gain Buffer in 90 nm CMOS Technology
A new unity gain buffer architecture is presented for on chip CMOS mixed signal applications. The proposed two stage common source active load (CSAL) buffer with source feedback offers improved performance compared to previously published source follower and source coupled differential pair based unity gain buffers. A 90 nm CMOS design (Vdd equals 1.2V) of the buffer has the following performance parameters. With Cin/CL of 10 fF/250 fF, f 3dB is 4.4GHz, low frequency gain is 0.16dB, maximum input range within 2% gain variation is 260mV, total harmonic distortion (THD) is 63.3dB, offset error (input offset minus output offset) is 26mV, and 1.06mW power consumption. The active load, low gain amplifiers eliminate stability issues and any need for compensation capacitors. The architecture facilitates a relatively large input/output voltage swing while keeping transistors operating in the saturation region, making it suitable for submicron technologies with low rail voltages.
J. Circuits Syst. Comput.