Two advanced energy back SAR ADC architectures with 99.21 and 99.37 reduction in switching energy
This letter presents novel energy efficient switching schemes for a successive approximation register analog to digital converter. The new switch method consumes no switching energy in the first three comparison cycles. The average switching energy is reduced by 99.21 and 99.37 for the signal independent and signal dependent common mode voltage at the comparator, respectively. A 75 reduction in the total capacitance over the conventional scheme is also achieved. The variation of the common mode voltage at the comparator input in the proposed architecture is 50 less than in other low power switching schemes.