High efficiency video coding
In the family of video coding standards, HEVC has the promise and potential to replace/supplement all the existing standards (MPEG and H.26x series including H.264/AVC) While the complexity of the HEVC encoder is several times that of the H.264/AVC, the decoder complexity is within the range of the latter. Researchers are exploring about reducing the HEVC encoder complexity Kim et al have shown that motion estimation (ME) occupies 77 81% of HEVC encoder implementation. Hence the focus has been in reducing the ME complexity. Several researchers have implemented performance comparison of HEVC with other standards such as H.264/AVC, MPEG 4 Part 2 visual, H.262/PEG 2 Video, H.263, and VP9 and also with image coding standards such as JPEG2000, JPEG LS, and JPEG XR. Several tests have shown that HEVC provides improved compression efficiency up to 50% bit rate reduction for the same subjective video quality compared to H.264/AVC. Besides addressing all current applications, HEVC is designed and developed to focus on two key issues: increased video resolution up to 8kx4k and increased use of parallel processing architecture. Brief description of the HEVC is provided. However for details and implementation, the reader is referred to the JCT VC documents, overview papers, keynote speeches, tutorials, panel discussions, poster sessions, special issues, test models (TM/HM) web/ftp site, open source software, test sequences, anchor bit streams and the latest books on HEVC. Also researchers are exploring transcoding between HEVC and other standards such as MPEG 2 and H.264. Further extensions to HEVC are scalable video coding (SVC) 3D video/multiview video coding and range extensions which include screen content coding (SCC) bit depths larger than 10 bits and color sampling of 4:2:2 and 4:4:4. SCC in general refers to computer generated objects and screen shots from computer applications (both images and videos) and may require lossless coding. Some of these extensions have been finalized by the end of 2014 (time frame for SCC is late 2016) They also provide fertile ground for R D. Iguchi et al have already developed a hardware encoder for super hi vision (SHV) i.e. ultra HDTV at 7680x4320 pixel resolution. Also real time hardware implementation of HEVC encoder for 1080p HD video has been done. NHK is planning SHV experimental broadcasting in 2016. A 249 Mpixel/s HEVC video decoder chip for 4k Ultra HD applications has already been developed. Bross et al have shown that real time software decoding of 4K (3840x2160) video with HEVC is feasible on current desktop CPUs using four CPU cores. They also state that encoding 4K video in real time on the other hand is a challenge. Multimedia research group (MRC) predicts 2 billion HEVC based devices by end of 2016.
2016 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA)