Implementation of FIR filter as per DO 254 compliance
Implementation of filter needs mainly three basic building blocks as multiplier, adder and signal delay. If a filter has to be speed means it should have high speed basic building block i.e. multiplier and adder blocks should be very high speed. The paper presents a proposed digital FIR filter which is delay efficient and area efficient. The improvement of proposed Direct Form FIR filter in delay is of 11% and 26% of area has been decreased. The design has been implemented in Verilog according to the DO 254 compliance guidelines, simulated in industrial standard simulator Questasim and synthesized using Precision synthesis RTL plus and Xilinx ISE. DO 254 compliance is done using HDL Designer tool suite.
2016 International Conference on Emerging Technological Trends (ICETT)