Abnormal positive bias stress instability of In Ga Zn O thin film transistors with low temperature Al2O3 gate dielectric
Low temperature atomic layer deposition (ALD) was employed to deposit Al2O3 as a gate dielectric in amorphous In Ga Zn O thin film transistors fabricated at temperatures below 120 degC. The devices exhibited a negligible threshold voltage shift (DVT) during negative bias stress, but a more pronounced DVT under positive bias stress with a characteristic turnaround behavior from a positive DVT to a negative DVT. This abnormal positive bias instability is explained using a two process model, including both electron trapping and hydrogen release and migration. Electron trapping induces the initial positive DVT, which can be fitted using the stretched exponential function. The breakage of residual AlO H bonds in low temperature ALD Al2O3 is triggered by the energetic channel electrons. The hydrogen atoms then diffuse toward the In Ga Zn O channel and induce the negative DVT through electron doping with power law time dependence. A rapid partial recovery of the negative DVT after stress is also observed during re.