A Low Noise, Low Power Phase Locked Loop, Using Optimization Methods
A divider less, low power, and low jitter phase locked loop (PLL) is presented in this paper. An extra simple open loop phase frequency detector (PFD) is proposed which reduces the power consumption and increases the overall speed. A novel bulk driven Wilson charge pump circuit, whose performance is enhanced by some optimization algorithms, is also introduced to get high output swing and high current matching. The designed PLL is utilized in a 0.18zzm CMOS process with a 1.8zV power supply. It has a wide locking range frequency of 500zMHz to 5zGHz. In addition, through the use of a dead zone less PFD and a divider less PLL, the overall jitter is decreased significantly.
J. Electr. Comput. Eng.