Enhanced slew rate, constant gm rail to rail OpAmp using 1:2 current mirror biasing technique
A constant gm, rail to rail operational amplifier circuit topology is presented in this paper. The amplifier input stage is realized using single NMOS pair at 0.13mm bulk CMOS process technology. The overall gain variation is within the range of 2.338% for the rail to rail common mode input range. The proposed design is able to reject the common mode input response with 115dB of common mode rejection ratio (CMRR) High slew rate is achieved and the simulated value is +19/ 43 (V/ms) of an unity gain buffer op amp at 5pF of CL. The variation in overall gm and gain are also simulated at different corner temperatures. The circuit simulation is done in Tanner EDA at 1.8 V of power supply which dissipates the power of 6.1mW.
2016 International Conference on Computing, Communication and Automation (ICCCA)