A Low Jitter Fast Locked All Digital Phase Locked Loop With Phase Frequency Error Compensation
The previous fast locked all digital phase locked loop (ADPLL) usually suffers from large timing jitter due to the steep frequency transfer curve of its digitally controlled oscillator (DCO) This paper presents an ADPLL that possesses a coarse frequency selection function. All DCO frequency transfer curves of the ADPLL have gentle slopes. The ADPLL selects one transfer curve before acquisition. To fulfill the fast acquisition requirement, the proposed ADPLL employs the phase frequency error compensation technique. In the acquisition mode, the phase error compensator resolves the problem of phase error accumulation. Meanwhile, the frequency error compensator predicts a proper control code by calculating the cycle time difference between the reference clock and the derived signal fed back from the DCO. Therefore, the proposed ADPLL can compensate for the phase and the frequency errors simultaneously. The experimental results show that the proposed ADPLL possesses a fine tuning acquisition within 5 reference clock cycles. After acquisition, the code updates in a fractional manner in the tracking mode to enhance the tracking jitter performance. The ADPLL output frequency ranges from 860 MHz to 1 GHz. The measured rms jitter is 1.31 ps at 1 GHz frequency.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems