Worst frame backlog estimation in an avionics full duplex switched ethernet end system
With the increase of needs in capability, bandwidth and reliability of modern aeronautical equipment, Avionics Full Duplex Switched Ethernet (AFDX) network has gained in popularity since its successful implementation in the Airbus A380. As AFDX networkis a deterministic network, frames have to reach the reception End System (ES) within a limited amount of time: the upper bound of the end to end delay. Similarly, a frame arriving at the reception ES has to be processed within a deterministic amount of time to be available to host applications. The duration of frame storage in the ES reception buffer represents a significant part of delays. Optimizing the size of the ES reception buffer is then a critical issue, which requires a precise analysis of the Worst Frame Backlog (WFB) This is the issue that we address in this paper. We propose in particular a method to construct the longest sequence of back to back frames from a regular reception flow and a simulation tool to estimate the WFB that helps to determine the size of the ES reception buffer for any configuration.
2016 IEEE/AIAA 35th Digital Avionics Systems Conference (DASC)