Enabling dynamic and partial reconfiguration in Xilinx SDSoC
In the past years dynamic partial reconfiguration (DPR) has been established as a well known technique for systems featuring a field programmable gate array (FPGA) Systems on Chip (SoC) with an ARM processor ease the utilization of DPR and motivate its implementation to make use of the obvious advantages, such as the reduction of area, power and the acceleration of reconfiguring the FPGA. Nonetheless, the development process for SoCs is still a complex and time consuming task, especially for those designs using DPR. Xilinx counters this complexity with the introduction of their new high level tools, namely the SDx Development Environment. The SDSoC Development Environment accelerates the development of designs running on Zynq 7000 devices by only using C/C+ applications as input. Unfortunately, this high level workflow does not incorporate DPR. This paper shows an approach on how to use DPR in Xilinx SDSoC. Thus an application specific design can benefit from both the high level workflow and the advantages of DPR. We show that our approach to DPR in SDSoC accelerates the overall design time and creates a more efficient embedded application. In our use case the dynamic and partial reconfiguration of hardware accelerators takes 10 ms and the hardware related section of our embedded application is accelerated by a factor of 14 due to DPR.
2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)