Fixation Ratio of Error Location Aware Strategy for Increased Reliable Retention Time of Flash Memory
The lifetime of NAND flash is highly restricted by the bit error rate (BER) while error correcting codes (ECC) can provide only limited error correction capability to tolerate increasing bit errors. In this paper, a novel fixation ratio of error locations aware (FRELA) strategy is proposed to prolong the reliable retention time of flash memory. The concept of FRELA is motivated by following two observations obtained from our real hardware experimental platform: first, the increasing trend of average BER with the retention time and the program/erase cycles can be easily modeled; second, there is a great possibility that an error bit of flash memory remains wrong after a certain retention time. The key purpose of FRELA is to flip the corresponding data bits according to the locations recording of error bits prior to operating ECC. By virtue of the BER prediction model, the required storage space of FRELA is effectively reduced because it avoids updating the information of locations frequently. The experimental results show that FRELA can prolong the reliable retention time of 2x nm NAND flash by more than 60% without stronger ECC, while experiencing at most 1.03% degradation in writing speed and 0.79% degradation in reading speed, respectively.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems