4.6 A 65nm CMOS 6.4 to 29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster
Energy efficient computing and ultra low power operation are requirements for many application areas, such as IoT and wearables. While for some applications, integer and fixed point processor instructions suffice, others (e.g. simultaneous localization and mapping SLAM, stereo vision, nonlinear regression and classification) require a larger dynamic range, typically obtained using single/double precision floating point (FP) instructions. Logarithmic number systems (LNS) have been proposed [1,2] as an energy efficient alternative to conventional FP, as several complex operations such as MUL, DIV, and EXP translate into simpler arithmetic operations in the logarithmic space and can be efficiently calculated using integer arithmetic units. However, ADD and SUB become nonlinear and have to be approximated by look up tables (LUTs) and interpolation, which is typically implemented in a dedicated LNS unit (LNU) [1,2] The area of LNUs grows exponentially with the desired precision, and an LNU with accuracy comparable to IEEE single precision format is larger than a traditional floating point unit (FPU) However, we show that in multi core systems optimized for ultra low power operation such as the PULP system [3] one LNU can be efficiently shared in a cluster as indicated in Fig. 4.6.1. This arrangement not only reduces the per core area overhead, but more importantly, allows several costly operations such as FP MUL/DIV to be processed without contention within the integer cores without additional overhead. We show that for typical nonlinear processing tasks, our LNU design can be up to 4.2x more energy efficient than a private FP design.
2016 IEEE International Solid State Circuits Conference (ISSCC)