29355074
Joint Multiuser Precoding and Scheduling with Imperfect Channel State Information at the Transmitter
This paper addresses the joint design of multiuser precoding and scheduling for downlink multiuser (MU-) multiple-input-multiple-output (MIMO) systems with imperfect channel state information at the transmitter (CSIT). The major issue is to control the increased co-channel-interference (CCI) caused by CSIT error among users sharing the same time-frequency resource. We propose an advanced joint multiuser precoding and scheduling technique, which uses the statistical information of the CSIT error to predict the relationship among CCI, precoding matrixes and scheduling results, and utilizes such information to improve the precoding and scheduling algorithms for better CCI control. Simulation results have shown that considerable capacity improvement can be achieved by the proposed technique in the case of imperfect CSIT.
18692029
A CCI-Feedback-Aided Scheduling Technique for MU-MIMO
Imperfect channel state information (CSI) at the transmitter is one of the major challenges that the downlink multiuser multiple-input-multiple-output (MU-MIMO) technology faces in real applications. It will lead to increased co- channel interference (CCI) among users and deteriorate the capacity of MU-MIMO seriously, especially at high signal-to- noise-ratios (SNRs). In this paper, we propose an advanced MU-MIMO scheduling technique to improve the capacity of MU-MIMO in the case of imperfect CSI at the transmitter (CSIT). The rational behind the proposed scheme is the observation that the CCI level increases with the number of users simultaneously supported in MU-MIMO transmission. Thus, decreasing the number of simultaneous users can reduce CCI and sometimes even increase the sum capacity. Motivated by this observation, we design a CCI-feedback-aided scheduling technique, which adaptively adjusts the number of simultaneous users based on the CCI measurement at the user side. Simulation results have shown that considerable capacity gain can be achieved by the proposed scheduling technique at the cost of only one bit additional feedback per user and marginal complexity increase at both the transmitter and user side.
11558298
Layer Key Management Scheme on Wireless Sensor Networks
Wireless sensor networks are open architectures, so any potential threat can easily intercept, wiretap and counterfeit the information. Therefore, the safety of WSN is very important. Since any single key system cannot guarantee the security of the wireless sensor network for communications, this paper introduces a hierarchical key management scheme based on the different abilities of different sensor nodes in the clustered wireless sensor network. In this scheme, the nodes are distributed into several clusters, and a cluster head must be elected for each cluster. Private communication between cluster heads is realized through the encryption system based on the identity of each head while private communication between cluster nodes in a same cluster head is achieved through the random key preliminary distribution system. For cluster head node plays a pivotal role in this scheme, a trust management system should be introduced into the election of the cluster head which will exclude the malicious node from outside the cluster, thus improve the whole network security.
13024197
Joint Performance Improvement and Error Tolerance for Memory Design Based on Soft Indexing
Memory design is facing the dual challenges of performance improvement and error tolerance due to a combination of technology scaling and higher levels of integration. To address these challenges, we propose a new memory microarchitecture referred to as the soft indexing. The proposed technique allocates memory resources in a self-adaptive manner in accordance with runtime program variations, thereby achieving efficient memory access and effective error protection in a coherent manner. Statistical analysis shows 10times improvement in error detection capability over the existing error-control techniques. The benefits of the proposed technique are also experimentally demonstrated using the SPEC CPU2000 benchmarks. Simulation results show 94.9% average error-control coverage on the 23 benchmarks, with average of 23.2% reduction in memory miss rates as compared to the conventional techniques.
6708583
Reducing error accumulation effect in multithreaded memory systems
Chip multithreading is exposed to dual challenges of increasing chip complexity and design variations. It is important to develop effective reliability-enhancing schemes to ensure robust computing. In this paper, we propose the immediate write-back and self-recovery schemes to reduce error accumulation effect in multithreaded memory systems. These schemes are built upon the previously proposed dynamic multithreading redundancy technique for improving reliability in multithreaded architectures. The idea of DMR is to exploit self-generated hardware redundancy due to inter-thread variations inherent in multithreaded architectures. Simulation results demonstrate that the proposed solutions improve error-control performance with minimal hardware overheads. The proposed immediate write-back and self-recovery schemes also feature good scalability for future process generations
117675
Analysis of Deskew Signaling Via Adaptive Timing
This paper presents an adaptive timing method for analysis of deskew signaling in high-performance integrated systems. The proposed approach models the practical deskew schemes as an adaptive system to study the performance limit of deskew signaling. We investigate the statistical properties of optimal deskew, which can be considered as the theoretical limit of deskew signaling. This approach also allows us to study the related energy efficiency issues in deskew schemes. We determine the bound on energy efficiency subject to the performance constraint on deskew signaling. Simulation results show that the performance of practical deskew schemes in a 90-nm process is 23.2% away from the optimal deskew scheme, and the gap of energy efficiency is 51% above the bound.
41699961
Automated Detection of Code Vulnerabilities Based on Program Analysis and Model Checking
Ensuring the correctness and reliability of software systems is one of the main problems in software development. Model checking, a static analysis method, is preponderant in improving the precision of vulnerabilities detection. However, when applied to buffer overflow and other bugs, it is hard to automatically construct the model for detecting the vulnerabilities. To address this problem we propose an approach that combines constraint based analysis and model checking together. We trace the memory size of buffer-related variables and instrument the code with corresponding constraint assertions before the potential vulnerable points by constraint based analysis. Then the problem of detecting vulnerabilities is converted into the problem of detecting vulnerabilities to verifying the reach ability of these assertions by model checking. In order to reduce the cost of model checking, program slicing is introduced to reduce the code size. CodeAuditor is a prototype implementation of our approach. With CodeAuditor, several yet unreported vulnerabilities are discovered in several open source software, and the performance is shown to be improved significantly with the help of program slicing.