267541
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration
With the continuing scaling of CMOS technologies, process variation is becoming a key factor highly impacting system-level power and temperature. Traditional methods of assuming a uniform temperature and no process variation can lead to gross inaccuracies even for system-level design, thus it is critical to consider the effects of process variation and temperature variation during early design exploration. In this paper, we describe the implementation of an architecture- level early-stage design space exploration tool that incorporates the effect of process and temperature variation for network-on-chips(NoC). The tool is used to study the impact of process and temperature variations on power and energy-delay-product-per-flit metrics for different NoC architectures, and our simulation results show that design choices are influenced by the effects of process and temperature variation, thus demonstrating the importance of considering, and enabling the high- level impact analysis of process and temperature variation early in the design flow.
8359291
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the increasing on-chip communication demand among the computation elements necessitates the use of scalable, nigh-bandwidth network-on-chip (NoC) fabrics. As transistor feature sizes are further miniaturized leading to rapidly increasing amounts of on-chip resources, more complicated and powerful NoC architectures become feasible that can support more sophisticated and demanding applications. Given the myriad emerging software-hardware combinations, for cost-effectiveness, a system designer critically needs to prune this widening NoC design space to identify the architecture(s) that best balance(s) cost/performance, before the actual design process begins. This prompted us to develop Polaris 1, a system-level roadmap for on-chip interconnection networks that guides designers towards the most suitable network design(s) tailored to their performance needs and power/silicon area constraints with respect to a range of applications that will run over this network(s). Polaris explores the plethora of NoC designs based on projections of network traffic, architectures, and process characteristics. While the Polaris roadmapping toolchain is extensible so new traffic, network designs, and processes can be added, the current version of the roadmap already incorporates 7,872 NoC design points. Polaris is rapid and iterates over all these NoC architectures within a tractable run time of 125 hours on a typical desktop machine, while maintaining high relative and absolute accuracies when validated against detailed NoC synthesis results.
6449965
Development of a snake-like robot adapting to the ground
Biological snakes' diverse locomotion modes and physiology make them supremely adapted for the ground. This paper discusses the biological snakes' locomotion mode on the diverse ground, and describes the development of a snake-like robot with the adaptability for the ground. The method to realize some locomotion modes is given. The method for detecting the characteristic of ground is proposed and identified in test.
5261874
Integrating software into PRA
Probabilistic Risk Assessment is a technique to assess the probability of failure or success of a mission. Results provided by the risk assessment methodology are used to make decisions concerning choice of upgrades, scheduling of maintenance, decision to launch, etc. However, current PRA neglects the contribution of software to the risk of failure of the mission. This paper presents a framework for "Integrating Software into PRA", a methodology for systematic integration of the software contribution to risk in system failure analysis. In particular, we established a software-related failure mode taxonomy and a three-level PRA sub-model to account for the impact of software to the classical PRA structure. Application and validation of the taxonomy are discussed in this paper. Future research is also summarized.
29218953
On Handoff Performance for an Integrated Voice/Data Cellular System
One of the key challenges in the design of bandwidth allocation policies for a multi-services mobile cellular network is to guarantee the potentially different Quality of Service (QoS) requirement from diverse applications, while at the same to ensure that the scarce bandwidth be utilized efficiently. Complete Sharing (CS) and Dynamic Partition (DP) schemes have been shown as viable techniques for managing the bandwidth. However, there has been no study that compares their respective performance, which is the focus of this paper. Specifically, in this paper, through both analysis and simulation, we demonstrate that both schemes can achieve comparable performance by proper manipulation of control parameters. The tradeoff is that DP scheme can more easily achieve the target QoS requirement, at the expense of some over-provisioning, thus can potentially lead to less channel efficiency when comparing to a CS based scheme.
1252893
A Configurable Web Service Performance Testing Framework
More and more softwares based on web service technologies are developed. Before their releases on the Internet, it is necessary to evaluate these systems' performance, especially their response time under different workload pressures. However, existing performance testing benchmarks and tools for web service applications are difficult to adapt to various user-specific testing purposes. This paper proposes a configurable web service performance testing framework which contains client module, application server module and database module. Client module, by using the network cooperation method that one central client drives several other clients, adapts to a great number of concurrent customers to request web services. Application server module contains web services under testing and external supporting web services, each of which is configured as a plug-in. The process to realize mixed ratio of web service interactions is similar to dealing cards and adapts to different commercial application characteristics. In database module, the data model including table and attribute dependence can be customized, and the data scale initialization can be resized according to the topology of above dependence. As such, this framework allows testers to dynamically define their data model, customize their scale of database, configure their transaction characteristics, deploy their application strategies and confirm their performance metrics..
14221074
Accurate and efficient processor performance prediction via regression tree based modeling
Computer architects usually evaluate new designs using cycle-accurate processor simulation. This approach provides a detailed insight into processor performance, power consumption and complexity. However, only configurations in a subspace can be simulated in practice due to long simulation time and limited resource, leading to suboptimal conclusions which might not be applied to a larger design space. In this paper, we propose a performance prediction approach which employs state-of-the-art techniques from experiment design, machine learning and data mining. According to our experiments on single and multi-core processors, our prediction model generates highly accurate estimations for unsampled points in the design space and show the robustness for the worst-case prediction. Moreover, the model provides quantitative interpretation tools that help investigators to efficiently tune design parameters and remove performance bottlenecks.