17584180
A compiler and runtime infrastructure for automatic program distribution
This paper presents the design and the implementation of a compiler and runtime infrastructure for automatic program distribution. We are building a research infrastructure that enables experimentation with various program partitioning and mapping strategies and the study of automatic distribution's effect on resource consumption (e.g., CPU, memory, communication). Since many optimization techniques are faced with conflicting optimization targets (e.g., memory and communication), we believe that it is important to be able to study their interaction. We present a set of techniques that enable flexible resource modeling and program distribution. These are: dependence analysis, weighted graph partitioning, code and communication generation, and profiling. We have developed these ideas in the context of the Java language. We present in detail the design and implementation of each of the techniques as part of our compiler and runtime infrastructure. Then, we evaluate our design and present preliminary experimental data for each component, as well as for the entire system.
13590609
Automatic Partitioning of Object-Oriented Programs for Resource-Constrained Mobile Devices with Multiple Distribution Objectives
We describe a system that takes monolithic Java programs as its input and automatically converts them into distributed Java programs. Our research is situated in the context of resource-constrained mobile devices, in which there are often multiple distribution objectives, such as minimizing energy consumption on mobile devices by off loading workloads to a stationary server, or minimizing total execution time. Our method initially constructs an object relation graph (ORG), using a combination of static analysis and offline profiling. Instead of directly partitioning this ORG, we then transform it into a target graph (TG) to abstract from concrete distribution infrastructures and objectives. By applying this two-layer graph modeling, we achieve a unified strategy for different partitioning goals. Preliminary benchmarks for our prototype implementation are highly promising, with an average speedup factor of almost 1.5 and an average energy savings of 83.5% for the beneficial benchmarks.
11258056
Data I/O Minimization for Loops on Limited Onchip Memory Processors
Due to significant advances in VLSI technology, ‘mega-processors’ made with a large number of transistors has become a reality. These processors typically provide multiple functional units which allow exploitation of parallelism. In order to cater to the data demands associated with parallelism, the processors provide a limited amount of on-chip memory. The amount of memory provided is quite limited due to higher area and power requirements associated with it. Even though limited, such on-chip memory is a very valuable resource in memory hierarchy. An important use of on-chip memory is to hold the instructions from short loops along with the associated data for very fast computation. Such schemes are very attractive on embedded processors where, due to the presence of dedicated hard-ware on-chip (such as very fast multipliers-shifters etc.) and extremely fast accesses to on-chip data, the computation time of such loops is extremely small meeting almost all real-time demands. Biggest bottleneck to performance in these cases are off-chip accesses and thus, compilers must carefully analyze references to identify good candidates for promotion to on-chip memory. In our earlier work [6], we formulated this problem in terms of 0/1 knapsack and proposed a heuristic solution that gives us good promotion candidates. Our analysis was limited to a single loop nest. When we attempted extending this framework to multiple loop nests (intra-procedurally), we realized that not only it is important to identify good candidates for promotion but a careful restructuring of loops must be undertaken before performing promotion since data i/o of loading and storing values to on-chip memory poses a significant bottleneck.
12523556
Design Patterns of Scalable Cluster System Software
The design pattern of cluster system software has an important influence on scalability of massive cluster system. The paper presents design patterns of scalable cluster system software, including scalable software topologies and optimized communication modes. These design patterns have been widely applied in Dawning series of supercomputers and some results of performance evaluation show their good scalability
14387828
Escape analysis for synchronization removal
In this paper we introduce our escape analysis framework for Java, which is a kind of flow-insensitive, inter-procedural, and context-sensitive data flow analysis. And we present an efficient static intra-procedural algorithm for inferring the set of types that can occur at runtime for each object. With intra-procedural type information, virtual method resolution, callee-stub inline, exception analysis, and thread allocation site analysis are implemented. Virtual method resolution and callee-stub inline effectively reduce the call graph and SCC (strongly connected components). In exception analysis, we present a more precise analysis algorithm, especially in the inter-procedural exception in SCC.Our escape analysis can be applied to the whole Java program and Java libraries to identify unnecessary synchronization in Java and remove them. We have developed an implementation on Intel's Open Runtime Platform. For our benchmarks, 7.3% to 99% (with an average of 54%) of synchronization operations are eliminated.
7977463
LiveBT: Providing Video-on-Demand Streaming Service over BitTorrent Systems
BitTorrent (BT) is one of the most popular Peer-to- Peer (P2P) protocols for delivering media files in the Internet today. Although BT is quite efficient for sharing and downloading files by using P2P swarming technique, the users have to download almost the whole media file before playing it. This is determined by the Rarest-Block-Download-First strategy of standard BT implementations, which is designed for fast delivery of files in the systems but not for streaming application. In this paper, we present LiveBT, a new protocol which supports video-on- demand streaming service and is totally compatible to the current BitTorrent protocol. LiveBT enables users to play hot movies shared in the BT systems smoothly just after 2-3 minutes of buffering time. We also develop the prototype of LiveBT and test the performance through the real BT download tasks of media files. By comparing our prototype with some popular BT clients claiming to support view-as- download service such as Bitcomet, we find that LiveBT spends a much shorter buffering time to play and achieves quite smooth playback performance.
34391241
A turbo codes optimization method using particle swarm algorithm
Turbo Codes present a new direction for the channel encoding, especially since they were adopted for multiple norms of telecommunications, such as deeper communication, etc. To obtain an excellent performance, it is necessary to design robust turbo code interleaver and decoding algorithms. In this paper, we are investigating particle swarm algorithm as a promising optimization method to find good interleaver for the large frame sizes, as well as design the decoding optimization mode (PSO-Turbo); and apply the proposed PSO-Turbo codes mode to the security radio data transmission; in which, a kind of transport control proposal based on PSO-Turbo optimizer for CBTC wireless channel is designed and simulated to validate our method.