25793288
Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multiprocessor systems-on-a-chip (MPSoCs) and chip multiprocessors (CMPs). In these systems, the increasing on-chip communication demand among the computation elements necessitates the use of scalable, high-bandwidth network-on-chip (NoC) fabrics instead of dedicated interconnects and shared buses. As transistor feature sizes are further miniaturized, more complicated NoC architectures become feasible that can support more demanding applications. Given the myriad emerging software-hardware combinations, for cost-effectiveness, a system designer critically needs to prune this widening NoC design-space to predict the interconnect fabric(s) that best balance(s) cost/performance, before the actual design process begins. This prompted us to develop Polaris, a system-level roadmapping toolchain for on-chip interconnection networks that helps designers predict the most suitable interconnection network design(s) tailored to their performance needs and power/silicon area constraints with respect to a range of applications that the system will run. Polaris explores the plethora of NoC designs based on projections of network traffic, architectures, and process characteristics. While Polaris's toolchain is extensible so new traffic, network designs, and technology processes can be added, the current version already incorporates 7872 NoC design points. Polaris is rapid, efficiently iterating over thousands of NoC design points, while maintaining high relative and absolute accuracies when validated against detailed NoC synthesis results.
8359291
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the increasing on-chip communication demand among the computation elements necessitates the use of scalable, nigh-bandwidth network-on-chip (NoC) fabrics. As transistor feature sizes are further miniaturized leading to rapidly increasing amounts of on-chip resources, more complicated and powerful NoC architectures become feasible that can support more sophisticated and demanding applications. Given the myriad emerging software-hardware combinations, for cost-effectiveness, a system designer critically needs to prune this widening NoC design space to identify the architecture(s) that best balance(s) cost/performance, before the actual design process begins. This prompted us to develop Polaris 1, a system-level roadmap for on-chip interconnection networks that guides designers towards the most suitable network design(s) tailored to their performance needs and power/silicon area constraints with respect to a range of applications that will run over this network(s). Polaris explores the plethora of NoC designs based on projections of network traffic, architectures, and process characteristics. While the Polaris roadmapping toolchain is extensible so new traffic, network designs, and processes can be added, the current version of the roadmap already incorporates 7,872 NoC design points. Polaris is rapid and iterates over all these NoC architectures within a tractable run time of 125 hours on a typical desktop machine, while maintaining high relative and absolute accuracies when validated against detailed NoC synthesis results.
267541
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration
With the continuing scaling of CMOS technologies, process variation is becoming a key factor highly impacting system-level power and temperature. Traditional methods of assuming a uniform temperature and no process variation can lead to gross inaccuracies even for system-level design, thus it is critical to consider the effects of process variation and temperature variation during early design exploration. In this paper, we describe the implementation of an architecture- level early-stage design space exploration tool that incorporates the effect of process and temperature variation for network-on-chips(NoC). The tool is used to study the impact of process and temperature variations on power and energy-delay-product-per-flit metrics for different NoC architectures, and our simulation results show that design choices are influenced by the effects of process and temperature variation, thus demonstrating the importance of considering, and enabling the high- level impact analysis of process and temperature variation early in the design flow.
39681871
Automated Cellular Modeling and Prediction on a Large Scale
We describe CHAMP (CHurn Analysis, Modeling, andPrediction), an automated system for modeling cellularsubscriber churn that is predicting which customerswill discontinue cellular phone service. We describevarious issues related to developing and deployingthis system including automating data access from aremote data warehouse, preprocessing, featureselection, model validation, and optimization toreflect business tradeoffs. Using data from GTE'sdata warehouse for cellular phone customers, CHAMP iscapable of developing churn models customized byregion for over one hundred GTE cellular phone marketstotaling over 5 million customers. Every month churnfactors are identified for each geographic region andmodels are updated to generate churn scores predictingwho is likely to churn in the short term. Learningmethods such as decision trees and genetic algorithmsare used for feature selection and a cascade neuralnetwork is used for predicting churn scores. Inaddition to producing churn scores, CHAMP alsoproduces qualitative results in the form of rules andcomparison of market trends that are disseminatedthrough a web based interface.
14221074
Accurate and efficient processor performance prediction via regression tree based modeling
Computer architects usually evaluate new designs using cycle-accurate processor simulation. This approach provides a detailed insight into processor performance, power consumption and complexity. However, only configurations in a subspace can be simulated in practice due to long simulation time and limited resource, leading to suboptimal conclusions which might not be applied to a larger design space. In this paper, we propose a performance prediction approach which employs state-of-the-art techniques from experiment design, machine learning and data mining. According to our experiments on single and multi-core processors, our prediction model generates highly accurate estimations for unsampled points in the design space and show the robustness for the worst-case prediction. Moreover, the model provides quantitative interpretation tools that help investigators to efficiently tune design parameters and remove performance bottlenecks.
5438961
A dynamic multiple-threshold bandwidth reservation (DMTBR) scheme for QoS provisioning in multimedia wireless networks
Next-generation wireless networks target to provide quality of service (QoS) for multimedia applications. We study the wireless systems that support two QoS requirements: keeping the handoff dropping probability less than a predefined QoS threshold while maintaining relative priorities for different traffic classes based on blocking probability. To achieve this goal, a dynamic multiple-threshold bandwidth reservation (DMTBR) scheme, which is capable of granting differential priorities to different traffic classes and to new and handoff traffic for each class by dynamically adjusting bandwidth reservation thresholds, is proposed. In this scheme, the thresholds are obtained in two steps. The initial values are estimated based on instantaneous network traffic situation, then the thresholds will be further adapted according to the instantaneous network QoS status. In times of network congestion, a preventive measure is taken to throttle the new connections. Another contribution of this paper is to generalize the concept of relative priority and hence give the network operator more flexibility to adjust admission control policy by taking into account some dynamic factors such as offered load. The extensive simulations are conducted for two purposes. First, we verify the performance of the proposed scheme and show our scheme performs well under various traffic loads. Second, we demonstrate that the DMTBR scheme gains more advantages when taking the offered load into consideration.
206574982
Battle Damage Assessment based on Bayesian Network
With the quickening rhythm of the war and the complication of battlefield environment,the battle damage assessment(BDA) has had a more important effect on the commander's decision.Because of the complexity of modern battlefield and the uncertainty of battle damage information,it is more and more difficult to determine the damage level of target.Bayesian network is a reasoning and predicting tool coming into vogue only in recent decades.It can correctly reason a problem of interest based on the uncertainty and incomplete information,which is suited to evaluate the battle damage based on the uncertainty and incomplete target damage information.According to the study of BDA based on Bayesian network,the building and updating process of Bayesian network model were discussed.The feasibility and validity of Bayesian network for BDA were analyzed by taking airport runway for example.
25955132
A new synchronization algorithm for VHDL-AMS simulation
VHDL-AMS is the Analog and Mixed-Signal Extensions to VHDL. The paper gives a brief overview of the added features to VHDL. A mixed-signal simulator has been developed based on VHDL-AMS. A new synchronization algorithm is adopted in the simulator. Using the new algorithm the analog kernel does not need to synchronize the digital kernel at each digital event time point. The efficiency of the new synchronization algorithm is tested by examples. Simulation results show the newly developed algorithm can speed up the simulation.