8221408
RTL concurrent fault simulation
The integrated circuit (IC) design has been pushed to hardware description language (HDL) description and high-level synthesis (HLS) techniques. The IC testing is also going to the high-level one. For the high-level testing, like gate level one, it needs a circuit model at high level such that, The model is easy to be converted and extended from the HDL descriptions. The model should be unified for multiple usages such as fault simulation, test generation, testability measure, etc. For various algorithms, it is easy to perform forward and backward tracing on the model, and easy to define fault models. In this paper, we try to construct such model and apply it to the fault simulation first.
7641777
GBNet: Deciphering regulatory rules in the co-regulated genes using a Gibbs sampler enhanced Bayesian network approach
BackgroundCombinatorial regulation of transcription factors (TFs) is important in determining the complex gene expression patterns particularly in higher organisms. Deciphering regulatory rules between cooperative TFs is a critical step towards understanding the mechanisms of combinatorial regulation.ResultsWe present here a Bayesian network approach called GBNet to search for DNA motifs that may be cooperative in transcriptional regulation and the sequence constraints that these motifs may satisfy. We showed that GBNet outperformed the other available methods in the simulated and the yeast data. We also demonstrated the usefulness of GBNet on learning regulatory rules between YY1, a human TF, and its co-factors. Most of the rules learned by GBNet on YY1 and co-factors were supported by literature. In addition, a spacing constraint between YY1 and E2F was also supported by independent TF binding experiments.ConclusionWe thus conclude that GBNet is a useful tool for deciphering the "grammar" of transcriptional regulation.
31019926
A Functional Testing Method for Microprocessors
A method is presented for functional testing of microprocessors. First, a control fault model at the RTL (register transfer language) level is developed. Based on this model, the authors establish testing requirements for control faults. They present two test procedures to verify the write and read sequences, and use the write and read sequences to test each instruction in the microprocessor. By utilizing k-out-of-m codes, they use fewer tests to cover more faults, thereby reducing the test generation time. >
43366543
VLSI functional testing using critical path traces at hardware description language level
A new approach for testing VLSI circuits is presented. Through backward critical path tracing, a test and all faults detectable by the test are generated simultaneously. Therefore, the expensive fault simulation is completely eliminated. We present a critical path test generation procedure for digital systems described by hardware description language (HDL). A multiplication circuit described by a HDL is utilized for demonstrating the test generation method.
62074016
Dimension Reduction-Based Penalized Logistic Regression for Cancer Classification Using Microarray Data
The use of penalized logistic regression for cancer classification using microarray expression data is presented. Two dimension reduction methods are respectively combined with the penalized logistic regression so that both the classification accuracy and computational speed are enhanced. Two other machine-learning methods, support vector machines and least-squares regression, have been chosen for comparison. It is shown that our methods have achieved at least equal or better results. They also have the advantage that the output probability can be explicitly given and the regression coefficients are easier to interpret. Several other aspects, such as the selection of penalty parameters and components, pertinent to the application of our methods for cancer classification are also discussed.
19415028
Unified model in identity subspace for face recognition
Human faces have two important characteristics: (1) They are similar objects and the specific, variations of each face are similar to each other; (2) They are nearly bilateral symmetric. Exploiting the two important properties, we build a unified model in identity subspace (UMIS) as a novel technique for face recognition from only one example image per person. An identity subspace spanned by bilateral symmetric bases, which compactly encodes identity information. is presented. The unified model, trained on an obtained training set with multiple samples per class from a known people groupA, can be generalized well to facial images of unknown individuals, and can be used to recognize facial images from an unknown people groupB with only one sample per subject. Extensive experimental results on two public databases (the Yale database and the Bern database) and our own database (the ICT-JDL database) demonstrate that the UMIS approach is significantly effective and robust for face recognition.
11178688
Dynamically utilizing computation accelerators for extensible processors in a software approach
In recent years, it is increasingly common to see using application specific instruction set processors (ASIPs) in embedded system designs. These ASIPs can offer the ability of customizing hardware computation accelerators for an application domain. Along with instruction set extensions (ISEs), the customized accelerators can significantly improve the performance of embedded processors, which has already been exemplified in previous research work and industrial products. However, these accelerators in ASIPs can only accelerate the applications that are compiled with ISEs. Those applications compiled without ISEs can not benefit from the hardware accelerators at all. In this paper, we propose using software dynamic binary translation to overcome this problem, i.e. dynamically utilizing the accelerators. Unlike a static approach, dynamically utilizing accelerator poses many new problems. This paper comprehensively explores the techniques and design choices for solving these problems, and demonstrates the effectiveness by the results of experiments.
27674470
Application of Software Fault Tree Analysis to an Airport Ground Control System
With the ever increasing role of software in our day-to-day life, and even more important the criticality of their role in safety and reliability of the applications, it is important to find techniques that helps with identifying and balancing risks. One such technique is Fault Tree Analysis, which has proven to be powerful in other domains such as systems and processes. This paper, describes the results of application of the fault tree analysis to software requirement specification for an airport ground control system. In addition, this paper proposes a set of guidelines on how to apply SFTA to software requirement specification.
9589989
Efficient photometric stereo technique for three-dimensional surfaces with unknown BRDF
The present paper focuses on efficient inverse rendering using a photometric stereo technique for realistic surfaces. The technique primarily assumes the Lambertian reflection model only. For non-Lambertian surfaces, application of the technique to real surfaces in order to estimate 3D shape and spatially varying reflectance from sparse images remains difficult. In the present paper, we propose a new photometric stereo technique by which to efficiently recover a full surface model, starting from a small set of photographs. The proposed technique allows diffuse albedo to vary arbitrarily over surfaces while non-diffuse characteristics remain constant for a material. Specifically, the basic approach is to first recover the specular reflectance parameters of the surfaces by a novel optimization procedure. These parameters are then used to estimate the diffuse reflectance and surface normal for each point. As a result, a lighting-independent model of the geometry and reflectance properties of the surface is established using the proposed method, which can be used to re-render the images under novel lighting via traditional rendering methods.
60639655
Parallel simulation of chip-multiprocessor by using multi-threading
Multi-core on one chip becomes the current main trend of micro processors' architecture, and simulation plays an important role in evaluating new processor architectures. Traditional ways of sequential simulation for chip-multiprocessor (CMP) require lots of simulation time which can't be afford during processor design phase. Therefore, exploiting parallelism is necessary for speeding up the multi-core processor simulation. 
 
In this paper, we present a parallel CMP simulator, which is implemented by using POSIX threads, and also present the programming methodology for converting a sequential single core simulator to a parallel CMP simulator. Furthermore, the tradeoffs in parallel simulator implementation are also discussed. The experiments are carried out on a four-CPU dual core Xeon server. Under weak consistence order model, the parallel simulator achieves a speedup of 7.2X comparing with the sequential one.
15408747
A Novel Surface Registration Algorithm With Biomedical Modeling Applications
In this paper, we propose a novel surface matching algorithm for arbitrarily shaped but simply connected 3-D objects. The spherical harmonic (SPHARM) method is used to describe these 3-D objects, and a novel surface registration approach is presented. The proposed technique is applied to various applications of medical image analysis. The results are compared with those using the traditional method, in which the first-order ellipsoid is used for establishing surface correspondence and aligning objects. In these applications, our surface alignment method is demonstrated to be more accurate and flexible than the traditional approach. This is due in large part to the fact that a new surface parameterization is generated by a shortcut that employs a useful rotational property of spherical harmonic basis functions for a fast implementation. In order to achieve a suitable computational speed for practical applications, we propose a fast alignment algorithm that improves computational complexity of the new surface registration method from O(n3) to O(n2).