18690900
Way-tagged cache: an energy-efficient L2 cache architecture under write-through policy
Write-through policy employed in many high-performance microprocessors provides good tolerance to soft errors in cache systems. However, it also incurs large energy overhead due to the increased accesses to caches at the lower level (e.g., the L2 cache) during write operations. In this paper, we propose a new cache architecture referred to as way-tagged cache to improve the energy efficiency of write-through cache systems. By maintaining the way tags of the L2 cache in the L1 cache during read operations, the proposed technique enables the L2 cache to work in an equivalent direct-mapping manner during write hits, which account for the majority of L2 cache accesses. This leads to significant energy reduction. Simulation results on the SPEC CPU2000 benchmarks demonstrate that the proposed technique achieves 65.4% energy savings on average with about 0.02% area overhead and no performance degradation.
18869116
Thread-Associative Memory for Multicore and Multithreaded Computing
Presented in this paper is the thread-associative memory microarchitecture for multicore and multithreaded processor design. Memory contention among concurrent threads in chip multithreaded processing has become a limiting factor for performance improvement. The proposed thread-associative memory addresses this challenge by incorporating thread-specific information explicitly into on-chip memory hardware. The proposed technique can be utilized at different levels of memory hierarchy. Furthermore, it is not just a technique for performance enhancement but also a solution for energy efficiency. Trace-driven simulations on a 32KB L1 data cache demonstrate 36.6% maximum performance improvement and up to 15.1% total energy reduction, with 20.3% dynamic energy reduction and 9.9% leakage energy reduction
6708583
Reducing error accumulation effect in multithreaded memory systems
Chip multithreading is exposed to dual challenges of increasing chip complexity and design variations. It is important to develop effective reliability-enhancing schemes to ensure robust computing. In this paper, we propose the immediate write-back and self-recovery schemes to reduce error accumulation effect in multithreaded memory systems. These schemes are built upon the previously proposed dynamic multithreading redundancy technique for improving reliability in multithreaded architectures. The idea of DMR is to exploit self-generated hardware redundancy due to inter-thread variations inherent in multithreaded architectures. Simulation results demonstrate that the proposed solutions improve error-control performance with minimal hardware overheads. The proposed immediate write-back and self-recovery schemes also feature good scalability for future process generations
8890864
Improving Error Tolerance for Multithreaded Register Files
Chip multithreaded computing is exposed to the dual challenges of increasing system complexity and error sensitivity. It is critical to develop effective solutions that achieve better error tolerance without inducing performance degradation. In this paper, we propose a new error-tolerant memory design based on a unique computing phenomenon referred to as the dynamic multithreading redundancy (DMR). The proposed technique exploits the interplay between the concurrent threads for runtime error control. We also present two DMR enhancements, immediate write-back and self-recovery, to address the error accumulation effect. A multithreaded register file was implemented to demonstrate the proposed DMR technique. Simulation results on the SPEC CPU2000 benchmarks demonstrate significant overhead reduction in performance and energy efficiency related to error recovery. In addition, the proposed technique features good scalability with respect to the instruction-level and thread-level parallelism for next-generation processor design, where the soft error problem is expected to get worse due to technology scaling and architecture-affecting trends.
16020986
Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation
Nanoelectronic devices are considered to be the computational fabrics for the emerging nanocomputing systems due to their ultra-high speed and integration density. However, the imperfect bottom-up self-assembly fabrication leads to excessive defects that have become a barrier for achieving reliable computing. In addition, transient errors continue to be a problem. The massive parallelism rendered by nanoscale integration opens up new opportunities but also poses challenges on how to manage such massive resources for reliable and high-performance computing. In this paper, we propose a nanoarchitecture solution to address these emerging challenges. By using dynamic redundancy allocation, the massive parallelism is exploited to jointly achieve fault (defect/error) tolerance and high performance. Simulation results demonstrate the effectiveness of the proposed technique under a range of fault rates and operating conditions.
36279845
Exploiting soft redundancy for error-resilient on-chip memory design
17771606
Phoenix Cloud : Consolidating Heterogeneous Workloads of Large Organizations on Cloud Computing Platforms
The present invention relates to a process to aminate electrophilic aromatic compounds by vicarious nucleophilic substitution of hydrogen using quaternary hydrazinium salts. The use of trialkylhydrazinium halide, e.g., trimethylhydrazinium iodide, as well as hydroxylamine, alkoxylamines, and 4-amino-1,2,4-triazole to produce aminated aromatic structures, such as 1,3-diamino-2,4,6-trinitrobenzene (DATB), 1,3,5-triamino-2,4,6-trinitrobenzene (TATB) and 3,5-diamino-2,4,6-trinitrotoluene (DATNT), is described. DATB and TATB are useful insensitive high explosives. TATB is also used for the preparation of benzenehexamine, a starting material for the synthesis of novel materials (optical imaging devices, liquid crystals, ferromagnetic compounds).
16336079
Low-power MIMO signal processing
In this paper, we present a new adaptive error-cancellation (AEC) technique, denoted as multi-input-multi-output (MIMO)-AEC, for the design of low-power MIMO signal processing systems. The MIMO-AEC technique builds on the previously proposed AEC technique by employing an algorithm transformation denoted as MIMO decorrelating (MIMO-DECOR) transform. MIMO-DECOR reduces complexity by exploiting correlations inherent in MIMO systems, thereby improving the energy efficiency of AEC. The proposed MIMO-AEC enables energy minimization of MIMO systems by correcting transient/soft errors that arise in very large scale integration signal processing implementations due to inherent process nonidealities and/or aggressive low-power design styles, such as voltage overscaling. We employ the MIMO-AEC in the design of a low-power Gigabit Ethernet 1000Base-T device. Simulation results indicate 69.1%-64.2% energy savings over optimally voltage-scaled present-day systems with no loss in algorithmic performance.
44863002
Comparative Study on Bionic Optimization Algorithms for Sewer Optimal Design
Sewer network as a necessary urban infrastructure plays an important role in people’s daily life. Conventional optimization techniques have significant limitations on solving the problems of sewer optimal design. Because as a high-dimensional discrete complex optimization problem, sewer optimal design is characterized by its discrete objective function and, as an integer discrete variable, its decision variable amount keeps the same pace with engineering scales. Over the last decade, various kinds of modern bionic optimization algorithms with their special advantages have been created and applied into sewer optimal design successfully. Based on previous studies, this paper analyses and compares the solution performances of Genetic Algorithms (GA), Particle Swarm Optimization (PSO) and Ant Colony Algorithms (ACA) from the three aspects respectively, they are convergence, speed and complexity of algorithm. The research result shows that compared with the other two algorithms, the ACA manifests its superiority for better convergence, satisfactory speed and relatively small algorithm complexity, which are very suitable for solving the problems of sewer optimal design.
7481401
Noise-tolerant dynamic circuit design
Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energy efficiency of VLSI systems in the deep submicron era. To address this problem, a new noise-tolerant dynamic circuit technique is presented. In addition, the average noise threshold energy (ANTE) and the energy normalized ANTE metrics are proposed for quantifying the noise immunity and energy efficiency, respectively, of circuit techniques. Simulation results in 0.35 micron CMOS for NAND gate designs indicate that the proposed technique improves the ANTE and energy normalized ANTE by 2.54X and 2.25X over the conventional domino circuit. The improvement in energy normalized ANTE is 1.22X higher than the existing noise-tolerance techniques. A full adder design based on the proposed technique improves the ANTE and energy normalized ANTE by 3.7X and 1.95X over the conventional dynamic circuit. In comparison, the static circuit improves ANTE by 2.2X but degrades the energy normalized ANTE by 11%. In addition, the proposed technique has a smaller area overhead (69%) as compared to the static circuit whose area overhead is 98%.
31999867
A Novel Classifier with the Immune-Training Based Wavelet Neural Network
After analyzing the classification and training ability of a wavelet neural network (WNN), a novel WNN learning scheme integrating immunity based evolutionary algorithm (IDEA) is proposed, in which, IDEA is an evolutionary algorithm with an embedded immune mechanism. When WNN is used as a classifier, the process of seeking the least mean-square error (LMS) of an optimal problem is equivalent to that of finding the wavelet feature with maximal separability, namely, maximizing its separable division. On the other hand, with the capability of robust learning of its evolutionary process, IDEA is able to eliminate local degenerative phenomenon due to blindfold behaviors of original operators in the existing evolutionary algorithms. In the case of the twin-spiral problem, experimental simulation shows the feasibility of WNN training with the IDEA based learning algorithm.