27426193
MCC: The Module Controller Chip for the ATLAS pixel detector
In this article we describe the architecture of the Module Controller Chip for the ATLAS Pixel Detector. The project started in 1997 with the definition of the system specifications. A first fully-working rad-soft prototype was designed in 1998, while a radiation hard version was submitted in 2000. The 1998 version was used to build pixel detector modules. Results from those modules and from the simulated performance in ATLAS are reported. In the article we also describe the hardware/software tools developed to test the MCC performance at the LHC event rate.
37159826
A measurement of Lorentz angle and spatial resolution of radiation hard silicon pixel sensors
Silicon pixel sensors developed by the ATLAS collaboration to meet LHC requirements and to withstand hadronic irradiation to fluences of up to $10^{15} n_eq/cm^{2}$ have been evaluated using a test beam facility at CERN providing a magnetic field. The Lorentz angle was measured and found to alter from 9.0 deg. before irradiation, when the detectors operated at 150 V bias at B=1.48 T, to 3.1 deg after irradiation and operating at 600 V bias at 1.01 T. In addition to the effect due to magnetic field variation, this change is explained by the variation of the electric field inside the detectors arising from the different bias conditions. The depletion depths of irradiated sensors at various bias voltages were also measured. At 600 V bias 280 micron thick sensors depleted to ~200 micron after irradiation at the design fluence of 1 10^{15} 1 MeV n_eq/cm2 and were almost fully depleted at a fluence of 0.5 * 10^{15} 1 MeV n_eq/cm2. The spatial resolution was measured for angles of incidence between 0 deg and 30 deg. The optimal value was found to be better than 5.3 micron before irradiation and 7.4 micron after irradiation.
108645383
The ATLAS Silicon Pixel Sensors
Abstract Prototype sensors for the ATLAS silicon pixel detector have been developed. The design of the sensors is guided by the need to operate them in the severe LHC radiation environment at up to several hundred volts while maintaining a good signal-to-noise ratio, small cell size, and minimal multiple scattering. The ability to be operated under full bias for electrical characterization prior to attachment of the readout integrated circuit electronics is also desired.
64504728
MAREBO: A full radhard pixel detector prototype for ATLAS
119605019
H1 FORWARD PROTON SPECTROMETER UPGRADE WITH SILICON PIXELS DETECTORS
Abstract The H1 experiment is already equipped with a four roman pots Forward Proton Spectrometer (FPS), using scintillating fibers. The H1 CPPM group has made a proposal to upgrade the FPS by adding silicon pixels detectors in the 90 m roman pot.
196042379
Emulation of an Event Builder using the ATM Local Area Network of the RCNP Institute
82263624
A read-out buffer prototype for ATLAS high level triggers
Read-out buffers are critical components in the dataflow chain of the ATLAS Trigger/DAQ system. At up to 75 kHz, after each level-1 trigger accept signal, these devices receive and store digitized data from groups of front-end electronic channels. Several read-out buffers are grouped to form a read-out buffer complex that acts as a data server for the high level trigger selection algorithms and for the final data collection system. This paper describes a functional prototype of a read-out buffer based on a custom made PCI mezzanine card that is designed to accept input data at up to 160 MB/s, to store up to 8 MB of data and to distribute data chunks at the desired request rate. We describe the hardware of the card that is based on an Intel 1960 processor and CPLDs. We present the integration of several of these cards in a read-out buffer complex. We measure various performance figures and we discuss to which extent these can fulfil ATLAS needs.
195863223
The ATLAS high level trigger ATM testbed
This paper describes an implementation of the High Level Trigger for the ATLAS experiment on a large testbed based on a 32 node switch attached to data sources, event processing units, supervisor modules and interface to the level-1 trigger. We describe the functionality of each component and investigate its performance. We show the operation of the complete system and outline future activities.
53769716
On the integration of high performance ATM-based event builders
A first demonstrator has shown encouraging results for the use of Asynchronous Transfer Mode (ATM) switching networks in the implementation of high performance parallel event builders. Our present goal is to show that the integration of event builders, including the implementation of the source and destination functions and the bandwidth adaptation to the switching network, can be realized with commercially available products and that good performance can be achieved. We shall review some critical issues, present results from performance measurements and analyse the overheads.
36799203
A study of performance issues of the ATLAS event selection system based on an ATM switching network
The next generation of High Energy Physics experiments, ATLAS and CMS, proposed at the CERN Large Hadron Collider (LHC), will place heavy demands on the data acquisition and on-line filtering systems. Asynchronous Transfer Mode (ATM) is a candidate technology to implement the high performance network in the data collection system for the ATLAS experiment. This work presents the results of modeling and simulation studies which aim at integrating the detailed organization of the detector read-out, the trigger requirements and the capabilities of ATM switching networks. The status of hardware development of small scale demonstrators is outlined.