45238482
TengYue-1TengYue: In Chinese means jump over.: A High Performance Embedded SoC
16447326
An Approximate Method for Performance Evaluation of Asynchronous Pipeline Rings
Performance evaluation of asynchronous circuits is one of the most difficult parts in asynchronous circuit research. This Paper presents an approximate method by queuing network modeling for performance evaluation of asynchronous pipeline rings. The asynchronous pipeline rings are modeled by closed queuing networks with transfer blocking. An efficient approximation method is used to analyze the performance metrics, such as response time and throughput. These performance metrics can be used to derive the cycle time and latency of the asynchronous pipeline rings. Compared with theoretic results, the algorithm presented in this paper is efficient for performance evaluation of asynchronous pipeline rings.
22959134
The Design of Asynchronous Microprocessor Based on Optimized NCL_X Design-Flow
NCL X circuit is a very efficient way to implement the QDI circuit, which can get all the advantages of the asynchronous circuit, especially the average performance. But the NCL_X circuits suffer from its huge area overhead. To solve this problem, a method for optimizing the complete detection network in the NCL_X circuit has been introduced in this paper. Using this method can dramatically reduced the area of the NCL_X circuit, according to the experimental result, the area of the NCL_X circuit may be reduced more than 60%. We also use this optimized method to implement an asynchronous microprocessor pipeline (APC). Compared to the synchronous implementation, this NCL_X implementation can achieve higher performance because the NCL_X circuit can get the average performance.
11142145
An Optimal Design Method for De-synchronous Circuit Based on Control Graph
De-synchronous is a very useful method to design asynchronous circuit automatically from synchronous description of circuits. This paper introduces an optimal design method based on Control Graph which is an abstract model of the de-synchronous circuit. The main purpose of this optimal design method is to reduce the extra overhead in the area of the de-synchronous circuit. The optimization algorithm takes the performance evaluation function based on the Control Graph of the de-synchronous circuit as its heuristic function. The performance evaluation function presented in this paper is a linear programming problem. In the end of this paper, the optimal method is applied to a set of benchmark circuits. The number of the local controllers in these circuits is markedly reduced by 54%, and the number of C-elements that is required to construct the handshake circuitry between local controllers is also reduced by 76.3%. So the entire area of the circuit is sharply reduced. Because this design method is directed by the performance evaluation function of the circuit, there is no penalty in performance of the de-synchronous circuit.
43074800
Research and Implementation of a 32-Bit Asynchronous Multiplier
提出基于宏单元（macrocell）的异步电路设计流程,由于在流程中尽量与现有的同步电路设计EDA工具兼容,降低了技术难度,提高了开发效率.基于该流程实现了0.35μm工艺条件下的32位异步乘法器.经过与相同工艺条件下,具有相同数据通路结构的同步乘法器比较,异步乘法器的性能与同步乘法器相当,而且面积更小、功耗更低.
32146489
Cycle Period Analysis and Optimization of Timed Circuits
In this paper, a method is proposed to analyze the minimum average cycle period of the timed circuits. Timed Petri net is used to model timed circuits. Our method is focus on structural analysis of the Petri net model of the timed circuits, which is another way to reduce the state space of the analyzed model. Then an algorithm is proposed to optimize the performance of timed circuit by asynchronous retiming technique. The algorithm balances the asynchronous pipelines to gain the target cycle period while minimize the area at the same time. Experimental results demonstrate the computational feasibility and effectiveness of both approaches.
7144886
Khatri-Rao Unitary Space-Time Modulation
Based on the Khatri-Rao matrix product, we propose a novel unitary space-time modulation design called KR-USTM in this paper. Different from existing USTM schemes, such as the systematic approach and space-time frequency-shift keying (ST-FSK), KR-USTM does not require any computer search and can be applied to any number of transmit antennas. Moreover, the special structure of KR-USTM also makes it a high-rate scheme and achieve full antenna diversity as well as lower decoding complexity. Simulation results show that the proposed KR-USTM constellation achieves error performance comparable to existing USTM designs at low rates, while it outperforms them at high rates.
16013630
Runtime Performance of Parallel Array Assignment: An Empirical Study
Generating code for the array assignment statement of High Performance Fortran (HPF) in the presence of block-cyclic distributions of data arrays is considered difficult, and several algorithms have been published to solve this problem. We present a comprehensive study of the run-time performance of the code these algorithms generate. We classify these algorithms into several families, identify several issues of interest in the generated code, and present experimental performance data for the various algorithms. We demonstrate that the code generated for block-cyclic distributions runs almost as efficiently as that generated for block or cyclic distributions.
19453960
Integrating Case based Reasoning and Explanation based Learning in an Apprentice Agent
The problem in applications of case based reasoning (CBR) is its utility problem, that is, the cost of retrieving the most appropriate case from the case library for a new given problem and the cost of adapting the retrieved case for solving the new given problem. This paper proposes an approach to solve the utility problem of CBR by integrating CBR and explanation based learning (EBL) from a perspective that emphasizes the function of learning in CBR. In this paper, CBR and EBL are integrated in an apprentice agent, and the application of this apprentice agent in the robotic assembly domain is given as an example.
42292334
An Initial Framework for Collaboration-Based Component Selection
6708583
Reducing error accumulation effect in multithreaded memory systems
Chip multithreading is exposed to dual challenges of increasing chip complexity and design variations. It is important to develop effective reliability-enhancing schemes to ensure robust computing. In this paper, we propose the immediate write-back and self-recovery schemes to reduce error accumulation effect in multithreaded memory systems. These schemes are built upon the previously proposed dynamic multithreading redundancy technique for improving reliability in multithreaded architectures. The idea of DMR is to exploit self-generated hardware redundancy due to inter-thread variations inherent in multithreaded architectures. Simulation results demonstrate that the proposed solutions improve error-control performance with minimal hardware overheads. The proposed immediate write-back and self-recovery schemes also feature good scalability for future process generations