11178688
Dynamically utilizing computation accelerators for extensible processors in a software approach
In recent years, it is increasingly common to see using application specific instruction set processors (ASIPs) in embedded system designs. These ASIPs can offer the ability of customizing hardware computation accelerators for an application domain. Along with instruction set extensions (ISEs), the customized accelerators can significantly improve the performance of embedded processors, which has already been exemplified in previous research work and industrial products. However, these accelerators in ASIPs can only accelerate the applications that are compiled with ISEs. Those applications compiled without ISEs can not benefit from the hardware accelerators at all. In this paper, we propose using software dynamic binary translation to overcome this problem, i.e. dynamically utilizing the accelerators. Unlike a static approach, dynamically utilizing accelerator poses many new problems. This paper comprehensively explores the techniques and design choices for solving these problems, and demonstrates the effectiveness by the results of experiments.
14935665
Optimal Matrix Computing Using Vector Division with Sub-word Parallel
Available computing is expected to be effective and efficient in ubiquitous multimedia services. And, matrix multiplication is particular to ubiquitous computing such as image transformation so that it is urgent to exploit potential parallelism as well as data reuse in matrix multiplication. Therefore, based on synchronized data triggered architecture (SDTA), we propose a method of parallel vector division (PVD) as well as sub-word parallel (SWP) supported on SDTA to optimize the matrix computation on specified architecture. Experimental results show that PVD with SWP is suitable for matrix multiplication on SDTA instruction set architecture. Besides, we could extend the proposed model into other data-intensive computing on SDTA.
33440658
A New Technique for Program Code Compression in Embedded Microprocessor
Program code compression has become a critical technology nowadays, and it can promote the performance of microprocessor systems. But compression techniques nowadays can hardly achieve both satisfactory compression ratio and low hardware complexity. A new program code compression method is proposed in this paper. Experiment results show that the code sizes of ARM and OR1200 microprocessor can be efficiently reduced by 32.2% and 36.9% individually with this algorithm, resulting to a sharp decrease in memory traffic. A hardware decompressing prototype is also presented, revealing its advantage in ultra high speed decompression and low hardware complexity.
60639655
Parallel simulation of chip-multiprocessor by using multi-threading
Multi-core on one chip becomes the current main trend of micro processors' architecture, and simulation plays an important role in evaluating new processor architectures. Traditional ways of sequential simulation for chip-multiprocessor (CMP) require lots of simulation time which can't be afford during processor design phase. Therefore, exploiting parallelism is necessary for speeding up the multi-core processor simulation. 
 
In this paper, we present a parallel CMP simulator, which is implemented by using POSIX threads, and also present the programming methodology for converting a sequential single core simulator to a parallel CMP simulator. Furthermore, the tradeoffs in parallel simulator implementation are also discussed. The experiments are carried out on a four-CPU dual core Xeon server. Under weak consistence order model, the parallel simulator achieves a speedup of 7.2X comparing with the sequential one.
31522150
Hardware Support for Arithmetic Units of Processor with Multimedia Extension
Multimedia extension technique is very popular in designing processors to improve multimedia processing performance. This paper carries on the study of hardware implementation of arithmetic units with multimedia extension support, and proposes new design methods for subword multiplier and SIMD (single instruction multiple data) IEEE FPU (floating-point unit). To verify the correctness and effectiveness of these methods, a multimedia coprocessor with SIMD fixed-point and floating-point units is designed. The implemented chip successfully demonstrates that the proposed SIMD Arithmetic units get good tradeoff between cost and performance.
40046861
A New CORDIC Algorithm and Software Implementation Based on Synchronized Data Triggering Architecture
A new CORDIC algorithm based on sign bits prediction is presented. It is an effective method for transforming arbitrary iterations of classic CORDIC to simple matrix multiplications. At the same time, this algorithm is implemented based on synchronized data triggering architecture (SDTA). Experimental results show that the average speed-up of transcendental functions tested based on our version CORDIC compared with mathematic library supported in gcc3.2.2 is up to 283% under the given Neuron microprocessor.
13122218
Intrinsic image decomposition with non-local texture cues
We present a method for decomposing an image into its intrinsic reflectance and shading components. Different from previous work, our method examines texture information to obtain constraints on reflectance among pixels that may be distant from one another in the image. We observe that distinct points with the same intensity-normalized texture configuration generally have the same reflectance value. The separation of shading and reflectance components should thus be performed in a manner that guarantees these non-local constraints. We formulate intrinsic image decomposition by adding these non-local texture constraints to the local derivative analysis employed in conventional techniques. Our results show a significant improvement in performance, with better recovery of global reflectance and shading structure than by previous methods.
27674470
Application of Software Fault Tree Analysis to an Airport Ground Control System
With the ever increasing role of software in our day-to-day life, and even more important the criticality of their role in safety and reliability of the applications, it is important to find techniques that helps with identifying and balancing risks. One such technique is Fault Tree Analysis, which has proven to be powerful in other domains such as systems and processes. This paper, describes the results of application of the fault tree analysis to software requirement specification for an airport ground control system. In addition, this paper proposes a set of guidelines on how to apply SFTA to software requirement specification.
14826038
A Spatio-Temporal Modeling Method for Shape Representation
The spherical harmonic (SPHARM) description is a powerful surface modeling technique that can model arbitrarily shaped but simply connected three dimensional (3D) objects. Because SPHARM based 3D models can derive functional information analysis and classify different pathological symptoms, it has been used in many applications in biomedical image computing. There is an urgent requirement for efficient spatio-temporal shape modeling to represent the dynamic anatomical structures in many applications (e.g., medical image analysis, geospatial information systems). In this paper we propose a novel real spherical harmonics based spatio-temporal shape modeling method to efficiently and flexibly represent the shapes sequence of anatomical structures in medical images. Our method works well on the simply connected 3D objects and the effectiveness of our approach is demonstrated through theoretic and experimental exploration of a set of medical image applications. Furthermore, an evaluation criterion for spatio-temporal shape modeling efficiency is proposed and the comparison results showed the good performance of our method.
22846762
SCENS: a system for the mediated sharing of sensitive data
We introduce SCENS, a secure content exchange negotiation system suitable for the exchange of private digital data that reside in distributed digital repositories. SCENS is an open negotiation system with flexibility, security and scalability. SCENS is currently being designed to support data sharing in scientific research, by providing incentives and goals specific to a research community. However, it can easily be extended to apply to other communities, such as government, commercial and other types of exchanges. It is a trusted third party software infrastructure enabling independent entities to interact and conduct multiple forms of negotiation.
43366543
VLSI functional testing using critical path traces at hardware description language level
A new approach for testing VLSI circuits is presented. Through backward critical path tracing, a test and all faults detectable by the test are generated simultaneously. Therefore, the expensive fault simulation is completely eliminated. We present a critical path test generation procedure for digital systems described by hardware description language (HDL). A multiplication circuit described by a HDL is utilized for demonstrating the test generation method.