15212853
Core-aware memory access scheduling schemes
Multi-core processors have changed the conventional hardware structure and require a rethinking of system scheduling and resource management to utilize them efficiently. However, current multi-core systems are still using conventional single-core memory scheduling. In this study, we investigate and evaluate traditional memory access scheduling techniques, and propose a core-aware memory scheduling for multi-core environments. Since memory requests from the same source exhibit better locality, it is reasonable to schedule the requests by taking the source of the requests into consideration. Motivated from this principle of locality, we propose two core-aware policies based on traditional bank-first and row-first schemes. Simulation results show that the core-aware policies can effectively improve the performance. Compared with the bank-first and row-first policies, the proposed core-aware policies reduce the execution time of certain NAS Parallel Benchmarks by up to 20% in running the benchmarks separately, and by 11% in running them concurrently.
12297104
CoStore: a reliable and highly available storage system using clusters
The CoStore cluster architecture is proposed to construct a reliable and highly available storage system. A prototype CoStore was implemented and its performance was measured with the cluster being mirrored in various network environments. The preliminary results demonstrate that there is little impact on performance if the cluster is mirrored in efficient campus network environments with high bandwidth and low latency. As a result the CoStore architecture considerably reinforces a storage system's preparedness for disaster recovery without sacrificing performance.
417212
Taxonomy of Data Prefetching for Multicore Processors
Data prefetching is an effective data access latency hiding technique to mask the CPU stall caused by cache misses and to bridge the performance gap between processor and memory. With hardware and/or software support, data prefetching brings data closer to a processor before it is actually needed. Many prefetching techniques have been developed for single-core processors. Recent developments in processor technology have brought multicore processors into mainstream. While some of the single-core prefetching techniques are directly applicable to multicore processors, numerous novel strategies have been proposed in the past few years to take advantage of multiple cores. This paper aims to provide a comprehensive review of the state-of-the-art prefetching techniques, and proposes a taxonomy that classifies various design concerns in developing a prefetching strategy, especially for multicore processors. We compare various existing methods through analysis as well.
61649411
Parallel I/O prefetching using MPI file caching and I/O signatures
Parallel I/O prefetching is considered to be effective in improving I/O performance. However, the effectiveness depends on determining patterns among future I/O accesses swiftly and fetching data in time, which is difficult to achieve in general. In this study, we propose an I/O signature-based prefetching strategy. The idea is to use a predetermined I/O signature of an application to guide prefetching. To put this idea to work, we first derived a classification of patterns and introduced a simple and effective signature notation to represent patterns. We then developed a toolkit to trace and generate I/O signatures automatically. Finally, we designed and implemented a thread-based client-side collective prefetching cache layer for MPI-IO library to support prefetching. A prefetching thread reads I/O signatures of an application and adjusts them by observing I/O accesses at runtime. Experimental results show that the proposed prefetching method improves I/O performance significantly for applications with complex patterns.
43007315
The impact of smart disks and spatial reuse property on RAID-5 storage systems
RAID storage systems using SCSI and traditional disk drives cannot meet the growing demand of new I/O intensive applications. New technologies such as smart disks and SSA are being proposed to improve the performance, scalability, and reliability of RAID systems. The objective of this work is to investigate the impact of smart disks and SSA's spatial reuse property on the performance of RAID-5 storage systems. In order to perform this work, we have enhanced CMU's RAIDframe simulator so that it accurately models the overhead of current SCSI and SSA protocols, and we have created smart disk models which include on-drive XOR logic and on-drive caches. We observe that neither smart disks alone nor spatial reuse property alone has much impact on RAID system performance. However, if smart disks and spatial reuse property are properly used in combination, RAID-5 system performance and scalability can be further enhanced. In particular, we propose a parity caching approach to improve the performance of small writes.
41542415
Reliability of two-stage weighted-k-out-of-n systems with components in common
This paper extends the existing one-stage weighted-k-out-of-n model to two-stage weighted-k-out-of-n models with components in common. Algorithms are developed to calculate the system reliability, and generate the minimal cuts & minimal paths of two-stage weighted-k-out-of-n systems. Reliability bounds for systems with s-dependent component failures are investigated based on the generated minimal cuts & minimal paths. Two types of two-stage weighted-k-out-of-n models, the SW-k-out-of-n model, and the PW-k-out-of-n model, can be applied to investigate reliability issues in network applications, such as the project management, and the shortest path problems. Examples are provided to demonstrate the developed models & algorithms.
37797167
A wide dynamic range CMOS image sensor with pulse-frequency-modulation and in-pixel amplification
This paper briefly examines the pros and cons of CMOS pulse-frequency-modulation (PFM) digital pixel sensors. A pulse-frequency-modulation digital pixel sensor with in-pixel amplification is proposed to improve the resolution of the pixel sensor at low illumination. The proposed PFM digital pixel sensor offers the characteristics of a reduced integration time when the level of illumination is low with the fill factor comparable to that of PFM digital pixel sensors without in-pixel amplification. The proposed digital image sensor has been designed in [email protected] 1.8V CMOS technology and validated using Spectre from Cadence Design Systems with BSIM3V3 device models. Simulation results demonstrate that the dynamic range of the proposed PFM digital pixel sensor with in-pixel amplification is 20dB larger as compared with that of PFM digital pixel sensors without in-pixel amplification. The increased dynamic range is obtained in the low illumination condition where PFM digital pixel sensors without in-pixel amplification cease the operation due to the low photo current.
28086202
A new elliptic equation rational expansion method and its application to the shallow long wave approximate equations
A new elliptic equation rational expansion method is presented by a new general ansatz, which is a direct and unified algebraic method for constructing multiple and more general travelling wave solution for nonlinear partial differential equation and implemented in a computer algebraic system. The proposed method is applied to consider the shallow long wave approximate equation and obtains rich new families of the exact solutions, including rational form solitary wave, rational form triangular periodic, rational form Jacobi and Weierstrass doubly periodic solutions.
9130265
Wireless drive and control of a swimming microrobot
A swimming microrobot actuated by two FMP (ferromagnetic polymer) fins was developed. The robot could be driven by external magnetic field wirelessly. Fabrication process and performance of the FMP actuators were presented. Working principle and scaling effect of the robot were analyzed. Experimental results demonstrated that the microrobot could swim under the water, and the speed and direction could be controlled.
41645176
Study on Steering Control Strategy of Electric Vehicles Driven by Hub-Motors
A control strategy applied to steering control was used to an electric vehicle driven by two hub-motors, which distributes the driving torque of the driving wheels according to control of actual yaw rate. The proposed fuzzy PID controller adjusts the actual yaw rate to the desired yaw rate. Comparisons between fuzzy PID controller, PID controller and no controller are performed. Simulation results show that the performance of fuzzy PID controller is satisfactory, which is helpful to improve the steering stability.
9381578
Numerical complexiton solutions for the complex KdV equation by the homotopy perturbation method
In this paper, the homotopy perturbation method is extended to investigate the numerical complexiton solutions of the complex KdV equation. By constructing special forms of initial conditions, three new types of realistic numerical solutions are obtained: numerical positon solution expressed by the trigonometric functions, numerical negaton solution expressed by the hyperbolic functions and particularly the numerical analytical complexiton solutions expressed by combinations of the two kinds of functions. All these numerical solutions obtained can rapidly converge to the exact solutions obtained by Lou et al. Illustrative numerical figures are exhibited the efficiency of the proposed method.