33314662
Design of error-tolerant cache memory for multithreaded computing
With the trend towards nanometer billion-transistor integration, reliable computing becomes increasingly challenged by semiconductor process variations and low-level physical effects. This is particularly a problem for on-chip memory circuits. In this paper, we propose an error-tolerant memory design technique based on a unique phenomenon referred to as the inter-thread transient redundancy in multithreaded computing. A new memory microarchitecture is developed that exploits dynamic mapping strategies for compensation of unpredictable performance variations and soft errors. Trace driven simulations on the SPEC CPU2000 benchmarks show the advantages of the proposed technique for improving error tolerance in multithreaded microprocessors.
16558773
Utilizing quantum dot transistors with programmable threshold voltages for low-power mobile computing
Power consumption poses one of the fundamental barriers for deploying mobile computing devices in energy-constrained situations with varying operation conditions. In particular, leakage power is projected to increase exponentially in future semiconductor process nodes. This challenging problem is pressing for renewed focus on power-performance optimization at all levels of design abstract, from novel device structures to fundamental shifts in design paradigm. In this article, we propose to exploit the programmable threshold voltage quantum dot (QD) transistors to reduce leakage thereby improving the energy efficiency for mobile computing. The unique programmability and reconfigurability enabled by QD transistors extend our capability in design optimization for new power-performance trade-offs. Simulation results demonstrate the significant leakage reduction over conventional techniques.
36279845
Exploiting soft redundancy for error-resilient on-chip memory design
16020986
Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation
Nanoelectronic devices are considered to be the computational fabrics for the emerging nanocomputing systems due to their ultra-high speed and integration density. However, the imperfect bottom-up self-assembly fabrication leads to excessive defects that have become a barrier for achieving reliable computing. In addition, transient errors continue to be a problem. The massive parallelism rendered by nanoscale integration opens up new opportunities but also poses challenges on how to manage such massive resources for reliable and high-performance computing. In this paper, we propose a nanoarchitecture solution to address these emerging challenges. By using dynamic redundancy allocation, the massive parallelism is exploited to jointly achieve fault (defect/error) tolerance and high performance. Simulation results demonstrate the effectiveness of the proposed technique under a range of fault rates and operating conditions.
8890864
Improving Error Tolerance for Multithreaded Register Files
Chip multithreaded computing is exposed to the dual challenges of increasing system complexity and error sensitivity. It is critical to develop effective solutions that achieve better error tolerance without inducing performance degradation. In this paper, we propose a new error-tolerant memory design based on a unique computing phenomenon referred to as the dynamic multithreading redundancy (DMR). The proposed technique exploits the interplay between the concurrent threads for runtime error control. We also present two DMR enhancements, immediate write-back and self-recovery, to address the error accumulation effect. A multithreaded register file was implemented to demonstrate the proposed DMR technique. Simulation results on the SPEC CPU2000 benchmarks demonstrate significant overhead reduction in performance and energy efficiency related to error recovery. In addition, the proposed technique features good scalability with respect to the instruction-level and thread-level parallelism for next-generation processor design, where the soft error problem is expected to get worse due to technology scaling and architecture-affecting trends.
18869116
Thread-Associative Memory for Multicore and Multithreaded Computing
Presented in this paper is the thread-associative memory microarchitecture for multicore and multithreaded processor design. Memory contention among concurrent threads in chip multithreaded processing has become a limiting factor for performance improvement. The proposed thread-associative memory addresses this challenge by incorporating thread-specific information explicitly into on-chip memory hardware. The proposed technique can be utilized at different levels of memory hierarchy. Furthermore, it is not just a technique for performance enhancement but also a solution for energy efficiency. Trace-driven simulations on a 32KB L1 data cache demonstrate 36.6% maximum performance improvement and up to 15.1% total energy reduction, with 20.3% dynamic energy reduction and 9.9% leakage energy reduction
45577558
MM-Correction: Meta-analysis-Based Multiple Hypotheses Correction in Omic Studies
The post-Genomic Era is characterized by the proliferation of high-throughput platforms that allow the parallel study of a complete body of molecules in one single run of experiments (omic approach). Analysis and integration of omic data represent one of the most challenging frontiers for all the disciplines related to Systems Biology. From the computational perspective this requires, among others, the massive use of automated approaches in several steps of the complex analysis pipeline, often consisting of cascades of statistical tests. In this frame, the identification of statistical significance has been one of the early challenges in the handling of omic data and remains a critical step due to the multiple hypotheses testing issue, given the large number of hypotheses examined at one time. Two main approaches are currently used: p-values based on random permutation approaches and the False Discovery Rate. Both give meaningful and important results, however they suffer respectively from being computationally heavy -due to the large number of data that has to be generated-, or extremely flexible with respect to the definition of the significance threshold, leading to difficulties in standardization. We present here a complementary/alternative approach to these current ones and discuss performances, properties and limitations.
46712099
Side Information Inserted Pilot Tone Transmission for PAPR Reduction in OFDM
In order to reduce the peak-to-average power ratio (PAPR) of orthogonal frequency division multiplexing (OFDM) signals over fading channels, the selected mapping (SLM) scheme and channel estimation technique can be used. Because of the side information of SLM, however, the data rate decreases in the conventional transmission method. In this letter, to overcome this impairment, we propose a technique which transmits side information by using pilot tones. Numerical analysis and computer simulations show that this method can maintain the PAPR reduction ability of SLM while improving error performance.
15972722
Optimal Approximation Algorithms for Multi-agent Combinatorial Problems with Discounted Price Functions
Submodular functions are an important class of functions in combinatorial optimization which satisfy the natural properties of decreasing marginal costs. The study of these functions has led to strong structural properties with applications in many areas. Recently, there has been significant interest in extending the theory of algorithms for optimizing combinatorial problems (such as network design problem of spanning tree) over submodular functions. Unfortunately, the lower bounds under the general class of submodular functions are known to be very high for many of the classical problems. 
In this paper, we introduce and study an important subclass of submodular functions, which we call discounted price functions. These functions are succinctly representable and generalize linear cost functions. In this paper we study the following fundamental combinatorial optimization problems: Edge Cover, Spanning Tree, Perfect Matching and Shortest Path, and obtain tight upper and lower bounds for these problems. 
The main technical contribution of this paper is designing novel adaptive greedy algorithms for the above problems. These algorithms greedily build the solution whist rectifying mistakes made in the previous steps.
9035268
Optimally Balanced Forward Degree Sequence
Forward degree seqences, arising from orderings of the vertices in a graph, carry a lot of vital information about the graph. In this paper, we focus our work on two special classes of forward degree sequences, which we named balanced and strongly balanced. Our main result is to prove that any chordal graph has a strongly balanced forward degree sequence and any graph with all degrees at most 3 has a balanced forward degree sequence. Moreover, we show that the strongly balanced forward degree sequence can be computed in polynomial time in the above cases.
45286898
TMAC: Taint-Based Memory Protection via Access Control
Memory corruption attacks account for most parts of malicious attacks toward software security. Recently dynamic taint analysis is proposed and is gaining momentum. This proposed technique attempts to defeat attacks by checking the taintedness and integrity of pointers when accessing memory since vulnerabilities are always motivated by tainting pointers. Unfortunately, there exists some class of attacks without tainting pointers, such as array bounds violation attacks using pointers. In this paper, we propose a novel approach to defeat this kind of undetected attacks using taint-based tracking analysis. Our notion is based on the memory access control, that is, first, we will check the taintedness of the pointers when accessing memory like existing taint-based approaches, second, we will check whether or not the memory area is in the legitimate range of a pointer used to access this memory. Our implementation dose not need source code and is based on Valgrind, hence works on commodity software. To demonstrate our idea, we performed a preliminary empirical experiments, the results are quite promising: TMAC can effectively detect a wide range of attacks, and the average runtime overhead is close to Memcheck, a widely memory error detector.