31522150
Hardware Support for Arithmetic Units of Processor with Multimedia Extension
Multimedia extension technique is very popular in designing processors to improve multimedia processing performance. This paper carries on the study of hardware implementation of arithmetic units with multimedia extension support, and proposes new design methods for subword multiplier and SIMD (single instruction multiple data) IEEE FPU (floating-point unit). To verify the correctness and effectiveness of these methods, a multimedia coprocessor with SIMD fixed-point and floating-point units is designed. The implemented chip successfully demonstrates that the proposed SIMD Arithmetic units get good tradeoff between cost and performance.
17498280
A Hardware Approach for Reducing Interpretation Overhead
Abstract—An interpreter reads instructions of the source executable and perform each corresponding operation in turn on a software-maintained version of the old ISA’s state. Interpretation has emerged as an important tool with real world applications. Interpretation is always adopted to support instruction set emulation and handle the non-hotspot code in a two-stage dynamic binary translation strategy. An important consideration of an interpreter is the runtime overhead. We investigate that repeated re-decode operations are the bottleneck of interpretation overhead. We propose interpreted code cache (Pcache), a hardware assist, to save the information of the decoded instruction for reuse. We analyze and model Pcache performance via a real interpretation system. Results from SPEC2000 integer benchmarks show that Pcache could significantly reduce re-decode operations and the overhead of interpretation. We demonstrate that the hardware Pcache is a highly effective approach, and the extra overhead is neglectable compared to the performance gains.
60639655
Parallel simulation of chip-multiprocessor by using multi-threading
Multi-core on one chip becomes the current main trend of micro processors' architecture, and simulation plays an important role in evaluating new processor architectures. Traditional ways of sequential simulation for chip-multiprocessor (CMP) require lots of simulation time which can't be afford during processor design phase. Therefore, exploiting parallelism is necessary for speeding up the multi-core processor simulation. 
 
In this paper, we present a parallel CMP simulator, which is implemented by using POSIX threads, and also present the programming methodology for converting a sequential single core simulator to a parallel CMP simulator. Furthermore, the tradeoffs in parallel simulator implementation are also discussed. The experiments are carried out on a four-CPU dual core Xeon server. Under weak consistence order model, the parallel simulator achieves a speedup of 7.2X comparing with the sequential one.
14935665
Optimal Matrix Computing Using Vector Division with Sub-word Parallel
Available computing is expected to be effective and efficient in ubiquitous multimedia services. And, matrix multiplication is particular to ubiquitous computing such as image transformation so that it is urgent to exploit potential parallelism as well as data reuse in matrix multiplication. Therefore, based on synchronized data triggered architecture (SDTA), we propose a method of parallel vector division (PVD) as well as sub-word parallel (SWP) supported on SDTA to optimize the matrix computation on specified architecture. Experimental results show that PVD with SWP is suitable for matrix multiplication on SDTA instruction set architecture. Besides, we could extend the proposed model into other data-intensive computing on SDTA.
11412243
Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques
Compared with single-issue general purpose processors (GPPs), extensible multi-issue/VLIW processors can exploit instruction - level parallelism, which are more suitable for computation intensive tasks. Moreover, they offer the ability of customizing computation accelerators for an application domain. In this paper, we present an automated methodology that customizes computation accelerators for the multi-issue/VLIW extensible processors, where several techniques are also proposed to optimize the design of an accelerator.
33440658
A New Technique for Program Code Compression in Embedded Microprocessor
Program code compression has become a critical technology nowadays, and it can promote the performance of microprocessor systems. But compression techniques nowadays can hardly achieve both satisfactory compression ratio and low hardware complexity. A new program code compression method is proposed in this paper. Experiment results show that the code sizes of ARM and OR1200 microprocessor can be efficiently reduced by 32.2% and 36.9% individually with this algorithm, resulting to a sharp decrease in memory traffic. A hardware decompressing prototype is also presented, revealing its advantage in ultra high speed decompression and low hardware complexity.
29851215
Unified probabilistic models for face recognition from a single example image per person
This paper presents a new technique of unified probabilistic models for face recognition from only one single example image per person. The unified models, trained on an obtained training set with multiple samples per person, are used to recognize facial images from another disjoint database with a single sample per person. Variations between facial images are modeled as two unified probabilistic models: within-class variations and between-class variations. Gaussian Mixture Models are used to approximate the distributions of the two variations and exploit a classifier combination method to improve the performance. Extensive experimental results on the ORL face database and the authors' database (the ICT-JDL database) including totally 1,750 facial images of 350 individuals demonstrate that the proposed technique, compared with traditional eigenface method and some well-known traditional algorithms, is a significantly more effective and robust approach, for face recognition.
8221408
RTL concurrent fault simulation
The integrated circuit (IC) design has been pushed to hardware description language (HDL) description and high-level synthesis (HLS) techniques. The IC testing is also going to the high-level one. For the high-level testing, like gate level one, it needs a circuit model at high level such that, The model is easy to be converted and extended from the HDL descriptions. The model should be unified for multiple usages such as fault simulation, test generation, testability measure, etc. For various algorithms, it is easy to perform forward and backward tracing on the model, and easy to define fault models. In this paper, we try to construct such model and apply it to the fault simulation first.
14020196
Spherical mapping for processing of 3D closed surfaces
Abstract The spherical harmonic (SPHARM) description is a powerful surface modeling technique used by many applications in biomedical imaging. However, earlier SPHARM studies employ a spherical parameterization procedure that can be applied only to voxel surfaces. This paper presents CALD, a new spherical parameterization algorithm that makes the SPHARM model applicable to general triangle meshes. The CALD algorithm starts from an initial mapping and performs novel local and global smoothing methods alternately until a solution is approached. This new algorithm can also be used for processing of 3D closed surfaces in many different areas, including medical image analysis, computer vision, and computer graphics.
31019926
A Functional Testing Method for Microprocessors
A method is presented for functional testing of microprocessors. First, a control fault model at the RTL (register transfer language) level is developed. Based on this model, the authors establish testing requirements for control faults. They present two test procedures to verify the write and read sequences, and use the write and read sequences to test each instruction in the microprocessor. By utilizing k-out-of-m codes, they use fewer tests to cover more faults, thereby reducing the test generation time. >
22846762
SCENS: a system for the mediated sharing of sensitive data
We introduce SCENS, a secure content exchange negotiation system suitable for the exchange of private digital data that reside in distributed digital repositories. SCENS is an open negotiation system with flexibility, security and scalability. SCENS is currently being designed to support data sharing in scientific research, by providing incentives and goals specific to a research community. However, it can easily be extended to apply to other communities, such as government, commercial and other types of exchanges. It is a trusted third party software infrastructure enabling independent entities to interact and conduct multiple forms of negotiation.