35334698
Estimation et optimisation de la consommation des mémoires
This paper gives an overview of memory power and area estimation at high level of ion. First, we introduce different techniques of memory size and power estimation are presented. Finally, we show how memory can be optimized at high level to reduce power and area cost of memory unit.
5563691
Synchronization processor synthesis for latency insensitive systems
In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carloni et al. (2001). Our contribution consists in IP encapsulation into a new wrapper model whose speed and area are optimized and synthetizability guaranteed. The main benefit of our approach is to preserve the local IP performance when encapsulating them and reduce SoC silicon area.
15462003
How to transform an architectural synthesis tool for low power VLSI designs
High level synthesis (HLS) for low power VLSI design is a complex optimization problem due to the area/time/power interdependence. As few low power design tools are available, a new approach providing a modular low power synthesis method is proposed. Although based for the moment on a generic architectural synthesis tool Gaut, the use of different "commercial" tools is possible. The Gaut-w HLS tool is constituted of low power modules: high level power dissipation estimation, assignment, module selection (operators and supply voltage), optimization criteria and operators library. As illustration, power saving factors on DWT algorithms are presented.
34309839
Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems
The increasingly demanding requirements of multimedia applications have led to the definition of complex image and video coding standards such as JPEG2000 and MPEG4. Implementation of image or video encoders or decoders on mobile device requires high integration densities together with ability for "real-time" (on-the-fly) data processing. Today, the electronic system design community is mainly concerned with defining efficient System-on-a-Chip (SoC) design methodologies in order to benefit from the high integration capabilities of current application-specific integrated circuit and field-programmable gate array technologies on the one hand, and manage the increasing algorithmic complexity of applications on the other hand. Intellectual property (IP) reuse is considered as the key to speed up the system design and verification flow and make it more reliable.In this context, we have introduced a novel methodology for VLSI implementation of computation-intensive algorithms targeting digital signal processing applications. Our methodology combines IP reuse and high-level synthesis (HLS) and introduces the notion of "Behavioral IP". This approach aims at leveraging IP re-usability through functional and architectural flexibility based on: (1) modeling a component's behavior at a high abstraction level and (2) benefiting from HLS tools for architectural exploration and hardware generation.In this paper, we illustrate our methodology in the case of a 2-D discrete wavelet transform IP core for JPEG2000 image compression. We describe the successive views of the component throughout the design flow, from the application level down to the architectural level. We also provide synthesis results showing the variety of dedicated architectures that can be generated depending on user-defined functional-level, system-level and architectural-level requirements. We compare the performance and re-usability of the set of obtained architectures versus hand-crafted RTL specifications.
15834659
Architectural Synthesis with Interconnection Cost Control
Architectural synthesis tools map algorithms to architectures under various constraints and quickly provide estimations of area and performance. However, these tools do not take the interconnection cost into account whereas it becomes predominant with the technology decrease and the application complexity increase. A way to control costly interconnections during the architectural process is presented in this paper.
11449422
Functional level power analysis: an efficient approach for modeling the power consumption of complex processors
A high-level consumption estimation methodology and its associated tool, SoftExplorer, are presented. The estimation methodology uses a functional modeling of the processor combined with a parametric model to allow the designer to estimate the power consumption when the embedded software is executed on the target. SoftExplorer uses as input the assembly code generated by the compiler; its efficiency is compared to SimplePower's approach. Results for different processors (TI C62, C67, C55, and ARM7) and for several DSP applications provide an average error less than 5%.
30324632
Neural Network Based Algorithm for Radiation Dose Evaluation in Heterogeneous Environments
An efficient and accurate algorithm for radiation dose evaluation is presented in this paper. Such computations are useful in the radiotherapic treatment planning of tumors. The originality of our approach is to use a neural network which has been trained with several homogeneous environments to deduce the doses in any kind of environment (possibly heterogeneous). Our algorithm is compared in several representative contexts to a reference simulation code in the domain.
7592429
On the Convergence of Incremental Knowledge Base Construction
Ripple Down Rules is a practical methodology to build knowledge-based systems, which has proved successful in a wide range of commercial applications. However, little work has been done on its theoretical foundations. In this paper, we formalise the key features of the method. We present the process of building a correct knowledge base as a discovery scenario involving a user, an expert, and a system. The user provides data for classification. The expert helps the system to build its knowledge base incrementally, using the output of the latter in response to the last datum provided by the user. In case the system’s output is not satisfactory, the expert guides the system to improve its future performance while not affecting its ability to properly classify past data. We examine under which conditions the sequence of knowledge bases constructed by the system eventually converges to a knowledge base that faithfully represents the target classification function. Our results are in accordance with the observed behaviour of real-life systems.
980414
A General Theory of Deduction, Induction, and Learning
Deduction, induction, learning, are various aspects of a more general scientific activity: the discovery of truth. We propose to embed them in a common, logical framework. First, we define a generalized notion of "logical consequence." Alternating compact and "weakly compact" consequences, we stratify the set of generalized logical consequences of a given theory in a hierarchy. Classical first-order logic is a particular case of this framework; the fact that it is all about deduction is due to the compactness theorem, and this is reflected by the collapsing of the corresponding hierarchy to the first level. Classical learning paradigms in the inductive inference literature provide other particular cases. Finite learning corresponds exactly to the first level (or level ?1) of the hierarchy, whereas learning in the limit corresponds to another level (namely ?2). More generally, strong and natural connections exist between our hierarchy of generalized logical consequences, the Borel hierarchy, and the hierarchy which measures the complexity of a formula in terms of alternations of quantifiers. It is hoped that this framework provides the foundation of a unified logic of deduction and induction, and highlights the inductive nature of learning. An essential motivation for our work is to apply the theory presented here to the design of "Inductive Prolog", a system with both deductive and inductive capabilities, based on a natural extension of the resolution principle.
21813971
Membership Functions for Spatial Proximity
Formalising nearness has been the subject of extensive work, resulting in many membership functions based on absolute distance metrics, relative distance metrics, and combinations of those. The possible strengths and weaknesses of these functions have been discussed and argued at length, but strangely enough, no experiment seems to have been conducted to assess the merits and shortcomings of competing approaches. Conducting such experiments can be expected not only to provide an objective evaluation of the various measures that have been proposed, but also to suggest new measures that outperform all those being analysed. This paper fulfills these expectations, and gives further evidence that fuzzy logic provides fruitful and powerful methods to formalise qualitative reasoning and capture fundamental qualitative notions. The proposed fuzzy membership functions can be directly used in qualitative reasoning about spatial proximity in Geographic Information Systems, which are becoming more and more important in software development for diverse purposes such as Tourist Information Systems or property development.
29056335
Learning power and language expressiveness
The topic of the present work is to study the relationship between the power of the learning algorithms on the one hand, and the expressive power of the logical language which is used to represent the problems to be learned on the other hand. The central question is whether enriching the language results in more learning power. In order to make the question relevant and nontrivial, it is required that both texts (sequences of data) and hypotheses (guesses) be translatable from the "rich" language into the "poor" one. The issue is considered for several logical languages suitable to describe structures whose domain is the set of natural numbers. It is shown that enriching the language does not give any advantage for those languages which define a monadic second-order language being decidable in the following sense: there is a fixed interpretation in the structure of natural numbers such that the set of sentences of this extended language true in that structure is decidable. But enriching the original language even by only one constant gives an advantage if this language contains a binary function symbol (which will be interpreted as addition). Furthermore, it is shown that behaviourally correct learning has exactly the same power as learning in the limit for those languages which define a monadic second-order language with the property given above, but has more power in case of languages containing a binary function symbol. Adding the natural requirement that the set of all structures to be learned is recursively enumerable, it is shown that it pays off to enrich the language of arithmetics for both finite learning and learning in the limit, but it does not pay off to enrich the language for behaviourally correct learning.