14189733
A formal method for hardware IP design and integration under I/O and timing constraints
IP integration, which is one of the most important SoC design steps, requires taking into account communication and timing constraints. In that context, design and reuse can be improved using IP cores described at a high abstraction level. In this paper, we present an IP design approach that relies on three main phases: (1) constraint modeling, (2) IP constraint analysis steps for feasibility checking, and (3) synthesis. We propose a set of techniques dedicated to the digital signal processing domain that lead to an optimized IP core integration. Based on a generic architecture of components, the method we propose provides automatic generation of IP cores designed under integration constraints. We show the effectiveness of our approach with a DCT core design case study.
15462003
How to transform an architectural synthesis tool for low power VLSI designs
High level synthesis (HLS) for low power VLSI design is a complex optimization problem due to the area/time/power interdependence. As few low power design tools are available, a new approach providing a modular low power synthesis method is proposed. Although based for the moment on a generic architectural synthesis tool Gaut, the use of different "commercial" tools is possible. The Gaut-w HLS tool is constituted of low power modules: high level power dissipation estimation, assignment, module selection (operators and supply voltage), optimization criteria and operators library. As illustration, power saving factors on DWT algorithms are presented.
5563691
Synchronization processor synthesis for latency insensitive systems
In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carloni et al. (2001). Our contribution consists in IP encapsulation into a new wrapper model whose speed and area are optimized and synthetizability guaranteed. The main benefit of our approach is to preserve the local IP performance when encapsulating them and reduce SoC silicon area.
11449422
Functional level power analysis: an efficient approach for modeling the power consumption of complex processors
A high-level consumption estimation methodology and its associated tool, SoftExplorer, are presented. The estimation methodology uses a functional modeling of the processor combined with a parametric model to allow the designer to estimate the power consumption when the embedded software is executed on the target. SoftExplorer uses as input the assembly code generated by the compiler; its efficiency is compared to SimplePower's approach. Results for different processors (TI C62, C67, C55, and ARM7) and for several DSP applications provide an average error less than 5%.
32575594
Synthèse architecturale d'applications temps réel pour technologies submicroniques
La synthese d'architectures est un procede automatise qui facilite l'adequation algorithme architecture par l'exploration de l'espace des solutions architecturales. A partir d'une description comportementale de l'algorithme a integrer, les outils de synthese d'architectures permettent ainsi l'implantation materielle sous contraintes et fournissent rapidement des estimations de surfaces et de performances. Les outils actuels ne prennent cependant pas en compte de maniere efficace le cout des interconnexions internes aux circuits, cout qui devient predominant avec l'evolution conjointe des technologies et de la complexite des applications. Nous proposons une methode qui, a partir d'une analyse des interconnexions des le niveau comportemental et d'une modelisation de leurs parametres de couts, assure le controle des interconnexions tout au long du processus de synthese d'architectures et autorise ainsi une adequation algorithme architecture efficace a un haut niveau d'abstraction.
34309839
Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems
The increasingly demanding requirements of multimedia applications have led to the definition of complex image and video coding standards such as JPEG2000 and MPEG4. Implementation of image or video encoders or decoders on mobile device requires high integration densities together with ability for "real-time" (on-the-fly) data processing. Today, the electronic system design community is mainly concerned with defining efficient System-on-a-Chip (SoC) design methodologies in order to benefit from the high integration capabilities of current application-specific integrated circuit and field-programmable gate array technologies on the one hand, and manage the increasing algorithmic complexity of applications on the other hand. Intellectual property (IP) reuse is considered as the key to speed up the system design and verification flow and make it more reliable.In this context, we have introduced a novel methodology for VLSI implementation of computation-intensive algorithms targeting digital signal processing applications. Our methodology combines IP reuse and high-level synthesis (HLS) and introduces the notion of "Behavioral IP". This approach aims at leveraging IP re-usability through functional and architectural flexibility based on: (1) modeling a component's behavior at a high abstraction level and (2) benefiting from HLS tools for architectural exploration and hardware generation.In this paper, we illustrate our methodology in the case of a 2-D discrete wavelet transform IP core for JPEG2000 image compression. We describe the successive views of the component throughout the design flow, from the application level down to the architectural level. We also provide synthesis results showing the variety of dedicated architectures that can be generated depending on user-defined functional-level, system-level and architectural-level requirements. We compare the performance and re-usability of the set of obtained architectures versus hand-crafted RTL specifications.
10962196
Absolute versus probabilistic classification in a logical setting
Suppose we are given a set W of logical structures, or possible worlds, a set of logical formulas called possible data and a logical formula @f. We then consider the classification problem of determining in the limit and almost always correctly whether a possible world M satisfies @f, from a complete enumeration of the possible data that are true in M. One interpretation of almost always correctly is that the classification might be wrong on a set of possible worlds of measure 0, with respect to some natural probability distribution over the set of possible worlds. Another interpretation is that the classifier is only required to classify a set W^' of possible worlds of measure 1, without having to produce any claim in the limit on the truth of @f for the members of the complement of W^' in W. We compare these notions with absolute classification of W with respect to a formula that is almost always equivalent to @f in W, hence we investigate whether the set of possible worlds on which the classification is correct is definable. We mainly work with the probability distribution that corresponds to the standard measure on the Cantor space, but we also consider an alternative probability distribution proposed by Solomonoff and contrast it with the former. Finally, in the spirit of the kind of computations considered in Logic programming, we address the issue of computing almost correctly in the limit witnesses to leading existentially quantified variables in existential formulas.
980414
A General Theory of Deduction, Induction, and Learning
Deduction, induction, learning, are various aspects of a more general scientific activity: the discovery of truth. We propose to embed them in a common, logical framework. First, we define a generalized notion of "logical consequence." Alternating compact and "weakly compact" consequences, we stratify the set of generalized logical consequences of a given theory in a hierarchy. Classical first-order logic is a particular case of this framework; the fact that it is all about deduction is due to the compactness theorem, and this is reflected by the collapsing of the corresponding hierarchy to the first level. Classical learning paradigms in the inductive inference literature provide other particular cases. Finite learning corresponds exactly to the first level (or level ?1) of the hierarchy, whereas learning in the limit corresponds to another level (namely ?2). More generally, strong and natural connections exist between our hierarchy of generalized logical consequences, the Borel hierarchy, and the hierarchy which measures the complexity of a formula in terms of alternations of quantifiers. It is hoped that this framework provides the foundation of a unified logic of deduction and induction, and highlights the inductive nature of learning. An essential motivation for our work is to apply the theory presented here to the design of "Inductive Prolog", a system with both deductive and inductive capabilities, based on a natural extension of the resolution principle.
1859636
Autonomous capture of a tumbling satellite
In this paper, we describe a framework for the autonomous capture and servicing of satellites. The work is based on laboratory experiments that illustrate the autonomy and remote-operation aspects. The satellite-capture problem is representative of most on-orbit robotic manipulation tasks where the environment is known and structured, but it is dynamic since the satellite to be captured is in free flight. Bandwidth limitations and communication dropouts dominate the quality of the communication link. The satellite-servicing scenario is implemented on a robotic test-bed in laboratory settings
2402100
Input-Dependence in Function-Learning
In the standard literature on inductive inference, a learner sees as input the course of values of the function to be learned. In the present work, it is investigated how reasonable this choice is and how sensitive the model is with respect to variations like the overgraph or undergraph of the function. Several implications and separations are shown and for the basic notions, a complete picture is obtained. Furthermore, relations to oracles, additional information and teams are explored.
1889407
Sensitivity Analysis and Other Improvements to Tailored Combinatorial Library Design
"Tailoring" combinatorial libraries was developed several years ago as a very general and intuitive method to design diverse compound collections while controlling the profile of other pharmaceutically relevant properties. The candidate substituents were assigned to "categorical bins" according to their properties, and successive steps of D-optimal design were performed to generate diverse substituent sets consistent with required membership quotas from each bin. This serial algorithm was expedient to implement from existing D-optimal design codes, but was order-dependent and did not generally locate the very best possible design. A new "parallel" Fedorov search algorithm has now been implemented that can find the most diverse property-tailored design. An ambiguous mass penalty has been added, whereby most duplicate masses can be eliminated with little loss of library diversity. Sensitivity analysis has also been added to quantitatively explore the diversity trade-offs due to increasing or decreasing each specific kind of bias.