17199895
An Active Storage System for High Performance Computing
Traditionally, active storage devices execute custom application code on large amounts of data by utilizing the unused processing power of the storage nodes. For computation-intensive applications, the performance might be quite low due to insufficient processing power on the storage devices. In this paper we present a reconfigurable computing solution that can provide flexible, high-performance processing capabilities for the storage nodes. We have made a change over the existing active storage framework for object-based storage device by off loading computation-intensive request-driven services to a reconfigurable hardware accelerator. In the experiment, we use two applications (AES encryption and FFT) as the case studies, and the results show that the reconfigurable computing-based system can dramatically increase the performance comparing with the traditional software-based active storage systems.
9713230
A Direction to Avoid Re-encryption in Cryptographic File Sharing
Almost all cryptographic file sharing systems need reencryption when the sharing was revoked. These systems differ from each other only in the timing of re-encryption. As re-encryption is an expensive operation, it is significant to avoid re-encryption. The purpose of this paper is to advise a direction to avoid re-encryption and facilitate file sharing in cryptographic file sharing system. A Black-box model is set up to achieve this objective. In the model, FPGA or ASIC chips are used to act as the black-box as they have been extensively researched and applied in cryptography. Some applications of FPGA and ASIC in cryptography are detailed in this paper. Their feasibility to be functioned as the black-box is discussed. Also a software implementation on FPGA is attached with tested and effective performance.
14748203
A history sensitive cascade model in diffusion networks
Diffusion is a process by which information, viruses, ideas and new behavior spread over social networks. The traditional independent cascade model gives activated nodes a one-time chance to activate each of its neighboring nodes with some probability. This paper extends the traditional cascade model to be history dependent. We propose a new model called the History Sensitive Cascade Model (HSCM) that allows activated nodes to receive more than a one-time chance to activate their neighbors. HSCM provides 1) a polynomial algorithm for calculating the probability of activity for any arbitrary node at any arbitrary time in tree structure graphs, and 2) a Markov model for calculating the probability in general graphs. Finally, we perform an empirical study on HSCM under different network settings. These simulations have showed its power to observe and explain the emergent phenomena in the macro level when changing parameters in the micro level.
4868693
An efficient texture generation technique for human head cloning and morphing
This paper presents a technique to efficiently generate a parameterized full-head texture from a single face image of the scanned data for modeling photorealistic 3D heads. We automatically register face scans in a database by deforming a generic head mesh to fit the specific person’s face geometry with a volume morphing approach. After the face texture is transferred onto it, the 3D generic mesh is parameterized over a 2D texture domain to establish a correspondence between all the scanned textures. After having performed a vertex-toimage binding for all vertices of the head mesh, we automatically generate a full-head texture using color interpolation for unbound regions and weighted average splines for visual boundary removal. We also use a deformation method to extract ear textures from the input image for texturing individual ears. With the exception of the initial feature point selection, our method is fully automated. We show photorealistic and real-time head rendering and morphing with the resulting texture.
5930637
Parallelization of IBM mambo system simulator in functional modes
Mambo [4] is IBM's full-system simulator which models PowerPC systems, and provides a complete set of simulation tools to help IBM and its partners in pre-hardware development and performance evaluation for future systems. Currently Mambo simulates target systems on a single host thread. When the number of cores increases in a target system, Mambo's simulation performance for each core goes down. As the so-called "multi-core era" approaches, both target and host systems will have more and more cores. It is very important for Mambo to efficiently simulate a multi-core target system on a multi-core host system. Parallelization is a natural method to speed up Mambo under this situation.
 Parallel Mambo (P-Mambo) is a multi-threaded implementation of Mambo. Mambo's simulation engine is implemented as a user-level thread-scheduler. We propose a multi-scheduler method to adapt Mambo's simulation engine to multi-threaded execution. Based on this method a core-based module partition is proposed to achieve both high inter-scheduler parallelism and low inter-scheduler dependency. Protection of shared resources is crucial to both correctness and performance of P-Mambo. Since there are two tiers of threads in P-Mambo, protecting shared resources by only OS-level locks possibly introduces deadlocks due to user-level context switch. We propose a new lock mechanism to handle this problem. Since Mambo is an on-going project with many modules currently under development, co-existence with new modules is also important to P-Mambo. We propose a global-lock-based method to guarantee compatibility of P-Mambo with future Mambo modules.
 We have implemented the first version of P-Mambo in functional modes. The performance of P-Mambo has been evaluated on the OpenMP implementation of NAS Parallel Benchmark (NPB) 3.2 [12]. Preliminary experimental results show that P-Mambo achieves an average speedup of 3.4 on a 4-core host machine.
17443935
Facilitating an Active Transmit-only RFID System Through Receiver-based Processing
Many asset tracking applications demand long-lived, low-cost, and continuous monitoring of a large number of items, which has posed a significant challenge to today's RFID design. In order to satisfy these requirements, we propose to adopt transmit-only tags without a receiver, which can offer both low power and low cost. In spite of their great potential, such a platform faces many challenges since it cannot sense the channel, causing the collisions among tag transmissions to be high. It is thus crucial to employ effective multi-user detection schemes at the tag reader to extract valid information from collided signals. Traditional detection schemes, such as successive cancellation, cannot be directly applied to the targeted system. Firstly, due to the simplicity of receiver-less transmit-only tags, there is no mechanism for feedback to the tags that is traditionally needed for accurate multi-user detection. More importantly, these schemes impose serious processing and memory requirements on the underlying system, which makes real-time tracking impossible. In this study, we address these challenges by performing a statistical estimation of the signal amplitude, and by dividing the received signal sequence (from all the tags) and assigning each block to one reader. We also adopt an online learning mechanism so that readers can anticipate the tags that belong to them. We show that the proposed detection algorithm can achieve low detection error under realistic system conditions.
7672026
A power and temperature aware DRAM architecture
Technological advances enable modern processors to utilize increasingly larger DRAMs with rising access frequencies. This is leading to high power consumption and operating temperature in DRAM chips. As a result, temperature management has become a real and pressing issue in high performance DRAM systems. Traditional low power techniques are not suitable for high performance DRAM systems with high bandwidth. In this paper, we propose and evaluate a customized DRAM low power technique based on page hit aware write buffer (PHA-WB). Our proposed approach reduces DRAM system power consumption and temperature without any performance penalty. Our experiments show that a system with a 64-entry PHA-WB could reduce the total DRAM power consumption by up to 22.0% (9.6% on average). The peak and average temperature reductions are 6.1degC and 2.1degC, respectively.