40046861
A New CORDIC Algorithm and Software Implementation Based on Synchronized Data Triggering Architecture
A new CORDIC algorithm based on sign bits prediction is presented. It is an effective method for transforming arbitrary iterations of classic CORDIC to simple matrix multiplications. At the same time, this algorithm is implemented based on synchronized data triggering architecture (SDTA). Experimental results show that the average speed-up of transcendental functions tested based on our version CORDIC compared with mathematic library supported in gcc3.2.2 is up to 283% under the given Neuron microprocessor.
33440658
A New Technique for Program Code Compression in Embedded Microprocessor
Program code compression has become a critical technology nowadays, and it can promote the performance of microprocessor systems. But compression techniques nowadays can hardly achieve both satisfactory compression ratio and low hardware complexity. A new program code compression method is proposed in this paper. Experiment results show that the code sizes of ARM and OR1200 microprocessor can be efficiently reduced by 32.2% and 36.9% individually with this algorithm, resulting to a sharp decrease in memory traffic. A hardware decompressing prototype is also presented, revealing its advantage in ultra high speed decompression and low hardware complexity.
31522150
Hardware Support for Arithmetic Units of Processor with Multimedia Extension
Multimedia extension technique is very popular in designing processors to improve multimedia processing performance. This paper carries on the study of hardware implementation of arithmetic units with multimedia extension support, and proposes new design methods for subword multiplier and SIMD (single instruction multiple data) IEEE FPU (floating-point unit). To verify the correctness and effectiveness of these methods, a multimedia coprocessor with SIMD fixed-point and floating-point units is designed. The implemented chip successfully demonstrates that the proposed SIMD Arithmetic units get good tradeoff between cost and performance.
14935665
Optimal Matrix Computing Using Vector Division with Sub-word Parallel
Available computing is expected to be effective and efficient in ubiquitous multimedia services. And, matrix multiplication is particular to ubiquitous computing such as image transformation so that it is urgent to exploit potential parallelism as well as data reuse in matrix multiplication. Therefore, based on synchronized data triggered architecture (SDTA), we propose a method of parallel vector division (PVD) as well as sub-word parallel (SWP) supported on SDTA to optimize the matrix computation on specified architecture. Experimental results show that PVD with SWP is suitable for matrix multiplication on SDTA instruction set architecture. Besides, we could extend the proposed model into other data-intensive computing on SDTA.
17498280
A Hardware Approach for Reducing Interpretation Overhead
Abstract—An interpreter reads instructions of the source executable and perform each corresponding operation in turn on a software-maintained version of the old ISA’s state. Interpretation has emerged as an important tool with real world applications. Interpretation is always adopted to support instruction set emulation and handle the non-hotspot code in a two-stage dynamic binary translation strategy. An important consideration of an interpreter is the runtime overhead. We investigate that repeated re-decode operations are the bottleneck of interpretation overhead. We propose interpreted code cache (Pcache), a hardware assist, to save the information of the decoded instruction for reuse. We analyze and model Pcache performance via a real interpretation system. Results from SPEC2000 integer benchmarks show that Pcache could significantly reduce re-decode operations and the overhead of interpretation. We demonstrate that the hardware Pcache is a highly effective approach, and the extra overhead is neglectable compared to the performance gains.
60639655
Parallel simulation of chip-multiprocessor by using multi-threading
Multi-core on one chip becomes the current main trend of micro processors' architecture, and simulation plays an important role in evaluating new processor architectures. Traditional ways of sequential simulation for chip-multiprocessor (CMP) require lots of simulation time which can't be afford during processor design phase. Therefore, exploiting parallelism is necessary for speeding up the multi-core processor simulation. 
 
In this paper, we present a parallel CMP simulator, which is implemented by using POSIX threads, and also present the programming methodology for converting a sequential single core simulator to a parallel CMP simulator. Furthermore, the tradeoffs in parallel simulator implementation are also discussed. The experiments are carried out on a four-CPU dual core Xeon server. Under weak consistence order model, the parallel simulator achieves a speedup of 7.2X comparing with the sequential one.
45019016
A Simplified Algorithm for Testing Microprocessors
Abstract In this paper, we present a number of algorithms to test the instruction decoding function of microprocessors. The algorithms are based on the knowledge of some timing and control information available to users through microprocessor manuals and data sheets. The tests are functional in nature. We also establish the order of complexity of the algorithms presented in this paper. As an example, the test complexity for a microprocessor is computed and the results are compared with a known algorithm.
31075540
Reducing multiclass cancer classification to binary by output coding and SVM
Multiclass cancer classification based on microarray data is presented. The binary classifiers used combine support vector machines with a generalized output-coding scheme. Different coding strategies, decoding functions and feature selection methods are incorporated and validated on two cancer datasets: GCM and ALL. Using random coding strategy and recursive feature elimination, the testing accuracy achieved is as high as 83% on GCM data with 14 classes. Comparing with other classification methods, our method is superior in classificatory performance.
6859814
Three-dimensional Models for Cardiac Bioelectricity Simulation: Cell to Organ
Computer models of the heart have become useful tools in improving understanding of cardiac electrical activation at the cellular level, and in analyzing mechanisms of arrhythmias and antiarrhythmic therapies. In this paper, we propose to use spherical harmonic (SPHARM) surface reconstruction and alignment methods to generate curvilinear meshes for finite element models of ventricular anatomy which incorporate detailed structural information. The endocardial and epicardial surfaces are defined by SPHARM, and the volume between these surfaces is divided into nested shells. Consequently, the resulting mesh comprises hexahedral elements. Using this novel SPHARM-based meshing method, the transmembrane potential propagation is simulated, based on FitzHugh—Nagumo reaction—diffusion equations. The dynamic electrical activation propagations are simulated on realistic cardiac data during a heart cycle. The obtained results clearly demonstrate an accurate resolution of the cardiac potential during the excitation. Our novel curvilinear mesh models have a great potential to be used in an improved simulation of cardiovascular pathologies for testing therapy strategies and planning interventions.
8150561
K-means+ method for improving gene selection for classification of microarray data
Microarray gene expression techniques have recently made it possible to offer phenotype classification of many diseases. One problem in this analysis is that each sample is represented by quite a large number of genes, and many of them are insignificant or redundant to clarify the disease problem. The previous work has shown that selecting informative genes from microarray data can improve the accuracy of classification. Clustering methods have been successfully applied to group similar genes and select informative genes from them to avoid redundancy and extract biological information from them. A problem with these approaches is that the number of clusters must be given and it is time-consuming to fry all possible numbers for clusters. In this paper, a heuristic, called K-means+, is used to address the number of clusters dependency and degeneracy problems. The result of our experiments shows that K-means+ method can automatically partition genes into a reasonable number of clusters and then the informative genes are selected from clusters.
8270756
MetaDL: A Digital Library of Metadata for Sensitive or Complex Research Data
Traditional digital library systems have certain limitations when dealing with complex or sensitive (e.g. proprietary) data. Collections of digital libraries have to be accessed individually and through non-uniform interfaces. By introducing a level of abstraction, a Meta-Digital Library or MetaDL, users gain a central access portal that allows for prioritized queries, evaluation and rating of the results, and secure negotiations to obtain primary data. This paper demonstrates the MetaDL architecture with an application in brain imaging research, BrassDL, the Brain Support Access System Digital Library. BrassDL is currently under development. This paper describes a theoretical framework behind it, addressing aspects from metadata extraction and system-supported negotiations to legal, ethical and sustainability issues.