11412243
Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques
Compared with single-issue general purpose processors (GPPs), extensible multi-issue/VLIW processors can exploit instruction - level parallelism, which are more suitable for computation intensive tasks. Moreover, they offer the ability of customizing computation accelerators for an application domain. In this paper, we present an automated methodology that customizes computation accelerators for the multi-issue/VLIW extensible processors, where several techniques are also proposed to optimize the design of an accelerator.
60639655
Parallel simulation of chip-multiprocessor by using multi-threading
Multi-core on one chip becomes the current main trend of micro processors' architecture, and simulation plays an important role in evaluating new processor architectures. Traditional ways of sequential simulation for chip-multiprocessor (CMP) require lots of simulation time which can't be afford during processor design phase. Therefore, exploiting parallelism is necessary for speeding up the multi-core processor simulation. 
 
In this paper, we present a parallel CMP simulator, which is implemented by using POSIX threads, and also present the programming methodology for converting a sequential single core simulator to a parallel CMP simulator. Furthermore, the tradeoffs in parallel simulator implementation are also discussed. The experiments are carried out on a four-CPU dual core Xeon server. Under weak consistence order model, the parallel simulator achieves a speedup of 7.2X comparing with the sequential one.
17498280
A Hardware Approach for Reducing Interpretation Overhead
Abstract—An interpreter reads instructions of the source executable and perform each corresponding operation in turn on a software-maintained version of the old ISA’s state. Interpretation has emerged as an important tool with real world applications. Interpretation is always adopted to support instruction set emulation and handle the non-hotspot code in a two-stage dynamic binary translation strategy. An important consideration of an interpreter is the runtime overhead. We investigate that repeated re-decode operations are the bottleneck of interpretation overhead. We propose interpreted code cache (Pcache), a hardware assist, to save the information of the decoded instruction for reuse. We analyze and model Pcache performance via a real interpretation system. Results from SPEC2000 integer benchmarks show that Pcache could significantly reduce re-decode operations and the overhead of interpretation. We demonstrate that the hardware Pcache is a highly effective approach, and the extra overhead is neglectable compared to the performance gains.
40046861
A New CORDIC Algorithm and Software Implementation Based on Synchronized Data Triggering Architecture
A new CORDIC algorithm based on sign bits prediction is presented. It is an effective method for transforming arbitrary iterations of classic CORDIC to simple matrix multiplications. At the same time, this algorithm is implemented based on synchronized data triggering architecture (SDTA). Experimental results show that the average speed-up of transcendental functions tested based on our version CORDIC compared with mathematic library supported in gcc3.2.2 is up to 283% under the given Neuron microprocessor.
14935665
Optimal Matrix Computing Using Vector Division with Sub-word Parallel
Available computing is expected to be effective and efficient in ubiquitous multimedia services. And, matrix multiplication is particular to ubiquitous computing such as image transformation so that it is urgent to exploit potential parallelism as well as data reuse in matrix multiplication. Therefore, based on synchronized data triggered architecture (SDTA), we propose a method of parallel vector division (PVD) as well as sub-word parallel (SWP) supported on SDTA to optimize the matrix computation on specified architecture. Experimental results show that PVD with SWP is suitable for matrix multiplication on SDTA instruction set architecture. Besides, we could extend the proposed model into other data-intensive computing on SDTA.
33440658
A New Technique for Program Code Compression in Embedded Microprocessor
Program code compression has become a critical technology nowadays, and it can promote the performance of microprocessor systems. But compression techniques nowadays can hardly achieve both satisfactory compression ratio and low hardware complexity. A new program code compression method is proposed in this paper. Experiment results show that the code sizes of ARM and OR1200 microprocessor can be efficiently reduced by 32.2% and 36.9% individually with this algorithm, resulting to a sharp decrease in memory traffic. A hardware decompressing prototype is also presented, revealing its advantage in ultra high speed decompression and low hardware complexity.
14020196
Spherical mapping for processing of 3D closed surfaces
Abstract The spherical harmonic (SPHARM) description is a powerful surface modeling technique used by many applications in biomedical imaging. However, earlier SPHARM studies employ a spherical parameterization procedure that can be applied only to voxel surfaces. This paper presents CALD, a new spherical parameterization algorithm that makes the SPHARM model applicable to general triangle meshes. The CALD algorithm starts from an initial mapping and performs novel local and global smoothing methods alternately until a solution is approached. This new algorithm can also be used for processing of 3D closed surfaces in many different areas, including medical image analysis, computer vision, and computer graphics.
14116656
The design and implementation of a program development system based on rewriting method
In this paper, we present a program development system based on rewriting method with the goal of providing an powerful tool for automatic software development and rapid prototyping. New mechanisms for defining constrained types and optimal rules are introduced to functional programming languages to achieve strong expressiveness. The enhanced functional programming language is combined with an algebraic specification language. Thus, the design from specification to program can be supported, and the efficiency and flexibility of programming can also be improved. In this system, both static and dynamic techniques are used to deal with constrained type check. All function definitions, computation constraints and optimal rules are regarded as rewriting rules. In order to provide a strong support for a large group of TRSs which may be neither terminating nor orthogonal, we propose a method using structure measure to decide TRSs' confluences. Based on this method, we present a partial completion algorithm to generate a rewriting model from a specification. Depending on term rewriting system, the mixed language system computes with parallel outermost and needed reduction. We explain the principles and implementation techniques in detail, some examples are provided.
17743882
Morphometric Analysis of Brain Structures for Improved Discrimination
We perform discriminative analysis of brain structures using morphometric information. Spherical harmonics technique and point distribution model are used for shape description. Classification is performed using linear discriminants and support vector machines with several feature selection approaches. We consider both inclusion and exclusion of volume information in the discrimination. We perform extensive experimental studies by applying different combinations of techniques to hippocampal data in schizophrenia and achieve best jackknife classification accuracies of 95% (whole set) and 90% (right-handed males), respectively. Our results find that the left hippocampus is a better predictor than the right in the complete dataset, but that the right hippocampus is a stronger predictor than the left in the right-handed male subset. We also propose a new method for visualization of discriminative patterns.
6802677
A surface-based approach for classification of 3D neuroanatomic structures
We present a new framework for 3D surface object classification that combines a powerful shape description method with suitable pattern classification techniques. Spherical harmonic parameterization and normalization techniques are used to describe a surface shape and derive a dual high dimensional landmark representation. A point distribution model is applied to reduce the dimensionality. Fisher's linear discriminants and support vector machines are used for classification. Several feature selection schemes are proposed for learning better classifiers. After showing the effectiveness of this framework using simulated shape data, we apply it to real hippocampal data in schizophrenia and perform extensive experimental studies by examining different combinations of techniques. We achieve best leave-one-out cross-validation accuracies of 93% (whole set, N = 56) and 90% (right-handed males, N = 39), respectively, which are competitive with the best results in previous studies using different techniques on similar types of data. Furthermore, to help medical diagnosis in practice, we employ a threshold-free receiver operating characteristic (ROC) approach as an alternative evaluation of classification results as well as propose a new method for visualizing discriminative patterns.
8221408
RTL concurrent fault simulation
The integrated circuit (IC) design has been pushed to hardware description language (HDL) description and high-level synthesis (HLS) techniques. The IC testing is also going to the high-level one. For the high-level testing, like gate level one, it needs a circuit model at high level such that, The model is easy to be converted and extended from the HDL descriptions. The model should be unified for multiple usages such as fault simulation, test generation, testability measure, etc. For various algorithms, it is easy to perform forward and backward tracing on the model, and easy to define fault models. In this paper, we try to construct such model and apply it to the fault simulation first.