13024197
Joint Performance Improvement and Error Tolerance for Memory Design Based on Soft Indexing
Memory design is facing the dual challenges of performance improvement and error tolerance due to a combination of technology scaling and higher levels of integration. To address these challenges, we propose a new memory microarchitecture referred to as the soft indexing. The proposed technique allocates memory resources in a self-adaptive manner in accordance with runtime program variations, thereby achieving efficient memory access and effective error protection in a coherent manner. Statistical analysis shows 10times improvement in error detection capability over the existing error-control techniques. The benefits of the proposed technique are also experimentally demonstrated using the SPEC CPU2000 benchmarks. Simulation results show 94.9% average error-control coverage on the 23 benchmarks, with average of 23.2% reduction in memory miss rates as compared to the conventional techniques.
6708583
Reducing error accumulation effect in multithreaded memory systems
Chip multithreading is exposed to dual challenges of increasing chip complexity and design variations. It is important to develop effective reliability-enhancing schemes to ensure robust computing. In this paper, we propose the immediate write-back and self-recovery schemes to reduce error accumulation effect in multithreaded memory systems. These schemes are built upon the previously proposed dynamic multithreading redundancy technique for improving reliability in multithreaded architectures. The idea of DMR is to exploit self-generated hardware redundancy due to inter-thread variations inherent in multithreaded architectures. Simulation results demonstrate that the proposed solutions improve error-control performance with minimal hardware overheads. The proposed immediate write-back and self-recovery schemes also feature good scalability for future process generations
8890864
Improving Error Tolerance for Multithreaded Register Files
Chip multithreaded computing is exposed to the dual challenges of increasing system complexity and error sensitivity. It is critical to develop effective solutions that achieve better error tolerance without inducing performance degradation. In this paper, we propose a new error-tolerant memory design based on a unique computing phenomenon referred to as the dynamic multithreading redundancy (DMR). The proposed technique exploits the interplay between the concurrent threads for runtime error control. We also present two DMR enhancements, immediate write-back and self-recovery, to address the error accumulation effect. A multithreaded register file was implemented to demonstrate the proposed DMR technique. Simulation results on the SPEC CPU2000 benchmarks demonstrate significant overhead reduction in performance and energy efficiency related to error recovery. In addition, the proposed technique features good scalability with respect to the instruction-level and thread-level parallelism for next-generation processor design, where the soft error problem is expected to get worse due to technology scaling and architecture-affecting trends.
16020986
Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation
Nanoelectronic devices are considered to be the computational fabrics for the emerging nanocomputing systems due to their ultra-high speed and integration density. However, the imperfect bottom-up self-assembly fabrication leads to excessive defects that have become a barrier for achieving reliable computing. In addition, transient errors continue to be a problem. The massive parallelism rendered by nanoscale integration opens up new opportunities but also poses challenges on how to manage such massive resources for reliable and high-performance computing. In this paper, we propose a nanoarchitecture solution to address these emerging challenges. By using dynamic redundancy allocation, the massive parallelism is exploited to jointly achieve fault (defect/error) tolerance and high performance. Simulation results demonstrate the effectiveness of the proposed technique under a range of fault rates and operating conditions.
36279845
Exploiting soft redundancy for error-resilient on-chip memory design
18869116
Thread-Associative Memory for Multicore and Multithreaded Computing
Presented in this paper is the thread-associative memory microarchitecture for multicore and multithreaded processor design. Memory contention among concurrent threads in chip multithreaded processing has become a limiting factor for performance improvement. The proposed thread-associative memory addresses this challenge by incorporating thread-specific information explicitly into on-chip memory hardware. The proposed technique can be utilized at different levels of memory hierarchy. Furthermore, it is not just a technique for performance enhancement but also a solution for energy efficiency. Trace-driven simulations on a 32KB L1 data cache demonstrate 36.6% maximum performance improvement and up to 15.1% total energy reduction, with 20.3% dynamic energy reduction and 9.9% leakage energy reduction
38516500
A New Approach of Network Intrusion Detection Using HVDM-Based SOM
The research of applying Self-organizing Maps for intrusion detection is investigated in this paper. A novel approach is presented for enhancing SOM's abilities of identifying temporal network attacks, which combine with FIR filter. Meanwhile, we reconsider the heterogeneous dataset that composed of network connection's features, and select HVDM as the distance function determining the winning neuron during SOM's training and testing. In the end, KDD benchmark dataset is employed to validate the efficiency of our approach, and the results is detection rates of 96.5%, false positive rates of 6.2%, which accounts for good performance of our new approach in intrusion detection fields.
45286898
TMAC: Taint-Based Memory Protection via Access Control
Memory corruption attacks account for most parts of malicious attacks toward software security. Recently dynamic taint analysis is proposed and is gaining momentum. This proposed technique attempts to defeat attacks by checking the taintedness and integrity of pointers when accessing memory since vulnerabilities are always motivated by tainting pointers. Unfortunately, there exists some class of attacks without tainting pointers, such as array bounds violation attacks using pointers. In this paper, we propose a novel approach to defeat this kind of undetected attacks using taint-based tracking analysis. Our notion is based on the memory access control, that is, first, we will check the taintedness of the pointers when accessing memory like existing taint-based approaches, second, we will check whether or not the memory area is in the legitimate range of a pointer used to access this memory. Our implementation dose not need source code and is based on Valgrind, hence works on commodity software. To demonstrate our idea, we performed a preliminary empirical experiments, the results are quite promising: TMAC can effectively detect a wide range of attacks, and the average runtime overhead is close to Memcheck, a widely memory error detector.
14307736
Positive Semidefinite Metric Learning with Boosting
The learning of appropriate distance metrics is a critical problem in image classification and retrieval. In this work, we propose a boosting-based technique, termed BOOSTMETRIC, for learning a Mahalanobis distance metric. One of the primary difficulties in learning such a metric is to ensure that the Mahalanobis matrix remains positive semidefinite. Semidefinite programming is sometimes used to enforce this constraint, but does not scale well. BOOSTMETRIC is instead based on a key observation that any positive semidefinite matrix can be decomposed into a linear positive combination of trace-one rank-one matrices. BOOSTMETRIC thus uses rank-one positive semidefinite matrices as weak learners within an efficient and scalable boosting-based learning process. The resulting method is easy to implement, does not require tuning, and can accommodate various types of constraints. Experiments on various datasets show that the proposed algorithm compares favorably to those state-of-the-art methods in terms of classification accuracy and running time.
7481401
Noise-tolerant dynamic circuit design
Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energy efficiency of VLSI systems in the deep submicron era. To address this problem, a new noise-tolerant dynamic circuit technique is presented. In addition, the average noise threshold energy (ANTE) and the energy normalized ANTE metrics are proposed for quantifying the noise immunity and energy efficiency, respectively, of circuit techniques. Simulation results in 0.35 micron CMOS for NAND gate designs indicate that the proposed technique improves the ANTE and energy normalized ANTE by 2.54X and 2.25X over the conventional domino circuit. The improvement in energy normalized ANTE is 1.22X higher than the existing noise-tolerance techniques. A full adder design based on the proposed technique improves the ANTE and energy normalized ANTE by 3.7X and 1.95X over the conventional dynamic circuit. In comparison, the static circuit improves ANTE by 2.2X but degrades the energy normalized ANTE by 11%. In addition, the proposed technique has a smaller area overhead (69%) as compared to the static circuit whose area overhead is 98%.
45238482
TengYue-1TengYue: In Chinese means jump over.: A High Performance Embedded SoC