9664247
Static Address Generation Easing: a design methodology for parallel interleaver architectures
For high throughput applications, turbo-like iterative decoders are implemented with parallel architectures. However, to be efficient parallel architectures require to avoid collision accesses i.e. concurrent read/write accesses should not target the same memory block. This consideration applies to the two main classes of turbo-like codes which are Low Density Parity Check (LDPC) and Turbo-Codes. In this paper we propose a methodology which finds a collision-free mapping of the variables in the memory banks and which optimizes the resulting interleaving architecture. Finally, we show through a pedagogical example the interest of our approach compared to state-of-the-art techniques.
34309839
Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems
The increasingly demanding requirements of multimedia applications have led to the definition of complex image and video coding standards such as JPEG2000 and MPEG4. Implementation of image or video encoders or decoders on mobile device requires high integration densities together with ability for "real-time" (on-the-fly) data processing. Today, the electronic system design community is mainly concerned with defining efficient System-on-a-Chip (SoC) design methodologies in order to benefit from the high integration capabilities of current application-specific integrated circuit and field-programmable gate array technologies on the one hand, and manage the increasing algorithmic complexity of applications on the other hand. Intellectual property (IP) reuse is considered as the key to speed up the system design and verification flow and make it more reliable.In this context, we have introduced a novel methodology for VLSI implementation of computation-intensive algorithms targeting digital signal processing applications. Our methodology combines IP reuse and high-level synthesis (HLS) and introduces the notion of "Behavioral IP". This approach aims at leveraging IP re-usability through functional and architectural flexibility based on: (1) modeling a component's behavior at a high abstraction level and (2) benefiting from HLS tools for architectural exploration and hardware generation.In this paper, we illustrate our methodology in the case of a 2-D discrete wavelet transform IP core for JPEG2000 image compression. We describe the successive views of the component throughout the design flow, from the application level down to the architectural level. We also provide synthesis results showing the variety of dedicated architectures that can be generated depending on user-defined functional-level, system-level and architectural-level requirements. We compare the performance and re-usability of the set of obtained architectures versus hand-crafted RTL specifications.
11449422
Functional level power analysis: an efficient approach for modeling the power consumption of complex processors
A high-level consumption estimation methodology and its associated tool, SoftExplorer, are presented. The estimation methodology uses a functional modeling of the processor combined with a parametric model to allow the designer to estimate the power consumption when the embedded software is executed on the target. SoftExplorer uses as input the assembly code generated by the compiler; its efficiency is compared to SimplePower's approach. Results for different processors (TI C62, C67, C55, and ARM7) and for several DSP applications provide an average error less than 5%.
15462003
How to transform an architectural synthesis tool for low power VLSI designs
High level synthesis (HLS) for low power VLSI design is a complex optimization problem due to the area/time/power interdependence. As few low power design tools are available, a new approach providing a modular low power synthesis method is proposed. Although based for the moment on a generic architectural synthesis tool Gaut, the use of different "commercial" tools is possible. The Gaut-w HLS tool is constituted of low power modules: high level power dissipation estimation, assignment, module selection (operators and supply voltage), optimization criteria and operators library. As illustration, power saving factors on DWT algorithms are presented.
15834659
Architectural Synthesis with Interconnection Cost Control
Architectural synthesis tools map algorithms to architectures under various constraints and quickly provide estimations of area and performance. However, these tools do not take the interconnection cost into account whereas it becomes predominant with the technology decrease and the application complexity increase. A way to control costly interconnections during the architectural process is presented in this paper.
5563691
Synchronization processor synthesis for latency insensitive systems
In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carloni et al. (2001). Our contribution consists in IP encapsulation into a new wrapper model whose speed and area are optimized and synthetizability guaranteed. The main benefit of our approach is to preserve the local IP performance when encapsulating them and reduce SoC silicon area.
38643151
Learning from Each Other
Since its inception, the field of machine learning has seen the advent of several learning paradigms, designed to frame the issues central to the learning activity, provide effective learning methods, and investigate the power and limitations inherent to the process of successful learning. In this article, we propose a formalization that underlies the key concepts of many such paradigms and discuss their relevance to scientific discovery, with the aim of assessing what scientists can expect from machines designed to assist them in their quest for the discovery of valid laws. We illustrate the formalization on several variations of a card game, and highlight the differences that paradigms impose on learners, as well as the assumptions they make on the nature of the learning process. We then use the formalization to describe a multi-agent interaction protocol, that has been inspired by these paradigms and that has been validated recently on some groups of agents. Finally, we propose extensions to this protocol.
39139980
On Sufficient Conditions for Learnability of Logic Programs from Positive Data
Shinohara, Arimura, and Krishna Rao have shown learnability in the limit of minimal models of classes of logic programs from positive only data. In most cases, these results involve logic programs in which the "size" of the head yields a bound on the size of the body literals. However, when local variables are present, such a bound on body literal size cannot directly be ensured. The above authors achieve such a restriction using technical notions like mode and linear inequalities. The present paper develops a conceptually clean framework where the behavior of local variables is controlled by nonlocal ones. It is shown that for certain classes of logic programs, learnablity from positive data is equivalent to limiting identification of bounds for the number of clauses and the number of local variables. This reduces the learning problem finding two integers. This cleaner framework generalizes all the known results and establishes learnability of new classes.
36905391
A note on the use of probabilities by mechanical learners
We raise the following problem: in a probabilistic context, is it always fruitful for a machine to compute probabilities? The question is made precise in a paradigm of the limit-identification kind, where a learner must discover almost surely whether an infinite sequence of heads and tails belongs to an effective subset S of the Cantor space. In this context, a successful strategy for an ineffective learner is to compute, at each stage, the conditional probability that he is faced with an element of S, given the data received so far. We show that an effective learner should not proceed this way in all circumstances. Indeed, even if he gets an optimal description of a set S, and even if some machine can always compute the conditional probability for S given any data, an effective learner optimizes his inductive competence only if he does not compute the relevant probabilities. We conclude that the advice “compute probabilities whenever you can” should sometimes be received with caution in the context of machine learning.
30324632
Neural Network Based Algorithm for Radiation Dose Evaluation in Heterogeneous Environments
An efficient and accurate algorithm for radiation dose evaluation is presented in this paper. Such computations are useful in the radiotherapic treatment planning of tumors. The originality of our approach is to use a neural network which has been trained with several homogeneous environments to deduce the doses in any kind of environment (possibly heterogeneous). Our algorithm is compared in several representative contexts to a reference simulation code in the domain.
31898263
Limiting Resolution: From Foundations to Implementation
We present a generalization of SLD-resolution, Limiting Resolution (LR) which embeds concepts from the field of inductive inference into logic programming. This paper describes the development of LR from theoretical underpinnings through to demonstrating a practical implementation. LR is designed to represent and solve problems which are not purely deductive more easily than current logic programming formalisms. It is based on the notion of identification in the limit, where successful computations produce a non-halting converging sequence of outputs as opposed to computations which produce a single output and halt. The queries of LR are of the form \(\exists \overline{x} ( \psi(\overline{x}) \land \forall \overline{y} \neg \chi(\overline{x},\overline{y}))\), with some restrictions on the occurrence of negation in ψ and χ. The programs are divided into background knowledge and a potentially infinite stream of data which drives the construction of the converging sequence of outputs. In some problems true negation can be applied to data in this stream. We describe the logical foundations of LR, where the notions of induction, deduction and identification in the limit are unified in a common framework. The programs, queries, and proof procedure of LR are precisely defined, and a completeness result is stated. Furthermore we present a Prolog-style system, RichProlog, which implements LR, and provide an extended example of RichProlog’s execution. This example shows that it is possible to solve genuine problems in polynomial time and also illustrates RichProlog’s utility, conciseness, and declarative nature.