8631948
A Framework for Loop Distribution on Limited On-Chip Memory Processors
This work proposes a framework for analyzing the flow of values and their re-use in loop nests to minimize data traffic under the constraints of limited on-chip memory capacity and dependences. Our analysis first undertakes fusion of possible loop nests intra-procedurally and then performs loop distribution. The analysis discovers the closeness factor of two statements which is a quantitative measure of data traffic saved per unit memory occupied if the statements were under the same loop nest over the case where they are under different loop nests. We then develop a greedy algorithm which traverses the program dependence graph (PDG) to group statements together under the same loop nest legally. The main idea of this greedy algorithm is to transitively generate a group of statements that can legally execute under a given loop nest that can lead to a minimum data traffic. We implemented our framework in Petit, a tool for dependence analysis and loop transformations. We show that the benefit due to our approach results in eliminating as much as 30 % traffic in some cases improving overall completion time by a 23.33 % for processors such as TI's TMS320C5x.
11258056
Data I/O Minimization for Loops on Limited Onchip Memory Processors
Due to significant advances in VLSI technology, ‘mega-processors’ made with a large number of transistors has become a reality. These processors typically provide multiple functional units which allow exploitation of parallelism. In order to cater to the data demands associated with parallelism, the processors provide a limited amount of on-chip memory. The amount of memory provided is quite limited due to higher area and power requirements associated with it. Even though limited, such on-chip memory is a very valuable resource in memory hierarchy. An important use of on-chip memory is to hold the instructions from short loops along with the associated data for very fast computation. Such schemes are very attractive on embedded processors where, due to the presence of dedicated hard-ware on-chip (such as very fast multipliers-shifters etc.) and extremely fast accesses to on-chip data, the computation time of such loops is extremely small meeting almost all real-time demands. Biggest bottleneck to performance in these cases are off-chip accesses and thus, compilers must carefully analyze references to identify good candidates for promotion to on-chip memory. In our earlier work [6], we formulated this problem in terms of 0/1 knapsack and proposed a heuristic solution that gives us good promotion candidates. Our analysis was limited to a single loop nest. When we attempted extending this framework to multiple loop nests (intra-procedurally), we realized that not only it is important to identify good candidates for promotion but a careful restructuring of loops must be undertaken before performing promotion since data i/o of loading and storing values to on-chip memory poses a significant bottleneck.
15142417
Low-Complexity Analysis of Repetitive Regularities for Biometric Applications
Presented in this paper is a joint algorithm optimization and architecture design framework for analysis of repetitive regularities. Two closely coupled algorithm optimization techniques, referred to as the prime subspace periodicity transform (PSPT) and circular periodicity transform (CPT), are developed that significantly reduce computational complexity while enable the extraction of a wide spectrum of periodic features. The proposed PSPTCPT algorithms lead to a parallel and resource sharing VLSI architecture. While most of the current systems rely on software solutions to performance feature extraction, the performance benefits rendered by the proposed framework show advantages in dealing with data-intensive computation for emerging applications in biometrics and bioinformatics. The explosive growth in database complexity combined with demand for fast analysis make the proposed framework a promising solution. Experimental results on an iris identification system demonstrate up to 99.2% accuracy and 24.6% − 41.9% reduction in computational complexity.
9617216
Achieving Scalable Parallel Molecular Dynamics Using Dynamic Spatial Domain Decomposition Techniques
To achieve scalable parallel performance in molecular dynamics simulations, we have modeled and implemented several dynamic spatial domain decomposition algorithms. The modeling is based upon the bulk synchronous parallel architecture model (BSP), which describes supersteps of computation, communication, and synchronization. Using this model, we have developed prototypes that explore the differing costs of several spatial decomposition algorithms and then use this data to drive implementation of our molecular dynamics simulator,Sigma. The parallel implementation is not bound to the limitations of the BSP model, allowing us to extend the spatial decomposition algorithm. For an initial decomposition, we use one of the successful decomposition strategies from the BSP study and then subsequently use performance data to adjust the decomposition, dynamically improving the load balance. The motivating reason to use historical performance data is that the computation to predict a better decomposition increases in cost with the quality of prediction, while the measurement of past work often has hardware support, requiring only a slight amount of work to modify the decomposition for future simulation steps. In this paper, we present our adaptive spatial decomposition algorithms, the results of modeling them with the BSP, the enhanced spatial decomposition algorithm, and its performance results on computers available locally and at the national supercomputer centers.
38710648
A Resource Allocating Neural Network Based Approach for Detecting End-to-End Network Performance Anomaly
Automatic detection of end-to-end network performance anomalies is important to efficient network management and optimization. We present an end-to-end network performance anomalies detection method, based on characterizing of the dynamic statistical properties of RTT normality. The experiment on real Internet end-to-end path RTT data shows that, the proposed method is accurate in detecting performance anomalies, it can successfully detect about 96.25% anomalies in the experiment.
7324862
A New Description Language for Data-Driven Asynchronous Circuits and its Design Flow
A lot of up-to-date asynchronous circuit design tools are based on the control-driven asynchronous circuit style, such as Balsa and Haste/Tangram. The control-driven approach will limit the performance of the result circuits. To improve the performance of the asynchronous circuits, a new description language - Biscotti, which is suitable for the data-driven asynchronous circuit design, has been introduced in this paper. And a data-driven asynchronous circuit design flow is also be presented here. The experimental results show that this design flow is a fast and efficient way to design the data-driven asynchronous circuit, which can achieve higher performance compared with the control-driven design approach.
17936922
A call admission control scheme for packet data in CDMA cellular communications
In wireless cellular communication systems, call admission control (CAC) is to ensure satisfactory services for mobile users and maximize the utilization of the limited radio spectrum. In this paper, we propose a new CAC scheme for a code division multiple access (CDMA) wireless cellular network supporting heterogeneous self-similar data traffic. In addition to ensuring transmission accuracy at the bit level, the CAC scheme guarantees service requirements at both the call level and the packet level. The grade of service (GoS) at the call level and the quality of service (QoS) at the packet level are evaluated using the handoff call dropping probability and the packet transmission delay, respectively. The effective bandwidth approach for data traffic is applied to guarantee QoS requirements. Handoff probability and cell overload probability are derived via the traffic aggregation method. The two probabilities are used to determine the handoff call dropping probability, and the GoS requirement can be guaranteed on a per call basis. Numerical analysis and computer simulation results demonstrate that the proposed CAC scheme can meet both QoS and GoS requirements and achieve efficient resource utilization.