7862909
A Study of Side-Channel Effects in Reliability-Enhancing Techniques
Reliability-enhancing techniques are critical for nanoscale integrated systems under the pressure of various physical non-idealities such as process variations and manufacturing defects. However, it is unclear how these techniques will affect the side-channel information leaked through hardware implementations. The related side-channel effects may have direct implications to the security requirement in a wide range of applications. In this paper, we investigate this new problem for trusted hardware design. Employing information-theoretic measures, the relationship between reliability enhancements and the induced side-channel effects is quantitatively evaluated. Simulation results on EDC/ECC schemes in memory circuits are presented to demonstrate the application of the proposed method.
6708583
Reducing error accumulation effect in multithreaded memory systems
Chip multithreading is exposed to dual challenges of increasing chip complexity and design variations. It is important to develop effective reliability-enhancing schemes to ensure robust computing. In this paper, we propose the immediate write-back and self-recovery schemes to reduce error accumulation effect in multithreaded memory systems. These schemes are built upon the previously proposed dynamic multithreading redundancy technique for improving reliability in multithreaded architectures. The idea of DMR is to exploit self-generated hardware redundancy due to inter-thread variations inherent in multithreaded architectures. Simulation results demonstrate that the proposed solutions improve error-control performance with minimal hardware overheads. The proposed immediate write-back and self-recovery schemes also feature good scalability for future process generations
16738561
Defect-tolerant digital filtering with unreliable molecular electronics
Molecular electronics such as silicon nanowires (NW) and carbon nanotubes (CNT) are considered to be the future computational substrates due to their ultra-high density and superior energy efficiency. However, excessive defects from bottom-up self-assembly fabrication pose a major technological barrier to achieving reliable computing at the molecular scale. Existing solutions targeting absolute correctness introduce high cost and complexity in post-fabrication testing and defect diagnosis. In this paper, we propose a new approach exploiting algorithm level enhancements for defect-insensitive signal processing. By deliberately allowing molecular-scale integrated systems to bear defects, the proposed design framework achieves reliable signal processing while significantly reduces the cost of defect tolerance.
16020986
Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation
Nanoelectronic devices are considered to be the computational fabrics for the emerging nanocomputing systems due to their ultra-high speed and integration density. However, the imperfect bottom-up self-assembly fabrication leads to excessive defects that have become a barrier for achieving reliable computing. In addition, transient errors continue to be a problem. The massive parallelism rendered by nanoscale integration opens up new opportunities but also poses challenges on how to manage such massive resources for reliable and high-performance computing. In this paper, we propose a nanoarchitecture solution to address these emerging challenges. By using dynamic redundancy allocation, the massive parallelism is exploited to jointly achieve fault (defect/error) tolerance and high performance. Simulation results demonstrate the effectiveness of the proposed technique under a range of fault rates and operating conditions.
36279845
Exploiting soft redundancy for error-resilient on-chip memory design
16558773
Utilizing quantum dot transistors with programmable threshold voltages for low-power mobile computing
Power consumption poses one of the fundamental barriers for deploying mobile computing devices in energy-constrained situations with varying operation conditions. In particular, leakage power is projected to increase exponentially in future semiconductor process nodes. This challenging problem is pressing for renewed focus on power-performance optimization at all levels of design abstract, from novel device structures to fundamental shifts in design paradigm. In this article, we propose to exploit the programmable threshold voltage quantum dot (QD) transistors to reduce leakage thereby improving the energy efficiency for mobile computing. The unique programmability and reconfigurability enabled by QD transistors extend our capability in design optimization for new power-performance trade-offs. Simulation results demonstrate the significant leakage reduction over conventional techniques.
8611890
Relevancy based semantic interoperation of reuse repositories
Software reuse is a promising solution to the software crisis. Reuse repositories are the basic infrastructure for software reuse. During the past decade, various academic, commercial, governmental, and industrial organizations have developed many Internet-enabled reuse repositories to provide access to software components and related resources. It has necessitated semantic interoperation to allow distributed maintenance and management of these repositories while enabling users to efficiently and conveniently access resources from multiple reuse repositories via a single representation view. In this paper, we have proposed an approach to enhancing the semantic interoperability of reuse repositories, called the improved relevancy matching and ranking (IRMR) method, based on analyzing the correlation of terms in representation methods of the repositories. A prototype system, the Virtual Repository supporting Semantic Interoperation (VRSI), is presented to illustrate the application of this approach to support the semantic interoperation of reuse repositories. Experimental results on real world reuse repositories demonstrated significant improvement in terms of searching effectiveness.
205393463
A new algorithm for solving classical Blasius equation
In this paper, a reliable algorithm is employed to investigate the classical Blasius equation. The algorithm is based mainly on applying the Adomian decomposition method to the transformation of the Blasius equation. The results demonstrate reliability and efficiency of the proposed algorithm.
5460989
End-To-End Worst-Case Response Time Analysis for Hard Real-Time Distributed Systems
The verification of end-to-end response time for distributed hard real-time systems is quite necessary for safety-critical applications. Although current time analysis techniques can precisely analyze the response time, the performance is not quite satisfying, especially for large size distributed systems. This paper presents a novel end-to-end worst-case response time analysis approach for hard real-time distributed systems. This technique is based on the critical instant analysis and the canonical form transformation. It extends the traditional holistic analysis technique by exploiting the precedence relations between tasks on both different processors and the same processor. Simulation results have shown that this algorithm can achieve accurate results and offers good performance for systems with wide range of CPU utilizations and task set size, and therefore is applicable to schedulability analysis of complex distributed systems.
1135112
Measurement and Statistics of Application Business in Complex Internet
Owing to independent topologies and autonomic routing mechanism, the logical networks formed by Internet application business behavior cause the significant influence on the physical networks. In this paper, the backbone traffic of TUNET (Tsinghua University Networks) is measured, further more, the two most important application business: HTTP and P2P are analyzed at IP-packet level. It is shown that uplink HTTP and P2P packets behavior presents spatio-temporal power-law characteristics with exponents 1.25 and 1.53 respectively. Downlink HTTP packets behavior also presents power-law characteristics, but has more little exponents γ = 0.82 which differs from traditional complex networks research result. Moreover, downlink P2P packets distribution presents an approximate power-law which means that flow equilibrium profits little from distributed peer-to peer mechanism actually.
14307736
Positive Semidefinite Metric Learning with Boosting
The learning of appropriate distance metrics is a critical problem in image classification and retrieval. In this work, we propose a boosting-based technique, termed BOOSTMETRIC, for learning a Mahalanobis distance metric. One of the primary difficulties in learning such a metric is to ensure that the Mahalanobis matrix remains positive semidefinite. Semidefinite programming is sometimes used to enforce this constraint, but does not scale well. BOOSTMETRIC is instead based on a key observation that any positive semidefinite matrix can be decomposed into a linear positive combination of trace-one rank-one matrices. BOOSTMETRIC thus uses rank-one positive semidefinite matrices as weak learners within an efficient and scalable boosting-based learning process. The resulting method is easy to implement, does not require tuning, and can accommodate various types of constraints. Experiments on various datasets show that the proposed algorithm compares favorably to those state-of-the-art methods in terms of classification accuracy and running time.