16738561
Defect-tolerant digital filtering with unreliable molecular electronics
Molecular electronics such as silicon nanowires (NW) and carbon nanotubes (CNT) are considered to be the future computational substrates due to their ultra-high density and superior energy efficiency. However, excessive defects from bottom-up self-assembly fabrication pose a major technological barrier to achieving reliable computing at the molecular scale. Existing solutions targeting absolute correctness introduce high cost and complexity in post-fabrication testing and defect diagnosis. In this paper, we propose a new approach exploiting algorithm level enhancements for defect-insensitive signal processing. By deliberately allowing molecular-scale integrated systems to bear defects, the proposed design framework achieves reliable signal processing while significantly reduces the cost of defect tolerance.
2723209
An energy-efficient skew compensation technique for high-speed skew-sensitive signaling
Presented in this paper is an energy-efficient skew compensation technique referred to as the resistance-based distributed clock deskew (RDSK) technique. In comparison with the existing clock deskew techniques, the proposed RDSK technique achieves significant power reduction while maintaining effective in skew management. Furthermore, the proposed RDSK provides a better scalability for future technology scaling. Simulation results of an on-chip interconnect communication system with distributed receivers designed in a 0.10 /spl mu/m CMOS process demonstrate 20%-51% power reduction over the existing techniques. The proposed RDSK is an essential element of our adaptive timing framework where circuit performance can be adjusted adaptively in response to time-varying disturbances and uncertainties.
1674451
A defect/error-tolerant nanosystem architecture for DSP
Emerging technologies such as silicon NanoWires (NW) and Carbon NanoTubes (CNT) have shown great potential for building the next generation of computing systems in the nano ranges. However, the excessive number of defects originating from bottom-up fabrication (such as a self-assembly process) poses a pressing challenge for achieving scalable system integration. This article proposes a new nanosystem architecture that employs nanowire crossbars for Digital Signal Processing (DSP) applications. Distributed arithmetic is utilized such that complex signal processing computation can be mapped into regular memory operations, thus making this architecture well suited for implementation by nanowire crossbars. Furthermore, the inherent features of DSP-type computation provide new insights to remedy errors (as logic/computational manifestation of defects). A new defect/error-tolerant technique that exploits algorithmic error compensation is proposed; at system level different trade-offs between correctness in output and performance are established while retaining low overhead in its implementation. As an instance of its application, the proposed approach has been utilized to a generic DSP nanosystem performing frequency-selective filtering. Simulation results show that the proposed nanoDSP introduces only a minor performance degradation under high defect rates and at a range of operational conditions. The proposed technique also features good scalability and viability for various DSP applications.
14777107
Cooperative OFDM for energy-efficient wireless sensor networks
This paper presents a new energy-efficient cooperative sensor network scheme. Cooperative nodes shift the carrier frequency of the source node, and the destination node receives the signal from the source node and the cooperative nodes as a standard orthogonal frequency division multiplexing (OFDM) receiver. The maximal ratio combining (MRC) approach is applied to achieve full diversity with low complexity. The proposed scheme is scalable with respect to the number of nodes and is robust to time synchronization. A clustered network topology and cooperation protocol are proposed to realize multi-hop long haul signal transmission. The effect of the cluster scale is studied thoroughly to obtain the optimal size of clusters subject to the cooperation overhead. Simulation results show that the proposed cooperation scheme can consistently reduce the transmission power with the increase of cooperation scale. However, there is an optimal cluster scale where a good tradeoff between the diversity gain and cooperation cost can be established to minimize the total power consumption of the whole network.
16558773
Utilizing quantum dot transistors with programmable threshold voltages for low-power mobile computing
Power consumption poses one of the fundamental barriers for deploying mobile computing devices in energy-constrained situations with varying operation conditions. In particular, leakage power is projected to increase exponentially in future semiconductor process nodes. This challenging problem is pressing for renewed focus on power-performance optimization at all levels of design abstract, from novel device structures to fundamental shifts in design paradigm. In this article, we propose to exploit the programmable threshold voltage quantum dot (QD) transistors to reduce leakage thereby improving the energy efficiency for mobile computing. The unique programmability and reconfigurability enabled by QD transistors extend our capability in design optimization for new power-performance trade-offs. Simulation results demonstrate the significant leakage reduction over conventional techniques.
500553
Making register file resistant to power analysis attacks
Power analysis attacks are a type of side-channel attacks that exploits the power consumption of computing devices to retrieve secret information. They are very effective in breaking many cryptographic algorithms, especially those running in low-end processors in embedded systems, sensor nodes, and smart cards. Although many countermeasures to power analysis attacks have been proposed, most of them are software based and designed for a specific algorithm. Many of them are also found vulnerable to more advanced attacks. Looking for a low-cost, algorithm-independent solution that can be implemented in many processors and makes all cryptographic algorithms secure against power analysis attacks, we start with register file, where the operands and results of most instructions are stored. In this paper, we propose RFRF, a register file that stores data with a redundant flipped copy. With the redundant copy and a new precharge phase in write operations, RFRF provides data-independent power consumption on read and write for cryptographic algorithms. Although RFRF has large energy overhead, it is only enabled in the security mode. We validate our method with simulations. The results show that the power consumption of RFRF is independent of the values read out from or written to registers. Thus RFRF can help mitigate power analysis attacks.
14879086
The Algorithm of Obtaining Best Rules Based on Rough Set
With the fast development of the technology in Database and Internet, excessive information has become a problem that decision makers engage in electronic commerce have to affront. This paper firstly establishes the decision table for excessive data, then reduces knowledge of the decision table, and obtains the best rules. This can reduce the redundancy of the data, and improve the efficiency of knowledge obtaining. Because of the high time complexity and spatial complexity the general algorithm has, this paper proposed a new algorithm based on analogical matrix, and carried out the algorithm. The practice proves that the algorithm can improve the efficiency of knowledge obtaining, and the rules is tidy and best.
14334349
Learning Cascaded Reduced-Set SVMs Using Linear Programming
This paper proposes a simple and efficient detection framework that uses reduced-set kernels. We first describe our approach which reduces the number of kernels. A convex optimization method is used for calculating the reduced sets. Following this, we propose a method that optimally designs the cascade. Our experimental results indicate that our method minimizes complexity regarding the number of kernels in the cascaded structure while preserving the low error rates. Our algorithm generates the optimal weight of kernels for each cascade stage. This proposed algorithm achieves high detection-rates at low computational cost.
1462661
Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers
Presented in this paper is a low-power technique, denoted as MIMO-AEC, to reduce energy dissipation in multi-input-multi-output (MIMO) signal processing systems. The proposed technique extends a previously proposed adaptive error-cancellation (AEC) technique to MIMO systems by employing an algorithm transformation denoted as MIMO-DECOR. The purpose of MIMO-DECOR is to reduce complexity by exploiting correlations inherent in MIMO systems, thereby improving the effectiveness of AEC. We employ the MIMO-AEC in the design of a low-power Gigabit Ethernet 1000Base-T device. Simulation results demonstrate 44.3% - 25.2% overhead reduction due to MIMO-DECOR and 69.1% - 64.2% energy savings over conventional implementations with no loss in algorithmic performance.
15107946
The Research on Controlling Method of Loom Warp Tension
In the textile industry, in order to better control loom warp tension and obtain better quality fabrics, it was very pivotal to choose a good control algorithm. This paper emphatically carried on the design and analysis on three control methods, they were PID algorithm, fuzzy PID algorithm and single neuron adaptive PID algorithm. This article took the let-off system of SAURER400 loom as experimental object, and adopted the simulation system of MATLAB to check up the advantage and disadvantage of three control methods. The results showed that the simulation curve of single neuron adaptive PID control algorithm was fast response and small overshoot; In the process of weaving, this algorithm was very effective to control warp tension and obviously reduced the range of fluctuation of warp tension; Three kinds of algorithms designed in this article provided some methods to reference for controlling the warp tension of the loom in the future.
43074800
Research and Implementation of a 32-Bit Asynchronous Multiplier
提出基于宏单元（macrocell）的异步电路设计流程,由于在流程中尽量与现有的同步电路设计EDA工具兼容,降低了技术难度,提高了开发效率.基于该流程实现了0.35μm工艺条件下的32位异步乘法器.经过与相同工艺条件下,具有相同数据通路结构的同步乘法器比较,异步乘法器的性能与同步乘法器相当,而且面积更小、功耗更低.