22959134
The Design of Asynchronous Microprocessor Based on Optimized NCL_X Design-Flow
NCL X circuit is a very efficient way to implement the QDI circuit, which can get all the advantages of the asynchronous circuit, especially the average performance. But the NCL_X circuits suffer from its huge area overhead. To solve this problem, a method for optimizing the complete detection network in the NCL_X circuit has been introduced in this paper. Using this method can dramatically reduced the area of the NCL_X circuit, according to the experimental result, the area of the NCL_X circuit may be reduced more than 60%. We also use this optimized method to implement an asynchronous microprocessor pipeline (APC). Compared to the synchronous implementation, this NCL_X implementation can achieve higher performance because the NCL_X circuit can get the average performance.
17076624
Performance Bound Analysis and Retiming of Timed Circuits
Timed asynchronous circuits are efficient in performance and power consumption. Traditional performance analysis method can not analyze timed circuits efficiently. In this paper, we model timed circuits using timed Petri net and digraph. We studied the mean cycle time of timed Petri net model. The upper bound and lower bound of mean cycle time were given. Then we proposed an algorithm for timed circuits retiming. The algorithm can efficiently distribute buffers along communication channels of timed circuits to gain maximal performance and minimal area. These algorithms were applied to phased logic circuitspsila design and optimization.
7324862
A New Description Language for Data-Driven Asynchronous Circuits and its Design Flow
A lot of up-to-date asynchronous circuit design tools are based on the control-driven asynchronous circuit style, such as Balsa and Haste/Tangram. The control-driven approach will limit the performance of the result circuits. To improve the performance of the asynchronous circuits, a new description language - Biscotti, which is suitable for the data-driven asynchronous circuit design, has been introduced in this paper. And a data-driven asynchronous circuit design flow is also be presented here. The experimental results show that this design flow is a fast and efficient way to design the data-driven asynchronous circuit, which can achieve higher performance compared with the control-driven design approach.
19382812
A High-Speed High-Resolution Low-Distortion CMOS Bootstrapped Switch
This paper presents a low-voltage and low-distortion CMOS bootstrapped switch that adopts a new technique to improve the accuracy of sample-and-hold (S/H) circuits. In order to reduce distortion due to variation of the gate overdrive and the threshold voltage in conventional bootstrapped switches, a PMOS-type bootstrapped circuit combining with a NMOS-type one forms a double sampling switch that transmits input signals to the output terminal. The switch reduces the on-resistance greatly and keeps it constant, resulting in precise sampling of signals and better input bandwidth. A test S/H circuit based on this switch was designed and fabricated in SMIC 0.18-mum CMOS mixed signal technology. Experiments show at 100 MSample/s, a peak signal-to-noise-and-distortion ratio (SNDR) of 100.9 dB, spurious-free dynamic range (SFDR) of 102 dB and total harmonic distortion (THD) of 101 dB can be acquired, and for input frequency up to the Nyquist frequency, this circuit maintains SNDR over 90 dB, SFDR and THD better than 92.7 dB, respectively
2862393
Online Constrained Pattern Detection over Streams
Online pattern detection poses a challenge in many data-intensive applications, including network traffic management, trend analysis, intrusion detection, and various intelligent sensor networks. These applications have to be time and space efficient while providing high quality answers. Meanwhile, far less attention has been paid for detecting constrained patterns, that cannot be simply matched because there is no available pattern for prediction. This paper presents our research effort in efficient pattern detection with constraint. We propose a new method named Online Pattern Detection with Constraint (OPDC) to detect constrained patterns over evolving data stream, taking into account various user-defined constraints. To ensure that the constrained patterns are representative, we extend regular expression in a simple but powerful way. Our experimental results on real data sets demonstrate the feasibility and effectiveness of the proposed scheme.
7481401
Noise-tolerant dynamic circuit design
Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energy efficiency of VLSI systems in the deep submicron era. To address this problem, a new noise-tolerant dynamic circuit technique is presented. In addition, the average noise threshold energy (ANTE) and the energy normalized ANTE metrics are proposed for quantifying the noise immunity and energy efficiency, respectively, of circuit techniques. Simulation results in 0.35 micron CMOS for NAND gate designs indicate that the proposed technique improves the ANTE and energy normalized ANTE by 2.54X and 2.25X over the conventional domino circuit. The improvement in energy normalized ANTE is 1.22X higher than the existing noise-tolerance techniques. A full adder design based on the proposed technique improves the ANTE and energy normalized ANTE by 3.7X and 1.95X over the conventional dynamic circuit. In comparison, the static circuit improves ANTE by 2.2X but degrades the energy normalized ANTE by 11%. In addition, the proposed technique has a smaller area overhead (69%) as compared to the static circuit whose area overhead is 98%.
17864128
Traffic Localizing Strategy for Peer-to-Peer Systems
Topology mismatching problem between peer-to-peer overlay network and physical underlying network brings great stress to Internet infrastructure. This paper proposes a traffic localizing strategy (TLS), it keeps scalability property of current DHT algorithms and improves system routing performance by partitioning DHT key space associating with local physical information. Experiments based on CAN model show that the traffic localizing strategy can significantly alleviate the backbone link traffic burden. Meanwhile, the average routing hops are reduced.
13024197
Joint Performance Improvement and Error Tolerance for Memory Design Based on Soft Indexing
Memory design is facing the dual challenges of performance improvement and error tolerance due to a combination of technology scaling and higher levels of integration. To address these challenges, we propose a new memory microarchitecture referred to as the soft indexing. The proposed technique allocates memory resources in a self-adaptive manner in accordance with runtime program variations, thereby achieving efficient memory access and effective error protection in a coherent manner. Statistical analysis shows 10times improvement in error detection capability over the existing error-control techniques. The benefits of the proposed technique are also experimentally demonstrated using the SPEC CPU2000 benchmarks. Simulation results show 94.9% average error-control coverage on the 23 benchmarks, with average of 23.2% reduction in memory miss rates as compared to the conventional techniques.