9776506
Adaptive timing for analysis of skew tolerance
This paper presents an adaptive timing framework for analysis of skew tolerance in high-performance synchronous integrated circuits. The proposed adaptive timing framework models practical deskew schemes as an adaptive system and employs the adaptive processing theory to investigate potential solutions and design constraints of deskew operation. Employing the adaptive timing framework, we determine the statistical properties of optimal deskew, which can be considered as the theoretical limit of skew tolerance. We also quantify the performance of practical deskew schemes and compare the performance gap with optimal deskew. Simulation results reveal that the performance of practical deskew schemes in 90-nm process is 24.3% away from optimal deskew
36279845
Exploiting soft redundancy for error-resilient on-chip memory design
8890864
Improving Error Tolerance for Multithreaded Register Files
Chip multithreaded computing is exposed to the dual challenges of increasing system complexity and error sensitivity. It is critical to develop effective solutions that achieve better error tolerance without inducing performance degradation. In this paper, we propose a new error-tolerant memory design based on a unique computing phenomenon referred to as the dynamic multithreading redundancy (DMR). The proposed technique exploits the interplay between the concurrent threads for runtime error control. We also present two DMR enhancements, immediate write-back and self-recovery, to address the error accumulation effect. A multithreaded register file was implemented to demonstrate the proposed DMR technique. Simulation results on the SPEC CPU2000 benchmarks demonstrate significant overhead reduction in performance and energy efficiency related to error recovery. In addition, the proposed technique features good scalability with respect to the instruction-level and thread-level parallelism for next-generation processor design, where the soft error problem is expected to get worse due to technology scaling and architecture-affecting trends.
6708583
Reducing error accumulation effect in multithreaded memory systems
Chip multithreading is exposed to dual challenges of increasing chip complexity and design variations. It is important to develop effective reliability-enhancing schemes to ensure robust computing. In this paper, we propose the immediate write-back and self-recovery schemes to reduce error accumulation effect in multithreaded memory systems. These schemes are built upon the previously proposed dynamic multithreading redundancy technique for improving reliability in multithreaded architectures. The idea of DMR is to exploit self-generated hardware redundancy due to inter-thread variations inherent in multithreaded architectures. Simulation results demonstrate that the proposed solutions improve error-control performance with minimal hardware overheads. The proposed immediate write-back and self-recovery schemes also feature good scalability for future process generations
18869116
Thread-Associative Memory for Multicore and Multithreaded Computing
Presented in this paper is the thread-associative memory microarchitecture for multicore and multithreaded processor design. Memory contention among concurrent threads in chip multithreaded processing has become a limiting factor for performance improvement. The proposed thread-associative memory addresses this challenge by incorporating thread-specific information explicitly into on-chip memory hardware. The proposed technique can be utilized at different levels of memory hierarchy. Furthermore, it is not just a technique for performance enhancement but also a solution for energy efficiency. Trace-driven simulations on a 32KB L1 data cache demonstrate 36.6% maximum performance improvement and up to 15.1% total energy reduction, with 20.3% dynamic energy reduction and 9.9% leakage energy reduction
16020986
Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation
Nanoelectronic devices are considered to be the computational fabrics for the emerging nanocomputing systems due to their ultra-high speed and integration density. However, the imperfect bottom-up self-assembly fabrication leads to excessive defects that have become a barrier for achieving reliable computing. In addition, transient errors continue to be a problem. The massive parallelism rendered by nanoscale integration opens up new opportunities but also poses challenges on how to manage such massive resources for reliable and high-performance computing. In this paper, we propose a nanoarchitecture solution to address these emerging challenges. By using dynamic redundancy allocation, the massive parallelism is exploited to jointly achieve fault (defect/error) tolerance and high performance. Simulation results demonstrate the effectiveness of the proposed technique under a range of fault rates and operating conditions.
11258056
Data I/O Minimization for Loops on Limited Onchip Memory Processors
Due to significant advances in VLSI technology, ‘mega-processors’ made with a large number of transistors has become a reality. These processors typically provide multiple functional units which allow exploitation of parallelism. In order to cater to the data demands associated with parallelism, the processors provide a limited amount of on-chip memory. The amount of memory provided is quite limited due to higher area and power requirements associated with it. Even though limited, such on-chip memory is a very valuable resource in memory hierarchy. An important use of on-chip memory is to hold the instructions from short loops along with the associated data for very fast computation. Such schemes are very attractive on embedded processors where, due to the presence of dedicated hard-ware on-chip (such as very fast multipliers-shifters etc.) and extremely fast accesses to on-chip data, the computation time of such loops is extremely small meeting almost all real-time demands. Biggest bottleneck to performance in these cases are off-chip accesses and thus, compilers must carefully analyze references to identify good candidates for promotion to on-chip memory. In our earlier work [6], we formulated this problem in terms of 0/1 knapsack and proposed a heuristic solution that gives us good promotion candidates. Our analysis was limited to a single loop nest. When we attempted extending this framework to multiple loop nests (intra-procedurally), we realized that not only it is important to identify good candidates for promotion but a careful restructuring of loops must be undertaken before performing promotion since data i/o of loading and storing values to on-chip memory poses a significant bottleneck.
14183415
Context-aware application programming for mobile devices
This research aims at facilitating the development of context-aware application software for mobile devices by providing a programming model, an implementation framework and a development environment. The programming model provides a multi-layered software architecture for context-aware application programming. The model supports developers to define contexts, behaviors and context-behavior binding rules through specifications and automates generation of context-aware application code based on the specifications. The implementation framework is a backbone program that implements the programming model. It facilitates the development in reducing the effort on the common tasks of context-awareness and help developers focus on the application-specific components. The development environment provides a series of tools to support the development of context-aware applications. These tools simplify the development process and provide the developed applications with robustness and testability.
11142145
An Optimal Design Method for De-synchronous Circuit Based on Control Graph
De-synchronous is a very useful method to design asynchronous circuit automatically from synchronous description of circuits. This paper introduces an optimal design method based on Control Graph which is an abstract model of the de-synchronous circuit. The main purpose of this optimal design method is to reduce the extra overhead in the area of the de-synchronous circuit. The optimization algorithm takes the performance evaluation function based on the Control Graph of the de-synchronous circuit as its heuristic function. The performance evaluation function presented in this paper is a linear programming problem. In the end of this paper, the optimal method is applied to a set of benchmark circuits. The number of the local controllers in these circuits is markedly reduced by 54%, and the number of C-elements that is required to construct the handshake circuitry between local controllers is also reduced by 76.3%. So the entire area of the circuit is sharply reduced. Because this design method is directed by the performance evaluation function of the circuit, there is no penalty in performance of the de-synchronous circuit.
16447326
An Approximate Method for Performance Evaluation of Asynchronous Pipeline Rings
Performance evaluation of asynchronous circuits is one of the most difficult parts in asynchronous circuit research. This Paper presents an approximate method by queuing network modeling for performance evaluation of asynchronous pipeline rings. The asynchronous pipeline rings are modeled by closed queuing networks with transfer blocking. An efficient approximation method is used to analyze the performance metrics, such as response time and throughput. These performance metrics can be used to derive the cycle time and latency of the asynchronous pipeline rings. Compared with theoretic results, the algorithm presented in this paper is efficient for performance evaluation of asynchronous pipeline rings.
119668212
Impulsive optimal control model for the trajectory of horizontal wells
This paper presents an impulsive optimal control model for solving the optimal designing problem of the trajectory of horizontal wells. We take fully into account the effect of unknown disturbances in drilling. The optimal control problem can be converted into a nonlinear parametric optimization by integrating the state equation. We discuss here that the locally optimal solution depends in a continuous way on the parameters (disturbances) and utilize this property to propose a revised Hooke-Jeeves algorithm. The uniform design technique is incorporated into the revised Hooke-Jeeves algorithm to handle the multimodal objective function. The numerical simulation is in accordance with theoretical results. The numerical results illustrate the validity of the model and efficiency of the algorithm.