15979714
A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design
The floating-point multiply-add fused (MAF) unit sets a new trend in the processor design to speed up floatingpoint performance in scientific and multimedia applications. This paper proposes a new architecture for the MAF unit that supports multiple IEEE precisions multiply-add operation (AtimesB+C) with Single Instruction Multiple Data (SIMD) feature. The proposed MAF unit can perform either one double-precision or two parallel single-precision operations using about 18% more hardware than a conventional double-precision MAF unit and with 9% increase in delay. To accommodate the simultaneous computation of two single-precision MAF operations, several basic modules of double-precision MAF unit are redesigned. They are either segmented by precision mode dependent multiplexers or attached by the duplicated hardware. The proposed MAF unit can be fully pipelined and the experimental results show that it is suitable for processors with floatingpoint unit (FPU).
33440658
A New Technique for Program Code Compression in Embedded Microprocessor
Program code compression has become a critical technology nowadays, and it can promote the performance of microprocessor systems. But compression techniques nowadays can hardly achieve both satisfactory compression ratio and low hardware complexity. A new program code compression method is proposed in this paper. Experiment results show that the code sizes of ARM and OR1200 microprocessor can be efficiently reduced by 32.2% and 36.9% individually with this algorithm, resulting to a sharp decrease in memory traffic. A hardware decompressing prototype is also presented, revealing its advantage in ultra high speed decompression and low hardware complexity.
40046861
A New CORDIC Algorithm and Software Implementation Based on Synchronized Data Triggering Architecture
A new CORDIC algorithm based on sign bits prediction is presented. It is an effective method for transforming arbitrary iterations of classic CORDIC to simple matrix multiplications. At the same time, this algorithm is implemented based on synchronized data triggering architecture (SDTA). Experimental results show that the average speed-up of transcendental functions tested based on our version CORDIC compared with mathematic library supported in gcc3.2.2 is up to 283% under the given Neuron microprocessor.
14935665
Optimal Matrix Computing Using Vector Division with Sub-word Parallel
Available computing is expected to be effective and efficient in ubiquitous multimedia services. And, matrix multiplication is particular to ubiquitous computing such as image transformation so that it is urgent to exploit potential parallelism as well as data reuse in matrix multiplication. Therefore, based on synchronized data triggered architecture (SDTA), we propose a method of parallel vector division (PVD) as well as sub-word parallel (SWP) supported on SDTA to optimize the matrix computation on specified architecture. Experimental results show that PVD with SWP is suitable for matrix multiplication on SDTA instruction set architecture. Besides, we could extend the proposed model into other data-intensive computing on SDTA.
60639655
Parallel simulation of chip-multiprocessor by using multi-threading
Multi-core on one chip becomes the current main trend of micro processors' architecture, and simulation plays an important role in evaluating new processor architectures. Traditional ways of sequential simulation for chip-multiprocessor (CMP) require lots of simulation time which can't be afford during processor design phase. Therefore, exploiting parallelism is necessary for speeding up the multi-core processor simulation. 
 
In this paper, we present a parallel CMP simulator, which is implemented by using POSIX threads, and also present the programming methodology for converting a sequential single core simulator to a parallel CMP simulator. Furthermore, the tradeoffs in parallel simulator implementation are also discussed. The experiments are carried out on a four-CPU dual core Xeon server. Under weak consistence order model, the parallel simulator achieves a speedup of 7.2X comparing with the sequential one.
31522150
Hardware Support for Arithmetic Units of Processor with Multimedia Extension
Multimedia extension technique is very popular in designing processors to improve multimedia processing performance. This paper carries on the study of hardware implementation of arithmetic units with multimedia extension support, and proposes new design methods for subword multiplier and SIMD (single instruction multiple data) IEEE FPU (floating-point unit). To verify the correctness and effectiveness of these methods, a multimedia coprocessor with SIMD fixed-point and floating-point units is designed. The implemented chip successfully demonstrates that the proposed SIMD Arithmetic units get good tradeoff between cost and performance.
29851215
Unified probabilistic models for face recognition from a single example image per person
This paper presents a new technique of unified probabilistic models for face recognition from only one single example image per person. The unified models, trained on an obtained training set with multiple samples per person, are used to recognize facial images from another disjoint database with a single sample per person. Variations between facial images are modeled as two unified probabilistic models: within-class variations and between-class variations. Gaussian Mixture Models are used to approximate the distributions of the two variations and exploit a classifier combination method to improve the performance. Extensive experimental results on the ORL face database and the authors' database (the ICT-JDL database) including totally 1,750 facial images of 350 individuals demonstrate that the proposed technique, compared with traditional eigenface method and some well-known traditional algorithms, is a significantly more effective and robust approach, for face recognition.
8343773
A spatio-temporal multi-modal data management and analysis environment for tracking MS lesions
We describe the development of a system that automates data collection, metadata extraction and analysis of spatio-temporal multi-modal data, combining data management and data analysis to provide an efficient resource for clinicians. Though the system is extensible to many applications, the current focus is on managing Multiple Sclerosis (MS) lesion data, which are disparate streams of image, numeric, and text data. In order to discover patterns of MS pathology and plan early and effective treatment, multispectral magnetic resonance (MR) image streams collected over time need to be correlated efficiently with each other and with patient performance and clinical data streams.
62074016
Dimension Reduction-Based Penalized Logistic Regression for Cancer Classification Using Microarray Data
The use of penalized logistic regression for cancer classification using microarray expression data is presented. Two dimension reduction methods are respectively combined with the penalized logistic regression so that both the classification accuracy and computational speed are enhanced. Two other machine-learning methods, support vector machines and least-squares regression, have been chosen for comparison. It is shown that our methods have achieved at least equal or better results. They also have the advantage that the output probability can be explicitly given and the regression coefficients are easier to interpret. Several other aspects, such as the selection of penalty parameters and components, pertinent to the application of our methods for cancer classification are also discussed.
33719729
New Algorithms for Efficient Mining of Association Rules
Abstract Discovery of association rules is an important data mining task. Several algorithms have been proposed to solve this problem. Most of them require repeated passes over the database, which incurs huge I/O overhead and high synchronization expense in parallel cases. There are a few algorithms trying to reduce these costs. But they contain weaknesses such as often requiring high pre-processing cost to get a vertical database layout, containing much redundant computation in parallel cases, and so on. We propose new association mining algorithms to overcome the above drawbacks, through minimizing the I/O cost and effectively controlling the computation cost. Experiments on well-known synthetic data show that our algorithms consistently outperform a priori, one of the best algorithms for association mining, by factors ranging from 2 to 4 in most cases. Also, our algorithms are very easy to be parallelized, and we present a parallelization for them based on a shared-nothing architecture. We observe that our parallelization develops the parallelism more sufficiently than two of the best existing parallel algorithms.
53224637
Generating fuzzy semantic metadata describing spatial relations from images using the R-histogram