195869396
Results from an ATM-based event builder demonstrator
ATM switching fabrics are good candidates to implement high performance parallel event builders for the future data acquisition systems of the LHC experiments. We are studying their feasibility through simulations and implementation of event builder demonstrators. The impact of the event builder characteristic traffic pattern on the switch has been studied and methods to avoid congestion in the switch have been proposed. Event building algorithms and data acquisition protocols have been developed. Measurements made with a demonstrator and comparisons with simulation studies are presented. The scalability of the measurements is discussed.
118645473
The topological second-level trigger of the H.E.S.S. phase 2 telescope
H.E.S.S is an array of atmospheric Cherenkov telescopes dedicated to GeV-TeV γ-ray astronomy. The original array has been in operation since the beginning of 2004. It is composed of four 12-meter diameter telescopes. The installation of a fifth 28-meter diameter telescope is being completed. This telescope will operate both in stereoscopic mode and in monoscopic mode i.e. without a coincident detection on the smaller telescopes. A second-level trigger system is needed to supress spurious triggers of the 28-meter telescope when operated in monoscopic mode. This paper gives the motivation and principle of the second-level trigger. The principle of operation is illustrated by an example algorithm. The hardware implementation of the second level trigger system of H.E.S.S. phase 2 is described and its expected performances are then evaluated.
82263624
A read-out buffer prototype for ATLAS high level triggers
Read-out buffers are critical components in the dataflow chain of the ATLAS Trigger/DAQ system. At up to 75 kHz, after each level-1 trigger accept signal, these devices receive and store digitized data from groups of front-end electronic channels. Several read-out buffers are grouped to form a read-out buffer complex that acts as a data server for the high level trigger selection algorithms and for the final data collection system. This paper describes a functional prototype of a read-out buffer based on a custom made PCI mezzanine card that is designed to accept input data at up to 160 MB/s, to store up to 8 MB of data and to distribute data chunks at the desired request rate. We describe the hardware of the card that is based on an Intel 1960 processor and CPLDs. We present the integration of several of these cards in a read-out buffer complex. We measure various performance figures and we discuss to which extent these can fulfil ATLAS needs.
53769716
On the integration of high performance ATM-based event builders
A first demonstrator has shown encouraging results for the use of Asynchronous Transfer Mode (ATM) switching networks in the implementation of high performance parallel event builders. Our present goal is to show that the integration of event builders, including the implementation of the source and destination functions and the bandwidth adaptation to the switching network, can be realized with commercially available products and that good performance can be achieved. We shall review some critical issues, present results from performance measurements and analyse the overheads.
110024675
A sequential processing strategy for the ATLAS event selection
A new processing strategy for the ATLAS event selection system is proposed for use downstream of the first level trigger. It aims to achieve a reduction of the event rate to a level suitable for recording on permanent storage via a sequential treatment of the "regions of interest" selected by the level 1 trigger. A possible Trigger/DAQ architecture which exploits this concept is presented. It is based on a single processing farm and a network which transports data and protocol traffic. The resources necessary for the implementation of this architecture are estimated. A set of performance figures obtained by calculations and computer simulations are given assuming the use of ATM networking technology.
55013324
Micromegas detector developments for Dark Matter directional detection with MIMAC
The aim of the MIMAC project is to detect non-baryonic Dark Matter with a directional TPC using a high precision Micromegas readout plane. We will describe in detail the recent developments done with bulk Micromegas detectors as well as the characterisation measurements performed in an Argon(95%)-Isobutane(5%) mixture. Track measurements with alpha particles will be shown.
37159826
A measurement of Lorentz angle and spatial resolution of radiation hard silicon pixel sensors
Silicon pixel sensors developed by the ATLAS collaboration to meet LHC requirements and to withstand hadronic irradiation to fluences of up to $10^{15} n_eq/cm^{2}$ have been evaluated using a test beam facility at CERN providing a magnetic field. The Lorentz angle was measured and found to alter from 9.0 deg. before irradiation, when the detectors operated at 150 V bias at B=1.48 T, to 3.1 deg after irradiation and operating at 600 V bias at 1.01 T. In addition to the effect due to magnetic field variation, this change is explained by the variation of the electric field inside the detectors arising from the different bias conditions. The depletion depths of irradiated sensors at various bias voltages were also measured. At 600 V bias 280 micron thick sensors depleted to ~200 micron after irradiation at the design fluence of 1 10^{15} 1 MeV n_eq/cm2 and were almost fully depleted at a fluence of 0.5 * 10^{15} 1 MeV n_eq/cm2. The spatial resolution was measured for angles of incidence between 0 deg and 30 deg. The optimal value was found to be better than 5.3 micron before irradiation and 7.4 micron after irradiation.
108645383
The ATLAS Silicon Pixel Sensors
Abstract Prototype sensors for the ATLAS silicon pixel detector have been developed. The design of the sensors is guided by the need to operate them in the severe LHC radiation environment at up to several hundred volts while maintaining a good signal-to-noise ratio, small cell size, and minimal multiple scattering. The ability to be operated under full bias for electrical characterization prior to attachment of the readout integrated circuit electronics is also desired.
64504728
MAREBO: A full radhard pixel detector prototype for ATLAS
27426193
MCC: The Module Controller Chip for the ATLAS pixel detector
In this article we describe the architecture of the Module Controller Chip for the ATLAS Pixel Detector. The project started in 1997 with the definition of the system specifications. A first fully-working rad-soft prototype was designed in 1998, while a radiation hard version was submitted in 2000. The 1998 version was used to build pixel detector modules. Results from those modules and from the simulated performance in ATLAS are reported. In the article we also describe the hardware/software tools developed to test the MCC performance at the LHC event rate.
109862390
Test system for the production of the Atlas Tile Calorimeter front-end electronics
Abstract The Atlas hadronic Tile Calorimeter front-end electronics is fully included in the so-called “super-drawers”. The 256 super-drawers needed for the entire calorimeter are assembled and extensively tested in Clermont-Ferrand before being sent to CERN to be inserted in the calorimeter modules. A mobile system has been developed to perform a complete test of the super-drawers during their insertion.