14992519
Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches
This paper presents a two-part study on managing distributed NUCA (non-uniform cache architecture) L2caches in a future many core processor to obtain high single thread program performance. The first part of our study is a limit study where we determine data to cache slice mappings at the memory page granularity based on detailed inter-page conflict information derived from program's memory reference trace. By considering cache access latency and cache miss rate simultaneously when mapping data to L2 cache slices, this "oracle" scheme outperforms the conventional shared caching scheme by up to 208% with an average of 45% on a sixteen-core processor. In the second part of the study, we propose and evaluate a dynamic cache management scheme that determines the home cache slice and cache bin for memory pages without any static program information. The dynamic scheme outperforms the shared caching scheme by up to 191% with an average of 32%, achieving much of the performance we observed in the limit study. We also find that the proposed dynamic scheme adapts to multiprogrammed workloads' behavior well and performs significantly better than both the private caching scheme and the shared caching scheme.
12748571
TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation
The slow speed of conventional execution-driven architecture simulators is a serious impediment to obtaining desirable research productivity. This paper proposes and evaluates a fast manycore processor simulation framework called two-phase trace-driven simulation (TPTS), which splits detailed timing simulation into a trace generation phase and a trace simulation phase. Much of the simulation overhead caused by uninteresting architectural events is only incurred once during the trace generation phase and can be omitted in the repeated trace-driven simulations. We design and implement tsim, an event-driven manycore processor simulator that models detailed memory hierarchy, interconnect, and coherence protocol models based on the proposed TPTS framework. By applying aggressive event filtering, tsim achieves an impressive simulation speed of 146 MIPS, when running 16-thread parallel applications.
1971798
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation
This paper presents and studies a distributed L2 cache management approach through OS-level page allocation for future many-core processors. L2 cache management is a crucial multicore processor design aspect to overcome non-uniform cache access latency for good program performance and to reduce on-chip network traffic and related power consumption. Unlike previously studied hardware-based private and shared cache designs implementing a "fixed" caching policy, the proposed OS-micro architecture approach is flexible; it can easily implement a wide spectrum of L2 caching policies without complex hardware support. Furthermore, our approach can provide differentiated execution environment to running programs by dynamically controlling data placement and cache sharing degrees. We discuss key design issues of the proposed approach and present preliminary experimental results showing the promise of our approach
11153805
Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems
Doubling the number of processing cores on a single processor chip with each technology generation has become conventional wisdom. While future manycore processors promise to offer much increased computational throughput under a given power envelope, sharing critical on-chip resources, such as caches and core- to-core interconnects, poses challenges to guaranteeing predictable performance to an application program. This paper focuses on the problem of sharing on-chip caching capacity among multiple programs scheduled together, especially at the L2 cache level. Specifically, two design aspects of a large shared L2 cache are considered: (1) non-uniform cache access latency and (2) cache contention. We observe that both the aspects have to do with where, among many cache slices, a cache block is mapped to, and present an OS-based approach to managing the on-chip L2 cache memory by carefully mapping data to a cache at the page granularity. We show that a reasonable extension to the OS memory management subsystem and simple architectural support enable enforcing high-level policies to achieve application performance isolation and improve program performance predictability thereof.
2578172
A flexible data to L2 cache mapping approach for future multicore processors
This paper proposes and studies a distributed L2 cache management approach through page-level data to cache slice mapping in a future processor chip comprising many cores. L2 cache management is a crucial multicore processor design aspect to overcome non-uniform cache access latency for high program performance and to reduce on-chip network traffic and related power consumption. Unlike previously studied "pure" hardware-based private and shared cache designs, the proposed OS-microarchitecture approach allows mimicking a wide spectrum of L2 caching policies without complex hardware support. Moreover, processors and cache slices can be isolated from each other without hardware modifications, resulting in improved chip reliability characteristics. We discuss the key design issues and implementation strategies of the proposed approach, and present an experimental result showing the promise of it.
62667888
Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approach
Simulation is indispensable in computer architecture research. Researchers increasingly resort to detailed architecture simulators to identify performance bottlenecks, analyze interactions among different hardware and software components, and measure the impact of new design ideas on the system performance. However, the slow speed of conventional execution-driven architecture simulators is a serious impediment to obtaining desirable research productivity. This paper describes a novel fast multicore processor architecture simulation framework called Two-Phase Trace-driven Simulation (TPTS), which splits detailed timing simulation into a trace generation phase and a trace simulation phase. Much of the simulation overhead caused by uninteresting architectural events is only incurred once during the cycle-accurate simulation-based trace generation phase and can be omitted in the repeated trace-driven simulations. We report our experiences with tsim, an event-driven multicore processor architecture simulator that models detailed memory hierarchy, interconnect, and coherence protocol based on the TPTS framework. By applying aggressive event filtering, tsim achieves an impressive simulation speed of 146 millions of simulated instructions per second, when running 16-thread parallel applications. Copyright © 2010 John Wiley & Sons, Ltd.
10940298
An Extensible Data Model with Security Support for Dataspace Management
Based on the iDM concept, this paper proposes an extensible data model with an 8-tuple representation, which can not only describe more complex data sources by extending the Group Component, but also contain rule-based security elements, which consist of Access Component and Authorization Component. Data model is detailed and two corresponding examples are analyzed to verify our approach.
46206821
A rule-based system for localization of water on the surface of Mars
In order to use autonomous robots to search for water on the Martian surface, several concerns are raised that need to be addressed, analyzed and remedied. These concerns include the development of a suitable scanning algorithm, positioning system, and obstacle handling. We investigate the above mentioned concerns and propose remedies for them. Also, the remedies are tested by a simulation process. The results convey that the proposed solutions for the raised concerns are effective.
7700541
A comparison of search patterns for cooperative robots operating in remote environment
In this paper, two scanning paradigms are presented and compared that may be used for robotic scanning of a harsh environment such as a celestial body or earth poles. The first paradigm, tight scanning, includes three algorithms, which may be used to find small objects or gasses confined to small regions such as the methane gas given off by bacteria in buried hot springs in the Canadian arctic. The second paradigm, relaxed scanning, includes four algorithms which may be used to find large objects such as large ice deposits that may be buried just below the surface of Mars. The algorithms are compared against their peer algorithms by their quality of performance. Such performance quality is determined by the ratio of scanned area to the traveled distance by the two robots.
2307602
A Multi-Dimensional K-Anonymity Model for Hierarchical Data
For improving the usability of the anonymous result, it is important to comply with the hierarchical structure when generalizing quasi-identifying attributes with hierarchical characteristics. We propose an unrestricted multi-dimensional anonymization model which combines global recoding and local recoding methods. The bottom-up anonymization algorithm with the minimal coverage subgraph constraint and the anonymization metric are proposed. The experiment results justify the effectiveness and scalability of this model.
60552525
Simulation model of the LS-DRMTA adaptive algorithm for multiple antenna system for DS-CDMA
We present the development of a simulation model and for a conceptual DS-CDMA system and simulation baseband models for the least-square despread respread multitarget array (LS-DRMTA) algorithm with two, four and six antenna elements in the Matlab/Simulink environment. The models are used to compare the performance of single and multiple adaptive antenna systems in an AWGN channel. The simulation models show the clear advantage of multiple antenna systems and represent a first step towards their implementation on an FPGA platform.