12297104
CoStore: a reliable and highly available storage system using clusters
The CoStore cluster architecture is proposed to construct a reliable and highly available storage system. A prototype CoStore was implemented and its performance was measured with the cluster being mirrored in various network environments. The preliminary results demonstrate that there is little impact on performance if the cluster is mirrored in efficient campus network environments with high bandwidth and low latency. As a result the CoStore architecture considerably reinforces a storage system's preparedness for disaster recovery without sacrificing performance.
417212
Taxonomy of Data Prefetching for Multicore Processors
Data prefetching is an effective data access latency hiding technique to mask the CPU stall caused by cache misses and to bridge the performance gap between processor and memory. With hardware and/or software support, data prefetching brings data closer to a processor before it is actually needed. Many prefetching techniques have been developed for single-core processors. Recent developments in processor technology have brought multicore processors into mainstream. While some of the single-core prefetching techniques are directly applicable to multicore processors, numerous novel strategies have been proposed in the past few years to take advantage of multiple cores. This paper aims to provide a comprehensive review of the state-of-the-art prefetching techniques, and proposes a taxonomy that classifies various design concerns in developing a prefetching strategy, especially for multicore processors. We compare various existing methods through analysis as well.
14925300
A Taxonomy of Data Prefetching Mechanisms
Data prefetching has been considered an effective way to mask data access latency caused by cache misses and to bridge the performance gap between processor and memory. With hardware and/or software support, data prefetching brings data closer to a processor before it is actually needed. Many prefetching techniques have been proposed in the last few years to reduce data access latency by taking advantage of multi-core architectures. In this paper, we propose a taxonomy that classifies various design concerns in developing a prefetching strategy. We discuss various prefetching strategies and issues that have to be considered in designing a prefetching strategy for multi-core processors.
5789716
Reevaluating Amdahl's law in the multicore era
Microprocessor architecture has entered the multicore era. Recently, Hill and Marty presented a pessimistic view of multicore scalability. Their analysis was based on Amdahl's law (i.e. fixed-workload condition) and challenged readers to develop better models. In this study, we analyze multicore scalability under fixed-time and memory-bound conditions and from the data access (memory wall) perspective. We use the same hardware cost model of multicore chips used by Hill and Marty, but achieve very different and more optimistic performance models. These models show that there is no inherent, immovable upper bound on the scalability of multicore architectures. These results complement existing studies and demonstrate that multicore architectures are capable of extensive scalability.
61649411
Parallel I/O prefetching using MPI file caching and I/O signatures
Parallel I/O prefetching is considered to be effective in improving I/O performance. However, the effectiveness depends on determining patterns among future I/O accesses swiftly and fetching data in time, which is difficult to achieve in general. In this study, we propose an I/O signature-based prefetching strategy. The idea is to use a predetermined I/O signature of an application to guide prefetching. To put this idea to work, we first derived a classification of patterns and introduced a simple and effective signature notation to represent patterns. We then developed a toolkit to trace and generate I/O signatures automatically. Finally, we designed and implemented a thread-based client-side collective prefetching cache layer for MPI-IO library to support prefetching. A prefetching thread reads I/O signatures of an application and adjusts them by observing I/O accesses at runtime. Experimental results show that the proposed prefetching method improves I/O performance significantly for applications with complex patterns.
10931722
STAS: A Scalability Testing and Analysis System
Scalability is a crucial factor in performance evaluation and analysis of parallel and distributed systems. Much effort has been devoted to scalability research and several metrics are proposed. However, the lacking of an effective scalability analysis toolkit is still a major barrier for researchers to measure and analyze scalabilities. Isospeed scalability is a known metric and has been extended for general computing systems recently. This paper proposes an effective scalability testing and analysis system, called STAS, and presents its implementation with isospeed-e scalability metric. STAS provides the facility to conduct automated isospeed-e scalability measure and analysis. It reduces the burden for users to evaluate the performance of algorithms and systems. Experiments have been conducted to verify the design and implementation
40372820
Mining circumstance-oriented association rules using singular value decomposition technique
Association rule has evolved from the primitive form of single dimension intratransaction to the form of multi-dimension intertransaction. The challenge for mining multi-dimension intertransaction rules is the formidable search space. Researchers have proposed various methods to handle this problem, such as restricting the number of dimensions, confining search space in a small window, etc. These methods unavoidably have negative impact on mining result and they are less effective when the number of dimensions and the length of rule are really large. Moreover, all these methods are derived from the a priori algorithm and have common weaknesses: time consuming and redundancy caused by the iterative nature of the a priori algorithm. To approach this problem from a different angle, we propose to use the singular value decomposition technique (SVD). With SVD, the multi-dimension intertransaction rules can be easily identified.
12301426
A Novel Symmetric Cryptography Based on Chaotic Signal Generator and a Clipped Neural Network
Recently, a novel encryption algorithm that integrates Haar wavelets transformation into chaotic signal generator, was proposed by R.Luo et al. In this paper, we first analyzed the merits and demerits of this algorithm. Then an improved scheme which uses a clipped neural network is proposed. Both theoretical analysis and computer simulations show our proposed scheme succeeds in overcoming the defects of Luo’s algorithm while retaining all its merits. Moreover, the way that the clipped neural network evolves may present a new idea to the cryptography.
15834568
An Artificial Neural Network Based on CIEA
Chaotic Immune evolutionary algorithm (CIEA) is proposed on the shortage of current algorithms training artificial neural network, biological immune mechanism and the characteristics of evolution. A novel artificial neural network based on chaotic immune evolutionary algorithm (CIEANN) is presented in this paper. The algorithm has the merits of chaos, immunity and evolutionary algorithm. It can ensure the ability of global search and local search and enhance the performances of the algorithm. At last, we analyzed the performance of CIEANN with a typical XOR problem and compared it with several common ANNs. The analysis results show that CIEANN converges quickly and avoids immature convergence and is an effective way to solve optimization problem.
11827610
A Runtime System for Dynamic DAG Programming
A runtime system is described here for dynamic DAG execution. A large D A G whihc represents an application program can be executed on a parallel system without consuming large amount of memory space. A DAG scheduling algorithm has been parallelized to scale to large systems. Inaccurate estimation of task execution time and comm unication time can be tolerated. Implementation of this parallel incremental system demonstrates the feasibility of this approach. Preliminary results show that it is superior to other approaches.
14066096
ADM-Padé technique for the nonlinear lattice equations
ADM-Pade technique is a combination of Adomian decomposition method (ADM) and Pade approximants. We solve two nonlinear lattice equations using the technique which gives the approximate solution with higher accuracy and faster convergence rate than using ADM alone. Bell-shaped solitary solution of Belov-Chaltikian (BC) lattice and kink-shaped solitary solution of the nonlinear self-dual network equations (SDNEs) are presented. Comparisons are made between approximate solutions and exact solutions to illustrate the validity and the great potential of the technique.