20311666
CoStore: a storage cluster architecture using network attached storage devices
We propose a storage cluster architecture CoStore, which evenly distributes system responsibilities across all collaborating cluster members without a separate central file manager. The serverless CoStore architecture has the potential to provide scalable high-performance high-capacity storage services with strong reliability and availability, traditionally only achievable by high-end storage systems. A prototype CoStore system has been implemented using cost-effective COTS-based network attached storage devices on commodity operating systems. The performance of the CoStore prototype has been measured and compared with those of other commonly available distributed file systems. Preliminary test results show that a single node CoStore has a comparable performance to that of NFS and that CoStore outperforms CIFS on Windows 2000.
61649411
Parallel I/O prefetching using MPI file caching and I/O signatures
Parallel I/O prefetching is considered to be effective in improving I/O performance. However, the effectiveness depends on determining patterns among future I/O accesses swiftly and fetching data in time, which is difficult to achieve in general. In this study, we propose an I/O signature-based prefetching strategy. The idea is to use a predetermined I/O signature of an application to guide prefetching. To put this idea to work, we first derived a classification of patterns and introduced a simple and effective signature notation to represent patterns. We then developed a toolkit to trace and generate I/O signatures automatically. Finally, we designed and implemented a thread-based client-side collective prefetching cache layer for MPI-IO library to support prefetching. A prefetching thread reads I/O signatures of an application and adjusts them by observing I/O accesses at runtime. Experimental results show that the proposed prefetching method improves I/O performance significantly for applications with complex patterns.
12297104
CoStore: a reliable and highly available storage system using clusters
The CoStore cluster architecture is proposed to construct a reliable and highly available storage system. A prototype CoStore was implemented and its performance was measured with the cluster being mirrored in various network environments. The preliminary results demonstrate that there is little impact on performance if the cluster is mirrored in efficient campus network environments with high bandwidth and low latency. As a result the CoStore architecture considerably reinforces a storage system's preparedness for disaster recovery without sacrificing performance.
14925300
A Taxonomy of Data Prefetching Mechanisms
Data prefetching has been considered an effective way to mask data access latency caused by cache misses and to bridge the performance gap between processor and memory. With hardware and/or software support, data prefetching brings data closer to a processor before it is actually needed. Many prefetching techniques have been proposed in the last few years to reduce data access latency by taking advantage of multi-core architectures. In this paper, we propose a taxonomy that classifies various design concerns in developing a prefetching strategy. We discuss various prefetching strategies and issues that have to be considered in designing a prefetching strategy for multi-core processors.
417212
Taxonomy of Data Prefetching for Multicore Processors
Data prefetching is an effective data access latency hiding technique to mask the CPU stall caused by cache misses and to bridge the performance gap between processor and memory. With hardware and/or software support, data prefetching brings data closer to a processor before it is actually needed. Many prefetching techniques have been developed for single-core processors. Recent developments in processor technology have brought multicore processors into mainstream. While some of the single-core prefetching techniques are directly applicable to multicore processors, numerous novel strategies have been proposed in the past few years to take advantage of multiple cores. This paper aims to provide a comprehensive review of the state-of-the-art prefetching techniques, and proposes a taxonomy that classifies various design concerns in developing a prefetching strategy, especially for multicore processors. We compare various existing methods through analysis as well.
43007315
The impact of smart disks and spatial reuse property on RAID-5 storage systems
RAID storage systems using SCSI and traditional disk drives cannot meet the growing demand of new I/O intensive applications. New technologies such as smart disks and SSA are being proposed to improve the performance, scalability, and reliability of RAID systems. The objective of this work is to investigate the impact of smart disks and SSA's spatial reuse property on the performance of RAID-5 storage systems. In order to perform this work, we have enhanced CMU's RAIDframe simulator so that it accurately models the overhead of current SCSI and SSA protocols, and we have created smart disk models which include on-drive XOR logic and on-drive caches. We observe that neither smart disks alone nor spatial reuse property alone has much impact on RAID system performance. However, if smart disks and spatial reuse property are properly used in combination, RAID-5 system performance and scalability can be further enhanced. In particular, we propose a parity caching approach to improve the performance of small writes.
17024398
Runtime parallel incremental scheduling of DAGs
A runtime parallel incremental DAG scheduling approach is described in this paper. A DAG is expanded incrementally, scheduled, and executed on a parallel machine. A DAG scheduling algorithm is parallelized to scale to large systems. In this approach, a large DAG can be executed without consuming large amount of memory space. Inaccurate estimation of task execution time and communication time can be tolerated. This runtime approach can also execute dynamic DAGs. Implementation of this parallel incremental system demonstrates the feasibility of this approach. Preliminary results show that it is superior to other approaches.
45747323
Generalized algebraic method and new exact traveling wave solutions for (2+1)-dimensional dispersive long wave equation
Abstract With the help of the symbolic computation system Maple , a new generalized algebraic method to uniformly construct solutions in terms of special function of nonlinear partial differential equations is presented by means of a more general ansatz. As an application of the method, we choose a (2 + 1)-dimensional dispersive long wave equation to illustrate the method. As a result, we can successfully obtain the solutions found by the method proposed by Fan [E.G. Fan, Phys. Lett. A 300 (2002) 243] and find other new and more general solutions at the same time, which include polynomial solutions, exponential solutions, rational solutions, triangular periodic wave solutions, hyperbolic, and soliton solutions, Jacobi, and Weierstrass doubly periodic wave solutions.
11827610
A Runtime System for Dynamic DAG Programming
A runtime system is described here for dynamic DAG execution. A large D A G whihc represents an application program can be executed on a parallel system without consuming large amount of memory space. A DAG scheduling algorithm has been parallelized to scale to large systems. Inaccurate estimation of task execution time and comm unication time can be tolerated. Implementation of this parallel incremental system demonstrates the feasibility of this approach. Preliminary results show that it is superior to other approaches.
16724396
Weighted Rough Graph and Its Application
Rough graph is the graph that can be used to research uncertainty problems, and it is a new research tool to analyze the rough characteristic of the system according to Tong He and Kaiquan Shi. This paper makes further research on rough graph, and gives the definitions of class connection of rough graph and some subgraphs of rough graph. Furthermore, this paper presents the definition of weighted rough graph by enduing the edges of rough graph with weight attribute, and gives the algorithm of exploring the class optimal tree in weighted rough graph, which generalizes the classical Kruskal algorithm of exploring the optimal tree. Finally, the application in relationship analysis shows the effectiveness of the algorithm
27063773
Aspect-Oriented Middleware-Based Real-Time and Embedded Systems Software Process
Middleware facilitates the development of real-time and embedded systems. However, middleware itself is becoming increasingly complex. Using the methodology of aspect-oriented software development to analyze and reconstruct the architecture of middleware can make the architecture more modularized and more customizable. In addition, since middleware plays a significant role in the realtime and embedded systems development, its characteristics must be considered in the entire real-time and embedded systems software process from requirements analyze phase to testing phase. This paper provides two contributions to the study of real-time and embedded systems development. First, presents the problems of current middleware architecture and analyzes functional requirements and non-functional requirements of aspect-oriented middleware. Second, proposes an aspect-oriented middleware based real-time and embedded systems software process. Both functional and non-functional characteristics of middleware are considered in all phases of the software process.