14751549
Energy-Efficient Cluster Computing via Accurate Workload Characterization
This paper presents an eco-friendly daemon that reduces power and energy consumption while better maintaining high performance via an accurate workload characterization that infers “processor stall cycles due to off-chip activities.” The eco-friendly daemon is an interval-based, run-time algorithm that uses the workload characterization to dynamically adjust a processor’s frequency and voltage to reduce power and energy consumption with little impact on application performance. Using the NAS Parallel Benchmarks as our workload, we then evaluate our eco-friendly daemon on a cluster computer. The results indicate that our workload characterization allows the power-aware daemon to more tightly control performance (5% loss instead of 11%) while delivering substantial energy savings (11% instead of 8%).
12054444
Modeling and analysis of power in multicore network processors
With the emergence of multicore network processors in support of high-performance computing and networking applications, power consumption has become a problem of increasing significance. Lower-power multicore processors, such as the Intel IXP network processors, have been employed in network devices to try to address this problem; however, effective tools are still needed to assist in the exploration of the "performance versus power" design space. In this paper, we present a composite power model that simultaneously leverages three existing power-modeling tools (Cacti, Wattch, and Orion) to model the power consumption of Intel IXP2400. This model is then integrated with an open-source Intel IXP2400 NP simulator called NePSim2 and validated against its datasheet to within 5% of actual power consumption. We utilize the simulator and power model to explore how architectural parameters affect the performance and power consumption of a set of high-performance security applications, thus delivering valuable insights to chip architects for designing energy-efficient multicore network processors.
4516164
Visual Hierarchical Dimension Reduction for Exploration of High Dimensional Datasets
Traditional visualization techniques for multidimensional data sets, such as parallel coordinates, glyphs, and scatterplot matrices, do not scale well to high numbers of dimensions. A common approach to solving this problem is dimensionality reduction. Existing dimensionality reduction techniques usually generate lower dimensional spaces that have little intuitive meaning to users and allow little user interaction. In this paper we propose a new approach to handling high dimensional data, named Visual Hierarchical Dimension Reduction (VHDR), that addresses these drawbacks. VHDR not only generates lower dimensional spaces that are meaningful to users, but also allows user interactions in most steps of the process. In VHDR, dimensions are grouped into a hierarchy, and lower dimensional spaces are constructed using clusters of the hierarchy. We have implemented the VHDR approach into XmdvTool, and extended several traditional multidimensional visualization methods to convey dimension cluster characteristics when visualizing the data set in lower dimensional spaces. Our case study of applying VHDR to a real data set supports our belief that this approach is effective in supporting the exploration of high dimensional data sets.
16524990
Optical Watermarking for Printed Document Authentication
This article describes a novel visual information concealment technique, referred to as optical watermarking, for the authentication of original printed documents. An optical watermark is a two-dimensional binary image. It can be of any shape and can be printed on any part of a document. The optical watermark is constructed by the superposition of multiple two-dimensional binary images (referred to as layers), each with different carrier structural patterns embedding various hidden information. The hidden information is embedded into each layer using phase modulation. Based on properties of the human visual system and modulation principle, the hidden information becomes visible to the human eyes only when a right "key" is positioned on top of the optical watermark with the right alignment. Here, "keys" play the similar role as keys in encryption, that is, to decode hidden information. Thus, with such a "lock and key" approach, it greatly improves the security level of the optical watermark. In addition, the multiple layer structure of the optical watermark makes it extremely robust against reverse engineering attacks. Due to its high security and tight link with electronic document systems, which requires documents to be finally printed on paper, the optical watermark has been applied to various electronic document systems. These are online ticketing, online bill of lading, and remote signing and printing of documents, where critical and unique information are embedded in watermarks and printed together with individual documents for future authentication. It has also been used in offline and traditional antiforgery applications, such as brand protection, preprinted high-value tickets, and identification documents
14294066
A novel methodology for transistor-level power estimation
Transistlw-level power simulators, which are more accurate than logic-level power estimators, have been popularly used to estimate the power dissipation of CMOS circuits. In this papel; we introduce cc1 method which extends the Monte-Carlo approach for deriving the average power dissipation of a circuit using transistor-level power simulators. To reduce the simulation time, we propose a mixedlevel extrapolation technique to speed up the convergence rate of the process, and thereby to achieve a good balance between simulation time and accuracy. Experimental results show that this is a promising method for deriving the accurate power dissipation of a circuit within reasonable time budget. 1. Introdiuction For a CIMOS circuit, the power dissipation is primarily caused by three types of currents: device leakage current, short-circuit current, and dynamic transition current. It is known that the power dissipation caused by device leakage current (staric current) is usually very small and negligible as compared with the dynamic transition current. The shortcircuit curre:nt occurs whenever a path from v,d to ground is conducted at a device for a short period of time. In some cases, shon:-circuit current cannot be ignored. However, only the trimistor-level simulators with continuous-time modeling of the device can accurately take this part into
16761691
Phatpackets for Data Transport within an HPC Network
Phatpackets is a term used to describe an open source initiative to reliably move large amounts of data more efficiently across the Internet. The Phatpackets protocol attempts to combine the best aspects of a variety of transport and control methods with the objective of developing a near optimal and robust protocol under a wide range of conditions and parameters. Here we discuss experimental results obtained moving large datasets between HPC nodes over the CAnet3 backbone. The HPC nodes are located at a number of Canadian Universities with a variety of access bandwidths.
120445321
Predictor-corrector method for linear complementarity problems with polynomial complexity and superlinear convergence
AbstractWe extend the Mizuno-Todd-Ye predictor-corrector algorithm for solving monotone linear complementarity problems. We prove that the extended algorithm is globally Q-linearly convergent and solves problems with integer data of bitlengthL in at most
$$O(\sqrt n L)$$
 iterations. We also prove that the duality gap converges to zero Q-superlinearly for problems having strictly complementary solutions. Our results generalize the results obtained by Ye, Tapia, and Zhang for linear programming.