117675
Analysis of Deskew Signaling Via Adaptive Timing
This paper presents an adaptive timing method for analysis of deskew signaling in high-performance integrated systems. The proposed approach models the practical deskew schemes as an adaptive system to study the performance limit of deskew signaling. We investigate the statistical properties of optimal deskew, which can be considered as the theoretical limit of deskew signaling. This approach also allows us to study the related energy efficiency issues in deskew schemes. We determine the bound on energy efficiency subject to the performance constraint on deskew signaling. Simulation results show that the performance of practical deskew schemes in a 90-nm process is 23.2% away from the optimal deskew scheme, and the gap of energy efficiency is 51% above the bound.
6708583
Reducing error accumulation effect in multithreaded memory systems
Chip multithreading is exposed to dual challenges of increasing chip complexity and design variations. It is important to develop effective reliability-enhancing schemes to ensure robust computing. In this paper, we propose the immediate write-back and self-recovery schemes to reduce error accumulation effect in multithreaded memory systems. These schemes are built upon the previously proposed dynamic multithreading redundancy technique for improving reliability in multithreaded architectures. The idea of DMR is to exploit self-generated hardware redundancy due to inter-thread variations inherent in multithreaded architectures. Simulation results demonstrate that the proposed solutions improve error-control performance with minimal hardware overheads. The proposed immediate write-back and self-recovery schemes also feature good scalability for future process generations
36279845
Exploiting soft redundancy for error-resilient on-chip memory design
8890864
Improving Error Tolerance for Multithreaded Register Files
Chip multithreaded computing is exposed to the dual challenges of increasing system complexity and error sensitivity. It is critical to develop effective solutions that achieve better error tolerance without inducing performance degradation. In this paper, we propose a new error-tolerant memory design based on a unique computing phenomenon referred to as the dynamic multithreading redundancy (DMR). The proposed technique exploits the interplay between the concurrent threads for runtime error control. We also present two DMR enhancements, immediate write-back and self-recovery, to address the error accumulation effect. A multithreaded register file was implemented to demonstrate the proposed DMR technique. Simulation results on the SPEC CPU2000 benchmarks demonstrate significant overhead reduction in performance and energy efficiency related to error recovery. In addition, the proposed technique features good scalability with respect to the instruction-level and thread-level parallelism for next-generation processor design, where the soft error problem is expected to get worse due to technology scaling and architecture-affecting trends.
16020986
Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation
Nanoelectronic devices are considered to be the computational fabrics for the emerging nanocomputing systems due to their ultra-high speed and integration density. However, the imperfect bottom-up self-assembly fabrication leads to excessive defects that have become a barrier for achieving reliable computing. In addition, transient errors continue to be a problem. The massive parallelism rendered by nanoscale integration opens up new opportunities but also poses challenges on how to manage such massive resources for reliable and high-performance computing. In this paper, we propose a nanoarchitecture solution to address these emerging challenges. By using dynamic redundancy allocation, the massive parallelism is exploited to jointly achieve fault (defect/error) tolerance and high performance. Simulation results demonstrate the effectiveness of the proposed technique under a range of fault rates and operating conditions.
18869116
Thread-Associative Memory for Multicore and Multithreaded Computing
Presented in this paper is the thread-associative memory microarchitecture for multicore and multithreaded processor design. Memory contention among concurrent threads in chip multithreaded processing has become a limiting factor for performance improvement. The proposed thread-associative memory addresses this challenge by incorporating thread-specific information explicitly into on-chip memory hardware. The proposed technique can be utilized at different levels of memory hierarchy. Furthermore, it is not just a technique for performance enhancement but also a solution for energy efficiency. Trace-driven simulations on a 32KB L1 data cache demonstrate 36.6% maximum performance improvement and up to 15.1% total energy reduction, with 20.3% dynamic energy reduction and 9.9% leakage energy reduction
14940474
The Representation of Chinese Semantic Knowledge and its Application in the Document Copy Detection
Digital documents are easily copied and distributed ille- gally. Document copy detection is a powerful tool to pro- tect the author's intellectual property and to improve the efficiency of information retrieval. It is difficult for the ex- isting copy detection systems to identify the sentence struc- ture changed copies. To address the problem, we research the semantic level of natural language processing and pro- pose a document copy detection method based on Chinese semantic knowledge. We introduce the realization mecha- nisms of Chinese language analysis, which contains syn- tactic parsing and semantic analyzing. We also report on the experimental comparison the proposed method with the representative document copy detection systems. The result is satisfying.
17154425
Background Subtraction using Incremental Subspace Learning
Background modeling and subtraction is a basic component of many computer vision and video analysis applications. It has a critical impact on the performance of object tracking and activity analysis. In this paper, we propose an effective and adaptive background modeling and subtraction approach that can deal with dynamic scenes. The proposed approach uses a subspace learning method to model the background and the subspace is updated on-line with a sequential Karhunen-Loeve algorithm. A linear prediction model is also used to make the detection more robust. Experimental results show that the proposed approach is able to model the background and detect moving objects under various type of background scenarios with close to real-time performance.
17047961
Image annotations by combining multiple evidence & wordNet
The development of technology generates huge amounts of non-textual information, such as images. An efficient image annotation and retrieval system is highly desired. Clustering algorithms make it possible to represent visual features of images with finite symbols. Based on this, many statistical models, which analyze correspondence between visual features and words and discover hidden semantics, have been published. These models improve the annotation and retrieval of large image databases. However, current state of the art including our previous work produces too many irrelevant keywords for images during annotation. In this paper, we propose a novel approach that augments the classical model with generic knowledge-based, WordNet. Our novel approach strives to prune irrelevant keywords by the usage of WordNet. To identify irrelevant keywords, we investigate various semantic similarity measures between keywords and finally fuse outcomes of all these measures together to make a final decision using Dempster-Shafer evidence combination. We have implemented various models to link visual tokens with keywords based on knowledge-based, WordNet and evaluated performance using precision, and recall using benchmark dataset. The results show that by augmenting knowledge-based with classical model we can improve annotation accuracy by removing irrelevant keywords.
30742448
Exact Distribution of the Amplitude of Adaptively Selected OFDM Signal Samples
The combination of deliberate clipping and an adaptive symbol selection scheme (ASSS) can be used to reduce the peak to average power ratio (PAPR) for Orthogonal Frequency Division Multiplexing (OFDM) signals. The probability density function (pdf) of a sample's amplitude of an adaptively selected OFDM signal without over-sampling has been considered to be approximately equal to the Rayleigh pdf. In this letter, we derive the exact pdf showing the relationship between the probability distribution of the sample's amplitude and the number of candidate OFDM symbols for ASSS. The use of the newly derived pdf can measure the effect of deliberate clipping on the adaptively selected OFDM signal more accurately.
38710648
A Resource Allocating Neural Network Based Approach for Detecting End-to-End Network Performance Anomaly
Automatic detection of end-to-end network performance anomalies is important to efficient network management and optimization. We present an end-to-end network performance anomalies detection method, based on characterizing of the dynamic statistical properties of RTT normality. The experiment on real Internet end-to-end path RTT data shows that, the proposed method is accurate in detecting performance anomalies, it can successfully detect about 96.25% anomalies in the experiment.