2723209
An energy-efficient skew compensation technique for high-speed skew-sensitive signaling
Presented in this paper is an energy-efficient skew compensation technique referred to as the resistance-based distributed clock deskew (RDSK) technique. In comparison with the existing clock deskew techniques, the proposed RDSK technique achieves significant power reduction while maintaining effective in skew management. Furthermore, the proposed RDSK provides a better scalability for future technology scaling. Simulation results of an on-chip interconnect communication system with distributed receivers designed in a 0.10 /spl mu/m CMOS process demonstrate 20%-51% power reduction over the existing techniques. The proposed RDSK is an essential element of our adaptive timing framework where circuit performance can be adjusted adaptively in response to time-varying disturbances and uncertainties.
16020986
Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation
Nanoelectronic devices are considered to be the computational fabrics for the emerging nanocomputing systems due to their ultra-high speed and integration density. However, the imperfect bottom-up self-assembly fabrication leads to excessive defects that have become a barrier for achieving reliable computing. In addition, transient errors continue to be a problem. The massive parallelism rendered by nanoscale integration opens up new opportunities but also poses challenges on how to manage such massive resources for reliable and high-performance computing. In this paper, we propose a nanoarchitecture solution to address these emerging challenges. By using dynamic redundancy allocation, the massive parallelism is exploited to jointly achieve fault (defect/error) tolerance and high performance. Simulation results demonstrate the effectiveness of the proposed technique under a range of fault rates and operating conditions.
8890864
Improving Error Tolerance for Multithreaded Register Files
Chip multithreaded computing is exposed to the dual challenges of increasing system complexity and error sensitivity. It is critical to develop effective solutions that achieve better error tolerance without inducing performance degradation. In this paper, we propose a new error-tolerant memory design based on a unique computing phenomenon referred to as the dynamic multithreading redundancy (DMR). The proposed technique exploits the interplay between the concurrent threads for runtime error control. We also present two DMR enhancements, immediate write-back and self-recovery, to address the error accumulation effect. A multithreaded register file was implemented to demonstrate the proposed DMR technique. Simulation results on the SPEC CPU2000 benchmarks demonstrate significant overhead reduction in performance and energy efficiency related to error recovery. In addition, the proposed technique features good scalability with respect to the instruction-level and thread-level parallelism for next-generation processor design, where the soft error problem is expected to get worse due to technology scaling and architecture-affecting trends.
16558773
Utilizing quantum dot transistors with programmable threshold voltages for low-power mobile computing
Power consumption poses one of the fundamental barriers for deploying mobile computing devices in energy-constrained situations with varying operation conditions. In particular, leakage power is projected to increase exponentially in future semiconductor process nodes. This challenging problem is pressing for renewed focus on power-performance optimization at all levels of design abstract, from novel device structures to fundamental shifts in design paradigm. In this article, we propose to exploit the programmable threshold voltage quantum dot (QD) transistors to reduce leakage thereby improving the energy efficiency for mobile computing. The unique programmability and reconfigurability enabled by QD transistors extend our capability in design optimization for new power-performance trade-offs. Simulation results demonstrate the significant leakage reduction over conventional techniques.
36279845
Exploiting soft redundancy for error-resilient on-chip memory design
18869116
Thread-Associative Memory for Multicore and Multithreaded Computing
Presented in this paper is the thread-associative memory microarchitecture for multicore and multithreaded processor design. Memory contention among concurrent threads in chip multithreaded processing has become a limiting factor for performance improvement. The proposed thread-associative memory addresses this challenge by incorporating thread-specific information explicitly into on-chip memory hardware. The proposed technique can be utilized at different levels of memory hierarchy. Furthermore, it is not just a technique for performance enhancement but also a solution for energy efficiency. Trace-driven simulations on a 32KB L1 data cache demonstrate 36.6% maximum performance improvement and up to 15.1% total energy reduction, with 20.3% dynamic energy reduction and 9.9% leakage energy reduction
22784392
The Application of Non-linear Regression Method to the Functional Connectivity during the Encoding and the Retrieval of Chinese Semantic Memory
Here, the tests about the study of Chinese semantic are presented. The experiments are performed on 9 healthy university students by using the scalp EEG and by using the pictures of Chinese words and idioms as stimuli. The mapping of the power density spectrums are adopted to detect the cognition-related region in the working memory including the memory and the retrieval. The non-linear regression method is available to investigate the interactions in these brain areas and the statistical measurement, ANOVA is utilized to get the significance of interdependencies differences between the working memory and before memory. It is concluded that not only the power density spectrums of gamma oscillations are significantly strengthened, but also the interdependencies in the prefrontal brain region are increased during these memory tasks on all subjects. It is indicated that it is possible to exist the strong feature modulations of attention in the local brain regions during the short-time memory of Chinese semantics.
17864197
Low-complexity adaptive step size constrained constant modulus SG algorithms for adaptive beamforming
In this paper, we propose two low-complexity adaptive step size mechanisms to enhance the performance of stochastic gradient (SG) algorithms for adaptive beamforming. The beamformer is designed according to the constrained constant modulus (CCM) criterion and the proposed mechanisms are employed in the SG algorithm for implementation. A complexity comparison is provided to show their advantages over existing methods, and a sufficient condition for the convergence of the mean weight vector is established. Theoretical expressions of the excess mean-squared error (EMSE), in both the steady-state and tracking cases, are derived based on the energy conservation approach. The effects of multiple access interference (MAI) and additive noise are considered. Simulation experiments are presented for both the stationary and non-stationary scenarios, illustrating that the proposed algorithms achieve superior performance compared with existing methods, and verifying the accuracy of the analyses.
1462661
Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers
Presented in this paper is a low-power technique, denoted as MIMO-AEC, to reduce energy dissipation in multi-input-multi-output (MIMO) signal processing systems. The proposed technique extends a previously proposed adaptive error-cancellation (AEC) technique to MIMO systems by employing an algorithm transformation denoted as MIMO-DECOR. The purpose of MIMO-DECOR is to reduce complexity by exploiting correlations inherent in MIMO systems, thereby improving the effectiveness of AEC. We employ the MIMO-AEC in the design of a low-power Gigabit Ethernet 1000Base-T device. Simulation results demonstrate 44.3% - 25.2% overhead reduction due to MIMO-DECOR and 69.1% - 64.2% energy savings over conventional implementations with no loss in algorithmic performance.
8984253
Recognizing Chinese Proper Nouns with Transformation-Based Learning and Ontology
This paper proposes an approach based on the Ontology and transformation-based error-driven learning (TBL) to recognize Chinese proper nouns. Firstly, our approach redefines the label set and tags Chinese words according to the usage of proper nouns and their context, and then it extracts Characteristic Information (CI) of the proper noun from the text and merges them based on the Ontology. Secondly, it tags the training corpus following the new definition of Multi-dimension Attribute Points (MAP), and then extracts rules using the TBL approach. Finally, it recognizes proper nouns by utilizing the rule set and Ontology. The experimental results in our open test show that the precision is 92.5% and the recall is 86.3%.
7983053
Auto-Calibration of a Compound-Type Omnidirectional Camera
We propose a method for auto-calibrating a compound-type omnidirectional camera (system). This camera produces spherical panoramic image through stitching some individual images captured by several modular cameras, each of which covers a different field of view of the full viewing sphere. By auto-calibration we mean that our algorithm works online in a self-calibration manner: it receives as input image point correspondences only, and outputs all the camera parameters. The calibration task consists of lens-distortion-removal, intrinsic-calibration, and relative-orientation. The focus of the paper is an algorithm for automatically removing lens distortion. By exploiting planar projective invariants, our algorithm is capable of estimating centre-of-distortion and distortion parameters efficiently without using any nonlinear iteration.