35084564
Effect of test condition and stress free temperature on the electromigration failure of Cu dual damascene submicron interconnect line-via test structures
Atomic flux divergence (AFD) based finite element analyses have been performed to show the difference in the electromigration (EM) failure mechanisms at different test conditions for Cu dual damascene line-via test structures. A combined driving force approach adapted in the model consists of driving forces from electron-wind, stress-migration and thermo-migration. It is shown that the failure mechanisms depend on the test condition and the stress free temperature of the structure. As the failure time depends on the failure mechanisms, the life-time prediction from accelerated test would be inaccurate if the invariability of failure mechanisms is assumed. It is also found that the interconnect life-time can be improved by lowering the final annealing temperature of the structure.
26545951
Placement of scattering bars in binary and attenuated phase shift mask for damascene trench patterning
Abstract Scattering bars have been very effective technique to increase the common lithography process window for patterns with design rules 0.18 μm and below. This paper studies the placement of scattering bars in binary and attenuated phase shift mask in damascene trench patterning. Different partial coherence values are used to compare the scattering bar effect in binary and 8% attenuated phase shift mask. At low partial coherence ( σ ) the trench size has been found more sensitive to scattering bar parameters than at high σ . Scattering bar separation is found more effective than size to affect the trench critical dimension (CD). At low partial coherence a deep valley or ‘V’ shaped CD trend is found in scattering bar separation versus CD curve. CD dip is more using APSM as compared to binary mask. The process latitude is poor at valley as compared to top. Also, 3 sigma CD variation and range is higher at valley as compared to other separations of the scattering bars.
1111313
Resist pattern peeling assessment in DUV chemically amplified resist
As device size shrinks resist line peeling becomes more challenging. In this paper we studied the resist pattern peeling based on resist processing parameters and type of bottom antireflective coating (BARC), for patterning trench structures with different duty ratios, in copper and low k dual damascene process. To minimize resist poisoning in dual damascene process, acetal-based resist was used. Significant improvement in via poisoning was observed with this chemistry as compared to environmentally stable chemically amplified resist chemistry but at the cost of pattern peeling. In order to solve pattern peeling problem we tried to analyze key factors such as compatibility with BARC, post-exposure bake, BARC curing, adhesion and their effects. Pitch dependency on pattern peeling margin is observed.
23462768
A method for deep etching in dielectric films for 3D-chip and photonics applications
Abstract In this paper, RIE of thick undoped silicate glass (USG) films for various applications is described. Though moderate etch rates (∼0.4 μm/min) were achieved for USG film, process development was quite challenging due to stringent requirements of deep USG etching (>6 μm) and vertical profile. Alternatively, etch process with higher etch rate (1.0 μm/min) was also evaluated for profile angle and results were found not comparable to low etch rate process. However, low etch rate process was found to have tool limitations and an alternate method called ‘discrete etching’ was proposed and successfully verified. Promising results were obtained with etch depth (6 μm) and vertical profile (∼89.50°) in USG as well as SiON films. Based on the results discrete etching method was found to have provided advantage of unlimited capability for deep etching.
135903312
Determination of the hardness and elastic modulus of low- k thin films and their barrier layer for microelectronic applications
This paper presents the experimental results and analysis of the elastic modulus and hardness for several thicknesses of dielectric films, namely low-k films and their barrier layer, using the nano-indentation technique. The elastic modulus and hardness of the films were determined by "normal" nano-indentation analysis. The data were then analyzed by rearranging the load-displacement data (P-h) obtained by nano-indentation in such a way that the applied load divided by the corresponding displacement (P/h) versus the displacement (h) was obtained, which effectively differentiates the film-only mechanical properties from those of the substrate. The low-k film, carbon-doped silicon oxide (SiOC), was prepared using a parallel plate PECVD system. The dielectric constant of the low-k film was measured to be 3.09, which is much lower than that of commonly used dielectric materials such as SiO2 (k ∼ 3.9). The hardness and elastic modulus of the film were measured to be approximately 2.23 and 13.98 GPa, respectively. To enhance the mechanical properties of the low-k thin film, a low-k barrier layer (SiCN:H) with better mechanical properties was deposited between the low-k film and the substrate or on top of the low-k film. It was found that the barrier layer improved the mechanical properties of the low-k film and the barrier layer stacked in certain circumstances. The effects of the arrangement of the barrier layer and the low-k film on the mechanical behavior of the bi-layer system were studied in detail.
2765279
PEET: Prototype Embedding and Embedding Transition for Matching Vehicles over Disparate Viewpoints
This paper presents a novel framework, prototype embedding and embedding transition (PEET), for matching objects, especially vehicles, that undergo drastic pose, appearance, and even modality changes. The problem of matching objects seen under drastic variations is reduced to matching embeddings of object appearances instead of matching the object images directly. An object appearance is first embedded in the space of a representative set of model prototypes (prototype embedding (PE)). Objects captured at disparate temporal and spatial sites are embedded in the space of prototypes that are rendered with the pose of the cameras at the respective sites. Low dimensional embedding vectors are subsequently matched. A significant feature of our approach is that no mapping function is needed to compute the distance between embedding vectors extracted from objects viewed from disparate pose and appearance changes, instead, an embedding transition (ET) scheme is utilized to implicitly realize the complex and non-linear mapping with high accuracy. The heterogeneous nature of matching between high-resolution and low-resolution image objects in PEET is discussed, and an unsupervised learning scheme based on the exploitation of the heterogeneous nature is developed to improve the overall matching performance of mixed resolution objects. The proposed approach has been applied to vehicular object classification and query application, and the extensive experimental results demonstrate the efficacy and versatility of the PEET framework.
36557391
Toward a sentient environment: real-time wide area multiple human tracking with identities
In this paper, we presented a fully integratedreal-time computer vision system that can detect and track multiple humans in a wide-area using a network of stereo cameras. Continuous human identities are achieved by fusing video tracking with different kinds of biometric devices. The system also provides immersive visualization which enables the users to conveniently navigate through space and time and query useful events. The key innovations include stereo-based multi-object detection and tracking, a unified approach for fusing multiple sensors of different modalities, visualization and user interface design.
12932631
Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05)
Chip multiprocessor architectures are becoming increasingly attractive as an option to provide high instruction throughput while keeping power and complexity under control. Such architectures have also been shown to have scalability and productivity advantages. Multi-core processors are fast becoming mainstream.
17883534
3D manipulation of motion imagery
We present a set of automatic methods for the recovery and refinement of 3D scene geometry and camera poses from motion imagery. First, we present a two-frame "direct" method, which simultaneously estimates both relative pose between the cameras and 3D scene geometry using information from the images alone. Second, we discuss how to automatically estimate pose and scene geometry using extended sequences. Third, we present methods for recovery of pose when a scene model is known a priori. We show how the recovered pose can be use to extend and refine the scene model. Finally, we present applications of the above techniques for 3D imagery manipulation such as enhanced visualization of video, synthetic view generation and insertion of synthetic objects in the imagery.
214800957
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class of interconnect architectures. It shows that the design choices for the interconnect have significant effect on the rest of the chip, potentially consuming a significant fraction of the real estate and power budget. This research shows that designs that treat interconnect as an entity that can be independently architected and optimized would not arrive at the best multi-core design. Several examples are presented showing the need for careful co-design. For instance, increasing interconnect bandwidth requires area that then constrains the number of cores or cache sizes, and does not necessarily increase performance. Also, shared level-2 caches become significantly less attractive when the overhead of the resulting crossbar is accounted for. A hierarchical bus structure is examined which negates some of the performance costs of the assumed base-line architecture.