205664504
Constrained algorithmic IP design for system-on-chip
In the system on chip design context, RTL design of complex digital signal processing coprocessors can be improved by using algorithmic description as input for the synthesis process. System integration, that is a major step in SoC design, requires taking into account communication and timing constraints to design and integrate dedicated hardware accelerator. In this paper, we propose a design flow based on formal models that allows high-level synthesis under input/output timing constraints of DSP algorithms. Based on a generic architecture, the presented method provides automatic generation of customized hardware components. We show the effectiveness of our approach in a case study of a maximum a posteriori (MAP) algorithm for turbo decoding.
15834659
Architectural Synthesis with Interconnection Cost Control
Architectural synthesis tools map algorithms to architectures under various constraints and quickly provide estimations of area and performance. However, these tools do not take the interconnection cost into account whereas it becomes predominant with the technology decrease and the application complexity increase. A way to control costly interconnections during the architectural process is presented in this paper.
34309839
Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems
The increasingly demanding requirements of multimedia applications have led to the definition of complex image and video coding standards such as JPEG2000 and MPEG4. Implementation of image or video encoders or decoders on mobile device requires high integration densities together with ability for "real-time" (on-the-fly) data processing. Today, the electronic system design community is mainly concerned with defining efficient System-on-a-Chip (SoC) design methodologies in order to benefit from the high integration capabilities of current application-specific integrated circuit and field-programmable gate array technologies on the one hand, and manage the increasing algorithmic complexity of applications on the other hand. Intellectual property (IP) reuse is considered as the key to speed up the system design and verification flow and make it more reliable.In this context, we have introduced a novel methodology for VLSI implementation of computation-intensive algorithms targeting digital signal processing applications. Our methodology combines IP reuse and high-level synthesis (HLS) and introduces the notion of "Behavioral IP". This approach aims at leveraging IP re-usability through functional and architectural flexibility based on: (1) modeling a component's behavior at a high abstraction level and (2) benefiting from HLS tools for architectural exploration and hardware generation.In this paper, we illustrate our methodology in the case of a 2-D discrete wavelet transform IP core for JPEG2000 image compression. We describe the successive views of the component throughout the design flow, from the application level down to the architectural level. We also provide synthesis results showing the variety of dedicated architectures that can be generated depending on user-defined functional-level, system-level and architectural-level requirements. We compare the performance and re-usability of the set of obtained architectures versus hand-crafted RTL specifications.
15462003
How to transform an architectural synthesis tool for low power VLSI designs
High level synthesis (HLS) for low power VLSI design is a complex optimization problem due to the area/time/power interdependence. As few low power design tools are available, a new approach providing a modular low power synthesis method is proposed. Although based for the moment on a generic architectural synthesis tool Gaut, the use of different "commercial" tools is possible. The Gaut-w HLS tool is constituted of low power modules: high level power dissipation estimation, assignment, module selection (operators and supply voltage), optimization criteria and operators library. As illustration, power saving factors on DWT algorithms are presented.
11449422
Functional level power analysis: an efficient approach for modeling the power consumption of complex processors
A high-level consumption estimation methodology and its associated tool, SoftExplorer, are presented. The estimation methodology uses a functional modeling of the processor combined with a parametric model to allow the designer to estimate the power consumption when the embedded software is executed on the target. SoftExplorer uses as input the assembly code generated by the compiler; its efficiency is compared to SimplePower's approach. Results for different processors (TI C62, C67, C55, and ARM7) and for several DSP applications provide an average error less than 5%.
5563691
Synchronization processor synthesis for latency insensitive systems
In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carloni et al. (2001). Our contribution consists in IP encapsulation into a new wrapper model whose speed and area are optimized and synthetizability guaranteed. The main benefit of our approach is to preserve the local IP performance when encapsulating them and reduce SoC silicon area.
30324632
Neural Network Based Algorithm for Radiation Dose Evaluation in Heterogeneous Environments
An efficient and accurate algorithm for radiation dose evaluation is presented in this paper. Such computations are useful in the radiotherapic treatment planning of tumors. The originality of our approach is to use a neural network which has been trained with several homogeneous environments to deduce the doses in any kind of environment (possibly heterogeneous). Our algorithm is compared in several representative contexts to a reference simulation code in the domain.
980414
A General Theory of Deduction, Induction, and Learning
Deduction, induction, learning, are various aspects of a more general scientific activity: the discovery of truth. We propose to embed them in a common, logical framework. First, we define a generalized notion of "logical consequence." Alternating compact and "weakly compact" consequences, we stratify the set of generalized logical consequences of a given theory in a hierarchy. Classical first-order logic is a particular case of this framework; the fact that it is all about deduction is due to the compactness theorem, and this is reflected by the collapsing of the corresponding hierarchy to the first level. Classical learning paradigms in the inductive inference literature provide other particular cases. Finite learning corresponds exactly to the first level (or level ?1) of the hierarchy, whereas learning in the limit corresponds to another level (namely ?2). More generally, strong and natural connections exist between our hierarchy of generalized logical consequences, the Borel hierarchy, and the hierarchy which measures the complexity of a formula in terms of alternations of quantifiers. It is hoped that this framework provides the foundation of a unified logic of deduction and induction, and highlights the inductive nature of learning. An essential motivation for our work is to apply the theory presented here to the design of "Inductive Prolog", a system with both deductive and inductive capabilities, based on a natural extension of the resolution principle.
33304178
Scientific Discovery Based on Belief Revision
Scientific inquiry is represented as a process of rational hypothesis revision in the face of data. For the concept of rationality, we rely on the theory of belief dynamics as developed in [5, 9]. Among other things, it is shown that if belief states are left unclosed under deductive logic then scientific theories can be expanded in a uniform, consistent fashion that allows inquiry to proceed by any method of hypothesis revision based on "kernel" contraction. In contrast, if belief states are closed under logic, then no such expansion is possible. ?
36905391
A note on the use of probabilities by mechanical learners
We raise the following problem: in a probabilistic context, is it always fruitful for a machine to compute probabilities? The question is made precise in a paradigm of the limit-identification kind, where a learner must discover almost surely whether an infinite sequence of heads and tails belongs to an effective subset S of the Cantor space. In this context, a successful strategy for an ineffective learner is to compute, at each stage, the conditional probability that he is faced with an element of S, given the data received so far. We show that an effective learner should not proceed this way in all circumstances. Indeed, even if he gets an optimal description of a set S, and even if some machine can always compute the conditional probability for S given any data, an effective learner optimizes his inductive competence only if he does not compute the relevant probabilities. We conclude that the advice “compute probabilities whenever you can” should sometimes be received with caution in the context of machine learning.
10369661
Identifying Clusters from Positive Data
The present work studies clustering from an abstract point of view and investigates its properties in the framework of inductive inference. Any class $S$ considered is given by a hypothesis space, i.e., numbering, $A_0,A_1,\ldots$ of nonempty recursively enumerable (r.e.) subsets of ${\mathbb{N}}$ or ${\mathbb{Q}^k}$. A clustering task is a finite and nonempty set of r. e. indices of pairwise disjoint such sets. The class $S$ is said to be clusterable if there is an algorithm which, for every clustering task $I$, converges in the limit on any text for $\bigcup_{i \in I} A_i$ to a finite set $J$ of indices of pairwise disjoint clusters such that $\bigcup_{j \in J} A_j = \bigcup_{i \in I} A_i$. A class is called semiclusterable if there is such an algorithm which finds a $J$ with the last condition relaxed to $\bigcup_{j \in J} A_j \supseteq \bigcup_{i \in I} A_i$. 
 
The relationship between natural topological properties and clusterability is investigated. Topological properties can provide sufficient or necessary conditions for clusterability, but they cannot characterize it. On the one hand, many interesting conditions make use of both the topological structure of the class and a well-chosen numbering. On the other hand, the clusterability of a class does not depend on which numbering of the class is used as a hypothesis space for the\break clusterer. 
 
These ideas are demonstrated in the context of naturally geometrically defined classes. Besides the text for the clustering task, clustering of many of these classes requires the following additional information: the class of convex hulls of finitely many points in a rational vector space can be clustered with the number of clusters as additional information. Interestingly, the class of polygons (together with their interiors) is clusterable if the number of clusters and the overall number of vertices of these clusters is given to the clusterer as additional information. Intriguingly, this additional information is not sufficient for classes including figures with holes. 
 
While some classes are unclusterable due to their topological structure, others are only computationally intractable. An oracle might permit clustering all computationally intractable clustering tasks but fail on some classes which are topologically difficult. It is shown that an oracle $E$ permits clustering all computationally difficult classes iff $E \geq_T K \wedge E' \geq_T K"$. Furthermore, no 1-generic oracle below $K$ and no 2-generic oracle permits clustering any class which is not clusterable without an oracle.