8988025
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing
This paper presents a technique to improve the storage density of spin-torque transfer (STT) magnetoresistive random access memory (MRAM) in the presence of significant magnetic tunneling junction (MTJ) write current threshold variability. In conventional design practice, the nMOS transistor within each memory cell is sized to be large enough to carry a current larger than the worst-case MTJ write current threshold, leading to an increasing storage density penalty as the technology scales down. To mitigate such variability-induced storage density penalty, this paper presents a smaller-than-worst-case transistor sizing approach with the underlying theme of jointly considering memory cell transistor sizing and defect tolerance. Its effectiveness is demonstrated using 256Mb STT MRAM design at 45nm node as a test vehicle. Results show that, under a normalized write current threshold deviation of 20%, the overall memory die size can be reduced by more than 20% compared with the conventional worst-case transistor sizing design practice.
14985315
Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin
This paper presents a new memory cell structure for content addressable memory (CAM) based on magnetic tunneling junction (MTJ). Each CAM cell uses a pair of differential MTJs as basic storage element and incorporates transistors to greatly improve the cell search noise margin at low sensing current. Using the same design principle, we further develop an area-efficient cell structure for ternary CAM (TCAM), which occupies about 25% less area compared with directly using two CAM cells to form one TCAM cell. The effectiveness of the proposed CAM and TCAM cell structures has been demonstrated by circuit simulation at 0.18 mum CMOS technology.
17935039
Data manipulation techniques to reduce phase change memory write energy
Due to its great scalability potential, phase change memory has become a topic of great current interest. However, high write energy consumption appears to be one of the biggest challenges to be tackled before phase change memory can be adopted as a mainstream memory technology. This paper presents architecture level technique to reduce phase change memory write energy consumption through data manipulations. Motivated by the fact that phase change memory read incurs much less energy than write and write of different value to a phase change memory cell incurs largely different energy, we present two memory write data manipulation techniques that can effectively reduce the overall memory write energy consumption. Their effectiveness has been demonstrated based on mathematical analysis and computer system simulation using phase change memory as the main memory in the computer memory hierarchy. Significant energy savings with up to more than 60% have been shown over a wide range of computer system benchmarks.
57229289
An algorithm for multiple object trajectory tracking
Most tracking algorithms are based on the maximum a posteriori (MAP) solution of a probabilistic framework called Hidden Markov Model, where the distribution of the object state at current time instance is estimated based on current and previous observations. However this approach is prone to errors caused by temporal distractions such as occlusion, background clutter and multi-object confusion. In this paper we propose a multiple object tracking algorithm that seeks the optimal state sequence which maximizes the joint state-observation probability. We name this algorithm trajectory tracking since it estimates the state sequence or "trajectory" instead of the current state. The algorithm is capable of tracking multiple objects whose number is unknown and varies during tracking. We introduce an observation model which is composed of the original image, the foreground mask given by background subtraction and the object detection map generated by an object detector The image provides the object appearance information. The foreground mask enables the likelihood computation to consider the multi-object configuration in its entirety. The detection map consists of pixel-wise object detection scores, which drives the tracking algorithm to perform joint inference on both the number of objects and their configurations efficiently.
4405529
BUPT at TREC 2006: Spam Track
This report summarizes our participation in the TREC 2006 spam track, in which we consider the use of Bayesian models for the spam filtering task. Firstly, our anti-spam filter, Kidult, is briefly introduced. And then we try to use weighted adjustment of separating hyper- plane and selective classifiers ensemble to improve the filtering performance. Finally, we sum- marize the relevant results from the official evaluation.
30599384
Category-based Web personalization system
There has been a massive growth in systems on the Internet that can personalize the content delivered to individual users. This paper develops a category-based Web personalization system in which an unconventional system logger, along with a category generator and a customizer, was designed. This system obtains and records more precise information directly from the users' activity and the objects they access. In addition, the system is designed with its own method to match and deliver individual information in which each user might be interested. Analysis and comparisons with related work are addressed in this research.
46077798
A Component-Based Analytical Performance Model of IP-Based SAN
In this paper we propose a component-based analytical performance model for IP-based SAN. This model evaluates and analyzes the behavior of IP network, cache, RAID and disks under multiple synchronous I/O workloads by using closed queueing networks. The theoretical results are compared with the results from a real IP-based SAN using a variety of synthetic workloads. These experiments prove that the component-based method is an appropriate way to build performance model for a complex storage system. Using the model, we can find out that the bottleneck of SAN performance is network or storage node under different workloads or applications. We also identify areas for future research in the performance analysis of real IP-based SAN.
13976369
Design of a nanosensor array architecture
This paper describes a nanowire sensor array architecture for high-speed, high-accuracy sensor systems. The chip has very simple processing elements (PEs) in a massively parallel architecture, in which each PE is directly connected to seven sensors. A sampling rate of 100 ns is enough to realized high-speed sensing feedback for electronic nose. We aim to create a very simple architecture, because a compact design is required ton integrate as many PEs as possible on a single chip. A widely used, easy to implement estimator-minimum distance classifier is introduced to realize the pattern recognition. A sample design is implemented in VHDL and has been simulated and synthesized using TSMC 0.25 standard cell library and a commercial 0.16 standard cell library.