9616848
Core architecture optimization for heterogeneous chip multiprocessors
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to design such a processor; instead, they started with an assumed combination of pre-existing cores. This work assumes the flexibility to design a multi-core architecture from the ground up and seeks to address the following question: what should be the characteristics of the cores for a heterogeneous multi-processor for the highest area or power efficiency? The study is done for varying degrees of thread-level parallelism and for different area and power budgets. The most efficient chip multiprocessors are shown to be heterogeneous, with each core customized to a different subset of application characteristics — no single core is necessarily well suited to all applications. The performance ordering of cores on such processors is different for different applications; there is only a partial ordering among cores in terms of resources and complexity. This methodology produces performance gains as high as 40%. The performance improvements come with the added cost of customization.
12932631
Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05)
Chip multiprocessor architectures are becoming increasingly attractive as an option to provide high instruction throughput while keeping power and complexity under control. Such architectures have also been shown to have scalability and productivity advantages. Multi-core processors are fast becoming mainstream.
205912378
The architecture of Efficient Multi-Core Processors: A Holistic Approach
Abstract The most straightforward methodology for designing a multi-core architecture is to replicate an off-the-shelf core design multiple times, and then connect the cores together using an interconnect mechanism. However, this methodology is “multi-core oblivious” as subsystems are designed/optimized unaware of the overall chip-multiprocessing system they would become parts of. The chapter demonstrates that this methodology is inefficient in terms of area/power. It recommends a holistic approach where the subsystems are designed from the ground up to be effective components of a complete system. The inefficiency in “multi-core oblivious” designs comes from many sources. Having multiple replicated cores results in an inability to adapt to the demands of execution workloads, and results in either underutilization or overutilization of processor resources. Single-ISA (instruction-set architecture) heterogeneous multi-core architectures host cores of varying power/performance characteristics on the die, but all cores are capable of running the same ISA. Such a processor can result in significant power savings and performance improvements if the applications are mapped to cores judiciously. The paper also presents holistic design methodologies for such architectures. Another source of inefficiency is blind replication of over-provisioned hardware structures. Conjoined-core chip multiprocessing allows adjacent cores of a multi-core architecture to share some resources. This can result in significant area savings with little performance degradation. Yet another source of inefficiency is the interconnect. The interconnection overheads can be very significant for a “multi-core oblivious” multi-core design—especially as the number of cores increases and the pipelines get deeper. The paper demonstrates the need to co-design the cores, the memory and the interconnection to address the inefficiency problem, and also makes several suggestions regarding co-design.
752417
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
This paper proposes and evaluates single-ISA heterogeneousmulti-core architectures as a mechanism to reduceprocessor power dissipation. Our design incorporatesheterogeneous cores representing different points inthe power/performance design space; during an application'sexecution, system software dynamically chooses themost appropriate core to meet specific performance andpower requirements.Our evaluation of this architecture shows significant energybenefits. For an objective function that optimizes forenergy efficiency with a tight performance threshold, for 14SPEC benchmarks, our results indicate a 39% average energyreduction while only sacrificing 3% in performance.An objective function that optimizes for energy-delay withlooser performance bounds achieves, on average, nearly afactor of three improvement in energy-delay product whilesacrificing only 22% in performance. Energy savings aresubstantially more than chip-wide voltage/frequency scaling.
113025
Distributed peak power management for many-core architectures
Recently proposed techniques for peak power management involve centralized decision-making and assume quick evaluation of the various power management states. These techniques do not prevent instantaneous power from exceeding the peak power budget, but instead trigger corrective action when the budget has been exceeded. Similarly, they are not suitable for many-core architectures (processors with tens or possibly hundreds of cores on the same die) due to an exponential explosion in the number of global power management states. In this paper, we look at a hierarchical and a gradient ascent-based technique for decentralized peak power management for many-core architectures. The proposed techniques prevent power from exceeding the peak power budget and enable the placement of several more cores on a die than what the power budget would normally allow. We show up to 47% (33% on average) improvements in throughput for a given power budget. Our techniques outperform the static oracle by 22%.
27580015
Register Multimapping: A technique for reducing register bank conflicts in processors with large register files
In this paper, we investigate Register Multimapping as a technique to reduce register bank conflicts for processors with large register files, but relatively slow clock speeds. Register multimapping involves mapping an architectural register to multiple physical registers belonging to different banks. Reads can proceed using any of the physical registers, thereby minimizing read bank conflicts. Write conflicts can be minimized by allowing delayed allocation of physical registers [5]. Our experiments show that register multimapping can result in performance improvements up to 15% (10% on average) over baseline processors that are port-constrained. Improvements are up to 13% (5.5% on average) over port-constrained processors that support delayed allocation of registers.
16117863
A Comparative Study of Different Sensors for Smart Car Park Management
Wireless sensor networks offer a very attractive, low cost alternative for traffic monitoring and surveillance in car parking, freeways and intersection in different environmental conditions. In such systems, robust and reliable vehicle detection is a critical step, thus it is important to carefully evaluate the different modes of operations in order to address existing issues. This paper proposes a vision of improvements to wireless sensor car parking network system by presenting valuable comparison data for different sensors using different type of software functions and hardware components. The main goal of this work is to present a simple, automated analysis and comparison of power management, communication efficiency and threshold times using different sensors and a corresponding prediction of the above features. The results show a clear difference in various parameters by using different types of sensors for vehicle detection.
14392689
Composition trust bindings in pervasive computing service composition
In pervasive computing, devices or peers may implement or compose services using services from other devices or peers, and may use components from various sources. A composition trust binding is a prescriptive set of rules which defines the combination of allowable components for a particular service or application. Composition trust bindings can be used to protect both the service invocation path as well as the content handling path. The subsidiary relationships addressed by a composition trust binding are typically transparent today, but represent potential security exposure in pervasive computing systems because the subsidiary services or components may have security vulnerabilities. We define the composition trust binding and illustrate its use in the context of rights management and distributed search in personal content publishing. We compare this approach to existing authentication and authorization methods in service composition
35084564
Effect of test condition and stress free temperature on the electromigration failure of Cu dual damascene submicron interconnect line-via test structures
Atomic flux divergence (AFD) based finite element analyses have been performed to show the difference in the electromigration (EM) failure mechanisms at different test conditions for Cu dual damascene line-via test structures. A combined driving force approach adapted in the model consists of driving forces from electron-wind, stress-migration and thermo-migration. It is shown that the failure mechanisms depend on the test condition and the stress free temperature of the structure. As the failure time depends on the failure mechanisms, the life-time prediction from accelerated test would be inaccurate if the invariability of failure mechanisms is assumed. It is also found that the interconnect life-time can be improved by lowering the final annealing temperature of the structure.
12166917
Learning Exemplar-Based Categorization for the Detection of Multi-View Multi-Pose Objects
This paper proposes a novel approach for multi-view multi-pose object detection using discriminative shapebased exemplars. The key idea underlying this method is motivated by numerous previous observations that manually clustering multi-view multi-pose training data into different categories and then combining the separately trained two-class classifiers greatly improved the detection performance. A novel computational framework is proposed to unify different processes of categorization, training individual classifier for each intra-class category, and training a strong classifier combining the individual classifiers. The individual processes employ a single objective function that is optimized using two nested AdaBoost loops. The outer AdaBoost loop is used to select discriminative exemplars and the inner AdaBoost is used to select discriminative features on the selected exemplars. The proposed approach replaces the manual time-consuming process of exemplar selection as well as addresses the problem of labeling ambiguity inherent in this process. Also, our approach fully complies with the standard AdaBoost-based object detection framework in terms of real-time implementation. Experiments on multi-view multi-pose people and vehicle data demonstrate the efficacy of the proposed approach.
16338795
Pose estimation, model refinement, and enhanced visualization using video
In this paper we present methods for exploitation and enhanced visualization of video given a prior coarse untextured polyhedral model of a scene. Since it is necessary to estimate the 3D poses of the moving camera, we develop an algorithm where tracked features are used to predict the pose between frames and the predicted poses are refined by a coarse to fine process of aligning projected 3D model line segments to oriented image gradient energy pyramids. The estimated poses can be used to update the model with information derived from video, and to re-project and visualize the video from different points of view with a larger scene context. Via image registration, we update the placement of objects in the model and the 3D shape of new or erroneously modeled objects, then map video texture to the model. Experimental results are presented for long aerial and ground level videos of a large-scale urban scene.