29654898
Analyzing crosstalk in the presence of weak bridge defects
An extensive simulation study of various combinations of resistive bridges and crosstalk has been performed and several notable properties that have significant implications for test development have been discovered. Scenarios have been identified where a combination of a bridge at one site and a crosstalk at a separate site in its transitive fanout (or vice versa) can cause slowdown/speed-up whose magnitude significantly exceeds the sum of the slow-down/speed-up, caused by each effect in isolation. It has also been identified that a test vector generated for crosstalk may in fact be invalidated due to the presence of a weak bridge at the crosstalk site. The properties discovered, provide the motivation for a more analytical study that will eventually lead to the proposed framework for test development.
30689090
Modeling and simulation for crosstalk aggravated by weak-bridge defects between on-chip interconnects
This paper presents comprehensive analytic models that consider both the case of a weak bridge, and the combination of a weak bridge and crosstalk between two interconnects. Our models capture the induced signal delay and pulse as a function of the parameters of the circuit and input signals. Our results are compared with HSPICE and shown to be accurate. A simulator is developed that implements our models and accurately captures timing (delay) characteristics of a circuit. We contrast our results with others, and show the benefits of this new model as well as the ability to predict the range of resistance that leads to delay errors.
25158433
Diagnosis of delay faults due to resistive bridges, delay variations and defects
In this paper, we present the first diagnosis algorithm for combinational circuit blocks that considers all combinations of multiple gate/wire delay variations/defects and any single resistive bridge. One key component of the proposed algorithm is a new path-oriented effect-cause procedure to identify all possible suspects of above type that might have caused the timing errors observed during test. The second key component is an efficient data structure to represent the suspects. The third key component is a new algorithm to analyze passing tests to vindicate some of the suspects identified. This algorithm exploits the newly identified concept of fixed-but-unknown delays, i.e., the fact that during the period of diagnosis the values of all delay parameters for every gate and wire in the particular circuit under test remain fixed, although at values unknown to us. The final set of suspects reported by the algorithm is guaranteed to contain all possible causes of the observed timing errors. Experimental results on benchmark circuits show the effectiveness of the proposed approach
7862909
A Study of Side-Channel Effects in Reliability-Enhancing Techniques
Reliability-enhancing techniques are critical for nanoscale integrated systems under the pressure of various physical non-idealities such as process variations and manufacturing defects. However, it is unclear how these techniques will affect the side-channel information leaked through hardware implementations. The related side-channel effects may have direct implications to the security requirement in a wide range of applications. In this paper, we investigate this new problem for trusted hardware design. Employing information-theoretic measures, the relationship between reliability enhancements and the induced side-channel effects is quantitatively evaluated. Simulation results on EDC/ECC schemes in memory circuits are presented to demonstrate the application of the proposed method.
1674451
A defect/error-tolerant nanosystem architecture for DSP
Emerging technologies such as silicon NanoWires (NW) and Carbon NanoTubes (CNT) have shown great potential for building the next generation of computing systems in the nano ranges. However, the excessive number of defects originating from bottom-up fabrication (such as a self-assembly process) poses a pressing challenge for achieving scalable system integration. This article proposes a new nanosystem architecture that employs nanowire crossbars for Digital Signal Processing (DSP) applications. Distributed arithmetic is utilized such that complex signal processing computation can be mapped into regular memory operations, thus making this architecture well suited for implementation by nanowire crossbars. Furthermore, the inherent features of DSP-type computation provide new insights to remedy errors (as logic/computational manifestation of defects). A new defect/error-tolerant technique that exploits algorithmic error compensation is proposed; at system level different trade-offs between correctness in output and performance are established while retaining low overhead in its implementation. As an instance of its application, the proposed approach has been utilized to a generic DSP nanosystem performing frequency-selective filtering. Simulation results show that the proposed nanoDSP introduces only a minor performance degradation under high defect rates and at a range of operational conditions. The proposed technique also features good scalability and viability for various DSP applications.
17864197
Low-complexity adaptive step size constrained constant modulus SG algorithms for adaptive beamforming
In this paper, we propose two low-complexity adaptive step size mechanisms to enhance the performance of stochastic gradient (SG) algorithms for adaptive beamforming. The beamformer is designed according to the constrained constant modulus (CCM) criterion and the proposed mechanisms are employed in the SG algorithm for implementation. A complexity comparison is provided to show their advantages over existing methods, and a sufficient condition for the convergence of the mean weight vector is established. Theoretical expressions of the excess mean-squared error (EMSE), in both the steady-state and tracking cases, are derived based on the energy conservation approach. The effects of multiple access interference (MAI) and additive noise are considered. Simulation experiments are presented for both the stationary and non-stationary scenarios, illustrating that the proposed algorithms achieve superior performance compared with existing methods, and verifying the accuracy of the analyses.
16013630
Runtime Performance of Parallel Array Assignment: An Empirical Study
Generating code for the array assignment statement of High Performance Fortran (HPF) in the presence of block-cyclic distributions of data arrays is considered difficult, and several algorithms have been published to solve this problem. We present a comprehensive study of the run-time performance of the code these algorithms generate. We classify these algorithms into several families, identify several issues of interest in the generated code, and present experimental performance data for the various algorithms. We demonstrate that the code generated for block-cyclic distributions runs almost as efficiently as that generated for block or cyclic distributions.
7727851
Facial Features Location by Analytic Boosted Cascade Detector
We describe a novel technique called Analytic Boosted Cascade Detector (ABCD) to automatically locate features on the human face. ABCD extends the original Boosted Cascade Detector (BCD) in three ways: (i) a probabilistic model is included to connect the classifier responses with the facial features; (ii) a features location method based on the probabilistic model is formulated; (iii) a selection criterion for face candidates is presented. The new technique melts face detection and facial features location into a unified process. It outperforms Average Positions (AVG) and Boosted Classifiers + best response (BestHit). It also shows great speed superior to the methods based on nonlinear optimization, e.g. AAM and SOS.