10504759
Architecture and Implementation of the Front-End Electronics of the Time Projection Chambers in the T2K Experiment
The tracker of the near detector in the T2K neutrino oscillation experiment comprises three time projection chambers based on micro-pattern gaseous detectors. A new readout system is being developed to amplify, condition and acquire in real time the data produced by the 124.000 detector channels. The cornerstone of the system is a 72-channel application specific integrated circuit which is based on a switched capacitor array. Using analog memories combined with deferred digitization enables reducing the initial burstiness of traffic from 50 Tbps to 400 Gbps in a practical manner and with a very low power budget. Modern field programmable gate arrays coupled to commercial digital memories are the next elements in the chain. Multi-gigabit optical links provide 140 Gbps of aggregate bandwidth to carry data outside of the magnet surrounding the detector to concentrator cards that pack data and provide the interface to commercial PCs via a standard Gigabit Ethernet network. We describe the requirements and constraints for this application and justify our technical choices. We detail the design and the performance of several key elements and show the deployment of the front-end electronics on the first time projection chamber where the final tests before installation on-site are being conducted.
82263624
A read-out buffer prototype for ATLAS high level triggers
Read-out buffers are critical components in the dataflow chain of the ATLAS Trigger/DAQ system. At up to 75 kHz, after each level-1 trigger accept signal, these devices receive and store digitized data from groups of front-end electronic channels. Several read-out buffers are grouped to form a read-out buffer complex that acts as a data server for the high level trigger selection algorithms and for the final data collection system. This paper describes a functional prototype of a read-out buffer based on a custom made PCI mezzanine card that is designed to accept input data at up to 160 MB/s, to store up to 8 MB of data and to distribute data chunks at the desired request rate. We describe the hardware of the card that is based on an Intel 1960 processor and CPLDs. We present the integration of several of these cards in a read-out buffer complex. We measure various performance figures and we discuss to which extent these can fulfil ATLAS needs.
53769716
On the integration of high performance ATM-based event builders
A first demonstrator has shown encouraging results for the use of Asynchronous Transfer Mode (ATM) switching networks in the implementation of high performance parallel event builders. Our present goal is to show that the integration of event builders, including the implementation of the source and destination functions and the bandwidth adaptation to the switching network, can be realized with commercially available products and that good performance can be achieved. We shall review some critical issues, present results from performance measurements and analyse the overheads.
195869396
Results from an ATM-based event builder demonstrator
ATM switching fabrics are good candidates to implement high performance parallel event builders for the future data acquisition systems of the LHC experiments. We are studying their feasibility through simulations and implementation of event builder demonstrators. The impact of the event builder characteristic traffic pattern on the switch has been studied and methods to avoid congestion in the switch have been proposed. Event building algorithms and data acquisition protocols have been developed. Measurements made with a demonstrator and comparisons with simulation studies are presented. The scalability of the measurements is discussed.
55013324
Micromegas detector developments for Dark Matter directional detection with MIMAC
The aim of the MIMAC project is to detect non-baryonic Dark Matter with a directional TPC using a high precision Micromegas readout plane. We will describe in detail the recent developments done with bulk Micromegas detectors as well as the characterisation measurements performed in an Argon(95%)-Isobutane(5%) mixture. Track measurements with alpha particles will be shown.
118645473
The topological second-level trigger of the H.E.S.S. phase 2 telescope
H.E.S.S is an array of atmospheric Cherenkov telescopes dedicated to GeV-TeV γ-ray astronomy. The original array has been in operation since the beginning of 2004. It is composed of four 12-meter diameter telescopes. The installation of a fifth 28-meter diameter telescope is being completed. This telescope will operate both in stereoscopic mode and in monoscopic mode i.e. without a coincident detection on the smaller telescopes. A second-level trigger system is needed to supress spurious triggers of the 28-meter telescope when operated in monoscopic mode. This paper gives the motivation and principle of the second-level trigger. The principle of operation is illustrated by an example algorithm. The hardware implementation of the second level trigger system of H.E.S.S. phase 2 is described and its expected performances are then evaluated.
109862390
Test system for the production of the Atlas Tile Calorimeter front-end electronics
Abstract The Atlas hadronic Tile Calorimeter front-end electronics is fully included in the so-called “super-drawers”. The 256 super-drawers needed for the entire calorimeter are assembled and extensively tested in Clermont-Ferrand before being sent to CERN to be inserted in the calorimeter modules. A mobile system has been developed to perform a complete test of the super-drawers during their insertion.
119605019
H1 FORWARD PROTON SPECTROMETER UPGRADE WITH SILICON PIXELS DETECTORS
Abstract The H1 experiment is already equipped with a four roman pots Forward Proton Spectrometer (FPS), using scintillating fibers. The H1 CPPM group has made a proposal to upgrade the FPS by adding silicon pixels detectors in the 90 m roman pot.
121719013
Electrical characteristics of silicon pixel detectors
Prototype sensors for the ATLAS silicon pixel detector have been electrically characterized. The current and voltage characteristics, charge-collection efficiencies, and resolutions have been examined. Devices were fabricated on oxygenated and standard detector-grade silicon wafers. Results from prototypes which examine p-stop and standard and moderated p-spray isolation are presented for a variety of geometrical options. Some of the comparisons relate unirradiated sensors with those that have received fluences relevant to LHC operation.