1462661
Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers
Presented in this paper is a low-power technique, denoted as MIMO-AEC, to reduce energy dissipation in multi-input-multi-output (MIMO) signal processing systems. The proposed technique extends a previously proposed adaptive error-cancellation (AEC) technique to MIMO systems by employing an algorithm transformation denoted as MIMO-DECOR. The purpose of MIMO-DECOR is to reduce complexity by exploiting correlations inherent in MIMO systems, thereby improving the effectiveness of AEC. We employ the MIMO-AEC in the design of a low-power Gigabit Ethernet 1000Base-T device. Simulation results demonstrate 44.3% - 25.2% overhead reduction due to MIMO-DECOR and 69.1% - 64.2% energy savings over conventional implementations with no loss in algorithmic performance.
7481401
Noise-tolerant dynamic circuit design
Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energy efficiency of VLSI systems in the deep submicron era. To address this problem, a new noise-tolerant dynamic circuit technique is presented. In addition, the average noise threshold energy (ANTE) and the energy normalized ANTE metrics are proposed for quantifying the noise immunity and energy efficiency, respectively, of circuit techniques. Simulation results in 0.35 micron CMOS for NAND gate designs indicate that the proposed technique improves the ANTE and energy normalized ANTE by 2.54X and 2.25X over the conventional domino circuit. The improvement in energy normalized ANTE is 1.22X higher than the existing noise-tolerance techniques. A full adder design based on the proposed technique improves the ANTE and energy normalized ANTE by 3.7X and 1.95X over the conventional dynamic circuit. In comparison, the static circuit improves ANTE by 2.2X but degrades the energy normalized ANTE by 11%. In addition, the proposed technique has a smaller area overhead (69%) as compared to the static circuit whose area overhead is 98%.
16050541
Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise
In this paper, we present an algorithm for computing the bounds on energy-efficiency of digital very large scale integration (VLSI) systems in the presence of deep submicron noise. The proposed algorithm is based on a soft-decision channel model of noisy VLSI systems and employs information-theoretic arguments. Bounds on energy-efficiency are computed for multimodule systems, static gates, dynamic circuits and noise-tolerant dynamic circuits in 0.25-/spl mu/m CMOS technology. As the complexity of the proposed algorithm grows linearly with the size of the system, it is suitable for computing the bounds on energy-efficiency for complex VLSI systems. A key result presented is that noise-tolerant dynamic circuits offer the best trade off between energy-efficiency and noise-immunity when compared to static and domino circuits. Furthermore, employing a 16-bit noise-tolerant Manchester adder in a CDMA receiver, we demonstrate a 31.2%-51.4% energy reduction over conventional systems when operating in the presence of noise. In addition, we compute the lower bounds on energy dissipation for this CDMA receiver and show that these lower bounds are 2.8/spl times/ below the actual energy consumed, and that noise-tolerance reduces the gap between the lower bounds and actual energy dissipation by a factor of 1.9/spl times/.
16336079
Low-power MIMO signal processing
In this paper, we present a new adaptive error-cancellation (AEC) technique, denoted as multi-input-multi-output (MIMO)-AEC, for the design of low-power MIMO signal processing systems. The MIMO-AEC technique builds on the previously proposed AEC technique by employing an algorithm transformation denoted as MIMO decorrelating (MIMO-DECOR) transform. MIMO-DECOR reduces complexity by exploiting correlations inherent in MIMO systems, thereby improving the energy efficiency of AEC. The proposed MIMO-AEC enables energy minimization of MIMO systems by correcting transient/soft errors that arise in very large scale integration signal processing implementations due to inherent process nonidealities and/or aggressive low-power design styles, such as voltage overscaling. We employ the MIMO-AEC in the design of a low-power Gigabit Ethernet 1000Base-T device. Simulation results indicate 69.1%-64.2% energy savings over optimally voltage-scaled present-day systems with no loss in algorithmic performance.
6708583
Reducing error accumulation effect in multithreaded memory systems
Chip multithreading is exposed to dual challenges of increasing chip complexity and design variations. It is important to develop effective reliability-enhancing schemes to ensure robust computing. In this paper, we propose the immediate write-back and self-recovery schemes to reduce error accumulation effect in multithreaded memory systems. These schemes are built upon the previously proposed dynamic multithreading redundancy technique for improving reliability in multithreaded architectures. The idea of DMR is to exploit self-generated hardware redundancy due to inter-thread variations inherent in multithreaded architectures. Simulation results demonstrate that the proposed solutions improve error-control performance with minimal hardware overheads. The proposed immediate write-back and self-recovery schemes also feature good scalability for future process generations
36695959
Selective Ensemble Algorithms of Support Vector Machines Based on Constraint Projection
This paper proposes two novel ensemble algorithms for training support vector machines based on constraint projection technique and selective ensemble strategy. Firstly, projective matrices are determined upon randomly selected must-link and cannot-link constraint sets, with which original training samples are transformed into different representation spaces to train a group of base classifiers. Then, two selective ensemble techniques are used to learn the best weighting vector for combining them, namely genetic optimization and minimizing deviation errors respectively. Experiments on UCI datasets show that both proposed algorithms improve the generalization performance of support vector machines significantly, which are much better than classical ensemble algorithms, such as Bagging, Boosting, feature Bagging and LoBag.
14688887
Data Compression Algorithm Based on Hierarchical Cluster Model for Sensor Networks
A new distributed algorithm of data compression based on hierarchical cluster model for sensor networks is proposed, in which, the whole sensor network is mapped into a kind of hierarchical clusters model firstly, and then different wavelet transform models are used to commit data compression in inner and super clusters respectively. Theoretical analyses and simulation results show that, the above new methods have good performance of approximation, and can compress data and reduce the amount of data efficiently.
14894173
Gingko: correlating causal paths in distributed systems
Many large-scale systems are distributed systems of multiple communicating components. Finding causal paths of message traces between components throughout these systems is important to uncover runtime behaviors and identify the root cause of failures, but this "art" often hides in the heads of developers or domain experts. Our goal is to design tools and algorithms to help developers record this art into logs and help the modestly-skilled users and system administrators master it to make better use and management of distributed systems. In this paper, we present a methodology that automatically builds the causal paths of message traces by 1) an agreement with programmers on the style and content of logs produced by operational distributed systems they develop and 2) a correlation algorithm to build message causal paths with the clues from these logs. To validate this mechanism, we have implemented Gingko, a prototype providing a tool chain for users to gain better comprehensions of distributed systems and to debug them efficiently when errors happen.
8890864
Improving Error Tolerance for Multithreaded Register Files
Chip multithreaded computing is exposed to the dual challenges of increasing system complexity and error sensitivity. It is critical to develop effective solutions that achieve better error tolerance without inducing performance degradation. In this paper, we propose a new error-tolerant memory design based on a unique computing phenomenon referred to as the dynamic multithreading redundancy (DMR). The proposed technique exploits the interplay between the concurrent threads for runtime error control. We also present two DMR enhancements, immediate write-back and self-recovery, to address the error accumulation effect. A multithreaded register file was implemented to demonstrate the proposed DMR technique. Simulation results on the SPEC CPU2000 benchmarks demonstrate significant overhead reduction in performance and energy efficiency related to error recovery. In addition, the proposed technique features good scalability with respect to the instruction-level and thread-level parallelism for next-generation processor design, where the soft error problem is expected to get worse due to technology scaling and architecture-affecting trends.