12932631
Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05)
Chip multiprocessor architectures are becoming increasingly attractive as an option to provide high instruction throughput while keeping power and complexity under control. Such architectures have also been shown to have scalability and productivity advantages. Multi-core processors are fast becoming mainstream.
27580015
Register Multimapping: A technique for reducing register bank conflicts in processors with large register files
In this paper, we investigate Register Multimapping as a technique to reduce register bank conflicts for processors with large register files, but relatively slow clock speeds. Register multimapping involves mapping an architectural register to multiple physical registers belonging to different banks. Reads can proceed using any of the physical registers, thereby minimizing read bank conflicts. Write conflicts can be minimized by allowing delayed allocation of physical registers [5]. Our experiments show that register multimapping can result in performance improvements up to 15% (10% on average) over baseline processors that are port-constrained. Improvements are up to 13% (5.5% on average) over port-constrained processors that support delayed allocation of registers.
44489135
Software Energy Optimization of Real Time Preemptive Tasks by Minimizing Cache-Related Preemption Costs
An attempt has been made to optimize the software energy of real time preemptive tasks by minimizing the cache related preemption costs which are primarily incurred due to the inter-task interference in the cache. We have presented an algorithm that outputs an "optimum" task layout which reduces the overall inter-task interference in cache and thus reduces the preemption costs of each task of a given task set. We have compared the result of our estimated layout with that of the random layout generated for benchmark examples for demonstrating the performance of our algorithm.
214800957
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class of interconnect architectures. It shows that the design choices for the interconnect have significant effect on the rest of the chip, potentially consuming a significant fraction of the real estate and power budget. This research shows that designs that treat interconnect as an entity that can be independently architected and optimized would not arrive at the best multi-core design. Several examples are presented showing the need for careful co-design. For instance, increasing interconnect bandwidth requires area that then constrains the number of cores or cache sizes, and does not necessarily increase performance. Also, shared level-2 caches become significantly less attractive when the overhead of the resulting crossbar is accounted for. A hierarchical bus structure is examined which negates some of the performance costs of the assumed base-line architecture.
7410518
Reducing peak power with a table-driven adaptive processor core
The increasing power dissipation of current processors and processor cores constrains design options, increases packaging and cooling costs, increases power delivery costs, and decreases reliability. Much research has been focused on decreasing average power dissipation, which most directly addresses cooling costs and reliability. However, much less has been done to decrease peak power, which most directly impacts the processor design, packaging, and power delivery. This research proposes a new architecture which provides a significant decrease in peak power with limited performance loss. It does this through the use of a highly adaptive processor. Many components of the processor can be configured at different levels, but because they are centrally controlled, the architecture can guarantee that they are never all configured maximally at the same time. This paper describes this adaptive processor and explores mechanisms for transitioning between allowed configurations to maximize performance within a peak power constraint. Such an architecture can cut peak power by 25% with less than 5% performance loss; among other advantages, this frees 5.3% of total core area used for decoupling capacitors.
7623585
Low-Overhead, High-Speed Multi-core Barrier Synchronization
Whereas efficient barrier implementations were once a concern only in high-performance computing, recent trends in core integration make the topic relevant even for general-purpose CMPs. While the nature of CMP applications requires low-latency, the cost of low-latency barrier implementations using hardware-based techniques can be prohibitive for CMPs, where die area represents opportunities for throughput and yield. Similarly, whereas traditional multiprocessor barrier implementations were developed primarily for dedicated environments, scheduling and multi-programming on CMPs require more adaptable barrier implementations. 
 
In this paper, we present and evaluate three barrier implementations that are hybrids of software and dedicated hardware barriers and are specifically tailored for CMPs. The implementations leverage the unique characteristics of CMPs and provide low latency comparable to that of dedicated hardware networks at a fraction of the cost. The implementations also support adaptability, enabling efficient multi-programming and dynamic remapping of the barrier network.
472328
Registration of highly-oblique and zoomed in aerial video to reference imagery
We present methods for estimating precise geo-coordinates of objects observed in highly oblique video from an airborne camera in real time. High precision is achieved by registering observed video frames in real time to rendered views of the scene using stored reference imagery. The reference imagery includes previously collected satellite images and terrain maps that have been precisely aligned to geo-coordinates. We present methods that work for both nadir and highly oblique video imagery and under a variety of conditions where any one frame may not have enough information for accurate geo-registration.
65135986
Model dependent inference of three-dimensional information from a sequence of two-dimensional images
In order to autonomously navigate through a complex environment, a mobile robot requires sensory feedback. This feedback will typically include the 3D motion and location of the robot and the 3D structure and motion of obstacles and other environmental features. The general problem considered in this thesis is how this 3D information may be obtained from a sequence of images generated by a camera mounted on a mobile robot. 
The first set of algorithms developed in this thesis are for robust determination of the 3D pose of the mobile robot from a matched set of model and image landmark features. Least-squares techniques for point and line tokens, which minimize both rotation and translation simultaneously are developed and shown to be far superior to the earlier techniques which solved for rotation first and then translation. However, least-squares techniques fail catastrophically when outliers (or gross errors) are present in the match data. Outliers arise frequently due to incorrect correspondences or gross errors in the 3D model. Robust techniques for pose determination are developed to handle data contaminated by fewer than 50.0% outliers. 
To make the model based approach widely applicable, it is necessary to be able to automatically build the landmark models. The approach adopted in this thesis is one of model extension and refinement. A partial model of the environment is assumed to exist and this model is extended over a sequence of frames. As will be shown in the experiments, the prior knowledge of the small partial model greatly enhances the robustness of the 3D structure computations. The initial 3D model may have errors and these too are refined over the sequence of frames. 
Finally, the sensitivity of pose determination and model extension to incorrect estimates of camera parameters is analyzed. It is shown that for small field of view systems, offsets in the image center do not significantly affect the location of the camera and the location of new 3D points in a world coordinate system. Errors in the focal length significantly affect only the component of translation along the optical axis in the pose computation.
10404965
Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?
There has been ongoing debate regarding the use of voltage overscaling along with error resilience techniques for ultra low power operation of scaled CMOS logic. The issue is whether to build enough design margin into future electronic systems so that errors do not impact the Quality of Service of the end application or to allow errors to occur and correct them using error tolerance mechanisms. Specific signal processing algorithms have been shown to be inherently tolerant to errors. However, large general purpose processors experience virtually zero errors under supply voltage scaling up to a certain scaling level and then exhibit “massive errors” or “complete breakdown”. The problem is made worse by the fact that low power design methodologies force devices to be sized in such a way as to make a large number of circuit paths “critical”. Under all of the above constraints, what is the best way to build low power systems of the future using deeply scaled CMOS technologies? Is the use of voltage overscaling along with error resilience techniques realistic? Can we allow errors to occur and compensate for them with high confidence? Under what conditions will design guardbanding be absolutely necessary? If we do let errors occur periodically, will customers buy the associated products and is there a marketplace for such error-resilient ICs?
377847
A Sampling Algorithm for Tracking Multiple Objects
The recently proposed CONDENSATION algorithm and its variants enable the estimation of arbitrary multi-modal posterior distributions that potentially represent multiple tracked objects. However, the specific state representation adopted in the earlier work does not explicitly supports counting, addition, deletion and occlusion of objects. Furthermore, the representation may increasingly bias the posterior density estimates towards objects with dominant likelihood as the estimation progresses over many frames. In this paper, a novel formulation and an associated CONDENSATION-like sampling algorithm that explicitly support counting, addition and deletion of objects are proposed. We represent all objects in an image as an object configuration. The a posteriori distribution of all possible configurations are explored and maintained using sampling techniques. The dynamics of configurations allow addition and deletion of objects and handle occlusion. An efficient hierarchical algorithm is also proposed to approximate the sampling process in high dimensional space. Promising comparative results on both synthetic and real data are demonstrated.
26545951
Placement of scattering bars in binary and attenuated phase shift mask for damascene trench patterning
Abstract Scattering bars have been very effective technique to increase the common lithography process window for patterns with design rules 0.18 μm and below. This paper studies the placement of scattering bars in binary and attenuated phase shift mask in damascene trench patterning. Different partial coherence values are used to compare the scattering bar effect in binary and 8% attenuated phase shift mask. At low partial coherence ( σ ) the trench size has been found more sensitive to scattering bar parameters than at high σ . Scattering bar separation is found more effective than size to affect the trench critical dimension (CD). At low partial coherence a deep valley or ‘V’ shaped CD trend is found in scattering bar separation versus CD curve. CD dip is more using APSM as compared to binary mask. The process latitude is poor at valley as compared to top. Also, 3 sigma CD variation and range is higher at valley as compared to other separations of the scattering bars.