1199842
Secure Dataspace with Access Policies
Inspired by rule-based access control models, this paper proposes a universal policy model and an access protection framework to secure dataspace. The key components and processes for this framework, policy organization, policy indexing and two resource searching strategies with access decision-making, are illustrated and experimented to harmonize the contradiction between security and efficiency.
2307602
A Multi-Dimensional K-Anonymity Model for Hierarchical Data
For improving the usability of the anonymous result, it is important to comply with the hierarchical structure when generalizing quasi-identifying attributes with hierarchical characteristics. We propose an unrestricted multi-dimensional anonymization model which combines global recoding and local recoding methods. The bottom-up anonymization algorithm with the minimal coverage subgraph constraint and the anonymization metric are proposed. The experiment results justify the effectiveness and scalability of this model.
10940298
An Extensible Data Model with Security Support for Dataspace Management
Based on the iDM concept, this paper proposes an extensible data model with an 8-tuple representation, which can not only describe more complex data sources by extending the Group Component, but also contain rule-based security elements, which consist of Access Component and Authorization Component. Data model is detailed and two corresponding examples are analyzed to verify our approach.
11153805
Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems
Doubling the number of processing cores on a single processor chip with each technology generation has become conventional wisdom. While future manycore processors promise to offer much increased computational throughput under a given power envelope, sharing critical on-chip resources, such as caches and core- to-core interconnects, poses challenges to guaranteeing predictable performance to an application program. This paper focuses on the problem of sharing on-chip caching capacity among multiple programs scheduled together, especially at the L2 cache level. Specifically, two design aspects of a large shared L2 cache are considered: (1) non-uniform cache access latency and (2) cache contention. We observe that both the aspects have to do with where, among many cache slices, a cache block is mapped to, and present an OS-based approach to managing the on-chip L2 cache memory by carefully mapping data to a cache at the page granularity. We show that a reasonable extension to the OS memory management subsystem and simple architectural support enable enforcing high-level policies to achieve application performance isolation and improve program performance predictability thereof.
60552525
Simulation model of the LS-DRMTA adaptive algorithm for multiple antenna system for DS-CDMA
We present the development of a simulation model and for a conceptual DS-CDMA system and simulation baseband models for the least-square despread respread multitarget array (LS-DRMTA) algorithm with two, four and six antenna elements in the Matlab/Simulink environment. The models are used to compare the performance of single and multiple adaptive antenna systems in an AWGN channel. The simulation models show the clear advantage of multiple antenna systems and represent a first step towards their implementation on an FPGA platform.
2578172
A flexible data to L2 cache mapping approach for future multicore processors
This paper proposes and studies a distributed L2 cache management approach through page-level data to cache slice mapping in a future processor chip comprising many cores. L2 cache management is a crucial multicore processor design aspect to overcome non-uniform cache access latency for high program performance and to reduce on-chip network traffic and related power consumption. Unlike previously studied "pure" hardware-based private and shared cache designs, the proposed OS-microarchitecture approach allows mimicking a wide spectrum of L2 caching policies without complex hardware support. Moreover, processors and cache slices can be isolated from each other without hardware modifications, resulting in improved chip reliability characteristics. We discuss the key design issues and implementation strategies of the proposed approach, and present an experimental result showing the promise of it.
1971798
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation
This paper presents and studies a distributed L2 cache management approach through OS-level page allocation for future many-core processors. L2 cache management is a crucial multicore processor design aspect to overcome non-uniform cache access latency for good program performance and to reduce on-chip network traffic and related power consumption. Unlike previously studied hardware-based private and shared cache designs implementing a "fixed" caching policy, the proposed OS-micro architecture approach is flexible; it can easily implement a wide spectrum of L2 caching policies without complex hardware support. Furthermore, our approach can provide differentiated execution environment to running programs by dynamically controlling data placement and cache sharing degrees. We discuss key design issues of the proposed approach and present preliminary experimental results showing the promise of our approach
41633714
Electrical and compositional properties of TaSi2 films
Tantalum silicide (TaSi2) thin films were sputter deposited on p- and n-type silicon substrates using ultrapure TaSi2 targets. The TaSi2/Si samples were annealed in nitrogen or forming gas or oxygen containing steam at temperatures in the range of 400–900°C. The sheet resistances of TaSi2/Si were measured by four-point probe before and after anneal. The structure of these films was investigated using x-ray diffraction (XRD) methods. It has been found that the sheet resistance decreases with the increase in annealing temperature and also with the increase in film thickness. X-ray diffraction patterns show changes in the morphological structure of the films. Oxidation characteristics of the film have been investigated in the temperature range of 400–900°C in oxygen containing steam ambient. The oxidation time ranged from 0.5 to 1.5 h. No oxide formation of the tantalum silicide films was observed in this investigation. This has been attributed to the high purity of TaSi2 sputter targets used in the preparation of the films.