30216304
Pipelined memory controllers for DSP applications handling unpredictable data accesses
Multimedia applications are often characterized by a large number of data accesses with regular and periodic access patterns. In these cases, optimized pipelined memory access controllers can be generated improving the pipeline access mode to RAM. We focus on the design and the implementation of memory sequencers that can be automatically generated from a behavioral synthesis tool and which can efficiently handle predictable address patterns as well as unpredictable ones (dynamic address computations) in a pipeline way.
11449422
Functional level power analysis: an efficient approach for modeling the power consumption of complex processors
A high-level consumption estimation methodology and its associated tool, SoftExplorer, are presented. The estimation methodology uses a functional modeling of the processor combined with a parametric model to allow the designer to estimate the power consumption when the embedded software is executed on the target. SoftExplorer uses as input the assembly code generated by the compiler; its efficiency is compared to SimplePower's approach. Results for different processors (TI C62, C67, C55, and ARM7) and for several DSP applications provide an average error less than 5%.
5563691
Synchronization processor synthesis for latency insensitive systems
In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carloni et al. (2001). Our contribution consists in IP encapsulation into a new wrapper model whose speed and area are optimized and synthetizability guaranteed. The main benefit of our approach is to preserve the local IP performance when encapsulating them and reduce SoC silicon area.
34309839
Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems
The increasingly demanding requirements of multimedia applications have led to the definition of complex image and video coding standards such as JPEG2000 and MPEG4. Implementation of image or video encoders or decoders on mobile device requires high integration densities together with ability for "real-time" (on-the-fly) data processing. Today, the electronic system design community is mainly concerned with defining efficient System-on-a-Chip (SoC) design methodologies in order to benefit from the high integration capabilities of current application-specific integrated circuit and field-programmable gate array technologies on the one hand, and manage the increasing algorithmic complexity of applications on the other hand. Intellectual property (IP) reuse is considered as the key to speed up the system design and verification flow and make it more reliable.In this context, we have introduced a novel methodology for VLSI implementation of computation-intensive algorithms targeting digital signal processing applications. Our methodology combines IP reuse and high-level synthesis (HLS) and introduces the notion of "Behavioral IP". This approach aims at leveraging IP re-usability through functional and architectural flexibility based on: (1) modeling a component's behavior at a high abstraction level and (2) benefiting from HLS tools for architectural exploration and hardware generation.In this paper, we illustrate our methodology in the case of a 2-D discrete wavelet transform IP core for JPEG2000 image compression. We describe the successive views of the component throughout the design flow, from the application level down to the architectural level. We also provide synthesis results showing the variety of dedicated architectures that can be generated depending on user-defined functional-level, system-level and architectural-level requirements. We compare the performance and re-usability of the set of obtained architectures versus hand-crafted RTL specifications.
15834659
Architectural Synthesis with Interconnection Cost Control
Architectural synthesis tools map algorithms to architectures under various constraints and quickly provide estimations of area and performance. However, these tools do not take the interconnection cost into account whereas it becomes predominant with the technology decrease and the application complexity increase. A way to control costly interconnections during the architectural process is presented in this paper.
15462003
How to transform an architectural synthesis tool for low power VLSI designs
High level synthesis (HLS) for low power VLSI design is a complex optimization problem due to the area/time/power interdependence. As few low power design tools are available, a new approach providing a modular low power synthesis method is proposed. Although based for the moment on a generic architectural synthesis tool Gaut, the use of different "commercial" tools is possible. The Gaut-w HLS tool is constituted of low power modules: high level power dissipation estimation, assignment, module selection (operators and supply voltage), optimization criteria and operators library. As illustration, power saving factors on DWT algorithms are presented.
638940
On the data consumption benefits of accepting increased uncertainty
In the context of learning paradigms of identification in the limit, we address the question: why is uncertainty sometimes desirable? We use mind change bounds on the output hypotheses as a measure of uncertainty, and interpret 'desirable' as reduction in data memorization, also defined in terms of mind change bounds. The resulting model is closely related to iterative learning with bounded mind change complexity, but the dual use of mind change bounds - for hypotheses and for data - is a key distinctive feature of our approach. We show that situations exists where the more mind changes the learner is willing to accept, the lesser the amount of data it needs to remember in order to converge to the correct hypothesis. We also investigate relationships between our model and learning from good examples, set-driven, monotonic and strong-monotonic learners, as well as class-comprising versus class-preserving learnability.
43024012
Absolute Versus Probabilistic Classification in a Logical Setting
Given a set $\mathcal{W}$of logical structures, or possible worlds, a set $\mathcal{D}$of logical formulas, or possible data, and a logical formula ϕ, we consider the classification problem of determining in the limit and almost always correctly whether a possible world $\mathcal{M}$satisfies ϕ, from a complete enumeration of the possible data that are true in $\mathcal{M}$. One interpretation of almost always correctly is that the classification might be wrong on a set of possible worlds of measure 0, w.r.t. some natural probability distribution over the set of possible worlds. Another interpretation is that the classifier is only required to classify a set $\mathcal{W}'$of possible worlds of measure 1, without having to produce any claim in the limit on the truth of ϕ in the members of the complement of $\mathcal{W}'$in $\mathcal{W}$. We compare these notions with absolute classification of $\mathcal{W}$w.r.t. a formula that is almost always equivalent to ϕ in $\mathcal{W}$, hence investigate whether the set of possible worlds on which the classification is correct is definable. Finally, in the spirit of the kind of computations considered in Logic programming, we address the issue of computing almost correctly in the limit witnesses to leading existentially quantified variables in existential formulas.
37212285
Quantification over names and modalities
35547835
Identifying Clusters from Positive Data
The present work studies clustering from an abstract point of view and investigates its properties in the framework of inductive inference. Any class S considered is given by a numbering A 0,A 1,... of nonempty subsets of ℕ or ℚ k which is also used as a hypothesis space. A clustering task is a finite and nonempty set of indices of pairwise disjoint sets. The class S is said to be clusterable if there is an algorithm which, for every clustering task I, converges in the limit on any text for ∪ i ∈ I A i to a finite set J of indices of pairwise disjoint clusters such that ∪ j ∈ J A j = ∪ i ∈ I A i . A class is called semiclusterable if there is such an algorithm which finds a J with the last condition relaxed to ∪ j ∈ J A j ⊒∪ i ∈ I A i .
1263625
On the Data Consumption Benefits of Accepting Increased Uncertainty