29358668
Symbolic Expression Analysis for Compiled Communication
Compiled communication can benefit the parallel application design and performance in several ways such as analyzing the communication pattern to optimize a configurable network for performance improvement or to visualize the communication requirements to study and improve the application design. In this article we present symbolic expression analysis techniques in a MPI parallel compiler. Symbolic expression analysis allows the identification and representation of the communication pattern and also assists in the determination of communication phases in MPI parallel applications at compile-time. We demonstrate that using compiler analysis based on symbolic expression analysis to determine the communication pattern can provide an accurate visualization of the communication requirements. Using information from the compiler to program a circuit switching interconnect in multiprocessor systems has the potential to achieve more efficient communication with lower cost compared to packet/wormhole switching. For example, we demonstrate that our compiler approach provides an average of 2.6 times improvement in message delay over a threshold-based runtime system for our benchmarks with a maximum improvement of 9.7 times.
7267319
Symbolic expression analysis for compiled communication
Enabling circuit switching in multiprocessor systems has the potential to achieve more efficient communication with lower cost compared to packet/wormhole switching. However, in order to accomplish this efficiently, assistance from the compiler is required to reveal the communication pattern in the parallel application. In this paper we present symbolic expression analysis techniques in a MPI parallel compiler. Symbolic expression analysis allows the identification and representation of the communication pattern and also assists in the determination of communication phases in MPI parallel applications at compile-time. We demonstrate that using the compiler analysis based on symbolic expression analysis to determine the communication pattern and phases provides an average of 2.6 times improvement in message delay over a threshold-based runtime system for our benchmarks with a maximum improvement of 9.7 times.
44740953
Non-Uniform "Fat-Meshes" for Chip Multiprocessors
This paper studies the traffic hot spots of mesh networks in the context of chip multiprocessors. To mitigate these effects, this paper describes a non-uniform fat-mesh extension to mesh networks, which are popular for chip multiprocessors. The fat-mesh is inspired by the fat-tree and dedicates additional links for connections with heavy traffic (e.g. near the center) with fewer links for lighter traffic (e.g. near the periphery). Two fat-mesh schemes are studied based on the traffic requirements of chip multiprocessors using dimensional ordered XY routing and a randomized XY-YX routing algorithms, respectively. Analytical fat-mesh models are constructed by theoretically presenting the expressions for the traffic requirements of personalized all-to-all traffic for both the raw message numbers and their normalized equivalents. We demonstrate how traffic scales for a traditional mesh compared to a non-uniform fat mesh. Simulation results demonstrate that using same number of physical links the non-uniform fat-mesh can achieve better performance than a uniform fat-mesh mesh using both synthetic traffic patterns and splash-2 benchmark traces.
17359946
Optimized Cross-Layer Design for Scalable Video Transmission Over the IEEE 802.11e Networks
A cross-layer design for optimizing 3-D wavelet scalable video transmission over the IEEE 802.11e networks is proposed. A thorough study on the behavior of the IEEE 802.11e protocol is conducted. Based on our findings, all timescales rate control is developed featuring a unique property of soft capacity support for multimedia delivery. The design consists of a macro timescale and a micro timescale rate control schemes residing at the application layer and the network sublayer respectively. The macro rate control uses bandwidth estimation to achieve optimal bit allocation with minimum distortion. The micro rate control employs an adaptive mapping of packets from video classifications to appropriate network priorities which preemptively drops less important video packets to maximize the transmission protection to the important video packets. The performance is investigated by simulations highlighting advantages of our cross-layer design.
52849739
Inverse System Decoupling Control for Induction Motor Based on Neural Network On-Line Learning
The induction motor is a MIMO, nonlinear and high coupling system. The reversibility of the induction motor is testified. Consequently, a pseudo-linear system is completed by constructing a neural network inverse (NNI) system and combining it with the motor system. The inverse can transform the MIMO nonlinear system into two SISO linear subsystems (i.e., rotor speed and flux subsystems). In order to approach the inversion exactly in operation of the motor, the control method online learning based on NNI system is proposed, in which connection value can be amended continuously on-line to make the NN adapt to the changes of environment to strengthen its robustness. Simulation and experiment results have shown that NN can be adjusted in the control process. The good applicability of NN along with the strong stability and robustness of the system can be achieved by using the proposed method.
8620934
Certifying Concurrent Programs Using Transactional Memory
Transactional memory (TM) is a new promising concurrency-control mechanism that can avoid many of the pitfalls of the traditional lock-based techniques. TM systems handle data races between threads automatically so that programmers do not have to reason about the interaction of threads manually. TM provides a programming model that may make the development of multi-threaded programs easier. Much work has been done to explore the various implementation strategies of TM systems and to achieve better performance, but little has been done on how to formally reason about programs using TM and how to make sure that such reasoning is sound. In this paper, we focus on the semantics of transactional memory and present a proof-carrying code (PCC) system for reasoning about programs using TM. We formalize our reasoning with respect to the TM semantics, prove its soundness, and use examples to demonstrate its effectiveness.
1229519
A decision-theoretic approach for designing proactive communication in multi-agent teamwork
Techniques that support effective communication during teamwork processes are of particular importance. Psychological study shows that an effective team often can anticipate information exchange among the team and communicate relevant information proactively. Proactive communication is crucial for understanding and sharing common goals and for cooperative actions. Communication can be valuable if it assists agents with new and timely information; it also has cost because it consumes network resources such as bandwidth. To address these issues, we present a new model that uses information production and need to capture the complex multi-agent communication process and a dynamic decision-theoretic determination of communication strategies. We also introduce a generic utility function and an algorithm, DTPC (Decision-Theoretic Proactive Communication), that focuses on representing information production and need of team members and resolving decision interactions among them for making decisions.
16272826
Analyzing the impact of on-chip network traffic on program phases for CMPs
It is known that the execution of programs exhibits repetitive phases; in other words, the execution of programs can be partitioned into segments of execution, during which the application exhibits unique architectural properties. This property has been used for various optimization goals. In addition, phase information is utilized to reduce the run time of the architectural simulation. Conventionally, an application is examined in an architecture-independent manner (such as the number of times a basic block is executed) to extract information about the phases and then only the representative execution intervals are executed to analyze architectural choices. We claim that such approaches are becoming inadequate in the many-core era as application execution is not dominated by the instructions only, but instead the communication structure of the application is becoming as important as the instruction behavior. Hence, we propose to utilize communication behavior to determine the phases of an application. Our results reveal that the inclusion of the communication information can increase the accuracy of the phase detection significantly. Specifically, for SPLASH2 and MineBench applications, the average (geometric mean) CPI error rate with the instruction-based phase detection is 11.01%, while our phase detection scheme has an average error rate of 3.41% when compared to the simulations that run the applications to completion.