43074800
Research and Implementation of a 32-Bit Asynchronous Multiplier
提出基于宏单元（macrocell）的异步电路设计流程,由于在流程中尽量与现有的同步电路设计EDA工具兼容,降低了技术难度,提高了开发效率.基于该流程实现了0.35μm工艺条件下的32位异步乘法器.经过与相同工艺条件下,具有相同数据通路结构的同步乘法器比较,异步乘法器的性能与同步乘法器相当,而且面积更小、功耗更低.
32146489
Cycle Period Analysis and Optimization of Timed Circuits
In this paper, a method is proposed to analyze the minimum average cycle period of the timed circuits. Timed Petri net is used to model timed circuits. Our method is focus on structural analysis of the Petri net model of the timed circuits, which is another way to reduce the state space of the analyzed model. Then an algorithm is proposed to optimize the performance of timed circuit by asynchronous retiming technique. The algorithm balances the asynchronous pipelines to gain the target cycle period while minimize the area at the same time. Experimental results demonstrate the computational feasibility and effectiveness of both approaches.
11142145
An Optimal Design Method for De-synchronous Circuit Based on Control Graph
De-synchronous is a very useful method to design asynchronous circuit automatically from synchronous description of circuits. This paper introduces an optimal design method based on Control Graph which is an abstract model of the de-synchronous circuit. The main purpose of this optimal design method is to reduce the extra overhead in the area of the de-synchronous circuit. The optimization algorithm takes the performance evaluation function based on the Control Graph of the de-synchronous circuit as its heuristic function. The performance evaluation function presented in this paper is a linear programming problem. In the end of this paper, the optimal method is applied to a set of benchmark circuits. The number of the local controllers in these circuits is markedly reduced by 54%, and the number of C-elements that is required to construct the handshake circuitry between local controllers is also reduced by 76.3%. So the entire area of the circuit is sharply reduced. Because this design method is directed by the performance evaluation function of the circuit, there is no penalty in performance of the de-synchronous circuit.
22959134
The Design of Asynchronous Microprocessor Based on Optimized NCL_X Design-Flow
NCL X circuit is a very efficient way to implement the QDI circuit, which can get all the advantages of the asynchronous circuit, especially the average performance. But the NCL_X circuits suffer from its huge area overhead. To solve this problem, a method for optimizing the complete detection network in the NCL_X circuit has been introduced in this paper. Using this method can dramatically reduced the area of the NCL_X circuit, according to the experimental result, the area of the NCL_X circuit may be reduced more than 60%. We also use this optimized method to implement an asynchronous microprocessor pipeline (APC). Compared to the synchronous implementation, this NCL_X implementation can achieve higher performance because the NCL_X circuit can get the average performance.
16447326
An Approximate Method for Performance Evaluation of Asynchronous Pipeline Rings
Performance evaluation of asynchronous circuits is one of the most difficult parts in asynchronous circuit research. This Paper presents an approximate method by queuing network modeling for performance evaluation of asynchronous pipeline rings. The asynchronous pipeline rings are modeled by closed queuing networks with transfer blocking. An efficient approximation method is used to analyze the performance metrics, such as response time and throughput. These performance metrics can be used to derive the cycle time and latency of the asynchronous pipeline rings. Compared with theoretic results, the algorithm presented in this paper is efficient for performance evaluation of asynchronous pipeline rings.
17076624
Performance Bound Analysis and Retiming of Timed Circuits
Timed asynchronous circuits are efficient in performance and power consumption. Traditional performance analysis method can not analyze timed circuits efficiently. In this paper, we model timed circuits using timed Petri net and digraph. We studied the mean cycle time of timed Petri net model. The upper bound and lower bound of mean cycle time were given. Then we proposed an algorithm for timed circuits retiming. The algorithm can efficiently distribute buffers along communication channels of timed circuits to gain maximal performance and minimal area. These algorithms were applied to phased logic circuitspsila design and optimization.
30275519
Traffic Intelligent Optimization and Local Traffic-Flow Control Inside Shanghai-EXPO-Area
368510
A Performance Model for Domino Mail Server
Using performance model to analyze the Internet service is prevailing. However, the research of the performance model for mail server retrains in the immature status. In this paper, based on the queue theory, we propose a performance model for Domino mail server. The verification and analysis of the model are also presented. The experimental results show that this model characterizes the behavior of Domino mail server well and prove that it is useful for the qualitative performance measurement of Domino mail server.
3648509
A Dynamic Quota-Based Peer Selection Strategy in BitTorrent
BitTorrent employs a static quota-based peer selection strategy to fixedly allocate upload quotas for the tit-for-tat (TFT) choke algorithm and optimistic unchoke (OU) algorithm, which would incur a paradox of supply and demand between upload peers and request peers, where many request peers stay in the starvation state while many upload quotas stay in the idleness state. We propose a dynamic quota-based peer selection strategy, where request peers are classified by the principle of investment return and according to dynamic changed numbers of different request peers an upload peer adaptively allocates upload quotas for the TFT and OU algorithms. Simulation experiment shows that our dynamic quota allocation scheme can eliminate the paradox of supply and demand, increase the resource utility ratio of upload peers, and decrease the file download time, at the cost of uploading more a few file blocks for each upload peer.
37911723
The Research of Complex System Modeling Based on Fractal Conception
45515067
Evaluation Mode Research on Particle Swarm Optimization Algorithm