15807941
Human Discovery and Machine Learning
This article studies machine learning paradigms from the point of view of human cognition. Indeed, conceptions in both machine learning and human learning evolved from a passive to an active conception of learning. Our objective is to provide an interaction protocol suited to both humans and machines to enable assisting human discoveries by learning machines. We identify the limitations of common machine learning paradigms in the context of scientific discovery, and we propose an extension inspired by game theory and multiagent systems. We present individual cognitive aspects of this protocol as well as social considerations, and we relate encouraging results concerning a game implementing it.
39139980
On Sufficient Conditions for Learnability of Logic Programs from Positive Data
Shinohara, Arimura, and Krishna Rao have shown learnability in the limit of minimal models of classes of logic programs from positive only data. In most cases, these results involve logic programs in which the "size" of the head yields a bound on the size of the body literals. However, when local variables are present, such a bound on body literal size cannot directly be ensured. The above authors achieve such a restriction using technical notions like mode and linear inequalities. The present paper develops a conceptually clean framework where the behavior of local variables is controlled by nonlocal ones. It is shown that for certain classes of logic programs, learnablity from positive data is equivalent to limiting identification of bounds for the number of clauses and the number of local variables. This reduces the learning problem finding two integers. This cleaner framework generalizes all the known results and establishes learnability of new classes.
37212285
Quantification over names and modalities
7592429
On the Convergence of Incremental Knowledge Base Construction
Ripple Down Rules is a practical methodology to build knowledge-based systems, which has proved successful in a wide range of commercial applications. However, little work has been done on its theoretical foundations. In this paper, we formalise the key features of the method. We present the process of building a correct knowledge base as a discovery scenario involving a user, an expert, and a system. The user provides data for classification. The expert helps the system to build its knowledge base incrementally, using the output of the latter in response to the last datum provided by the user. In case the system’s output is not satisfactory, the expert guides the system to improve its future performance while not affecting its ability to properly classify past data. We examine under which conditions the sequence of knowledge bases constructed by the system eventually converges to a knowledge base that faithfully represents the target classification function. Our results are in accordance with the observed behaviour of real-life systems.
38643151
Learning from Each Other
Since its inception, the field of machine learning has seen the advent of several learning paradigms, designed to frame the issues central to the learning activity, provide effective learning methods, and investigate the power and limitations inherent to the process of successful learning. In this article, we propose a formalization that underlies the key concepts of many such paradigms and discuss their relevance to scientific discovery, with the aim of assessing what scientists can expect from machines designed to assist them in their quest for the discovery of valid laws. We illustrate the formalization on several variations of a card game, and highlight the differences that paradigms impose on learners, as well as the assumptions they make on the nature of the learning process. We then use the formalization to describe a multi-agent interaction protocol, that has been inspired by these paradigms and that has been validated recently on some groups of agents. Finally, we propose extensions to this protocol.
2402100
Input-Dependence in Function-Learning
In the standard literature on inductive inference, a learner sees as input the course of values of the function to be learned. In the present work, it is investigated how reasonable this choice is and how sensitive the model is with respect to variations like the overgraph or undergraph of the function. Several implications and separations are shown and for the basic notions, a complete picture is obtained. Furthermore, relations to oracles, additional information and teams are explored.
16853689
A complete methodology for memory optimization in DSP applications
In the digital and signal processing (DSP) applications, the main issue in system performance is strongly related to the memory subsystem characteristics and data positions. In such applications, exhaustive data analysis is often highly complex and time consuming whereas the actual bottlenecks are essentially due to the few largest data objects (arrays). Therefore, to ensure a good trade-off between analysis time and efficiency, we focus the optimization on these objects also called 'structures'. Our approach relies on a new graph formalism called 'data control flow graph' which analyzes an algorithm (written in C), and brings out data structure dependencies while retaining execution order constraints. Manipulating this graph allows to determine an optimized memory mapping according to a fixed memory hierarchy and thus to reduce bus activity, resulting in improved both execution time and energy consumption. This method is also planned to be extended to memory optimization by sizing both the memory hierarchy and the architecture.
18045473
Low power design of an acoustic echo canceller Gmdf/spl alpha/ algorithm on dedicated VLSI architectures
The acoustic echo cancellation with adaptive filters is a computationally intensive problem that needs real time cost effective solutions for embedded systems. Low power optimized signal processing architectures are likely to provide such solutions in the future. In this paper, we present different real-time optimized architectures of the popular Gmdf/spl alpha/ algorithm, obtained by an HLS CAD tool providing trade-off-between area and power dissipation.
34573352
A Vision System on Chip for Industrial Control
This paper describes the building of an original vision system on chip. Our smart sensor performs motion detection and pattern recognition with only one single line of pixels. The maximum cross-correlation number is processed by the processors network. A peculiar methodology was defined to tackle the sensor’s processing part design. Relying on our architectural synthesis tool GAUT, it leads to an optimal matching between the application specifications, the sensor’s architecture and the processor’s. The elementary processor’s architecture is detailed. Its CMOS VLSI implementation is sketched, as well as the sensor’s analog part and the light to byte conversion. The circuit’s final structure and floorplan are outlined. Its performances are exhibited.
15088597
G729 Voice Decoder Design
Embedded digital signal processing (DSP) systems are usually associated with real time constraints and/or high data rates such that fully software implementations are often not satisfactory. In that case, mixed hardware/software implementations are to be investigated. This paper presents the design of a HW/SW G.729 voice decoder dedicated to embedded systems. The decoder has been built around, on the one hand a reconfigurable digital circuit (FPGA) to achieve the so called IP hardware part—the autocorrelation computation—using a linear systolic array, and on the other hand a digital signal processor (DSP) for the remainder of the algorithm. Apart such an implementation is typically driven by the use of reusable component (IP) it is of great interest for new G729-based applications such as Voice over IP (VoIP) for example. It results in an overall reduction of the execution time per frame. Another interesting point is the design of a parameterizable autocorrelation block which can be useful for a wide range of applications such as GSM 13 Kbit/s, APC 9.6 Kbit/s and G723 6.3 Kbit/s and 5.3 Kbit/s. In the G729 context and using a V50 Virtex FPGA, the execution time of this function is 10 times faster than a TMS320C6201 DSP implementation.
20266767
High-level synthesis in latency insensitive system methodology
This paper presents our contribution in terms of synchronization processor to a SoC design methodology based on the theory of the latency insensitive systems (US). This methodology 1) promotes pre-developed IPs intensive reuse, 2) segments inter-IPs interconnects with relay stations to break critical paths and 3) brings robustness to data stream irregularities to IPs by encapsulation into a synchronization wrapper. Our contribution consists of IP encapsulation into a new wrapper model containing a synchronization processor, which speed and area are optimized and synthesizability guaranteed. The main benefit of our approach is to preserve the local IP performances when encapsulating them. This approach is part of the RNRT ALIPTA project which targets design automation of intensive digital signal processing systems with GAUT, a high-level synthesis tool.