2171095
Heterogeneous chip multiprocessors
Heterogeneous (or asymmetric) chip multiprocessors present unique opportunities for improving system throughput, reducing processor power, and mitigating Amdahl's law. On-chip heterogeneity allow the processor to better match execution resources to each application's needs and to address a much wider spectrum of system loads - from low to high thread parallelism - with high efficiency.
7623585
Low-Overhead, High-Speed Multi-core Barrier Synchronization
Whereas efficient barrier implementations were once a concern only in high-performance computing, recent trends in core integration make the topic relevant even for general-purpose CMPs. While the nature of CMP applications requires low-latency, the cost of low-latency barrier implementations using hardware-based techniques can be prohibitive for CMPs, where die area represents opportunities for throughput and yield. Similarly, whereas traditional multiprocessor barrier implementations were developed primarily for dedicated environments, scheduling and multi-programming on CMPs require more adaptable barrier implementations. 
 
In this paper, we present and evaluate three barrier implementations that are hybrids of software and dedicated hardware barriers and are specifically tailored for CMPs. The implementations leverage the unique characteristics of CMPs and provide low latency comparable to that of dedicated hardware networks at a fraction of the cost. The implementations also support adaptability, enabling efficient multi-programming and dynamic remapping of the barrier network.
9616848
Core architecture optimization for heterogeneous chip multiprocessors
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to design such a processor; instead, they started with an assumed combination of pre-existing cores. This work assumes the flexibility to design a multi-core architecture from the ground up and seeks to address the following question: what should be the characteristics of the cores for a heterogeneous multi-processor for the highest area or power efficiency? The study is done for varying degrees of thread-level parallelism and for different area and power budgets. The most efficient chip multiprocessors are shown to be heterogeneous, with each core customized to a different subset of application characteristics — no single core is necessarily well suited to all applications. The performance ordering of cores on such processors is different for different applications; there is only a partial ordering among cores in terms of resources and complexity. This methodology produces performance gains as high as 40%. The performance improvements come with the added cost of customization.
7664388
Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures
This paper proposes a single-ISA heterogeneousmulti-core architecture as a mechanism to reduce processorpower dissipation. It assumes a single chip containing a diverseset of cores that target different performance levels and consumedifferent levels of power. During an application’s execution,system software dynamically chooses the most appropriate core tomeet specific performance and power requirements. It describesan example architecture with five cores of varying performanceand complexity. Initial results demonstrate a five-fold reductionin energy at a cost of only 25% performance.
27580015
Register Multimapping: A technique for reducing register bank conflicts in processors with large register files
In this paper, we investigate Register Multimapping as a technique to reduce register bank conflicts for processors with large register files, but relatively slow clock speeds. Register multimapping involves mapping an architectural register to multiple physical registers belonging to different banks. Reads can proceed using any of the physical registers, thereby minimizing read bank conflicts. Write conflicts can be minimized by allowing delayed allocation of physical registers [5]. Our experiments show that register multimapping can result in performance improvements up to 15% (10% on average) over baseline processors that are port-constrained. Improvements are up to 13% (5.5% on average) over port-constrained processors that support delayed allocation of registers.
7410518
Reducing peak power with a table-driven adaptive processor core
The increasing power dissipation of current processors and processor cores constrains design options, increases packaging and cooling costs, increases power delivery costs, and decreases reliability. Much research has been focused on decreasing average power dissipation, which most directly addresses cooling costs and reliability. However, much less has been done to decrease peak power, which most directly impacts the processor design, packaging, and power delivery. This research proposes a new architecture which provides a significant decrease in peak power with limited performance loss. It does this through the use of a highly adaptive processor. Many components of the processor can be configured at different levels, but because they are centrally controlled, the architecture can guarantee that they are never all configured maximally at the same time. This paper describes this adaptive processor and explores mechanisms for transitioning between allowed configurations to maximize performance within a peak power constraint. Such an architecture can cut peak power by 25% with less than 5% performance loss; among other advantages, this frees 5.3% of total core area used for decoupling capacitors.
62017650
VideoTrek: A vision system for a tag-along robot
We present a system that combines multiple visual navigation techniques to achieve GPS-denied, non-line-of-sight SLAM capability for heterogeneous platforms. Our approach builds on several layers of vision algorithms, including sparse frame-to-frame structure from motion (visual odometry), a Kalman filter for fusion with inertial measurement unit (IMU) data and a distributed visual landmark matching capability with geometric consistency verification. We apply these techniques to implement a tag-along robot, where a human operator leads the way and a robot autonomously follows. We show results for a real-time implementation of such a system with real field constraints on CPU power and network resources.
15134584
Replication of Biomolecular Techniques for Implementing Intelligent Systems
In this paper, it has been shown that computational jobs, such as encoding of input data and AND, OR operation, can work on the computers (by using computer databases and algorithms for the purpose of speeding up and enhancing biological research). By combining more complex functions, more complex molecular programs for gene analysis can be constructed. It is expected an in vivo (i.e. inside cellular life forms) computer will be realized from this technology, which detects the cell state through gene expression patterns, and controls the cell conditions with output RNA (ribose nucleic acid). The replication of biomolecular techniques based upon DNA (deoxyribose nucleic acid) architecture has been proposed. It may provide a powerful tool for both research and clinical applications. To develop functional supra-molecular systems, where sequence-programmable and evolvable molecular systems have been constructed as cell-free chemical systems using biomolecules such as DNA and proteins based on the integration of electronics, computer science, IT (information technology), mathematical and statistical tools. This paper is organised into four parts: part I describes the functioning and encoding processes of DNA computers, which are implemented using a traveling salesman problem (as in artificial intelligent systems) and single shortest path routing approach (as in computer networks) using object-oriented approach of software development, part II presents database integration with DNA using client-server technologies of Web design, part III discusses the implications of DNA for computer and network security, and part IV investigates and shows the results with the use of above mentioned approaches.
27240142
Two optimal peer selection problems
Many peer computers today participate in peer-to-peer file sharing applications in which the computers contribute storage and bandwidth resources. Of course, applications can only harness the resource pool if peers make available their surplus resources to them. It is widely documented, however, that the P2P systems are havens for "free riders": a significant fraction of users do not contribute any resources, and a minute fraction of users contribute the majority of the resources. Clearly, to improve the performance of existing P2P file sharing systems, and to enable new classes of P2P applications, a compelling incentive system needs to be put in place.
8733679
Stochastic Fluid Theory for P2P Streaming Systems
We develop a simple stochastic fluid model that seeks to expose the fundamental characteristics and limitations of P2P streaming systems. This model accounts for many of the essential features of a P2P streaming system, including the peers' realtime demand for content, peer churn (peers joining and leaving), peers with heterogeneous upload capacity, limited infrastructure capacity, and peer buffering and playback delay. The model is tractable, providing closed-form expressions which can be used to shed insight on the fundamental behavior of P2P streaming systems. The model shows that performance is largely determined by a critical value. When the system is of moderate-to-large size, if a certain ratio of traffic loads exceeds the critical value, the system performs well; otherwise, the system performs poorly. Furthermore, large systems have better performance than small systems since they are more resilient to bandwidth fluctuations caused by peer churn. Finally, buffering can dramatically improve performance in the critical region, for both small and large systems. In particular, buffering can bring more improvement than can additional infrastructure bandwidth.
1111313
Resist pattern peeling assessment in DUV chemically amplified resist
As device size shrinks resist line peeling becomes more challenging. In this paper we studied the resist pattern peeling based on resist processing parameters and type of bottom antireflective coating (BARC), for patterning trench structures with different duty ratios, in copper and low k dual damascene process. To minimize resist poisoning in dual damascene process, acetal-based resist was used. Significant improvement in via poisoning was observed with this chemistry as compared to environmentally stable chemically amplified resist chemistry but at the cost of pattern peeling. In order to solve pattern peeling problem we tried to analyze key factors such as compatibility with BARC, post-exposure bake, BARC curing, adhesion and their effects. Pitch dependency on pattern peeling margin is observed.