6708583
Reducing error accumulation effect in multithreaded memory systems
Chip multithreading is exposed to dual challenges of increasing chip complexity and design variations. It is important to develop effective reliability-enhancing schemes to ensure robust computing. In this paper, we propose the immediate write-back and self-recovery schemes to reduce error accumulation effect in multithreaded memory systems. These schemes are built upon the previously proposed dynamic multithreading redundancy technique for improving reliability in multithreaded architectures. The idea of DMR is to exploit self-generated hardware redundancy due to inter-thread variations inherent in multithreaded architectures. Simulation results demonstrate that the proposed solutions improve error-control performance with minimal hardware overheads. The proposed immediate write-back and self-recovery schemes also feature good scalability for future process generations
33314662
Design of error-tolerant cache memory for multithreaded computing
With the trend towards nanometer billion-transistor integration, reliable computing becomes increasingly challenged by semiconductor process variations and low-level physical effects. This is particularly a problem for on-chip memory circuits. In this paper, we propose an error-tolerant memory design technique based on a unique phenomenon referred to as the inter-thread transient redundancy in multithreaded computing. A new memory microarchitecture is developed that exploits dynamic mapping strategies for compensation of unpredictable performance variations and soft errors. Trace driven simulations on the SPEC CPU2000 benchmarks show the advantages of the proposed technique for improving error tolerance in multithreaded microprocessors.
2723209
An energy-efficient skew compensation technique for high-speed skew-sensitive signaling
Presented in this paper is an energy-efficient skew compensation technique referred to as the resistance-based distributed clock deskew (RDSK) technique. In comparison with the existing clock deskew techniques, the proposed RDSK technique achieves significant power reduction while maintaining effective in skew management. Furthermore, the proposed RDSK provides a better scalability for future technology scaling. Simulation results of an on-chip interconnect communication system with distributed receivers designed in a 0.10 /spl mu/m CMOS process demonstrate 20%-51% power reduction over the existing techniques. The proposed RDSK is an essential element of our adaptive timing framework where circuit performance can be adjusted adaptively in response to time-varying disturbances and uncertainties.
16738561
Defect-tolerant digital filtering with unreliable molecular electronics
Molecular electronics such as silicon nanowires (NW) and carbon nanotubes (CNT) are considered to be the future computational substrates due to their ultra-high density and superior energy efficiency. However, excessive defects from bottom-up self-assembly fabrication pose a major technological barrier to achieving reliable computing at the molecular scale. Existing solutions targeting absolute correctness introduce high cost and complexity in post-fabrication testing and defect diagnosis. In this paper, we propose a new approach exploiting algorithm level enhancements for defect-insensitive signal processing. By deliberately allowing molecular-scale integrated systems to bear defects, the proposed design framework achieves reliable signal processing while significantly reduces the cost of defect tolerance.
8890864
Improving Error Tolerance for Multithreaded Register Files
Chip multithreaded computing is exposed to the dual challenges of increasing system complexity and error sensitivity. It is critical to develop effective solutions that achieve better error tolerance without inducing performance degradation. In this paper, we propose a new error-tolerant memory design based on a unique computing phenomenon referred to as the dynamic multithreading redundancy (DMR). The proposed technique exploits the interplay between the concurrent threads for runtime error control. We also present two DMR enhancements, immediate write-back and self-recovery, to address the error accumulation effect. A multithreaded register file was implemented to demonstrate the proposed DMR technique. Simulation results on the SPEC CPU2000 benchmarks demonstrate significant overhead reduction in performance and energy efficiency related to error recovery. In addition, the proposed technique features good scalability with respect to the instruction-level and thread-level parallelism for next-generation processor design, where the soft error problem is expected to get worse due to technology scaling and architecture-affecting trends.
18869116
Thread-Associative Memory for Multicore and Multithreaded Computing
Presented in this paper is the thread-associative memory microarchitecture for multicore and multithreaded processor design. Memory contention among concurrent threads in chip multithreaded processing has become a limiting factor for performance improvement. The proposed thread-associative memory addresses this challenge by incorporating thread-specific information explicitly into on-chip memory hardware. The proposed technique can be utilized at different levels of memory hierarchy. Furthermore, it is not just a technique for performance enhancement but also a solution for energy efficiency. Trace-driven simulations on a 32KB L1 data cache demonstrate 36.6% maximum performance improvement and up to 15.1% total energy reduction, with 20.3% dynamic energy reduction and 9.9% leakage energy reduction
46410326
A Platform Implementation for Real Time Image Processing
The technologies for image processing are improved evidently since the popularity of modern IA products in the last decade. In order to satisfy the needs on high quality images, higher contrast, higher saturation and higher resolution become the main goals of the researches. This article focuses on how to implement a platform for real time image processing to provide a realistic environment for developing techniques on enhancing image contrast dynamically in real time. A new method for improving the contrast quality of images can be verified by feeding analog images of NTSC television to this platform after digitalized, then perform the functions of enhancing image contrast by FPGA to provide the enhanced result of image contrast. It's different from the simulations made by software that proposed by the past researches, this article proposes a practical hardware real time processing foundation that can be used as a valuable reference of real time image processing.
8984253
Recognizing Chinese Proper Nouns with Transformation-Based Learning and Ontology
This paper proposes an approach based on the Ontology and transformation-based error-driven learning (TBL) to recognize Chinese proper nouns. Firstly, our approach redefines the label set and tags Chinese words according to the usage of proper nouns and their context, and then it extracts Characteristic Information (CI) of the proper noun from the text and merges them based on the Ontology. Secondly, it tags the training corpus following the new definition of Multi-dimension Attribute Points (MAP), and then extracts rules using the TBL approach. Finally, it recognizes proper nouns by utilizing the rule set and Ontology. The experimental results in our open test show that the precision is 92.5% and the recall is 86.3%.
31999867
A Novel Classifier with the Immune-Training Based Wavelet Neural Network
After analyzing the classification and training ability of a wavelet neural network (WNN), a novel WNN learning scheme integrating immunity based evolutionary algorithm (IDEA) is proposed, in which, IDEA is an evolutionary algorithm with an embedded immune mechanism. When WNN is used as a classifier, the process of seeking the least mean-square error (LMS) of an optimal problem is equivalent to that of finding the wavelet feature with maximal separability, namely, maximizing its separable division. On the other hand, with the capability of robust learning of its evolutionary process, IDEA is able to eliminate local degenerative phenomenon due to blindfold behaviors of original operators in the existing evolutionary algorithms. In the case of the twin-spiral problem, experimental simulation shows the feasibility of WNN training with the IDEA based learning algorithm.
18692029
A CCI-Feedback-Aided Scheduling Technique for MU-MIMO
Imperfect channel state information (CSI) at the transmitter is one of the major challenges that the downlink multiuser multiple-input-multiple-output (MU-MIMO) technology faces in real applications. It will lead to increased co- channel interference (CCI) among users and deteriorate the capacity of MU-MIMO seriously, especially at high signal-to- noise-ratios (SNRs). In this paper, we propose an advanced MU-MIMO scheduling technique to improve the capacity of MU-MIMO in the case of imperfect CSI at the transmitter (CSIT). The rational behind the proposed scheme is the observation that the CCI level increases with the number of users simultaneously supported in MU-MIMO transmission. Thus, decreasing the number of simultaneous users can reduce CCI and sometimes even increase the sum capacity. Motivated by this observation, we design a CCI-feedback-aided scheduling technique, which adaptively adjusts the number of simultaneous users based on the CCI measurement at the user side. Simulation results have shown that considerable capacity gain can be achieved by the proposed scheduling technique at the cost of only one bit additional feedback per user and marginal complexity increase at both the transmitter and user side.
16336079
Low-power MIMO signal processing
In this paper, we present a new adaptive error-cancellation (AEC) technique, denoted as multi-input-multi-output (MIMO)-AEC, for the design of low-power MIMO signal processing systems. The MIMO-AEC technique builds on the previously proposed AEC technique by employing an algorithm transformation denoted as MIMO decorrelating (MIMO-DECOR) transform. MIMO-DECOR reduces complexity by exploiting correlations inherent in MIMO systems, thereby improving the energy efficiency of AEC. The proposed MIMO-AEC enables energy minimization of MIMO systems by correcting transient/soft errors that arise in very large scale integration signal processing implementations due to inherent process nonidealities and/or aggressive low-power design styles, such as voltage overscaling. We employ the MIMO-AEC in the design of a low-power Gigabit Ethernet 1000Base-T device. Simulation results indicate 69.1%-64.2% energy savings over optimally voltage-scaled present-day systems with no loss in algorithmic performance.