752417
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
This paper proposes and evaluates single-ISA heterogeneousmulti-core architectures as a mechanism to reduceprocessor power dissipation. Our design incorporatesheterogeneous cores representing different points inthe power/performance design space; during an application'sexecution, system software dynamically chooses themost appropriate core to meet specific performance andpower requirements.Our evaluation of this architecture shows significant energybenefits. For an objective function that optimizes forenergy efficiency with a tight performance threshold, for 14SPEC benchmarks, our results indicate a 39% average energyreduction while only sacrificing 3% in performance.An objective function that optimizes for energy-delay withlooser performance bounds achieves, on average, nearly afactor of three improvement in energy-delay product whilesacrificing only 22% in performance. Energy savings aresubstantially more than chip-wide voltage/frequency scaling.
27580015
Register Multimapping: A technique for reducing register bank conflicts in processors with large register files
In this paper, we investigate Register Multimapping as a technique to reduce register bank conflicts for processors with large register files, but relatively slow clock speeds. Register multimapping involves mapping an architectural register to multiple physical registers belonging to different banks. Reads can proceed using any of the physical registers, thereby minimizing read bank conflicts. Write conflicts can be minimized by allowing delayed allocation of physical registers [5]. Our experiments show that register multimapping can result in performance improvements up to 15% (10% on average) over baseline processors that are port-constrained. Improvements are up to 13% (5.5% on average) over port-constrained processors that support delayed allocation of registers.
214800957
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class of interconnect architectures. It shows that the design choices for the interconnect have significant effect on the rest of the chip, potentially consuming a significant fraction of the real estate and power budget. This research shows that designs that treat interconnect as an entity that can be independently architected and optimized would not arrive at the best multi-core design. Several examples are presented showing the need for careful co-design. For instance, increasing interconnect bandwidth requires area that then constrains the number of cores or cache sizes, and does not necessarily increase performance. Also, shared level-2 caches become significantly less attractive when the overhead of the resulting crossbar is accounted for. A hierarchical bus structure is examined which negates some of the performance costs of the assumed base-line architecture.
7623585
Low-Overhead, High-Speed Multi-core Barrier Synchronization
Whereas efficient barrier implementations were once a concern only in high-performance computing, recent trends in core integration make the topic relevant even for general-purpose CMPs. While the nature of CMP applications requires low-latency, the cost of low-latency barrier implementations using hardware-based techniques can be prohibitive for CMPs, where die area represents opportunities for throughput and yield. Similarly, whereas traditional multiprocessor barrier implementations were developed primarily for dedicated environments, scheduling and multi-programming on CMPs require more adaptable barrier implementations. 
 
In this paper, we present and evaluate three barrier implementations that are hybrids of software and dedicated hardware barriers and are specifically tailored for CMPs. The implementations leverage the unique characteristics of CMPs and provide low latency comparable to that of dedicated hardware networks at a fraction of the cost. The implementations also support adaptability, enabling efficient multi-programming and dynamic remapping of the barrier network.
7410518
Reducing peak power with a table-driven adaptive processor core
The increasing power dissipation of current processors and processor cores constrains design options, increases packaging and cooling costs, increases power delivery costs, and decreases reliability. Much research has been focused on decreasing average power dissipation, which most directly addresses cooling costs and reliability. However, much less has been done to decrease peak power, which most directly impacts the processor design, packaging, and power delivery. This research proposes a new architecture which provides a significant decrease in peak power with limited performance loss. It does this through the use of a highly adaptive processor. Many components of the processor can be configured at different levels, but because they are centrally controlled, the architecture can guarantee that they are never all configured maximally at the same time. This paper describes this adaptive processor and explores mechanisms for transitioning between allowed configurations to maximize performance within a peak power constraint. Such an architecture can cut peak power by 25% with less than 5% performance loss; among other advantages, this frees 5.3% of total core area used for decoupling capacitors.
7664388
Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures
This paper proposes a single-ISA heterogeneousmulti-core architecture as a mechanism to reduce processorpower dissipation. It assumes a single chip containing a diverseset of cores that target different performance levels and consumedifferent levels of power. During an application’s execution,system software dynamically chooses the most appropriate core tomeet specific performance and power requirements. It describesan example architecture with five cores of varying performanceand complexity. Initial results demonstrate a five-fold reductionin energy at a cost of only 25% performance.
8733679
Stochastic Fluid Theory for P2P Streaming Systems
We develop a simple stochastic fluid model that seeks to expose the fundamental characteristics and limitations of P2P streaming systems. This model accounts for many of the essential features of a P2P streaming system, including the peers' realtime demand for content, peer churn (peers joining and leaving), peers with heterogeneous upload capacity, limited infrastructure capacity, and peer buffering and playback delay. The model is tractable, providing closed-form expressions which can be used to shed insight on the fundamental behavior of P2P streaming systems. The model shows that performance is largely determined by a critical value. When the system is of moderate-to-large size, if a certain ratio of traffic loads exceeds the critical value, the system performs well; otherwise, the system performs poorly. Furthermore, large systems have better performance than small systems since they are more resilient to bandwidth fluctuations caused by peer churn. Finally, buffering can dramatically improve performance in the critical region, for both small and large systems. In particular, buffering can bring more improvement than can additional infrastructure bandwidth.
135903312
Determination of the hardness and elastic modulus of low- k thin films and their barrier layer for microelectronic applications
This paper presents the experimental results and analysis of the elastic modulus and hardness for several thicknesses of dielectric films, namely low-k films and their barrier layer, using the nano-indentation technique. The elastic modulus and hardness of the films were determined by "normal" nano-indentation analysis. The data were then analyzed by rearranging the load-displacement data (P-h) obtained by nano-indentation in such a way that the applied load divided by the corresponding displacement (P/h) versus the displacement (h) was obtained, which effectively differentiates the film-only mechanical properties from those of the substrate. The low-k film, carbon-doped silicon oxide (SiOC), was prepared using a parallel plate PECVD system. The dielectric constant of the low-k film was measured to be 3.09, which is much lower than that of commonly used dielectric materials such as SiO2 (k ∼ 3.9). The hardness and elastic modulus of the film were measured to be approximately 2.23 and 13.98 GPa, respectively. To enhance the mechanical properties of the low-k thin film, a low-k barrier layer (SiCN:H) with better mechanical properties was deposited between the low-k film and the substrate or on top of the low-k film. It was found that the barrier layer improved the mechanical properties of the low-k film and the barrier layer stacked in certain circumstances. The effects of the arrangement of the barrier layer and the low-k film on the mechanical behavior of the bi-layer system were studied in detail.
18669485
A QoS routing protocol for delay-sensitive applications in mobile ad hoc networks
The Ad hoc On Demand Distance Vector (AODV) routing protocol is intended for use by mobile nodes in ad hoc networks. To provide quality of service, extensions can be added to the messages used during route discovery. These extensions specify the service requirements which must be met by nodes rebroadcasting a route request (RREQ) or returning a route reply (RREP) for a destination. In order to provide quality delivery to delay sensitive applications such as voice and video, it is extremely important that mobile ad hoc networks provide quality of service (QoS) support in terms of bandwidth and delay. Most existing routing protocols for mobile ad hoc networks are designed to search for the shortest path with minimum hop count. However, the shortest routes do not always provide the best performance, especially when there are congested nodes along these routes. In this paper we propose an on demand delay based quality of service (QoS) routing protocol (AODV-D) to ensure that delay does not exceed a maximum value for mobile ad hoc networks. This protocol will take into consideration MAC layer channel contention information and number of packets in the interface queue in addition to minimum hops. The protocol is implemented and simulated using GlomoSim simulator. Performance comparisons of the proposed AODV-D protocol against AODV, and QS-AODV is presented and shown that the proposed algorithm performs well.
6548026
Automated Mosaics via Topology Inference
The authors present a complete approach for the automated construction of mosaics from images and video using topology inference, local and global alignment, and compositing.
16117863
A Comparative Study of Different Sensors for Smart Car Park Management
Wireless sensor networks offer a very attractive, low cost alternative for traffic monitoring and surveillance in car parking, freeways and intersection in different environmental conditions. In such systems, robust and reliable vehicle detection is a critical step, thus it is important to carefully evaluate the different modes of operations in order to address existing issues. This paper proposes a vision of improvements to wireless sensor car parking network system by presenting valuable comparison data for different sensors using different type of software functions and hardware components. The main goal of this work is to present a simple, automated analysis and comparison of power management, communication efficiency and threshold times using different sensors and a corresponding prediction of the above features. The results show a clear difference in various parameters by using different types of sensors for vehicle detection.