9484645
A 1-V UHF low noise amplifier for ultralow-power applications
This paper is focused on low voltage, ultra low power LNA design at 404 MHz for a wireless transceiver used in a cochlear implant device. The design is implemented in a 0.18mum RF CMOS process. The circuit operated with 1V, reduced power supply voltage. The LNA performance is investigated for different power consumption levels to come up with the best performance at minimum possible power level. The performance target is, having a moderate gain and a moderate noise figure without degrading the linearity too much. The circuit, which will be used in receiver chain, consumes only 500 muW power. It has simulated noise figure of 0.9 dB, input 1-dB compression point of -19.5 dBm, input third order intercept point of -5.01 dBm and small signal gain of 15.85 dB. The design will be used in the MICS transceiver
23478055
1-V ultra-low-power CMOS LC VCO for UHF quadrature signal generation
Design, implementation, and simulation of ultra-low-power LC-VCOs with quadrature signal generation are presented, as well as the analysis and the comparison of several different VCO topologies. The VCO topology having the best performance is then used further for quadrature signal generation. Based on a 0.18mum RF/mixed-signal CMOS process, the VCOs are simulated using 1V supply voltage. It is demonstrated that the N- & P- MOS cross-coupled pair VCO with balance resistors operating at 1.6GHz has a power consumption of 0.1mW with as low as -121 dBc/Hz of phase noise at 1-MHz offset. To generate the quadrature signals at 400MHz, N- & P- MOS pair VCOs at the frequency of 400MHz, 800MHz, 1.6GHz, divide-by-two, and divide-by-four circuits are implemented and compared. It turns out that the frequency dividers degrade the phase noise. Comparison of FOMs shows that VCO at 800MHz followed by a divide-by-two is the best choice for quadrature signal generation at 400 MHz, achieving 177muW for the VCO and 25muW for the divider. The phase noise is -127dBc/Hz at 1-MHz offset
34859568
On Digital Watermarking via Public-Key Cryptosystems
In a gate valve, which has a backseat which is made up only when the normally non-rising operator stem is permitted to rise a short distance, and in order that a smaller-diameter stem may be used than one which is of sufficient area where it passes through the stem packing to cause the internal pressure within the valve cavity to generate sufficient force to overcome the frictional forces resisting stem movement developed by the internal pressure between the gate plates and the seats, so that the stem may rise when it is supposed to, to make the backseat, a system of clearances is provided between the stem nut and the gate plates. A different stop arrangement is shown for limiting rising of the gate, for defining the fully open position of the gate.
36591988
Power-Aware Test Data Compression for Embedded IP Cores
Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, the authors propose in this paper to modify an existing test data compression technique so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded intellectual property (IP) cores. Compared to the initial solution that fill don't-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS'89 and ITC'99 benchmark circuits and on a number of industrial circuits. Results show that up to 20times reduction in test data volume and 95% test power reduction can be obtained simultaneously
2240396
Scheduling High-Level Blocks for Functional Simulation
This paper presents a method for scheduling high-level blocks for functional simulation under the assumptions that circuits may be cyclic (due to element grouping), and that blocks cannot be broken down into simpler elements. The solution presented here may simulate one block many times per clock period. Obtaining a minimal schedule for a cyclic circuit is shown to be NP-complete, and two approximation algorithms are presented, along with empirical data to evaluate their effectiveness.
17770433
A generalized expansion matching based feature extractor
A novel and efficient generalized feature extraction method is presented based on the expansion matching (EXM) method and the Karhunen-Loueve (KL) transform. The EXM method is used to design optimal detectors for different features. The KL representation is used to define an optimal basis for representing these EXM feature detectors with minimum truncation error. Input images are then analyzed with the resulting KL basis set. The KL coefficients obtained from the analysis are used to efficiently reconstruct the response due to any combination of feature detectors. The method is applied to real images and successfully extracts a variety of arc and edge features as well as complex junction features formed by combining two or more arc or line features.
19349376
Automatically Generating Ada95 Codes for Concurrent Objects