62212474
A design flow dedicated to multi-mode architectures for DSP applications
This paper addresses the design of multi-mode architectures for digital signal processing applications. We present a dedicated design flow and its associated high-level synthesis tool, named GAUT. Given a unified description of a set of time-wise mutually exclusive tasks and their associated throughput constraints, a single RTL hardware architecture optimized in area is generated. In order to reduce the register, steering logic (multiplexers) and controller (decoding logic) complexities, we propose a joint-scheduling algorithm which maximizes the similarities between control steps and specific binding approaches for both functional units and storage elements which maximize the similarities between the datapaths. We show through a set of test cases that our approach offers significant area saving relative to the state-of-the-art.
11623202
A memory aware behavioral synthesis tool for real-time VLSI circuits
We introduce a new approach to take into account the memory architecture and the memory mapping in the Behavioral Synthesis of Real-Time VLSI circuits. We formalize the memory mapping as a set of constraints for the thesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a memory mapping file to include those memory straints in our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time. Several experiments are performed to demonstrate the efficiency of our method, and to compare GAUT with an industrial behavioral synthesis tool. We finally show how to explore, with the help of GAUT, a wide range of solutions, and to reach a good tradeoffs between time, power-consumption, and area.
11449422
Functional level power analysis: an efficient approach for modeling the power consumption of complex processors
A high-level consumption estimation methodology and its associated tool, SoftExplorer, are presented. The estimation methodology uses a functional modeling of the processor combined with a parametric model to allow the designer to estimate the power consumption when the embedded software is executed on the target. SoftExplorer uses as input the assembly code generated by the compiler; its efficiency is compared to SimplePower's approach. Results for different processors (TI C62, C67, C55, and ARM7) and for several DSP applications provide an average error less than 5%.
32575594
Synthèse architecturale d'applications temps réel pour technologies submicroniques
La synthese d'architectures est un procede automatise qui facilite l'adequation algorithme architecture par l'exploration de l'espace des solutions architecturales. A partir d'une description comportementale de l'algorithme a integrer, les outils de synthese d'architectures permettent ainsi l'implantation materielle sous contraintes et fournissent rapidement des estimations de surfaces et de performances. Les outils actuels ne prennent cependant pas en compte de maniere efficace le cout des interconnexions internes aux circuits, cout qui devient predominant avec l'evolution conjointe des technologies et de la complexite des applications. Nous proposons une methode qui, a partir d'une analyse des interconnexions des le niveau comportemental et d'une modelisation de leurs parametres de couts, assure le controle des interconnexions tout au long du processus de synthese d'architectures et autorise ainsi une adequation algorithme architecture efficace a un haut niveau d'abstraction.
34309839
Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems
The increasingly demanding requirements of multimedia applications have led to the definition of complex image and video coding standards such as JPEG2000 and MPEG4. Implementation of image or video encoders or decoders on mobile device requires high integration densities together with ability for "real-time" (on-the-fly) data processing. Today, the electronic system design community is mainly concerned with defining efficient System-on-a-Chip (SoC) design methodologies in order to benefit from the high integration capabilities of current application-specific integrated circuit and field-programmable gate array technologies on the one hand, and manage the increasing algorithmic complexity of applications on the other hand. Intellectual property (IP) reuse is considered as the key to speed up the system design and verification flow and make it more reliable.In this context, we have introduced a novel methodology for VLSI implementation of computation-intensive algorithms targeting digital signal processing applications. Our methodology combines IP reuse and high-level synthesis (HLS) and introduces the notion of "Behavioral IP". This approach aims at leveraging IP re-usability through functional and architectural flexibility based on: (1) modeling a component's behavior at a high abstraction level and (2) benefiting from HLS tools for architectural exploration and hardware generation.In this paper, we illustrate our methodology in the case of a 2-D discrete wavelet transform IP core for JPEG2000 image compression. We describe the successive views of the component throughout the design flow, from the application level down to the architectural level. We also provide synthesis results showing the variety of dedicated architectures that can be generated depending on user-defined functional-level, system-level and architectural-level requirements. We compare the performance and re-usability of the set of obtained architectures versus hand-crafted RTL specifications.
16853689
A complete methodology for memory optimization in DSP applications
In the digital and signal processing (DSP) applications, the main issue in system performance is strongly related to the memory subsystem characteristics and data positions. In such applications, exhaustive data analysis is often highly complex and time consuming whereas the actual bottlenecks are essentially due to the few largest data objects (arrays). Therefore, to ensure a good trade-off between analysis time and efficiency, we focus the optimization on these objects also called 'structures'. Our approach relies on a new graph formalism called 'data control flow graph' which analyzes an algorithm (written in C), and brings out data structure dependencies while retaining execution order constraints. Manipulating this graph allows to determine an optimized memory mapping according to a fixed memory hierarchy and thus to reduce bus activity, resulting in improved both execution time and energy consumption. This method is also planned to be extended to memory optimization by sizing both the memory hierarchy and the architecture.
37212285
Quantification over names and modalities
28948159
Autonomous capture of a tumbling satellite
In this paper, we describe a framework for the autonomous capture and servicing of satellites. The work is based on laboratory experiments that illustrate the autonomy and remote-operation aspects. The satellite-capture problem is representative of most on-orbit robotic manipulation tasks where the environment is known and structured, but it is dynamic since the satellite to be captured is in free flight. Bandwidth limitations and communication dropouts dominate the quality of the communication link. The satellite-servicing scenario is implemented on a robotic test-bed in laboratory settings. The communication aspects were validated in transatlantic tests. © 2007 Canadian Space Agency
2402100
Input-Dependence in Function-Learning
In the standard literature on inductive inference, a learner sees as input the course of values of the function to be learned. In the present work, it is investigated how reasonable this choice is and how sensitive the model is with respect to variations like the overgraph or undergraph of the function. Several implications and separations are shown and for the basic notions, a complete picture is obtained. Furthermore, relations to oracles, additional information and teams are explored.
980414
A General Theory of Deduction, Induction, and Learning
Deduction, induction, learning, are various aspects of a more general scientific activity: the discovery of truth. We propose to embed them in a common, logical framework. First, we define a generalized notion of "logical consequence." Alternating compact and "weakly compact" consequences, we stratify the set of generalized logical consequences of a given theory in a hierarchy. Classical first-order logic is a particular case of this framework; the fact that it is all about deduction is due to the compactness theorem, and this is reflected by the collapsing of the corresponding hierarchy to the first level. Classical learning paradigms in the inductive inference literature provide other particular cases. Finite learning corresponds exactly to the first level (or level ?1) of the hierarchy, whereas learning in the limit corresponds to another level (namely ?2). More generally, strong and natural connections exist between our hierarchy of generalized logical consequences, the Borel hierarchy, and the hierarchy which measures the complexity of a formula in terms of alternations of quantifiers. It is hoped that this framework provides the foundation of a unified logic of deduction and induction, and highlights the inductive nature of learning. An essential motivation for our work is to apply the theory presented here to the design of "Inductive Prolog", a system with both deductive and inductive capabilities, based on a natural extension of the resolution principle.
1889407
Sensitivity Analysis and Other Improvements to Tailored Combinatorial Library Design
"Tailoring" combinatorial libraries was developed several years ago as a very general and intuitive method to design diverse compound collections while controlling the profile of other pharmaceutically relevant properties. The candidate substituents were assigned to "categorical bins" according to their properties, and successive steps of D-optimal design were performed to generate diverse substituent sets consistent with required membership quotas from each bin. This serial algorithm was expedient to implement from existing D-optimal design codes, but was order-dependent and did not generally locate the very best possible design. A new "parallel" Fedorov search algorithm has now been implemented that can find the most diverse property-tailored design. An ambiguous mass penalty has been added, whereby most duplicate masses can be eliminated with little loss of library diversity. Sensitivity analysis has also been added to quantitatively explore the diversity trade-offs due to increasing or decreasing each specific kind of bias.