12455452
Single-ISA heterogeneous multi-core architectures for multithreaded workload performance
A single-ISA heterogeneous multi-core architecture is a chip multiprocessor composed of cores of varying size, performance, and complexity. This paper demonstrates that this architecture can provide significantly higher performance in the same area than a conventional chip multiprocessor. It does so by matching the various jobs of a diverse workload to the various cores. This type of architecture covers a spectrum of workloads particularly well, providing high single-thread performance when thread parallelism is low, and high throughput when thread parallelism is high. This paper examines two such architectures in detail, demonstrating dynamic core assignment policies that provide significant performance gains over naive assignment, and even outperform the best static assignment. It examines policies for heterogeneous architectures both with and without multithreading cores. One heterogeneous architecture we examine outperforms the comparable-area homogeneous architecture by up to 63%, and our best core assignment strategy achieves up to 31% speedup over a naive policy.
9616848
Core architecture optimization for heterogeneous chip multiprocessors
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to design such a processor; instead, they started with an assumed combination of pre-existing cores. This work assumes the flexibility to design a multi-core architecture from the ground up and seeks to address the following question: what should be the characteristics of the cores for a heterogeneous multi-processor for the highest area or power efficiency? The study is done for varying degrees of thread-level parallelism and for different area and power budgets. The most efficient chip multiprocessors are shown to be heterogeneous, with each core customized to a different subset of application characteristics — no single core is necessarily well suited to all applications. The performance ordering of cores on such processors is different for different applications; there is only a partial ordering among cores in terms of resources and complexity. This methodology produces performance gains as high as 40%. The performance improvements come with the added cost of customization.
7664388
Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures
This paper proposes a single-ISA heterogeneousmulti-core architecture as a mechanism to reduce processorpower dissipation. It assumes a single chip containing a diverseset of cores that target different performance levels and consumedifferent levels of power. During an application’s execution,system software dynamically chooses the most appropriate core tomeet specific performance and power requirements. It describesan example architecture with five cores of varying performanceand complexity. Initial results demonstrate a five-fold reductionin energy at a cost of only 25% performance.
7410518
Reducing peak power with a table-driven adaptive processor core
The increasing power dissipation of current processors and processor cores constrains design options, increases packaging and cooling costs, increases power delivery costs, and decreases reliability. Much research has been focused on decreasing average power dissipation, which most directly addresses cooling costs and reliability. However, much less has been done to decrease peak power, which most directly impacts the processor design, packaging, and power delivery. This research proposes a new architecture which provides a significant decrease in peak power with limited performance loss. It does this through the use of a highly adaptive processor. Many components of the processor can be configured at different levels, but because they are centrally controlled, the architecture can guarantee that they are never all configured maximally at the same time. This paper describes this adaptive processor and explores mechanisms for transitioning between allowed configurations to maximize performance within a peak power constraint. Such an architecture can cut peak power by 25% with less than 5% performance loss; among other advantages, this frees 5.3% of total core area used for decoupling capacitors.
7623585
Low-Overhead, High-Speed Multi-core Barrier Synchronization
Whereas efficient barrier implementations were once a concern only in high-performance computing, recent trends in core integration make the topic relevant even for general-purpose CMPs. While the nature of CMP applications requires low-latency, the cost of low-latency barrier implementations using hardware-based techniques can be prohibitive for CMPs, where die area represents opportunities for throughput and yield. Similarly, whereas traditional multiprocessor barrier implementations were developed primarily for dedicated environments, scheduling and multi-programming on CMPs require more adaptable barrier implementations. 
 
In this paper, we present and evaluate three barrier implementations that are hybrids of software and dedicated hardware barriers and are specifically tailored for CMPs. The implementations leverage the unique characteristics of CMPs and provide low latency comparable to that of dedicated hardware networks at a fraction of the cost. The implementations also support adaptability, enabling efficient multi-programming and dynamic remapping of the barrier network.
27580015
Register Multimapping: A technique for reducing register bank conflicts in processors with large register files
In this paper, we investigate Register Multimapping as a technique to reduce register bank conflicts for processors with large register files, but relatively slow clock speeds. Register multimapping involves mapping an architectural register to multiple physical registers belonging to different banks. Reads can proceed using any of the physical registers, thereby minimizing read bank conflicts. Write conflicts can be minimized by allowing delayed allocation of physical registers [5]. Our experiments show that register multimapping can result in performance improvements up to 15% (10% on average) over baseline processors that are port-constrained. Improvements are up to 13% (5.5% on average) over port-constrained processors that support delayed allocation of registers.
8038424
Robust Object Matching for Persistent Tracking with Heterogeneous Features
This paper addresses the problem of matching vehicles across multiple sightings under variations in illumination and camera poses. Since multiple observations of a vehicle are separated in large temporal and/or spatial gaps, thus prohibiting the use of standard frame-to-frame data association, we employ features extracted over a sequence during one time interval as a vehicle fingerprint that is used to compute the likelihood that two or more sequence observations are from the same or different vehicles. Furthermore, since our domain is aerial video tracking, in order to deal with poor image quality and large resolution and quality variations, our approach employs robust alignment and match measures for different stages of vehicle matching. Most notably, we employ a heterogeneous collection of features such as lines, points, and regions in an integrated matching framework. Heterogeneous features are shown to be important. Line and point features provide accurate localization and are employed for robust alignment across disparate views. The challenges of change in pose, aspect, and appearances across two disparate observations are handled by combining a novel feature-based quasi-rigid alignment with flexible matching between two or more sequences. However, since lines and points are relatively sparse, they are not adequate to delineate the object and provide a comprehensive matching set that covers the complete object. Region features provide a high degree of coverage and are employed for continuous frames to provide a delineation of the vehicle region for subsequent generation of a match measure. Our approach reliably delineates objects by representing regions as robust blob features and matching multiple regions to multiple regions using earth mover's distance (EMD). Extensive experimentation under a variety of real-world scenarios and over hundreds of thousands of confirmatory identification (CID) trails has demonstrated about 95 percent accuracy in vehicle reacquisition with both visible and infrared (IR) imaging cameras
2765279
PEET: Prototype Embedding and Embedding Transition for Matching Vehicles over Disparate Viewpoints
This paper presents a novel framework, prototype embedding and embedding transition (PEET), for matching objects, especially vehicles, that undergo drastic pose, appearance, and even modality changes. The problem of matching objects seen under drastic variations is reduced to matching embeddings of object appearances instead of matching the object images directly. An object appearance is first embedded in the space of a representative set of model prototypes (prototype embedding (PE)). Objects captured at disparate temporal and spatial sites are embedded in the space of prototypes that are rendered with the pose of the cameras at the respective sites. Low dimensional embedding vectors are subsequently matched. A significant feature of our approach is that no mapping function is needed to compute the distance between embedding vectors extracted from objects viewed from disparate pose and appearance changes, instead, an embedding transition (ET) scheme is utilized to implicitly realize the complex and non-linear mapping with high accuracy. The heterogeneous nature of matching between high-resolution and low-resolution image objects in PEET is discussed, and an unsupervised learning scheme based on the exploitation of the heterogeneous nature is developed to improve the overall matching performance of mixed resolution objects. The proposed approach has been applied to vehicular object classification and query application, and the extensive experimental results demonstrate the efficacy and versatility of the PEET framework.
12111272
Ten-fold Improvement in Visual Odometry Using Landmark Matching
Our goal is to create a visual odometry system for robots and wearable systems such that localization accuracies of centimeters can be obtained for hundreds of meters of distance traveled. Existing systems have achieved approximately a 1% to 5% localization error rate whereas our proposed system achieves close to 0.1% error rate, a ten-fold reduction. Traditional visual odometry systems drift over time as the frame-to-frame errors accumulate. In this paper, we propose to improve visual odometry using visual landmarks in the scene. First, a dynamic local landmark tracking technique is proposed to track a set of local landmarks across image frames and select an optimal set of tracked local landmarks for pose computation. As a result, the error associated with each pose computation is minimized to reduce the drift significantly. Second, a global landmark based drift correction technique is proposed to recognize previously visited locations and use them to correct drift accumulated during motion. At each visited location along the route, a set of distinctive visual landmarks is automatically extracted and inserted into a landmark database dynamically. We integrate the landmark based approach into a navigation system with 2 stereo pairs and a low-cost inertial measurement unit (IMU) for increased robustness. We demonstrate that a real-time visual odometry system using local and global landmarks can precisely locate a user within 1 meter over 1000 meters in unknown indoor/outdoor environments with challenging situations such as climbing stairs, opening doors, moving foreground objects etc..
46163853
Enhancement of adhesion strength of Cu layer with low dielectric constant SiC: H liners in Cu interconnects
Abstract One of the primary candidates for the liner/etch stop layer in damascene process is silicon nitride (Si 3 N 4 ). However, silicon nitride has a high dielectric constant of 7.0. To reduce the effective dielectric constant in Copper (Cu) damascene structure, dielectric SiC:H (prepared by plasma enhanced chemical vapor deposition (PECVD) using trimethylsilane source) as the Cu diffusion barrier was studied. The dielectric constant of SiC:H used is 4.2. A systematic study was made on the properties of liner material and electro-chemically plated (ECP) Cu to enhance the adhesion strength in Cu/low-dielectric constant ( k ) multilevel interconnects. Though the effects of as Si 3 N 4 the liner have been much studied in the past, less is known about the relation between adhesion strength of ECP Cu layer and physical vapor deposited (PVD) Cu seeds, with seed thickness below 1000 A. The annealing of Cu seed layer was carried out at 200 °C in N 2 ambient for 30 min was carried out to study the impact on adhesion strength and the microstructure evolution on the adhesion between ECP Cu and its barrier layer. In the study, our claim that SiC:H barrier/etch stop layer is essential for replacing conventional Si 3 N 4 layer in enhancing adhesion strength and interfacial bonding between Cu/dielectric interconnects.
31836660
A Global Matching Framework for Stereo Computation
This paper presents a new global matching framework f o r stereo computation. In this framework, the second view is first predicted front the reference view using the depth information. A global match measure is then defined as the similarity function between the predicted image and the actual image. Stereo coniputcction is converted into a search problem where the goal is to find the depth rnup that maximizes the global match measure. The major advantage of this framework is that the global visibility constraint is inherently enforced in the computation. This paper explores several key components of this framework including ( I ) three color segmentation based depth representations, (2) an incremental warping algorithm that dramatically reduces the computational complexity, and (3) scene constraints such as the smoothness constraint and the color sinzilarity constraint. Experimental results using different types of depth representations are presented. The quality of the computed depth maps is demonstrated through image-based rendering from new viewpoints.