1111313
Resist pattern peeling assessment in DUV chemically amplified resist
As device size shrinks resist line peeling becomes more challenging. In this paper we studied the resist pattern peeling based on resist processing parameters and type of bottom antireflective coating (BARC), for patterning trench structures with different duty ratios, in copper and low k dual damascene process. To minimize resist poisoning in dual damascene process, acetal-based resist was used. Significant improvement in via poisoning was observed with this chemistry as compared to environmentally stable chemically amplified resist chemistry but at the cost of pattern peeling. In order to solve pattern peeling problem we tried to analyze key factors such as compatibility with BARC, post-exposure bake, BARC curing, adhesion and their effects. Pitch dependency on pattern peeling margin is observed.
26545951
Placement of scattering bars in binary and attenuated phase shift mask for damascene trench patterning
Abstract Scattering bars have been very effective technique to increase the common lithography process window for patterns with design rules 0.18 μm and below. This paper studies the placement of scattering bars in binary and attenuated phase shift mask in damascene trench patterning. Different partial coherence values are used to compare the scattering bar effect in binary and 8% attenuated phase shift mask. At low partial coherence ( σ ) the trench size has been found more sensitive to scattering bar parameters than at high σ . Scattering bar separation is found more effective than size to affect the trench critical dimension (CD). At low partial coherence a deep valley or ‘V’ shaped CD trend is found in scattering bar separation versus CD curve. CD dip is more using APSM as compared to binary mask. The process latitude is poor at valley as compared to top. Also, 3 sigma CD variation and range is higher at valley as compared to other separations of the scattering bars.
16117863
A Comparative Study of Different Sensors for Smart Car Park Management
Wireless sensor networks offer a very attractive, low cost alternative for traffic monitoring and surveillance in car parking, freeways and intersection in different environmental conditions. In such systems, robust and reliable vehicle detection is a critical step, thus it is important to carefully evaluate the different modes of operations in order to address existing issues. This paper proposes a vision of improvements to wireless sensor car parking network system by presenting valuable comparison data for different sensors using different type of software functions and hardware components. The main goal of this work is to present a simple, automated analysis and comparison of power management, communication efficiency and threshold times using different sensors and a corresponding prediction of the above features. The results show a clear difference in various parameters by using different types of sensors for vehicle detection.
7664388
Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures
This paper proposes a single-ISA heterogeneousmulti-core architecture as a mechanism to reduce processorpower dissipation. It assumes a single chip containing a diverseset of cores that target different performance levels and consumedifferent levels of power. During an application’s execution,system software dynamically chooses the most appropriate core tomeet specific performance and power requirements. It describesan example architecture with five cores of varying performanceand complexity. Initial results demonstrate a five-fold reductionin energy at a cost of only 25% performance.
377847
A Sampling Algorithm for Tracking Multiple Objects
The recently proposed CONDENSATION algorithm and its variants enable the estimation of arbitrary multi-modal posterior distributions that potentially represent multiple tracked objects. However, the specific state representation adopted in the earlier work does not explicitly supports counting, addition, deletion and occlusion of objects. Furthermore, the representation may increasingly bias the posterior density estimates towards objects with dominant likelihood as the estimation progresses over many frames. In this paper, a novel formulation and an associated CONDENSATION-like sampling algorithm that explicitly support counting, addition and deletion of objects are proposed. We represent all objects in an image as an object configuration. The a posteriori distribution of all possible configurations are explored and maintained using sampling techniques. The dynamics of configurations allow addition and deletion of objects and handle occlusion. An efficient hierarchical algorithm is also proposed to approximate the sampling process in high dimensional space. Promising comparative results on both synthetic and real data are demonstrated.
10404965
Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?
There has been ongoing debate regarding the use of voltage overscaling along with error resilience techniques for ultra low power operation of scaled CMOS logic. The issue is whether to build enough design margin into future electronic systems so that errors do not impact the Quality of Service of the end application or to allow errors to occur and correct them using error tolerance mechanisms. Specific signal processing algorithms have been shown to be inherently tolerant to errors. However, large general purpose processors experience virtually zero errors under supply voltage scaling up to a certain scaling level and then exhibit “massive errors” or “complete breakdown”. The problem is made worse by the fact that low power design methodologies force devices to be sized in such a way as to make a large number of circuit paths “critical”. Under all of the above constraints, what is the best way to build low power systems of the future using deeply scaled CMOS technologies? Is the use of voltage overscaling along with error resilience techniques realistic? Can we allow errors to occur and compensate for them with high confidence? Under what conditions will design guardbanding be absolutely necessary? If we do let errors occur periodically, will customers buy the associated products and is there a marketplace for such error-resilient ICs?
7623585
Low-Overhead, High-Speed Multi-core Barrier Synchronization
Whereas efficient barrier implementations were once a concern only in high-performance computing, recent trends in core integration make the topic relevant even for general-purpose CMPs. While the nature of CMP applications requires low-latency, the cost of low-latency barrier implementations using hardware-based techniques can be prohibitive for CMPs, where die area represents opportunities for throughput and yield. Similarly, whereas traditional multiprocessor barrier implementations were developed primarily for dedicated environments, scheduling and multi-programming on CMPs require more adaptable barrier implementations. 
 
In this paper, we present and evaluate three barrier implementations that are hybrids of software and dedicated hardware barriers and are specifically tailored for CMPs. The implementations leverage the unique characteristics of CMPs and provide low latency comparable to that of dedicated hardware networks at a fraction of the cost. The implementations also support adaptability, enabling efficient multi-programming and dynamic remapping of the barrier network.