This paper presents the development of a new algorithm for Gaussian based color image enhancement system. The algorithm has been designed into architecture suitable for FPGA ASIC implementation. The color image enhancement is achieved by first convolving an original image with a Gaussian kernel since Gaussian distribution is a point spread function which smoothes the image. Further, logarithm-domain processing and gain offset corrections are employed in order to enhance and translate pixels into the display range of 0 to 255. The proposed algorithm not only provides better dynamic range compression and color rendition effect but also achieves color constancy in an image. The design exploits high degrees of pipelining and parallel processing to achieve real time performance. The design has been realized by RTL compliant Verilog coding and fits into a single FPGA with a gate count utilization of 321,804. The proposed method is implemented using Xilinx Virtex-II Pro XC2VP40-7FF1148 FPGA device and is capable of processing high resolution color motion pictures of sizes of up to 1600×1200 pixels at the real time video rate of 116 frames per second. This shows that the proposed design would work for not only still images but also for high resolution video sequences.
A design of a high performance digital architecture for a nonlinear image enhancement technique is presented in this paper. The image enhancement is based on illuminance-reflectance model which improves the visual quality of digital images and video captured under insufficient or non-uniform lighting conditions [1]. Systolic, pipelined and parallel design techniques are utilized effectively in the proposed FPGA-based architectural design to achieve real-time performance. Estimation and folding techniques are used in the hardware algorithmic design to achieve faster, simpler and more efficient architecture. The video enhancement system is implemented using Xilinx's multimedia development board that contains a VirtexII-X2000 FPGA and it is capable of processing approximately 66 Mega-pixels (Mpixels) per second. A luminance based multi scale retinex (LB spl I.bar MSR) algorithm for the enhancement of darker images is proposed in this paper. The new technique consists only the addition of the convolution results of 3 different scales. In this way, the color noise in the shadow dark areas can be suppressed and the convolutions with different scales can be calculated simultaneously to save CPU time. Color saturation adjustment for producing more natural colors is implemented. Each spectral band can be adjusted based on the enhancement of the intensity of the band and by using a color saturation parameter. The color saturation degree can be automatically adjusted according to different types of images by compensating the original color saturation in each band. Luminance control is applied to prevent the unwanted luminance drop at the uniform luminance areas by automatically detecting the luminance drop and keeping the luminance up to certain level that is evaluated from the original image. Down-sized convolution is used for fast processing and then the result is re-sized back to the original size. Performance of the new enhancement algorithm is tested in various images captured at different lighting conditions. It is observed that the new technique outperforms the conventional MSR technique in terms of the quality of the enhanced images and computational speed. A novel architecture for performing hue-saturation-value (HSV) domain enhancement of digital color images with non-uniform lighting conditions is proposed in this paper for video streaming applications. The approach promotes log-domain computation to eliminate all multiplications, divisions and exponentiations utilizing the effective logarithmic estimation modules. An optimized quadrant symmetric architecture is incorporated into the design of homomorphic filter for the enhancement of intensity value. Efficient modules are also presented for conversion between RGB and HSV color spaces. The design is able to bring out details hidden in shadow regions of the image. It is capable of producing 187.86 million outputs per second (MOPs) on Xilinx's Virtex II XC2V2000-4ff896 field programmable gate array (FPGA) at a clock frequency of 187.86 MHz. It can process over 179.1 (1024 X 1024) frames per second and consumes approximately 70.7 and 76.8 less hardware resource with 127 and 280 performance boost when compared to the designs with machine learning algorithm [10], and with separated dynamic and contrast enhancements [11], respectively. The aim of this work is to design a real-time adaptive and reusable image enhancement architecture for video signals, based on a statistical processing of the video sequence. The VHDL hardware description language has been used in order to make possible a top-down design methodology. Generic design methodology has been followed by means of two features of the VHDL: global packages and generic pass. Image processing systems like this one require specific simulation tools in order to reduce the development time. A VHDL test bench has been designed specifically for image processing applications to facilitate the simulation process. It was necessary to define a new image file format with special characteristics for this purpose. A physical realization has been carried out on a FPGA to prove the validation of the design.