A physical unclonable function (PUF), like a fingerprint, exploits manufacturing randomness to endow each physical item with a unique identifier. One primary PUF application is the secure derivation of volatile cryptographic keys using a fuzzy extractor (FE) comprising: 1) a secure sketch and 2) an entropy extractor. Although the entropy extractor can be lightweight, the overhead of the secure sketch responsible for correcting naturally noisy PUF responses is usually high. We observe that, in general, response unreliability with respect to an enrolled reference measurement increases with increasing differences between the in-the-field PUF operating condition and the operating condition used in evaluating the enrolled reference response. For the first time, we exploit such an inadvertent but important observation. In contrast to the conventional single reference response enrollment, we propose enrolling multiple reference responses (MRRs) subject to the same challenge but under multiple distinct operating conditions. The critical observation here is that one of the reference operating conditions is likely to be closer to the operating condition of the field deployed PUF, thus resulting in minimizing the expected unreliability when compared to the single reference under the nominal condition. As a consequence, MRR greatly reduces the demand for the expected number of erroneous bits requiring correction and, subsequently, achieves a significant reduction in the error correction overhead. The significant implementation efficiency gains from the proposed MRR method are demonstrated from software implementations of FEs on batteryless resource constraint computational radio frequency identification devices, where realistic PUF data are collected from intrinsic static random access memory PUFs.
Ring oscillator (RO)-based physical unclonable function (PUF) is an emerging hardware security primitive but its response reproducibility is susceptible to changes in operating conditions and device aging. Present solutions to increase RO PUF reliability either incur large hardware overhead or require sophisticated RO selection algorithm. This paper exploits the optimal biasing of current starved (CS) inverter for the design of RO PUF with very high reliability against both temperature and voltage variations. With two additional transistors, the CS inverter can be adaptively biased at idle time and in active mode to significantly reduce the overall stress, making the proposed CS RO PUF robust against both environmental condition variations and aging. Without using error correction code, the reliability is further improved by a low-cost proximity detector circuit with a small sacrifice on challenge-response pair space. The correlation between successive RO pairs of different input challenges is also broken by an irregular clocking of the linear feedback shift register used to encipher the input challenges. Based on Monte Carlo simulation in TSMC 40-nm CMOS process, the reliability of native PUF responses has been raised substantially from 89.78 for the regular RO PUF to 95.88 for the proposed CS RO PUF over a broad temperature range of −40°C to 120 °C and ± 20 supply variation. With the proximity detector, the proposed Aging-resistant Current-starved RO (ACRO) PUF can attain 100 reliability statistically by discarding 34.47 fewer challenge-response pairs than the regular RO PUF. It is also 3.7x more aging resilient than existing aging-resilient RO PUFs with 2.38x lower power dissipation. In this paper we describe the results of our investigations Supported by EU FP7 project UNIQUE on the randomness and reliability of D flip-flops when used as a Physically Unclonable Function (PUF). These D flip-flops are hardware components which present a random start-up value when powered up. We show that against all odds, enough randomness exists in such elements when implemented on an Application-Specific Integrated Circuit (ASIC) to turn the responses of a number of D flip-flops into a secret random sequence allowing to derive keys for use in conjunction with cryptographic algorithms. In addition to being unpredictable, these flip-flops have the advantage that they can be spread over random locations in an ASIC. This makes them very difficult to reverse-engineer when used to hide a secret key in a design at a relatively small cost in resources.  One main problem encountered in the FPGA implementation of Arbiter based Physical Unclonable Function (A-PUF) is the response instability caused by the metastability of delay flip-flop. This paper presents a new multi-arbiter approach to extract more entropy to extend the number of response bits to a single challenge. New multi-arbiter schemes based on the insertion of either a four-flip-flop arbiter or SR latch arbiter after each pair of multiplexers in the configurable paths are proposed to detect the metastable state when two copies of test pulse arrive at the arbiter inputs almost simultaneously. The detected metastable states are distinguishable by the encoded multiple valued outputs of the arbiter. The codes corresponding to the metastable states collectively form a deterministic ternary state that can be recoded to one of the stable states to improve the uniqueness and reliability of the PUF. Our analysis shows that the proposed design can generate robust and reliable challenge-response pairs with a uniqueness of 0.4982 and a reliability of 0.9985 at the expense of a relatively small FPGA resource overhead. A 128-bit, 1.6 pJ bit, 96 stable chip ID generation circuit utilizing process variations is designed in a 0.13 mum CMOS process. The circuit consumes 162 nW from a 1 V supply at low readout frequencies and 1.6 muW at 1 Mb s. Cross-coupled logic gates were employed to simultaneously generate, amplify, and digitize the random circuit offset to create a stable unique digital chip ID code. A thorough statistical analysis is presented in order to explore the ID circuit reliability and stability. Two ID generators with different layout techniques were designed and fabricated to provide a performance comparison of power consumption, ID stability, and ID statistical robustness. We introduce the notion of a Physical Random Function (PUF). We argue that a complex integrated circuit can be viewed as a silicon PUF and describe a technique to identify and authenticate individual integrated circuits (ICs).We describe several possible circuit realizations of different PUFs. These circuits have been implemented in commodity Field Programmable Gate Arrays (FPGAs). We present experiments which indicate that reliable authentication of individual FPGAs can be performed even in the presence of significant environmental variations.We describe how secure smart cards can be built, and also briefly describe how PUFs can be applied to licensing and certification applications. Silicon physical unclonable function (PUF) is a popular hardware security primitive that exploits the intrinsic variation of IC manufacturing process to generate chip-unique information for various security related applications. For example, the PUF information can be used as a chip identifier, a secret key, the seed for a random number generator, or the response to a given challenge. Due to the unpredictability and irreplicability of IC manufacturing variation, silicon PUF has emerged as a promising hardware security primitive and gained a lot of attention over the past few years. In this article, we first give a survey on the current state-of-the-art of silicon PUFs, then analyze known attacks to PUFs and the countermeasures. After that we discuss PUF-based applications, highlight some recent research advances in ring oscillator PUFs, and conclude with some challenges and opportunities in PUF research and applications.  Physically unclonable functions (PUFs) are innovative physical security primitives that produce unclonable and inherent instance-specific measurements of physical objects; in many ways they are the inanimate equivalent of biometrics for human beings. Since they are able to securely generate and store secrets, they allow us to bootstrap the physical implementation of an information security system. In this book the author discusses PUFs in all their facets: the multitude of their physical constructions, the algorithmic and physical properties which describe them, and the techniques required to deploy them in security applications. The author first presents an extensive overview and classification of PUF constructions, with a focus on so-called intrinsic PUFs. He identifies subclasses, implementation properties, and design techniques used to amplify submicroscopic physical distinctions into observable digital response vectors. He lists the useful qualities attributed to PUFs and captures them in descriptive definitions, identifying the truly PUF-defining properties in the process, and he also presents the details of a formal framework for deploying PUFs and similar physical primitives in cryptographic reductions. The author then describes a silicon test platform carrying different intrinsic PUF structures which was used to objectively compare their reliability, uniqueness, and unpredictability based on experimental data. In the final chapters, the author explains techniques for PUF-based entity identification, entity authentication, and secure key generation. He proposes practical schemes that implement these techniques, and derives and calculates measures for assessing different PUF constructions in these applications based on the quality of their response statistics. Finally, he presents a fully functional prototype implementation of a PUF-based cryptographic key generator, demonstrating the full benefit of using PUFs and the efficiency of the processing techniques described. This is a suitable introduction and reference for security researchers and engineers, and graduate students in information security and cryptography. Ring oscillator (RO)-based physical unclonable function (PUF) is resilient against noise impacts, but its response is susceptible to temperature variations. This paper presents a low-power and small footprint hybrid RO PUF with a very high temperature stability, which makes it an ideal candidate for lightweight applications. The negative temperature coefficient of the low-power subthreshold operation of current starved inverters is exploited to mitigate the variations of differential RO frequencies with temperature. The new architecture uses conspicuously simplified circuitries to generate and compare a large number of pairs of RO frequencies. The proposed nine-stage hybrid RO PUF was fabricated using global foundry 65-nm CMOS technology. The PUF occupies only @math of chip area and consumes only @math per challenge response pair at 1.2 V and 230 MHz. The measured average and worst-case reliability of its responses are 99.84 and 97.28 , respectively, over a wide range of temperature from −40 to 120 °C. Cloning, theft of service and tampering have become serious threats on the revenue and reputation of hardware vendors. To protect their products against these attacks hardware security, based on cryptographic primitives using keys, can be used. These keys are usually stored somewhere in the hardware, so the strength of the security depends on the effort required from attackers to compromise them. Tools for attacking hardware have become very advanced, which has decreased the protection provided by storing a key in memory to a minimum. To protect devices against attacks on their keys, Physically Unclonable Functions (PUFs) can be used. PUFs are primitives that extract secrets from physical characteristics of integrated circuits (ICs) and can be used, amongst others, for secure key storage. This paper introduces a new type of PUF, the Buskeeper. In our study this new type of PUF is evaluated on the properties of reliability and uniqueness. For this purpose several tests have been performed in order to compare the results of Buskeeper PUFs to those of D Flip-Flop (DFF) PUFs from [4] and [14]. This comparison shows that the Buskeeper PUF performs as well as, if not better than, this (already known and generally accepted) PUF type. Since Buskeepers are much more efficient than DFFs in regard to the amount of hardware resources required, we conclude that the Buskeeper PUF is a viable (and probably preferable) alternative to DFF PUFs. We present a side-channel attack based on remanence decay in volatile memory and show how it can be exploited effectively to launch a noninvasive cloning attack against SRAM physically unclonable functions (PUFs) - an important class of PUFs typically proposed as lightweight security primitives, which use existing memory on the underlying device. We validate our approach using SRAM PUFs instantiated on two 65-nm CMOS devices. We discuss countermeasures against our attack and propose the constructive use of remanence decay to improve the cloning resistance of SRAM PUFs. Moreover, as a further contribution of independent interest, we show how to use our evaluation results to significantly improve the performance of the recently proposed TARDIS scheme, which is based on remanence decay in SRAM memory and used as a time-keeping mechanism for low-power clockless devices. Physically Unclonable Functions (PUFs) are lightweight hardware security primitives for generating unique signatures from the unpredictable nature of silicon. However, most of the proposed PUFs have been shown to be vulnerable to modeling attacks, especially against Machine Learning algorithms. A subset of challenge-response pairs can leak the required information to break a PUF due to the presence of a linear separating boundary between the PUF responses. In this paper, we propose a strong and secure PUF based on non-linear current mirrors. The fundamental idea is to propagate a current through two identical chains of non-linear current mirrors. The current through a single stage is shifted by some amount based on the strength of the input current. As the current shift is not a fixed value anymore, strong non-linearity is introduced into the challenge-response relationship. The proposed PUF shows excellent properties upon statistical circuit simulation. The average inter-distance and intra-distance of the proposed PUF are 49.9 and 0.8 respectively. One of the most striking features of the proposed PUF is the low information leakage measured in terms of its modeling attack resistance. By employing Support Vector Machine (SVM) based attacks, we observed that the proposed PUF is almost 10-30x stronger than the delay-based PUFs. Moreover, the current mode nature of the PUF circuit enables low power operation. The proposed PUF consumes about 15 lower energy than an arbiter PUF to produce a single response bit. Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describe how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations. Intermittently powered applications create a need for low-cost security and privacy in potentially hostile environments, supported by primitives including identification and random number generation. Our measurements show that power-up of SRAM produces a physical fingerprint. We propose a system of fingerprint extraction and random numbers in SRAM (FERNS) that harvests static identity and randomness from existing volatile CMOS memory without requiring any dedicated circuitry. The identity results from manufacture-time physically random device threshold voltage mismatch, and the random numbers result from runtime physically random noise. We use experimental data from high-performance SRAM chips and the embedded SRAM of the WISP UHF RFID tag to validate the principles behind FERNS. For the SRAM chip, we demonstrate that 8-byte fingerprints can uniquely identify circuits among a population of 5,120 instances and extrapolate that 24-byte fingerprints would uniquely identify all instances ever produced. Using a smaller population, we demonstrate similar identifying ability from the embedded SRAM. In addition to identification, we show that SRAM fingerprints capture noise, enabling true random number generation. We demonstrate that a 512-byte SRAM fingerprint contains sufficient entropy to generate 128-bit true random numbers and that the generated numbers pass the NIST tests for runs, approximate entropy, and block frequency. Physical unclonable functions (PUFs) are increasingly used for authentication and identification applications as well as the cryptographic key generation. An important feature of a PUF is the reliance on minute random variations in the fabricated hardware to derive a trusted random key. Currently, most PUF designs focus on exploiting process variations intrinsic to the CMOS technology. In recent years, progress in emerging nanoelectronic devices has demonstrated an increase in variation as a consequence of scaling down to the nanoregion. To date, emerging PUFs with nanotechnology have not been fully established, but they are expected to emerge. Initial research in this area aims to provide security primitives for emerging integrated circuits with nanotechnology. In this paper, we review emerging nanotechnology-based PUFs. This paper presents an easy to design Physically Unclonable Function (PUF). The proposed PUF implementation is a loop composed of @math identical and controllable delay chains which are serially assembled in a loop to create a single ring oscillator. The frequency discrepancies resulting from the oscillator driven by complementary combinations of the delay chains allows to characterize one device. The presented PUF, nicknamed the Loop PUF (LPUF), returns a frequency comparison of loops made of @math delay chains ( @math ). The comparisons are done sequentially on the same structure. Unlike others PUFs based on delays, there is no specific routing constraints. Hence the LPUF is particularly flexible and easy to design. The basic use of the Loop PUF is to generate intrinsic device keys for cryptographic algorithms. It can also be used to generate challenge response pairs for simple authentication. Experiments have been carried out on CYCLONE II FPGAs to assess the performance of the LPUF, such as randomness, uniqueness and steadiness. They clearly show both the easiness of design and the quality level of the LPUF. The measurement time steadiness, as well as resistance against side-channel and modeling attacks are discussed.