We consider a task graph to be executed on a set of processors. We assume that the mapping is given, say by an ordered list of tasks to execute on each processor, and we aim at optimizing the energy consumption while enforcing a prescribed bound on the execution time. While it is not possible to change the allocation of a task, it is possible to change its speed. Rather than using a local approach such as backfilling, we consider the problem as a whole and study the impact of several speed variation models on its complexity. For continuous speeds, we give a closed-form formula for trees and series-parallel graphs, and we cast the problem into a geometric programming problem for general directed acyclic graphs. We show that the classical dynamic voltage and frequency scaling (DVFS) model with discrete modes leads to a NP-complete problem, even if the modes are regularly distributed (an important particular case in practice, which we analyze as the incremental model). On the contrary, the VDD-hopping model leads to a polynomial solution. Finally, we provide an approximation algorithm for the incremental model, which we extend for the general DVFS model.
As an increasing number of electronic systems are powered by batteries, battery life becomes a primary design consideration. Maxiimizing battery life requires system designers to develop an understanding of the capabilities and limitations of the batteries that power such systems, and to incorporate battery considerations into the system design process. Recent research has shown that, the amount of energy that can be supplied by a given battery varies significantly, depending on how the energy is drawn. Consequently, researchers are attempting to develop new battery-driven approaches to system design, which deliver battery life improvements over and beyond what can be achieved through conventional low-power design techniques. This paper presents an introduction to this emerging area, surveys promising technologies that have been developed for battery modeling and battery-efficient system design, and outlines emerging industry standards for smart battery systems. In this paper we investigate possible ways to improve the energy efficiency of a general purpose microprocessor. We show that the energy of a processor depends on its performance, so we chose the energy-delay product to compare different processors. To improve the energy-delay product we explore methods of reducing energy consumption that do not lead to performance loss (i.e. wasted energy), and explore methods to reduce delay by exploiting instruction level parallelism. We found that careful design reduced the energy dissipation by almost 25 . Pipelining can give approximately a 2 spl times improvement in energy-delay product. Superscalar issue, however, does not improve the energy-delay product any further since the overhead required offsets the gains in performance. Further improvements will be hard to come by since a large fraction of the energy (50-80 ) is dissipated in the clock network and the on-chip memories. Thus, the efficiency of processors will depend more on the technology being used and the algorithm chosen by the programmer than the micro-architecture.