A modified Gradient Descent Bit Flipping (GDBF) algorithm is proposed for decoding Low Density Parity Check (LDPC) codes on the binary-input additive white Gaussian noise channel. The new algorithm, called Noisy GDBF (NGDBF), introduces a random perturbation into each symbol metric at each iteration. The noise perturbation allows the algorithm to escape from undesirable local maxima, resulting in improved performance. A combination of heuristic improvements to the algorithm are proposed and evaluated. When the proposed heuristics are applied, NGDBF performs better than any previously reported GDBF variant, and comes within 0.5 dB of the belief propagation algorithm for several tested codes. Unlike other previous GDBF algorithms that provide an escape from local maxima, the proposed algorithm uses only local, fully parallelizable operations and does not require computing a global objective function or a sort over symbol metrics, making it highly efficient in comparison. The proposed NGDBF algorithm requires channel state information which must be obtained from a signal to noise ratio (SNR) estimator. Architectural details are presented for implementing the NGDBF algorithm. Complexity analysis and optimizations are also discussed.
Stochastic decoding is a recently proposed approach for graph-based iterative error control decoding. We present and investigate three hysteresis methods for stochastic decoding on graphs with cycles and show their close relationship with the successive relaxation method. Implementation results demonstrate the tradeoff in bit error rate performance with circuit complexity.  This paper proposes Tracking Forecast Memories (TFMs) as a novel method for implementing re-randomization and de-correlation of stochastic bit streams in stochastic channel decoders. We show that TFMs are able to achieve decoding performance similar to that of the previous re-randomization methods in the literature (i.e., edge memories), but they exhibit much lower hardware complexity. We then present circuit topologies for analog implementation of TFMs. This paper proposes majority-based tracking forecast memories (MTFMs) for area efficient high throughput ASIC implementation of stochastic Low-Density Parity-Check (LDPC) decoders. The proposed method is applied for ASIC implementation of a fully parallel stochastic decoder that decodes the (2048, 1723) LDPC code from the IEEE 802.3an (10GBASE-T) standard. The decoder occupies a silicon core area of 6.38 mm2 in CMOS 90 nm technology, achieves a maximum clock frequency of 500 MHz, and provides a maximum core throughput of 61.3 Gb s. The decoder also has good decoding performance and error-floor behavior and provides a bit error rate (BER) of about 4 × 10-13 at Eb N0=5.15 dB. To the best of our knowledge, the implemented decoder is the most area efficient fully parallel soft -decision LDPC decoder reported in the literature. A device for controlling timing of fuel supply for starting a gas turbine engine which has a glow plug as an ignition source for fuel is herein disclosed. The device comprises a temperature sensor mounted on the engine for detecting the initial temperature of the glow plug upon application of electricity to the glow plug and generating a signal for starting the engine, which corresponds to the initial temperature of the glow plug, a means for determining time for preheating the glow plug from starting of application of electricity to the glow plug till starting of the engine by the signal and a means for determining timing for starting fuel supply to a combustion chamber of the engine after starting thereof by the signal. This letter presents the first successful method for iterative stochastic decoding of state-of-the-art low-density parity-check (LDPC) codes. The proposed method shows the viability of the stochastic approach for decoding LDPC codes on factor graphs. In addition, simulation results for a 200 and a 1024 length LDPC code demonstrate the near-optimal performance of this method with respect to sum-product decoding. The proposed method has a significant potential for high-throughput and or low complexity iterative decoding. An iterative decoding architecture based on stochastic computational elements is proposed. Simulation results for a simple low-density parity-check code demonstrate near-optimal performance with respect to a maximum likelihood decoder. The proposed method provides an alternative to analogue decoding for high-speed low-power applications. This paper introduces clockless stochastic decoding for high-throughput low-density parity-check (LDPC) decoders. Stochastic computation provides ultra-low-complexity hardware using simple logic gates. Clockless decoding eliminates global clocking, which eases the worst-case timing restrictions of synchronous stochastic decoders. The lack of synchronization might use outdated bits to update outputs in computation nodes; however, it does not significantly affect output probabilities. A timing model of clockless-computation behaviours under a 90 nm CMOS technology is used to simulate the BER performance of the proposed decoding scheme. Based on our models, the proposed decoding scheme significantly reduces error floors due to the "lock-up" problem and achieves superior BER performance compared with conventional synchronous stochastic decoders. The timing model includes metastability to verify the affect on BER performance.