ITEM 1. BUSINESS
INTRODUCTION
Synopsys, Inc. ("Synopsys" or the "Company") is a leading supplier of electronic design automation (EDA) software to the global electronics industry. The Company's products are used by designers of integrated circuits (ICs), including system-on-a-chip ICs, and the electronic products (such as computers, cell phones, and internet routers) that use such ICs to automate significant portions of their chip design process. ICs are distinguished by the speed at which they run, their area, the amount of power they consume and the cost of production. The Company's products offer its customers the opportunity to design ICs that are optimized for speed, area, power consumption and production cost, while reducing overall design time. The Company also provides consulting services to assist customers with their IC designs, as well as training and support services. Synopsys was incorporated in Delaware in 1987.
THE ROLE OF EDA IN THE ELECTRONICS INDUSTRY
Over the past three decades, technology advances in the semiconductor industry have dramatically increased the size, speed and capacity of ICs:
- The number of transistors that can be placed on a chip has doubled roughly every 18 months. A state-of-the-art IC may hold over 20 million transistors. This is made possible in large part because the width of the features on the chip is steadily shrinking. Most ICs today are produced at 0.35 micron or 0.25 micron. Over the next several years, the bulk of production will shift to 0.18 micron, and then to 0.13 micron or below.
- The speed at which chips operate has steadily increased. Microprocessors operating at 1.4 gigahertz, a speed that was unheard of a few years ago, are available today.
- Chips are also becoming more economical in their power consumption, which is necessary to drive more and more powerful handheld devices.
- Increasingly, functions that formerly were performed by multiple ICs attached to a printed circuit board are being combined in a single chip, referred to as a system-on-a-chip.
Combined, these changes have fostered the development of computers, internet routers, wireless communications networks, hand-held personal digital assistants, and many other goods and services with tremendous capabilities at relatively low cost.
In the current economic environment, competition and continuing innovation have shortened the life cycle of electronic products, so time-to-market is crucial to the success of a product. Time to market can in large part be determined by the time it takes to design the chip that will run such product. EDA products play a critical role in reducing time-to-market for new products by providing IC designers with tools and techniques to (a) reduce the time and manual effort required to design, analyze and verify individual ICs, (b) improve the performance and density of complex IC designs and (c) enhance the reliability of the IC design and manufacturing process.
THE DESIGN PROCESS
In simplified form, the design of an integrated circuit consists of five basic steps:
System Design. First, a designer describes the functions that the chip is to perform in a specialized high level computer language. During this phase, designers perform high level architectural design tradeoffs, to determine, for example, which algorithms to use to implement the design, and what portions of the design to implement in hardware and what portions in software. At the completion of this phase, the designer produces a "register transfer language" or "RTL" description of the chip. Most of this process is completed manually, although there is a small but growing market for products that help automate design and verification at the system level.
Logic Synthesis. After the designer is satisfied with the RTL code, a logic synthesis program converts the RTL code into a logical diagram of the chip. Related programs insert the circuitry that will be required to test the chip after manufacture. A "gate level" (so called because it describes the various logic blocks, or gates, required to implement the chip) data file is produced. In a growing number of designs, the logic synthesis phase is performed together with a portion of physical design. This combined process, known as "physical synthesis" produces a file containing "placed gates", which describes the logic blocks and includes information about where they will be physically located, or "placed", on a chip. See discussion below under "Current Issues Facing IC Designers".
High Level Verification. At this stage the designer uses simulation and related programs to verify that the design successfully performs the functions that the designer intended, by feeding an exhaustive array of potential inputs into a specialized program, "simulating" the functioning of the chip as designed, and checking to confirm that the outputs match what was expected. The designer also uses a timing analysis program to confirm that the chip as designed will operate at the speed the designer intended.
Physical Design. If the designer is satisfied with the results of high level verification, the transistors, and all of the wires connecting each one of them, are mapped out in a series of transformations that gradually gets more and more detailed. First the location on the chip die of each block of the chip and each transistor within each block is determined -- a process known as "placement" -- then all of the connections between the transistors are determined -- a process known as "routing". The result is one or more data files that can be read by physical verification programs (see below) or by the equipment used to manufacture the chip.
Physical Verification. Before sending the design data file to a chip manufacturer for fabrication, a further verification step is undertaken. The designer must confirm that the chip as placed and routed will operate at the speed anticipated during the logic design phase. The designer also must check for unintended electrical effects that may arise as a consequence of placing certain portions of the chip, or routing certain of its "wires", too close together or in a bad position. Finally, the designer must verify that the final design complies with all of the design rules set forth by the party that will manufacture the chip.
The foregoing discussion has been greatly simplified. In the actual design of a chip each of these steps has a number of different elements. The steps, or the different elements within the steps, may be undertaken in a different order or repeated one to multiple times. In any event, if at any stage of the process the chip does not perform as intended, then the designer must go back one or more steps to either redesign the RTL, redesign the logic, re-run the verification or redo the physical design of the chip. Each iteration takes time, and the more time the process takes, the more difficult it will be for the designer to meet his or her time to market goals.
CURRENT ISSUES FACING IC DESIGNERS
As chip technology continues to advance, and particularly as the state-of-the-art in chip design moves to 0.18 micron and below, Synopsys' customers are facing a number of difficult design challenges:
Timing Closure. Ensuring that a chip will run at the desired speed becomes substantially more difficult as transistor sizes move to 0.18 micron and below. At larger transistor feature sizes, IC designers could use standard estimates of chip timing during the logic design phase, and be confident that the timing characteristics would be preserved through the physical design phase. At 0.18 micron and below, these estimates become more and more unreliable. To address this problem, customers will increasingly need products (referred to in the EDA industry as "physical synthesis" products) that integrate logic design and physical design. Synopsys physical synthesis solution takes physical design information into account during logic design, and produces a file containing "placed gates". Physical synthesis provides more accurate timing estimates at the logic design phase and greatly improving the correlation between original timing estimates after logic design and timing results after physical design.
Verification. Verification is the process of ensuring, at various stages of the design process, that a chip will perform as intended. As the number of transistors on a chip grows, the verification problem grows geometrically. In
fact, with today's chips, verification often takes up the single largest proportion of the overall design process. Verification products must offer customers a combination of speed, accuracy and the ability to focus on the portions of the chip most likely to cause problems.
Designer Shortage. Finding, hiring and retaining qualified design engineers is often the most difficult problem that our customers face. Without enough designers it is difficult for a company to meet ambitious development schedules, and to get its products to market in a timely manner. Companies address this shortage in a variety of ways, including seeking to import designers from outside of the United States, locating development efforts offshore and outsourcing all or parts of their design work. For EDA companies the shortage of designers creates opportunities for companies that offer pre-designed, pre-verified design "building blocks" that can be re-used in multiple designs, and that offer professional services to augment their customers design teams.
SYNOPSYS OVERVIEW
Synopsys provides products and services that help customers meet the challenges of designing leading edge ICs and the products that incorporate them.
Synopsys offers a comprehensive suite of logic synthesis and related products that allow an IC designer to describe chip behavior in a high-level language and convert that description into a map of the logic implementing such chip, including circuits that facilitate testing of the chip it is fabricated. During fiscal 1999 and fiscal 2000, Synopsys has extended its design tools product line to include several products targeted at the physical design portion of the IC design process. Rather than producing a standalone physical design product, Synopsys is focusing on physical synthesis products, which integrate logic design and physical design. In fiscal 2000, Synopsys formally introduced Physical Compiler, the principal product in our physical synthesis suite, which integrates synthesis, placement and global routing.
Synopsys' high level and physical verification products are used by IC designers in several stages of the IC design process to ensure that the resulting IC performs the function that the designer intended. Synopsys' simulation products permit IC designers to simulate their designs and to explore tradeoffs between incorporating functionality in hardware or software. Synopsys also offers a suite of products that help designers focus on the most problematic portions of their chips. And to help customers analyze other aspects of chip performance, Synopsys offers an extensive line of software tools to analyze power, timing and reliability concerns in an IC design at the RTL, gate and transistor level.
Synopsys provides the broadest array of reusable design building blocks of any company in the EDA and intellectual property (IP) industry. The Company's IP products also include software and hardware models, which are used to test an IC design within the context of the system in which the IC will eventually be used.
Synopsys also offers a full range of professional services to help customers improve their internal design methodologies, as well as design services ranging from specialized assistance to turnkey design.
Synopsys markets its products on a worldwide basis and offers comprehensive customer service, education, consulting, and support as integral components of its product offerings. Products are marketed primarily through its direct sales force. Synopsys has licensed its products to most of the world's leading semiconductor, computer, communications and electronics companies.
STRATEGY
Synopsys' strategy is to develop and offer to its customers a broad array of tools and services required to enable design of complex ICs, especially system-on-a-chip ICs. The Company is seeking to build on its current market position to help customers address the most pressing problems of IC design at 0.18 micron and below: timing closure, verification, and the shortage of skilled designers. First, building from its historical base of strength in high level design, Synopsys plans to help customers address the timing closure problem by continuing its expansion into the market for physical synthesis products -- products that integrate logical and physical design. Second, Synopsys will seek to help customers address their verification needs by building a comprehensive offering of verification products around its current position in simulation, test and timing analysis. Third, Synopsys intends to help customers address the designer shortage by expanding its inventory of reusable design building blocks, which will allow customers to focus their own design teams on areas of competitive differentiation, and by expanding its capacity to offer professional services to supplement customers' own design teams.
PRODUCTS
Synopsys products and services are focused on the principle needs of IP and systems designers, and can be divided into five categories -- IC Implementation, Verification and Test, IP and Systems Design, Transistor Level Design and Professional Services. These products included in these categories are discussed below. Financial information regarding these products is included under Item 7 --Management's Discussion and Analysis of Financial Condition and Results of Operation -- Results of Operation -- Revenue -- Product Groups".
IC Implementation Products
Synopsys' IC Implementation products include the Company's basic logic synthesis and related products, and the Company's new physical synthesis products.
During fiscal 2000, IC Implementation products accounted for 39% of the Company's revenues.
Logic synthesis is the process by which a high-level description of desired chip functions is mapped into a connected collection of logic gates and other circuit elements that performs the desired functions. Design Compiler(TM) is the market-leading logic synthesis tool and is used by a broad range of companies engaged in the design of ICs to optimize their designs for performance and area. Design Compiler was introduced in 1988 and has been updated regularly since then. The Company's Design Compiler product family also includes Power Compiler and Module Compiler. Power Compiler provides "push-button" power optimization and early analysis for the design of low power circuits, which are key for the design of hand-held devices. Module Compiler is used in the design of complex datapaths.
In fiscal 2000, Synopsys released Design Compiler(TM) 2000 as the latest generation in the Design Compiler family. Design Compiler 2000 features significant enhancements, including integration of datapath synthesis technology from the Company's Module Compiler product, enhanced design-for-test capabilities, and improved quality of results. In the Company's physical synthesis suite of products, Design Compiler will continue to be used for synthesis of non-timing-critical portions of a design.
Physical synthesis unites logic synthesis, placement and top level routing and links them together with common timing. When used together, the physical synthesis suite of products provides customers with an integrated design flow from register transfer level (RTL) through placement and top level routing, and addresses the critical timing problems encountered in designing advanced ICs and systems-on-a-chip. In fiscal 2000, Synopsys formally released Physical Compiler, a next-generation product aimed at designing ICs at 0.18 micron and below. Physical Compiler unifies synthesis and placement into a single product to provide high-quality timing closure capability for the individual blocks large IC designs. Physical Compiler is marketed to customers as an upgrade to Design Compiler, and shares with Design Compiler a common database, user model, constraints, timer and libraries.
As of January 15, 2001, Physical Compiler had been licensed to over 70 customers and more than 70 IC designs had been completed using Physical Compiler. During fiscal 2000 the Company received approximately $57 million in orders for Physical Compiler.
The physical synthesis suite of products also includes Chip Architect and FlexRoute. Chip Architect is a hierarchical design planner, which takes into account physical phenomena and is used at various stages of the system-on-a-chip design process to perform chip-level estimation, floor-planning, timing analysis and placement. FlexRoute is a high-capacity, object-based, top-level router, which is used to route the longest, most-difficult-to-route connections between functional blocks on a system-on-a-chip. FlexRoute is "object-based" and permits true gridless routing, which enables chip designers to address issues such as cross-talk, delay and signal integrity, while optimizing chip area.
The Company's IC Implementation products also include logic synthesis products for field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). With the advent of high-density chips (.25 micron and below), FPGAs have become fast enough to handle a substantial fraction of projects that previously required mask-programmed application specific integrated circuits (ASICs). Furthermore, FPGAs' unique ability to deliver very quick time-to-market make them attractive in today's business environment. In fiscal 2000, Synopsys announced new versions of FPGA Express(TM) and FPGA Compiler II(TM).
Verification and Test Products
The Company's Verification and Test products consist of a group of tools, including simulation, test automation and timing verification products, to enable IC designers to quickly and reliably verify the behavior of a design before it is committed to the expensive and time-consuming process of IC fabrication, and to assist in the testing of the chip after manufacturing.
During fiscal 2000, Verification and Test products accounted for 30% of the Company's revenues.
Simulation and related products. Simulation software "exercises" an IC design by running it through a series of tests and comparing the actual outputs from the design with the expected output. As such, simulation products are the key products for functional verification. The goal of simulation is to make sure that the functionality and timing performance of the design meets the original specifications of the chip. Synopsys offers two products for high-level simulation: VCS(TM), for designs written in Verilog (one of the two principal register transfer languages) and Scirocco(TM), for designs written in VHDL (the other principal RTL). Simulation products are distinguished principally by their runtime -- i.e., how fast they can fully simulate a proposed design. The Company is focused on providing the industry's fastest simulation technology and believes that both VCS and Scirocco are industry leaders in performance and capacity. VCS is supported by all major semiconductor manufacturers and many third-party EDA software providers.
In addition to focusing on building the fastest simulator, Synopsys is focused on developing a suite of products that help simulation products work "smarter." The Company estimates that more time is spent in writing verification testbenches than in creating the design description. Testbenches, which create stimuli for chips and check the results, are used in conjunction with simulation tools to verify that a design functions as expected. The Verification Technology group provides software that helps generate and manage testbenches as well as evaluate the effectiveness of the simulation process. VERA(R) is a tool that automates the design of testbenches, thereby offering the IC designer significant reductions in overall design and verification time. VERA provides a high-level language designed specifically for verifying complex designs. VERA is integrated with the Company's other simulation, modeling and hardware/software co-verification products. The Company's CoverMeter product enables designers to measure the effectiveness of their testbenches to ensure that all aspects of the design is tested. CoverMeter is tightly integrated with VCS.
Test Automation. In order to meet today's stringent quality requirements, chips must pass through rigorous testing after manufacturing. Synopsys' design-for-test (DFT) tools offer a complete DFT solution. Synopsys' DFT Compiler, the industry-standard 1-pass test synthesis product, inserts all functional and test logic required to enable efficient, high-coverage testing of the chip after manufacturing, while complying with the customer's design rules and constraints (timing, area, power, etc.). DFT Compiler works seamlessly with Design Compiler and Physical Compiler, with the added benefit, in the case of Physical Compiler, of placement-driven optimization of test logic. In January 2001 DFT Compiler was awarded the 2001 "Best in Test" Award from Test & Measurement World, an industry journal. The award is presented annually to honor important and innovative new products in the electronics test and measurement industry.
Automatic test pattern generation (ATPG) is the other component of Synopsys' complete DFT solution. TetraMAX(TM) ATPG, the Company's ATPG product is optimized for ease-of-use, capacity, speed, coverage and vector compaction. TetraMAX ATPG works in concert with DFT Compiler to enable total automation of the DFT flow. Synopsys test methodology also includes software to facilitate the failure diagnosis of chips after manufacturing test, expediting the time-consuming and expensive post-fabrication activities required to determine the cause of manufacturing defects. TetraMAX ATPG was also awarded the 2000 "Best in Test" award from Test & Measurement World.
Static Timing Analysis. Synopsys provides a complete tool suite to help designers perform static timing analysis at the gate- and transistor levels and analyze signal integrity issues such as cross-talk. Synopsys' gate-level analysis tool is called PrimeTime(R). PrimeTime is a full-chip, gate-level static timing analysis tool targeted for complex multimillion gate designs, which is used by designers to verify, at various stages of the design process, the speed at which a design will operate when it is fabricated. PrimeTime's analysis of a design's speed is accepted as a "sign off" tool by virtually all major semiconductor manufacturers, which means that they accept its analysis as determinative. (Synopsys transistor-level timing analysis products are described below under "Transistor Level Design".
Formal Verification -- Equivalence Checking. Formal verification is a method for comparing two versions of a design to determine if they are equivalent. Usually an RTL version of the design is validated using simulation and other dynamic verification tools, establishing it as the golden version. Subsequent versions (i.e., after each step of the design process) are then compared to the golden version, using mathematical algorithms, to determine if
they are functionally equivalent. The use of formal verification greatly reduces the need to perform simulation, which is substantially more time-consuming, at each stage of the design process, thus potentially saving a significant amount of time in the overall design process. Synopsys' formal verification product is Formality(R). Formality was one of the industry's first commercial equivalency checkers to employ a multi-solver architecture, which enables the verification of complex multimillion-gate system-on-a-chip designs in days or minutes.
Intellectual Property (IP) and Systems Products
The Company's IP and Systems products include our DesignWare, models, and systems design and verification products.
During fiscal 2000, IP and Systems products accounted for 14% of the Company's revenues.
Intellectual Property Products. As IC designs continue to grow in size, reusing design blocks is becoming a more important method for reducing overall design cycle time. By reusing portions of a design, and particularly those that implement basic or standardized functions, a company can let its IC design team focus on designing the chip features that will give its product a competitive advantage. It can also reduce it's verification risk by ensuring that these portions of the chip are of high quality. Enabling reuse of intellectual property (IP) requires a significant methodology shift from traditional IC design. In the past, designs were intimately tied to a particular semiconductor process technology or design methodology, making reuse of design blocks from one chip design to the next difficult and costly.
Synopsys' DesignWare(R) product provides IC designers with libraries of pre-designed, pre-verified Synopsys-synthesizable (i.e., usable by Synopsys' design tools in optimizing a design), off-the-shelf design modules to incorporate into their own designs. The DesignWare foundation library includes more than 100 commonly used functions of low- to medium-scale complexity, including an 8051 microcontroller block and a PCI 2.1 bus interface block. DesignWare Developer helps customers package their own low-complexity functions so that they are integrated into designs in the same way as DesignWare components.
The Company's IP and Systems products also include high-level models and tools to facilitate the modeling and verification of complex electronic systems. Synopsys offers a full range of hardware and software modeling solutions. ModelSource(TM) 3000 series is a family of hardware modeling systems for ASIC and board level design which provide a flexible means for designers to model complex devices. ModelSource 3000 systems use the actual integrated circuit to model its own behavior in a larger system. Synopsys' SmartModels(R) Libraries offer models for more than 18,000 commercially available ICs, including a wide range of microprocessors, controllers, digital signal processors, FPGAs, CPLDs, peripherals, memories and standard logic. Synopsys' bus interface models are used to verify that designs comply with established industry standards. Starting in fiscal 2001, these models and the SmartModels libraries will be offered exclusively with DesignWare. In addition, Synopsys offers modeling technologies to allow designers to create models of both standard and proprietary devices. These models support all major EDA simulation environments and a wide range of EDA platforms, giving designers access to a broad range of models to assist them with verification of their designs.
Systems Design and Verification Products. Currently, automated design generally begins at the RTL level, with logic synthesis. The goal of "system-level" products is to permit designers to design and verify their products at a level of abstraction above RTL. Synopsys' systems products consist of the CoCentric(TM) family of tools and methodologies for concurrent design, validation, refinement and implementation of an electronic system.
The CoCentric family of products are based on a new language named "SystemC" developed by Synopsys and now available under an open source license. SystemC enables designers to create, validate and share system level models of a complex IC or system incorporating the chip, and therefore can be used to explore and verify design alternatives at an early stage of the design process. In addition, EDA vendors have complete access to the SystemC modeling platform required to build interoperable tools. SystemC is managed by the Open SystemC Initiative, which includes representation from the systems, semiconductor, IP, embedded software and EDA industries. The steering group is composed of ARM, Cadence Design Systems, CoWare, Ericsson, Fujitsu Microelectronics, Infineon Technologies, Lucent Technologies, Motorola, NEC, Sony, STMicroelectronics, Texas Instruments and Synopsys.
The Company has introduced two products based on SystemC. CoCentric System Studio is a system-level design environment for the rapid creation of executable system specifications that can be verified and implemented as hardware and software functions. System Studio enables designers to use hierarchical graphical and language modeling to capture system complexity in a
unified environment based on C, C++ and SystemC. System Studio supports verification of hardware and software design refinements through concurrent execution of C-based specifications, popular hardware simulators, and a variety of processor models. In fiscal year 2000, Synopsys started to migrate customers of its COSSAP(R) design system to CoCentric System Studio.
CoCentric SystemC Compiler is a synthesis tool that allows designers to implement complex circuits from SystemC, enabling design to progress from an initial C/C++ executable specification. Starting from a higher level of abstraction than Design Compiler and eliminating the need to remodel in Verilog or VHDL, SystemC Compiler accelerates the design cycle. SystemC Compiler allows designers to rapidly create alternative implementations of a design, enabling them to spend time productively evaluating tradeoffs in performance, size and power consumption before committing to a particular implementation. CoCentric SystemC is undergoing evaluation by a number of customers.
In fiscal 2000, the Company's IP and Systems products included silicon libraries of logic functions used in developing ICs. On December 4, 2000, the Company entered into an agreement to sell this business to Artisan Components, Inc. The transaction closed in January 2001.
Transistor Level Design Products
Synopsys' transistor level design products include a range of products in the areas of timing analysis and verification; power management; circuit simulation and IP verification. These products, which are used after the completion of physical design, help customers analyze the increasingly important electrical effects resulting from designing at 0.18 micron and below, and to locate implementation errors that can be costly and time-consuming to correct during or after production. As the logic and physical design phases of IC Implementation grow more and more integrated, the Company is also integrating many of its transistor level design products with its high level verification products, particularly in the areas of timing and power analysis.
During fiscal 2000, Transistor Level Design products accounted for 7% of the Company's revenues.
Static Timing Analysis and Signal Integrity. As part of it's overall approach to timing and signal integrity analysis and verification, Synopsys' offers PathMill(R), PathMillPlus and AMPS(R). These tools are integrated with Arcadia, the Company's resistance and capacitance (RC) extraction tool. The tools enable quick identification and debugging of complex timing problems taking into account signal integrity (not yet released) effects for ICs designed at 0.18 micron and below. PathMill is a transistor-level static timing analysis tool for designers of large, complex and high performance microprocessor and DSPs. PathMillPlus is the next generation IP characterization product that incorporates the capabilities of PathMill and delivers a comprehensive solution for IP characterization and re-use.
Circuit Simulation. TimeMill(R) and PowerMill(R) provide high accuracy, high speed, and high capacity circuit simulation technology. These tools are vital in the diagnosis of design flaws in transistor-level blocks, including the critical memories, datapaths, and analog/mixed-signal blocks, and assist designers with the overall optimization of circuit speed and power dissipation.
Power Management. Synopsys delivers a complete solution to help designers manage and verify power consumption at different levels of the design process. The products in the solution include: Power Compiler (described under IC Implementation category), PrimePower, PowerArc, PowerMill and RailMill. PrimePower, introduced in fiscal 2000, is a dynamic, full-chip comprehensive power analysis tool for complex multimillion-gate ASICs. PrimePower allows users to quickly and efficiently verify that their IC designs meet power budgets and specifications, select the proper packaging, determine cooling requirements and estimate the battery life for portable applications. As a foundation for Synopsys' power solution, PowerArc delivers automatic cell library power characterization, making it easy for library providers and ASIC and silicon vendors to automatically produce power libraries with SPICE-level accuracy.
Synopsys Professional Services Business Unit
Synopsys Professional Services provides a comprehensive portfolio of consulting services covering all critical phases of the system-on-a-chip development process, as well as systems development in wireless and broadband applications. Customers are offered a variety of engagement models ranging from project assistance - which helps a customer design, verify and/or test its chips and improve its design process -- to full turn-key development.
During fiscal 2000, the Synopsys Professional Services business unit accounted for 10% of the Company's revenues.
Internet Design Services Business Unit
Through its DesignSphere(SM) Access program, the Internet Design Services group provides a complete design environment for complex IC development accessible over the internet. This service enables customers to use software of the Company and others remotely without incurring the time and costs of installing, owning and maintaining the software and associated hardware. The software is available on custom-configured, dedicated, high-performance computer hardware, protected by physical and software security measures including firewalls, bi-directional data encryption and custom access protocols. Security is audited by third-party experts, and the Company provides backup and disaster recovery services.
ORGANIZATION
Synopsys is currently organized into four product development groups -- Physical Synthesis, Verification Technology, Intellectual Property and Systems, and Nanometer Analysis and Test -- and a services group -- Synopsys Professional Services. The Physical Synthesis business unit principally develops and manages our IC Implementation products. The Verification Technology business unit develops and manages the simulation products in our Verification and Test product portfolio. The Intellectual Property and Systems business unit develops and manages all of the product in the IP and Systems product category. The Nanometer Analysis and Test business unit develops and manages the timing analysis, power and test products in the Verification and Test product category, and the products in the Transistor Level Design category.
During fiscal year 2000 Synopsys established a business unit -- the Internet Design Services Business Unit -- to develop an "application service provider" or "hosted design environment" business for the Company's software products.
CUSTOMER SERVICE AND SUPPORT
Synopsys devotes substantial resources to providing customers with technical support, customer education, and consulting services. The Company believes that a high level of customer service and support is critical to the adoption and successful utilization of high-level design automation methodology. In Fiscal 2000, service revenue as a percentage of total revenue increased to 44% as compared to 37% in fiscal 1999.
TECHNICAL SUPPORT
Technical support for the Company's products is provided through both field- and corporate-based technical application engineering groups. Synopsys provides customers with software updates and a formal problem identification and resolution process through the Synopsys Technical Support Center. Synopsys' central entry point for all customer inquiries is SolvNET(R), a direct-access service available worldwide, 24 hours per day, through electronic mail and the World Wide Web that lets customers quickly seek answers to design questions or more insight into design problems. SolvNET combines Synopsys' complete design knowledge database with sophisticated information retrieval technology. Updated daily, it includes documentation, design tips, and answers to user questions.
CUSTOMER EDUCATION SERVICES
Synopsys offers workshops focused on many aspects of high-level design languages, high-level design, simulation, synthesis, physical design, system design and test. Regularly scheduled workshops are offered in Mountain View, California; Austin, Texas; Burlington, Massachusetts; Reading, England; Rungis, France; Munich, Germany; Tokyo and Osaka, Japan; Seoul, Korea and other locations. On-site workshops are available on a worldwide basis at customers' facilities or in their locales. Over 15,000 design engineers attended Synopsys workshops during fiscal 2000.
PRODUCT WARRANTIES
Synopsys generally warrants its products to be free from defects in media and to substantially conform to material specifications for a period of 90 days. Synopsys has not experienced significant returns to date.
SUPPORT FOR INDUSTRY STANDARDS
Synopsys actively supports standards that it believes will help its customers increase productivity and solve design problems, including key interfaces and modeling languages that promote system-on-a-chip design and facilitate interoperability of tools from different vendors. Standards in the EDA industry can be obtained through formal accredited committees, by licensing made available to all, or through community licensing.
Synopsys' products support many formal standards, including the two most commonly used hardware description languages, VHDL and Verilog HDL, and industry standard data formats for the exchange of data between Synopsys' tools and other EDA products.
Synopsys is a board member and/or participant in the major EDA standards organizations: Virtual Socket Interface Alliance (VSIA), an industry group formed to promote standards that facilitate the integration and reuse of functional blocks of intellectual property; Accellera, a not-for-profit consortium formed from the union of VHDL International and Open Verilog International to drive language-based standards for systems, semiconductor, and design tools companies; the EDIF steering committee of the Electronics Industry Association (EIA), which evolves the Electronic Design Interchange Format (EDIF); and the interoperability committee of the EDA Consortium, which helps promote interoperability among EDA products from different vendors.
Synopsys' TAP-In program provides open access for all companies to selected interfaces for Synopsys tools. Synopsys has licensed its text-based synthesis library format, Liberty, as well as its design constraints format, SDC, to the majority of the EDA industry, including the Company's competitors, on reasonable terms. Synopsys has licensed to certain EDA companies its VERA API (application programming interface) and VERA HVL (High-level Verification Language) for test bench verification and its OpenESPF format for representing physical data necessary for reliability verification.
SystemC, an open industry standard language for the exchange of intellectual property and executable specifications, is discussed above under "IP and Systems Business Unit."
Synopsys' products are written mainly in the C and C++ languages and utilize industry standards for graphical user interfaces. Synopsys' software runs principally under the UNIX operating system, with some products running under Windows NT and many on Linux. Synopsys' products are offered on the most widely used workstation platforms, including those from Sun Microsystems, Hewlett-Packard, IBM, and Compaq (formerly Digital Equipment Corporation).
SALES, DISTRIBUTION AND BACKLOG
Synopsys markets its products and services primarily through its direct sales and service force in over 30 offices in the United States and principal international markets. Synopsys employs highly skilled engineers and technically proficient sales persons, as required to understand our customers needs and to explain and demonstrate the value of Synopsys' products.
For fiscal years 2000, 1999 and 1998, international sales represented 42%, 34% and 39%, respectively, of Synopsys' total revenue. For the one-month period ended October 31, 1999, international sales represented 36% of the Company's total revenue. Additional information relating to domestic and foreign operations is contained in Note 8 of Notes to Synopsys' Consolidated Financial Statements.
The Company has 23 sales/support centers throughout the United States, in addition to its Mountain View, California headquarters. Internationally, the Company has sales/support offices in Canada, Denmark, Finland, France, Germany, Hong Kong, India, Israel, Italy, Japan, Korea, the People's Republic of China, Singapore, Sweden, Taiwan and the United Kingdom, including international headquarters offices in Ireland. On a limited basis, the Company also utilizes manufacturer's representatives and distributors. The Company has established such relationships in Australia, Brazil, China, India, Korea, Malaysia, and Taiwan.
Synopsys' backlog on December 1, 2000 was approximately $462.8 million, compared to approximately $276.0 million on December 1, 1999.
Backlog consists of orders for system and software products sold under perpetual and time-based licenses with customer requested ship dates within three months but which have not been shipped, orders for customer training and consulting services which are expected to be completed within one year, and
subscription services, maintenance and support with contract periods extending up to fifteen months. In the case of a Technology Subscription License (TSL), including a multiyear TSL, backlog includes the full amount of the order, less any amount of revenue that has been recognized on such TSL.
The Company has not historically experienced significant cancellations of orders. Customers frequently reschedule or revise the requested ship dates of orders however, which can have the effect of deferring recognition of revenue for these orders beyond the expected time period.
RESEARCH AND DEVELOPMENT
The Company's future performance depends in large part on its ability to maintain and enhance its current product lines, develop new products, maintain technological competitiveness, and meet an expanding range of customer requirements. In addition to research and development conducted within each business unit, the Company maintains an advanced research group that is responsible for exploring new directions and applications of its core technologies, migrating new technologies into the existing product lines, and maintaining strong research relationships outside the Company within both industry and academia.
During fiscal years 2000, 1999 and 1998, research and development expenses, net of capitalized software development costs, were $189.3 million, $167.1 million and $156.7 million, respectively. For the one-month period ended October 31, 1999, research and development expenses were $17.2 million. Synopsys capitalized software development costs of approximately $1.0 million, $1.0 million and $2.1 million in fiscal 2000, 1999 and 1998, respectively. For the one-month period ended October 31, 1999, capitalized software development costs were not material. The Company anticipates that it will continue to commit substantial resources to research and development in the future.
MANUFACTURING
Synopsys' manufacturing operations consist of assembling, testing, packaging and shipping its system and software products and documentation needed to fulfill each order. Manufacturing is currently performed in Synopsys' Mountain View, California, Beaverton, Oregon and Dublin, Ireland facilities. Outside vendors provide tape and CD-ROM duplication, printing of documentation and manufacturing of packaging materials. Synopsys employees manufacture and test the hardware modeling system products, with some sub-assembly performed by outside vendors. Synopsys typically ships its software products within 10 days of acceptance of customer purchase orders and execution of software license agreements, unless the customer has requested otherwise. On customer request, Synopsys delivers its software products through electronic means rather than shipping disks. This method of delivery is becoming increasingly common for domestic customers. For its hardware modeling products, Synopsys buys components and assemblies in anticipation of orders and configures units to match orders, typically shipping within one to ten weeks of order acceptance, unless the customer has requested otherwise.
COMPETITION
The EDA industry is highly competitive. We compete against other EDA vendors, and with customers' internally developed design tools and internal design capabilities, for a share of the overall EDA budgets of our potential customers. In general, competition is based on product quality and features, post-sale support, price and, as discussed below, the ability to offer a complete design flow. Our competitors include companies that offer a broad range of products and services, such as Cadence, Mentor Graphics and Avant!, as well as companies, including numerous start-up companies, that offer products focused on a discrete phase of the integrated circuit design process. In certain situations, Synopsys' competitors have been offering aggressive discounts on certain of their products, in particular simulation and synthesis products. As a result, average prices for these products may fall. In order to compete successfully, we must continue to enhance our products and bring to market new products that address the needs of our customers. We also will have to expand our consulting services business. The failure to enhance existing products, develop and/or acquire new products or expand our ability to offer consulting services could have a material adverse effect on our business, financial condition and results of operations.
Technology advances and customer requirements continue to fuel a change in the nature of competition among EDA vendors. Increasingly, EDA companies compete on the basis of "design flows" involving integrated logic and physical design products (referred to as "physical synthesis" products) rather than on the basis of individual "point" tools performing a discrete phase of the design process. The need to offer physical synthesis products will become increasingly important as ICs grow more complex. Our main physical synthesis product was fully released in June 2000, and has been well-received by customers, but we
still do not offer customers a complete design flow. We are working on completing our design flow, although there is no guarantee that we will be able to offer a competitive flow to customers. The market for physical design tools is dominated by Cadence and Avant!, both of which offer products linking logic and physical design. If we are unsuccessful in developing a complete design flow on a timely basis or in convincing customers to adopt our integrated logical and physical design products and methodology, our competitive position could be significantly weakened.
PRODUCT SALES AND LICENSING AGREEMENTS
Synopsys typically licenses its software to customers under non-exclusive license agreements that transfer title to the media only and that restrict use of the software to specified purposes within specified geographical areas. The Company currently licenses the majority of its software as a network license that allows a number of individual users to access the software on a defined network. License fees are dependent on the type of license, product mix and number of copies of each product required.
Synopsys currently offers its software products under either a perpetual license or a shorter-term subscription license. Under a perpetual license a customer pays a one time license fee for the right to use the software. The vast majority of customers also purchase annual software support services, under which they receive minor enhancements to the products developed during the year, bug fixes and technical assistance. A subscription license, and the various forms of time-based licenses that the Company has offered before introducing subscription licenses, operates like a rental of software. A customer pays a fee for license and support over a fixed period of time, and at the end of the time period the license expires unless the customer pays for a renewal. Subscription licenses are offered with a range of terms; the average length is approximately three years. See "Management's Discussion and Analysis of Financial Condition and Results of Operations --Results of Operations-Revenue."
Over the past several years, orders for time-based licenses (now subscription licenses) have increased significantly as a percentage of total product orders. During fiscal year 2000, orders for time-based licenses accounted for 74% of total product orders compared to 64% in fiscal 1999 and 111% in fiscal 1998.
During fiscal year 2001 Synopsys expects that orders for subscription licenses will account for approximately 75% of total product orders and orders for perpetual licenses approximately 25% of total product orders, although there are likely to be variations of plus or minus five percentage points in any particular quarter.
Synopsys offers its hardware modeler products for sale or lease.
PROPRIETARY RIGHTS
The Company primarily relies upon a combination of copyright, patent, trademark and trade secret laws and license and nondisclosure agreements to establish and protect proprietary rights in its products. The source code for Synopsys' products is protected both as a trade secret and as an unpublished copyrighted work. However, it may be possible for third parties to develop similar technology independently. In addition, effective copyright and trade secret protection may be unavailable or limited in certain foreign countries. The Company currently holds U.S. and foreign patents on some of the technologies included in its products and will continue to pursue additional patents in the future.
Although the Company believes that its products, trademarks and other proprietary rights do not infringe on the proprietary rights of third parties, there can be no assurance that infringement claims will not be asserted against the Company in the future or that any such claims will not require the Company to enter into royalty arrangements or result in costly and time-consuming litigation.
EMPLOYEES
As of October 31, 2000, Synopsys had a total of 2,922 employees, of whom 2,098 were based in the United States and 824 were based internationally. Synopsys' future financial results depend, in part, upon the continued service of its key technical and senior management personnel and its continuing ability to attract and retain highly qualified technical and managerial personnel. Competition for such personnel is intense. Experience at Synopsys is highly valued in the EDA industry, and the Company's employees are recruited aggressively by competitors and by start-up companies, including those in internet-related businesses. The Company's salaries are competitive in the market, but under certain circumstances, start-up companies can offer more attractive stock option packages. As a result, the Company has experienced, and may continue to experience, significant employee turnover. There can be no assurance that Synopsys can retain its key managerial and technical employees or
that it can attract, assimilate or retain other highly qualified technical and managerial personnel in the future. None of Synopsys' employees is represented by a labor union. Synopsys has not experienced any work stoppages and considers its relations with its employees to be good.
ITEM 2.
ITEM 2. PROPERTIES
Synopsys' principal offices are located in four adjacent buildings in Mountain View, California, which together provide approximately 400,000 square feet of available space. This space is leased through February 2003. Within one half mile of these buildings, in Sunnyvale, California, Synopsys occupies approximately 200,000 square feet of space in two adjacent buildings, which are under lease through 2007, and approximately 85,000 square feet of space in a third building, which is under lease until April 2007.
The Company currently leases approximately 14,000 square feet in Dublin, Ireland, for its international headquarters and for research and development purposes. This lease expires in May 2001, at which time the Company will execute a 25-year lease for 45,000 square feet in a new facility in Dublin.
The Company leases approximately 93,000 square feet of space in Beaverton, Oregon for administrative, marketing, research and development and support activities. This facility is leased through March 2002, and will be replaced by the newly constructed site in Hillsborough, Oregon.
In addition, the Company leases approximately 82,000 square feet of space in Marlboro, Massachusetts for sales and support, research and development and customer education activities. This facility is leased through March 2009.
The Company currently leases 23 other domestic sales offices throughout the United States, as well as three remote locations. Synopsys currently leases international sales and service offices in Canada, Finland, France, Germany, Hong Kong, India, Israel, Italy, Japan, Korea, the People's Republic of China, Singapore, Sweden, Taiwan, and the United Kingdom. The Company also leases research and development facilities in France, Germany and India.
Synopsys owns a fourth building in Sunnyvale, with approximately 120,000 square feet, which is leased to a third party through May 2003. Synopsys also owns thirty-four acres of undeveloped land in San Jose, California and 13 acres of undeveloped land in Marlboro, Massachusetts. Additionally, Synopsys owns forty-four acres of land in Hillsborough, Oregon on which two buildings, totaling 236,000 square feet, are being constructed, with completion scheduled for December 2001. This facility will replace the currently leased site in Beaverton.
ITEM 3.
ITEM 3. LEGAL PROCEEDINGS
There are no material legal proceedings pending against the Company.
ITEM 4.
ITEM 4. SUBMISSION OF MATTERS TO A VOTE OF SECURITY HOLDERS
No matters were submitted for a vote of security holders during the fourth quarter of the fiscal year covered by this Report.
EXECUTIVE OFFICERS OF THE COMPANY
The executive officers of the Company and their ages, as of December 1, 2000, are as follows:
Dr. Aart J. de Geus co-founded Synopsys and currently serves as Chief Executive Officer and Chairman of the Board of Directors. Since the inception of Synopsys in December 1986 he has held a variety of positions including Senior Vice President of Engineering and Senior Vice President of Marketing. From 1986 to 1992 Dr. de Geus served as Chairman of the Board. He served as President from 1992 to 1998. Dr. de Geus has served as Chief Executive Officer since January 1994 and has held the additional title of Chairman of the Board since February 1998. He has served as a Director since 1986. From 1982 to 1986, Dr. de Geus was employed by General Electric Corporation, where he was the Manager of the Advanced Computer-Aided Engineering Group. Dr. de Geus holds an M.S.E.E. from the Swiss Federal Institute of Technology in Lausanne, Switzerland and a Ph.D. in electrical engineering from Southern Methodist University.
Dr. Chi-Foon Chan joined Synopsys as Vice President of Application Engineering & Services in May 1990. Since April 1997 he has served as Chief Operating Officer and since February 1998 he has held the additional title of President. Dr. Chan also became a Director of the Company in February 1998. From September 1996 to February 1998 he served as Executive Vice President, Office of the President. From February 1994 until April 1997 he served as Senior Vice President, Design Tools Group and from October 1996 until April 1997 as Acting Senior Vice President, Design Reuse Group. Additionally, he has held the titles of Vice President, Engineering and General Manager, DesignWare Operations and Sr. Vice President, Worldwide Field Organization. From March 1987 to May 1990, Dr. Chan was employed by NEC Electronics, where his last position was General Manager, Microprocessor Division. From 1977 to 1987, Dr. Chan held a number of senior engineering positions at Intel Corporation. Dr. Chan holds an M.S. and Ph.D. in computer engineering from Case Western Reserve University.
Vicki L. Andrews joined Synopsys in May 1993 and currently serves as Senior Vice President, Worldwide Sales. Before holding that position, she served in a number of senior sales roles at Synopsys, including Vice President, Global and Strategic Sales, Vice President, North America Sales and Director, Western United States Sales. She has more than 18 years of experience in the EDA industry. Ms. Andrews holds a B.S. in biology and chemistry from the University of Miami.
Robert B. "Brad" Henske joined Synopsys in May 2000 and currently serves as Senior Vice President and Chief Financial Officer. Mr. Henske joined Synopsys from Oak Hill Capital Management, a Robert M. Bass Group private equity investment firm where he was a partner from January 1997 to April 2000. Additionally, Mr. Henske was Executive Vice President and Chief Financial Officer, and a member of the board of directors of American Savings Bank, F.A., a Bass portfolio company from January 1996 to December 1996. Prior to that, he was a business strategy and financial consultant for Bain & Company from September 1988 to December 1995, where he last held the position of Vice President. Mr. Henske received an MBA in finance and strategic management from The Wharton School, University of Pennsylvania. He serves or has served on the board of directors for several companies, including Grove Worldwide, L.L.C., Williams Scotsman, Inc., Reliant Building Products, Inc. and American Savings Bank, F.A.
Steven K. Shevick joined Synopsys in July 1995 and currently serves as Vice President, Investor Relations and Legal, General Counsel and Corporate Secretary. From July 1995 to March 1998 he served as Deputy General Counsel and Assistant Corporate Secretary. In March 1998 he was appointed Vice President, Legal and General Counsel. In October 1999, Mr. Shevick gained the additional title of Vice President of Investor Relations and was appointed Corporate Secretary. Prior to joining Synopsys, Mr. Shevick was a lawyer in the New York, Hong Kong and Washington, D.C. offices of Cleary, Gottlieb, Steen & Hamilton, where his practice focused on international securities transactions, mergers and acquisitions and technology licensing. Mr. Shevick holds an A.B. from Harvard College and a J.D. from Georgetown University Law Center.
There are no family relationships among any executive officers of the Company.
PART II
ITEM 5.
ITEM 5. MARKET FOR REGISTRANT'S COMMON EQUITY AND RELATED STOCKHOLDER MATTERS
The information required by this item is set forth on page 50 of the Synopsys 2000 Annual Report on Form 10-K.
ITEM 6.
ITEM 6. SELECTED FINANCIAL DATA
FINANCIAL SUMMARY
(1) Amounts and per share data for periods presented have been retroactively restated to reflect the merger of Everest Automation, Inc. (Everest) in a pooling-of-interests transaction effective November 21, 1998.
(2) The Company has a fiscal year that ends on the Saturday nearest October 31. Fiscal 2000, 1999, 1997 and 1996 were 52-week years while fiscal 1998 was a 53-week year. Fiscal year 2001 will be a 53-week year. For presentation purposes, the consolidated financial statements and notes refer to the calendar month end. Prior to fiscal 2000, the Company's fiscal year ended on the Saturday nearest to September 30. The period from October 3, 1999 through October 30, 1999 was a transition period. Information for the transition period was filed with Synopsys' quarterly report on Form 10-Q for the first quarter of fiscal 2000 and is included in this annual report.
(3) Includes charges of $1.7 million, $21.2 million, $33.1 million, $5.5 million, $64.5 million, for the years ended October 31, 2000 and September 30, 1999, 1998, 1997, and 1996, respectively, for in-process research and development. Includes merger-related and other costs of $51.0 million and $11.4 million for the years ended September 30, 1998 and 1997, respectively.
ITEM 7.
ITEM 7. MANAGEMENT'S DISCUSSION AND ANALYSIS OF FINANCIAL CONDITION AND RESULTS OF OPERATIONS
The following discussion contains forward-looking statements within the meaning of Section 21E of the Securities Exchange Act of 1934. For example, statements including terms such as "projects," "expects," "believes," "anticipates" or "targets" are forward-looking statements. Actual results could differ materially from those anticipated in such forward-looking statements as a result of certain factors, including those set forth under "Factors That May Affect Future Results."
RESULTS OF OPERATIONS
Business Combinations. During the fourth quarter of fiscal 2000, the Company acquired VirSim, a software product, from Innoveda, Inc., for a purchase price of approximately $7.0 million in cash. The purchase price of the transaction was allocated to the acquired assets based on their estimated fair values as of the date of the acquisition. Amounts allocated to intangible assets and goodwill are being amortized on a straight-line basis over a three-year period.
During the third quarter of fiscal 2000, the Company acquired The Silicon Group, Inc. (TSG), a privately held provider of integrated circuit (IC) design and intellectual property (IP) integration services, for a purchase price of $3.0 million, including cash payments of $1.8 million. The purchase price was allocated to the acquired assets and liabilities based on their estimated fair values at the time of the acquisition. Amounts allocated to intangible assets and goodwill are being amortized on a straight-line basis over a four-year period.
During the first quarter of fiscal 2000, the Company acquired Leda, S.A. (Leda), a privately held provider of RTL coding-style-checkers, for a purchase price of $7.7 million, including cash payments of $7.5 million. The purchase price of the transaction was allocated to the acquired assets and liabilities based on their estimated fair values as of the date of the acquisition. Amounts allocated to developed technology, workforce and goodwill are being amortized on a straight-line basis over a five-year period. Approximately $1.8 million was allocated to in-process research and development and charged to operations because the acquired technology had not reached technological feasibility and had no alternative uses.
Disposition of Viewlogic PCB/Systems Business -- Effect on Comparative Financial Information. The Company merged with Viewlogic in December 1997 in a transaction accounted for as a pooling of interests. On October 2, 1998, the Company sold the printed circuit board and electronics systems business (PCB/Systems business) of Viewlogic. In the discussion below, financial information for fiscal 1999 excludes the PCB/Systems business, while financial information for fiscal 1998 includes the results of the PCB/Systems business. Therefore, the comparative measures included in the discussion, in particular with respect to absolute dollar amounts of revenue or expenditure, are not necessarily valid with respect to the Company's business as it is presently conducted. A pro forma unaudited consolidated statement of income for 1998, excluding the results of the PCB/Systems business and certain unusual charges, was filed with the Securities and Exchange Commission (SEC) on Form 8-K on January 25, 1999.
Revenue. Revenue consists of fees for licenses and subscriptions of the Company's software products. The Company's total revenue decreased by 3% in fiscal 2000 compared to fiscal 1999. The decrease in revenue in fiscal 2000 was primarily attributable to changes we made to our license model at the beginning of the fourth quarter of fiscal 2000. Total revenue for the one month transition period ended October 31,1999 was $23.2 million with product and service revenue of $4.2 million and $19.0 million, respectively. This is compared to the one month ended October 31, 1998 with total revenue of $28.2 million with product and service revenue of $9.9 million and $18.3 million, respectively.
On July 31, 2000, Synopsys introduced Technology Subscription Licenses (TSLs). TSLs are time-limited rights to use Synopsys software. The terms of TSLs, and the payments due thereon, may be structured flexibly to meet the needs of the customer. For creditworthy customers, payments will often extend over the entire term of the license. With minor exceptions, under TSLs, customers cannot obtain major new products developed or acquired during the term of their license without making an additional purchase. TSLs will be structured so that both product and service revenue will generally be recognized ratably over the term of the license, or as payments become due. We expect that the average duration of TSLs will be approximately three years.
Synopsys expects that approximately 75% of its new product orders will be for TSLs and approximately 25% will be for perpetual licenses, in each case plus or minus 5%. Synopsys believes that the principal benefits of TSLs will be that Synopsys will (i) be able to offer customers technology and terms that more
closely match their needs; (ii) have greater visibility into our earnings stream; (iii) see improvements in the pricing environment for our products; and (iv) be able to roll out our new technology in a more planned manner.
The replacement of time-based licenses by subscription licenses will impact our reported revenue, and reported revenue declined in the fourth quarter of fiscal 2000, as compared to both the fourth quarter of fiscal 1999 and the third quarter of fiscal 2000. Under a subscription license, relatively little revenue is recognized during the quarter the product is delivered, and the rest goes into deferred revenue to be recognized over the term of the license. Under the old form of time-based license, generally all license revenue has been recognized in the quarter the product is delivered, with relatively little going into deferred revenue. Therefore, an order for subscription licenses will result in much less current-quarter revenue than an equal-sized order for the old form of time-based license.
Product revenue decreased by 13% to $442.5 million in fiscal 2000 from $505.8 million in fiscal 1999 and increased by 17% from $431.0 million in fiscal 1998 compared to fiscal 1999. The decrease in fiscal 2000 is primarily due to the change in the license model to TSLs, which are recognized ratably over the term of the license. The increase in fiscal 1999 is primarily due to increased worldwide licensing and sales of the Company's EDA software products such as synthesis, verification and system level design software products. Service revenue increased by 14% to $341.3 million in fiscal 2000 from $300.3 million in fiscal 1999 and by 5% from $287.0 million in fiscal 1998 compared to fiscal 1999. For each of the years, these increases were primarily attributable to the renewal of maintenance and support contracts for EDA products and growth in customer training and consulting services.
Revenue from international operations was $327.0 million, $275.2 million and $279.8 million, or 42%, 34% and 39% of total revenue in fiscal 2000, 1999 and 1998, respectively. The increase in international revenue as a percentage of total revenue in fiscal 2000 compared to fiscal 1999 was primarily a result of relatively greater revenue growth in Japan and Asia Pacific. This revenue increase for this region is due to the continued economic recovery in the Pacific Rim and the Company's increased sales focus in this region during fiscal 2000. Revenue from our international operations decreased 31% to $8.7 million for the one month transition period ended October 31, 1999, compared to $12.5 million for the one month ended October 31, 1998. This decrease is attributed to reduced customer shipment requests to receive licenses in October 1999. International revenue represented approximately 37% and 44% of total revenue for the one-month ended October 31, 1999 and 1998, respectively.
Revenue -- Product Groups. For management reporting purposes, the Company's software products have been organized into four distinct product groups -- IC Implementation (composed of two product categories, DC Family and Physical Synthesis), Verification and Test, IP and Systems Design, Transistor Level Design (TLD), and a services group -- Synopsys(R) Professional Services. The following table summarizes the performance of the various groups as a percentage of total company revenue:
(1) Includes revenue from Viewlogic's systems & PCB design business. The segment was sold to a management-led buy-out group during fiscal 1998.
IC Implementation. During fiscal 2000, the Company introduced Physical Compiler, a product that unifies synthesis, placement and global routing. Included in the Physical Synthesis family are Chip Architect, the Company's chip floor-planning product, Flex Route, the Company's high-level router and the Company's detailed routing technology. This product family contributed revenue of $32.6 million during fiscal 2000. The Company expects continued increases in the revenue contribution from the Physical Synthesis family in future years. The decline in revenue contribution percentage of the DC family from fiscal 1999 to fiscal 2000 reflects the maturation of the market for Design Compiler and the beginning of what we believe is a transition from the DC family to the newer
generation of products. The Company expects that revenue and orders from the DC family will remain approximately flat from fiscal 2000 to fiscal 2001, and then will begin to decline. Future revenue growth in the IC Implementation product group is anticipated to come from the Physical Synthesis product family.
Verification and Test. Verification and Test includes the Company's simulation, timing analysis, formal verification and test products. The increase in percentage of total company revenue from fiscal 1999 to fiscal 2000 is due to greater demand for verification products from our customers. The Company expects demand for verification products to continue to increase as both systems and semiconductor companies experience a crisis in verification.
Intellectual Property and System Level Design (IP&SG). The Company's Intellectual Property and System Level Design products include DesignWare, models, system design products and cell libraries (recently sold to Artisan Components -- see Note 10, Subsequent Events, of Notes to Synopsys' Consolidated Financial Statements). Revenue contribution has remained relatively constant over the last three fiscal periods, even with the Viewlogic's Systems & PCB design business segment sale. Revenue growth within the IP&SG group has come primarily from DesignWare, as this product has grown significantly faster other products with in the group.
Transistor Level Design. The Company's transistor level design products include the products acquired though the acquisition of Epic Design Technology, which was completed in fiscal 1997. These tools are used in the transistor-level simulation and analysis. The decline in revenue contribution from 12% in fiscal 1999 to 7% in fiscal 2000 was due to the lack of significant large orders during fiscal 2000 and the effects of competition. This decline also impacted overall Company performance in fiscal 2000. The Company believes the technology embedded in these tools will have significant value to our customers as these customers migrate to smaller geometries in their chip designs.
Professional Services. The Company's Professional Services group includes consulting and training activities as well as the Company's new Internet Design Service Business. The Professional Services group provides a comprehensive portfolio of consulting services covering all critical phases of the system-on-a-chip development process, as well as systems development in wireless and broadband applications. The increase in the total Company revenue contribution for this services group from 8% in fiscal 1999 to 10% in fiscal 2000 is due largely to the increased demand for the Company's turnkey design and wireless and broadband consulting services. The Company anticipates continued growth in fiscal 2001.
Cost of Revenue. Cost of product revenue includes personnel and related costs, production costs, product packaging, documentation, amortization of capitalized software development costs and purchased technology, and costs of the components of the Company's hardware system products. The cost of internally developed capitalized software is amortized based on the greater of the ratio of current product revenue to the total of current and anticipated product revenue or the straight-line method over the software's estimated economic life of approximately two years. Cost of product revenue was 10% of total product revenue for fiscal 2000, as compared to 8% for fiscal 1999. The increase in cost of product revenue is due primarily to the change in the license strategy introduced in Q4 of fiscal 2000. The Company's product costs are relatively fixed and do not fluctuate significantly with changes in revenue or changes in revenue recognition methods. Cost of product revenue for fiscal 1998 was 8% of total product revenue. Cost of service revenue includes personnel and the related costs associated with providing training and consulting services. Cost of service revenue as a percentage of total service revenue was 24% in fiscal 2000, 23% in fiscal 1999 and 20% in 1998. The increases in cost of service revenue over the last two fiscal periods results from the continued investment in the Company's infrastructure required to expand its consulting and training businesses. For the one-month transition period ended October 31, 1999, cost of revenue, as a percentage of total revenue was 32% compared to 31% for the one month ended October 31, 1998. The increase in cost of revenue resulted primarily from increased royalties and personnel costs relating to maintenance and support. The Company expects that cost of revenue in fiscal 2001 will remain flat or increase slightly. In addition, fiscal 2001 will include an additional week of operations due to the method by which we determine our fiscal year.
Research and Development. Research and development expenses increased by 13% to $189.3 million in fiscal 2000, from $167.1 million in fiscal 1999, and by 7% in fiscal 1999 compared to $156.7 million in fiscal 1998, net of capitalized software development costs. Research and development expenses represented 24%, 21% and 22% of total revenue in fiscal 2000, 1999 and 1998, respectively. The increase in absolute dollars reflects the Company's ongoing research and development. A significant portion of the increase for each fiscal year was due to the addition of personnel and personnel related costs, partly through acquisitions, for enhancement of existing applications and development of new products. Also, fiscal 1998 included an additional week of operations, which was partially offset by synergies realized from the integration of Viewlogic into Synopsys' operations. Research and development expenses for the one-month transition period ended October 31, 1999 were $17.2 million as compared to $14.9
million for the one-month ended October 31, 1998. This increase can be attributed to increases in personnel and personnel related costs. The Company anticipates that it will continue to commit substantial resources to research and development in the future, provided that it is able to continue to hire and retain a sufficient number of qualified personnel. If the Company believes that it is unable to enter a particular market in a timely manner, it may license technology from other businesses or acquire other businesses as an alternative to internal research and development. Fiscal 2001 will include an additional week of operations due to the method by which we determine our fiscal year.
Sales and Marketing. Sales and marketing expenses increased by 20% to $288.8 million in fiscal 2000 from $241.6 million in fiscal 1999 and decreased by 2% from $245.4 million in fiscal 1998 compared to fiscal 1999. Sales and marketing expenses represented 37%, 30% and 34% of total revenue in fiscal 2000, 1999 and 1998, respectively. Total expenses increased in absolute dollars and as a percentage of revenue in fiscal 2000 primarily as a result of increases in personnel related costs. Total expenses decreased in absolute dollars and as a percentage of revenue in fiscal 1999 primarily as a result of the divestiture of the PCB/Systems business, as well as savings resulting from ongoing integration of Viewlogic's other operations into the Company as a whole. The fiscal 1998 increase over fiscal 1999 primarily resulted from the additional week of operations. Sales and marketing expenses for the one-month transition period ended October 31, 1999 were $19.0 million as compared to $16.9 million for the one-month ended October 31, 1998. This increase primarily related to the higher costs associated with the 1999 annual business planning events. Fiscal 2001 will include an additional week of operations due to the method by which we determine our fiscal year.
General and Administrative. General and administrative expenses increased to $59.2 million in fiscal 2000 compared to $47.1 million in fiscal 1999. General and administrative expense decreased slightly from $47.2 million in fiscal 1998 compared to fiscal 1999. As a percentage of total revenue, general and administrative expenses were 8%, 6% and 7% in fiscal 2000, 1999 and 1998, respectively. In fiscal 2000, the increase in absolute dollars and percentage of revenue was primarily due to increases in bad debt expense, personnel costs, facility expenditures and patent and proxy services. General and administrative expenses for the one-month transition period ended October 31, 1999 were $5.7 million as compared to $4.9 million for the one-month ended October 31, 1998. This increase was primarily a result of higher professional service fees. Fiscal 2001 will include an additional week of operations due to the method by which we determine our fiscal year.
Operating Expense Targets -- Fiscal 2001. For Fiscal 2001, our target for overall operating expense growth over fiscal 2000, before the amortization of intangible assets, is 2.5% to 3.5%.
Amortization of Intangible Assets. Amortization of intangible assets represents the excess of the aggregate purchase price over the fair value of the tangible and identifiable intangible assets acquired by the Company. Under the Company's accounting policies, intangible assets as of October 31, 2000, including goodwill, are being amortized over the estimated useful life of three to five-year periods. The Company assesses the recoverability of goodwill by determining whether the amortized asset over its useful life may be recovered through estimated future undiscounted cash flows. Amortization of intangible assets charged to operations in fiscal 2000 was $15.1 million as compared to $7.9 million for fiscal 1999. Amortization of intangible assets charged to operations for the one-month ended October 31, 1999 was $1.2 million. Amortization of intangible assets for the one-month ended October 31, 1998 was not material.
Merger-Related and Other Costs. As a result of various business combinations accounted for as pooling of interests during fiscal 1998, the Company incurred merger-related and other costs of $51.0 million. These expenses related to transaction costs, employee termination and transition costs, legal costs, write-off of equipment and other assets, and redundant facility and other costs. During fiscal 1999 and fiscal 2000, the Company did not incur any merger-related or other costs related to business combinations accounted for as a pooling of interests.
In-Process Research and Development. The following paragraphs contain forward-looking statements within the meaning of Section 21E of the Securities Exchange Act of 1934, including statements and assumptions regarding percentage of completion, expected product release dates, dates for which we expect to begin generating benefits from projects, expected product capabilities and product life cycles, costs and efforts to complete projects, growth
rates, royalty rates and projected revenue and expense information used by us to calculate discounted cash flows and discounts rates. These forward-looking statements involve risks and uncertainties, and the cautionary statements set forth below and in "Factors that May Affect Future Results" identify important factors that could cause actual results to differ materially from those predicted in any such forward-looking statement.
Purchased in-process research and development (IPRD) of $1.7 million and $21.2 million in fiscal 2000 and 1999 respectively, represent the write-off of in-process technologies associated with our acquisitions of Leda in fiscal 2000 and Gambit Automated Design, Inc. (Gambit), Stanza Systems, Inc. (Stanza), Smartech, the rights to CoverMeter, a software product owned by Advanced Technology Center, and Apteq Design Systems, Inc. (Apteq), in fiscal 1999. At the date of each acquisition the projects associated with the IPRD efforts had not yet reached technological feasibility and the research and development in process had no alternative future uses. Accordingly, these amounts were expensed on the respective acquisition dates of each of the Acquired Companies. (Also see Note 3, Business Combinations, of Notes to Synopsys' Consolidated Financial Statements.)
Valuation of IPRD. We calculated amounts allocated to IPRD using established valuation techniques in the high technology industry and expensed such amounts in the quarter that each acquisition was consummated because technological feasibility had not been achieved and no alternative future uses had been established. This approach gave consideration to relevant market sizes and growth factors, expected industry trends, the anticipated nature and timing of new product introductions by us and our competitors, individual product sales cycles, and the estimated life of each products' underlying technology.
The fair value of the in-process technology was based on a discounted cash flow model, similar to the traditional "Income Approach," which discounts expected future cash flows to present value, net of tax. In discounting the estimated cash flows, the discount rates used in the present value calculations were typically derived from a weighted-average cost of capital analysis, adjusted upward to reflect additional risks inherent in the development life cycle, the risks associated with achieving such projected cash flows upon successful completion of the acquired projects and the risks and uncertainties in incorporating the acquired technology into the Company's development projects.
Other Income, Net. Other income, net was $40.8 million, $37.0 million and $26.0 million, or 5%, 5% and 4% of total revenue in fiscal 2000, 1999 and 1998, respectively. Other income, net increased in absolute dollars each fiscal year primarily due to higher interest income from higher invested cash balances in fiscal 1999 and from a higher mix of taxable to tax-exempt investments in fiscal 2000. In addition, in fiscal 2000, 1999 and 1998 other income, net increased due to gains realized on sales of equity investments. Other income, net for the one-month transition period ended October 31, 1999 was $1.7 million as compared to $1.1 million for the one-month ended October 31, 1998.
Interest Rate Risk. The Company's exposure to market risk for changes in interest rates relate primarily to its investment portfolio. The Company does not use derivative financial instruments for speculative or trading purposes with respect to its cash and short-term investments. The Company places its investments in a mix of tax-exempt and taxable instruments that meet high credit quality standards, as specified in the Company's investment policy. The policy also limits the amount of credit exposure to any one issue, issuer and type of instrument. The Company does not anticipate any material loss with respect to its investment portfolio.
The following table presents the carrying value and related weighted-average after tax interest rates for the Company's investment portfolio at October 31, 2000. The carrying value approximates fair value at that date. In accordance with the Company's investment policy, all investments mature in fifteen months or less.
Principal (Notional) Amounts in U.S. Dollars:
(See Note 4, Financial Instruments, in accompanying notes to consolidated financial statements for additional information on investment maturity dates,
long-term debt and equity price risk related to the Company's long-term investments.)
Foreign Currency Risk. At the present time, the Company does not generally hedge anticipated foreign currency cash flows but hedges only those currency exposures associated with certain assets and liabilities denominated in nonfunctional currencies. Hedging activities undertaken by the Company are intended to offset the impact of currency fluctuations on these balances. The success of this activity depends upon estimates of intercompany balances denominated in various currencies, primarily the Japanese yen and the euro. The Company had contracts for the sale and purchase of foreign currencies with a notional value expressed in U.S. dollars of $47.5 million. Looking forward, the Company does not anticipate any material adverse effect on its consolidated financial position, results of operations, or cash flows resulting from the use of these instruments. There can be no assurance in the future that these hedging transactions will be effective.
The following table provides information about the Company's foreign exchange forward contracts at October 31, 2000. Due to the short-term nature of these contracts, the amount in U.S. dollars approximates the fair value of the contract at October 31, 2000. These forward contracts mature in approximately thirty days.
Short-Term Forward Contracts to Sell and Buy Foreign Currencies in U.S. Dollars Related to Intercompany Balances:
The unrealized gains/losses on the outstanding forward contracts at October 31, 2000 were immaterial to the Company's consolidated financial statements. The realized gain/loss on these contracts as they matured were not material to the Company's consolidated financial position, results of operations, or cash flows for the periods presented.
Derivative Financial Instruments. Apart from its foreign currency hedging and forward sales of certain equity investments, the Company does not use derivative financial instruments. In particular, the Company does not use derivative financial instruments for speculative or trading purposes.
Extraordinary Items. During fiscal 2000 and 1999, the Company incurred no extraordinary gains or losses. During the first quarter of fiscal 1998, the Company recorded an extraordinary gain on extinguishment of debt of $1.9 million, net of income tax expense of $1.0 million, related to the cancellation of certain interest bearing notes issued by the Company to International Business Machines Corporation (IBM).
During the fourth quarter of fiscal 1998, Synopsys completed the partial spin-off of Viewlogic Systems, Inc. (VSI), a company that owns the printed circuit board (PCB/Systems business) of Viewlogic. Synopsys' merger with Viewlogic in December 1997 was accounted for as a pooling of interests. The spin-off was accounted for as an extraordinary item, as provided by paragraph 60 of Accounting Principles Board Opinion No. 16 (APB 16), and Synopsys recorded an extraordinary gain, net of income tax expense, of $26.5 million in fiscal 1998 in respect to the spin-off. Synopsys retained common stock equal to 14.9% of the fully diluted equity in VSI.
The Company concluded that the disposition of VSI was consistent with its treatment of the Synopsys-Viewlogic merger as a pooling of interests. A condition of the pooling-of-interests treatment is that at the time of the merger, management did not plan to dispose of any significant part of the assets of the merged entity. The Company concluded that this condition was met because, on the date of the Synopsys-Viewlogic merger, the Company did not plan to dispose of the PCB/Systems business. The Company believed that there would be synergies between the Company's "high-level" integrated circuit design products and VSI's PCB design products. The ultimate decision to spin-off VSI was based on changes in circumstances following the Synopsys-Viewlogic merger.
During the months following the merger, the Company came to realize that certain of its assumptions and expectations regarding the operation of the PCB/Systems business as part of Synopsys were not being fulfilled. The Company's initial intent to retain VSI altered due to changes in circumstances as follows:
- A number of engineers working in the PCB/Systems business were hired by competitors, and management became concerned that it would lose more if the business remained part of Synopsys.
- Certain synergies anticipated from operation of the PCB/Systems business as part of Synopsys did not materialize.
- The revenues of the PCB/Systems business grew more slowly than those of Synopsys' other businesses. Management concluded that the reduction in the Company's overall growth rate caused by the PCB/Systems business was contributing to a market discounting of the Company's stock value.
- Managers of the PCB/Systems business concluded that the business could grow faster if it was a stand-alone entity, which would allow them to attract and retain key employees.
Accordingly, Synopsys has not changed its accounting for the Viewlogic merger and has reported the gain on the VSI disposition as an extraordinary item.
EFFECT OF NEW ACCOUNTING STANDARDS
In December 1998, the AICPA issued Statement of Position (SOP) 98-9, Modification of SOP 97-2, Software Revenue Recognition, With Respect to Certain Transactions, which amends SOP 97-2 and supercedes SOP 98-4. The Company adopted SOP 98-9 during fiscal 2000. The adoption of the statement did not have a material impact on the Company's consolidated financial position or results of operations, as the Company modified certain business practices. See Note 1 to Notes to Synopsys' Consolidated Financial Statements.
In fiscal 2000, the Emerging Issues Task Force (EITF) published their consensus on EITF Issue No. 00-2, Accounting for Web Site Development Costs, which requires that costs incurred during the development of web site applications and infrastructure, including developing software to operate the web site, and including graphics that affect the "look and feel" of the web page and all costs relating to software used to operate a web site should be accounted for under Statement of Position 98-1, Accounting for the Costs of Computer Software Developed or Obtained for Internal Use, (SOP 98-1). The Company adopted EITF No. 00-2 in fiscal 2000. The adoption did not have a material effect on our consolidated financial position or results of operations.
In fiscal 2000, the EITF published their consensus on Issue No. 00-3, Application of AICPA Statement of Position 97-2, Software Revenue Recognition, to Arrangements That Include the Right to Use Software Stored on Another Entity's Hardware. The Issue states that a software element covered by SOP 97-2 is only present in a hosting arrangement if the customer has the contractual right to take possession of the software at any time during the hosting period without significant penalty and it is feasible for the customer to either run the software on its own hardware or contract with another party unrelated to the vendor to host the software. The Company recently introduced a software hosting service. Synopsys hosting services agreements now in place do not grant customers the right to take possession of hosted software without an additional charge.
In fiscal 2000, the Financial Accounting Standards Board (FASB) issued Interpretation No. 44, Accounting for Certain Transactions involving Stock Compensation, an interpretation of APB Opinion No. 25. This Interpretation clarifies the application of Opinion 25 for certain issues including: (a) the definition of employee for purposes of applying Opinion 25, (b) the criteria for determining whether a plan qualifies as a noncompensatory plan, (c) the accounting consequence of various modifications to the terms of a previously fixed stock option or award, and (d) the accounting for an exchange of stock option awards in a business combination. The Company adopted Interpretation 44 in fiscal 2000 and the adoption did not have a material effect on our consolidated financial position or results of operations.
In June 1999, the FASB issued Statement of Financial Accounting Standards (SFAS) Nos. 137 and 138, Accounting for Derivative Instruments and Hedging Activities, which amends the effective date of SFAS No. 133, Accounting for Derivative Instruments and Hedging Activities. SFAS No. 133 establishes accounting and reporting standards for derivative financial instruments and hedging activities and requires the Company to recognize all derivatives as either assets or liabilities on the balance sheet and measure them at fair value. Gains and losses resulting from changes in fair value would be accounted for based on the use of the derivative and whether it is designated and qualifies for hedge accounting. The Company will adopt SFAS No. 133 for the fiscal year beginning November 1, 2000. The Company does not expect to have a transition adjustment related to the adoption of SFAS 133.
During fiscal 2000, the Securities and Exchange Commission issued Staff Accounting Bulletin No. 101 ("SAB 101"), Revenue Recognition in Financial Statements. The objective of SAB 101 is to provide further guidance on revenue recognition issues in the absence of authoritative literature addressing a specific arrangement or a specific industry. The Company is required to adopt the guidance in SAB 101 no later than the fourth quarter of its fiscal year 2001. Adoption of this guidance is not expected to have a material impact on the Company's financial position or results of operations.
LIQUIDITY AND CAPITAL RESOURCES
Cash, cash equivalents and short-term investments were $435.6 million at October 31, 2000, a decrease of $273.8 million or 39% from October 31, 1999. The decrease is primarily a result of cash outflow for financing and investing activities, mainly the repurchase of common stock of $397.5 million, capital expenditures of $68.5 million, cash paid for acquisitions of $14.5 million, and cash paid on debt obligations of $14.3 million. These outflows were partially offset by cash generated by operations of $151.1 million and through investing and financing activities, mainly the exercise of stock options and sale of stock through the employee stock purchase plan of $59.5 million, and proceeds from sale of long-term investments of $24.3 million.
Accounts receivable increased 12% during fiscal 2000, while sales declined by 3% to $783.8 million in fiscal 2000 from $806.1 million in fiscal 1999. Days sales outstanding in receivables increased to 99 days as of October 31, 2000 from 61 days at September 30, 1999, largely as a result of decreased revenue in the fourth quarter of fiscal 2000 as compared to the same period in fiscal 1999. The decrease in revenues during the fourth quarter of fiscal 2000 was the result of a change in the Company's license and pricing strategy. As of October 31, 2000, the remaining balance of the Company's accounts receivable sold to a financial institution was $5.3 million.
The Company's management believes that its current cash, cash equivalents, short-term investments, and cash generated from operations will satisfy its expected working capital and capital expenditure requirements for at least the next twelve months.
FACTORS THAT MAY AFFECT FUTURE RESULTS
Our Revenue and Earnings May Fluctuate. Many factors affect our revenue and earnings, which makes it difficult to achieve predictable revenue and earnings growth. Among these factors are customer product and service demand, product license terms, and the timing of revenue recognition on products and services sold. The following specific factors could affect our revenues and earnings in a particular quarter or over several quarterly or annual periods:
- - Our orders have been, and are expected to continue to be, seasonal. Historically, our first fiscal quarter has been our weakest.
- - Our products are complex, and before buying them customers spend a great deal of time reviewing and testing them. Our customers' evaluation and purchase cycles do not necessarily match our quarterly periods. Like many companies in the software industry, in the past we have received a disproportionate volume of orders in the last week of a quarter. In addition, a large proportion of our business is attributable to our largest customers. As a result, if any order, and especially a large order, is delayed beyond the end of a fiscal period, our orders and revenue for that period could be below our plan.
- - Accounting rules determine when revenue is recognized on our product and service contracts, and therefore impact how much revenue we will report in any given fiscal period. The authoritative literature under which the Company recognizes revenue has been, and is expected to continue to be, the subject of much interpretative guidance. In general, following the change to our license model in the fourth quarter of fiscal 2000, most orders for our products and services yield revenue over multiple quarters (extending beyond the current fiscal year) or upon completion of performance rather than at the time the contract is executed. The specific terms agreed to with a customer may have the effect of requiring deferral or acceleration of revenue in whole or in part. Therefore, for any given fiscal period it is possible for us to fall short in our revenue and/or earnings plan even while orders and backlog remain on plan or, conversely, to meet our revenue and/or earnings plan because of backlog and deferred revenue while orders are under plan.
- - In fiscal 2000, we modified the license and pricing structure for our software products twice. We believe that the changes we made in August 2000 (the adoption of Technology Subscription Licenses) are producing benefits for both Synopsys and our customers, but it remains possible that customer reaction will be unfavorable or; that the transition to the new structure will be disruptive to business, in either case resulting in the deferral or loss of sales, or that our planned mix of license types will not be achieved.
Our Industry is Highly Competitive. The EDA industry is highly competitive. We compete against other EDA vendors, and with customers' internally developed design tools and internal design capabilities, for a share of the overall EDA budgets of our potential customers. In general, competition is based on product quality and features, post-sale support, price and, as discussed below, the ability to offer a complete design flow. Our competitors include companies that offer a broad range of products and services, such as Cadence, Mentor and Avant!, as well as companies, including numerous start-up companies, that offer products focused on a discrete phase of the integrated circuit design process. In certain situations, Synopsys' competitors have been offering aggressive discounts on certain of their products, in particular simulation and synthesis products. As a result, average prices for these products may fall. In order to compete successfully, we must continue to enhance our products and bring to market new products that address the needs of our customers. We also will have to expand our consulting services business. The failure to enhance existing products, develop and/or acquire new products or expand our ability to offer consulting services could have a material adverse effect on our business, financial condition and results of operations.
Technology advances and customer requirements continue to fuel a change in the nature of competition among EDA vendors. Increasingly, EDA companies compete on the basis of "design flows" involving integrated logic and physical design products (referred to as "physical synthesis" products) rather than on the basis of individual "point" tools performing a discrete phase of the design process. The need to offer physical synthesis products will become increasingly important, as ICs grow more complex. Our main physical synthesis product was fully released in June 2000, and has been well received by customers, but we still do not offer customers a complete design flow. We are working on completing our design flow, although there is no guarantee that we will be able to offer a competitive flow to customers. The market for physical design tools is dominated by Cadence and Avant!, both of which offer products linking logic and physical design. If we are unsuccessful in developing a complete design flow
on a timely long-term debt basis or in convincing customers to adopt our integrated logical and physical design products and methodology, our competitive position could be significantly weakened.
Our Revenue Growth Depends on New and Non-Synthesis Products. Historically, much of our growth has been attributable to the strength of our logic synthesis products. These products accounted for 35% of revenue in fiscal 2000. We believe that orders and revenues for our flagship logic synthesis product, Design Compiler, peaked in fiscal 2000. Therefore, in order to meet our revenue plan, revenue from our physical synthesis products, our non-synthesis products and professional services must grow faster than our overall revenue growth target. Among the products that we expect to be the most important contributors to revenue growth are our Physical Compiler physical synthesis, VCS Verilog simulation and DesignWare IP library products. If revenue growth for these products fails to meet our goals, it is unlikely that we will meet our overall revenue growth target.
In order to sustain revenue growth over the long term, we will have to introduce new products that are accepted by a broad range of customers and to significantly expand our consulting services business. Product success is difficult to predict. The introduction of new products and growth of a market for such products cannot be assured. In the past we, like all companies, have had products that have failed to meet our revenue expectations. Expanding revenue from consulting services will require us to recruit, hire and train a large number of skilled employees, and to implement management controls on bidding and executing on consulting engagements. The consulting business is significantly different from the software business, however, and increasing consulting orders and revenue while maintaining an adequate level of profit can be difficult. There can be no assurance that we will be successful in expanding revenue from existing or new products at the desired rate or in expanding our services business, and the failure to do so would have a material adverse effect on our business, financial condition and results of operations.
Businesses We Acquire May Not Perform as Projected. We have acquired or merged with a number of companies in recent years, including EPIC Design Technology, Inc., Viewlogic, Systems Science, Inc., Everest, Gambit, Smartech, Stanza, Apteq, TSG and Leda, and as part of our efforts to increase revenue and expand our product and services offerings we may acquire additional companies. In addition to direct costs, acquisitions pose a number of risks, including potential dilution of earnings per share, problems in integrating the acquired products and employees into our business, the failure to realize expected synergies or cost savings, the failure of acquired products to achieve projected sales, the drain on management time for acquisition-related activities, adverse effects on customer buying patterns and assumption of unknown liabilities. While we attempt to review proposed acquisitions carefully and negotiate terms that are favorable to us, there is no assurance that any acquisition will have a positive effect on our performance.
Our Business Depends on the Semiconductor and Electronics Businesses. Purchases of our products are largely dependent upon the commencement of new design projects by semiconductor manufacturers and their customers, the number of design engineers and the increasing complexity of designs. Our business has benefited from the rapid worldwide growth of the semiconductor industry, though we do not directly benefit from increased volume alone. Several semiconductor manufacturers and vendors of products incorporating semiconductors have recently announced earnings shortfalls, and the outlook for the electronics industry, and the U.S. economy as a whole, is uncertain. In addition, demand may be affected by mergers in the semiconductor and systems industries, which may reduce the aggregate level of purchases of our products and services by the combined companies. Slower growth in the semiconductor and electronics industries; a reduced number of design starts; tightening of customers' operating budgets; continued consolidation among our customers or a shift toward FPGAs or other types of semiconductors that can be designed with less-expensive EDA software; all could have a material adverse effect on our business, financial condition and results of operations.
Stagnation of International Economies Would Adversely Affect Our Performance. During fiscal 2000, 42% of our revenue was derived from outside of North America, an increase from 34% in fiscal 1999. International revenue is vulnerable to changes in foreign currency exchange rates and in regional or worldwide economic or political conditions. It will be difficult to sustain our overall growth rate without continued growth in revenue from Japan, Asia Pacific and Europe. Revenue from Japan grew by almost 30% during fiscal 2000, notwithstanding a weak economy, based in large part on the multiyear renewal of licenses by a number of large customers. We do not expect similar growth in revenue from Japan during fiscal 2001. If the Japanese economy remains weak, revenue from Japan, and perhaps the rest of Asia, could be adversely affected. In addition, the yen-dollar and euro-dollar exchange rates remain subject to unpredictable fluctuations. Weakness of the yen could adversely affect revenue from Japan during future quarters. Asian countries other than Japan also have experienced economic and currency problems, and in most cases they have not fully recovered. If such conditions persist or worsen, orders and revenues from the Asia Pacific region would be adversely affected.
Our Success Depends on Recruiting and Retaining Key Personnel. Our success is dependent on technical and other contributions of key employees. We participate in a dynamic industry, with significant start-up activity, and our headquarters is in Silicon Valley, where skilled technical, sales and management employees are in high demand. There are a limited number of qualified EDA engineers, and the competition for such individuals is intense. Experience at Synopsys is highly valued in the EDA industry, and our employees are recruited aggressively by our competitors and by start-up companies. Our compensation packages are competitive in the market, but start-up companies may be able to offer more attractive stock option packages. As a result, we have experienced, and may continue to experience, significant employee turnover. There can be no assurance that we can continue to recruit and retain the technical and managerial personnel we need to run our business. Failure to do so could have a material adverse effect on our business, financial condition and results of operations.
Dependence on Proprietary Technology. Our success is dependent, in part, upon our proprietary technology and other intellectual property rights. We rely on contractual arrangements with customers, employees and others, and intellectual property laws, to protect our proprietary technology. There can be no assurance that these agreements will not be breached, that we would have adequate remedies for any breach or that our trade secrets will not otherwise become known or be independently developed by competitors. Moreover, effective intellectual property protection may be unavailable or limited in certain foreign countries. Failure to obtain or maintain appropriate patent, copyright or trade secret protection, for any reason, could have a material adverse effect on our business, financial condition and results of operations. In addition, there can be no assurance that infringement claims will not be asserted against us; and any such claims could require us to enter into royalty arrangements or result in costly and time-consuming litigation.
Fixed Operating Expenses. Our operating expenses are based in part on our expectations of future revenue, and expense levels are generally committed in advance of revenue. Since only a small portion of our expenses varies with revenue, a shortfall in revenue translates directly into a reduction in net income. For fiscal 2001 our target for overall expense growth over fiscal 2000 is 2.5% to 3.5%, substantially below the rate of growth in recent years, and we have implemented expense controls to achieve this target. If we are unsuccessful in generating anticipated revenue, or unsuccessful at controlling the growth of expenses, however, our business, financial condition and results of operations could be materially adversely affected.
Anti-Takeover Provisions. We have adopted a number of provisions that could have anti-takeover effects. The Board of Directors has adopted a Preferred Shares Rights Plan, commonly referred to as a "poison pill." In addition, the Board of Directors has the authority, without further action by its stockholders, to issue additional shares of Common Stock and to fix the rights and preferences of, and to issue authorized but undesignated shares of Preferred Stock. These and other provisions of Synopsys' Restated Certificate of Incorporation and Bylaws and the Delaware General Corporation Law may have the effect of deterring hostile takeovers or delaying or preventing changes in control or management of Synopsys, including transactions in which the shareholders of the Company might otherwise receive a premium for their shares over then current market prices.
Change in Financial Accounting Standards. We prepare our financial statements in conformity with generally accepted accounting principles (GAAP). GAAP are subject to interpretation by the American Institute of Certified Public Accountants (AICPA), the SEC and various bodies appointed by these organizations to interpret existing rules and create new accounting policies. In particular, a task force of the Accounting Standards Executive Committee, a subgroup of the AICPA, meets on a quarterly basis to review various issues arising under the existing software revenue recognition rules, and issues interpretations of these rules. Additional Interpretations issued by the task force may have an adverse effect on how we report revenue or on the way we conduct our business in the future.
European Monetary Unit. The Company's sales to European customers are primarily U.S. dollar based. The Company has made system changes to make all infrastructures capable of operations in the European Monetary Unit. The Company has not experienced any disruption in operations due to the European Monetary Unit implementation.
ITEM 7A.
ITEM 7A. QUANTITATIVE AND QUALITATIVE DISCLOSURE ABOUT MARKET RISK.
Information relating to quantitative and qualitative disclosure about market risk is set forth in Synopsys' 2000 Annual Report on Form 10-K under the captions "Interest Rate Risk" and "Foreign Currency Risk" in Management's Discussion and Analysis of Financial Condition and Results of Operations, and "Foreign Exchange Hedging" in Note 1 of Synopsys' Notes to Consolidated Financial Statements.
ITEM 8.
ITEM 8. FINANCIAL STATEMENTS AND SUPPLEMENTARY DATA
REPORT OF KPMG LLP, INDEPENDENT AUDITORS
To The Board of Directors and Shareholders of Synopsys, Inc.:
We have audited the accompanying consolidated balance sheets of Synopsys, Inc. and subsidiaries as of October 31, 2000 and 1999 and September 30, 1999, and the related consolidated statements of operations, stockholders' equity and comprehensive income (loss) and cash flows for the year ended October 31, 2000, the one-month period ended October 31, 1999 and each of the years in the two-year period ended September 30, 1999. These consolidated financial statements are the responsibility of the Company's management. Our responsibility is to express an opinion on these consolidated financial statements based on our audits.
We conducted our audits in accordance with auditing standards generally accepted in the United States of America. Those standards require that we plan and perform the audit to obtain reasonable assurance about whether the financial statements are free of material misstatement. An audit includes examining, on a test basis, evidence supporting the amounts and disclosures in the financial statements. An audit also includes assessing the accounting principles used and significant estimates made by management, as well as evaluating the overall financial statement presentation. We believe that our audits provide a reasonable basis for our opinion.
In our opinion, the consolidated financial statements referred to above present fairly, in all material respects, the financial position of Synopsys, Inc. and subsidiaries as of October 31, 2000 and 1999, and September 30, 1999, and the results of their operations and their cash flows for the year ended October 31, 2000, the one-month period ended October 31, 1999 and each of the years in the two-year period ended September 30, 1999 in conformity with accounting principles generally accepted in the United States of America.
/s/ KPMG LLP
Mountain View, California November 17, 2000, except as to Note 10, which is as of January 4, 2001
SYNOPSYS, INC. CONSOLIDATED BALANCE SHEETS (in thousands, except share data)
See accompanying notes to consolidated financial statements.
SYNOPSYS, INC. CONSOLIDATED STATEMENTS OF OPERATIONS (in thousands, except per share data)
See accompanying notes to consolidated financial statements.
SYNOPSYS, INC. CONSOLIDATED STATEMENTS OF STOCKHOLDERS' EQUITY AND COMPREHENSIVE INCOME (LOSS) (in thousands)
See accompanying notes to the consolidated financial statements
SYNOPSYS, INC. CONSOLIDATED STATEMENTS OF CASH FLOWS (in thousands)
See accompanying notes to consolidated financial statements
SYNOPSYS, INC. NOTES TO CONSOLIDATED FINANCIAL STATEMENTS
NOTE 1. SUMMARY OF SIGNIFICANT ACCOUNTING POLICIES
Nature of Operations. Synopsys, Inc. ("Synopsys" or the "Company") is a leading supplier of EDA software to the global electronics industry. The Company develops, markets, and supports a wide range of IC design products that are used by designers of advanced ICs, including system-on-a-chip ICs, and the electronic systems (such as computers, cell phones, and internet routers) that use such ICs. The Company also provides consulting services to help its customers improve their IC design processes and, where requested, to assist them with their IC designs.
Fiscal Year End. The Company has a fiscal year that ends on the Saturday nearest October 31. Fiscal 1999 and 2000 were 52-week years while fiscal 1998 was a 53-week year. Fiscal year 2001 will be a 53-week year. For presentation purposes, the consolidated financial statements and notes refer to the calendar month end.
Principles of Consolidation. The consolidated financial statements include the accounts of the Company and all of its subsidiaries. All significant intercompany accounts and transactions have been eliminated.
Use of Estimates. The preparation of financial statements in conformity with generally accepted accounting principles requires management to make estimates and assumptions that affect the recorded amounts of revenues and expenses, assets and liabilities, disclosure of assets and liabilities at the date of the financial statements. A change in the facts and circumstances surrounding these estimates could result in a change to the estimates and impact future operating results.
Cash Equivalents, Fair Values of Financial Instruments and Concentration of Credit Risk. Financial instruments which potentially subject the Company to concentrations of credit risk consist principally of cash equivalents, investments and trade receivables.
All of the Company's cash equivalents and investments are classified as available-for-sale and unrealized gains and losses (determined as the difference between the recorded amount of the investment and its fair value) are reported in stockholders' equity as a component of accumulated other comprehensive income, net of tax, if any. The fair value of investments is based on quoted market prices. Realized gains and losses are included in other income, net. Cash equivalents have remaining maturities of three months or less when acquired. The Company has cash equivalents and investments with various high quality institutions and, by policy, limits the amount of credit exposure to any one institution.
The Company sells its products worldwide primarily to customers in the semiconductor industry. The Company performs on-going credit evaluations of its customers' financial condition and generally does not require collateral. The Company maintains reserves for potential credit losses, and such losses have been within management's expectations and have not been material in any year. As of October 31, 2000, October 31, 1999, September 30, 1999 and September 30, 1998, the Company had sold approximately $5.3 million, $21.8 million, $22.8 million and $12.6 million, respectively, of its accounts receivable to a financial institution.
The fair value of the Company's cash, accounts receivable, long-term investments, put/call and forward contracts relating to certain of the Company's equity securities, accounts payable, long-term debt and foreign currency contracts, approximates the carrying amount, which is the amount for which the instrument could be exchanged in a current transaction between willing parties.
Foreign Currency Translation. The functional currency of each of the Company's international subsidiaries is the foreign subsidiary's local currency. Assets and liabilities of the Company's international operations are translated into U.S. dollars at exchange rates in effect at the balance sheet date. Income and expense items are translated at average exchange rates for the period. Accumulated net translation adjustments are reported in stockholders' equity as
a component of accumulated other comprehensive income. The associated tax benefit for cumulative translation adjustment was $2.2 million and $0.2 million in fiscal 2000 and 1999, and the associated tax expense was $0.5 million in fiscal 1998. For the one-month ended October 31, 1999, the tax benefit for the cumulative translation was not material. Foreign exchange transaction gains and losses were not material for all periods presented and are included in the results of operations.
Synopsys' international business is an important contributor to the Company's revenue and net profits. However, the majority of Synopsys' international sales are denominated in the U.S. dollar, and an increase in the value of the U.S. dollar relative to foreign currencies could make products sold internationally less competitive. The operating expenses of Synopsys' overseas offices are paid in local currencies and are subject to the effect of fluctuations in foreign currency exchange rates as compared to their respective local currency. The effect of foreign exchange rate fluctuations did not significantly impact the Company's operating results. Financial exposure may nonetheless result, primarily from the timing of transactions and the movement of foreign exchange rates.
Foreign Exchange Contracts. The Company operates internationally and thus is exposed to potentially adverse movements in foreign currency rate changes. In fiscal 2000, the Company entered into foreign exchange forward contracts to reduce its exposure to foreign currency rate changes on non-functional currency denominated balance sheet positions. The objective of these contracts is to neutralize the impact of foreign currency exchange rate movements on the Company' operating results.
These contracts require the Company to exchange currencies at rates agreed upon at the inception of the contracts. The hedge contracts reduce the exposure to fluctuations in exchange rate movements because the gains and losses associated with foreign currency balances and transactions are generally offset with the gains and losses of the hedge contracts. Because the impact of movements in currency exchange rates on forward contracts offsets the related impact on the underlying items being hedged, these financial instruments help alleviate the risk that might otherwise result from changes in currency exchange rates.
The Company does not use derivative financial instruments for speculative or trading purposes. In the event of termination or extinguishment of a contract, associated gains and losses would be recognized in operations in the period in which the contract was terminated or extinguished.
These contracts contain credit risk in that the counterparty may be unable to meet the terms of the agreements. The Company has limited these agreements to major financial institutions to reduce such credit risk. Furthermore, the Company monitors the potential risk of loss with any one financial institution and does not expect any material loss as a result of default by the counterparties.
Revenue Recognition. Revenue consists of fees for licenses and subscriptions of the Company' software products, sales of hardware system products, maintenance and support, customer training, and consulting. Cost of product revenue includes cost of production personnel, product packaging, documentation, amortization of capitalized software development costs and purchased technology, and costs of the Company's systems products. Cost of service revenue includes personnel and the related costs associated with providing training and consulting.
The Company recognizes revenue in accordance with SOP 97-2, Software Revenue Recognition, as amended by SOP 98-9. SOP 97-2 generally requires revenue earned on software arrangements involving multiple elements to be allocated to each element based on the relative fair values of the elements. The revenue allocated to software products, including time-based software licenses, will be recognized upon delivery of the products, ratably over the term of the license or as payments are received, depending upon the structure and terms of the arrangement. The revenue allocated to postcontract customer support (PCS) is recognized ratably over the term of the support. Revenue allocated to professional service is generally recognized as the services are performed.
In accordance with SOP 97-2, the Company has analyzed all of the elements included in its multiple-element arrangements and determined that it has sufficient evidence of fair value to allocate revenue to the license and PCS components of its product licenses. Accordingly, revenue from perpetual
licenses is recognized upon delivery and revenue from PCS, ratably. With respect to time-based licenses, except as described in the next sentence, the portion of the license fee allocated to the license component is recognized upon delivery of the software product and the portion of the fee allocated to PCS is recognized ratably over the term of the support. Software subscriptions are recognized on a ratable basis. Certain of the Company's contracts with customers, particularly TSLs entered into in the fourth quarter, included unspecified additional software products and/or payment terms that extended beyond twelve months. The Company recognizes revenue from contracts which include unspecified additional software products in an amount that is the lesser of amounts due and payable or the ratable portion of the entire fee. Revenue from contracts with extended payment terms are recognized as payments become due and payable.
Accounts receivable include amounts due from customers for which revenue has been recognized. Deferred revenue includes amounts received from customers for which revenue has not been recognized.
Property and Equipment. Property and equipment are recorded at cost. Depreciation and amortization of owned assets are provided using the straight-line method over the estimated useful lives of property and equipment of three to five years. Leasehold improvements are amortized using the straight-line method over the remaining lease term or the economic useful life of the related asset, whichever is shorter. Property and equipment detail is as follows:
Software Development Costs. Capitalization of computer software development costs begins upon the establishment of technological feasibility, which is generally the completion of a working prototype. Software development costs capitalized were $1.0 million for 2000, $1.0 million for 1999 and $2.1 million for 1998.
Amortization of computer software development costs is computed as the greater of the ratio of current product revenue to the total of current and anticipated product revenue or the straight-line method over the software's estimated economic life of approximately two years. The Company recorded amortization of $1.0 million for 2000, $1.6 million for 1999 and $2.2 million for 1998, respectively. For the one month ended October 31, 1999, software development costs and the associated amortization amount were not material.
Amortization of Intangible Assets. Amortization of intangible assets consists of goodwill and goodwill-like assets such as assembled workforce. Goodwill represents the excess of the aggregate purchase price over the fair value of the tangible and identifiable intangible assets acquired by the Company and, under the Company's accounting policies, is being amortized over estimated useful lives ranging from three to five years. The Company assesses the recoverability of goodwill by determining whether the amortized asset may be recovered through estimated future undiscounted cash flows over its useful life. A review of the intangible assets has been completed and it has been determined that the values are properly stated and no adjustments are required. Amortization of intangible assets charged to operations amounted to $15.1 million in fiscal 2000, $1.2 million for the one month ended October 31, 1999, $7.9 million in fiscal 1999 and was not material in fiscal 1998.
Accrued Liabilities. Accrued liabilities consist of:
Income Taxes. The Company accounts for income taxes using the asset and liability method. Under the asset and liability method, deferred tax assets and liabilities are recognized for the future tax consequences attributable to differences between the financial statement carrying amounts of existing assets and liabilities and their respective tax bases. Deferred tax assets are recognized for deductible temporary differences, net operating loss carryforwards, and credit carryforwards if it is more likely than not that the tax benefits will be realized. To the extent a deferred tax asset cannot be recognized under the preceding criteria, a valuation allowance has been established.
Earnings per Share. Basic earnings per share is computed using the weighted-average number of common shares outstanding during the period. Diluted earnings per share is computed using the weighted-average number of common shares and potentially dilutive common shares outstanding during the period. Potentially dilutive common shares consist of the weighted-average number of employee stock options outstanding, computed using the treasury stock method.
The following is a reconciliation of the weighted-average common shares used to calculate basic net income per share to the weighted-average common shares used to calculate diluted net income per share for fiscal 2000, 1999 and 1998 and the one-month ended October 31, 1999:
Stock-Based Compensation. As permitted under SFAS No. 123, "Accounting for Stock-Based Compensation," the Company has elected to follow Accounting Principles Board Opinion No. 25 (APB 25), "Accounting for Stock Issued to Employees," in accounting for stock-based awards to employees.
Reclassifications. Certain amounts reported in previous years have been reclassified to conform to the fiscal 2000 presentation.
NOTE 2. CHANGE IN FISCAL YEAR END
On July 15, 1999, the Board of Directors determined that Synopsys' fiscal 2000 and subsequent fiscal years shall end on the Saturday nearest to October 31. As a result, fiscal 2000 commenced on October 31, 1999 and ended on October 28, 2000. The period from October 3, 1999 through October 30, 1999 was a transition period. Total revenue and gross margin for the one-month ended October 31, 1998 were $28.2 million and $19.5 million, respectively. In addition, benefit for income taxes and net loss for the one month ended October 31, 1998 were $5.8 million and $10.3 million, respectively. For the one-month ended October 31, 1998, basic and diluted loss was $0.15 per share computed using net loss of $10.3 million and weighted-average common shares of 68.4 million. (Information related to October 1998 is unaudited).
NOTE 3. BUSINESS COMBINATIONS
Pooling-of-Interests Combinations. In fiscal 2000, the Company did not account for any business combinations using the pooling-of-interests method. In fiscal 1999, the Company issued approximately 1.4 million shares of its common stock for all the outstanding stock of Everest Design Automation, Inc. (Everest), a developer of integrated circuit routing and related technology and reserved approximately 120,000 shares of its common stock for issuance under Everest's stock option plan, which the Company assumed in the transaction. The business combination was accounted for as a pooling of interests, and accordingly, the Company's consolidated financial statements have been restated to include the financial position and results of Everest for all periods prior to the merger date. The Board of Directors approved the rescission of the Company's July 1998 stock repurchase program in order to comply with pooling-of-interests accounting guidance provided in the SEC Staff Accounting Bulletin (SAB) No. 96. In fiscal 1998, Everest issued shares of its preferred stock for $5.9 million. The Everest preferred shares are presented in the Consolidated Statements of Stockholders' Equity and Comprehensive Income in terms of equivalent shares of the Company's common stock.
In fiscal 1998, the Company issued approximately 11.3 million shares of its common stock for all of the outstanding stock of Viewlogic, a worldwide supplier of EDA software. In addition, options to acquire Viewlogic's common stock were exchanged for approximately 2.8 million shares of the Company's common stock. The business combination was accounted for as a pooling of interests, and accordingly, the Company's consolidated financial statements have been restated to include the financial position and results of Viewlogic for fiscal 1998.
During fiscal 1998, the Company sold VSI, the PCB/Systems business design segment of the Viewlogic business to a management-led buy-out group for $51.9 million in cash. As a result of the transaction, the Company recorded an extraordinary gain of $26.5 million, net of income tax expense, in the fourth quarter of fiscal 1998. The Company retained a minority investment of 14.9% (fully diluted) in the new company, Viewlogic Systems, Inc. During fiscal 2000, Viewlogic Systems, Inc. merged with Summit Design, Inc. and formed a new entity, Innoveda, Inc. The Company retains a minority equity investment in Innoveda.
The following information represents revenue and net income (loss) of the separate enterprises through the periods preceding the business combinations and the combined results following the business combinations.
(1) Includes extraordinary gains of $28.4 million, net of income tax expense, in fiscal 1998.
The Company recorded merger-related and other costs of $51.0 million in fiscal 1998. The following table presents the components of merger-related and other costs recorded in fiscal 1998, along with charges against the reserves through fiscal 2000.
Purchase Combinations. During the three fiscal years ended October 31, 2000, and September 30, 1999 and 1998, the Company made a number of purchase acquisitions. Pro forma results of operations have not been presented since the effects of the acquisitions were not material to the Company's consolidated financial position, results of operations or cash flows for the periods presented. The consolidated financial statements include the operating results of each business from the date of acquisition. The purchase price of each transaction was allocated to the acquired assets and liabilities based on their estimated fair values as of the date of the respective acquisitions.
The excess purchase price over the estimated value of the net tangible assets acquired was allocated to various intangible assets, consisting primarily of developed technology and goodwill, as well as goodwill-like assets such as assembled workforce. The values assigned to developed technologies related to each acquisition were based upon future discounted cash flows related to the existing products' projected income streams. The values of the assembled workforces were based upon the cost to replace those workforces. Amounts allocated to developed technology, workforce and goodwill are being amortized on a straight-line basis, generally over a period of three to five years.
The amounts allocated to purchased research and development were determined through established valuation techniques in the high-technology industry and were expensed upon acquisition, because technological feasibility had not been established and no future alternative uses existed. Research and development costs to bring the products from the acquired companies to technological feasibility are not expected to have a material impact on the Company's future results of operations or cash flows.
In fiscal 2000, the Company acquired VirSim, a software product, from Innoveda, Inc.; The Silicon Group, Inc. (TSG), a privately held provider of integrated circuit design and intellectual property integration services; and Leda, a privately held provider of RTL coding-style-checkers.
In fiscal 1999, the Company acquired Gambit Automated Design, Inc. (Gambit), a privately held provider of place and route software and physical design services; Stanza Systems, Inc. (Stanza), a privately held company with physical layout editor expertise and technology; Smartech OY (Smartech), a privately held design services firm with expertise in the design of wireless communication devices; and the rights to CoverMeter, a Verilog code coverage tool, from Advanced Technology Center of Massachusetts. The Company also completed the acquisition of Apteq, Inc. (Apteq), which has an expertise in analog simulation and Verilog-A product.
In fiscal 1998, the Company acquired Systems Science, Inc. (SSI), a developer of tools for electronic design verification and test, and two small privately held companies in the EDA industry. The acquisitions were accounted for as purchases with the Company exchanging a combination of cash of $26.0 million and notes of $12.0 million. In addition, the Company reserved approximately 318,000 shares of its common stock for issuance under SSI's stock option plan, which the Company assumed in the acquisition. The total purchase price of $51.3 million was allocated to the acquired assets and liabilities
based on their estimated fair values as of the date of the acquisition. Approximately $33.1 million was allocated to IPRD and other costs and charged to operations because the acquired technology had not reached technological feasibility and had no alternative uses.
A summary of the Company's purchase transactions during fiscal 2000, 1999 and 1998 that included IPRD charges, if any, is included in the following table:
NOTE 4. FINANCIAL INSTRUMENTS
Cash, Cash equivalents and investments. All cash equivalents, short-term investments, and non-current investments have been classified as available-for-sale securities and are detailed as follows:
At October 31, 2000, $153.1 million of current cash, cash equivalents and investments is classified as cash and cash equivalents and $282.5 million is classified as short-term investments. At October 31, 1999, $309.4 million and $400.0 million of current cash, cash equivalents and investments are classified as cash and cash equivalents and short-term investments. At September 30, 1999, $285.3 million and $418.9 million of current cash, cash equivalents and investments are classified as cash and cash equivalents and short-term investments, respectively. Short-term investments include tax-exempt municipal obligations which have underlying maturities of more than one year. However, such investments have put options or reset dates within one year and are either supported by a letter of credit from a top-rated bank or insurance company or are over-collateralized for redemption at par at the reset date. At October 31, 2000, the underlying maturities of the short-term investments are $65.8 million within one year, $45.5 million within five to ten years and $171.2 million after ten years. These investments are generally classified as available for sale, and are recorded on the balance sheet at fair market value with unrealized gains or losses reported as a separate component of accumulated other comprehensive income, net of tax. Realized gains and losses on sales of short-term investments have not been material.
Strategic Investments. The Company's strategic investment portfolio consists of minority equity investments in several publicly traded companies and investments in privately held companies, many of which can still be considered in the start-up or development stages. The securities of public traded companies are generally classified as available for sale and are reported at fair value, with unrealized gains or losses, net of tax, recorded in stockholders' equity. The securities of privately held companies are reported at cost. The Company utilizes forward sale contracts to reduce financial market risk and to lock in gains on publicly-traded investments which will be realized in fiscal year 2001 and beyond.
The Company entered into forward sale contracts in the fourth quarter of fiscal 2000 for the sale through November 15, 2001 of the 1,344,188 shares of Cadence stock, 114,987 shares of Broadcom stock and 687,804 shares of Nvidia stock at forward prices ranging from $20.3734 to $27.6383, $231.196 to $247.177, and $59.0188 to $80.7560, respectively.
As of October 31, 2000, the fair market value of the forward sales against cost, based on the quoted market prices of $25.6875 for Cadence shares, $227.0625 for Broadcom shares and $61.25 for Nvidia shares, have been recorded in stockholders' equity as a component of accumulated other comprehensive income.
Foreign Exchange Hedging. The Company conducts business on a global basis. Consequently, the Company enters into foreign exchange forward contracts to reduce the impact of certain currency exposures. As of October 31, 2000, the Company had $47.5 million of short-term foreign exchange forward contracts outstanding which approximated the fair value of such contracts and their underlying transactions. These contracts are denominated in the Japanese yen and the euro. The outstanding forward contracts have maturities that expire in approximately one month. The foreign currency gains and losses on forward exchange contracts and their underlying transactions resulting from market adjustments are included in earnings. Gains and losses related to these instruments at October 31, 2000 were not material. The Company does not anticipate any material adverse effect on its consolidated financial position, results of operations, or cash flows resulting from the use of these instruments.
Long-term Debt. During fiscal 2000, the Company entered into an equipment lease agreement with a total lease obligation of $0.8 million, of which approximately $0.3 million was included in long-term debt as of October 31, 2000.
During fiscal 1996, the Company and IBM entered into a six-year Joint Development and License Agreement Concerning EDA Software and Related Intellectual Property (the IBM Agreement). In accordance with the IBM Agreement, the Company paid IBM $11.0 million in cash and issued $30.0 million in notes, which bear interest at 3%, and are payable to IBM upon the earlier achievement of scheduled milestones or at maturity in fiscal 2006. During fiscal 1998, the Company recorded an extraordinary gain on extinguishment of debt of $1.9 million, net of income tax expense of $1.0 million, related to the cancellation of certain interest bearing notes issued by the Company to IBM. During fiscal
1999, the Company settled the remaining balance of the long-term debt related to the modified IBM Joint Development and License Agreement and dissolved the original agreement, which resulted in no extraordinary gain.
The fair value of the Company's long-term debt approximates the carrying amount.
NOTE 5. COMMITMENTS AND CONTINGENCIES
The Company leases its domestic and international facilities under cancelable, non-cancelable and month-to-month operating leases and certain office equipment under operating leases. Rent expense was $29.1 million, $23.5 million and $25.5 million in 2000, 1999 and 1998, respectively. For the one month ended October 31, 1999 rent expense was $1.9 million.
Future minimum lease payments as of October 31, 2000 are as follows:
NOTE 6. STOCKHOLDERS' EQUITY
Stock Repurchase Programs
On July 31, 2000, the Company announced that its Board of Directors authorized a stock repurchase program under which Synopsys common stock with a market value up to $500 million may be acquired in the open market. The stock repurchase program replaced all prior repurchase programs authorized by the Board. Under the new program, share purchases may be made in the open market at prevailing prices and ending when all available funds have been spent or upon termination of the program by the Board. Repurchased shares are to be used for issuance under Synopsys' employee stock plans and for other corporate purposes. During fiscal 2000, the Company purchased 9,931,500 shares at an average price of $40.02 per share, under all share repurchase programs.
In June 1999, the Board of Directors authorized a stock repurchase program under which Synopsys' common stock with a market value of up to $200 million may be acquired in the open market. The repurchased shares were to be used for issuance under Synopsys' employee stock plans and for other corporate purposes. During fiscal 1999, the Company purchased 1,680,000 shares at an average price of $56.76 per share. This stock repurchase program was terminated by the Board as noted in the paragraph above.
In July 1998, the Board of Directors authorized the repurchase of up to 3,250,000 shares of the Company's outstanding common stock in the open market over the following 24 months. The repurchased shares were to be used for issuance under the Company's employee stock plans and for other corporate purposes. During fiscal 1998, the Company purchased approximately 353,000 shares at an average price of $35.00 per share. In October 1998, the Company announced that it had rescinded the stock repurchase program to comply with pooling-of-interests accounting guidance provided in SAB No. 96, Treasury Stock Acquisitions Following Consummation of a Business Combination Accounted For as a Pooling of Interests (See Note 3).
Preferred Shares Rights Plan. The Company has adopted a number of provisions that could have anti-takeover effects. In September 1997, the Board of Directors adopted a Preferred Shares Rights Plan. In
addition, the Board of Directors has the authority, without further action by its shareholders, to fix the rights and preferences and issue shares of, authorized but undesignated shares of Preferred Stock. This provision and other provisions of the Company's Restated Certificate of Incorporation and Bylaws and the Delaware General Corporation Law may have the effect of deterring hostile takeovers or delaying or preventing changes in control or management of the Company, including transactions in which the shareholders of the Company might otherwise receive a premium for their shares over then current market prices. The rights expire on October 24, 2007.
Employee Stock Purchase Plan. Under the Company's 1992 Employee Stock Purchase Plan (ESPP) 5,850,000 shares have been authorized for issuance as of October 31, 2000. Under the ESPP, employees are granted the right to purchase shares of common stock at a price per share that is 85% of the lesser of: the fair market value of the shares at (i) the beginning of a rolling two-year offering period, or (ii) the end of each semi-annual purchase period. During fiscal 2000, the one-month ended October 31, 1999, fiscal 1999 and 1998 shares totaling 512,988, 225,347, 460,438, and 433,036, respectively, were issued under the plan at average prices of $32.63, $39.30, $31.73, and $27.61 per share, respectively. As of October 31, 2000, 2,880,648 shares of common stock were reserved for issuance under the ESPP.
Stock Option Plans. Under the Company's 1992 Stock Option Plan (the 1992 Plan), the Board of Directors may grant either incentive or non-qualified stock options to purchase shares of the Company's stock to eligible individuals at not less than 100% of the fair market value of those shares on the grant date. The stock options issued to new employees typically vest 25% after one year with the remaining options vesting on a pro rata basis over the following 36 months, while stock options issued to existing employees typically vest on a pro rata basis over 48 months. Stock options expire ten years from the date of grant. As of October 31, 2000, 2,034,119 shares of common stock are reserved for future grants.
Under the Company's Non-Statutory Stock Option Plan (the 1998 Plan), 17,242,534 shares of common stock have been reserved for issuance. Pursuant to the 1998 Plan, the Board of Directors may grant non-qualified stock options to employees, excluding executive officers. Exercisibility, option price and other terms are determined by the Board of Directors, but the option price shall not be less than 100% of the fair market value of the stock at the grant date. The stock options issued to new employees typically vest 25% after one year with the remaining options vesting on a pro rata basis over the following 36 months, while stock options issued to existing employees typically vest on a pro rata basis over 48 months. At October 31, 2000, 1,034,956 shares of common stock were reserved for future grants.
Under the Company's 1994 Non-Employee Directors Stock Option Plan (the Directors Plan), a total of 450,000 shares have been reserved for issuance. Pursuant to the Directors Plan, each non-employee member of the Board of Directors is automatically granted an option to purchase 20,000 shares of the Company's common stock upon initial appointment or election to the Board, 10,000 shares of the Company's common stock upon reelection to the Board, and 5,000 shares of the Company's common stock annually for service on Board committees, subject to a limit of two committee-service grants per year. Stock options are granted at not less than 100% of the fair market value of those shares on the grant date. Stock options granted upon appointment or election to the Board vest 25% annually on the day before each of the first four Annual Meetings following the initial appointment or election to the Board. Stock options granted upon reelection to the Board and committee-service grants vest 100% after the first year of continuous service. As of October 31, 2000, 45,585 shares of common stock were reserved for future grants.
The Company has assumed certain option plans in connection with business combinations (See Note 3). Generally, these options were granted under terms similar to the terms of the Company's stock option plans at prices adjusted to reflect the relative exchange ratios. All assumed plans were terminated as to future grants upon completion of each of the business combinations.
Additional information concerning stock option activity under the various plans is as follows:
The following table summarizes information about stock options outstanding at October 31, 2000:
Stock-Based Compensation. Under APB 25, the Company generally recognizes no compensation expense with respect to stock-based awards to employees. Pro forma information regarding net income and net income per share is required by SFAS No. 123 for awards granted after September 30, 1995, as if the
Company had accounted for its stock-based awards to employees under the fair value method of SFAS No. 123. The weighted-average estimated fair value of stock options issued during fiscal 2000, 1999 and 1998 was $15.96, $22.88 and $20.32 per share, respectively. The weighted-average estimated fair value of shares granted under the ESPP during fiscal 2000, 1999 and 1998 was $14.32, $13.76 and $11.70 per share, respectively. The fair value of the Company's stock-based awards to employees was estimated using the Black-Scholes option pricing model. The fair value of the Company's stock-based awards to employees was estimated assuming no expected dividends and the following weighted-average assumptions, for fiscal 2000, 1999 and 1998:
For pro forma purposes, the estimated fair value of the Company's stock-based awards to employees is generally amortized over the options' vesting period of four years (for options) and the six-month purchase period (for stock purchases under the ESPP). The Company's pro forma net income and earnings per share data, under SFAS No. 123 is as follows:
NOTE 7. INCOME TAXES
The Company is entitled to a deduction for federal and state tax purposes with respect to employees' stock option activity. The net reduction in taxes otherwise payable arising from that deduction has been credited to additional paid-in capital.
The components of the Company's total income before provision for income taxes are as follows:
The components of the provision for income taxes are as follows:
The provision for income taxes differs from the amount obtained by applying the statutory federal income tax rate to income (loss) before income taxes as follows:
A net deferred tax asset of $85.8 million, $48.1 million, and $35.6 million is primarily included in prepaid expenses, deferred taxes, and other at October 31, 2000 and 1999 and September 30, 1999, respectively. The tax effects of temporary differences and carryforwards, which give rise to significant portions of the deferred tax assets and liabilities, are as follows:
At October 31, 2000, the Company believes that it is more likely than not that the results of future operations will generate sufficient taxable income to realize the deferred tax assets.
The Company's United States income tax returns for fiscal years ended September 30, 1996 and September 30, 1995 are under examination and the Internal Revenue Service has proposed certain adjustments. Management believes that adequate amounts have been provided for any adjustments that may ultimately result from these examinations.
NOTE 8. SEGMENT DISCLOSURE
SFAS No. 131, Disclosures about Segments of an Enterprise and Related Information, requires disclosures of certain information regarding operating segments, products and services, geographic areas of operation and major customers. The method for determining what information to report under SFAS No. 131 is based upon the "management approach," or the way that management organizes the operating segments within a company, for which separate financial information is available that is evaluated regularly
by the Chief Operating Decision Maker (CODM) in deciding how to allocate resources and in assessing performance. Synopsys' CODM is the Chief Executive Officer and Chief Operating Officer.
The Company provides comprehensive design technology products and consulting services in the electronic design automation software industry. The CODM evaluates the performance of the Company based on profit or loss from operations before income taxes not including merger-related costs, in-process research and development and amortization of intangible assets. For the purpose of making operating decisions, the CODM primarily considers financial information presented on a consolidated basis accompanied by disaggregated information about revenues by geographic region. There are no differences between the accounting policies used to measure profit and loss for the Company segment and those used on a consolidated basis. Revenue is defined as revenues from external customers.
The disaggregated financial information reviewed by the CODM is as follows:
The CODM did not review disaggregated financial information for the one-month ended October 31, 1999.
Reconciliation of the Company's segment profit and loss to the Company's income before provision for income taxes is as follows:
Revenue and long-lived assets related to operations in United States and other geographic areas are as follows:
Transfers between geographic areas represent both intercompany product and service revenue accounted for at prices representative of unaffiliated party transactions and export shipments directly to customers. No one customer accounted for more than ten percent of the Company's consolidated revenue in fiscal 2000, 1999 and 1998 and the one month ended October 31, 1999.
Geographic revenue data for multi-region, multi-product transactions reflects internal allocations and is therefore subject to certain assumptions and the Company's methodology. Revenue is not reallocated among geographic regions to reflect any re-mixing of licenses between different regions following the initial product shipment.
During the fourth quarter of fiscal 2000, the Company began segregating revenue into five categories for purposes of internal management reporting: IC Implementation, including both the Design Compiler (DC) Family and Physical Synthesis; Verification and Test; Intellectual Property (IP) and System Level Design; Transistor Level Design (TLD); and Professional Services. Revenues for each of the sectors for the fiscal years 2000, 1999 and 1998 are as follows:
NOTE 9. SELECTED QUARTERLY DATA (UNAUDITED)
(1) Includes $56,456 in revenue from Viewlogic's systems & PCB design business. The segment was sold to a management-led buy-out group during fiscal 1998.
(2) The Company's common stock is traded on The Nasdaq Stock Market under the symbol "SNPS." The stock prices shown represent quotations among dealers without adjustments for retail markups, markdowns or commissions and may not represent actual transactions. As of October 31, 2000, there were approximately 680 shareholders of record. To date, the Company has paid no cash dividends on its capital stock, and has no current intention to do so.
NOTE 10. SUBSEQUENT EVENT
On January 4, 2001, the Company sold the assets of the Company's Silicon Liabraries business and licenses to Artisan Components, Inc. (Artisan), for approximately $24.6 million in cash and common stock. In addition, the Company has subcontracted certain performance obligations under existing contracts to Artisan. The Company is in the process of determining any losses related to the subcontractor agreement. Direct revenue for this product line was $4.3 million, $10.1 million and $13.8 million in fiscal 2000, 1999 and 1998, respectively.
ITEM 9.
ITEM 9. CHANGES IN AND DISAGREEMENTS WITH ACCOUNTANTS ON ACCOUNTING AND FINANCIAL DISCLOSURE
Not applicable.
PART III
ITEM 10.
ITEM 10. DIRECTORS AND EXECUTIVE OFFICERS OF THE REGISTRANT
Information with respect to Directors is included under the caption "Proposal One -- Election of Directors" in Synopsys' Notice of Annual Meeting and Proxy Statement for Synopsys' annual meeting of stockholders to be held on April 6, 2001 (the "Proxy Statement") and is incorporated herein by reference. Information with respect to Executive Officers is included under the heading "Executive Officers of the Company" in Part I hereof after Item 4.
Information regarding delinquent filers pursuant to Item 405 of Regulation S-K is included under the heading "Section 16(a) Beneficial Ownership Reporting Compliance" under the caption "Additional Information" in the Proxy Statement and is incorporated herein by reference.
ITEM 11.
ITEM 11. EXECUTIVE COMPENSATION
The information required by this item is included under the heading "Executive Compensation" under the caption "Proposal One -- Election of Directors" in the Proxy Statement and is incorporated herein by reference.
ITEM 12.
ITEM 12. SECURITY OWNERSHIP OF CERTAIN BENEFICIAL OWNERS AND MANAGEMENT
The information required by this item is included under the heading "Security Ownership of Certain Beneficial Owners and Management" under the caption "Proposal One -- Election of Directors" in the Proxy Statement and is incorporated herein by reference.
ITEM 13.
ITEM 13. CERTAIN RELATIONSHIPS AND RELATED TRANSACTIONS
The information required by this item is included under the caption "Proposal One -- Election of Directors" in the Proxy Statement and is incorporated herein by reference.
PART IV
ITEM 14.
ITEM 14. EXHIBITS, FINANCIAL STATEMENTS, SCHEDULES AND REPORTS ON FORM 8-K
(a) The following documents are filed as part of this Annual Report on Form 10-K:
1. FINANCIAL STATEMENTS
The following documents are included as Part II, Item 8, of this Annual Report on Form 10-K:
2. FINANCIAL STATEMENT SCHEDULE
The following schedule of the Company is included herein:
Valuation and Qualifying Accounts and Reserves (Schedule II)
All other schedules are omitted because they are not applicable or the amounts are immaterial or the required information is presented in the consolidated financial statements or notes thereto.
The following documents are included in Exhibit 23 hereto:
Exhibit 23.1 Report on Financial Statement Schedule of Synopsys, Inc. Exhibit 23.2 Consent of KPMG LLP, Independent Auditors
3. EXHIBITS
See Item 14(c) below.
(b) Reports on Form 8-K
None.
(c) Exhibits
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(1) Incorporated by reference to Annex A to the form of prospectus contained in the Registration Statement on Form S-4 (File No. 333-39713) of Synopsys, Inc. as filed with the Securities and Exchange Commission on November 7, 1997
(2) Incorporated by reference from exhibit to the Company's Quarterly Report on Form 10-Q for the quarterly period ended April 3, 1999
(3) Incorporated by reference from exhibit to Amendment No. 1 to the Company's Registration Statement on Form 8-A as filed with the Securities and Exchange Commission on December 13, 1999
(4) Incorporated by reference from exhibit of the same number filed with the Company's Registration Statement on Form S-1 (File No. 33-45138) which became effective February 24, 1992
(5) Incorporated by reference from exhibit of the same number filed with the Company's Annual Report on Form 10-K for the fiscal year ended September 30,
(6) Incorporated by reference from exhibit of the same number filed with the Company's Annual Report on Form 10-K for the fiscal year ended September 30,
(7) Incorporated by reference from exhibit of the same number filed with the Company's Annual Report on Form 10-K for the fiscal year ended September 30,
(8) Incorporated by reference from exhibit of the same number filed with the Company's Quarterly Report on Form 10-Q for the quarterly period ended December 31, 1995
(9) Incorporated by reference from exhibit of the same number filed with the Company's Quarterly Report on Form 10-Q for the quarterly period ended March 31,
(10) Incorporated by reference from exhibit to the Company's Quarterly Report on Form 10-Q for the quarterly period ended April 30, 2000, as filed with the Securities and Exchange Commission on June 13, 2000
(11) Compensatory plan or agreement in which an executive officer participates
(12) Incorporated by reference from exhibit to the Company's Registration Statement on Form S-8 (file no. 333-38810), as filed with the Securities and Exchange Commission on June 8, 2000
(13) Incorporated by reference from exhibit to the Registration Statement on Form S-4 (File No. 333-21129) of Synopsys, Inc. as filed with the Securities and Exchange Commission on February 5, 1997
(14) Incorporated by reference from exhibit to the Company's Registration Statement on Form S-8 (file No. 333-77597), as filed with the Securities and Exchange Commission on May 3, 1999
(15) Incorporated by reference from exhibit to the Company's Quarterly Report on Form 10-Q for the quarterly period ended January 3, 1998
(16) Incorporated by reference to exhibit to the Company's Registration Statement on Form S-8 (File No. 333-90643) as filed with the Securities and Exchange Commission on November 9, 1999
SIGNATURES
Pursuant to the requirements of section 13 or 15(d) of the Securities Exchange Act of 1934, the registrant has duly caused this report to be signed on its behalf by the undersigned, thereunto duly authorized, in Mountain View, State of California, on this day of January 16, 2001.
SYNOPSYS, INC.
By /s/ AART J. DE GEUS ------------------------------------------------ Aart J. de Geus Chief Executive Officer and Chairman of the Board of Directors (Principal Executive Officer)
By /s/ ROBERT B. HENSKE ------------------------------------------------ Robert B. Henske Senior Vice President, Finance and Operations, and Chief Financial Officer (Principal Financial Officer)
By /s/ RICHARD T. ROWLEY ------------------------------------------------ Richard T. Rowley Vice President, Corporate Controller (Principal Accounting Officer)
POWER OF ATTORNEY
KNOW ALL PERSONS BY THESE PRESENTS, that each person whose signature appears below constitutes and appoints Aart J. de Geus and Robert B. Henske, and each of them, as his true and lawful attorneys-in-fact and agents, with full power of substitution and resubstitution, for him and in his name, place and stead, in any and all capacities, to sign any and all amendments (including post-effective amendments) to this Report on Form 10-K, and to file the same, with all exhibits thereto, and other documents in connection therewith, with the Securities and Exchange Commission, granting unto said attorneys-in-fact and agents, and each of them, full power and authority to do and perform each and every act and thing requisite and necessary to be done in connection therewith, as fully to all intents and purposes as he might or could do in person, hereby ratifying and confirming all that said attorneys-in-fact and agents, or any of them, or their or his substitute or substitutes, may lawfully do or cause to be done by virtue hereof. Pursuant to the requirements of the Securities Exchange Act of 1934, this report has been signed below by the following persons on behalf of the registrant and in the capacities and on the dates indicated:
SCHEDULE II
SYNOPSYS, INC. --------------------
VALUATION AND QUALIFYING ACCOUNTS AND RESERVES (in thousands)
(1) Fiscal 1998 includes a $2,049 reduction due to the sale of Viewlogic Systems, Inc. Other amounts are translation and other adjustments.
(2) Accounts written off, net of recoveries.
EXHIBIT INDEX
- ----------
(1) Incorporated by reference to Annex A to the form of prospectus contained in the Registration Statement on Form S-4 (File No. 333-39713) of Synopsys, Inc. as filed with the Securities and Exchange Commission on November 7, 1997
(2) Incorporated by reference from exhibit to the Company's Quarterly Report on Form 10-Q for the quarterly period ended April 3, 1999
(3) Incorporated by reference from exhibit to Amendment No. 1 to the Company's Registration Statement on Form 8-A as filed with the Securities and Exchange Commission on December 13, 1999
(4) Incorporated by reference from exhibit of the same number filed with the Company's Registration Statement on Form S-1 (File No. 33-45138) which became effective February 24, 1992
(5) Incorporated by reference from exhibit of the same number filed with the Company's Annual Report on Form 10-K for the fiscal year ended September 30,
(6) Incorporated by reference from exhibit of the same number filed with the Company's Annual Report on Form 10-K for the fiscal year ended September 30,
(7) Incorporated by reference from exhibit of the same number filed with the Company's Annual Report on Form 10-K for the fiscal year ended September 30,
(8) Incorporated by reference from exhibit of the same number filed with the Company's Quarterly Report on Form 10-Q for the quarterly period ended December 31, 1995
(9) Incorporated by reference from exhibit of the same number filed with the Company's Quarterly Report on Form 10-Q for the quarterly period ended March 31,
(10) Incorporated by reference from exhibit to the Company's Quarterly Report on Form 10-Q for the quarterly period ended April 30, 2000, as filed with the Securities and Exchange Commission on June 13, 2000
(11) Compensatory plan or agreement in which an executive officer participates
(12) Incorporated by reference from exhibit to the Company's Registration Statement on Form S-8 (file no. 333-38810), as filed with the Securities and Exchange Commission on June 8, 2000
(13) Incorporated by reference from exhibit to the Registration Statement on Form S-4 (File No. 333-21129) of Synopsys, Inc. as filed with the Securities and Exchange Commission on February 5, 1997
(14) Incorporated by reference from exhibit to the Company's Registration Statement on Form S-8 (file No. 333-77597), as filed with the Securities and Exchange Commission on May 3, 1999
(15) Incorporated by reference from exhibit to the Company's Quarterly Report on Form 10-Q for the quarterly period ended January 3, 1998
(16) Incorporated by reference to exhibit to the Company's Registration Statement on Form S-8 (File No. 333-90643) as filed with the Securities and Exchange Commission on November 9, 1999