def validate_ports(self):
    sources = ''
    for source_file in self.config['source']:
        sources += os.path.join(self.directory, source_file)
        sources += ' '
    top = self.config['caravel_test']['module_name']
    json_file = '/tmp/ports.json'
    os.system(("yosys -qp 'read_verilog -sv %s; hierarchy -top %s ; proc; json -o %s x:*' -DUSE_POWER_PINS=1 -DMPRJ_IO_PADS=38" % (sources, top, json_file)))
    with open(json_file) as fh:
        ports = json.load(fh)
    module_ports = ports['modules'][self.config['caravel_test']['module_name']]['ports']
    for (port_type, port_def) in self.system_config['interfaces']['required'].items():
        for (port_name, bits) in port_def.items():
            if (port_name not in module_ports):
                logging.error(('required port %s not in interface' % port_name))
                exit(1)
            if (len(module_ports[port_name]['bits']) != bits):
                logging.error(('required port %s is wrong size' % port_name))
                exit(1)
            del module_ports[port_name]
    for optional_port in self.config['interfaces']:
        for (port_name, bits) in self.system_config['interfaces']['optional'][optional_port].items():
            if (port_name not in module_ports):
                logging.error(('optional port %s was set but %s is not in interface' % (optional_port, port_name)))
                exit(1)
            if (len(module_ports[port_name]['bits']) != bits):
                logging.error(('optional port %s is wrong size' % port_name))
                exit(1)
            del module_ports[port_name]
    if (len(module_ports) != 0):
        logging.error('additional interfaces found in module')
        logging.error(module_ports)
        exit(1)
    logging.info('test ports pass')
def validate_ports(self):
    sources = 
    for source_file in self.config['source']:
        sources += os.path.join(self.directory, source_file)
        sources += ' '
    top = self.config['caravel_test']['module_name']
    json_file = '/tmp/ports.json'
    os.system(("yosys -qp 'read_verilog -sv %s; hierarchy -top %s ; proc; json -o %s x:*' -DUSE_POWER_PINS=1 -DMPRJ_IO_PADS=38" % (sources, top, json_file)))
    with open(json_file) as fh:
        ports = json.load(fh)
    module_ports = ports['modules'][self.config['caravel_test']['module_name']]['ports']
    for (port_type, port_def) in self.system_config['interfaces']['required'].items():
        for (port_name, bits) in port_def.items():
            if (port_name not in module_ports):
                logging.error(('required port %s not in interface' % port_name))
                exit(1)
            if (len(module_ports[port_name]['bits']) != bits):
                logging.error(('required port %s is wrong size' % port_name))
                exit(1)
            del module_ports[port_name]
    for optional_port in self.config['interfaces']:
        for (port_name, bits) in self.system_config['interfaces']['optional'][optional_port].items():
            if (port_name not in module_ports):
                logging.error(('optional port %s was set but %s is not in interface' % (optional_port, port_name)))
                exit(1)
            if (len(module_ports[port_name]['bits']) != bits):
                logging.error(('optional port %s is wrong size' % port_name))
                exit(1)
            del module_ports[port_name]
    if (len(module_ports) != 0):
        logging.error('additional interfaces found in module')
        logging.error(module_ports)
        exit(1)
    logging.info('test ports pass')