def __init__(self, platform, *args, **kwargs):
    kwargs['cpu_type'] = None
    BaseSoC.__init__(self, platform, *args, with_uart=False, **kwargs)
    self.add_cpu_or_bridge(UARTWishboneBridge(platform.request('serial'), self.clk_freq, baudrate=19200))
    self.add_wb_master(self.cpu_or_bridge.wishbone)
    self.submodules.io = LiteScopeIO(8)
    for i in range(8):
        try:
            self.comb += platform.request('user_led', i).eq(self.io.output[i])
        except:
            pass
    analyzer_signals = [self.spiflash.bus]
    self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 1024)
def __init__(self, platform, *args, **kwargs):
    kwargs['cpu_type'] = None
    BaseSoC.__init__(self, platform, *args, with_uart=False, **kwargs)
    self.add_cpu_or_bridge(UARTWishboneBridge(platform.request('serial'), self.clk_freq, baudrate=19200))
    self.add_wb_master(self.cpu_or_bridge.wishbone)
    self.submodules.io = LiteScopeIO(8)
    for i in range(8):
        try:
            self.comb += platform.request('user_led', i).eq(self.io.output[i])
        except:
            pass
    analyzer_signals = [self.spiflash.bus]
    self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 1024)