def __init__(self, platform, sys_clk_freq):
    self.rst = Signal()
    self.clock_domains.cd_init = ClockDomain()
    self.clock_domains.cd_por = ClockDomain(reset_less=True)
    self.clock_domains.cd_sys = ClockDomain()
    self.clock_domains.cd_sys2x = ClockDomain()
    self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
    self.stop = Signal()
    self.reset = Signal()
    clk30 = platform.request('clk30')
    rst_n = platform.request('user_btn', 0)
    por_count = Signal(16, reset=((2 ** 16) - 1))
    por_done = Signal()
    self.comb += self.cd_por.clk.eq(clk30)
    self.comb += por_done.eq((por_count == 0))
    self.sync.por += If((~ por_done), por_count.eq((por_count - 1)))
    self.submodules.pll = pll = ECP5PLL()
    self.comb += pll.reset.eq((((~ por_done) | (~ rst_n)) | self.rst))
    pll.register_clkin(clk30, 30000000.0)
    pll.create_clkout(self.cd_sys2x_i, (2 * sys_clk_freq))
    pll.create_clkout(self.cd_init, 25000000.0)
    self.specials += [Instance('ECLKSYNCB', i_ECLKI=self.cd_sys2x_i.clk, i_STOP=self.stop, o_ECLKO=self.cd_sys2x.clk), Instance('CLKDIVF', p_DIV='2.0', i_ALIGNWD=0, i_CLKI=self.cd_sys2x.clk, i_RST=self.reset, o_CDIVX=self.cd_sys.clk), AsyncResetSynchronizer(self.cd_sys, ((~ pll.locked) | self.reset)), AsyncResetSynchronizer(self.cd_sys2x, ((~ pll.locked) | self.reset))]
def __init__(self, platform, sys_clk_freq):
    self.rst = Signal()
    self.clock_domains.cd_init = ClockDomain()
    self.clock_domains.cd_por = ClockDomain(reset_less=True)
    self.clock_domains.cd_sys = ClockDomain()
    self.clock_domains.cd_sys2x = ClockDomain()
    self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
    self.stop = Signal()
    self.reset = Signal()
    clk30 = platform.request('clk30')
    rst_n = platform.request('user_btn', 0)
    por_count = Signal(16, reset=((2 ** 16) - 1))
    por_done = Signal()
    self.comb += self.cd_por.clk.eq(clk30)
    self.comb += por_done.eq((por_count == 0))
    self.sync.por += If((~ por_done), por_count.eq((por_count - 1)))
    self.submodules.pll = pll = ECP5PLL()
    self.comb += pll.reset.eq((((~ por_done) | (~ rst_n)) | self.rst))
    pll.register_clkin(clk30, 30000000.0)
    pll.create_clkout(self.cd_sys2x_i, (2 * sys_clk_freq))
    pll.create_clkout(self.cd_init, 25000000.0)
    self.specials += [Instance('ECLKSYNCB', i_ECLKI=self.cd_sys2x_i.clk, i_STOP=self.stop, o_ECLKO=self.cd_sys2x.clk), Instance('CLKDIVF', p_DIV='2.0', i_ALIGNWD=0, i_CLKI=self.cd_sys2x.clk, i_RST=self.reset, o_CDIVX=self.cd_sys.clk), AsyncResetSynchronizer(self.cd_sys, ((~ pll.locked) | self.reset)), AsyncResetSynchronizer(self.cd_sys2x, ((~ pll.locked) | self.reset))]