@core.cache_frame_data(type=core.G3FrameType.Housekeeping, wiring_map='WiringMap', tf='DfMuxTransferFunction', system='ReadoutSystem')
def AddVbiasAndCurrentConv(frame, wiring_map):
    hk_map = frame['DfMuxHousekeeping']
    v_bias = core.G3MapDouble()
    i_conv = core.G3MapDouble()
    for k in wiring_map.keys():
        vb = (dfmux.unittransforms.bolo_bias_voltage_rms(wiring_map, hk_map, bolo=k, tf=tf, system=system) / core.G3Units.V)
        ic = (dfmux.unittransforms.counts_to_rms_amps(wiring_map, hk_map, bolo=k, tf=tf, system=system) / core.G3Units.amp)
        v_bias[k] = vb
        i_conv[k] = ic
    frame['VoltageBias'] = v_bias
    frame['CurrentConv'] = i_conv
@core.cache_frame_data(type=core.G3FrameType.Housekeeping, wiring_map='WiringMap', tf='DfMuxTransferFunction', system='ReadoutSystem')
def AddVbiasAndCurrentConv(frame, wiring_map):
    hk_map = frame['DfMuxHousekeeping']
    v_bias = core.G3MapDouble()
    i_conv = core.G3MapDouble()
    for k in wiring_map.keys():
        vb = (dfmux.unittransforms.bolo_bias_voltage_rms(wiring_map, hk_map, bolo=k, tf=tf, system=system) / core.G3Units.V)
        ic = (dfmux.unittransforms.counts_to_rms_amps(wiring_map, hk_map, bolo=k, tf=tf, system=system) / core.G3Units.amp)
        v_bias[k] = vb
        i_conv[k] = ic
    frame['VoltageBias'] = v_bias
    frame['CurrentConv'] = i_conv