def __init__(self, dram_port, *, size, data_width, granularity=None, dirty_init=False):
    if (not isinstance(dram_port, litedram.NativePort)):
        raise TypeError('DRAM port must be an instance of lambdasoc.cores.litedram.NativePort, not {!r}'.format(dram_port))
    if ((not isinstance(size, int)) or (size <= 0) or (size & (size - 1))):
        raise ValueError('Cache size must be a positive power of two integer, not {!r}'.format(size))
    if ((not isinstance(data_width, int)) or (data_width <= 0) or (data_width & (data_width - 1))):
        raise ValueError('Data width must be a positive power of two integer, not {!r}'.format(data_width))
    if ((dram_port.data_width % data_width) != 0):
        raise ValueError('DRAM port data width must be a multiple of data width, but {} is not a multiple of {}'.format(dram_port.data_width, data_width))
    self.intr_bus = wishbone.Interface(addr_width=(dram_port.addr_width + log2_int((dram_port.data_width // data_width))), data_width=data_width, granularity=granularity, features={'cti', 'bte'})
    intr_map = MemoryMap(addr_width=(self.intr_bus.addr_width + log2_int((data_width // granularity))), data_width=granularity)
    try:
        intr_map.add_window(dram_port.memory_map)
    except AttributeError:
        pass
    self.intr_bus.memory_map = intr_map
    self.dram_port = dram_port
    self.size = size
    self.dirty_init = bool(dirty_init)
def __init__(self, dram_port, *, size, data_width, granularity=None, dirty_init=False):
    if (not isinstance(dram_port, litedram.NativePort)):
        raise TypeError('DRAM port must be an instance of lambdasoc.cores.litedram.NativePort, not {!r}'.format(dram_port))
    if ((not isinstance(size, int)) or (size <= 0) or (size & (size - 1))):
        raise ValueError('Cache size must be a positive power of two integer, not {!r}'.format(size))
    if ((not isinstance(data_width, int)) or (data_width <= 0) or (data_width & (data_width - 1))):
        raise ValueError('Data width must be a positive power of two integer, not {!r}'.format(data_width))
    if ((dram_port.data_width % data_width) != 0):
        raise ValueError('DRAM port data width must be a multiple of data width, but {} is not a multiple of {}'.format(dram_port.data_width, data_width))
    self.intr_bus = wishbone.Interface(addr_width=(dram_port.addr_width + log2_int((dram_port.data_width // data_width))), data_width=data_width, granularity=granularity, features={'cti', 'bte'})
    intr_map = MemoryMap(addr_width=(self.intr_bus.addr_width + log2_int((data_width // granularity))), data_width=granularity)
    try:
        intr_map.add_window(dram_port.memory_map)
    except AttributeError:
        pass
    self.intr_bus.memory_map = intr_map
    self.dram_port = dram_port
    self.size = size
    self.dirty_init = bool(dirty_init)