def test_nested():

    def hierIO():

        class dictIO(Product):
            baseIO = make_baseIO()
            ctr = m.In(m.Bit)
        return dictIO

    def DefineCtrModule():

        class ctrModule(m.Circuit):
            name = 'ctr_module'
            io = m.IO(ctr=m.In(m.Bit))
        return ctrModule

    def make_baseIO():

        class dictIO(Product):
            in0 = (m.In(m.Bit),)
            out0 = m.Out(m.Bit)
        return dictIO

    def DefineBaseModule():

        class baseModule(m.Circuit):
            name = 'base_module'
            io = m.IO(baseIO=make_baseIO())
        return baseModule

    def DefineHier():

        class HierModule(m.Circuit):
            name = 'hier_module'
            io = m.IO(hier=hierIO())
            baseM = DefineBaseModule()()
            ctrM = DefineCtrModule()()
            m.wire(baseM.baseIO, io.hier.baseIO)
            m.wire(ctrM.ctr, io.hier.ctr)
        return HierModule
    baseMH = DefineHier()
    m.compile('build/baseMH', baseMH, output='coreir-verilog')
def test_nested():

    def hierIO():

        class dictIO(Product):
            baseIO = make_baseIO()
            ctr = m.In(m.Bit)
        return dictIO

    def DefineCtrModule():

        class ctrModule(m.Circuit):
            name = 'ctr_module'
            io = m.IO(ctr=m.In(m.Bit))
        return ctrModule

    def make_baseIO():

        class dictIO(Product):
            in0 = (m.In(m.Bit),)
            out0 = m.Out(m.Bit)
        return dictIO

    def DefineBaseModule():

        class baseModule(m.Circuit):
            name = 'base_module'
            io = m.IO(baseIO=make_baseIO())
        return baseModule

    def DefineHier():

        class HierModule(m.Circuit):
            name = 'hier_module'
            io = m.IO(hier=hierIO())
            baseM = DefineBaseModule()()
            ctrM = DefineCtrModule()()
            m.wire(baseM.baseIO, io.hier.baseIO)
            m.wire(ctrM.ctr, io.hier.ctr)
        return HierModule
    baseMH = DefineHier()
    m.compile('build/baseMH', baseMH, output='coreir-verilog')